py/emitnative: Fix x86-64 emitter to generate correct 8/16-bit stores.

Fixes issue #6643.

Signed-off-by: Damien George <damien@micropython.org>

py/emitnative.c

@@ -1769,7 +1769,7 @@ STATIC void emit_native_store_subscr(emit_t *emit) {
             int reg_index = REG_ARG_2;
             int reg_value = REG_ARG_3;
             emit_pre_pop_reg_flexible(emit, &vtype_base, &reg_base, reg_index, reg_value);
-            #if N_X86
+            #if N_X64 || N_X86
             // special case: x86 needs byte stores to be from lower 4 regs (REG_ARG_3 is EDX)
             emit_pre_pop_reg(emit, &vtype_value, reg_value);
             #else
@@ -1856,7 +1856,7 @@ STATIC void emit_native_store_subscr(emit_t *emit) {
                 EMIT_NATIVE_VIPER_TYPE_ERROR(emit,
                     MP_ERROR_TEXT("can't store with '%q' index"), vtype_to_qstr(vtype_index));
             }
-            #if N_X86
+            #if N_X64 || N_X86
             // special case: x86 needs byte stores to be from lower 4 regs (REG_ARG_3 is EDX)
             emit_pre_pop_reg(emit, &vtype_value, reg_value);
             #else

tests/micropython/viper_misc2.py

@@ -0,0 +1,21 @@
+# Miscellaneous viper tests
+
+# Test correct use of registers in load and store
+@micropython.viper
+def expand(dest: ptr8, source: ptr8, length: int):
+    n = 0
+    for x in range(0, length, 2):
+        c = source[x]
+        d = source[x + 1]
+        dest[n] = (c & 0xE0) | ((c & 0x1C) >> 1)
+        n += 1
+        dest[n] = ((c & 3) << 6) | ((d & 0xE0) >> 4)
+        n += 1
+        dest[n] = ((d & 0x1C) << 3) | ((d & 3) << 2)
+        n += 1
+
+
+source = b"\xaa\xaa\xff\xff"
+dest = bytearray(len(source) // 2 * 3)
+expand(dest, source, len(source))
+print(dest)

tests/micropython/viper_misc2.py.exp

@@ -0,0 +1 @@
+bytearray(b'\xa4\x8aH\xee\xce\xec')