py/emitnative: Fix x86-64 emitter to generate correct 8/16-bit stores.
Fixes issue #6643. Signed-off-by: Damien George <damien@micropython.org>
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@ -1769,7 +1769,7 @@ STATIC void emit_native_store_subscr(emit_t *emit) {
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int reg_index = REG_ARG_2;
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int reg_value = REG_ARG_3;
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emit_pre_pop_reg_flexible(emit, &vtype_base, ®_base, reg_index, reg_value);
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#if N_X86
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#if N_X64 || N_X86
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// special case: x86 needs byte stores to be from lower 4 regs (REG_ARG_3 is EDX)
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emit_pre_pop_reg(emit, &vtype_value, reg_value);
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#else
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@ -1856,7 +1856,7 @@ STATIC void emit_native_store_subscr(emit_t *emit) {
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EMIT_NATIVE_VIPER_TYPE_ERROR(emit,
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MP_ERROR_TEXT("can't store with '%q' index"), vtype_to_qstr(vtype_index));
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}
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#if N_X86
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#if N_X64 || N_X86
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// special case: x86 needs byte stores to be from lower 4 regs (REG_ARG_3 is EDX)
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emit_pre_pop_reg(emit, &vtype_value, reg_value);
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#else
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21
tests/micropython/viper_misc2.py
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21
tests/micropython/viper_misc2.py
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@ -0,0 +1,21 @@
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# Miscellaneous viper tests
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# Test correct use of registers in load and store
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@micropython.viper
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def expand(dest: ptr8, source: ptr8, length: int):
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n = 0
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for x in range(0, length, 2):
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c = source[x]
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d = source[x + 1]
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dest[n] = (c & 0xE0) | ((c & 0x1C) >> 1)
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n += 1
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dest[n] = ((c & 3) << 6) | ((d & 0xE0) >> 4)
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n += 1
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dest[n] = ((d & 0x1C) << 3) | ((d & 3) << 2)
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n += 1
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source = b"\xaa\xaa\xff\xff"
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dest = bytearray(len(source) // 2 * 3)
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expand(dest, source, len(source))
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print(dest)
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1
tests/micropython/viper_misc2.py.exp
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1
tests/micropython/viper_misc2.py.exp
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@ -0,0 +1 @@
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bytearray(b'\xa4\x8aH\xee\xce\xec')
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