mimxrt/sdio: Add support for the 117x series.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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@ -38,8 +38,14 @@
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#if MICROPY_HW_SDIO_SDMMC == 1
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#define SDMMC USDHC1
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#define SDMMC_IRQn USDHC1_IRQn
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#ifdef MIMXRT117x_SERIES
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#define SDMMC_CLOCK_MUX kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2
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#define SDMMC_CLOCK_ROOT kCLOCK_Root_Usdhc1
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#else
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#define SDMMC_CLOCK_DIV kCLOCK_Usdhc1Div
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#define SDMMC_CLOCK_MUX kCLOCK_Usdhc1Mux
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#define SDMMC_CLOCK_ROOT kCLOCK_Usdhc1ClkRoot
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#endif
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#ifndef MICROPY_HW_SDIO_CLK_ALT
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#define MICROPY_HW_SDIO_CMD_ALT (0)
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#define MICROPY_HW_SDIO_CLK_ALT (0)
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@ -51,8 +57,14 @@
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#else
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#define SDMMC USDHC2
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#define SDMMC_IRQn USDHC2_IRQn
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#ifdef MIMXRT117x_SERIES
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#define SDMMC_CLOCK_MUX kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2
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#define SDMMC_CLOCK_ROOT kCLOCK_Root_Usdhc2
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#else
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#define SDMMC_CLOCK_DIV kCLOCK_Usdhc2Div
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#define SDMMC_CLOCK_MUX kCLOCK_Usdhc2Mux
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#define SDMMC_CLOCK_ROOT kCLOCK_Usdhc2ClkRoot
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#endif
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#ifndef MICROPY_HW_SDIO_CLK_ALT
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#define MICROPY_HW_SDIO_CMD_ALT (6)
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#define MICROPY_HW_SDIO_CLK_ALT (6)
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@ -95,7 +107,11 @@ typedef enum {
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} sdio_xfer_flags_t;
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static uint32_t sdio_base_clk(void) {
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return CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U);
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#ifdef MIMXRT117x_SERIES
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return CLOCK_GetRootClockFreq(SDMMC_CLOCK_ROOT);
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#else
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return CLOCK_GetClockRootFreq(SDMMC_CLOCK_ROOT);
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#endif
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}
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static uint32_t sdio_response_type(uint32_t cmd) {
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@ -144,19 +160,30 @@ void sdio_init(uint32_t irq_pri) {
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machine_pin_config(MICROPY_HW_SDIO_D2, PIN_MODE_ALT, PIN_PULL_UP_100K, PIN_DRIVE_6, 0, MICROPY_HW_SDIO_D2_ALT);
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machine_pin_config(MICROPY_HW_SDIO_D3, PIN_MODE_ALT, PIN_PULL_UP_100K, PIN_DRIVE_6, 0, MICROPY_HW_SDIO_D3_ALT);
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#ifdef MIMXRT117x_SERIES
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CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
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clock_root_config_t rootCfg = { 0 };
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rootCfg.mux = SDMMC_CLOCK_MUX;
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rootCfg.div = 2;
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CLOCK_SetRootClock(SDMMC_CLOCK_ROOT, &rootCfg);
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#else
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// Configure PFD0 of PLL2 (system PLL) fractional divider to 24 resulting in:
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// with PFD0_clk = PLL2_clk * 18 / N
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// PFD0_clk = 528MHz * 18 / 24 = 396MHz
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CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
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CLOCK_SetDiv(SDMMC_CLOCK_DIV, 1U); // USDHC_input_clk = PFD0_clk / 2
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CLOCK_SetMux(SDMMC_CLOCK_MUX, 1U); // Select PFD0 as clock input for USDHC
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#endif
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// Initialize USDHC
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const usdhc_config_t config = {
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.endianMode = kUSDHC_EndianModeLittle,
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.dataTimeout = 0xFU,
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#ifndef MIMXRT117x_SERIES
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.readBurstLen = 0,
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.writeBurstLen = 0,
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#endif
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.readWatermarkLevel = 128U,
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.writeWatermarkLevel = 128U,
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};
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