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stmhal: Fix some typos in stm32f411 files, regarding FS layout and CSV.

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This commit is contained in:
Dave Hylands 2016-03-05 20:14:40 -08:00 committed by Damien George
parent 367c084c4b
commit 484a471f9b
2 changed files with 4 additions and 3 deletions
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3
stmhal/boards/stm32f411.ld
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@ -7,7 +7,8 @@ MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x080000 /* entire flash, 512 KiB */
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 0x004000 /* sector 0, 16 KiB */
FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x060000 /* sectors 5,6,7 4*128KiB = 384 KiB */
/* sectors 1,2,3 are 16K, 4 is 64K (for filesystem) */
FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x060000 /* sectors 5,6,7 3*128KiB = 384 KiB */
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x020000 /* 128 KiB */
}

4
stmhal/boards/stm32f411_af.csv
View File

@ -1,5 +1,5 @@
Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,
,,SYS_AF,TIM1/TIM2,TIM3/TIM4/TIM5,TIM9/TIM10/TIM11,I2C1/I2C2/I2C3,SPI1/I2S1/SPI2/I2S2/SPI3/I2S3,SPI2/I2S2/SPI3/I2S3/SPI4/I2S4/SPI5/I2S5,SPI3/I2S3/USART1/USART2,USART6,I2C2/I2C3,,,SDIO,,,,,ADC
,,SYS_AF,TIM1/TIM2,TIM3/TIM4/TIM5,TIM9/TIM10/TIM11,I2C1/I2C2/I2C3,SPI1/I2S1/SPI2/I2S2/SPI3/I2S3,SPI2/I2S2/SPI3/I2S3/SPI4/I2S4/SPI5/I2S5,SPI3/I2S3/USART1/USART2,USART6,I2C2/I2C3,,,SDIO,,,,ADC
PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,,EVENTOUT,ADC1_IN0
PortA,PA1,,TIM2_CH2,TIM5_CH2,,,SPI4_MOSI/I2S4_SD,,USART2_RTS,,,,,,,,EVENTOUT,ADC1_IN1
PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,I2S2_CKIN,,USART2_TX,,,,,,,,EVENTOUT,ADC1_IN2
@ -80,5 +80,5 @@ PortE,PE12,,TIM1_CH3N,,,,SPI4_SCK/I2S4_CK,SPI5_SCK/I2S5_CK,,,,,,,,,EVENTOUT,
PortE,PE13,,TIM1_CH3,,,,SPI4_MISO,SPI5_MISO,,,,,,,,,EVENTOUT,
PortE,PE14,,TIM1_CH4,,,,SPI4_MOSI/I2S4_SD,SPI5_MOSI/I2S5_SD,,,,,,,,,EVENTOUT,
PortE,PE15,,TIM1_BKIN,,,,,,,,,,,,,,EVENTOUT,
PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,,
PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,
PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT,

1 Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15, Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
2 ,,SYS_AF,TIM1/TIM2,TIM3/TIM4/TIM5,TIM9/TIM10/TIM11,I2C1/I2C2/I2C3,SPI1/I2S1/SPI2/I2S2/SPI3/I2S3,SPI2/I2S2/SPI3/I2S3/SPI4/I2S4/SPI5/I2S5,SPI3/I2S3/USART1/USART2,USART6,I2C2/I2C3,,,SDIO,,,,,ADC SYS_AF TIM1/TIM2 TIM3/TIM4/TIM5 TIM9/TIM10/TIM11 I2C1/I2C2/I2C3 SPI1/I2S1/SPI2/I2S2/SPI3/I2S3 SPI2/I2S2/SPI3/I2S3/SPI4/I2S4/SPI5/I2S5 SPI3/I2S3/USART1/USART2 USART6 I2C2/I2C3 SDIO ADC
3 PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,,EVENTOUT,ADC1_IN0 PortA PA0 TIM2_CH1/TIM2_ETR TIM5_CH1 USART2_CTS EVENTOUT ADC1_IN0
4 PortA,PA1,,TIM2_CH2,TIM5_CH2,,,SPI4_MOSI/I2S4_SD,,USART2_RTS,,,,,,,,EVENTOUT,ADC1_IN1 PortA PA1 TIM2_CH2 TIM5_CH2 SPI4_MOSI/I2S4_SD USART2_RTS EVENTOUT ADC1_IN1
5 PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,I2S2_CKIN,,USART2_TX,,,,,,,,EVENTOUT,ADC1_IN2 PortA PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 I2S2_CKIN USART2_TX EVENTOUT ADC1_IN2
80 PortE,PE13,,TIM1_CH3,,,,SPI4_MISO,SPI5_MISO,,,,,,,,,EVENTOUT, PortE PE13 TIM1_CH3 SPI4_MISO SPI5_MISO EVENTOUT
81 PortE,PE14,,TIM1_CH4,,,,SPI4_MOSI/I2S4_SD,SPI5_MOSI/I2S5_SD,,,,,,,,,EVENTOUT, PortE PE14 TIM1_CH4 SPI4_MOSI/I2S4_SD SPI5_MOSI/I2S5_SD EVENTOUT
82 PortE,PE15,,TIM1_BKIN,,,,,,,,,,,,,,EVENTOUT, PortE PE15 TIM1_BKIN EVENTOUT
83 PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,, PortH PH0 EVENTOUT
84 PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT, PortH PH1 EVENTOUT