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Implement F7 Nucleo

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This commit is contained in:
Lucian Copeland 2020-04-02 11:47:16 -04:00
parent 80b08bfaec
commit 47a5d83267
27 changed files with 3038 additions and 28 deletions
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2
ports/mimxrt10xx/supervisor/port.c
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@ -154,7 +154,7 @@ __attribute__((used, naked)) void Reset_Handler(void) {
/* Disable MPU */
ARM_MPU_Disable();
// Copy all of the code to run from ITCM. Do this while the MPU is disabled because we write
// Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write
// protect it.
for (uint32_t i = 0; i < ((size_t) &_ld_itcm_size) / 4; i++) {
(&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i];

7
ports/stm/Makefile
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@ -96,11 +96,8 @@ C_DEFS = -D$(MCU_PACKAGE) -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -D$(MCU_VARIANT)
CFLAGS += $(INC) -Werror -Wall -std=gnu11 -nostdlib $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT)
# Undo some warnings.
# STM32 apparently also uses undefined preprocessor variables quite casually,
# so we can't do warning checks for these.
CFLAGS += -Wno-undef
# STM32 might do casts that increase alignment requirements.
CFLAGS += -Wno-cast-align
# STM32 HAL uses undefined preprocessor variables, shadowed variables, casts that change alignment reqs
CFLAGS += -Wno-undef -Wno-shadow -Wno-cast-align
CFLAGS += -mthumb -mabi=aapcs-linux

189
ports/stm/boards/STM32F767ZITx_FLASH.ld Normal file
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@ -0,0 +1,189 @@
/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Author : Auto-generated by System Workbench for STM32
**
** Abstract : Linker script for STM32F767ZITx series
** 2048Kbytes FLASH and 512Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20080000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

107
ports/stm/boards/STM32F767_fs.ld Normal file
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@ -0,0 +1,107 @@
/*
GNU linker script for STM32F405 via Micropython
*/
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 32K /* sector 0 */
FLASH_FS (rx) : ORIGIN = 0x08008000, LENGTH = 96K /* sectors 1,2,3 are 32K */
FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 1920K /* sector 4 is 128K, sectors 5,6,7 are 256K */
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
above last byte of RAM. Note that EABI requires the stack to be 8-byte
aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
ENTRY(Reset_Handler)
/* define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
/* This first flash block is 16K annd the isr vectors only take up
about 400 bytes. Micropython pads this with files, but this didn't
work with the size of Circuitpython's ff object. */
. = ALIGN(4);
} >FLASH_ISR
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text*) /* .text* sections (code) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
/* *(.glue_7) */ /* glue arm to thumb code */
/* *(.glue_7t) */ /* glue thumb to arm code */
. = ALIGN(4);
_etext = .; /* define a global symbol at end of code */
} >FLASH_TEXT
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* This is the initialized data section
The program executes knowing that the data is in the RAM
but the loader puts the initial values in the FLASH (inidata).
It is one task of the startup to copy the initial values from FLASH to RAM. */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
} >RAM AT> FLASH_TEXT
/* Uninitialized data section */
.bss :
{
. = ALIGN(4);
_sbss = .; /* define a global symbol at bss start; used by startup code */
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end; used by startup code and GC */
} >RAM
/* this is to define the start of the heap, and make sure we have a minimum size */
.heap :
{
. = ALIGN(4);
. = . + _minimum_heap_size;
. = ALIGN(4);
} >RAM
/* this just checks there is enough RAM for the stack */
.stack :
{
. = ALIGN(4);
. = . + _minimum_stack_size;
. = ALIGN(4);
} >RAM
.ARM.attributes 0 : { *(.ARM.attributes) }
}

38
ports/stm/boards/nucleo_f767zi/board.c Normal file
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@ -0,0 +1,38 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "boards/board.h"
void board_init(void) {
}
bool board_requests_safe_mode(void) {
return false;
}
void reset_board(void) {
}

35
ports/stm/boards/nucleo_f767zi/mpconfigboard.h Normal file
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@ -0,0 +1,35 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
//Micropython setup
#define MICROPY_HW_BOARD_NAME "NUCLEO STM32F767"
#define MICROPY_HW_MCU_NAME "STM32F767"
#define FLASH_SIZE (0x200000)
#define FLASH_PAGE_SIZE (0x4000)
#define BOARD_OSC_DIV (8)

14
ports/stm/boards/nucleo_f767zi/mpconfigboard.mk Normal file
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@ -0,0 +1,14 @@
USB_VID = 0x239A #REPLACE
USB_PID = 0x808A #REPLACE
USB_PRODUCT = "Nucleo F767ZI - CPy"
USB_MANUFACTURER = "STMicroelectronics"
USB_DEVICES = "CDC,MSC"
INTERNAL_FLASH_FILESYSTEM = 1
MCU_SERIES = F7
MCU_VARIANT = STM32F767xx
MCU_PACKAGE = LQFP144
LD_FILE = boards/STM32F767_fs.ld

142
ports/stm/boards/nucleo_f767zi/pins.c Normal file
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@ -0,0 +1,142 @@
#include "shared-bindings/board/__init__.h"
STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) },
{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) },
{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) },
{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) },
{ MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PB01) },
{ MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PC02) },
{ MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PF04) },
{ MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) },
{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) },
{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) },
{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) },
{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) },
{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) },
{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) },
{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) },
{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
{ MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
{ MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) },
{ MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) },
{ MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) },
{ MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) },
{ MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) },
{ MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) },
{ MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) },
{ MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) },
{ MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) },
{ MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) },
{ MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) },
{ MP_ROM_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_PB06) },
{ MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_PB02) },
{ MP_ROM_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_PD13) },
{ MP_ROM_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_PD12) },
{ MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PD11) },
{ MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PE02) },
{ MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA00) },
{ MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PB00) },
{ MP_ROM_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_PE00) },
{ MP_ROM_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_PB11) },
{ MP_ROM_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_PB10) },
{ MP_ROM_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_PE15) },
{ MP_ROM_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_PE14) },
{ MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_PE12) },
{ MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_PE10) },
{ MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_PE07) },
{ MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_PE08) },
{ MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_PC08) },
{ MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_PC09) },
{ MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_PC10) },
{ MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_PC11) },
{ MP_ROM_QSTR(MP_QSTR_D47), MP_ROM_PTR(&pin_PC12) },
{ MP_ROM_QSTR(MP_QSTR_D48), MP_ROM_PTR(&pin_PD02) },
{ MP_ROM_QSTR(MP_QSTR_D49), MP_ROM_PTR(&pin_PG02) },
{ MP_ROM_QSTR(MP_QSTR_D50), MP_ROM_PTR(&pin_PG03) },
{ MP_ROM_QSTR(MP_QSTR_D51), MP_ROM_PTR(&pin_PD07) },
{ MP_ROM_QSTR(MP_QSTR_D52), MP_ROM_PTR(&pin_PD06) },
{ MP_ROM_QSTR(MP_QSTR_D53), MP_ROM_PTR(&pin_PD05) },
{ MP_ROM_QSTR(MP_QSTR_D54), MP_ROM_PTR(&pin_PD04) },
{ MP_ROM_QSTR(MP_QSTR_D55), MP_ROM_PTR(&pin_PD03) },
{ MP_ROM_QSTR(MP_QSTR_D56), MP_ROM_PTR(&pin_PE02) },
{ MP_ROM_QSTR(MP_QSTR_D57), MP_ROM_PTR(&pin_PE04) },
{ MP_ROM_QSTR(MP_QSTR_D58), MP_ROM_PTR(&pin_PE05) },
{ MP_ROM_QSTR(MP_QSTR_D59), MP_ROM_PTR(&pin_PE06) },
{ MP_ROM_QSTR(MP_QSTR_D60), MP_ROM_PTR(&pin_PE03) },
{ MP_ROM_QSTR(MP_QSTR_D61), MP_ROM_PTR(&pin_PF08) },
{ MP_ROM_QSTR(MP_QSTR_D62), MP_ROM_PTR(&pin_PF07) },
{ MP_ROM_QSTR(MP_QSTR_D63), MP_ROM_PTR(&pin_PF09) },
{ MP_ROM_QSTR(MP_QSTR_D64), MP_ROM_PTR(&pin_PG01) },
{ MP_ROM_QSTR(MP_QSTR_D65), MP_ROM_PTR(&pin_PG00) },
{ MP_ROM_QSTR(MP_QSTR_D66), MP_ROM_PTR(&pin_PD01) },
{ MP_ROM_QSTR(MP_QSTR_D67), MP_ROM_PTR(&pin_PD00) },
{ MP_ROM_QSTR(MP_QSTR_D68), MP_ROM_PTR(&pin_PF00) },
{ MP_ROM_QSTR(MP_QSTR_D69), MP_ROM_PTR(&pin_PF01) },
{ MP_ROM_QSTR(MP_QSTR_D70), MP_ROM_PTR(&pin_PF02) },
{ MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PA07) },
{ MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) },
{ MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) },
{ MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) },
{ MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) },
{ MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) },
{ MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) },
{ MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) },
{ MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) },
{ MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) },
{ MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) },
{ MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) },
{ MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) },
{ MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PG02) },
{ MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PG06) },
{ MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PG07) },
{ MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) },
{ MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) },
{ MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) },
{ MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) },
{ MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) },
{ MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) },
{ MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) },
{ MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) },
{ MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PD08) },
{ MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PD09) },
{ MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PD08) },
{ MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PD09) },
{ MP_ROM_QSTR(MP_QSTR_UART5_TX), MP_ROM_PTR(&pin_PB06) },
{ MP_ROM_QSTR(MP_QSTR_UART5_RX), MP_ROM_PTR(&pin_PB12) },
{ MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PC06) },
{ MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PC07) },
{ MP_ROM_QSTR(MP_QSTR_UART7_TX), MP_ROM_PTR(&pin_PF07) },
{ MP_ROM_QSTR(MP_QSTR_UART7_RX), MP_ROM_PTR(&pin_PF06) },
{ MP_ROM_QSTR(MP_QSTR_UART8_TX), MP_ROM_PTR(&pin_PE01) },
{ MP_ROM_QSTR(MP_QSTR_UART8_RX), MP_ROM_PTR(&pin_PE00) },
{ MP_ROM_QSTR(MP_QSTR_SPI3_NSS), MP_ROM_PTR(&pin_PA04) },
{ MP_ROM_QSTR(MP_QSTR_SPI3_SCK), MP_ROM_PTR(&pin_PB03) },
{ MP_ROM_QSTR(MP_QSTR_SPI3_MISO), MP_ROM_PTR(&pin_PB04) },
{ MP_ROM_QSTR(MP_QSTR_SPI3_MOSI), MP_ROM_PTR(&pin_PB05) },
{ MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) },
{ MP_ROM_QSTR(MP_QSTR_I2C1_SCL), MP_ROM_PTR(&pin_PB08) },
{ MP_ROM_QSTR(MP_QSTR_I2C2_SDA), MP_ROM_PTR(&pin_PF00) },
{ MP_ROM_QSTR(MP_QSTR_I2C2_SCL), MP_ROM_PTR(&pin_PF01) },
{ MP_ROM_QSTR(MP_QSTR_I2C4_SCL), MP_ROM_PTR(&pin_PF14) },
{ MP_ROM_QSTR(MP_QSTR_I2C4_SDA), MP_ROM_PTR(&pin_PF15) },
{ MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) },
{ MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) },
{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) },
{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) },
{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) },
{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) },
{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) },
{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) },
{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PB13) },
{ MP_ROM_QSTR(MP_QSTR_SWDIO), MP_ROM_PTR(&pin_PA13) },
{ MP_ROM_QSTR(MP_QSTR_SWDCLK), MP_ROM_PTR(&pin_PA14) }
};
MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);

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/**
******************************************************************************
* @file stm32f7xx_hal_conf_template.h
* @author MCD Application Team
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f7xx_hal_conf.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_CONF_H
#define __STM32F7xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
#define HAL_DAC_MODULE_ENABLED
/* #define HAL_DCMI_MODULE_ENABLED */
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
/* #define HAL_SDRAM_MODULE_ENABLED */
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
/* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_MDIOS_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_EXTI_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U
#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* LAN8742A_PHY_ADDRESS Address*/
#define LAN8742A_PHY_ADDRESS 0
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x1FU) /*!< PHY status register Offset */
#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */
#define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */
#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f7xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f7xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f7xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f7xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f7xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f7xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f7xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f7xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f7xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f7xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f7xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f7xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f7xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f7xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f7xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f7xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f7xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f7xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f7xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f7xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f7xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f7xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f7xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32f7xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f7xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f7xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32f7xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f7xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f7xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f7xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f7xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f7xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32f7xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f7xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f7xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f7xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f7xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f7xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f7xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f7xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f7xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f7xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32f7xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32f7xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_JPEG_MODULE_ENABLED
#include "stm32f7xx_hal_jpeg.h"
#endif /* HAL_JPEG_MODULE_ENABLED */
#ifdef HAL_MDIOS_MODULE_ENABLED
#include "stm32f7xx_hal_mdios.h"
#endif /* HAL_MDIOS_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f7xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file startup_stm32f767xx.s
* @author MCD Application Team
* @brief STM32F767xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M7 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M7. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* RNG */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word 0 /* Reserved */
.word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
.word SDMMC2_IRQHandler /* SDMMC2 */
.word CAN3_TX_IRQHandler /* CAN3 TX */
.word CAN3_RX0_IRQHandler /* CAN3 RX0 */
.word CAN3_RX1_IRQHandler /* CAN3 RX1 */
.word CAN3_SCE_IRQHandler /* CAN3 SCE */
.word JPEG_IRQHandler /* JPEG */
.word MDIOS_IRQHandler /* MDIOS */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak CAN3_TX_IRQHandler
.thumb_set CAN3_TX_IRQHandler,Default_Handler
.weak CAN3_RX0_IRQHandler
.thumb_set CAN3_RX0_IRQHandler,Default_Handler
.weak CAN3_RX1_IRQHandler
.thumb_set CAN3_RX1_IRQHandler,Default_Handler
.weak CAN3_SCE_IRQHandler
.thumb_set CAN3_SCE_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
ports/stm/common-hal/digitalio/DigitalInOut.c
View File

@ -32,6 +32,8 @@
//TODO: rework this module to use HAL only
#ifdef STM32H743xx
#include "stm32h7xx_ll_gpio.h"
#elif STM32F767xx
#include "stm32f7xx_ll_gpio.h"
#else
#include "stm32f4xx_ll_gpio.h"
#endif

16
ports/stm/mpconfigport.mk
View File

@ -88,3 +88,19 @@ ifeq ($(MCU_SERIES), H7)
CIRCUITPY_NEOPIXEL_WRITE = 0
CIRCUITPY_DISPLAYIO = 0
endif
ifeq ($(MCU_SERIES), F7)
CIRCUITPY_BOARD = 1
CIRCUITPY_DIGITALIO = 1
CIRCUITPY_ANALOGIO = 0
CIRCUITPY_MICROCONTROLLER = 1
CIRCUITPY_BUSIO = 0
CIRCUITPY_PULSEIO = 0
CIRCUITPY_OS = 0
CIRCUITPY_STORAGE = 0
CIRCUITPY_RANDOM = 0
CIRCUITPY_USB_HID = 0
CIRCUITPY_USB_MIDI = 0
CIRCUITPY_NEOPIXEL_WRITE = 0
CIRCUITPY_DISPLAYIO = 0
endif

9
ports/stm/peripherals/periph.h
View File

@ -105,6 +105,15 @@ typedef struct {
#include "stm32f4/stm32f407xx/periph.h"
#endif
// F7 Series
#ifdef STM32F767xx
#define HAS_DAC 0
#define HAS_TRNG 0
#define HAS_BASIC_TIM 0
#include "stm32f7/stm32f767xx/periph.h"
#endif
// H7 Series
// Single Core

5
ports/stm/peripherals/pins.h
View File

@ -92,6 +92,11 @@ extern const mp_obj_type_t mcu_pin_type;
#include "stm32f4/stm32f407xx/pins.h"
#endif
// F7 Series
#ifdef STM32F767xx
#include "stm32f7/stm32f767xx/pins.h"
#endif
// H7 Series
#ifdef STM32H743xx
#include "stm32h7/stm32h743xx/pins.h"

66
ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c Normal file
View File

@ -0,0 +1,66 @@
/*
* This file is part of the Micro Python project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/mpconfig.h"
void stm32_peripherals_clocks_init(void) {
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
/* Enable Power Control clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
RCC_OscInitStruct.PLL.PLLN = 432;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 9;
RCC_OscInitStruct.PLL.PLLR = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Activate the OverDrive to reach the 216 MHz Frequency */
HAL_PWREx_EnableOverDrive();
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
}

48
ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c Normal file
View File

@ -0,0 +1,48 @@
/*
* This file is part of the Micro Python project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "gpio.h"
#include "common-hal/microcontroller/Pin.h"
void stm32_peripherals_gpio_init(void) {
//Enable all GPIO for now
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
//Never reset pins
never_reset_pin_number(2,14); //PC14 OSC32_IN
never_reset_pin_number(2,15); //PC15 OSC32_OUT
never_reset_pin_number(0,13); //PA13 SWDIO
never_reset_pin_number(0,14); //PA14 SWCLK
}

248
ports/stm/peripherals/stm32f7/stm32f767xx/periph.c Normal file
View File

@ -0,0 +1,248 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/obj.h"
#include "py/mphal.h"
#include "peripherals/pins.h"
#include "peripherals/periph.h"
// I2C
I2C_TypeDef * mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4};
const mcu_periph_obj_t mcu_i2c_sda_list[12] = {
PERIPH(1, 4, &pin_PB07),
PERIPH(4, 11, &pin_PB07),
PERIPH(4, 1, &pin_PB09),
PERIPH(1, 4, &pin_PB09),
PERIPH(2, 4, &pin_PB11),
PERIPH(3, 4, &pin_PC09),
PERIPH(4, 4, &pin_PD13),
PERIPH(2, 4, &pin_PF00),
PERIPH(4, 4, &pin_PF15),
PERIPH(2, 4, &pin_PH05),
PERIPH(3, 4, &pin_PH08),
PERIPH(4, 4, &pin_PH12),
};
const mcu_periph_obj_t mcu_i2c_scl_list[12] = {
PERIPH(3, 4, &pin_PA08),
PERIPH(1, 4, &pin_PB06),
PERIPH(4, 11, &pin_PB06),
PERIPH(4, 1, &pin_PB08),
PERIPH(1, 4, &pin_PB08),
PERIPH(2, 4, &pin_PB10),
PERIPH(4, 4, &pin_PD12),
PERIPH(2, 4, &pin_PF01),
PERIPH(4, 4, &pin_PF14),
PERIPH(2, 4, &pin_PH04),
PERIPH(3, 4, &pin_PH07),
PERIPH(4, 4, &pin_PH11),
};
//SPI
SPI_TypeDef * mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6};
const mcu_periph_obj_t mcu_spi_sck_list[18] = {
PERIPH(1, 5, &pin_PA05),
PERIPH(6, 8, &pin_PA05),
PERIPH(2, 5, &pin_PA09),
PERIPH(2, 5, &pin_PA12),
PERIPH(1, 5, &pin_PB03),
PERIPH(3, 6, &pin_PB03),
PERIPH(6, 8, &pin_PB03),
PERIPH(2, 5, &pin_PB10),
PERIPH(2, 5, &pin_PB13),
PERIPH(3, 6, &pin_PC10),
PERIPH(2, 5, &pin_PD03),
PERIPH(4, 5, &pin_PE02),
PERIPH(4, 5, &pin_PE12),
PERIPH(5, 5, &pin_PF07),
PERIPH(1, 5, &pin_PG11),
PERIPH(6, 5, &pin_PG13),
PERIPH(5, 5, &pin_PH06),
PERIPH(2, 5, &pin_PI01),
};
const mcu_periph_obj_t mcu_spi_mosi_list[18] = {
PERIPH(1, 5, &pin_PA07),
PERIPH(6, 8, &pin_PA07),
PERIPH(3, 7, &pin_PB02),
PERIPH(1, 5, &pin_PB05),
PERIPH(3, 6, &pin_PB05),
PERIPH(6, 8, &pin_PB05),
PERIPH(2, 5, &pin_PB15),
PERIPH(2, 5, &pin_PC01),
PERIPH(2, 5, &pin_PC03),
PERIPH(3, 6, &pin_PC12),
PERIPH(3, 5, &pin_PD06),
PERIPH(1, 5, &pin_PD07),
PERIPH(4, 5, &pin_PE06),
PERIPH(4, 5, &pin_PE14),
PERIPH(5, 5, &pin_PF09),
PERIPH(5, 5, &pin_PF11),
PERIPH(6, 5, &pin_PG14),
PERIPH(2, 5, &pin_PI03),
};
const mcu_periph_obj_t mcu_spi_miso_list[15] = {
PERIPH(1, 5, &pin_PA06),
PERIPH(6, 8, &pin_PA06),
PERIPH(1, 5, &pin_PB04),
PERIPH(3, 6, &pin_PB04),
PERIPH(6, 8, &pin_PB04),
PERIPH(2, 5, &pin_PB14),
PERIPH(2, 5, &pin_PC02),
PERIPH(3, 6, &pin_PC11),
PERIPH(4, 5, &pin_PE05),
PERIPH(4, 5, &pin_PE13),
PERIPH(5, 5, &pin_PF08),
PERIPH(1, 5, &pin_PG09),
PERIPH(6, 5, &pin_PG12),
PERIPH(5, 5, &pin_PH07),
PERIPH(2, 5, &pin_PI02),
};
//UART
USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8};
bool mcu_uart_has_usart[MAX_UART] = {true, true, true, true, true, true, true, true};
const mcu_periph_obj_t mcu_uart_tx_list[24] = {
PERIPH(4, 8, &pin_PA00),
PERIPH(2, 7, &pin_PA02),
PERIPH(1, 7, &pin_PA09),
PERIPH(4, 6, &pin_PA12),
PERIPH(7, 12, &pin_PA15),
PERIPH(7, 12, &pin_PB04),
PERIPH(5, 1, &pin_PB06),
PERIPH(1, 7, &pin_PB06),
PERIPH(5, 7, &pin_PB09),
PERIPH(3, 7, &pin_PB10),
PERIPH(5, 8, &pin_PB13),
PERIPH(1, 4, &pin_PB14),
PERIPH(6, 8, &pin_PC06),
PERIPH(3, 7, &pin_PC10),
PERIPH(4, 8, &pin_PC10),
PERIPH(5, 8, &pin_PC12),
PERIPH(4, 8, &pin_PD01),
PERIPH(2, 7, &pin_PD05),
PERIPH(3, 7, &pin_PD08),
PERIPH(8, 8, &pin_PE01),
PERIPH(7, 8, &pin_PE08),
PERIPH(7, 8, &pin_PF07),
PERIPH(6, 8, &pin_PG14),
PERIPH(4, 8, &pin_PH13),
};
const mcu_periph_obj_t mcu_uart_rx_list[25] = {
PERIPH(4, 8, &pin_PA01),
PERIPH(2, 7, &pin_PA03),
PERIPH(7, 12, &pin_PA08),
PERIPH(1, 7, &pin_PA10),
PERIPH(4, 6, &pin_PA11),
PERIPH(7, 12, &pin_PB03),
PERIPH(5, 1, &pin_PB05),
PERIPH(1, 7, &pin_PB07),
PERIPH(5, 7, &pin_PB08),
PERIPH(3, 7, &pin_PB11),
PERIPH(5, 8, &pin_PB12),
PERIPH(1, 4, &pin_PB15),
PERIPH(6, 8, &pin_PC07),
PERIPH(3, 7, &pin_PC11),
PERIPH(4, 8, &pin_PC11),
PERIPH(4, 8, &pin_PD00),
PERIPH(5, 8, &pin_PD02),
PERIPH(2, 7, &pin_PD06),
PERIPH(3, 7, &pin_PD09),
PERIPH(8, 8, &pin_PE00),
PERIPH(7, 8, &pin_PE07),
PERIPH(7, 8, &pin_PF06),
PERIPH(6, 8, &pin_PG09),
PERIPH(4, 8, &pin_PH14),
PERIPH(4, 8, &pin_PI09),
};
//Timers
//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
//TODO: H7 has more timers than this, but are they tied to pins?
TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL,
NULL, TIM12, TIM13, TIM14};
const mcu_tim_pin_obj_t mcu_tim_pin_list[55] = {
TIM(2, 1, 1, &pin_PA00),
TIM(5, 2, 1, &pin_PA00),
TIM(2, 1, 2, &pin_PA01),
TIM(5, 2, 2, &pin_PA01),
TIM(2, 1, 3, &pin_PA02),
TIM(5, 2, 3, &pin_PA02),
TIM(9, 3, 1, &pin_PA02),
TIM(2, 1, 4, &pin_PA03),
TIM(5, 2, 4, &pin_PA03),
TIM(9, 3, 2, &pin_PA03),
TIM(2, 1, 1, &pin_PA05),
TIM(3, 2, 1, &pin_PA06),
TIM(3, 2, 2, &pin_PA07),
TIM(1, 1, 1, &pin_PA08),
TIM(1, 1, 2, &pin_PA09),
TIM(1, 1, 3, &pin_PA10),
TIM(1, 1, 4, &pin_PA11),
TIM(2, 1, 1, &pin_PA15),
TIM(3, 2, 3, &pin_PB00),
TIM(3, 2, 4, &pin_PB01),
TIM(2, 1, 2, &pin_PB03),
TIM(3, 2, 1, &pin_PB04),
TIM(3, 2, 2, &pin_PB05),
TIM(4, 2, 1, &pin_PB06),
TIM(4, 2, 2, &pin_PB07),
TIM(4, 2, 3, &pin_PB08),
TIM(4, 2, 4, &pin_PB09),
TIM(2, 1, 3, &pin_PB10),
TIM(2, 1, 4, &pin_PB11),
TIM(3, 2, 1, &pin_PC06),
TIM(8, 3, 1, &pin_PC06),
TIM(3, 2, 2, &pin_PC07),
TIM(8, 3, 2, &pin_PC07),
TIM(3, 2, 3, &pin_PC08),
TIM(8, 3, 3, &pin_PC08),
TIM(3, 2, 4, &pin_PC09),
TIM(8, 3, 4, &pin_PC09),
TIM(4, 2, 1, &pin_PD12),
TIM(4, 2, 2, &pin_PD13),
TIM(4, 2, 3, &pin_PD14),
TIM(4, 2, 4, &pin_PD15),
TIM(9, 3, 1, &pin_PE05),
TIM(9, 3, 2, &pin_PE06),
TIM(1, 1, 1, &pin_PE09),
TIM(1, 1, 2, &pin_PE11),
TIM(1, 1, 3, &pin_PE13),
TIM(1, 1, 4, &pin_PE14),
TIM(5, 2, 1, &pin_PH10),
TIM(5, 2, 2, &pin_PH11),
TIM(5, 2, 3, &pin_PH12),
TIM(5, 2, 4, &pin_PI00),
TIM(8, 3, 4, &pin_PI02),
TIM(8, 3, 1, &pin_PI05),
TIM(8, 3, 2, &pin_PI06),
TIM(8, 3, 3, &pin_PI07),
};

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H
#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H
//I2C
extern I2C_TypeDef * mcu_i2c_banks[4];
const mcu_periph_obj_t mcu_i2c_sda_list[12];
const mcu_periph_obj_t mcu_i2c_scl_list[12];
//SPI
extern SPI_TypeDef * mcu_spi_banks[6];
const mcu_periph_obj_t mcu_spi_sck_list[18];
const mcu_periph_obj_t mcu_spi_mosi_list[18];
const mcu_periph_obj_t mcu_spi_miso_list[15];
//UART
extern USART_TypeDef * mcu_uart_banks[MAX_UART];
extern bool mcu_uart_has_usart[MAX_UART];
const mcu_periph_obj_t mcu_uart_tx_list[24];
const mcu_periph_obj_t mcu_uart_rx_list[25];
//Timers
#define TIM_BANK_ARRAY_LEN 14
#define TIM_PIN_ARRAY_LEN 55
TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/obj.h"
#include "py/mphal.h"
#include "peripherals/pins.h"
// Todo: some pins do have ADCs, but the module isn't set up yet.
const mcu_pin_obj_t pin_PA00 = PIN(0, 0, NO_ADC);
const mcu_pin_obj_t pin_PA01 = PIN(0, 1, NO_ADC);
const mcu_pin_obj_t pin_PA02 = PIN(0, 2, NO_ADC);
const mcu_pin_obj_t pin_PA03 = PIN(0, 3, NO_ADC);
const mcu_pin_obj_t pin_PA04 = PIN(0, 4, NO_ADC);
const mcu_pin_obj_t pin_PA05 = PIN(0, 5, NO_ADC);
const mcu_pin_obj_t pin_PA06 = PIN(0, 6, NO_ADC);
const mcu_pin_obj_t pin_PA07 = PIN(0, 7, NO_ADC);
const mcu_pin_obj_t pin_PA08 = PIN(0, 8, NO_ADC);
const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC);
const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC);
const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC);
const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC);
const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC);
const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC);
const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC);
const mcu_pin_obj_t pin_PB00 = PIN(1, 0, NO_ADC);
const mcu_pin_obj_t pin_PB01 = PIN(1, 1, NO_ADC);
const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC);
const mcu_pin_obj_t pin_PB03 = PIN(1, 3, NO_ADC);
const mcu_pin_obj_t pin_PB04 = PIN(1, 4, NO_ADC);
const mcu_pin_obj_t pin_PB05 = PIN(1, 5, NO_ADC);
const mcu_pin_obj_t pin_PB06 = PIN(1, 6, NO_ADC);
const mcu_pin_obj_t pin_PB07 = PIN(1, 7, NO_ADC);
const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC);
const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC);
const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC);
const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC);
const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC);
const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC);
const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC);
const mcu_pin_obj_t pin_PB15 = PIN(1, 15, NO_ADC);
const mcu_pin_obj_t pin_PC00 = PIN(2, 0, NO_ADC);
const mcu_pin_obj_t pin_PC01 = PIN(2, 1, NO_ADC);
const mcu_pin_obj_t pin_PC02 = PIN(2, 2, NO_ADC);
const mcu_pin_obj_t pin_PC03 = PIN(2, 3, NO_ADC);
const mcu_pin_obj_t pin_PC04 = PIN(2, 4, NO_ADC);
const mcu_pin_obj_t pin_PC05 = PIN(2, 5, NO_ADC);
const mcu_pin_obj_t pin_PC06 = PIN(2, 6, NO_ADC);
const mcu_pin_obj_t pin_PC07 = PIN(2, 7, NO_ADC);
const mcu_pin_obj_t pin_PC08 = PIN(2, 8, NO_ADC);
const mcu_pin_obj_t pin_PC09 = PIN(2, 9, NO_ADC);
const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC);
const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC);
const mcu_pin_obj_t pin_PC12 = PIN(2, 12, NO_ADC);
const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC);
const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC);
const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC);
const mcu_pin_obj_t pin_PD00 = PIN(3, 0, NO_ADC);
const mcu_pin_obj_t pin_PD01 = PIN(3, 1, NO_ADC);
const mcu_pin_obj_t pin_PD02 = PIN(3, 2, NO_ADC);
const mcu_pin_obj_t pin_PD03 = PIN(3, 3, NO_ADC);
const mcu_pin_obj_t pin_PD04 = PIN(3, 4, NO_ADC);
const mcu_pin_obj_t pin_PD05 = PIN(3, 5, NO_ADC);
const mcu_pin_obj_t pin_PD06 = PIN(3, 6, NO_ADC);
const mcu_pin_obj_t pin_PD07 = PIN(3, 7, NO_ADC);
const mcu_pin_obj_t pin_PD08 = PIN(3, 8, NO_ADC);
const mcu_pin_obj_t pin_PD09 = PIN(3, 9, NO_ADC);
const mcu_pin_obj_t pin_PD10 = PIN(3, 10, NO_ADC);
const mcu_pin_obj_t pin_PD11 = PIN(3, 11, NO_ADC);
const mcu_pin_obj_t pin_PD12 = PIN(3, 12, NO_ADC);
const mcu_pin_obj_t pin_PD13 = PIN(3, 13, NO_ADC);
const mcu_pin_obj_t pin_PD14 = PIN(3, 14, NO_ADC);
const mcu_pin_obj_t pin_PD15 = PIN(3, 15, NO_ADC);
const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC);
const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC);
const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC);
const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC);
const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC);
const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC);
const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC);
const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC);
const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC);
const mcu_pin_obj_t pin_PE09 = PIN(4, 9, NO_ADC);
const mcu_pin_obj_t pin_PE10 = PIN(4, 10, NO_ADC);
const mcu_pin_obj_t pin_PE11 = PIN(4, 11, NO_ADC);
const mcu_pin_obj_t pin_PE12 = PIN(4, 12, NO_ADC);
const mcu_pin_obj_t pin_PE13 = PIN(4, 13, NO_ADC);
const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC);
const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC);
const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC);
const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC);
const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC);
const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC);
const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC);
const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC);
const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC);
const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC);
const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC);
const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC);
const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC);
const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC);
const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC);
const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC);
const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC);
const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC);
const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC);
const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC);
const mcu_pin_obj_t pin_PG02 = PIN(6, 2, NO_ADC);
const mcu_pin_obj_t pin_PG03 = PIN(6, 3, NO_ADC);
const mcu_pin_obj_t pin_PG04 = PIN(6, 4, NO_ADC);
const mcu_pin_obj_t pin_PG05 = PIN(6, 5, NO_ADC);
const mcu_pin_obj_t pin_PG06 = PIN(6, 6, NO_ADC);
const mcu_pin_obj_t pin_PG07 = PIN(6, 7, NO_ADC);
const mcu_pin_obj_t pin_PG08 = PIN(6, 8, NO_ADC);
const mcu_pin_obj_t pin_PG09 = PIN(6, 9, NO_ADC);
const mcu_pin_obj_t pin_PG10 = PIN(6, 10, NO_ADC);
const mcu_pin_obj_t pin_PG11 = PIN(6, 11, NO_ADC);
const mcu_pin_obj_t pin_PG12 = PIN(6, 12, NO_ADC);
const mcu_pin_obj_t pin_PG13 = PIN(6, 13, NO_ADC);
const mcu_pin_obj_t pin_PG14 = PIN(6, 14, NO_ADC);
const mcu_pin_obj_t pin_PG15 = PIN(6, 15, NO_ADC);
const mcu_pin_obj_t pin_PH00 = PIN(7, 0, NO_ADC);
const mcu_pin_obj_t pin_PH01 = PIN(7, 1, NO_ADC);
const mcu_pin_obj_t pin_PH02 = PIN(7, 2, NO_ADC);
const mcu_pin_obj_t pin_PH03 = PIN(7, 3, NO_ADC);
const mcu_pin_obj_t pin_PH04 = PIN(7, 4, NO_ADC);
const mcu_pin_obj_t pin_PH05 = PIN(7, 5, NO_ADC);
const mcu_pin_obj_t pin_PH06 = PIN(7, 6, NO_ADC);
const mcu_pin_obj_t pin_PH07 = PIN(7, 7, NO_ADC);
const mcu_pin_obj_t pin_PH08 = PIN(7, 8, NO_ADC);
const mcu_pin_obj_t pin_PH09 = PIN(7, 9, NO_ADC);
const mcu_pin_obj_t pin_PH10 = PIN(7, 10, NO_ADC);
const mcu_pin_obj_t pin_PH11 = PIN(7, 11, NO_ADC);
const mcu_pin_obj_t pin_PH12 = PIN(7, 12, NO_ADC);
const mcu_pin_obj_t pin_PH13 = PIN(7, 13, NO_ADC);
const mcu_pin_obj_t pin_PH14 = PIN(7, 14, NO_ADC);
const mcu_pin_obj_t pin_PH15 = PIN(7, 15, NO_ADC);
const mcu_pin_obj_t pin_PI00 = PIN(8, 0, NO_ADC);
const mcu_pin_obj_t pin_PI01 = PIN(8, 1, NO_ADC);
const mcu_pin_obj_t pin_PI02 = PIN(8, 2, NO_ADC);
const mcu_pin_obj_t pin_PI03 = PIN(8, 3, NO_ADC);
const mcu_pin_obj_t pin_PI04 = PIN(8, 4, NO_ADC);
const mcu_pin_obj_t pin_PI05 = PIN(8, 5, NO_ADC);
const mcu_pin_obj_t pin_PI06 = PIN(8, 6, NO_ADC);
const mcu_pin_obj_t pin_PI07 = PIN(8, 7, NO_ADC);
const mcu_pin_obj_t pin_PI08 = PIN(8, 8, NO_ADC);
const mcu_pin_obj_t pin_PI09 = PIN(8, 9, NO_ADC);
const mcu_pin_obj_t pin_PI10 = PIN(8, 10, NO_ADC);
const mcu_pin_obj_t pin_PI11 = PIN(8, 11, NO_ADC);
const mcu_pin_obj_t pin_PI12 = PIN(8, 12, NO_ADC);
const mcu_pin_obj_t pin_PI13 = PIN(8, 13, NO_ADC);
const mcu_pin_obj_t pin_PI14 = PIN(8, 14, NO_ADC);
const mcu_pin_obj_t pin_PI15 = PIN(8, 15, NO_ADC);
const mcu_pin_obj_t pin_PJ00 = PIN(9, 0, NO_ADC);
const mcu_pin_obj_t pin_PJ01 = PIN(9, 1, NO_ADC);
const mcu_pin_obj_t pin_PJ02 = PIN(9, 2, NO_ADC);
const mcu_pin_obj_t pin_PJ03 = PIN(9, 3, NO_ADC);
const mcu_pin_obj_t pin_PJ04 = PIN(9, 4, NO_ADC);
const mcu_pin_obj_t pin_PJ05 = PIN(9, 5, NO_ADC);
const mcu_pin_obj_t pin_PJ06 = PIN(9, 6, NO_ADC);
const mcu_pin_obj_t pin_PJ07 = PIN(9, 7, NO_ADC);
const mcu_pin_obj_t pin_PJ08 = PIN(9, 8, NO_ADC);
const mcu_pin_obj_t pin_PJ09 = PIN(9, 9, NO_ADC);
const mcu_pin_obj_t pin_PJ10 = PIN(9, 10, NO_ADC);
const mcu_pin_obj_t pin_PJ11 = PIN(9, 11, NO_ADC);
const mcu_pin_obj_t pin_PJ12 = PIN(9, 12, NO_ADC);
const mcu_pin_obj_t pin_PJ13 = PIN(9, 13, NO_ADC);
const mcu_pin_obj_t pin_PJ14 = PIN(9, 14, NO_ADC);
const mcu_pin_obj_t pin_PJ15 = PIN(9, 15, NO_ADC);
const mcu_pin_obj_t pin_PK00 = PIN(10, 0, NO_ADC);
const mcu_pin_obj_t pin_PK01 = PIN(10, 1, NO_ADC);
const mcu_pin_obj_t pin_PK02 = PIN(10, 2, NO_ADC);
const mcu_pin_obj_t pin_PK03 = PIN(10, 3, NO_ADC);
const mcu_pin_obj_t pin_PK04 = PIN(10, 4, NO_ADC);
const mcu_pin_obj_t pin_PK05 = PIN(10, 5, NO_ADC);
const mcu_pin_obj_t pin_PK06 = PIN(10, 6, NO_ADC);
const mcu_pin_obj_t pin_PK07 = PIN(10, 7, NO_ADC);

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@ -0,0 +1,199 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PINS_H
#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PINS_H
extern const mcu_pin_obj_t pin_PA00;
extern const mcu_pin_obj_t pin_PA01;
extern const mcu_pin_obj_t pin_PA02;
extern const mcu_pin_obj_t pin_PA03;
extern const mcu_pin_obj_t pin_PA04;
extern const mcu_pin_obj_t pin_PA05;
extern const mcu_pin_obj_t pin_PA06;
extern const mcu_pin_obj_t pin_PA07;
extern const mcu_pin_obj_t pin_PA08;
extern const mcu_pin_obj_t pin_PA09;
extern const mcu_pin_obj_t pin_PA10;
extern const mcu_pin_obj_t pin_PA11;
extern const mcu_pin_obj_t pin_PA12;
extern const mcu_pin_obj_t pin_PA13;
extern const mcu_pin_obj_t pin_PA14;
extern const mcu_pin_obj_t pin_PA15;
extern const mcu_pin_obj_t pin_PB00;
extern const mcu_pin_obj_t pin_PB01;
extern const mcu_pin_obj_t pin_PB02;
extern const mcu_pin_obj_t pin_PB03;
extern const mcu_pin_obj_t pin_PB04;
extern const mcu_pin_obj_t pin_PB05;
extern const mcu_pin_obj_t pin_PB06;
extern const mcu_pin_obj_t pin_PB07;
extern const mcu_pin_obj_t pin_PB08;
extern const mcu_pin_obj_t pin_PB09;
extern const mcu_pin_obj_t pin_PB10;
extern const mcu_pin_obj_t pin_PB11;
extern const mcu_pin_obj_t pin_PB12;
extern const mcu_pin_obj_t pin_PB13;
extern const mcu_pin_obj_t pin_PB14;
extern const mcu_pin_obj_t pin_PB15;
extern const mcu_pin_obj_t pin_PC00;
extern const mcu_pin_obj_t pin_PC01;
extern const mcu_pin_obj_t pin_PC02;
extern const mcu_pin_obj_t pin_PC03;
extern const mcu_pin_obj_t pin_PC04;
extern const mcu_pin_obj_t pin_PC05;
extern const mcu_pin_obj_t pin_PC06;
extern const mcu_pin_obj_t pin_PC07;
extern const mcu_pin_obj_t pin_PC08;
extern const mcu_pin_obj_t pin_PC09;
extern const mcu_pin_obj_t pin_PC10;
extern const mcu_pin_obj_t pin_PC11;
extern const mcu_pin_obj_t pin_PC12;
extern const mcu_pin_obj_t pin_PC13;
extern const mcu_pin_obj_t pin_PC14;
extern const mcu_pin_obj_t pin_PC15;
extern const mcu_pin_obj_t pin_PD00;
extern const mcu_pin_obj_t pin_PD01;
extern const mcu_pin_obj_t pin_PD02;
extern const mcu_pin_obj_t pin_PD03;
extern const mcu_pin_obj_t pin_PD04;
extern const mcu_pin_obj_t pin_PD05;
extern const mcu_pin_obj_t pin_PD06;
extern const mcu_pin_obj_t pin_PD07;
extern const mcu_pin_obj_t pin_PD08;
extern const mcu_pin_obj_t pin_PD09;
extern const mcu_pin_obj_t pin_PD10;
extern const mcu_pin_obj_t pin_PD11;
extern const mcu_pin_obj_t pin_PD12;
extern const mcu_pin_obj_t pin_PD13;
extern const mcu_pin_obj_t pin_PD14;
extern const mcu_pin_obj_t pin_PD15;
extern const mcu_pin_obj_t pin_PE00;
extern const mcu_pin_obj_t pin_PE01;
extern const mcu_pin_obj_t pin_PE02;
extern const mcu_pin_obj_t pin_PE03;
extern const mcu_pin_obj_t pin_PE04;
extern const mcu_pin_obj_t pin_PE05;
extern const mcu_pin_obj_t pin_PE06;
extern const mcu_pin_obj_t pin_PE07;
extern const mcu_pin_obj_t pin_PE08;
extern const mcu_pin_obj_t pin_PE09;
extern const mcu_pin_obj_t pin_PE10;
extern const mcu_pin_obj_t pin_PE11;
extern const mcu_pin_obj_t pin_PE12;
extern const mcu_pin_obj_t pin_PE13;
extern const mcu_pin_obj_t pin_PE14;
extern const mcu_pin_obj_t pin_PE15;
extern const mcu_pin_obj_t pin_PF00;
extern const mcu_pin_obj_t pin_PF01;
extern const mcu_pin_obj_t pin_PF02;
extern const mcu_pin_obj_t pin_PF03;
extern const mcu_pin_obj_t pin_PF04;
extern const mcu_pin_obj_t pin_PF05;
extern const mcu_pin_obj_t pin_PF06;
extern const mcu_pin_obj_t pin_PF07;
extern const mcu_pin_obj_t pin_PF08;
extern const mcu_pin_obj_t pin_PF09;
extern const mcu_pin_obj_t pin_PF10;
extern const mcu_pin_obj_t pin_PF11;
extern const mcu_pin_obj_t pin_PF12;
extern const mcu_pin_obj_t pin_PF13;
extern const mcu_pin_obj_t pin_PF14;
extern const mcu_pin_obj_t pin_PF15;
extern const mcu_pin_obj_t pin_PG00;
extern const mcu_pin_obj_t pin_PG01;
extern const mcu_pin_obj_t pin_PG02;
extern const mcu_pin_obj_t pin_PG03;
extern const mcu_pin_obj_t pin_PG04;
extern const mcu_pin_obj_t pin_PG05;
extern const mcu_pin_obj_t pin_PG06;
extern const mcu_pin_obj_t pin_PG07;
extern const mcu_pin_obj_t pin_PG08;
extern const mcu_pin_obj_t pin_PG09;
extern const mcu_pin_obj_t pin_PG10;
extern const mcu_pin_obj_t pin_PG11;
extern const mcu_pin_obj_t pin_PG12;
extern const mcu_pin_obj_t pin_PG13;
extern const mcu_pin_obj_t pin_PG14;
extern const mcu_pin_obj_t pin_PG15;
extern const mcu_pin_obj_t pin_PH00;
extern const mcu_pin_obj_t pin_PH01;
extern const mcu_pin_obj_t pin_PH02;
extern const mcu_pin_obj_t pin_PH03;
extern const mcu_pin_obj_t pin_PH04;
extern const mcu_pin_obj_t pin_PH05;
extern const mcu_pin_obj_t pin_PH06;
extern const mcu_pin_obj_t pin_PH07;
extern const mcu_pin_obj_t pin_PH08;
extern const mcu_pin_obj_t pin_PH09;
extern const mcu_pin_obj_t pin_PH10;
extern const mcu_pin_obj_t pin_PH11;
extern const mcu_pin_obj_t pin_PH12;
extern const mcu_pin_obj_t pin_PH13;
extern const mcu_pin_obj_t pin_PH14;
extern const mcu_pin_obj_t pin_PH15;
extern const mcu_pin_obj_t pin_PI00;
extern const mcu_pin_obj_t pin_PI01;
extern const mcu_pin_obj_t pin_PI02;
extern const mcu_pin_obj_t pin_PI03;
extern const mcu_pin_obj_t pin_PI04;
extern const mcu_pin_obj_t pin_PI05;
extern const mcu_pin_obj_t pin_PI06;
extern const mcu_pin_obj_t pin_PI07;
extern const mcu_pin_obj_t pin_PI08;
extern const mcu_pin_obj_t pin_PI09;
extern const mcu_pin_obj_t pin_PI10;
extern const mcu_pin_obj_t pin_PI11;
extern const mcu_pin_obj_t pin_PI12;
extern const mcu_pin_obj_t pin_PI13;
extern const mcu_pin_obj_t pin_PI14;
extern const mcu_pin_obj_t pin_PI15;
extern const mcu_pin_obj_t pin_PJ00;
extern const mcu_pin_obj_t pin_PJ01;
extern const mcu_pin_obj_t pin_PJ02;
extern const mcu_pin_obj_t pin_PJ03;
extern const mcu_pin_obj_t pin_PJ04;
extern const mcu_pin_obj_t pin_PJ05;
extern const mcu_pin_obj_t pin_PJ06;
extern const mcu_pin_obj_t pin_PJ07;
extern const mcu_pin_obj_t pin_PJ08;
extern const mcu_pin_obj_t pin_PJ09;
extern const mcu_pin_obj_t pin_PJ10;
extern const mcu_pin_obj_t pin_PJ11;
extern const mcu_pin_obj_t pin_PJ12;
extern const mcu_pin_obj_t pin_PJ13;
extern const mcu_pin_obj_t pin_PJ14;
extern const mcu_pin_obj_t pin_PJ15;
extern const mcu_pin_obj_t pin_PK00;
extern const mcu_pin_obj_t pin_PK01;
extern const mcu_pin_obj_t pin_PK02;
extern const mcu_pin_obj_t pin_PK03;
extern const mcu_pin_obj_t pin_PK04;
extern const mcu_pin_obj_t pin_PK05;
extern const mcu_pin_obj_t pin_PK06;
extern const mcu_pin_obj_t pin_PK07;
#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PINS_H

56
ports/stm/supervisor/internal_flash.c
View File

@ -49,27 +49,47 @@ typedef struct {
#if defined(STM32F4)
STATIC const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x04000, 4 },
{ 0x08010000, 0x10000, 1 },
{ 0x08020000, 0x20000, 3 },
#if defined(FLASH_SECTOR_8)
{ 0x08080000, 0x20000, 4 },
#endif
#if defined(FLASH_SECTOR_12)
{ 0x08100000, 0x04000, 4 },
{ 0x08110000, 0x10000, 1 },
{ 0x08120000, 0x20000, 7 },
#endif
};
STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4)));
STATIC const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x04000, 4 },
{ 0x08010000, 0x10000, 1 },
{ 0x08020000, 0x20000, 3 },
#if defined(FLASH_SECTOR_8)
{ 0x08080000, 0x20000, 4 },
#endif
#if defined(FLASH_SECTOR_12)
{ 0x08100000, 0x04000, 4 },
{ 0x08110000, 0x10000, 1 },
{ 0x08120000, 0x20000, 7 },
#endif
};
STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4)));
#elif defined(STM32F7)
// FLASH_FLAG_PGSERR (Programming Sequence Error) was renamed to
// FLASH_FLAG_ERSERR (Erasing Sequence Error) in STM32F7
#define FLASH_FLAG_PGSERR FLASH_FLAG_ERSERR
#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx)
static const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x04000, 4 },
{ 0x08010000, 0x10000, 1 },
{ 0x08020000, 0x20000, 3 },
};
STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4)));
#else
static const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x08000, 4 },
{ 0x08020000, 0x20000, 1 },
{ 0x08040000, 0x40000, 3 },
};
STATIC uint8_t _flash_cache[0x8000] __attribute__((aligned(4)));
#endif
#elif defined(STM32H7)
STATIC const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x20000, 16 },
};
STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4)));
STATIC const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x20000, 16 },
};
STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4)));
#else
#error Unsupported processor

6
ports/stm/supervisor/internal_flash.h
View File

@ -66,6 +66,12 @@
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
#endif
#ifdef STM32F767xx
#define STM32_FLASH_SIZE 0x200000 //2MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 //96KiB
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08008000
#endif
#ifdef STM32H743xx
#define STM32_FLASH_SIZE 0x200000 //2MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x20000 //128KiB

5
ports/stm/supervisor/usb.c
View File

@ -80,7 +80,7 @@ void init_usb_hardware(void) {
GPIO_InitStruct.Pull = GPIO_NOPULL;
#if defined(STM32H7)
GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS;
#elif defined(STM32F4)
#elif defined(STM32F4) || defined(STM32F7)
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
#else
#error Unsupported processor
@ -105,7 +105,7 @@ void init_usb_hardware(void) {
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
#if defined(STM32H7)
GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS;
#elif defined(STM32F4)
#elif defined(STM32F4) || defined(STM32F7)
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
#else
#error Unsupported processor
@ -128,7 +128,6 @@ void init_usb_hardware(void) {
__HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
#else
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_DISABLE();
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
#endif

247
ports/stm/system_stm32f7xx.c Normal file
View File

@ -0,0 +1,247 @@
/**
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f7xx_system
* @{
*/
/** @addtogroup STM32F7xx_System_Private_Includes
* @{
*/
#include "stm32f7xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Configure the Vector Table location add offset address ------------------*/
#if !(BOARD_VTOR_DEFER) //only set VTOR if the bootloader hasn't already
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
ports/stm/tools/parse_af_csv.py
View File

@ -102,7 +102,7 @@ with open(sys.argv[1]) as csv_file:
for i in range(len(todo)):
ins = (todo[i][0]).lower() + '_' + (todo[i][1]).lower() + '_'
# const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4] = {
print("const mcu_" + ins + "obj_t mcu_" + ins + "list[" + str(len(outlist[i])) + "] = {")
print("const mcu_periph_obj_t mcu_" + ins + "list[" + str(len(outlist[i])) + "] = {")
for row in outlist[i]:
print(" PERIPH(" + row[0] + ", " + str(row[1]) + ", &pin_" + row[2] + "),")
print("};")

137
ports/stm/tools/pins.csv Normal file
View File

@ -0,0 +1,137 @@
A0,PA3
A1,PC0
A2,PC3
A3,PF3
A4,PF5
A5,PF10
A6,PB1
A7,PC2
A8,PF4
D0,PG9
D1,PG14
D2,PF15
D3,PE13
D4,PF14
D5,PE11
D6,PE9
D7,PF13
D8,PF12
D9,PD15
D10,PD14
D11,PA7
D12,PA6
D13,PA5
D14,PB9
D15,PB8
D16,PC6
D17,PB15
D18,PB13
D19,PB12
D20,PA15
D21,PC7
D22,PB5
D23,PB3
D24,PA4
D25,PB4
D26,PB6
D27,PB2
D28,PD13
D29,PD12
D30,PD11
D31,PE2
D32,PA0
D33,PB0
D34,PE0
D35,PB11
D36,PB10
D37,PE15
D38,PE14
D39,PE12
D40,PE10
D41,PE7
D42,PE8
D43,PC8
D44,PC9
D45,PC10
D46,PC11
D47,PC12
D48,PD2
D49,PG2
D50,PG3
D51,PD7
D52,PD6
D53,PD5
D54,PD4
D55,PD3
D56,PE2
D57,PE4
D58,PE5
D59,PE6
D60,PE3
D61,PF8
D62,PF7
D63,PF9
D64,PG1
D65,PG0
D66,PD1
D67,PD0
D68,PF0
D69,PF1
D70,PF2
D71,PA7
DAC1,PA4
DAC2,PA5
LED1,PB0
LED2,PB7
LED3,PB14
SW,PC13
SD_D0,PC8
SD_D1,PC9
SD_D2,PC10
SD_D3,PC11
SD_CMD,PD2
SD_CK,PC12
SD_SW,PG2
OTG_FS_POWER,PG6
OTG_FS_OVER_CURRENT,PG7
USB_VBUS,PA9
USB_ID,PA10
USB_DM,PA11
USB_DP,PA12
UART2_TX,PD5
UART2_RX,PD6
UART2_RTS,PD4
UART2_CTS,PD3
VCP_TX,PD8
VCP_RX,PD9
UART3_TX,PD8
UART3_RX,PD9
UART5_TX,PB6
UART5_RX,PB12
UART6_TX,PC6
UART6_RX,PC7
UART7_TX,PF7
UART7_RX,PF6
UART8_TX,PE1
UART8_RX,PE0
SPI3_NSS,PA4
SPI3_SCK,PB3
SPI3_MISO,PB4
SPI3_MOSI,PB5
I2C1_SDA,PB9
I2C1_SCL,PB8
I2C2_SDA,PF0
I2C2_SCL,PF1
I2C4_SCL,PF14
I2C4_SDA,PF15
ETH_MDC,PC1
ETH_MDIO,PA2
ETH_RMII_REF_CLK,PA1
ETH_RMII_CRS_DV,PA7
ETH_RMII_RXD0,PC4
ETH_RMII_RXD1,PC5
ETH_RMII_TX_EN,PG11
ETH_RMII_TXD0,PG13
ETH_RMII_TXD1,PB13
SWDIO,PA13
SWDCLK,PA14
1 A0 PA3
2 A1 PC0
3 A2 PC3
4 A3 PF3
5 A4 PF5
6 A5 PF10
7 A6 PB1
8 A7 PC2
9 A8 PF4
10 D0 PG9
11 D1 PG14
12 D2 PF15
13 D3 PE13
14 D4 PF14
15 D5 PE11
16 D6 PE9
17 D7 PF13
18 D8 PF12
19 D9 PD15
20 D10 PD14
21 D11 PA7
22 D12 PA6
23 D13 PA5
24 D14 PB9
25 D15 PB8
26 D16 PC6
27 D17 PB15
28 D18 PB13
29 D19 PB12
30 D20 PA15
31 D21 PC7
32 D22 PB5
33 D23 PB3
34 D24 PA4
35 D25 PB4
36 D26 PB6
37 D27 PB2
38 D28 PD13
39 D29 PD12
40 D30 PD11
41 D31 PE2
42 D32 PA0
43 D33 PB0
44 D34 PE0
45 D35 PB11
46 D36 PB10
47 D37 PE15
48 D38 PE14
49 D39 PE12
50 D40 PE10
51 D41 PE7
52 D42 PE8
53 D43 PC8
54 D44 PC9
55 D45 PC10
56 D46 PC11
57 D47 PC12
58 D48 PD2
59 D49 PG2
60 D50 PG3
61 D51 PD7
62 D52 PD6
63 D53 PD5
64 D54 PD4
65 D55 PD3
66 D56 PE2
67 D57 PE4
68 D58 PE5
69 D59 PE6
70 D60 PE3
71 D61 PF8
72 D62 PF7
73 D63 PF9
74 D64 PG1
75 D65 PG0
76 D66 PD1
77 D67 PD0
78 D68 PF0
79 D69 PF1
80 D70 PF2
81 D71 PA7
82 DAC1 PA4
83 DAC2 PA5
84 LED1 PB0
85 LED2 PB7
86 LED3 PB14
87 SW PC13
88 SD_D0 PC8
89 SD_D1 PC9
90 SD_D2 PC10
91 SD_D3 PC11
92 SD_CMD PD2
93 SD_CK PC12
94 SD_SW PG2
95 OTG_FS_POWER PG6
96 OTG_FS_OVER_CURRENT PG7
97 USB_VBUS PA9
98 USB_ID PA10
99 USB_DM PA11
100 USB_DP PA12
101 UART2_TX PD5
102 UART2_RX PD6
103 UART2_RTS PD4
104 UART2_CTS PD3
105 VCP_TX PD8
106 VCP_RX PD9
107 UART3_TX PD8
108 UART3_RX PD9
109 UART5_TX PB6
110 UART5_RX PB12
111 UART6_TX PC6
112 UART6_RX PC7
113 UART7_TX PF7
114 UART7_RX PF6
115 UART8_TX PE1
116 UART8_RX PE0
117 SPI3_NSS PA4
118 SPI3_SCK PB3
119 SPI3_MISO PB4
120 SPI3_MOSI PB5
121 I2C1_SDA PB9
122 I2C1_SCL PB8
123 I2C2_SDA PF0
124 I2C2_SCL PF1
125 I2C4_SCL PF14
126 I2C4_SDA PF15
127 ETH_MDC PC1
128 ETH_MDIO PA2
129 ETH_RMII_REF_CLK PA1
130 ETH_RMII_CRS_DV PA7
131 ETH_RMII_RXD0 PC4
132 ETH_RMII_RXD1 PC5
133 ETH_RMII_TX_EN PG11
134 ETH_RMII_TXD0 PG13
135 ETH_RMII_TXD1 PB13
136 SWDIO PA13
137 SWDCLK PA14

168
ports/stm/tools/stm32f767_af.csv Normal file
View File

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PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT,ADC123_IN0
PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,LCD_R2,EVENTOUT,ADC123_IN1
PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,MDIOS_MDIO,,LCD_R1,EVENTOUT,ADC123_IN2
PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,LCD_B2,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT,ADC123_IN3
PortA,PA4,,,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,SPI6_NSS,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT,ADC12_IN4
PortA,PA5,,TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,SPI6_SCK,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT,ADC12_IN5
PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,SPI6_MISO,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,LCD_G2,EVENTOUT,ADC12_IN6
PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,SPI6_MOSI,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT,ADC12_IN7
PortA,PA8,MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,LCD_B3,LCD_R6,EVENTOUT,
PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,LCD_R5,EVENTOUT,
PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,LCD_B4,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,LCD_B1,EVENTOUT,
PortA,PA11,,TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT,
PortA,PA12,,TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT,
PortA,PA13,JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT,
PortA,PA14,JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT,
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,SPI6_NSS,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT,
PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT,ADC12_IN8
PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATAIN1,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT,ADC12_IN9
PortB,PB2,,,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT,
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,SDMMC2_D2,CAN3_RX,UART7_RX,,,EVENTOUT,
PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,SDMMC2_D3,CAN3_TX,UART7_TX,,,EVENTOUT,
PortB,PB5,,UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT,
PortB,PB6,,UART5_TX,TIM4_CH1,HDMI_CEC,I2C1_SCL,,DFSDM1_DATAIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT,
PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2C4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT,
PortB,PB8,,I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,SDMMC2_D4,ETH_MII_TXD3,SDMMC1_D4,DCMI_D6,LCD_B6,EVENTOUT,
PortB,PB9,,I2C4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATAIN7,UART5_TX,,CAN1_TX,SDMMC2_D5,I2C4_SMBA,SDMMC1_D5,DCMI_D7,LCD_B7,EVENTOUT,
PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATAIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT,
PortB,PB11,,TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DSI_TE,LCD_G5,EVENTOUT,
PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATAIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT,
PortB,PB13,,TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT,
PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATAIN2,USART3_RTS,UART4_RTS,TIM12_CH1,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT,
PortB,PB15,RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT,
PortC,PC0,,,,DFSDM1_CKIN0,,,DFSDM1_DATAIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT,ADC123_IN10
PortC,PC1,TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,ETH_MDC,MDIOS_MDC,,,EVENTOUT,ADC123_IN11
PortC,PC2,,,,DFSDM1_CKIN1,,SPI2_MISO,DFSDM1_CKOUT,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT,ADC123_IN12
PortC,PC3,,,,DFSDM1_DATAIN1,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT,ADC123_IN13
PortC,PC4,,,,DFSDM1_CKIN2,,I2S1_MCK,,,SPDIFRX_IN2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT,ADC12_IN14
PortC,PC5,,,,DFSDM1_DATAIN2,,,,,SPDIFRX_IN3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT,ADC12_IN15
PortC,PC6,,,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,SDMMC2_D6,,SDMMC1_D6,DCMI_D0,LCD_HSYNC,EVENTOUT,
PortC,PC7,,,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,SDMMC2_D7,,SDMMC1_D7,DCMI_D1,LCD_G6,EVENTOUT,
PortC,PC8,TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC1_D0,DCMI_D2,,EVENTOUT,
PortC,PC9,MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,,SDMMC1_D1,DCMI_D3,LCD_B2,EVENTOUT,
PortC,PC10,,,,DFSDM1_CKIN5,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC1_D2,DCMI_D8,LCD_R2,EVENTOUT,
PortC,PC11,,,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC1_D3,DCMI_D4,,EVENTOUT,
PortC,PC12,TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC1_CK,DCMI_D9,,EVENTOUT,
PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD0,,,,DFSDM1_CKIN6,,,DFSDM1_DATAIN7,,UART4_RX,CAN1_RX,,,FMC_D2,,,EVENTOUT,
PortD,PD1,,,,DFSDM1_DATAIN6,,,DFSDM1_CKIN7,,UART4_TX,CAN1_TX,,,FMC_D3,,,EVENTOUT,
PortD,PD2,TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC1_CMD,DCMI_D11,,EVENTOUT,
PortD,PD3,,,,DFSDM1_CKOUT,,SPI2_SCK/I2S2_CK,DFSDM1_DATAIN0,USART2_CTS,,,,,FMC_CLK,DCMI_D5,LCD_G7,EVENTOUT,
PortD,PD4,,,,,,,DFSDM1_CKIN0,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT,
PortD,PD5,,,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT,
PortD,PD6,,,,DFSDM1_CKIN4,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,DFSDM1_DATAIN1,SDMMC2_CK,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT,
PortD,PD7,,,,DFSDM1_DATAIN4,,SPI1_MOSI/I2S1_SD,DFSDM1_CKIN1,USART2_CK,SPDIFRX_IN0,,,SDMMC2_CMD,FMC_NE1,,,EVENTOUT,
PortD,PD8,,,,DFSDM1_CKIN3,,,,USART3_TX,SPDIFRX_IN1,,,,FMC_D13,,,EVENTOUT,
PortD,PD9,,,,DFSDM1_DATAIN3,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT,
PortD,PD10,,,,DFSDM1_CKOUT,,,,USART3_CK,,,,,FMC_D15,,LCD_B3,EVENTOUT,
PortD,PD11,,,,,I2C4_SMBA,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT,
PortD,PD12,,,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT,
PortD,PD13,,,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT,
PortD,PD14,,,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT,
PortD,PD15,,,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT,
PortE,PE0,,,TIM4_ETR,LPTIM1_ETR,,,,,UART8_RX,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT,
PortE,PE1,,,,LPTIM1_IN2,,,,,UART8_TX,,,,FMC_NBL1,DCMI_D3,,EVENTOUT,
PortE,PE2,TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,QUADSPI_BK1_IO2,,ETH_MII_TXD3,FMC_A23,,,EVENTOUT,
PortE,PE3,TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT,
PortE,PE4,TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,DFSDM1_DATAIN3,,FMC_A20,DCMI_D4,LCD_B0,EVENTOUT,
PortE,PE5,TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,DFSDM1_CKIN3,,FMC_A21,DCMI_D6,LCD_G0,EVENTOUT,
PortE,PE6,TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,LCD_G1,EVENTOUT,
PortE,PE7,,TIM1_ETR,,,,,DFSDM1_DATAIN2,,UART7_RX,,QUADSPI_BK2_IO0,,FMC_D4,,,EVENTOUT,
PortE,PE8,,TIM1_CH1N,,,,,DFSDM1_CKIN2,,UART7_TX,,QUADSPI_BK2_IO1,,FMC_D5,,,EVENTOUT,
PortE,PE9,,TIM1_CH1,,,,,DFSDM1_CKOUT,,UART7_RTS,,QUADSPI_BK2_IO2,,FMC_D6,,,EVENTOUT,
PortE,PE10,,TIM1_CH2N,,,,,DFSDM1_DATAIN4,,UART7_CTS,,QUADSPI_BK2_IO3,,FMC_D7,,,EVENTOUT,
PortE,PE11,,TIM1_CH2,,,,SPI4_NSS,DFSDM1_CKIN4,,,,SAI2_SD_B,,FMC_D8,,LCD_G3,EVENTOUT,
PortE,PE12,,TIM1_CH3N,,,,SPI4_SCK,DFSDM1_DATAIN5,,,,SAI2_SCK_B,,FMC_D9,,LCD_B4,EVENTOUT,
PortE,PE13,,TIM1_CH3,,,,SPI4_MISO,DFSDM1_CKIN5,,,,SAI2_FS_B,,FMC_D10,,LCD_DE,EVENTOUT,
PortE,PE14,,TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,LCD_CLK,EVENTOUT,
PortE,PE15,,TIM1_BKIN,,,,,,,,,,,FMC_D12,,LCD_R7,EVENTOUT,
PortF,PF0,,,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT,
PortF,PF1,,,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT,
PortF,PF2,,,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT,
PortF,PF3,,,,,,,,,,,,,FMC_A3,,,EVENTOUT,ADC3_IN9
PortF,PF4,,,,,,,,,,,,,FMC_A4,,,EVENTOUT,ADC3_IN14
PortF,PF5,,,,,,,,,,,,,FMC_A5,,,EVENTOUT,ADC3_IN15
PortF,PF6,,,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_RX,QUADSPI_BK1_IO3,,,,,,EVENTOUT,ADC3_IN4
PortF,PF7,,,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_TX,QUADSPI_BK1_IO2,,,,,,EVENTOUT,ADC3_IN5
PortF,PF8,,,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,QUADSPI_BK1_IO0,,,,,EVENTOUT,ADC3_IN6
PortF,PF9,,,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,QUADSPI_BK1_IO1,,,,,EVENTOUT,ADC3_IN7
PortF,PF10,,,,,,,,,,QUADSPI_CLK,,,,DCMI_D11,LCD_DE,EVENTOUT,ADC3_IN8
PortF,PF11,,,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT,
PortF,PF12,,,,,,,,,,,,,FMC_A6,,,EVENTOUT,
PortF,PF13,,,,,I2C4_SMBA,,DFSDM1_DATAIN6,,,,,,FMC_A7,,,EVENTOUT,
PortF,PF14,,,,,I2C4_SCL,,DFSDM1_CKIN6,,,,,,FMC_A8,,,EVENTOUT,
PortF,PF15,,,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT,
PortG,PG0,,,,,,,,,,,,,FMC_A10,,,EVENTOUT,
PortG,PG1,,,,,,,,,,,,,FMC_A11,,,EVENTOUT,
PortG,PG2,,,,,,,,,,,,,FMC_A12,,,EVENTOUT,
PortG,PG3,,,,,,,,,,,,,FMC_A13,,,EVENTOUT,
PortG,PG4,,,,,,,,,,,,,FMC_A14/FMC_BA0,,,EVENTOUT,
PortG,PG5,,,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT,
PortG,PG6,,,,,,,,,,,,,FMC_NE3,DCMI_D12,LCD_R7,EVENTOUT,
PortG,PG7,,,,,,,SAI1_MCLK_A,,USART6_CK,,,,FMC_INT,DCMI_D13,LCD_CLK,EVENTOUT,
PortG,PG8,,,,,,SPI6_NSS,,SPDIFRX_IN2,USART6_RTS,,,ETH_PPS_OUT,FMC_SDCLK,,LCD_G7,EVENTOUT,
PortG,PG9,,,,,,SPI1_MISO,,SPDIFRX_IN3,USART6_RX,QUADSPI_BK2_IO2,SAI2_FS_B,SDMMC2_D0,FMC_NE2/FMC_NCE,DCMI_VSYNC,,EVENTOUT,
PortG,PG10,,,,,,SPI1_NSS/I2S1_WS,,,,LCD_G3,SAI2_SD_B,SDMMC2_D1,FMC_NE3,DCMI_D2,LCD_B2,EVENTOUT,
PortG,PG11,,,,,,SPI1_SCK/I2S1_CK,,SPDIFRX_IN0,,,SDMMC2_D2,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DCMI_D3,LCD_B3,EVENTOUT,
PortG,PG12,,,,LPTIM1_IN1,,SPI6_MISO,,SPDIFRX_IN1,USART6_RTS,LCD_B4,,SDMMC2_D3,FMC_NE4,,LCD_B1,EVENTOUT,
PortG,PG13,TRACED0,,,LPTIM1_OUT,,SPI6_SCK,,,USART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FMC_A24,,LCD_R0,EVENTOUT,
PortG,PG14,TRACED1,,,LPTIM1_ETR,,SPI6_MOSI,,,USART6_TX,QUADSPI_BK2_IO3,,ETH_MII_TXD1/ETH_RMII_TXD1,FMC_A25,,LCD_B0,EVENTOUT,
PortG,PG15,,,,,,,,,USART6_CTS,,,,FMC_SDNCAS,DCMI_D13,,EVENTOUT,
PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,
PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT,
PortH,PH2,,,,LPTIM1_IN2,,,,,,QUADSPI_BK2_IO0,SAI2_SCK_B,ETH_MII_CRS,FMC_SDCKE0,,LCD_R0,EVENTOUT,
PortH,PH3,,,,,,,,,,QUADSPI_BK2_IO1,SAI2_MCK_B,ETH_MII_COL,FMC_SDNE0,,LCD_R1,EVENTOUT,
PortH,PH4,,,,,I2C2_SCL,,,,,LCD_G5,OTG_HS_ULPI_NXT,,,,LCD_G4,EVENTOUT,
PortH,PH5,,,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT,
PortH,PH6,,,,,I2C2_SMBA,SPI5_SCK,,,,TIM12_CH1,,ETH_MII_RXD2,FMC_SDNE1,DCMI_D8,,EVENTOUT,
PortH,PH7,,,,,I2C3_SCL,SPI5_MISO,,,,,,ETH_MII_RXD3,FMC_SDCKE1,DCMI_D9,,EVENTOUT,
PortH,PH8,,,,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC,LCD_R2,EVENTOUT,
PortH,PH9,,,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,DCMI_D0,LCD_R3,EVENTOUT,
PortH,PH10,,,TIM5_CH1,,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1,LCD_R4,EVENTOUT,
PortH,PH11,,,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2,LCD_R5,EVENTOUT,
PortH,PH12,,,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3,LCD_R6,EVENTOUT,
PortH,PH13,,,,TIM8_CH1N,,,,,UART4_TX,CAN1_TX,,,FMC_D21,,LCD_G2,EVENTOUT,
PortH,PH14,,,,TIM8_CH2N,,,,,UART4_RX,CAN1_RX,,,FMC_D22,DCMI_D4,LCD_G3,EVENTOUT,
PortH,PH15,,,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11,LCD_G4,EVENTOUT,
PortI,PI0,,,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,LCD_G5,EVENTOUT,
PortI,PI1,,,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,LCD_G6,EVENTOUT,
PortI,PI2,,,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,DCMI_D9,LCD_G7,EVENTOUT,
PortI,PI3,,,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT,
PortI,PI4,,,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,LCD_B4,EVENTOUT,
PortI,PI5,,,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,LCD_B5,EVENTOUT,
PortI,PI6,,,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,LCD_B6,EVENTOUT,
PortI,PI7,,,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,LCD_B7,EVENTOUT,
PortI,PI8,,,,,,,,,,,,,,,,EVENTOUT,
PortI,PI9,,,,,,,,,UART4_RX,CAN1_RX,,,FMC_D30,,LCD_VSYNC,EVENTOUT,
PortI,PI10,,,,,,,,,,,,ETH_MII_RX_ER,FMC_D31,,LCD_HSYNC,EVENTOUT,
PortI,PI11,,,,,,,,,,LCD_G6,OTG_HS_ULPI_DIR,,,,,EVENTOUT,
PortI,PI12,,,,,,,,,,,,,,,LCD_HSYNC,EVENTOUT,
PortI,PI13,,,,,,,,,,,,,,,LCD_VSYNC,EVENTOUT,
PortI,PI14,,,,,,,,,,,,,,,LCD_CLK,EVENTOUT,
PortI,PI15,,,,,,,,,,LCD_G2,,,,,LCD_R0,EVENTOUT,
PortJ,PJ0,,,,,,,,,,LCD_R7,,,,,LCD_R1,EVENTOUT,
PortJ,PJ1,,,,,,,,,,,,,,,LCD_R2,EVENTOUT,
PortJ,PJ2,,,,,,,,,,,,,,DSI_TE,LCD_R3,EVENTOUT,
PortJ,PJ3,,,,,,,,,,,,,,,LCD_R4,EVENTOUT,
PortJ,PJ4,,,,,,,,,,,,,,,LCD_R5,EVENTOUT,
PortJ,PJ5,,,,,,,,,,,,,,,LCD_R6,EVENTOUT,
PortJ,PJ6,,,,,,,,,,,,,,,LCD_R7,EVENTOUT,
PortJ,PJ7,,,,,,,,,,,,,,,LCD_G0,EVENTOUT,
PortJ,PJ8,,,,,,,,,,,,,,,LCD_G1,EVENTOUT,
PortJ,PJ9,,,,,,,,,,,,,,,LCD_G2,EVENTOUT,
PortJ,PJ10,,,,,,,,,,,,,,,LCD_G3,EVENTOUT,
PortJ,PJ11,,,,,,,,,,,,,,,LCD_G4,EVENTOUT,
PortJ,PJ12,,,,,,,,,,LCD_G3,,,,,LCD_B0,EVENTOUT,
PortJ,PJ13,,,,,,,,,,LCD_G4,,,,,LCD_B1,EVENTOUT,
PortJ,PJ14,,,,,,,,,,,,,,,LCD_B2,EVENTOUT,
PortJ,PJ15,,,,,,,,,,,,,,,LCD_B3,EVENTOUT,
PortK,PK0,,,,,,,,,,,,,,,LCD_G5,EVENTOUT,
PortK,PK1,,,,,,,,,,,,,,,LCD_G6,EVENTOUT,
PortK,PK2,,,,,,,,,,,,,,,LCD_G7,EVENTOUT,
PortK,PK3,,,,,,,,,,,,,,,LCD_B4,EVENTOUT,
PortK,PK4,,,,,,,,,,,,,,,LCD_B5,EVENTOUT,
PortK,PK5,,,,,,,,,,,,,,,LCD_B6,EVENTOUT,
PortK,PK6,,,,,,,,,,,,,,,LCD_B7,EVENTOUT,
PortK,PK7,,,,,,,,,,,,,,,LCD_DE,EVENTOUT,
1 PortA PA0 TIM2_CH1/TIM2_ETR TIM5_CH1 TIM8_ETR USART2_CTS UART4_TX SAI2_SD_B ETH_MII_CRS EVENTOUT ADC123_IN0
2 PortA PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX QUADSPI_BK1_IO3 SAI2_MCK_B ETH_MII_RX_CLK/ETH_RMII_REF_CLK LCD_R2 EVENTOUT ADC123_IN1
3 PortA PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX SAI2_SCK_B ETH_MDIO MDIOS_MDIO LCD_R1 EVENTOUT ADC123_IN2
4 PortA PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX LCD_B2 OTG_HS_ULPI_D0 ETH_MII_COL LCD_B5 EVENTOUT ADC123_IN3
5 PortA PA4 SPI1_NSS/I2S1_WS SPI3_NSS/I2S3_WS USART2_CK SPI6_NSS OTG_HS_SOF DCMI_HSYNC LCD_VSYNC EVENTOUT ADC12_IN4
6 PortA PA5 TIM2_CH1/TIM2_ETR TIM8_CH1N SPI1_SCK/I2S1_CK SPI6_SCK OTG_HS_ULPI_CK LCD_R4 EVENTOUT ADC12_IN5
7 PortA PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO SPI6_MISO TIM13_CH1 MDIOS_MDC DCMI_PIXCLK LCD_G2 EVENTOUT ADC12_IN6
8 PortA PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI/I2S1_SD SPI6_MOSI TIM14_CH1 ETH_MII_RX_DV/ETH_RMII_CRS_DV FMC_SDNWE EVENTOUT ADC12_IN7
9 PortA PA8 MCO1 TIM1_CH1 TIM8_BKIN2 I2C3_SCL USART1_CK OTG_FS_SOF CAN3_RX UART7_RX LCD_B3 LCD_R6 EVENTOUT
10 PortA PA9 TIM1_CH2 I2C3_SMBA SPI2_SCK/I2S2_CK USART1_TX DCMI_D0 LCD_R5 EVENTOUT
11 PortA PA10 TIM1_CH3 USART1_RX LCD_B4 OTG_FS_ID MDIOS_MDIO DCMI_D1 LCD_B1 EVENTOUT
12 PortA PA11 TIM1_CH4 SPI2_NSS/I2S2_WS UART4_RX USART1_CTS CAN1_RX OTG_FS_DM LCD_R4 EVENTOUT
13 PortA PA12 TIM1_ETR SPI2_SCK/I2S2_CK UART4_TX USART1_RTS SAI2_FS_B CAN1_TX OTG_FS_DP LCD_R5 EVENTOUT
14 PortA PA13 JTMS/SWDIO EVENTOUT
15 PortA PA14 JTCK/SWCLK EVENTOUT
16 PortA PA15 JTDI TIM2_CH1/TIM2_ETR HDMI_CEC SPI1_NSS/I2S1_WS SPI3_NSS/I2S3_WS SPI6_NSS UART4_RTS CAN3_TX UART7_TX EVENTOUT
17 PortB PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N DFSDM1_CKOUT UART4_CTS LCD_R3 OTG_HS_ULPI_D1 ETH_MII_RXD2 LCD_G1 EVENTOUT ADC12_IN8
18 PortB PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N DFSDM1_DATAIN1 LCD_R6 OTG_HS_ULPI_D2 ETH_MII_RXD3 LCD_G0 EVENTOUT ADC12_IN9
19 PortB PB2 SAI1_SD_A SPI3_MOSI/I2S3_SD QUADSPI_CLK DFSDM1_CKIN1 EVENTOUT
20 PortB PB3 JTDO/TRACESWO TIM2_CH2 SPI1_SCK/I2S1_CK SPI3_SCK/I2S3_CK SPI6_SCK SDMMC2_D2 CAN3_RX UART7_RX EVENTOUT
21 PortB PB4 NJTRST TIM3_CH1 SPI1_MISO SPI3_MISO SPI2_NSS/I2S2_WS SPI6_MISO SDMMC2_D3 CAN3_TX UART7_TX EVENTOUT
22 PortB PB5 UART5_RX TIM3_CH2 I2C1_SMBA SPI1_MOSI/I2S1_SD SPI3_MOSI/I2S3_SD SPI6_MOSI CAN2_RX OTG_HS_ULPI_D7 ETH_PPS_OUT FMC_SDCKE1 DCMI_D10 LCD_G7 EVENTOUT
23 PortB PB6 UART5_TX TIM4_CH1 HDMI_CEC I2C1_SCL DFSDM1_DATAIN5 USART1_TX CAN2_TX QUADSPI_BK1_NCS I2C4_SCL FMC_SDNE1 DCMI_D5 EVENTOUT
24 PortB PB7 TIM4_CH2 I2C1_SDA DFSDM1_CKIN5 USART1_RX I2C4_SDA FMC_NL DCMI_VSYNC EVENTOUT
25 PortB PB8 I2C4_SCL TIM4_CH3 TIM10_CH1 I2C1_SCL DFSDM1_CKIN7 UART5_RX CAN1_RX SDMMC2_D4 ETH_MII_TXD3 SDMMC1_D4 DCMI_D6 LCD_B6 EVENTOUT
26 PortB PB9 I2C4_SDA TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS/I2S2_WS DFSDM1_DATAIN7 UART5_TX CAN1_TX SDMMC2_D5 I2C4_SMBA SDMMC1_D5 DCMI_D7 LCD_B7 EVENTOUT
27 PortB PB10 TIM2_CH3 I2C2_SCL SPI2_SCK/I2S2_CK DFSDM1_DATAIN7 USART3_TX QUADSPI_BK1_NCS OTG_HS_ULPI_D3 ETH_MII_RX_ER LCD_G4 EVENTOUT
28 PortB PB11 TIM2_CH4 I2C2_SDA DFSDM1_CKIN7 USART3_RX OTG_HS_ULPI_D4 ETH_MII_TX_EN/ETH_RMII_TX_EN DSI_TE LCD_G5 EVENTOUT
29 PortB PB12 TIM1_BKIN I2C2_SMBA SPI2_NSS/I2S2_WS DFSDM1_DATAIN1 USART3_CK UART5_RX CAN2_RX OTG_HS_ULPI_D5 ETH_MII_TXD0/ETH_RMII_TXD0 OTG_HS_ID EVENTOUT
30 PortB PB13 TIM1_CH1N SPI2_SCK/I2S2_CK DFSDM1_CKIN1 USART3_CTS UART5_TX CAN2_TX OTG_HS_ULPI_D6 ETH_MII_TXD1/ETH_RMII_TXD1 EVENTOUT
31 PortB PB14 TIM1_CH2N TIM8_CH2N USART1_TX SPI2_MISO DFSDM1_DATAIN2 USART3_RTS UART4_RTS TIM12_CH1 SDMMC2_D0 OTG_HS_DM EVENTOUT
32 PortB PB15 RTC_REFIN TIM1_CH3N TIM8_CH3N USART1_RX SPI2_MOSI/I2S2_SD DFSDM1_CKIN2 UART4_CTS TIM12_CH2 SDMMC2_D1 OTG_HS_DP EVENTOUT
33 PortC PC0 DFSDM1_CKIN0 DFSDM1_DATAIN4 SAI2_FS_B OTG_HS_ULPI_STP FMC_SDNWE LCD_R5 EVENTOUT ADC123_IN10
34 PortC PC1 TRACED0 DFSDM1_DATAIN0 SPI2_MOSI/I2S2_SD SAI1_SD_A DFSDM1_CKIN4 ETH_MDC MDIOS_MDC EVENTOUT ADC123_IN11
35 PortC PC2 DFSDM1_CKIN1 SPI2_MISO DFSDM1_CKOUT OTG_HS_ULPI_DIR ETH_MII_TXD2 FMC_SDNE0 EVENTOUT ADC123_IN12
36 PortC PC3 DFSDM1_DATAIN1 SPI2_MOSI/I2S2_SD OTG_HS_ULPI_NXT ETH_MII_TX_CLK FMC_SDCKE0 EVENTOUT ADC123_IN13
37 PortC PC4 DFSDM1_CKIN2 I2S1_MCK SPDIFRX_IN2 ETH_MII_RXD0/ETH_RMII_RXD0 FMC_SDNE0 EVENTOUT ADC12_IN14
38 PortC PC5 DFSDM1_DATAIN2 SPDIFRX_IN3 ETH_MII_RXD1/ETH_RMII_RXD1 FMC_SDCKE0 EVENTOUT ADC12_IN15
39 PortC PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK DFSDM1_CKIN3 USART6_TX FMC_NWAIT SDMMC2_D6 SDMMC1_D6 DCMI_D0 LCD_HSYNC EVENTOUT
40 PortC PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK DFSDM1_DATAIN3 USART6_RX FMC_NE1 SDMMC2_D7 SDMMC1_D7 DCMI_D1 LCD_G6 EVENTOUT
41 PortC PC8 TRACED1 TIM3_CH3 TIM8_CH3 UART5_RTS USART6_CK FMC_NE2/FMC_NCE SDMMC1_D0 DCMI_D2 EVENTOUT
42 PortC PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN UART5_CTS QUADSPI_BK1_IO0 LCD_G3 SDMMC1_D1 DCMI_D3 LCD_B2 EVENTOUT
43 PortC PC10 DFSDM1_CKIN5 SPI3_SCK/I2S3_CK USART3_TX UART4_TX QUADSPI_BK1_IO1 SDMMC1_D2 DCMI_D8 LCD_R2 EVENTOUT
44 PortC PC11 DFSDM1_DATAIN5 SPI3_MISO USART3_RX UART4_RX QUADSPI_BK2_NCS SDMMC1_D3 DCMI_D4 EVENTOUT
45 PortC PC12 TRACED3 SPI3_MOSI/I2S3_SD USART3_CK UART5_TX SDMMC1_CK DCMI_D9 EVENTOUT
46 PortC PC13 EVENTOUT
47 PortC PC14 EVENTOUT
48 PortC PC15 EVENTOUT
49 PortD PD0 DFSDM1_CKIN6 DFSDM1_DATAIN7 UART4_RX CAN1_RX FMC_D2 EVENTOUT
50 PortD PD1 DFSDM1_DATAIN6 DFSDM1_CKIN7 UART4_TX CAN1_TX FMC_D3 EVENTOUT
51 PortD PD2 TRACED2 TIM3_ETR UART5_RX SDMMC1_CMD DCMI_D11 EVENTOUT
52 PortD PD3 DFSDM1_CKOUT SPI2_SCK/I2S2_CK DFSDM1_DATAIN0 USART2_CTS FMC_CLK DCMI_D5 LCD_G7 EVENTOUT
53 PortD PD4 DFSDM1_CKIN0 USART2_RTS FMC_NOE EVENTOUT
54 PortD PD5 USART2_TX FMC_NWE EVENTOUT
55 PortD PD6 DFSDM1_CKIN4 SPI3_MOSI/I2S3_SD SAI1_SD_A USART2_RX DFSDM1_DATAIN1 SDMMC2_CK FMC_NWAIT DCMI_D10 LCD_B2 EVENTOUT
56 PortD PD7 DFSDM1_DATAIN4 SPI1_MOSI/I2S1_SD DFSDM1_CKIN1 USART2_CK SPDIFRX_IN0 SDMMC2_CMD FMC_NE1 EVENTOUT
57 PortD PD8 DFSDM1_CKIN3 USART3_TX SPDIFRX_IN1 FMC_D13 EVENTOUT
58 PortD PD9 DFSDM1_DATAIN3 USART3_RX FMC_D14 EVENTOUT
59 PortD PD10 DFSDM1_CKOUT USART3_CK FMC_D15 LCD_B3 EVENTOUT
60 PortD PD11 I2C4_SMBA USART3_CTS QUADSPI_BK1_IO0 SAI2_SD_A FMC_A16/FMC_CLE EVENTOUT
61 PortD PD12 TIM4_CH1 LPTIM1_IN1 I2C4_SCL USART3_RTS QUADSPI_BK1_IO1 SAI2_FS_A FMC_A17/FMC_ALE EVENTOUT
62 PortD PD13 TIM4_CH2 LPTIM1_OUT I2C4_SDA QUADSPI_BK1_IO3 SAI2_SCK_A FMC_A18 EVENTOUT
63 PortD PD14 TIM4_CH3 UART8_CTS FMC_D0 EVENTOUT
64 PortD PD15 TIM4_CH4 UART8_RTS FMC_D1 EVENTOUT
65 PortE PE0 TIM4_ETR LPTIM1_ETR UART8_RX SAI2_MCK_A FMC_NBL0 DCMI_D2 EVENTOUT
66 PortE PE1 LPTIM1_IN2 UART8_TX FMC_NBL1 DCMI_D3 EVENTOUT
67 PortE PE2 TRACECLK SPI4_SCK SAI1_MCLK_A QUADSPI_BK1_IO2 ETH_MII_TXD3 FMC_A23 EVENTOUT
68 PortE PE3 TRACED0 SAI1_SD_B FMC_A19 EVENTOUT
69 PortE PE4 TRACED1 SPI4_NSS SAI1_FS_A DFSDM1_DATAIN3 FMC_A20 DCMI_D4 LCD_B0 EVENTOUT
70 PortE PE5 TRACED2 TIM9_CH1 SPI4_MISO SAI1_SCK_A DFSDM1_CKIN3 FMC_A21 DCMI_D6 LCD_G0 EVENTOUT
71 PortE PE6 TRACED3 TIM1_BKIN2 TIM9_CH2 SPI4_MOSI SAI1_SD_A SAI2_MCK_B FMC_A22 DCMI_D7 LCD_G1 EVENTOUT
72 PortE PE7 TIM1_ETR DFSDM1_DATAIN2 UART7_RX QUADSPI_BK2_IO0 FMC_D4 EVENTOUT
73 PortE PE8 TIM1_CH1N DFSDM1_CKIN2 UART7_TX QUADSPI_BK2_IO1 FMC_D5 EVENTOUT
74 PortE PE9 TIM1_CH1 DFSDM1_CKOUT UART7_RTS QUADSPI_BK2_IO2 FMC_D6 EVENTOUT
75 PortE PE10 TIM1_CH2N DFSDM1_DATAIN4 UART7_CTS QUADSPI_BK2_IO3 FMC_D7 EVENTOUT
76 PortE PE11 TIM1_CH2 SPI4_NSS DFSDM1_CKIN4 SAI2_SD_B FMC_D8 LCD_G3 EVENTOUT
77 PortE PE12 TIM1_CH3N SPI4_SCK DFSDM1_DATAIN5 SAI2_SCK_B FMC_D9 LCD_B4 EVENTOUT
78 PortE PE13 TIM1_CH3 SPI4_MISO DFSDM1_CKIN5 SAI2_FS_B FMC_D10 LCD_DE EVENTOUT
79 PortE PE14 TIM1_CH4 SPI4_MOSI SAI2_MCK_B FMC_D11 LCD_CLK EVENTOUT
80 PortE PE15 TIM1_BKIN FMC_D12 LCD_R7 EVENTOUT
81 PortF PF0 I2C2_SDA FMC_A0 EVENTOUT
82 PortF PF1 I2C2_SCL FMC_A1 EVENTOUT
83 PortF PF2 I2C2_SMBA FMC_A2 EVENTOUT
84 PortF PF3 FMC_A3 EVENTOUT ADC3_IN9
85 PortF PF4 FMC_A4 EVENTOUT ADC3_IN14
86 PortF PF5 FMC_A5 EVENTOUT ADC3_IN15
87 PortF PF6 TIM10_CH1 SPI5_NSS SAI1_SD_B UART7_RX QUADSPI_BK1_IO3 EVENTOUT ADC3_IN4
88 PortF PF7 TIM11_CH1 SPI5_SCK SAI1_MCLK_B UART7_TX QUADSPI_BK1_IO2 EVENTOUT ADC3_IN5
89 PortF PF8 SPI5_MISO SAI1_SCK_B UART7_RTS TIM13_CH1 QUADSPI_BK1_IO0 EVENTOUT ADC3_IN6
90 PortF PF9 SPI5_MOSI SAI1_FS_B UART7_CTS TIM14_CH1 QUADSPI_BK1_IO1 EVENTOUT ADC3_IN7
91 PortF PF10 QUADSPI_CLK DCMI_D11 LCD_DE EVENTOUT ADC3_IN8
92 PortF PF11 SPI5_MOSI SAI2_SD_B FMC_SDNRAS DCMI_D12 EVENTOUT
93 PortF PF12 FMC_A6 EVENTOUT
94 PortF PF13 I2C4_SMBA DFSDM1_DATAIN6 FMC_A7 EVENTOUT
95 PortF PF14 I2C4_SCL DFSDM1_CKIN6 FMC_A8 EVENTOUT
96 PortF PF15 I2C4_SDA FMC_A9 EVENTOUT
97 PortG PG0 FMC_A10 EVENTOUT
98 PortG PG1 FMC_A11 EVENTOUT
99 PortG PG2 FMC_A12 EVENTOUT
100 PortG PG3 FMC_A13 EVENTOUT
101 PortG PG4 FMC_A14/FMC_BA0 EVENTOUT
102 PortG PG5 FMC_A15/FMC_BA1 EVENTOUT
103 PortG PG6 FMC_NE3 DCMI_D12 LCD_R7 EVENTOUT
104 PortG PG7 SAI1_MCLK_A USART6_CK FMC_INT DCMI_D13 LCD_CLK EVENTOUT
105 PortG PG8 SPI6_NSS SPDIFRX_IN2 USART6_RTS ETH_PPS_OUT FMC_SDCLK LCD_G7 EVENTOUT
106 PortG PG9 SPI1_MISO SPDIFRX_IN3 USART6_RX QUADSPI_BK2_IO2 SAI2_FS_B SDMMC2_D0 FMC_NE2/FMC_NCE DCMI_VSYNC EVENTOUT
107 PortG PG10 SPI1_NSS/I2S1_WS LCD_G3 SAI2_SD_B SDMMC2_D1 FMC_NE3 DCMI_D2 LCD_B2 EVENTOUT
108 PortG PG11 SPI1_SCK/I2S1_CK SPDIFRX_IN0 SDMMC2_D2 ETH_MII_TX_EN/ETH_RMII_TX_EN DCMI_D3 LCD_B3 EVENTOUT
109 PortG PG12 LPTIM1_IN1 SPI6_MISO SPDIFRX_IN1 USART6_RTS LCD_B4 SDMMC2_D3 FMC_NE4 LCD_B1 EVENTOUT
110 PortG PG13 TRACED0 LPTIM1_OUT SPI6_SCK USART6_CTS ETH_MII_TXD0/ETH_RMII_TXD0 FMC_A24 LCD_R0 EVENTOUT
111 PortG PG14 TRACED1 LPTIM1_ETR SPI6_MOSI USART6_TX QUADSPI_BK2_IO3 ETH_MII_TXD1/ETH_RMII_TXD1 FMC_A25 LCD_B0 EVENTOUT
112 PortG PG15 USART6_CTS FMC_SDNCAS DCMI_D13 EVENTOUT
113 PortH PH0 EVENTOUT
114 PortH PH1 EVENTOUT
115 PortH PH2 LPTIM1_IN2 QUADSPI_BK2_IO0 SAI2_SCK_B ETH_MII_CRS FMC_SDCKE0 LCD_R0 EVENTOUT
116 PortH PH3 QUADSPI_BK2_IO1 SAI2_MCK_B ETH_MII_COL FMC_SDNE0 LCD_R1 EVENTOUT
117 PortH PH4 I2C2_SCL LCD_G5 OTG_HS_ULPI_NXT LCD_G4 EVENTOUT
118 PortH PH5 I2C2_SDA SPI5_NSS FMC_SDNWE EVENTOUT
119 PortH PH6 I2C2_SMBA SPI5_SCK TIM12_CH1 ETH_MII_RXD2 FMC_SDNE1 DCMI_D8 EVENTOUT
120 PortH PH7 I2C3_SCL SPI5_MISO ETH_MII_RXD3 FMC_SDCKE1 DCMI_D9 EVENTOUT
121 PortH PH8 I2C3_SDA FMC_D16 DCMI_HSYNC LCD_R2 EVENTOUT
122 PortH PH9 I2C3_SMBA TIM12_CH2 FMC_D17 DCMI_D0 LCD_R3 EVENTOUT
123 PortH PH10 TIM5_CH1 I2C4_SMBA FMC_D18 DCMI_D1 LCD_R4 EVENTOUT
124 PortH PH11 TIM5_CH2 I2C4_SCL FMC_D19 DCMI_D2 LCD_R5 EVENTOUT
125 PortH PH12 TIM5_CH3 I2C4_SDA FMC_D20 DCMI_D3 LCD_R6 EVENTOUT
126 PortH PH13 TIM8_CH1N UART4_TX CAN1_TX FMC_D21 LCD_G2 EVENTOUT
127 PortH PH14 TIM8_CH2N UART4_RX CAN1_RX FMC_D22 DCMI_D4 LCD_G3 EVENTOUT
128 PortH PH15 TIM8_CH3N FMC_D23 DCMI_D11 LCD_G4 EVENTOUT
129 PortI PI0 TIM5_CH4 SPI2_NSS/I2S2_WS FMC_D24 DCMI_D13 LCD_G5 EVENTOUT
130 PortI PI1 TIM8_BKIN2 SPI2_SCK/I2S2_CK FMC_D25 DCMI_D8 LCD_G6 EVENTOUT
131 PortI PI2 TIM8_CH4 SPI2_MISO FMC_D26 DCMI_D9 LCD_G7 EVENTOUT
132 PortI PI3 TIM8_ETR SPI2_MOSI/I2S2_SD FMC_D27 DCMI_D10 EVENTOUT
133 PortI PI4 TIM8_BKIN SAI2_MCK_A FMC_NBL2 DCMI_D5 LCD_B4 EVENTOUT
134 PortI PI5 TIM8_CH1 SAI2_SCK_A FMC_NBL3 DCMI_VSYNC LCD_B5 EVENTOUT
135 PortI PI6 TIM8_CH2 SAI2_SD_A FMC_D28 DCMI_D6 LCD_B6 EVENTOUT
136 PortI PI7 TIM8_CH3 SAI2_FS_A FMC_D29 DCMI_D7 LCD_B7 EVENTOUT
137 PortI PI8 EVENTOUT
138 PortI PI9 UART4_RX CAN1_RX FMC_D30 LCD_VSYNC EVENTOUT
139 PortI PI10 ETH_MII_RX_ER FMC_D31 LCD_HSYNC EVENTOUT
140 PortI PI11 LCD_G6 OTG_HS_ULPI_DIR EVENTOUT
141 PortI PI12 LCD_HSYNC EVENTOUT
142 PortI PI13 LCD_VSYNC EVENTOUT
143 PortI PI14 LCD_CLK EVENTOUT
144 PortI PI15 LCD_G2 LCD_R0 EVENTOUT
145 PortJ PJ0 LCD_R7 LCD_R1 EVENTOUT
146 PortJ PJ1 LCD_R2 EVENTOUT
147 PortJ PJ2 DSI_TE LCD_R3 EVENTOUT
148 PortJ PJ3 LCD_R4 EVENTOUT
149 PortJ PJ4 LCD_R5 EVENTOUT
150 PortJ PJ5 LCD_R6 EVENTOUT
151 PortJ PJ6 LCD_R7 EVENTOUT
152 PortJ PJ7 LCD_G0 EVENTOUT
153 PortJ PJ8 LCD_G1 EVENTOUT
154 PortJ PJ9 LCD_G2 EVENTOUT
155 PortJ PJ10 LCD_G3 EVENTOUT
156 PortJ PJ11 LCD_G4 EVENTOUT
157 PortJ PJ12 LCD_G3 LCD_B0 EVENTOUT
158 PortJ PJ13 LCD_G4 LCD_B1 EVENTOUT
159 PortJ PJ14 LCD_B2 EVENTOUT
160 PortJ PJ15 LCD_B3 EVENTOUT
161 PortK PK0 LCD_G5 EVENTOUT
162 PortK PK1 LCD_G6 EVENTOUT
163 PortK PK2 LCD_G7 EVENTOUT
164 PortK PK3 LCD_B4 EVENTOUT
165 PortK PK4 LCD_B5 EVENTOUT
166 PortK PK5 LCD_B6 EVENTOUT
167 PortK PK6 LCD_B7 EVENTOUT
168 PortK PK7 LCD_DE EVENTOUT