Add Artisense RD00 board files
This commit is contained in:
Matthias Breithaupt
parent
38382bfd12
commit
43ba81ffa1
1
.github/workflows/build.yml
vendored
1
.github/workflows/build.yml
vendored
@ -450,6 +450,7 @@ jobs:
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- "adafruit_funhouse"
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- "adafruit_funhouse"
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- "adafruit_magtag_2.9_grayscale"
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- "adafruit_magtag_2.9_grayscale"
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- "adafruit_metro_esp32s2"
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- "adafruit_metro_esp32s2"
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- "artisense_rd00"
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- "electroniccats_bastwifi"
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- "electroniccats_bastwifi"
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- "espressif_kaluga_1"
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- "espressif_kaluga_1"
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- "espressif_saola_1_wroom"
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- "espressif_saola_1_wroom"
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59
ports/esp32s2/boards/artisense_rd00/board.c
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59
ports/esp32s2/boards/artisense_rd00/board.c
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@ -0,0 +1,59 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Matthias Breithaupt for Artisense GmbH
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "supervisor/board.h"
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#include "mpconfigboard.h"
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#include "shared-bindings/microcontroller/Pin.h"
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void board_init(void) {
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// USB
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common_hal_never_reset_pin(&pin_GPIO19);
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common_hal_never_reset_pin(&pin_GPIO20);
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// Debug UART
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#ifdef DEBUG
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common_hal_never_reset_pin(&pin_GPIO43);
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common_hal_never_reset_pin(&pin_GPIO44);
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#endif /* DEBUG */
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// Crystal
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common_hal_never_reset_pin(&pin_GPIO15);
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common_hal_never_reset_pin(&pin_GPIO16);
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// PSRAM
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common_hal_never_reset_pin(&pin_GPIO26);
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}
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bool board_requests_safe_mode(void) {
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return false;
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}
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void reset_board(void) {
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}
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void board_deinit(void) {
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}
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43
ports/esp32s2/boards/artisense_rd00/mpconfigboard.h
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43
ports/esp32s2/boards/artisense_rd00/mpconfigboard.h
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Matthias Breithaupt for Artisense GmbH
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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//Micropython setup
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//Same setup as the Saola board but with no Neopixel on board
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#define MICROPY_HW_BOARD_NAME "Artisense Reference Design RD00"
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#define MICROPY_HW_MCU_NAME "ESP32S2"
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#define MICROPY_HW_NEOPIXEL (&pin_GPIO45)
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#define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
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#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
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#define AUTORESET_DELAY_MS 500
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#define DEFAULT_UART_BUS_RX (&pin_GPIO17)
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#define DEFAULT_UART_BUS_TX (&pin_GPIO18)
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17
ports/esp32s2/boards/artisense_rd00/mpconfigboard.mk
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17
ports/esp32s2/boards/artisense_rd00/mpconfigboard.mk
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@ -0,0 +1,17 @@
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USB_VID = 0x303A
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USB_PID = 0x80AF
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USB_PRODUCT = "Reference Design RD00"
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USB_MANUFACTURER = "Artisense"
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INTERNAL_FLASH_FILESYSTEM = 1
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LONGINT_IMPL = MPZ
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# The default queue depth of 16 overflows on release builds,
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# so increase it to 32.
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CFLAGS += -DCFG_TUD_TASK_QUEUE_SZ=32
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CIRCUITPY_ESP_FLASH_MODE=dio
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CIRCUITPY_ESP_FLASH_FREQ=40m
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CIRCUITPY_ESP_FLASH_SIZE=4MB
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CIRCUITPY_MODULE=wrover
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48
ports/esp32s2/boards/artisense_rd00/pins.c
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48
ports/esp32s2/boards/artisense_rd00/pins.c
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#include "shared-bindings/board/__init__.h"
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STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_GPIO1) },
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{ MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_GPIO2) },
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{ MP_ROM_QSTR(MP_QSTR_IO2), MP_ROM_PTR(&pin_GPIO6) },
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{ MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_GPIO7) },
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{ MP_ROM_QSTR(MP_QSTR_IO4), MP_ROM_PTR(&pin_GPIO8) },
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{ MP_ROM_QSTR(MP_QSTR_CAM), MP_ROM_PTR(&pin_GPIO9) },
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{ MP_ROM_QSTR(MP_QSTR_HVIO0), MP_ROM_PTR(&pin_GPIO1) },
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{ MP_ROM_QSTR(MP_QSTR_HVIO1), MP_ROM_PTR(&pin_GPIO2) },
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{ MP_ROM_QSTR(MP_QSTR_HVIO2), MP_ROM_PTR(&pin_GPIO6) },
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{ MP_ROM_QSTR(MP_QSTR_HVIO3), MP_ROM_PTR(&pin_GPIO7) },
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{ MP_ROM_QSTR(MP_QSTR_HVIO4), MP_ROM_PTR(&pin_GPIO8) },
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{ MP_ROM_QSTR(MP_QSTR_HVCAM), MP_ROM_PTR(&pin_GPIO9) },
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{ MP_ROM_QSTR(MP_QSTR_LVIO0), MP_ROM_PTR(&pin_GPIO34) },
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{ MP_ROM_QSTR(MP_QSTR_LVIO1), MP_ROM_PTR(&pin_GPIO33) },
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{ MP_ROM_QSTR(MP_QSTR_LVIO2), MP_ROM_PTR(&pin_GPIO21) },
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{ MP_ROM_QSTR(MP_QSTR_LVIO3), MP_ROM_PTR(&pin_GPIO5) },
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{ MP_ROM_QSTR(MP_QSTR_LVIO4), MP_ROM_PTR(&pin_GPIO13) },
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{ MP_ROM_QSTR(MP_QSTR_LVCAM), MP_ROM_PTR(&pin_GPIO12) },
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{ MP_ROM_QSTR(MP_QSTR_DIRIO0), MP_ROM_PTR(&pin_GPIO4) },
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{ MP_ROM_QSTR(MP_QSTR_DIRIO1), MP_ROM_PTR(&pin_GPIO3) },
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{ MP_ROM_QSTR(MP_QSTR_DIRIO2), MP_ROM_PTR(&pin_GPIO14) },
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{ MP_ROM_QSTR(MP_QSTR_DIRIO3), MP_ROM_PTR(&pin_GPIO15) },
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{ MP_ROM_QSTR(MP_QSTR_DIRIO4), MP_ROM_PTR(&pin_GPIO10) },
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{ MP_ROM_QSTR(MP_QSTR_DIRCAM), MP_ROM_PTR(&pin_GPIO11) },
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{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO42) },
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{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO41) },
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{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO40) },
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{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO39) },
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{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO38) },
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{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO37) },
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{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO36) },
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{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO35) },
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{ MP_ROM_QSTR(MP_QSTR_DBG_TX), MP_ROM_PTR(&pin_GPIO43) },
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{ MP_ROM_QSTR(MP_QSTR_DBG_RX), MP_ROM_PTR(&pin_GPIO44) },
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{ MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO17) },
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{ MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO18) },
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{ MP_ROM_QSTR(MP_QSTR_RS232_TX), MP_ROM_PTR(&pin_GPIO17) },
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{ MP_ROM_QSTR(MP_QSTR_RS232_RX), MP_ROM_PTR(&pin_GPIO18) },
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{ MP_ROM_QSTR(MP_QSTR_RS232_EN), MP_ROM_PTR(&pin_GPIO16) },
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{ MP_ROM_QSTR(MP_QSTR_DFU), MP_ROM_PTR(&pin_GPIO0) },
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{ MP_ROM_QSTR(MP_QSTR_SW1), MP_ROM_PTR(&pin_GPIO0) },
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{ MP_ROM_QSTR(MP_QSTR_BOOT), MP_ROM_PTR(&pin_GPIO0) },
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{ MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO45) },
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};
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MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
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39
ports/esp32s2/boards/artisense_rd00/sdkconfig
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39
ports/esp32s2/boards/artisense_rd00/sdkconfig
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CONFIG_ESP32S2_SPIRAM_SUPPORT=y
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#
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# SPI RAM config
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#
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# CONFIG_SPIRAM_TYPE_AUTO is not set
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CONFIG_SPIRAM_TYPE_ESPPSRAM16=y
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# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
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# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set
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CONFIG_SPIRAM_SIZE=2097152
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#
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# PSRAM clock and cs IO for ESP32S2
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#
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CONFIG_DEFAULT_PSRAM_CLK_IO=30
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CONFIG_DEFAULT_PSRAM_CS_IO=26
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# end of PSRAM clock and cs IO for ESP32S2
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# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set
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# CONFIG_SPIRAM_RODATA is not set
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# CONFIG_SPIRAM_SPEED_80M is not set
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CONFIG_SPIRAM_SPEED_40M=y
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# CONFIG_SPIRAM_SPEED_26M is not set
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# CONFIG_SPIRAM_SPEED_20M is not set
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CONFIG_SPIRAM=y
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CONFIG_SPIRAM_BOOT_INIT=y
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# CONFIG_SPIRAM_IGNORE_NOTFOUND is not set
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CONFIG_SPIRAM_USE_MEMMAP=y
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# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
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# CONFIG_SPIRAM_USE_MALLOC is not set
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CONFIG_SPIRAM_MEMTEST=y
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# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
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# end of SPI RAM config
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#
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# LWIP
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#
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CONFIG_LWIP_LOCAL_HOSTNAME="RD00-ESP32S2"
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# end of LWIP
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