samd/mcu: Set the SAMD21 us-counter to 2 MHz for better resolution.
It turned out that the result of calling ticks_us() was always either odd or even, depending on some internal state during boot. So the us-counter was set to a 2 MHz input and the result shifted by 1. The counting period is still long enough, since internally a (now) 63 bit value is used for us.
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@ -166,7 +166,7 @@ void init_clocks(uint32_t cpu_freq) {
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// GCLK0: 48MHz, source: DFLL48M or FDPLL96M, usage: CPU
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// GCLK1: 32kHz, source: XOSC32K or OSCULP32K, usage: FDPLL96M reference
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// GCLK2: 1-48MHz, source: DFLL48M, usage: Peripherals
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// GCLK3: 1Mhz, source: DFLL48M, usage: us-counter (TC4/TC5)
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// GCLK3: 2Mhz, source: DFLL48M, usage: us-counter (TC4/TC5)
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// GCLK4: 32kHz, source: XOSC32K, if crystal present, usage: DFLL48M reference
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// GCLK5: 48MHz, source: DFLL48M, usage: USB
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// GCLK8: 1kHz, source: XOSC32K or OSCULP32K, usage: WDT and RTC
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@ -291,8 +291,8 @@ void init_clocks(uint32_t cpu_freq) {
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set_cpu_freq(cpu_freq);
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// Enable GCLK output: 1MHz on GCLK3 for TC4
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(3) | GCLK_GENDIV_DIV(48);
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// Enable GCLK output: 2MHz on GCLK3 for TC4
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(3) | GCLK_GENDIV_DIV(24);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(3);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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@ -147,7 +147,7 @@ uint64_t mp_hal_ticks_us_64(void) {
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us64_upper++;
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}
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#if defined(MCU_SAMD21)
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return ((uint64_t)us64_upper << 32) | us64_lower;
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return ((uint64_t)us64_upper << 31) | (us64_lower >> 1);
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#elif defined(MCU_SAMD51)
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return ((uint64_t)us64_upper << 28) | (us64_lower >> 4);
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#endif
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@ -54,11 +54,7 @@ static inline mp_uint_t mp_hal_ticks_ms(void) {
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}
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static inline mp_uint_t mp_hal_ticks_us(void) {
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#if defined(MCU_SAMD21)
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return REG_TC4_COUNT32_COUNT;
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#else
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return (mp_uint_t)mp_hal_ticks_us_64();
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#endif
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}
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#if defined(MCU_SAMD21)
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