diff --git a/ports/samd/mcu/samd21/clock_config.c b/ports/samd/mcu/samd21/clock_config.c index 630b5c0a4a..d3c8c71995 100644 --- a/ports/samd/mcu/samd21/clock_config.c +++ b/ports/samd/mcu/samd21/clock_config.c @@ -166,7 +166,7 @@ void init_clocks(uint32_t cpu_freq) { // GCLK0: 48MHz, source: DFLL48M or FDPLL96M, usage: CPU // GCLK1: 32kHz, source: XOSC32K or OSCULP32K, usage: FDPLL96M reference // GCLK2: 1-48MHz, source: DFLL48M, usage: Peripherals - // GCLK3: 1Mhz, source: DFLL48M, usage: us-counter (TC4/TC5) + // GCLK3: 2Mhz, source: DFLL48M, usage: us-counter (TC4/TC5) // GCLK4: 32kHz, source: XOSC32K, if crystal present, usage: DFLL48M reference // GCLK5: 48MHz, source: DFLL48M, usage: USB // GCLK8: 1kHz, source: XOSC32K or OSCULP32K, usage: WDT and RTC @@ -291,8 +291,8 @@ void init_clocks(uint32_t cpu_freq) { set_cpu_freq(cpu_freq); - // Enable GCLK output: 1MHz on GCLK3 for TC4 - GCLK->GENDIV.reg = GCLK_GENDIV_ID(3) | GCLK_GENDIV_DIV(48); + // Enable GCLK output: 2MHz on GCLK3 for TC4 + GCLK->GENDIV.reg = GCLK_GENDIV_ID(3) | GCLK_GENDIV_DIV(24); GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(3); while (GCLK->STATUS.bit.SYNCBUSY) { } diff --git a/ports/samd/mphalport.c b/ports/samd/mphalport.c index 44d1470fc5..d7511e61fb 100644 --- a/ports/samd/mphalport.c +++ b/ports/samd/mphalport.c @@ -147,7 +147,7 @@ uint64_t mp_hal_ticks_us_64(void) { us64_upper++; } #if defined(MCU_SAMD21) - return ((uint64_t)us64_upper << 32) | us64_lower; + return ((uint64_t)us64_upper << 31) | (us64_lower >> 1); #elif defined(MCU_SAMD51) return ((uint64_t)us64_upper << 28) | (us64_lower >> 4); #endif diff --git a/ports/samd/mphalport.h b/ports/samd/mphalport.h index d5fc935343..83ccf44222 100644 --- a/ports/samd/mphalport.h +++ b/ports/samd/mphalport.h @@ -54,11 +54,7 @@ static inline mp_uint_t mp_hal_ticks_ms(void) { } static inline mp_uint_t mp_hal_ticks_us(void) { - #if defined(MCU_SAMD21) - return REG_TC4_COUNT32_COUNT; - #else return (mp_uint_t)mp_hal_ticks_us_64(); - #endif } #if defined(MCU_SAMD21)