Wait for the DFLL to be stable.

2018-06-06 12:02:17 -07:00 · 2018-06-06 12:02:17 -07:00 · 383bf9a59e
parent 07a8899c72
commit 383bf9a59e
1 changed files with 3 additions and 0 deletions
--- a/ports/atmel-samd/peripherals/samd21/clocks.c
+++ b/ports/atmel-samd/peripherals/samd21/clocks.c
@ -130,6 +130,9 @@ static void init_clock_source_dfll48m_xosc(void) {
                            SYSCTRL_DFLLCTRL_ENABLE;
    while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}
    while (GCLK->STATUS.bit.SYNCBUSY) {}
+
+    // Wait for the fine lock on the DFLL.
+    while (!SYSCTRL->PCLKSR.bit.DFLLLCKC || !SYSCTRL->PCLKSR.bit.DFLLLCKF) {}
 }

 static void init_clock_source_dfll48m_usb(void) {