diff --git a/atmel-samd/boards/feather_m0_adalogger/pins.c b/atmel-samd/boards/feather_m0_adalogger/pins.c
index ab78a1592d..6cc2e33bd5 100644
--- a/atmel-samd/boards/feather_m0_adalogger/pins.c
+++ b/atmel-samd/boards/feather_m0_adalogger/pins.c
@@ -6,7 +6,7 @@ STATIC const mp_map_elem_t board_global_dict_table[] = {
   { MP_OBJ_NEW_QSTR(MP_QSTR_A2), (mp_obj_t)&pin_PB09 },
   { MP_OBJ_NEW_QSTR(MP_QSTR_A3), (mp_obj_t)&pin_PA04 },
   { MP_OBJ_NEW_QSTR(MP_QSTR_A4), (mp_obj_t)&pin_PA05 },
-  { MP_OBJ_NEW_QSTR(MP_QSTR_SD), (mp_obj_t)&pin_PA08 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_SD_CS), (mp_obj_t)&pin_PA08 },
   { MP_OBJ_NEW_QSTR(MP_QSTR_A5), (mp_obj_t)&pin_PB02 },
   { MP_OBJ_NEW_QSTR(MP_QSTR_SCK), (mp_obj_t)&pin_PB11 },
   { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), (mp_obj_t)&pin_PB10 },
diff --git a/atmel-samd/common-hal/nativeio/SPI.c b/atmel-samd/common-hal/nativeio/SPI.c
index f24cd40a2a..705e30d8ee 100644
--- a/atmel-samd/common-hal/nativeio/SPI.c
+++ b/atmel-samd/common-hal/nativeio/SPI.c
@@ -135,6 +135,11 @@ void common_hal_nativeio_spi_construct(nativeio_spi_obj_t *self,
         self->MISO_pin = miso->pin;
     }
 
+    // Always start at 250khz which is what SD cards need. They are sensitive to
+    // SPI bus noise before they are put into SPI mode.
+    self->current_baudrate = 250000;
+    config_spi_master.mode_specific.master.baudrate = self->current_baudrate;
+
     spi_init(&self->spi_master_instance, sercom, &config_spi_master);
 
     spi_enable(&self->spi_master_instance);
@@ -150,9 +155,11 @@ void common_hal_nativeio_spi_deinit(nativeio_spi_obj_t *self) {
 bool common_hal_nativeio_spi_configure(nativeio_spi_obj_t *self,
         uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
     // TODO(tannewt): Check baudrate first before changing it.
-    enum status_code status = spi_set_baudrate(&self->spi_master_instance, baudrate);
-    if (status != STATUS_OK) {
-        return false;
+    if (baudrate != self->current_baudrate) {
+        enum status_code status = spi_set_baudrate(&self->spi_master_instance, baudrate);
+        if (status != STATUS_OK) {
+            return false;
+        }
     }
 
     SercomSpi *const spi_module = &(self->spi_master_instance.hw->SPI);
@@ -213,7 +220,7 @@ bool common_hal_nativeio_spi_write(nativeio_spi_obj_t *self,
 }
 
 bool common_hal_nativeio_spi_read(nativeio_spi_obj_t *self,
-        uint8_t *data, size_t len) {
+        uint8_t *data, size_t len, uint8_t write_value) {
     if (len == 0) {
         return true;
     }
@@ -221,6 +228,6 @@ bool common_hal_nativeio_spi_read(nativeio_spi_obj_t *self,
         &self->spi_master_instance,
         data,
         len,
-        0);
+        write_value);
     return status == STATUS_OK;
 }
diff --git a/atmel-samd/common-hal/nativeio/types.h b/atmel-samd/common-hal/nativeio/types.h
index ad52053816..c039ed2936 100644
--- a/atmel-samd/common-hal/nativeio/types.h
+++ b/atmel-samd/common-hal/nativeio/types.h
@@ -85,6 +85,7 @@ typedef struct {
     uint8_t clock_pin;
     uint8_t MOSI_pin;
     uint8_t MISO_pin;
+    uint32_t current_baudrate;
 } nativeio_spi_obj_t;
 
 typedef struct {
diff --git a/esp8266/common-hal/nativeio/SPI.c b/esp8266/common-hal/nativeio/SPI.c
index 444483eb3f..27774dcab6 100644
--- a/esp8266/common-hal/nativeio/SPI.c
+++ b/esp8266/common-hal/nativeio/SPI.c
@@ -126,20 +126,24 @@ bool common_hal_nativeio_spi_write(nativeio_spi_obj_t *self,
 }
 
 bool common_hal_nativeio_spi_read(nativeio_spi_obj_t *self,
-        uint8_t * data, size_t len) {
+        uint8_t * data, size_t len, uint8_t write_value) {
     // Process data in chunks, let the pending tasks run in between
     size_t chunk_size = 1024; // TODO this should depend on baudrate
     size_t count = len / chunk_size;
     size_t i = 0;
+    uint32_t long_write_value = ((uint32_t) write_value) << 24 |
+                                write_value << 16 |
+                                write_value << 8 |
+                                write_value;
     for (size_t j = 0; j < count; ++j) {
         for (size_t k = 0; k < chunk_size; ++k) {
-            data[i] = spi_rx8(HSPI);
+            data[i] = spi_transaction(HSPI, 0, 0, 0, 0, 0, 0, 8, long_write_value);
             ++i;
         }
         ets_loop_iter();
     }
     while (i < len) {
-        data[i] = spi_rx8(HSPI);
+        data[i] = spi_transaction(HSPI, 0, 0, 0, 0, 0, 0, 8, long_write_value);
         ++i;
     }
     return true;
diff --git a/shared-bindings/nativeio/SPI.c b/shared-bindings/nativeio/SPI.c
index 004c55e4e2..75d7117e52 100644
--- a/shared-bindings/nativeio/SPI.c
+++ b/shared-bindings/nativeio/SPI.c
@@ -189,39 +189,92 @@ STATIC mp_obj_t nativeio_spi_obj_unlock(mp_obj_t self_in) {
 }
 MP_DEFINE_CONST_FUN_OBJ_1(nativeio_spi_unlock_obj, nativeio_spi_obj_unlock);
 
-//|   .. method:: SPI.write(buf)
+//|   .. method:: SPI.write(buffer, \*, start=0, end=len(buffer))
 //|
 //|     Write the data contained in ``buf``. Requires the SPI being locked.
 //|
-STATIC mp_obj_t nativeio_spi_write(mp_obj_t self_in, mp_obj_t wr_buf) {
-    mp_buffer_info_t src;
-    mp_get_buffer_raise(wr_buf, &src, MP_BUFFER_READ);
-    nativeio_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
+//|     :param bytearray buffer: buffer containing the bytes to write
+//|     :param int start: Index to start writing from
+//|     :param int end: Index to read up to but not include
+//|
+STATIC mp_obj_t nativeio_spi_write(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    enum { ARG_buffer, ARG_start, ARG_end };
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_buffer,     MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_start,      MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+        { MP_QSTR_end,        MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = INT_MAX} },
+    };
+    nativeio_spi_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
     check_lock(self);
-    bool ok = common_hal_nativeio_spi_write(self, src.buf, src.len);
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    mp_buffer_info_t bufinfo;
+    mp_get_buffer_raise(args[ARG_buffer].u_obj, &bufinfo, MP_BUFFER_READ);
+    int32_t end = args[ARG_end].u_int;
+    if (end < 0) {
+        end += bufinfo.len;
+    }
+    uint32_t start = args[ARG_start].u_int;
+    uint32_t len = end - start;
+    if ((uint32_t) end < start) {
+        len = 0;
+    } else if (len > bufinfo.len) {
+        len = bufinfo.len;
+    }
+
+    bool ok = common_hal_nativeio_spi_write(self, ((uint8_t*)bufinfo.buf) + start, len);
     if (!ok) {
         nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "SPI bus error"));
     }
     return mp_const_none;
 }
-MP_DEFINE_CONST_FUN_OBJ_2(nativeio_spi_write_obj, nativeio_spi_write);
+MP_DEFINE_CONST_FUN_OBJ_KW(nativeio_spi_write_obj, 2, nativeio_spi_write);
 
 
-//|   .. method:: SPI.readinto(buf)
+//|   .. method:: SPI.readinto(buffer, \*, start=0, end=len(buffer), write_value=0)
 //|
 //|     Read into the buffer specified by ``buf`` while writing zeroes. Requires the SPI being locked.
 //|
-STATIC mp_obj_t nativeio_spi_readinto(size_t n_args, const mp_obj_t *args) {
+//|     :param bytearray buffer: buffer to write into
+//|     :param int start: Index to start writing at
+//|     :param int end: Index to write up to but not include
+//|     :param int write_value: Value to write reading. (Usually ignored.)
+//|
+STATIC mp_obj_t nativeio_spi_readinto(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    enum { ARG_buffer, ARG_start, ARG_end, ARG_write_value };
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_buffer,     MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_start,      MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+        { MP_QSTR_end,        MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = INT_MAX} },
+        { MP_QSTR_write_value,MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+    };
+    nativeio_spi_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
+    check_lock(self);
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
     mp_buffer_info_t bufinfo;
-    mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_WRITE);
-    check_lock(args[0]);
-    bool ok = common_hal_nativeio_spi_read(args[0], bufinfo.buf, bufinfo.len);
+    mp_get_buffer_raise(args[ARG_buffer].u_obj, &bufinfo, MP_BUFFER_WRITE);
+    int32_t end = args[ARG_end].u_int;
+    if (end < 0) {
+        end += bufinfo.len;
+    }
+    uint32_t start = args[ARG_start].u_int;
+    uint32_t len = end - start;
+    if ((uint32_t) end < start) {
+        len = 0;
+    } else if (len > bufinfo.len) {
+        len = bufinfo.len;
+    }
+
+    bool ok = common_hal_nativeio_spi_read(self, ((uint8_t*)bufinfo.buf) + start, len, args[ARG_write_value].u_int);
     if (!ok) {
         nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "SPI bus error"));
     }
     return mp_const_none;
 }
-MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(nativeio_spi_readinto_obj, 2, 2, nativeio_spi_readinto);
+MP_DEFINE_CONST_FUN_OBJ_KW(nativeio_spi_readinto_obj, 2, nativeio_spi_readinto);
 
 STATIC const mp_rom_map_elem_t nativeio_spi_locals_dict_table[] = {
     { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&nativeio_spi_deinit_obj) },
diff --git a/shared-bindings/nativeio/SPI.h b/shared-bindings/nativeio/SPI.h
index 9c7dd255ef..b997ddf671 100644
--- a/shared-bindings/nativeio/SPI.h
+++ b/shared-bindings/nativeio/SPI.h
@@ -52,6 +52,6 @@ extern void common_hal_nativeio_spi_unlock(nativeio_spi_obj_t *self);
 extern bool common_hal_nativeio_spi_write(nativeio_spi_obj_t *self, const uint8_t *data, size_t len);
 
 // Reads in len bytes while outputting zeroes.
-extern bool common_hal_nativeio_spi_read(nativeio_spi_obj_t *self, uint8_t *data, size_t len);
+extern bool common_hal_nativeio_spi_read(nativeio_spi_obj_t *self, uint8_t *data, size_t len, uint8_t write_value);
 
 #endif // __MICROPY_INCLUDED_SHARED_BINDINGS_NATIVEIO_SPI_H__