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stm32/system_stm32: Allow boards to configure PLL VCI, VCO and FRACN.

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This removes hard-coded PLL1/3 VCI, VCO and FRACN.
This commit is contained in:
iabdalkader 2022-04-08 09:41:19 +02:00 committed by Damien George
parent a3e5a68c46
commit 36cac5e154
4 changed files with 46 additions and 26 deletions
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6
ports/stm32/boards/NUCLEO_H743ZI/mpconfigboard.h
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@ -19,6 +19,9 @@ void NUCLEO_H743ZI_board_early_init(void);
#define MICROPY_HW_CLK_PLLP (2) #define MICROPY_HW_CLK_PLLP (2)
#define MICROPY_HW_CLK_PLLQ (4) #define MICROPY_HW_CLK_PLLQ (4)
#define MICROPY_HW_CLK_PLLR (2) #define MICROPY_HW_CLK_PLLR (2)
#define MICROPY_HW_CLK_PLLVCI (RCC_PLL1VCIRANGE_1)
#define MICROPY_HW_CLK_PLLVCO (RCC_PLL1VCOWIDE)
#define MICROPY_HW_CLK_PLLFRAC (0)
// The USB clock is set using PLL3 // The USB clock is set using PLL3
#define MICROPY_HW_CLK_PLL3M (4) #define MICROPY_HW_CLK_PLL3M (4)
@ -26,6 +29,9 @@ void NUCLEO_H743ZI_board_early_init(void);
#define MICROPY_HW_CLK_PLL3P (2) #define MICROPY_HW_CLK_PLL3P (2)
#define MICROPY_HW_CLK_PLL3Q (5) #define MICROPY_HW_CLK_PLL3Q (5)
#define MICROPY_HW_CLK_PLL3R (2) #define MICROPY_HW_CLK_PLL3R (2)
#define MICROPY_HW_CLK_PLL3VCI (RCC_PLL3VCIRANGE_1)
#define MICROPY_HW_CLK_PLL3VCO (RCC_PLL3VCOWIDE)
#define MICROPY_HW_CLK_PLL3FRAC (0)
// 4 wait states // 4 wait states
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_4 #define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_4

7
ports/stm32/boards/STM32H7B3I_DK/mpconfigboard.h
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@ -18,6 +18,10 @@
#define MICROPY_HW_CLK_PLLP (2) #define MICROPY_HW_CLK_PLLP (2)
#define MICROPY_HW_CLK_PLLQ (2) #define MICROPY_HW_CLK_PLLQ (2)
#define MICROPY_HW_CLK_PLLR (2) #define MICROPY_HW_CLK_PLLR (2)
#define MICROPY_HW_CLK_PLLVCI (RCC_PLL1VCIRANGE_1)
#define MICROPY_HW_CLK_PLLVCO (RCC_PLL1VCOWIDE)
#define MICROPY_HW_CLK_PLLFRAC (0)
// The USB clock is set using PLL3 (48Mhz usb clock) // The USB clock is set using PLL3 (48Mhz usb clock)
#define MICROPY_HW_CLK_PLL3M (12) #define MICROPY_HW_CLK_PLL3M (12)
@ -25,6 +29,9 @@
#define MICROPY_HW_CLK_PLL3P (17) #define MICROPY_HW_CLK_PLL3P (17)
#define MICROPY_HW_CLK_PLL3Q (8) #define MICROPY_HW_CLK_PLL3Q (8)
#define MICROPY_HW_CLK_PLL3R (2) #define MICROPY_HW_CLK_PLL3R (2)
#define MICROPY_HW_CLK_PLL3VCI (RCC_PLL3VCIRANGE_1)
#define MICROPY_HW_CLK_PLL3VCO (RCC_PLL3VCOWIDE)
#define MICROPY_HW_CLK_PLL3FRAC (0)
// 6 wait states when running at 280MHz (VOS0 range) // 6 wait states when running at 280MHz (VOS0 range)
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_6 #define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_6

7
ports/stm32/boards/VCC_GND_H743VI/mpconfigboard.h
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@ -28,6 +28,10 @@
#define MICROPY_HW_CLK_PLLP (2) #define MICROPY_HW_CLK_PLLP (2)
#define MICROPY_HW_CLK_PLLQ (4) #define MICROPY_HW_CLK_PLLQ (4)
#define MICROPY_HW_CLK_PLLR (2) #define MICROPY_HW_CLK_PLLR (2)
#define MICROPY_HW_CLK_PLLVCI (RCC_PLL1VCIRANGE_1)
#define MICROPY_HW_CLK_PLLVCO (RCC_PLL1VCOWIDE)
#define MICROPY_HW_CLK_PLLFRAC (0)
// The USB clock is set using PLL3 // The USB clock is set using PLL3
#define MICROPY_HW_CLK_PLL3M (5) #define MICROPY_HW_CLK_PLL3M (5)
@ -35,6 +39,9 @@
#define MICROPY_HW_CLK_PLL3P (2) #define MICROPY_HW_CLK_PLL3P (2)
#define MICROPY_HW_CLK_PLL3Q (5) #define MICROPY_HW_CLK_PLL3Q (5)
#define MICROPY_HW_CLK_PLL3R (2) #define MICROPY_HW_CLK_PLL3R (2)
#define MICROPY_HW_CLK_PLL3VCI (RCC_PLL3VCIRANGE_1)
#define MICROPY_HW_CLK_PLL3VCO (RCC_PLL3VCOWIDE)
#define MICROPY_HW_CLK_PLL3FRAC (0)
// 5 wait states // 5 wait states
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_5 #define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_5

12
ports/stm32/system_stm32.c
View File

@ -351,9 +351,9 @@ MP_WEAK void SystemClock_Config(void) {
#endif #endif
#if defined(STM32H7) #if defined(STM32H7)
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; RCC_OscInitStruct.PLL.PLLRGE = MICROPY_HW_CLK_PLLVCI;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; RCC_OscInitStruct.PLL.PLLVCOSEL = MICROPY_HW_CLK_PLLVCO;
RCC_OscInitStruct.PLL.PLLFRACN = 0; RCC_OscInitStruct.PLL.PLLFRACN = MICROPY_HW_CLK_PLLFRAC;
#endif #endif
#if defined(STM32F4) || defined(STM32F7) #if defined(STM32F4) || defined(STM32F7)
@ -392,9 +392,9 @@ MP_WEAK void SystemClock_Config(void) {
PeriphClkInitStruct.PLL3.PLL3P = MICROPY_HW_CLK_PLL3P; PeriphClkInitStruct.PLL3.PLL3P = MICROPY_HW_CLK_PLL3P;
PeriphClkInitStruct.PLL3.PLL3Q = MICROPY_HW_CLK_PLL3Q; PeriphClkInitStruct.PLL3.PLL3Q = MICROPY_HW_CLK_PLL3Q;
PeriphClkInitStruct.PLL3.PLL3R = MICROPY_HW_CLK_PLL3R; PeriphClkInitStruct.PLL3.PLL3R = MICROPY_HW_CLK_PLL3R;
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1; PeriphClkInitStruct.PLL3.PLL3RGE = MICROPY_HW_CLK_PLL3VCI;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; PeriphClkInitStruct.PLL3.PLL3VCOSEL = MICROPY_HW_CLK_PLL3VCO;
PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3FRACN = MICROPY_HW_CLK_PLL3FRAC;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
__fatal_error("HAL_RCCEx_PeriphCLKConfig"); __fatal_error("HAL_RCCEx_PeriphCLKConfig");
} }