Merge pull request #888 from notro/samd51_clock_rework
atmel-samd/samd51: Refactor clock setup + implement samd.clock
This commit is contained in:
Scott Shawcroft
GitHub
commit
317bb6d2ce
@ -32,6 +32,8 @@
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#include "external_flash/external_flash.h"
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#define BOARD_HAS_CRYSTAL 1
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#define DEFAULT_I2C_BUS_SCL (&pin_PA13)
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#define DEFAULT_I2C_BUS_SDA (&pin_PA12)
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@ -33,6 +33,8 @@
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#include "external_flash/external_flash.h"
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#define BOARD_HAS_CRYSTAL 1
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#define DEFAULT_I2C_BUS_SCL (&pin_PB03)
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#define DEFAULT_I2C_BUS_SDA (&pin_PB02)
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@ -28,6 +28,7 @@
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#include "hpl_gclk_config.h"
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#include "bindings/samd/Clock.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "py/runtime.h"
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@ -51,9 +52,26 @@ void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
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GCLK->PCHCTRL[peripheral].reg = 0;
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}
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static void enable_clock_generator_sync(uint8_t gclk, uint32_t source, uint16_t divisor, bool sync) {
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uint32_t divsel = 0;
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// The datasheet says 8 bits and max value of 512, how is that possible?
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if (divisor > 255) { // Generator 1 has 16 bits
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divsel = GCLK_GENCTRL_DIVSEL;
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for (int i = 15; i > 0; i--) {
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if (divisor & (1 << i)) {
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divisor = i - 1;
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break;
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}
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}
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}
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GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_DIV(divisor) | divsel | GCLK_GENCTRL_OE | GCLK_GENCTRL_GENEN;
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if (sync)
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while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
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}
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void enable_clock_generator(uint8_t gclk, uint32_t source, uint16_t divisor) {
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GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_DIV(divisor) | GCLK_GENCTRL_GENEN;
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while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
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enable_clock_generator_sync(gclk, source, divisor, true);
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}
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void disable_clock_generator(uint8_t gclk) {
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@ -61,26 +79,394 @@ void disable_clock_generator(uint8_t gclk) {
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while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
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}
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static void init_clock_source_osculp32k(void) {
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// Calibration value is loaded at startup
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OSC32KCTRL->OSCULP32K.bit.EN1K = 1;
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OSC32KCTRL->OSCULP32K.bit.EN32K = 0;
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}
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static void init_clock_source_xosc32k(void) {
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OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ONDEMAND |
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OSC32KCTRL_XOSC32K_EN1K |
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OSC32KCTRL_XOSC32K_XTALEN |
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OSC32KCTRL_XOSC32K_ENABLE |
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OSC32KCTRL_XOSC32K_CGM(1);
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}
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static void init_clock_source_dpll0(void)
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{
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(5);
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OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(59);
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OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(0);
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OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
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while (!(OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY)) {}
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}
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void clock_init(void) {
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// DFLL48M is enabled by default
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init_clock_source_osculp32k();
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if (board_has_crystal()) {
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init_clock_source_xosc32k();
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OSC32KCTRL->RTCCTRL.bit.RTCSEL = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val;
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} else {
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OSC32KCTRL->RTCCTRL.bit.RTCSEL = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val;
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}
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MCLK->CPUDIV.reg = MCLK_CPUDIV_DIV(1);
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enable_clock_generator_sync(0, GCLK_GENCTRL_SRC_DPLL0_Val, 1, false);
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enable_clock_generator_sync(1, GCLK_GENCTRL_SRC_DFLL_Val, 1, false);
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enable_clock_generator_sync(4, GCLK_GENCTRL_SRC_DPLL0_Val, 1, false);
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enable_clock_generator_sync(5, GCLK_GENCTRL_SRC_DFLL_Val, 24, false);
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init_clock_source_dpll0();
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}
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static bool clk_enabled(uint8_t clk) {
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return GCLK->PCHCTRL[clk].bit.CHEN;
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}
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static uint8_t clk_get_generator(uint8_t clk) {
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return GCLK->PCHCTRL[clk].bit.GEN;
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}
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static uint8_t generator_get_source(uint8_t gen) {
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return GCLK->GENCTRL[gen].bit.SRC;
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}
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static bool osc_enabled(uint8_t index) {
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switch (index) {
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case GCLK_SOURCE_XOSC0:
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return OSCCTRL->XOSCCTRL[0].bit.ENABLE;
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case GCLK_SOURCE_XOSC1:
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return OSCCTRL->XOSCCTRL[1].bit.ENABLE;
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case GCLK_SOURCE_OSCULP32K:
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return true;
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case GCLK_SOURCE_XOSC32K:
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return OSC32KCTRL->XOSC32K.bit.ENABLE;
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case GCLK_SOURCE_DFLL:
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return OSCCTRL->DFLLCTRLA.bit.ENABLE;
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case GCLK_SOURCE_DPLL0:
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return OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE;
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case GCLK_SOURCE_DPLL1:
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return OSCCTRL->Dpll[1].DPLLCTRLA.bit.ENABLE;
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};
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return false;
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}
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static uint32_t osc_get_source(uint8_t index) {
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uint8_t dpll_index = index - GCLK_SOURCE_DPLL0;
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uint32_t refclk = OSCCTRL->Dpll[dpll_index].DPLLCTRLB.bit.REFCLK;
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switch (refclk) {
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case 0x0:
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return generator_get_source(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0 + dpll_index].bit.GEN);
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case 0x1:
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return GCLK_SOURCE_XOSC32K;
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case 0x2:
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return GCLK_SOURCE_XOSC0;
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case 0x3:
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return GCLK_SOURCE_XOSC1;
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}
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return 0;
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}
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static uint32_t osc_get_frequency(uint8_t index);
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static uint32_t generator_get_frequency(uint8_t gen) {
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uint8_t src = GCLK->GENCTRL[gen].bit.SRC;
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uint32_t div;
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if (GCLK->GENCTRL[gen].bit.DIVSEL) {
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div = 1 << (GCLK->GENCTRL[gen].bit.DIV + 1);
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} else {
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div = GCLK->GENCTRL[gen].bit.DIV;
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if (!div)
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div = 1;
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}
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return osc_get_frequency(src) / div;
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}
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static uint32_t dpll_get_frequency(uint8_t index) {
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uint8_t dpll_index = index - GCLK_SOURCE_DPLL0;
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uint32_t refclk = OSCCTRL->Dpll[dpll_index].DPLLCTRLB.bit.REFCLK;
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uint32_t freq;
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switch (refclk) {
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case 0x0: // GCLK
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freq = generator_get_frequency(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0 + dpll_index].bit.GEN);
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break;
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case 0x1: // XOSC32
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freq = 32768;
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break;
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case 0x2: // XOSC0
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case 0x3: // XOSC1
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return 0; // unknown
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}
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return (freq * (OSCCTRL->Dpll[dpll_index].DPLLRATIO.bit.LDR + 1)) +
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(freq * OSCCTRL->Dpll[dpll_index].DPLLRATIO.bit.LDRFRAC / 32);
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}
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static uint32_t osc_get_frequency(uint8_t index) {
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switch (index) {
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case GCLK_SOURCE_XOSC0:
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case GCLK_SOURCE_XOSC1:
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return 0; // unknown
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case GCLK_SOURCE_OSCULP32K:
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case GCLK_SOURCE_XOSC32K:
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return 32768;
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case GCLK_SOURCE_DFLL:
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return 48000000;
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case GCLK_SOURCE_DPLL0:
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case GCLK_SOURCE_DPLL1:
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return dpll_get_frequency(index);
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}
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return 0;
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}
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bool clock_get_enabled(uint8_t type, uint8_t index) {
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if (type == 0)
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return osc_enabled(index);
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if (type == 1)
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return clk_enabled(index);
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if (type == 2)
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return SysTick->CTRL & SysTick_CTRL_ENABLE_Msk;
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return false;
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}
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bool clock_get_parent(uint8_t type, uint8_t index, uint8_t *p_type, uint8_t *p_index) {
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if (type == 0 && osc_enabled(index)) {
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if (index == GCLK_SOURCE_DPLL0 || index == GCLK_SOURCE_DPLL1) {
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*p_type = 0;
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*p_index = osc_get_source(index);
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return true;
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}
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return false;
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}
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if (type == 1 && index <= 47 && clk_enabled(index)) {
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*p_type = 0;
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*p_index = generator_get_source(clk_get_generator(index));
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return true;
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}
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if (type == 2) {
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switch (index) {
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case 0:
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case 1:
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*p_type = 0;
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*p_index = generator_get_source(0);
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return true;
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case 2:
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*p_type = 0;
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switch (OSC32KCTRL->RTCCTRL.bit.RTCSEL) {
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case 0:
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case 1:
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*p_index = GCLK_SOURCE_OSCULP32K;
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return true;
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case 4:
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case 5:
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*p_index = GCLK_SOURCE_XOSC32K;
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return true;
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}
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return false;
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}
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}
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return false;
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}
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uint32_t clock_get_frequency(uint8_t type, uint8_t index) {
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if (type == 0) {
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return osc_get_frequency(index);
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}
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if (type == 1 && index <= 47 && clk_enabled(index)) {
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return generator_get_frequency(clk_get_generator(index));
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}
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if (type == 2) {
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switch (index) {
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case 0:
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return clock_get_frequency(0, generator_get_source(0)) / SysTick->LOAD;
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case 1:
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return clock_get_frequency(0, generator_get_source(0)) / MCLK->CPUDIV.bit.DIV;
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case 2:
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switch (OSC32KCTRL->RTCCTRL.bit.RTCSEL) {
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case 0:
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case 4:
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return 1024;
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case 1:
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case 5:
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return 32768;
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}
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}
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}
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return 0;
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}
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uint32_t clock_get_calibration(uint8_t type, uint8_t index) {
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if (type == 0) {
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switch (index) {
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case GCLK_SOURCE_OSCULP32K:
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return OSC32KCTRL->OSCULP32K.bit.CALIB;
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};
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}
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if (type == 2 && index == 0) {
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return SysTick->LOAD + 1;
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}
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return 0;
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}
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int clock_set_calibration(uint8_t type, uint8_t index, uint32_t val) {
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if (type == 0) {
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switch (index) {
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case GCLK_SOURCE_OSCULP32K:
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if (val > 0x3f)
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return -1;
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OSC32KCTRL->OSCULP32K.bit.CALIB = val;
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return 0;
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};
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}
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if (type == 2 && index == 0) {
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if (val < 0x1000 || val > 0x1000000)
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return -1;
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SysTick->LOAD = val - 1;
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return 0;
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}
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return -2;
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}
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#include <instance/can0.h>
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#include <instance/can1.h>
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#include <instance/i2s.h>
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#include <instance/sdhc1.h>
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#include <instance/sercom6.h>
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#include <instance/sercom7.h>
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#include <instance/tcc4.h>
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CLOCK_SOURCE(XOSC0);
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CLOCK_SOURCE(XOSC1);
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CLOCK_SOURCE(GCLKIN);
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CLOCK_SOURCE(GCLKGEN1);
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CLOCK_SOURCE(OSCULP32K);
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CLOCK_SOURCE(XOSC32K);
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CLOCK_SOURCE(DFLL);
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CLOCK_SOURCE(DPLL0);
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CLOCK_SOURCE(DPLL1);
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CLOCK_GCLK_(OSCCTRL, DFLL48);
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CLOCK_GCLK_(OSCCTRL, FDPLL0);
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CLOCK_GCLK_(OSCCTRL, FDPLL1);
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CLOCK_GCLK_(OSCCTRL, FDPLL032K); // GCLK_OSCCTRL_FDPLL1_32K, GCLK_SDHC0_SLOW, GCLK_SDHC1_SLOW, GCLK_SERCOM[0..7]_SLOW
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CLOCK_GCLK(EIC);
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CLOCK_GCLK_(FREQM, MSR);
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// 6: GCLK_FREQM_REF
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CLOCK_GCLK_(SERCOM0, CORE);
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CLOCK_GCLK_(SERCOM1, CORE);
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CLOCK(TC0_TC1, 1, 9);
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CLOCK_GCLK(USB);
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CLOCK_GCLK_(EVSYS, 0);
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CLOCK_GCLK_(EVSYS, 1);
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CLOCK_GCLK_(EVSYS, 2);
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CLOCK_GCLK_(EVSYS, 3);
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CLOCK_GCLK_(EVSYS, 4);
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CLOCK_GCLK_(EVSYS, 5);
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CLOCK_GCLK_(EVSYS, 6);
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CLOCK_GCLK_(EVSYS, 7);
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CLOCK_GCLK_(EVSYS, 8);
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CLOCK_GCLK_(EVSYS, 9);
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CLOCK_GCLK_(EVSYS, 10);
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CLOCK_GCLK_(EVSYS, 11);
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CLOCK_GCLK_(SERCOM2, CORE);
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CLOCK_GCLK_(SERCOM3, CORE);
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CLOCK(TCC0_TCC1, 1, 25);
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CLOCK(TC2_TC3, 1, 26);
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CLOCK_GCLK(CAN0);
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CLOCK_GCLK(CAN1);
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CLOCK(TCC2_TCC3, 1, 29);
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CLOCK(TC4_TC5, 1, 30);
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CLOCK_GCLK(PDEC);
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CLOCK_GCLK(AC);
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CLOCK_GCLK(CCL);
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CLOCK_GCLK_(SERCOM4, CORE);
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CLOCK_GCLK_(SERCOM5, CORE);
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CLOCK_GCLK_(SERCOM6, CORE);
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CLOCK_GCLK_(SERCOM7, CORE);
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CLOCK_GCLK(TCC4);
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CLOCK(TC6_TC7, 1, 39);
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CLOCK_GCLK(ADC0);
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CLOCK_GCLK(ADC1);
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CLOCK_GCLK(DAC);
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CLOCK_GCLK_(I2S, 0);
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CLOCK_GCLK_(I2S, 1);
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CLOCK_GCLK(SDHC0);
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CLOCK_GCLK(SDHC1);
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// 47: GCLK_CM4_TRACE
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CLOCK(SYSTICK, 2, 0);
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CLOCK(CPU, 2, 1);
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CLOCK(RTC, 2, 2);
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STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = {
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CLOCK_ENTRY(XOSC0),
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CLOCK_ENTRY(XOSC1),
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CLOCK_ENTRY(GCLKIN),
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CLOCK_ENTRY(GCLKGEN1),
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CLOCK_ENTRY(OSCULP32K),
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CLOCK_ENTRY(XOSC32K),
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CLOCK_ENTRY(DFLL),
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CLOCK_ENTRY(DPLL0),
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CLOCK_ENTRY(DPLL1),
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CLOCK_ENTRY_(OSCCTRL, DFLL48),
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CLOCK_ENTRY_(OSCCTRL, FDPLL0),
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CLOCK_ENTRY_(OSCCTRL, FDPLL1),
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CLOCK_ENTRY_(OSCCTRL, FDPLL032K),
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CLOCK_ENTRY(EIC),
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CLOCK_ENTRY_(FREQM, MSR),
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CLOCK_ENTRY_(SERCOM0, CORE),
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CLOCK_ENTRY_(SERCOM1, CORE),
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CLOCK_ENTRY(TC0_TC1),
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CLOCK_ENTRY(USB),
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CLOCK_ENTRY_(EVSYS, 0),
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CLOCK_ENTRY_(EVSYS, 1),
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CLOCK_ENTRY_(EVSYS, 2),
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CLOCK_ENTRY_(EVSYS, 3),
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CLOCK_ENTRY_(EVSYS, 4),
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CLOCK_ENTRY_(EVSYS, 5),
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CLOCK_ENTRY_(EVSYS, 6),
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CLOCK_ENTRY_(EVSYS, 7),
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CLOCK_ENTRY_(EVSYS, 8),
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CLOCK_ENTRY_(EVSYS, 9),
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CLOCK_ENTRY_(EVSYS, 10),
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CLOCK_ENTRY_(EVSYS, 11),
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CLOCK_ENTRY_(SERCOM2, CORE),
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CLOCK_ENTRY_(SERCOM3, CORE),
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CLOCK_ENTRY(TCC0_TCC1),
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CLOCK_ENTRY(TC2_TC3),
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CLOCK_ENTRY(CAN0),
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CLOCK_ENTRY(CAN1),
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CLOCK_ENTRY(TCC2_TCC3),
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CLOCK_ENTRY(TC4_TC5),
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CLOCK_ENTRY(PDEC),
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CLOCK_ENTRY(AC),
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CLOCK_ENTRY(CCL),
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CLOCK_ENTRY_(SERCOM4, CORE),
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CLOCK_ENTRY_(SERCOM5, CORE),
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CLOCK_ENTRY_(SERCOM6, CORE),
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CLOCK_ENTRY_(SERCOM7, CORE),
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CLOCK_ENTRY(TCC4),
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CLOCK_ENTRY(TC6_TC7),
|
||||
CLOCK_ENTRY(ADC0),
|
||||
CLOCK_ENTRY(ADC1),
|
||||
CLOCK_ENTRY(DAC),
|
||||
CLOCK_ENTRY_(I2S, 0),
|
||||
CLOCK_ENTRY_(I2S, 1),
|
||||
CLOCK_ENTRY(SDHC0),
|
||||
CLOCK_ENTRY(SDHC1),
|
||||
|
||||
CLOCK_ENTRY(SYSTICK),
|
||||
CLOCK_ENTRY(CPU),
|
||||
CLOCK_ENTRY(RTC),
|
||||
};
|
||||
MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table);
|
||||
|
||||
@ -181,11 +181,9 @@ safe_mode_t port_init(void) {
|
||||
#ifdef SAMD21
|
||||
hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
|
||||
_pm_init();
|
||||
#endif
|
||||
clock_init();
|
||||
#endif
|
||||
#ifdef SAMD51
|
||||
init_mcu();
|
||||
#endif
|
||||
|
||||
board_init();
|
||||
|
||||
// Configure millisecond timer initialization.
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user