stm32/rfcore: Update rfcore.c to match how ST examples work.
- Split tables and buffers into SRAM2A/2B. - Use structs rather than word offsets to access tables. - Use FLASH_IPCCDBA register value rather than option bytes directly.
This commit is contained in:
Jim Mussared
Damien George
parent
b27edb8073
commit
30e8162ac4
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@ -9,7 +9,8 @@ MEMORY
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FLASH_APP (rx) : ORIGIN = 0x08004000, LENGTH = 496K /* sectors 4-127 */
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FLASH_FS (r) : ORIGIN = 0x08080000, LENGTH = 256K /* sectors 128-191 */
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K /* SRAM1 */
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RAM2A (xrw) : ORIGIN = 0x20030020, LENGTH = 8K /* SRAM2A */
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RAM2A (xrw) : ORIGIN = 0x20030000, LENGTH = 10K /* SRAM2A */
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RAM2B (xrw) : ORIGIN = 0x20038000, LENGTH = 10K /* SRAM2B */
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}
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/* produce a link error if there is not this amount of RAM for these sections */
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@ -36,10 +37,20 @@ _flash_fs_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);
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SECTIONS
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{
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/* Put all IPCC tables into SRAM2A. */
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.ram2a_bss :
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{
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. = ALIGN(4);
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. = . + 64; /* Leave room for the mb_ref_table_t (assuming IPCCDBA==0). */
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*rfcore.o(.bss.ipcc_mem_*)
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. = ALIGN(4);
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} >RAM2A
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/* Put all IPCC buffers into SRAM2B. */
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.ram2b_bss :
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{
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. = ALIGN(4);
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*rfcore.o(.bss.ipcc_membuf_*)
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. = ALIGN(4);
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} >RAM2B
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}
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@ -4,6 +4,7 @@
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Damien P. George
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* Copyright (c) 2020 Jim Mussared
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -34,6 +35,10 @@
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#if defined(STM32WB)
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#include "stm32wbxx_ll_ipcc.h"
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#define DEBUG_printf(...) // printf("rfcore: " __VA_ARGS__)
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// Define to 1 to print traces of HCI packets
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#define HCI_TRACE (0)
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@ -61,23 +66,88 @@ typedef struct _parse_hci_info_t {
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bool was_hci_reset_evt;
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} parse_hci_info_t;
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static volatile uint32_t ipcc_mem_dev_info_tab[8];
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static volatile uint32_t ipcc_mem_ble_tab[4];
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static volatile uint32_t ipcc_mem_sys_tab[2];
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static volatile uint32_t ipcc_mem_memmgr_tab[7];
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// Version
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// [0:3] = Build - 0: Untracked - 15:Released - x: Tracked version
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// [4:7] = branch - 0: Mass Market - x: ...
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// [8:15] = Subversion
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// [16:23] = Version minor
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// [24:31] = Version major
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static volatile uint32_t ipcc_mem_sys_cmd_buf[272 / 4];
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static volatile tl_list_node_t ipcc_mem_sys_queue;
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// Memory Size
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// [0:7] = Flash (Number of 4k sectors)
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// [8:15] = Reserved (Shall be set to 0 - may be used as flash extension)
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// [16:23] = SRAM2b (Number of 1k sectors)
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// [24:31] = SRAM2a (Number of 1k sectors)
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static volatile tl_list_node_t ipcc_mem_memmgr_free_buf_queue;
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static volatile uint32_t ipcc_mem_memmgr_ble_spare_evt_buf[272 / 4];
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static volatile uint32_t ipcc_mem_memmgr_sys_spare_evt_buf[272 / 4];
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static volatile uint32_t ipcc_mem_memmgr_evt_pool[6 * 272 / 4];
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typedef struct __attribute__((packed)) _ipcc_device_info_table_t {
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uint32_t safeboot_version;
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uint32_t fus_version;
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uint32_t fus_memorysize;
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uint32_t fus_info;
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uint32_t fw_version;
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uint32_t fw_memorysize;
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uint32_t fw_infostack;
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uint32_t fw_reserved;
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} ipcc_device_info_table_t;
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static volatile uint32_t ipcc_mem_ble_cmd_buf[272 / 4];
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static volatile uint32_t ipcc_mem_ble_cs_buf[272 / 4];
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static volatile tl_list_node_t ipcc_mem_ble_evt_queue;
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static volatile uint32_t ipcc_mem_ble_hci_acl_data_buf[272 / 4];
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typedef struct __attribute__((packed)) _ipcc_ble_table_t {
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uint8_t *pcmd_buffer;
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uint8_t *pcs_buffer;
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tl_list_node_t *pevt_queue;
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uint8_t *phci_acl_data_buffer;
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} ipcc_ble_table_t;
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// msg
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// [0:7] = cmd/evt
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// [8:31] = Reserved
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typedef struct __attribute__((packed)) _ipcc_sys_table_t {
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uint8_t *pcmd_buffer;
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tl_list_node_t *sys_queue;
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} ipcc_sys_table_t;
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typedef struct __attribute__((packed)) _ipcc_mem_manager_table_t {
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uint8_t *spare_ble_buffer;
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uint8_t *spare_sys_buffer;
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uint8_t *blepool;
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uint32_t blepoolsize;
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tl_list_node_t *pevt_free_buffer_queue;
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uint8_t *traces_evt_pool;
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uint32_t tracespoolsize;
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} ipcc_mem_manager_table_t;
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typedef struct __attribute__((packed)) _ipcc_ref_table_t {
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ipcc_device_info_table_t *p_device_info_table;
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ipcc_ble_table_t *p_ble_table;
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void *p_thread_table;
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ipcc_sys_table_t *p_sys_table;
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ipcc_mem_manager_table_t *p_mem_manager_table;
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void *p_traces_table;
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void *p_mac_802_15_4_table;
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void *p_zigbee_table;
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void *p_lld_tests_table;
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void *p_lld_ble_table;
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} ipcc_ref_table_t;
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// The stm32wb55xg.ld script puts .bss.ipcc_mem_* into SRAM2A and .bss_ipcc_membuf_* into SRAM2B.
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// It also leaves 64 bytes at the start of SRAM2A for the ref table.
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STATIC ipcc_device_info_table_t ipcc_mem_dev_info_tab; // mem1
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STATIC ipcc_ble_table_t ipcc_mem_ble_tab; // mem1
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STATIC ipcc_sys_table_t ipcc_mem_sys_tab; // mem1
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STATIC ipcc_mem_manager_table_t ipcc_mem_memmgr_tab; // mem1
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STATIC uint8_t ipcc_membuf_sys_cmd_buf[272]; // mem2
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STATIC tl_list_node_t ipcc_mem_sys_queue; // mem1
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STATIC tl_list_node_t ipcc_mem_memmgr_free_buf_queue; // mem1
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STATIC uint8_t ipcc_membuf_memmgr_ble_spare_evt_buf[272]; // mem2
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STATIC uint8_t ipcc_membuf_memmgr_sys_spare_evt_buf[272]; // mem2
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STATIC uint8_t ipcc_membuf_memmgr_evt_pool[6 * 272]; // mem2
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STATIC uint8_t ipcc_membuf_ble_cmd_buf[272]; // mem2
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STATIC uint8_t ipcc_membuf_ble_cs_buf[272]; // mem2
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STATIC tl_list_node_t ipcc_mem_ble_evt_queue; // mem1
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STATIC uint8_t ipcc_membuf_ble_hci_acl_data_buf[272]; // mem2
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/******************************************************************************/
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// Transport layer linked list
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@ -105,21 +175,21 @@ STATIC void tl_list_append(volatile tl_list_node_t *head, volatile tl_list_node_
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/******************************************************************************/
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// IPCC interface
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STATIC uint32_t get_ipccdba(void) {
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return *(uint32_t *)(OPTION_BYTE_BASE + 0x68) & 0x3fff;
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}
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STATIC volatile void **get_buffer_table(void) {
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return (volatile void **)(SRAM2A_BASE + get_ipccdba());
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STATIC volatile ipcc_ref_table_t *get_buffer_table(void) {
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// The IPCCDBA option bytes must not be changed without
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// making a corresponding change to the linker script.
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return (volatile ipcc_ref_table_t *)(SRAM2A_BASE + LL_FLASH_GetIPCCBufferAddr() * 4);
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}
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void ipcc_init(uint32_t irq_pri) {
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DEBUG_printf("ipcc_init\n");
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// Setup buffer table pointers
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volatile void **tab = get_buffer_table();
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tab[0] = &ipcc_mem_dev_info_tab[0];
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tab[1] = &ipcc_mem_ble_tab[0];
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tab[3] = &ipcc_mem_sys_tab[0];
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tab[4] = &ipcc_mem_memmgr_tab[0];
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volatile ipcc_ref_table_t *tab = get_buffer_table();
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tab->p_device_info_table = &ipcc_mem_dev_info_tab;
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tab->p_ble_table = &ipcc_mem_ble_tab;
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tab->p_sys_table = &ipcc_mem_sys_tab;
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tab->p_mem_manager_table = &ipcc_mem_memmgr_tab;
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// Start IPCC peripheral
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__HAL_RCC_IPCC_CLK_ENABLE();
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@ -130,32 +200,34 @@ void ipcc_init(uint32_t irq_pri) {
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NVIC_SetPriority(IPCC_C1_RX_IRQn, irq_pri);
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HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
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// Device info table will be populated by FUS/WS
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// Device info table will be populated by FUS/WS on CPU2 boot.
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// Populate system table
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tl_list_init(&ipcc_mem_sys_queue);
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ipcc_mem_sys_tab[0] = (uint32_t)&ipcc_mem_sys_cmd_buf[0];
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ipcc_mem_sys_tab[1] = (uint32_t)&ipcc_mem_sys_queue;
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ipcc_mem_sys_tab.pcmd_buffer = ipcc_membuf_sys_cmd_buf;
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ipcc_mem_sys_tab.sys_queue = &ipcc_mem_sys_queue;
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// Populate memory manager table
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tl_list_init(&ipcc_mem_memmgr_free_buf_queue);
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ipcc_mem_memmgr_tab[0] = (uint32_t)&ipcc_mem_memmgr_ble_spare_evt_buf[0];
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ipcc_mem_memmgr_tab[1] = (uint32_t)&ipcc_mem_memmgr_sys_spare_evt_buf[0];
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ipcc_mem_memmgr_tab[2] = (uint32_t)&ipcc_mem_memmgr_evt_pool[0];
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ipcc_mem_memmgr_tab[3] = sizeof(ipcc_mem_memmgr_evt_pool);
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ipcc_mem_memmgr_tab[4] = (uint32_t)&ipcc_mem_memmgr_free_buf_queue;
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ipcc_mem_memmgr_tab[5] = 0;
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ipcc_mem_memmgr_tab[6] = 0;
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ipcc_mem_memmgr_tab.spare_ble_buffer = ipcc_membuf_memmgr_ble_spare_evt_buf;
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ipcc_mem_memmgr_tab.spare_sys_buffer = ipcc_membuf_memmgr_sys_spare_evt_buf;
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ipcc_mem_memmgr_tab.blepool = ipcc_membuf_memmgr_evt_pool;
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ipcc_mem_memmgr_tab.blepoolsize = sizeof(ipcc_membuf_memmgr_evt_pool);
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ipcc_mem_memmgr_tab.pevt_free_buffer_queue = &ipcc_mem_memmgr_free_buf_queue;
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ipcc_mem_memmgr_tab.traces_evt_pool = NULL;
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ipcc_mem_memmgr_tab.tracespoolsize = 0;
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// Populate BLE table
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tl_list_init(&ipcc_mem_ble_evt_queue);
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ipcc_mem_ble_tab[0] = (uint32_t)&ipcc_mem_ble_cmd_buf[0];
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ipcc_mem_ble_tab[1] = (uint32_t)&ipcc_mem_ble_cs_buf[0];
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ipcc_mem_ble_tab[2] = (uint32_t)&ipcc_mem_ble_evt_queue;
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ipcc_mem_ble_tab[3] = (uint32_t)&ipcc_mem_ble_hci_acl_data_buf[0];
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ipcc_mem_ble_tab.pcmd_buffer = ipcc_membuf_ble_cmd_buf;
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ipcc_mem_ble_tab.pcs_buffer = ipcc_membuf_ble_cs_buf;
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ipcc_mem_ble_tab.pevt_queue = &ipcc_mem_ble_evt_queue;
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ipcc_mem_ble_tab.phci_acl_data_buffer = ipcc_membuf_ble_hci_acl_data_buf;
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}
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STATIC int ipcc_wait_ack(unsigned int ch, uint32_t timeout_ms) {
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DEBUG_printf("ipcc_wait_ack\n");
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uint32_t t0 = mp_hal_ticks_ms();
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while (IPCC->C1TOC2SR & ch) {
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if (mp_hal_ticks_ms() - t0 > timeout_ms) {
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@ -168,6 +240,8 @@ STATIC int ipcc_wait_ack(unsigned int ch, uint32_t timeout_ms) {
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}
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STATIC int ipcc_wait_msg(unsigned int ch, uint32_t timeout_ms) {
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DEBUG_printf("ipcc_wait_msg\n");
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uint32_t t0 = mp_hal_ticks_ms();
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while (!(IPCC->C2TOC1SR & ch)) {
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if (mp_hal_ticks_ms() - t0 > timeout_ms) {
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@ -254,8 +328,8 @@ STATIC void tl_check_msg(volatile tl_list_node_t *head, unsigned int ch, parse_h
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while (cur != head) {
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tl_parse_hci_msg((uint8_t *)cur->body, parse);
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volatile tl_list_node_t *next = tl_list_unlink(cur);
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if ((void *)&ipcc_mem_memmgr_evt_pool[0] <= (void *)cur
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&& (void *)cur < (void *)&ipcc_mem_memmgr_evt_pool[MP_ARRAY_SIZE(ipcc_mem_memmgr_evt_pool)]) {
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if ((void *)&ipcc_membuf_memmgr_evt_pool[0] <= (void *)cur
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&& (void *)cur < (void *)&ipcc_membuf_memmgr_evt_pool[MP_ARRAY_SIZE(ipcc_membuf_memmgr_evt_pool)]) {
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// Place memory back in free pool
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tl_list_append(&ipcc_mem_memmgr_free_buf_queue, cur);
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free = true;
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@ -291,12 +365,12 @@ STATIC void tl_sys_wait_resp(const uint8_t *buf, unsigned int ch) {
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}
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STATIC void tl_sys_hci_cmd_resp(uint16_t opcode, size_t len, const uint8_t *buf) {
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tl_hci_cmd((uint8_t *)&ipcc_mem_sys_cmd_buf, IPCC_CH_SYS, 0x10, opcode, len, buf);
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tl_sys_wait_resp((uint8_t *)&ipcc_mem_sys_cmd_buf, IPCC_CH_SYS);
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tl_hci_cmd((uint8_t *)&ipcc_membuf_sys_cmd_buf, IPCC_CH_SYS, 0x10, opcode, len, buf);
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tl_sys_wait_resp((uint8_t *)&ipcc_membuf_sys_cmd_buf, IPCC_CH_SYS);
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}
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STATIC void tl_ble_hci_cmd_resp(uint16_t opcode, size_t len, const uint8_t *buf) {
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tl_hci_cmd((uint8_t *)&ipcc_mem_ble_cmd_buf[0], IPCC_CH_BLE, 0x01, opcode, len, buf);
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tl_hci_cmd((uint8_t *)&ipcc_membuf_ble_cmd_buf[0], IPCC_CH_BLE, 0x01, opcode, len, buf);
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ipcc_wait_msg(IPCC_CH_BLE, 250);
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tl_check_msg(&ipcc_mem_ble_evt_queue, IPCC_CH_BLE, NULL);
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}
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@ -305,6 +379,8 @@ STATIC void tl_ble_hci_cmd_resp(uint16_t opcode, size_t len, const uint8_t *buf)
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// RF core interface
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void rfcore_init(void) {
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DEBUG_printf("rfcore_init\n");
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// Ensure LSE is running
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rtc_init_finalise();
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@ -361,6 +437,8 @@ static const struct {
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};
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void rfcore_ble_init(void) {
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DEBUG_printf("rfcore_ble_init\n");
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// Clear any outstanding messages from ipcc_init
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tl_check_msg(&ipcc_mem_sys_queue, IPCC_CH_SYS, NULL);
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tl_check_msg(&ipcc_mem_ble_evt_queue, IPCC_CH_BLE, NULL);
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@ -371,6 +449,8 @@ void rfcore_ble_init(void) {
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}
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void rfcore_ble_hci_cmd(size_t len, const uint8_t *src) {
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DEBUG_printf("rfcore_ble_hci_cmd\n");
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#if HCI_TRACE
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printf("[% 8d] HCI_CMD(%02x", mp_hal_ticks_ms(), src[0]);
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for (int i = 1; i < len; ++i) {
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@ -382,10 +462,10 @@ void rfcore_ble_hci_cmd(size_t len, const uint8_t *src) {
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tl_list_node_t *n;
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uint32_t ch;
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if (src[0] == 0x01) {
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n = (tl_list_node_t *)&ipcc_mem_ble_cmd_buf[0];
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n = (tl_list_node_t *)&ipcc_membuf_ble_cmd_buf[0];
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ch = IPCC_CH_BLE;
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} else if (src[0] == 0x02) {
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n = (tl_list_node_t *)&ipcc_mem_ble_hci_acl_data_buf[0];
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n = (tl_list_node_t *)&ipcc_membuf_ble_hci_acl_data_buf[0];
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ch = IPCC_CH_HCI_ACL;
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} else {
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printf("** UNEXPECTED HCI HDR: 0x%02x **\n", src[0]);
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