nrf5/devices: Updating header files for nrf51 and nrf52. Adding headers for nrf52840.
This commit is contained in:
Glenn Ruben Bakke
parent
19d354ed05
commit
307f95bd03
@ -33,30 +33,48 @@
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/* MDK version */
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#define MDK_MAJOR_VERSION 8
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#define MDK_MINOR_VERSION 9
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#define MDK_MICRO_VERSION 0
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#define MDK_MINOR_VERSION 11
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#define MDK_MICRO_VERSION 1
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/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
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#if defined (NRF52)
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#ifndef NRF52832_XXAA
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#define NRF52832_XXAA
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#endif
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#endif
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/* Define NRF52_SERIES for common use in nRF52 series devices. */
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#if defined (NRF52832_XXAA) || defined (NRF52840_XXAA)
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#define NRF52_SERIES
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#endif
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#if defined(_WIN32)
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/* Do not include nrf51 specific files when building for PC host */
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/* Do not include nrf specific files when building for PC host */
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#elif defined(__unix)
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/* Do not include nrf51 specific files when building for PC host */
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/* Do not include nrf specific files when building for PC host */
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#elif defined(__APPLE__)
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/* Do not include nrf51 specific files when building for PC host */
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/* Do not include nrf specific files when building for PC host */
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#else
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/* Family selection for family includes. */
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/* Device selection for device includes. */
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#if defined (NRF51)
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#include "nrf51.h"
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#include "nrf51_bitfields.h"
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#include "nrf51_deprecated.h"
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#elif defined (NRF52)
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#elif defined (NRF52840_XXAA)
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#include "nrf52840.h"
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#include "nrf52840_bitfields.h"
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#include "nrf51_to_nrf52840.h"
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#include "nrf52_to_nrf52840.h"
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#elif defined (NRF52832_XXAA)
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#include "nrf52.h"
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#include "nrf52_bitfields.h"
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#include "nrf51_to_nrf52.h"
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#include "nrf52_name_change.h"
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#else
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#error "Device family must be defined. See nrf.h."
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#endif /* NRF51, NRF52 */
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#error "Device must be defined. See nrf.h."
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#endif /* NRF51, NRF52832_XXAA, NRF52840_XXAA */
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#include "compiler_abstraction.h"
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@ -6,7 +6,7 @@
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* nrf51 from Nordic Semiconductor.
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*
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* @version V522
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* @date 30. September 2016
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* @date 18. November 2016
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*
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* @note Generated with SVDConv V2.81d
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* from CMSIS SVD File 'nrf51.svd' Version 522,
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@ -5692,7 +5692,7 @@
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#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
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#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
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#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
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#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
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#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps). */
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/* Register: TWI_ADDRESS */
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/* Description: Address used in the two-wire transfer. */
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@ -5886,6 +5886,7 @@
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#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
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#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
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#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
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#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud. */
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#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
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#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud. */
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#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
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567
nrf5/device/nrf52/nrf51_to_nrf52840.h
Normal file
567
nrf5/device/nrf52/nrf51_to_nrf52840.h
Normal file
@ -0,0 +1,567 @@
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/* Copyright (c) 2016, Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* * Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef NRF51_TO_NRF52840_H
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#define NRF51_TO_NRF52840_H
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/*lint ++flb "Enter library region */
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/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices.
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* It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
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* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
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* from the nrf51_deprecated.h file. */
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/* IRQ */
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/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
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#define UART0_IRQHandler UARTE0_UART0_IRQHandler
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#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
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#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
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#define ADC_IRQHandler SAADC_IRQHandler
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#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler
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#define SWI0_IRQHandler SWI0_EGU0_IRQHandler
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#define SWI1_IRQHandler SWI1_EGU1_IRQHandler
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#define SWI2_IRQHandler SWI2_EGU2_IRQHandler
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#define SWI3_IRQHandler SWI3_EGU3_IRQHandler
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#define SWI4_IRQHandler SWI4_EGU4_IRQHandler
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#define SWI5_IRQHandler SWI5_EGU5_IRQHandler
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#define UART0_IRQn UARTE0_UART0_IRQn
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#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
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#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
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#define ADC_IRQn SAADC_IRQn
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#define LPCOMP_IRQn COMP_LPCOMP_IRQn
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#define SWI0_IRQn SWI0_EGU0_IRQn
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#define SWI1_IRQn SWI1_EGU1_IRQn
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#define SWI2_IRQn SWI2_EGU2_IRQn
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#define SWI3_IRQn SWI3_EGU3_IRQn
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#define SWI4_IRQn SWI4_EGU4_IRQn
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#define SWI5_IRQn SWI5_EGU5_IRQn
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/* UICR */
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/* Register RBPCONF was renamed to APPROTECT. */
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#define RBPCONF APPROTECT
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#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos
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#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk
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#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled
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#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled
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/* GPIO */
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/* GPIO port was renamed to P0. */
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#define NRF_GPIO NRF_P0
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#define NRF_GPIO_BASE NRF_P0_BASE
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/* QDEC */
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/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
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#define PSELLED PSEL.LED
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#define PSELA PSEL.A
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#define PSELB PSEL.B
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/* SPIS */
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/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
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#define PSELSCK PSEL.SCK
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#define PSELMISO PSEL.MISO
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#define PSELMOSI PSEL.MOSI
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#define PSELCSN PSEL.CSN
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/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
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#define RXDPTR RXD.PTR
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#define MAXRX RXD.MAXCNT
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#define AMOUNTRX RXD.AMOUNT
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#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos
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#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk
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#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos
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#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk
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/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
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#define TXDPTR TXD.PTR
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#define MAXTX TXD.MAXCNT
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#define AMOUNTTX TXD.AMOUNT
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#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos
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#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk
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#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos
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#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
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/* UART */
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/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
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#define PSELRTS PSEL.RTS
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#define PSELTXD PSEL.TXD
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#define PSELCTS PSEL.CTS
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#define PSELRXD PSEL.RXD
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/* TWI */
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/* The registers PSELSCL, PSELSDA were restructured into a struct. */
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#define PSELSCL PSEL.SCL
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#define PSELSDA PSEL.SDA
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/* From nrf51_deprecated.h */
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/* NVMC */
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/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
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#define ERASEPROTECTEDPAGE ERASEPCR0
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/* IRQ */
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/* COMP module was eliminated. Adapted to nrf52840 headers. */
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#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler
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#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn
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/* REFSEL register redefined enumerated values and added some more. */
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#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
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#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
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#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
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#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
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#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
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#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
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#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
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/* RADIO */
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/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
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#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
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#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
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#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
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#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
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/* FICR */
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/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
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#define DEVICEID0 DEVICEID[0]
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#define DEVICEID1 DEVICEID[1]
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/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
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#define ER0 ER[0]
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#define ER1 ER[1]
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#define ER2 ER[2]
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#define ER3 ER[3]
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/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
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#define IR0 IR[0]
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#define IR1 IR[1]
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#define IR2 IR[2]
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#define IR3 IR[3]
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/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
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#define DEVICEADDR0 DEVICEADDR[0]
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#define DEVICEADDR1 DEVICEADDR[1]
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/* PPI */
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/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
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#define TASKS_CHG0EN TASKS_CHG[0].EN
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#define TASKS_CHG0DIS TASKS_CHG[0].DIS
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#define TASKS_CHG1EN TASKS_CHG[1].EN
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#define TASKS_CHG1DIS TASKS_CHG[1].DIS
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#define TASKS_CHG2EN TASKS_CHG[2].EN
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#define TASKS_CHG2DIS TASKS_CHG[2].DIS
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#define TASKS_CHG3EN TASKS_CHG[3].EN
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#define TASKS_CHG3DIS TASKS_CHG[3].DIS
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/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
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#define CH0_EEP CH[0].EEP
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#define CH0_TEP CH[0].TEP
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#define CH1_EEP CH[1].EEP
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#define CH1_TEP CH[1].TEP
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#define CH2_EEP CH[2].EEP
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#define CH2_TEP CH[2].TEP
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#define CH3_EEP CH[3].EEP
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#define CH3_TEP CH[3].TEP
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#define CH4_EEP CH[4].EEP
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#define CH4_TEP CH[4].TEP
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#define CH5_EEP CH[5].EEP
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#define CH5_TEP CH[5].TEP
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#define CH6_EEP CH[6].EEP
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#define CH6_TEP CH[6].TEP
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#define CH7_EEP CH[7].EEP
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#define CH7_TEP CH[7].TEP
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#define CH8_EEP CH[8].EEP
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#define CH8_TEP CH[8].TEP
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#define CH9_EEP CH[9].EEP
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#define CH9_TEP CH[9].TEP
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#define CH10_EEP CH[10].EEP
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#define CH10_TEP CH[10].TEP
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#define CH11_EEP CH[11].EEP
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#define CH11_TEP CH[11].TEP
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#define CH12_EEP CH[12].EEP
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#define CH12_TEP CH[12].TEP
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#define CH13_EEP CH[13].EEP
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#define CH13_TEP CH[13].TEP
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#define CH14_EEP CH[14].EEP
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#define CH14_TEP CH[14].TEP
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#define CH15_EEP CH[15].EEP
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#define CH15_TEP CH[15].TEP
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/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
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#define CHG0 CHG[0]
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#define CHG1 CHG[1]
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#define CHG2 CHG[2]
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#define CHG3 CHG[3]
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/* All bitfield macros for the CHGx registers therefore changed name. */
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#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
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#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
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#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
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#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
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#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
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#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
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#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
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#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
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#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
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#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
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#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
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#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
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#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
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#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
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#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
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#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
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#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
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#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
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#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
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#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
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#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
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#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
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#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
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#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
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#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
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#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
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#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
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#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
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#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
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#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_TO_NRF52840_H */
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
* nrf52 from Nordic Semiconductor.
|
||||
*
|
||||
* @version V1
|
||||
* @date 30. September 2016
|
||||
* @date 18. November 2016
|
||||
*
|
||||
* @note Generated with SVDConv V2.81d
|
||||
* from CMSIS SVD File 'nrf52.svd' Version 1,
|
||||
|
||||
2417
nrf5/device/nrf52/nrf52840.h
Normal file
2417
nrf5/device/nrf52/nrf52840.h
Normal file
File diff suppressed because it is too large
Load Diff
14633
nrf5/device/nrf52/nrf52840_bitfields.h
Normal file
14633
nrf5/device/nrf52/nrf52840_bitfields.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -1909,7 +1909,8 @@
|
||||
#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
|
||||
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
|
||||
#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
|
||||
#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2001UL) /*!< CIxx - 7x8 WLCSP 56 balls */
|
||||
#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
|
||||
#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */
|
||||
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
|
||||
|
||||
/* Register: FICR_INFO_RAM */
|
||||
@ -11093,18 +11094,21 @@
|
||||
#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
|
||||
#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
|
||||
#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
|
||||
#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */
|
||||
|
||||
/* Bit 1 : NACK received after sending the address (write '1' to clear) */
|
||||
#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
|
||||
#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
|
||||
#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
|
||||
#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
|
||||
#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */
|
||||
|
||||
/* Bit 0 : Overrun error */
|
||||
#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
|
||||
#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
|
||||
#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
|
||||
#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
|
||||
#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */
|
||||
|
||||
/* Register: TWI_ENABLE */
|
||||
/* Description: Enable TWI */
|
||||
@ -11363,6 +11367,12 @@
|
||||
#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
|
||||
#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
|
||||
|
||||
/* Bit 0 : Overrun error */
|
||||
#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
|
||||
#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
|
||||
#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
|
||||
#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
|
||||
|
||||
/* Register: TWIM_ENABLE */
|
||||
/* Description: Enable TWIM */
|
||||
|
||||
@ -11961,6 +11971,7 @@
|
||||
#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
|
||||
#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
|
||||
#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
|
||||
#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
|
||||
#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
|
||||
#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
|
||||
#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
|
||||
@ -12336,6 +12347,7 @@
|
||||
#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
|
||||
#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
|
||||
#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
|
||||
#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
|
||||
#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
|
||||
#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
|
||||
#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
|
||||
|
||||
@ -64,11 +64,6 @@
|
||||
/* Corrected typo in RESULT register. */
|
||||
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
|
||||
|
||||
/* FICR */
|
||||
/* Renamed name of the package. */
|
||||
#define FICR_INFO_PACKAGE_PACKAGE_CH FICR_INFO_PACKAGE_PACKAGE_CI
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF52_NAME_CHANGE_H */
|
||||
|
||||
88
nrf5/device/nrf52/nrf52_to_nrf52840.h
Normal file
88
nrf5/device/nrf52/nrf52_to_nrf52840.h
Normal file
@ -0,0 +1,88 @@
|
||||
/* Copyright (c) 2016, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NRF52_TO_NRF52840_H
|
||||
#define NRF52_TO_NRF52840_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices.
|
||||
* It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
|
||||
* from the nrf52_namechange.h file. */
|
||||
|
||||
/* Differences between latest nRF52 headers and nRF52840 headers. */
|
||||
|
||||
/* UART */
|
||||
/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
|
||||
#define PSELRTS PSEL.RTS
|
||||
#define PSELTXD PSEL.TXD
|
||||
#define PSELCTS PSEL.CTS
|
||||
#define PSELRXD PSEL.RXD
|
||||
|
||||
/* TWI */
|
||||
/* The registers PSELSCL, PSELSDA were restructured into a struct. */
|
||||
#define PSELSCL PSEL.SCL
|
||||
#define PSELSDA PSEL.SDA
|
||||
|
||||
|
||||
/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
|
||||
|
||||
/* I2S */
|
||||
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
|
||||
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
|
||||
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
|
||||
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
|
||||
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
|
||||
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
|
||||
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
|
||||
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
|
||||
|
||||
/* LPCOMP */
|
||||
/* Corrected typo in RESULT register. */
|
||||
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_TO_NRF52840_H */
|
||||
|
||||
209
nrf5/device/nrf52/system_nrf52840.c
Normal file
209
nrf5/device/nrf52/system_nrf52840.c
Normal file
@ -0,0 +1,209 @@
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of ARM nor the names of its contributors may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "system_nrf52840.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#define __SYSTEM_CLOCK_64M (64000000UL)
|
||||
|
||||
static bool errata_36(void);
|
||||
static bool errata_98(void);
|
||||
static bool errata_103(void);
|
||||
static bool errata_115(void);
|
||||
static bool errata_120(void);
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __ICCARM__ )
|
||||
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#endif
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_36()){
|
||||
NRF_CLOCK->EVENTS_DONE = 0;
|
||||
NRF_CLOCK->EVENTS_CTTO = 0;
|
||||
NRF_CLOCK->CTIV = 0;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_98()){
|
||||
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_103()){
|
||||
NRF_CCM->MAXPACKETSIZE = 0xFBul;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_115()){
|
||||
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
|
||||
}
|
||||
|
||||
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_120()){
|
||||
*(volatile uint32_t *)0x40029640ul = 0x200ul;
|
||||
}
|
||||
|
||||
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
|
||||
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
|
||||
* operations are not used in your code. */
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= (3UL << 20) | (3UL << 22);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
|
||||
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
|
||||
normal GPIOs. */
|
||||
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
|
||||
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
|
||||
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
|
||||
reserved for PinReset and not available as normal GPIO. */
|
||||
#if defined (CONFIG_GPIO_AS_PINRESET)
|
||||
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
|
||||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[0] = 18;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[1] = 18;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
|
||||
Specification to see which one). */
|
||||
#if defined (ENABLE_SWO)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
|
||||
Specification to see which ones). */
|
||||
#if defined (ENABLE_TRACE)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
|
||||
static bool errata_36(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool errata_98(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool errata_103(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool errata_115(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool errata_120(void)
|
||||
{
|
||||
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
69
nrf5/device/nrf52/system_nrf52840.h
Normal file
69
nrf5/device/nrf52/system_nrf52840.h
Normal file
@ -0,0 +1,69 @@
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of ARM nor the names of its contributors may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_NRF52_H
|
||||
#define SYSTEM_NRF52_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_NRF52_H */
|
||||
Loading…
Reference in New Issue
Block a user