stm32/system_stm32: Add H7 MCU system initialisation.
This commit is contained in:
iabdalkader
Damien George
parent
81f8f5f163
commit
2e93d4167d
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@ -135,6 +135,17 @@ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8,
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
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4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
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#elif defined(STM32H7)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_2ND (~0xEAF6ED7F)
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#define CONFIG_RCC_PLLCFGR (0x00000000)
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#define SRAM_BASE D1_AXISRAM_BASE
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#define FLASH_BASE FLASH_BANK1_BASE
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uint32_t SystemD2Clock = 64000000;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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#else
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#error Unknown processor
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#endif
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@ -216,16 +227,53 @@ void SystemInit(void)
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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#if defined(STM32H7)
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/* Reset D1CFGR register */
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RCC->D1CFGR = 0x00000000;
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/* Reset D2CFGR register */
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RCC->D2CFGR = 0x00000000;
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/* Reset D3CFGR register */
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RCC->D3CFGR = 0x00000000;
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/* Reset PLLCKSELR register */
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RCC->PLLCKSELR = 0x00000000;
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/* Reset PLL1DIVR register */
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RCC->PLL1DIVR = 0x00000000;
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/* Reset PLL1FRACR register */
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RCC->PLL1FRACR = 0x00000000;
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/* Reset PLL2DIVR register */
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RCC->PLL2DIVR = 0x00000000;
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/* Reset PLL2FRACR register */
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RCC->PLL2FRACR = 0x00000000;
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/* Reset PLL3DIVR register */
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RCC->PLL3DIVR = 0x00000000;
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000;
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#endif
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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RCC->CIR = 0x00000000;
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#elif defined(MCU_SERIES_L4)
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#elif defined(MCU_SERIES_L4) || defined(STM32H7)
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RCC->CIER = 0x00000000;
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#endif
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#if defined(STM32H7)
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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*((__IO uint32_t*)0x51008108) = 0x00000001;
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#endif
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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@ -321,10 +369,18 @@ void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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#if defined(STM32H7)
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
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#endif
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) || defined(STM32H7)
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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/* Enable Power Control clock */
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#if defined(STM32H7)
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MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
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#else
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__PWR_CLK_ENABLE();
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#endif
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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@ -335,10 +391,20 @@ void SystemClock_Config(void)
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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#endif
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#if defined(STM32H7)
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// Wait for PWR_FLAG_VOSRDY
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while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {
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}
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#endif
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) || defined(STM32H7)
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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#if defined(STM32H7)
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RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
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#endif
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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#elif defined(MCU_SERIES_L4)
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
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@ -352,6 +418,9 @@ void SystemClock_Config(void)
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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#if defined(STM32H7)
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RCC_ClkInitStruct.ClockType |= (RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1);
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#endif
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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#if defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
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@ -401,24 +470,55 @@ void SystemClock_Config(void)
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RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
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RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP;
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RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ;
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#if defined(MCU_SERIES_L4)
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#if defined(MCU_SERIES_L4) || defined(STM32H7)
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RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR;
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#endif
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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#if defined(STM32H7)
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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#endif
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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#elif defined(MCU_SERIES_L4)
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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#elif defined(STM32H7)
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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#endif
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#endif
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if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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__fatal_error("HAL_RCC_OscConfig");
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}
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#if defined(STM32H7)
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/* PLL3 for USB Clock */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
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PeriphClkInitStruct.PLL3.PLL3M = 4;
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PeriphClkInitStruct.PLL3.PLL3N = 120;
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PeriphClkInitStruct.PLL3.PLL3P = 2;
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PeriphClkInitStruct.PLL3.PLL3Q = 5;
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PeriphClkInitStruct.PLL3.PLL3R = 2;
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PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1;
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PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
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PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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__fatal_error("HAL_RCCEx_PeriphCLKConfig");
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}
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#endif
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#if defined(MCU_SERIES_F7)
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/* Activate the OverDrive to reach the 200 MHz Frequency */
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if (HAL_PWREx_EnableOverDrive() != HAL_OK)
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@ -436,6 +536,20 @@ void SystemClock_Config(void)
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__fatal_error("HAL_RCC_ClockConfig");
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}
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#if defined(STM32H7)
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/* Activate CSI clock mandatory for I/O Compensation Cell*/
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__HAL_RCC_CSI_ENABLE() ;
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/* Enable SYSCFG clock mandatory for I/O Compensation Cell */
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__HAL_RCC_SYSCFG_CLK_ENABLE() ;
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/* Enable the I/O Compensation Cell */
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HAL_EnableCompensationCell();
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/* Enable the USB voltage level detector */
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HAL_PWREx_EnableUSBVoltageDetector();
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#endif
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#if defined(MCU_SERIES_F7)
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// The DFU bootloader changes the clocksource register from its default power
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// on reset value, so we set it back here, so the clocksources are the same
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@ -486,7 +600,7 @@ void SystemClock_Config(void)
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}
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void HAL_MspInit(void) {
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#if defined(MCU_SERIES_F7)
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#if defined(MCU_SERIES_F7) || defined(STM32H7)
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/* Enable I-Cache */
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SCB_EnableICache();
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