add feather nrf52 uart rts, cts support

This commit is contained in:
hathach 2018-06-08 15:59:38 +07:00
parent c10899d13f
commit 2b3436e87c
3 changed files with 7 additions and 2 deletions

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@ -41,6 +41,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */ /* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20007000; /* tunable */ _heap_end = 0x20020000; /* tunable */
INCLUDE "boards/common.ld" INCLUDE "boards/common.ld"

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@ -114,7 +114,7 @@ int hal_uart_available(NRF_UART_Type * p_instance)
void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init) { void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init) {
hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_uart_init->rx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_pin_clear(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin); hal_gpio_pin_clear(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin);

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@ -49,8 +49,13 @@ void serial_init(void) {
.id = 0, .id = 0,
.rx_pin = &MICROPY_HW_UART1_RX, .rx_pin = &MICROPY_HW_UART1_RX,
.tx_pin = &MICROPY_HW_UART1_TX, .tx_pin = &MICROPY_HW_UART1_TX,
#if MICROPY_HW_UART1_HWFC
.rts_pin = &MICROPY_HW_UART1_RTS,
.cts_pin = &MICROPY_HW_UART1_CTS,
#else
.rts_pin = NULL, .rts_pin = NULL,
.cts_pin = NULL, .cts_pin = NULL,
#endif
.flow_control = MICROPY_HW_UART1_HWFC ? true : false, .flow_control = MICROPY_HW_UART1_HWFC ? true : false,
.use_parity = false, .use_parity = false,
.baud_rate = HAL_UART_BAUD_115K2, .baud_rate = HAL_UART_BAUD_115K2,