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stm32/boards: Split UARTx_RTS_DE into UARTx_RTS/UARTx_DE in pin defs. 

So these alternate functions can be parsed by the build scripts and used in
application code.

Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George 2021-04-13 23:22:08 +10:00
parent 1a2ffda175
commit 25c029ce9f
4 changed files with 17 additions and 17 deletions
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24
ports/stm32/boards/stm32l072_af.csv
View File

@ -1,7 +1,7 @@
Port,Pin,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,,
,,SPI1/SPI2/I2S2/USART1/2/LPUART1/USB/LPTIM1/TSC/TIM2/21/22/EVENTOUT/SYS_AF,SPI1/SPI2/I2S2/I2C1/TIM2/21,SPI1/SPI2/I2S2/LPUART1/USART5/USB/LPTIM1/TIM2/3/EVENTOUT/SYS_AF,I2C1/TSC/EVENTOUT,I2C1/USART1/2/LPUART1/TIM3/22/EVENTOUT,SPI2/I2S2/I2C2/USART1/TIM2/21/22,I2C1/2/LPUART1/USART4/UASRT5/TIM21/EVENTOUT,I2C3/LPUART1/COMP1/2/TIM3,,ADC
PortA,PA0,,,TIM2_CH1,TSC_G1_IO1,USART2_CTS,TIM2_ETR,USART4_TX,COMP1_OUT,,ADC_IN0
PortA,PA1,EVENTOUT,,TIM2_CH2,TSC_G1_IO2,USART2_RTS_DE,TIM21_ETR,USART4_RX,,,ADC_IN1
PortA,PA1,EVENTOUT,,TIM2_CH2,TSC_G1_IO2,USART2_RTS/USART2_DE,TIM21_ETR,USART4_RX,,,ADC_IN1
PortA,PA2,TIM21_CH1,,TIM2_CH3,TSC_G1_IO3,USART2_TX,,LPUART1_TX,COMP2_OUT,,ADC_IN2
PortA,PA3,TIM21_CH2,,TIM2_CH4,TSC_G1_IO4,USART2_RX,,LPUART1_RX,,,ADC_IN3
PortA,PA4,SPI1_NSS,,,TSC_G2_IO1,USART2_CK,TIM22_ETR,,,,ADC_IN4
@ -12,25 +12,25 @@ PortA,PA8,MCO,,USB_CRS_SYNC,EVENTOUT,USART1_CK,,,I2C3_SCL,,
PortA,PA9,MCO,,,TSC_G4_IO1,USART1_TX,,I2C1_SCL,I2C3_SMBA,,
PortA,PA10,,,,TSC_G4_IO2,USART1_RX,,I2C1_SDA,,,
PortA,PA11,SPI1_MISO,,EVENTOUT,TSC_G4_IO3,USART1_CTS,,,COMP1_OUT,,
PortA,PA12,SPI1_MOSI,,EVENTOUT,TSC_G4_IO4,USART1_RTS_DE,,,COMP2_OUT,,
PortA,PA12,SPI1_MOSI,,EVENTOUT,TSC_G4_IO4,USART1_RTS/USART1_DE,,,COMP2_OUT,,
PortA,PA13,SWDIO,,USB_NOE,,,,LPUART1_RX,,,
PortA,PA14,SWCLK,,,,USART2_TX,,LPUART1_TX,,,
PortA,PA15,SPI1_NSS,,TIM2_ETR,EVENTOUT,USART2_RX,TIM2_CH1,USART4_RTS_DE,,,
PortA,PA15,SPI1_NSS,,TIM2_ETR,EVENTOUT,USART2_RX,TIM2_CH1,USART4_RTS/USART4_DE,,,
PortB,PB0,EVENTOUT,,TIM3_CH3,TSC_G3_IO2,,,,,,ADC_IN8
PortB,PB1,,,TIM3_CH4,TSC_G3_IO3,LPUART1_RTS_DE,,,,,ADC_IN9
PortB,PB1,,,TIM3_CH4,TSC_G3_IO3,LPUART1_RTS/LPUART1_DE,,,,,ADC_IN9
PortB,PB2,,,LPTIM1_OUT,TSC_G3_IO4,,,,I2C3_SMBA,,
PortB,PB3,SPI1_SCK,,TIM2_CH2,TSC_G5_IO1,EVENTOUT,USART1_RTS_DE,USART5_TX,,,
PortB,PB3,SPI1_SCK,,TIM2_CH2,TSC_G5_IO1,EVENTOUT,USART1_RTS/USART1_DE,USART5_TX,,,
PortB,PB4,SPI1_MISO,,TIM3_CH1,TSC_G5_IO2,TIM22_CH1,USART1_CTS,USART5_RX,I2C3_SDA,,
PortB,PB5,SPI1_MOSI,,LPTIM1_IN1,I2C1_SMBA,TIM3_CH2/TIM22_CH2,USART1_CK,USART5_CK/USART5_RTS_DE,,,
PortB,PB5,SPI1_MOSI,,LPTIM1_IN1,I2C1_SMBA,TIM3_CH2/TIM22_CH2,USART1_CK,USART5_CK/USART5_RTS/USART5_DE,,,
PortB,PB6,USART1_TX,I2C1_SCL,LPTIM1_ETR,TSC_G5_IO3,,,,,,
PortB,PB7,USART1_RX,I2C1_SDA,LPTIM1_IN2,TSC_G5_IO4,,,USART4_CTS,,,
PortB,PB8,,,,TSC_SYNC,I2C1_SCL,,,,,
PortB,PB9,,,EVENTOUT,,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,
PortB,PB10,,,TIM2_CH3,TSC_SYNC,LPUART1_TX,SPI2_SCK,I2C2_SCL,LPUART1_RX,,
PortB,PB11,EVENTOUT,,TIM2_CH4,TSC_G6_IO1,LPUART1_RX,,I2C2_SDA,LPUART1_TX,,
PortB,PB12,SPI2_NSS/I2S2_WS,,LPUART1_RTS_DE,TSC_G6_IO2,I2C2_SMBA,,EVENTOUT,,,
PortB,PB12,SPI2_NSS/I2S2_WS,,LPUART1_RTS/LPUART1_DE,TSC_G6_IO2,I2C2_SMBA,,EVENTOUT,,,
PortB,PB13,SPI2_SCK/I2S2_CK,,MCO,TSC_G6_IO3,LPUART1_CTS,I2C2_SCL,TIM21_CH1,,,
PortB,PB14,SPI2_MISO/I2S2_MCK,,RTC_OUT,TSC_G6_IO4,LPUART1_RTS_DE,I2C2_SDA,TIM21_CH2,,,
PortB,PB14,SPI2_MISO/I2S2_MCK,,RTC_OUT,TSC_G6_IO4,LPUART1_RTS/LPUART1_DE,I2C2_SDA,TIM21_CH2,,,
PortB,PB15,SPI2_MOSI/I2S2_SD,,RTC_REFIN,,,,,,,
PortC,PC0,LPTIM1_IN1,,EVENTOUT,TSC_G7_IO1,,,LPUART1_RX,I2C3_SCL,,ADC_IN10
PortC,PC1,LPTIM1_OUT,,EVENTOUT,TSC_G7_IO2,,,LPUART1_TX,I2C3_SDA,,ADC_IN11
@ -50,9 +50,9 @@ PortC,PC14,,,,,,,,,,
PortC,PC15,,,,,,,,,,
PortD,PD0,TIM21_CH1,SPI2_NSS/I2S2_WS,,,,,,,,
PortD,PD1,,SPI2_SCK/I2S2_CK,,,,,,,,
PortD,PD2,LPUART1_RTS_DE,,TIM3_ETR,,,,USART5_RX,,,
PortD,PD2,LPUART1_RTS/LPUART1_DE,,TIM3_ETR,,,,USART5_RX,,,
PortD,PD3,USART2_CTS,,SPI2_MISO/I2S2_MCK,,,,,,,
PortD,PD4,USART2_RTS_DE,SPI2_MOSI/I2S2_SD,,,,,,,,
PortD,PD4,USART2_RTS/USART2_DE,SPI2_MOSI/I2S2_SD,,,,,,,,
PortD,PD5,USART2_TX,,,,,,,,,
PortD,PD6,USART2_RX,,,,,,,,,
PortD,PD7,USART2_CK,TIM21_CH2,,,,,,,,
@ -60,7 +60,7 @@ PortD,PD8,LPUART1_TX,,,,,,,,,
PortD,PD9,LPUART1_RX,,,,,,,,,
PortD,PD10,,,,,,,,,,
PortD,PD11,LPUART1_CTS,,,,,,,,,
PortD,PD12,LPUART1_RTS_DE,,,,,,,,,
PortD,PD12,LPUART1_RTS/LPUART1_DE,,,,,,,,,
PortD,PD13,,,,,,,,,,
PortD,PD14,,,,,,,,,,
PortD,PD15,USB_CRS_SYNC,,,,,,,,,
@ -71,7 +71,7 @@ PortE,PE3,TIM22_CH1,,TIM3_CH1,,,,,,,
PortE,PE4,TIM22_CH2,,TIM3_CH2,,,,,,,
PortE,PE5,TIM21_CH1,,TIM3_CH3,,,,,,,
PortE,PE6,TIM21_CH2,,TIM3_CH4,,,,,,,
PortE,PE7,,,,,,,USART5_CK/USART5_RTS_DE,,,
PortE,PE7,,,,,,,USART5_CK/USART5_RTS/USART5_DE,,,
PortE,PE8,,,,,,,USART4_TX,,,
PortE,PE9,TIM2_CH1,,TIM2_ETR,,,,USART4_RX,,,
PortE,PE10,TIM2_CH2,,,,,,USART5_TX,,,

1 Port Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
2 SPI1/SPI2/I2S2/USART1/2/LPUART1/USB/LPTIM1/TSC/TIM2/21/22/EVENTOUT/SYS_AF SPI1/SPI2/I2S2/I2C1/TIM2/21 SPI1/SPI2/I2S2/LPUART1/USART5/USB/LPTIM1/TIM2/3/EVENTOUT/SYS_AF I2C1/TSC/EVENTOUT I2C1/USART1/2/LPUART1/TIM3/22/EVENTOUT SPI2/I2S2/I2C2/USART1/TIM2/21/22 I2C1/2/LPUART1/USART4/UASRT5/TIM21/EVENTOUT I2C3/LPUART1/COMP1/2/TIM3 ADC
3 PortA PA0 TIM2_CH1 TSC_G1_IO1 USART2_CTS TIM2_ETR USART4_TX COMP1_OUT ADC_IN0
4 PortA PA1 EVENTOUT TIM2_CH2 TSC_G1_IO2 USART2_RTS_DE USART2_RTS/USART2_DE TIM21_ETR USART4_RX ADC_IN1
5 PortA PA2 TIM21_CH1 TIM2_CH3 TSC_G1_IO3 USART2_TX LPUART1_TX COMP2_OUT ADC_IN2
6 PortA PA3 TIM21_CH2 TIM2_CH4 TSC_G1_IO4 USART2_RX LPUART1_RX ADC_IN3
7 PortA PA4 SPI1_NSS TSC_G2_IO1 USART2_CK TIM22_ETR ADC_IN4
12 PortA PA9 MCO TSC_G4_IO1 USART1_TX I2C1_SCL I2C3_SMBA
13 PortA PA10 TSC_G4_IO2 USART1_RX I2C1_SDA
14 PortA PA11 SPI1_MISO EVENTOUT TSC_G4_IO3 USART1_CTS COMP1_OUT
15 PortA PA12 SPI1_MOSI EVENTOUT TSC_G4_IO4 USART1_RTS_DE USART1_RTS/USART1_DE COMP2_OUT
16 PortA PA13 SWDIO USB_NOE LPUART1_RX
17 PortA PA14 SWCLK USART2_TX LPUART1_TX
18 PortA PA15 SPI1_NSS TIM2_ETR EVENTOUT USART2_RX TIM2_CH1 USART4_RTS_DE USART4_RTS/USART4_DE
19 PortB PB0 EVENTOUT TIM3_CH3 TSC_G3_IO2 ADC_IN8
20 PortB PB1 TIM3_CH4 TSC_G3_IO3 LPUART1_RTS_DE LPUART1_RTS/LPUART1_DE ADC_IN9
21 PortB PB2 LPTIM1_OUT TSC_G3_IO4 I2C3_SMBA
22 PortB PB3 SPI1_SCK TIM2_CH2 TSC_G5_IO1 EVENTOUT USART1_RTS_DE USART1_RTS/USART1_DE USART5_TX
23 PortB PB4 SPI1_MISO TIM3_CH1 TSC_G5_IO2 TIM22_CH1 USART1_CTS USART5_RX I2C3_SDA
24 PortB PB5 SPI1_MOSI LPTIM1_IN1 I2C1_SMBA TIM3_CH2/TIM22_CH2 USART1_CK USART5_CK/USART5_RTS_DE USART5_CK/USART5_RTS/USART5_DE
25 PortB PB6 USART1_TX I2C1_SCL LPTIM1_ETR TSC_G5_IO3
26 PortB PB7 USART1_RX I2C1_SDA LPTIM1_IN2 TSC_G5_IO4 USART4_CTS
27 PortB PB8 TSC_SYNC I2C1_SCL
28 PortB PB9 EVENTOUT I2C1_SDA SPI2_NSS/I2S2_WS
29 PortB PB10 TIM2_CH3 TSC_SYNC LPUART1_TX SPI2_SCK I2C2_SCL LPUART1_RX
30 PortB PB11 EVENTOUT TIM2_CH4 TSC_G6_IO1 LPUART1_RX I2C2_SDA LPUART1_TX
31 PortB PB12 SPI2_NSS/I2S2_WS LPUART1_RTS_DE LPUART1_RTS/LPUART1_DE TSC_G6_IO2 I2C2_SMBA EVENTOUT
32 PortB PB13 SPI2_SCK/I2S2_CK MCO TSC_G6_IO3 LPUART1_CTS I2C2_SCL TIM21_CH1
33 PortB PB14 SPI2_MISO/I2S2_MCK RTC_OUT TSC_G6_IO4 LPUART1_RTS_DE LPUART1_RTS/LPUART1_DE I2C2_SDA TIM21_CH2
34 PortB PB15 SPI2_MOSI/I2S2_SD RTC_REFIN
35 PortC PC0 LPTIM1_IN1 EVENTOUT TSC_G7_IO1 LPUART1_RX I2C3_SCL ADC_IN10
36 PortC PC1 LPTIM1_OUT EVENTOUT TSC_G7_IO2 LPUART1_TX I2C3_SDA ADC_IN11
50 PortC PC15
51 PortD PD0 TIM21_CH1 SPI2_NSS/I2S2_WS
52 PortD PD1 SPI2_SCK/I2S2_CK
53 PortD PD2 LPUART1_RTS_DE LPUART1_RTS/LPUART1_DE TIM3_ETR USART5_RX
54 PortD PD3 USART2_CTS SPI2_MISO/I2S2_MCK
55 PortD PD4 USART2_RTS_DE USART2_RTS/USART2_DE SPI2_MOSI/I2S2_SD
56 PortD PD5 USART2_TX
57 PortD PD6 USART2_RX
58 PortD PD7 USART2_CK TIM21_CH2
60 PortD PD9 LPUART1_RX
61 PortD PD10
62 PortD PD11 LPUART1_CTS
63 PortD PD12 LPUART1_RTS_DE LPUART1_RTS/LPUART1_DE
64 PortD PD13
65 PortD PD14
66 PortD PD15 USB_CRS_SYNC
71 PortE PE4 TIM22_CH2 TIM3_CH2
72 PortE PE5 TIM21_CH1 TIM3_CH3
73 PortE PE6 TIM21_CH2 TIM3_CH4
74 PortE PE7 USART5_CK/USART5_RTS_DE USART5_CK/USART5_RTS/USART5_DE
75 PortE PE8 USART4_TX
76 PortE PE9 TIM2_CH1 TIM2_ETR USART4_RX
77 PortE PE10 TIM2_CH2 USART5_TX

2
ports/stm32/boards/stm32l452_af.csv
View File

@ -30,7 +30,7 @@ PortB,PB10,,TIM2_CH3,,I2C4_SCL,I2C2_SCL,SPI2_SCK,,USART3_TX,LPUART1_RX,TSC_SYNC,
PortB,PB11,,TIM2_CH4,,I2C4_SDA,I2C2_SDA,,,USART3_RX,LPUART1_TX,,QUADSPI_NCS,,COMP2_OUT,,,EVENTOUT,,,
PortB,PB12,,TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,DFSDM_DATIN1,USART3_CK,LPUART1_RTS/LPUART1_DE,TSC_G1_IO1,CAN1_RX,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT,,,
PortB,PB13,,TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,DFSDM_CKIN1,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,CAN1_TX,,,SAI1_SCK_A,TIM15_CH1N,EVENTOUT,,,
PortB,PB14,,TIM1_CH2N,,,I2C2_SDA,SPI2_MISO,DFSDM_DATIN2,USART3_RTS_DE,,TSC_G1_IO3,,,,SAI1_MCLK_A,TIM15_CH1,EVENTOUT,,,
PortB,PB14,,TIM1_CH2N,,,I2C2_SDA,SPI2_MISO,DFSDM_DATIN2,USART3_RTS/USART3_DE,,TSC_G1_IO3,,,,SAI1_MCLK_A,TIM15_CH1,EVENTOUT,,,
PortB,PB15,RTC_REFIN,TIM1_CH3N,,,,SPI2_MOSI,DFSDM_CKIN2,,,TSC_G1_IO4,,,,SAI1_SD_A,TIM15_CH2,EVENTOUT,,,
PortC,PC0,,LPTIM1_IN1,I2C4_SCL,,I2C3_SCL,,,,LPUART1_RX,,,,,,LPTIM2_IN1,EVENTOUT,ADC123_IN1,,
PortC,PC1,TRACED0,LPTIM1_OUT,I2C4_SDA,,I2C3_SDA,,,,LPUART1_TX,,,,,,,EVENTOUT,ADC123_IN2,,

1 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
30 PortB PB11 TIM2_CH4 I2C4_SDA I2C2_SDA USART3_RX LPUART1_TX QUADSPI_NCS COMP2_OUT EVENTOUT
31 PortB PB12 TIM1_BKIN TIM1_BKIN_COMP2 I2C2_SMBA SPI2_NSS DFSDM_DATIN1 USART3_CK LPUART1_RTS/LPUART1_DE TSC_G1_IO1 CAN1_RX SAI1_FS_A TIM15_BKIN EVENTOUT
32 PortB PB13 TIM1_CH1N I2C2_SCL SPI2_SCK DFSDM_CKIN1 USART3_CTS LPUART1_CTS TSC_G1_IO2 CAN1_TX SAI1_SCK_A TIM15_CH1N EVENTOUT
33 PortB PB14 TIM1_CH2N I2C2_SDA SPI2_MISO DFSDM_DATIN2 USART3_RTS_DE USART3_RTS/USART3_DE TSC_G1_IO3 SAI1_MCLK_A TIM15_CH1 EVENTOUT
34 PortB PB15 RTC_REFIN TIM1_CH3N SPI2_MOSI DFSDM_CKIN2 TSC_G1_IO4 SAI1_SD_A TIM15_CH2 EVENTOUT
35 PortC PC0 LPTIM1_IN1 I2C4_SCL I2C3_SCL LPUART1_RX LPTIM2_IN1 EVENTOUT ADC123_IN1
36 PortC PC1 TRACED0 LPTIM1_OUT I2C4_SDA I2C3_SDA LPUART1_TX EVENTOUT ADC123_IN2

2
ports/stm32/boards/stm32l476_af.csv
View File

@ -30,7 +30,7 @@ PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK,DFSDM_DATIN7,USART3_TX,LPUART1_RX,,QUAD
PortB,PB11,,TIM2_CH4,,,I2C2_SDA,,DFSDM_CKIN7,USART3_RX,LPUART1_TX,,QUADSPI_NCS,LCD_SEG11,COMP2_OUT,,,EVENTOUT,,
PortB,PB12,,TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,DFSDM_DATIN1,USART3_CK,LPUART1_RTS/LPUART1_DE,TSC_G1_IO1,,LCD_SEG12,SWPMI1_IO,SAI2_FS_A,TIM15_BKIN,EVENTOUT,,
PortB,PB13,,TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,DFSDM_CKIN1,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,,LCD_SEG13,SWPMI1_TX,SAI2_SCK_A,TIM15_CH1N,EVENTOUT,,
PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,I2C2_SDA,SPI2_MISO,DFSDM_DATIN2,USART3_RTS_DE,,TSC_G1_IO3,,LCD_SEG14,SWPMI1_RX,SAI2_MCLK_A,TIM15_CH1,EVENTOUT,,
PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,I2C2_SDA,SPI2_MISO,DFSDM_DATIN2,USART3_RTS/USART3_DE,,TSC_G1_IO3,,LCD_SEG14,SWPMI1_RX,SAI2_MCLK_A,TIM15_CH1,EVENTOUT,,
PortB,PB15,RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI,DFSDM_CKIN2,,,TSC_G1_IO4,,LCD_SEG15,SWPMI1_SUSPEND,SAI2_SD_A,TIM15_CH2,EVENTOUT,,
PortC,PC0,,LPTIM1_IN1,,,I2C3_SCL,,DFSDM_DATIN4,,LPUART1_RX,,,LCD_SEG18,,,LPTIM2_IN1,EVENTOUT,ADC123_IN1,
PortC,PC1,,LPTIM1_OUT,,,I2C3_SDA,,DFSDM_CKIN4,,LPUART1_TX,,,LCD_SEG19,,,,EVENTOUT,ADC123_IN2,

1 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
30 PortB PB11 TIM2_CH4 I2C2_SDA DFSDM_CKIN7 USART3_RX LPUART1_TX QUADSPI_NCS LCD_SEG11 COMP2_OUT EVENTOUT
31 PortB PB12 TIM1_BKIN TIM1_BKIN_COMP2 I2C2_SMBA SPI2_NSS DFSDM_DATIN1 USART3_CK LPUART1_RTS/LPUART1_DE TSC_G1_IO1 LCD_SEG12 SWPMI1_IO SAI2_FS_A TIM15_BKIN EVENTOUT
32 PortB PB13 TIM1_CH1N I2C2_SCL SPI2_SCK DFSDM_CKIN1 USART3_CTS LPUART1_CTS TSC_G1_IO2 LCD_SEG13 SWPMI1_TX SAI2_SCK_A TIM15_CH1N EVENTOUT
33 PortB PB14 TIM1_CH2N TIM8_CH2N I2C2_SDA SPI2_MISO DFSDM_DATIN2 USART3_RTS_DE USART3_RTS/USART3_DE TSC_G1_IO3 LCD_SEG14 SWPMI1_RX SAI2_MCLK_A TIM15_CH1 EVENTOUT
34 PortB PB15 RTC_REFIN TIM1_CH3N TIM8_CH3N SPI2_MOSI DFSDM_CKIN2 TSC_G1_IO4 LCD_SEG15 SWPMI1_SUSPEND SAI2_SD_A TIM15_CH2 EVENTOUT
35 PortC PC0 LPTIM1_IN1 I2C3_SCL DFSDM_DATIN4 LPUART1_RX LCD_SEG18 LPTIM2_IN1 EVENTOUT ADC123_IN1
36 PortC PC1 LPTIM1_OUT I2C3_SDA DFSDM_CKIN4 LPUART1_TX LCD_SEG19 EVENTOUT ADC123_IN2

6
ports/stm32/boards/stm32wb55_af.csv
View File

@ -12,14 +12,14 @@ PortA,PA8,MCO,TIM1_CH1,,SAI1_PDM_CK2,,,,USART1_CK,,,,LCD_COM0,,SAI1_SCK_A,LPTIM2
PortA,PA9,,TIM1_CH2,,SAI1_PDM_DI2,I2C1_SCL,SPI2_SCK,,USART1_TX,,,,LCD_COM1,,SAI1_FS_A,,EVENTOUT,ADC1_IN16
PortA,PA10,,TIM1_CH3,,SAI1_PDM_DI1,I2C1_SDA,,,USART1_RX,,,USB_CRS_SYNC,LCD_COM2,,SAI1_SD_A,TIM17_BKIN,EVENTOUT,
PortA,PA11,,TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,,USART1_CTS,,,USB_DM,,TIM1_BKIN2,,,EVENTOUT,
PortA,PA12,,TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS_DE,LPUART1_RX,,USB_DP,,,,,EVENTOUT,
PortA,PA12,,TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS/USART1_DE,LPUART1_RX,,USB_DP,,,,,EVENTOUT,
PortA,PA13,JTMS/SWDIO,,,,,,,,IR_OUT,,USB_NOE,,,SAI1_SD_B,,EVENTOUT,
PortA,PA14,JTCK/SWCLK,LPTIM1_OUT,,,I2C1_SMBA,,,,,,,LCD_SEG5,,SAI1_FS_B,,EVENTOUT,
PortA,PA15,JTDI,TIM2_CH1,TIM2_ETR,,,SPI1_NSS,,,,TSC_G3_IO1,,LCD_SEG17,,,,EVENTOUT,
PortB,PB0,,,,,,,EXT_PA_TX,,,,,,COMP1_OUT,,,EVENTOUT,
PortB,PB1,,,,,,,,,LPUART1_RTS_DE,,,,,,LPTIM2_IN1,EVENTOUT,
PortB,PB1,,,,,,,,,LPUART1_RTS/LPUART1_DE,,,,,,LPTIM2_IN1,EVENTOUT,
PortB,PB2,RTC_OUT,LPTIM1_OUT,,,I2C3_SMBA,SPI1_NSS,,,,,,LCD_VLCD,,SAI1_EXTCLK,,EVENTOUT,
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,,USART1_RTS_DE,,,,LCD_SEG7,,SAI1_SCK_B,,EVENTOUT,
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,,USART1_RTS/USART1_DE,,,,LCD_SEG7,,SAI1_SCK_B,,EVENTOUT,
PortB,PB4,NJTRST,,,,I2C3_SDA,SPI1_MISO,,USART1_CTS,,TSC_G2_IO1,,LCD_SEG8,,SAI1_MCLK_B,TIM17_BKIN,EVENTOUT,
PortB,PB5,,LPTIM1_IN1,,,I2C1_SMBA,SPI1_MOSI,,USART1_CK,LPUART1_TX,TSC_G2_IO2,,LCD_SEG9,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT,
PortB,PB6,MCO,LPTIM1_ETR,,,I2C1_SCL,,,USART1_TX,,TSC_G2_IO3,,LCD_SEG6,,SAI1_FS_B,TIM16_CH1N,EVENTOUT,

1 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
12 PortA PA9 TIM1_CH2 SAI1_PDM_DI2 I2C1_SCL SPI2_SCK USART1_TX LCD_COM1 SAI1_FS_A EVENTOUT ADC1_IN16
13 PortA PA10 TIM1_CH3 SAI1_PDM_DI1 I2C1_SDA USART1_RX USB_CRS_SYNC LCD_COM2 SAI1_SD_A TIM17_BKIN EVENTOUT
14 PortA PA11 TIM1_CH4 TIM1_BKIN2 SPI1_MISO USART1_CTS USB_DM TIM1_BKIN2 EVENTOUT
15 PortA PA12 TIM1_ETR SPI1_MOSI USART1_RTS_DE USART1_RTS/USART1_DE LPUART1_RX USB_DP EVENTOUT
16 PortA PA13 JTMS/SWDIO IR_OUT USB_NOE SAI1_SD_B EVENTOUT
17 PortA PA14 JTCK/SWCLK LPTIM1_OUT I2C1_SMBA LCD_SEG5 SAI1_FS_B EVENTOUT
18 PortA PA15 JTDI TIM2_CH1 TIM2_ETR SPI1_NSS TSC_G3_IO1 LCD_SEG17 EVENTOUT
19 PortB PB0 EXT_PA_TX COMP1_OUT EVENTOUT
20 PortB PB1 LPUART1_RTS_DE LPUART1_RTS/LPUART1_DE LPTIM2_IN1 EVENTOUT
21 PortB PB2 RTC_OUT LPTIM1_OUT I2C3_SMBA SPI1_NSS LCD_VLCD SAI1_EXTCLK EVENTOUT
22 PortB PB3 JTDO/TRACESWO TIM2_CH2 SPI1_SCK USART1_RTS_DE USART1_RTS/USART1_DE LCD_SEG7 SAI1_SCK_B EVENTOUT
23 PortB PB4 NJTRST I2C3_SDA SPI1_MISO USART1_CTS TSC_G2_IO1 LCD_SEG8 SAI1_MCLK_B TIM17_BKIN EVENTOUT
24 PortB PB5 LPTIM1_IN1 I2C1_SMBA SPI1_MOSI USART1_CK LPUART1_TX TSC_G2_IO2 LCD_SEG9 COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT
25 PortB PB6 MCO LPTIM1_ETR I2C1_SCL USART1_TX TSC_G2_IO3 LCD_SEG6 SAI1_FS_B TIM16_CH1N EVENTOUT