stm32: Include .ARM section in firmware for C++ exception handling.
Support for C++ was added in 97960dc7de
but
that commit didn't include the C++ exception handling table in the binary
firmware image. This commit fixes that.
Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
parent
2d8aecd2ad
commit
25ae169e6e
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@ -643,7 +643,7 @@ TEXT0_ADDR ?= 0x08000000
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ifeq ($(TEXT1_ADDR),)
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# No TEXT1_ADDR given so put all firmware at TEXT0_ADDR location
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TEXT0_SECTIONS ?= .isr_vector .text .data
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TEXT0_SECTIONS ?= .isr_vector .text .data .ARM
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deploy-stlink: $(BUILD)/firmware.bin
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$(call RUN_STLINK,$^,$(TEXT0_ADDR))
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@ -661,7 +661,7 @@ else
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# TEXT0_ADDR and TEXT1_ADDR are specified so split firmware between these locations
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TEXT0_SECTIONS ?= .isr_vector
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TEXT1_SECTIONS ?= .text .data
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TEXT1_SECTIONS ?= .text .data .ARM
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deploy-stlink: $(BUILD)/firmware0.bin $(BUILD)/firmware1.bin
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$(call RUN_STLINK,$(word 1,$^),$(TEXT0_ADDR))
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@ -6,7 +6,7 @@ AF_FILE = boards/stm32f722_af.csv
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LD_FILES = boards/PYBD_SF2/f722_qspi.ld
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TEXT0_ADDR = 0x08008000
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TEXT1_ADDR = 0x90000000
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TEXT0_SECTIONS = .isr_vector .text .data
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TEXT0_SECTIONS = .isr_vector .text .data .ARM
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TEXT1_SECTIONS = .text_ext
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# MicroPython settings
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@ -6,7 +6,7 @@ AF_FILE = boards/stm32f722_af.csv
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LD_FILES = boards/PYBD_SF2/f722_qspi.ld
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TEXT0_ADDR = 0x08008000
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TEXT1_ADDR = 0x90000000
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TEXT0_SECTIONS = .isr_vector .text .data
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TEXT0_SECTIONS = .isr_vector .text .data .ARM
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TEXT1_SECTIONS = .text_ext
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# MicroPython settings
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@ -22,7 +22,7 @@ ifeq ($(USE_QSPI_XIP),1)
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LD_FILES = boards/STM32F769DISC/f769_qspi.ld
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TEXT0_ADDR = 0x08020000
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TEXT1_ADDR = 0x90000000
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TEXT0_SECTIONS = .isr_vector .text .data
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TEXT0_SECTIONS = .isr_vector .text .data .ARM
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TEXT1_SECTIONS = .text_qspi
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else
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