stm: Increase timeout for RTC LSE startup; use backup regs.
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e4b6a079b3
commit
217814cc63
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@ -655,7 +655,7 @@ soft_reset:
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rt_store_attr(m, MP_QSTR_mma_mode, (mp_obj_t)&pyb_mma_write_mode_obj);
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#endif
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rt_store_attr(m, MP_QSTR_hid, rt_make_function_n(1, pyb_hid_send_report));
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#if MICROPY_HW_HAS_RTC
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#if MICROPY_HW_ENABLE_RTC
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rt_store_attr(m, MP_QSTR_time, rt_make_function_n(0, pyb_rtc_read));
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#endif
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#if MICROPY_HW_ENABLE_RNG
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30
stm/rtc.c
30
stm/rtc.c
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@ -8,8 +8,20 @@
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#include "rtc.h"
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void rtc_init(void) {
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uint32_t rtc_clksrc;
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uint32_t timeout = 1000000;
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/* Enable the PWR clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Allow access to RTC */
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PWR_BackupAccessCmd(ENABLE);
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if (RTC_ReadBackupRegister(RTC_BKP_DR0) == 0x32F2) {
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// RTC still alive, so don't re-init it
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// wait for RTC APB register synchronisation
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RTC_WaitForSynchro();
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return;
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}
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uint32_t timeout = 10000000;
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/* Enable the PWR clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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@ -26,7 +38,10 @@ void rtc_init(void) {
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/* If LSE timed out, use LSI instead */
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if (timeout == 0) {
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/* Enable the LSI OSC */
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// Disable the LSE OSC
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RCC_LSEConfig(RCC_LSE_OFF);
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// Enable the LSI OSC
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RCC_LSICmd(ENABLE);
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/* Wait till LSI is ready */
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@ -34,15 +49,12 @@ void rtc_init(void) {
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}
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/* Use LSI as the RTC Clock Source */
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rtc_clksrc = RCC_RTCCLKSource_LSI;
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RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI);
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} else {
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/* Use LSE as the RTC Clock Source */
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rtc_clksrc = RCC_RTCCLKSource_LSE;
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RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
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}
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/* Select the RTC Clock Source */
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RCC_RTCCLKConfig(rtc_clksrc);
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/* Note: LSI is around (32KHz), these dividers should work either way */
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/* ck_spre(1Hz) = RTCCLK(LSE) /(uwAsynchPrediv + 1)*(uwSynchPrediv + 1)*/
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uint32_t uwSynchPrediv = 0xFF;
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@ -78,7 +90,7 @@ void rtc_init(void) {
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RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure);
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// Indicator for the RTC configuration
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//RTC_WriteBackupRegister(RTC_BKP_DR0, 0x32F2);
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RTC_WriteBackupRegister(RTC_BKP_DR0, 0x32F2);
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}
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/******************************************************************************/
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