From 1bd9003338306fd6c307ea1bd3fdd7920e204804 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 22 Jan 2017 23:04:25 +0100 Subject: [PATCH] nrf5/hal: Adding more types to quad SPI header. --- nrf5/hal/hal_qspie.h | 53 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/nrf5/hal/hal_qspie.h b/nrf5/hal/hal_qspie.h index 0916678824..c62d32ac51 100644 --- a/nrf5/hal/hal_qspie.h +++ b/nrf5/hal/hal_qspie.h @@ -47,12 +47,57 @@ typedef enum { } hal_qspi_clk_freq_t; /** - * @brief Quad SPI mode configuration type definition + * @brief Quad SPI mode type definition */ typedef enum { - HAL_QSPI_MODE_SINGLE_LINE, - HAL_QSPI_MODE_DUAL_LINE, - HAL_QSPI_MODE_QUAL_LINE + HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge) + HAL_SPI_MODE_CPOL1_CPHA1 = 3 // CPOL = 1, CPHA = 1 (data on trailing edge) } hal_qspi_mode_t; +/** + * @brief Quad SPI data line configuration type definition + */ +typedef enum { + HAL_QSPI_DATA_LINE_SINGLE, + HAL_QSPI_DATA_LINE_DUAL, + HAL_QSPI_DATA_LINE_QUAL +} hal_qspi_data_line_t; + + + +/** + * @brief Quad SPI Configuration Structure definition + */ +typedef struct { + uint8_t d0_mosi_pin; + uint8_t d1_miso_pin; + uint8_t d2_pin; + uint8_t d3_pin; + uint8_t clk_pin; + uint8_t d0_mosi_pin_port; + uint8_t d1_miso_pin_port; + uint8_t d2_pin_port; + uint8_t d3_pin_port; + uint8_t clk_pin_port; + hal_qspi_mode_t mode; + hal_qspi_data_line_t data_line; + hal_qspi_clk_freq_t freq; +} hal_qspi_init_t; + +/** + * @brief Quad SPI handle Structure definition + */ +typedef struct __QSPI_HandleTypeDef +{ + NRF_QSPI_Type *instance; /* QSPI registers base address */ + hal_qspi_init_t init; /* QSPI initialization parameters */ +} QSPI_HandleTypeDef; + +void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init); + +void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance, + uint16_t transfer_size, + const uint8_t * tx_data, + uint8_t * rx_data); + #endif // HAL_QSPIE_H__