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Remove unnecessary USB files from stm.

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This commit is contained in:
Damien 2013-10-22 16:23:53 +01:00
parent d276f6357e
commit 1b50affca8
6 changed files with 0 additions and 1886 deletions
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262
stm/lib/usb_hcd.c
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@ -1,262 +0,0 @@
/**
******************************************************************************
* @file usb_hcd.c
* @author MCD Application Team
* @version V2.1.0
* @date 19-March-2012
* @brief Host Interface Layer
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "usb_core.h"
#include "usb_hcd.h"
#include "usb_conf.h"
#include "usb_bsp.h"
/** @addtogroup USB_OTG_DRIVER
* @{
*/
/** @defgroup USB_HCD
* @brief This file is the interface between EFSL ans Host mass-storage class
* @{
*/
/** @defgroup USB_HCD_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_Private_Functions
* @{
*/
/**
* @brief HCD_Init
* Initialize the HOST portion of the driver.
* @param pdev: Selected device
* @param base_address: OTG base address
* @retval Status
*/
uint32_t HCD_Init(USB_OTG_CORE_HANDLE *pdev ,
USB_OTG_CORE_ID_TypeDef coreID)
{
uint8_t i = 0;
pdev->host.ConnSts = 0;
for (i= 0; i< USB_OTG_MAX_TX_FIFOS; i++)
{
pdev->host.ErrCnt[i] = 0;
pdev->host.XferCnt[i] = 0;
pdev->host.HC_Status[i] = HC_IDLE;
}
pdev->host.hc[0].max_packet = 8;
USB_OTG_SelectCore(pdev, coreID);
#ifndef DUAL_ROLE_MODE_ENABLED
USB_OTG_DisableGlobalInt(pdev);
USB_OTG_CoreInit(pdev);
/* Force Host Mode*/
USB_OTG_SetCurrentMode(pdev , HOST_MODE);
USB_OTG_CoreInitHost(pdev);
USB_OTG_EnableGlobalInt(pdev);
#endif
return 0;
}
/**
* @brief HCD_GetCurrentSpeed
* Get Current device Speed.
* @param pdev : Selected device
* @retval Status
*/
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_HPRT0_TypeDef HPRT0;
HPRT0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
return HPRT0.b.prtspd;
}
/**
* @brief HCD_ResetPort
* Issues the reset command to device
* @param pdev : Selected device
* @retval Status
*/
uint32_t HCD_ResetPort(USB_OTG_CORE_HANDLE *pdev)
{
/*
Before starting to drive a USB reset, the application waits for the OTG
interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT),
which indicates that the bus is stable again after the electrical debounce
caused by the attachment of a pull-up resistor on DP (FS) or DM (LS).
*/
USB_OTG_ResetPort(pdev);
return 0;
}
/**
* @brief HCD_IsDeviceConnected
* Check if the device is connected.
* @param pdev : Selected device
* @retval Device connection status. 1 -> connected and 0 -> disconnected
*
*/
uint32_t HCD_IsDeviceConnected(USB_OTG_CORE_HANDLE *pdev)
{
return (pdev->host.ConnSts);
}
/**
* @brief HCD_GetCurrentFrame
* This function returns the frame number for sof packet
* @param pdev : Selected device
* @retval Frame number
*
*/
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev)
{
return (USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0xFFFF) ;
}
/**
* @brief HCD_GetURB_State
* This function returns the last URBstate
* @param pdev: Selected device
* @retval URB_STATE
*
*/
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num)
{
return pdev->host.URB_State[ch_num] ;
}
/**
* @brief HCD_GetXferCnt
* This function returns the last URBstate
* @param pdev: Selected device
* @retval No. of data bytes transferred
*
*/
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
{
return pdev->host.XferCnt[ch_num] ;
}
/**
* @brief HCD_GetHCState
* This function returns the HC Status
* @param pdev: Selected device
* @retval HC_STATUS
*
*/
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num)
{
return pdev->host.HC_Status[ch_num] ;
}
/**
* @brief HCD_HC_Init
* This function prepare a HC and start a transfer
* @param pdev: Selected device
* @param hc_num: Channel number
* @retval status
*/
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
{
return USB_OTG_HC_Init(pdev, hc_num);
}
/**
* @brief HCD_SubmitRequest
* This function prepare a HC and start a transfer
* @param pdev: Selected device
* @param hc_num: Channel number
* @retval status
*/
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
{
pdev->host.URB_State[hc_num] = URB_IDLE;
pdev->host.hc[hc_num].xfer_count = 0 ;
return USB_OTG_HC_StartXfer(pdev, hc_num);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

108
stm/lib/usb_hcd.h
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/**
******************************************************************************
* @file usb_hcd.h
* @author MCD Application Team
* @version V2.1.0
* @date 19-March-2012
* @brief Host layer Header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_HCD_H__
#define __USB_HCD_H__
/* Includes ------------------------------------------------------------------*/
#include "usb_regs.h"
#include "usb_core.h"
/** @addtogroup USB_OTG_DRIVER
* @{
*/
/** @defgroup USB_HCD
* @brief This file is the
* @{
*/
/** @defgroup USB_HCD_Exported_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_Exported_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_Exported_FunctionsPrototype
* @{
*/
uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev ,
USB_OTG_CORE_ID_TypeDef coreID);
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev ,
uint8_t hc_num);
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev ,
uint8_t hc_num) ;
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev);
uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev);
uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev);
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) ;
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) ;
/**
* @}
*/
#endif //__USB_HCD_H__
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

858
stm/lib/usb_hcd_int.c
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/**
******************************************************************************
* @file usb_hcd_int.c
* @author MCD Application Team
* @version V2.1.0
* @date 19-March-2012
* @brief Host driver interrupt subroutines
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "usb_core.h"
#include "usb_defines.h"
#include "usb_hcd_int.h"
#if defined (__CC_ARM) /*!< ARM Compiler */
#pragma O0
#elif defined (__GNUC__) /*!< GNU Compiler */
#pragma GCC optimize ("O0")
#elif defined (__TASKING__) /*!< TASKING Compiler */
#pragma optimize=0
#endif /* __CC_ARM */
/** @addtogroup USB_OTG_DRIVER
* @{
*/
/** @defgroup USB_HCD_INT
* @brief This file contains the interrupt subroutines for the Host mode.
* @{
*/
/** @defgroup USB_HCD_INT_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_INT_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_INT_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_INT_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_INT_Private_FunctionPrototypes
* @{
*/
static uint32_t USB_OTG_USBH_handle_sof_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_USBH_handle_port_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev ,
uint32_t num);
static uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev ,
uint32_t num);
static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev);
/**
* @}
*/
/** @defgroup USB_HCD_INT_Private_Functions
* @{
*/
/**
* @brief HOST_Handle_ISR
* This function handles all USB Host Interrupts
* @param pdev: Selected device
* @retval status
*/
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTSTS_TypeDef gintsts;
uint32_t retval = 0;
gintsts.d32 = 0;
/* Check if HOST Mode */
if (USB_OTG_IsHostMode(pdev))
{
gintsts.d32 = USB_OTG_ReadCoreItr(pdev);
if (!gintsts.d32)
{
return 0;
}
if (gintsts.b.sofintr)
{
retval |= USB_OTG_USBH_handle_sof_ISR (pdev);
}
if (gintsts.b.rxstsqlvl)
{
retval |= USB_OTG_USBH_handle_rx_qlvl_ISR (pdev);
}
if (gintsts.b.nptxfempty)
{
retval |= USB_OTG_USBH_handle_nptxfempty_ISR (pdev);
}
if (gintsts.b.ptxfempty)
{
retval |= USB_OTG_USBH_handle_ptxfempty_ISR (pdev);
}
if (gintsts.b.hcintr)
{
retval |= USB_OTG_USBH_handle_hc_ISR (pdev);
}
if (gintsts.b.portintr)
{
retval |= USB_OTG_USBH_handle_port_ISR (pdev);
}
if (gintsts.b.disconnect)
{
retval |= USB_OTG_USBH_handle_Disconnect_ISR (pdev);
}
if (gintsts.b.incomplisoout)
{
retval |= USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (pdev);
}
}
return retval;
}
/**
* @brief USB_OTG_USBH_handle_hc_ISR
* This function indicates that one or more host channels has a pending
* @param pdev: Selected device
* @retval status
*/
static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_HAINT_TypeDef haint;
USB_OTG_HCCHAR_TypeDef hcchar;
uint32_t i = 0;
uint32_t retval = 0;
/* Clear appropriate bits in HCINTn to clear the interrupt bit in
* GINTSTS */
haint.d32 = USB_OTG_ReadHostAllChannels_intr(pdev);
for (i = 0; i < pdev->cfg.host_channels ; i++)
{
if (haint.b.chint & (1 << i))
{
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
if (hcchar.b.epdir)
{
retval |= USB_OTG_USBH_handle_hc_n_In_ISR (pdev, i);
}
else
{
retval |= USB_OTG_USBH_handle_hc_n_Out_ISR (pdev, i);
}
}
}
return retval;
}
/**
* @brief USB_OTG_otg_hcd_handle_sof_intr
* Handles the start-of-frame interrupt in host mode.
* @param pdev: Selected device
* @retval status
*/
static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTSTS_TypeDef gintsts;
gintsts.d32 = 0;
USBH_HCD_INT_fops->SOF(pdev);
/* Clear interrupt */
gintsts.b.sofintr = 1;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
return 1;
}
/**
* @brief USB_OTG_USBH_handle_Disconnect_ISR
* Handles disconnect event.
* @param pdev: Selected device
* @retval status
*/
static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTSTS_TypeDef gintsts;
gintsts.d32 = 0;
USBH_HCD_INT_fops->DevDisconnected(pdev);
/* Clear interrupt */
gintsts.b.disconnect = 1;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
return 1;
}
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
/**
* @brief USB_OTG_USBH_handle_nptxfempty_ISR
* Handles non periodic tx fifo empty.
* @param pdev: Selected device
* @retval status
*/
static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTMSK_TypeDef intmsk;
USB_OTG_HNPTXSTS_TypeDef hnptxsts;
uint16_t len_words , len;
hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4;
while ((hnptxsts.b.nptxfspcavail > len_words)&&
(pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len != 0))
{
len = hnptxsts.b.nptxfspcavail * 4;
if (len > pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len)
{
/* Last packet */
len = pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len;
intmsk.d32 = 0;
intmsk.b.nptxfempty = 1;
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
}
len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4;
USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff, hnptxsts.b.nptxqtop.chnum, len);
pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff += len;
pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len -= len;
pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_count += len;
hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
}
return 1;
}
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
/**
* @brief USB_OTG_USBH_handle_ptxfempty_ISR
* Handles periodic tx fifo empty
* @param pdev: Selected device
* @retval status
*/
static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTMSK_TypeDef intmsk;
USB_OTG_HPTXSTS_TypeDef hptxsts;
uint16_t len_words , len;
hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4;
while ((hptxsts.b.ptxfspcavail > len_words)&&
(pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len != 0))
{
len = hptxsts.b.ptxfspcavail * 4;
if (len > pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len)
{
len = pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len;
/* Last packet */
intmsk.d32 = 0;
intmsk.b.ptxfempty = 1;
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
}
len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4;
USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff, hptxsts.b.ptxqtop.chnum, len);
pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff += len;
pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len -= len;
pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_count += len;
hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
}
return 1;
}
/**
* @brief USB_OTG_USBH_handle_port_ISR
* This function determines which interrupt conditions have occurred
* @param pdev: Selected device
* @retval status
*/
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_HPRT0_TypeDef hprt0;
USB_OTG_HPRT0_TypeDef hprt0_dup;
USB_OTG_HCFG_TypeDef hcfg;
uint32_t do_reset = 0;
uint32_t retval = 0;
hcfg.d32 = 0;
hprt0.d32 = 0;
hprt0_dup.d32 = 0;
hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
hprt0_dup.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
/* Clear the interrupt bits in GINTSTS */
hprt0_dup.b.prtena = 0;
hprt0_dup.b.prtconndet = 0;
hprt0_dup.b.prtenchng = 0;
hprt0_dup.b.prtovrcurrchng = 0;
/* Port Connect Detected */
if (hprt0.b.prtconndet)
{
hprt0_dup.b.prtconndet = 1;
USBH_HCD_INT_fops->DevConnected(pdev);
retval |= 1;
}
/* Port Enable Changed */
if (hprt0.b.prtenchng)
{
hprt0_dup.b.prtenchng = 1;
if (hprt0.b.prtena == 1)
{
USBH_HCD_INT_fops->DevConnected(pdev);
if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) ||
(hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED))
{
hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
if (hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED)
{
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 );
if (hcfg.b.fslspclksel != HCFG_6_MHZ)
{
if(pdev->cfg.phy_itface == USB_OTG_EMBEDDED_PHY)
{
USB_OTG_InitFSLSPClkSel(pdev ,HCFG_6_MHZ );
}
do_reset = 1;
}
}
else
{
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 48000 );
if (hcfg.b.fslspclksel != HCFG_48_MHZ)
{
USB_OTG_InitFSLSPClkSel(pdev ,HCFG_48_MHZ );
do_reset = 1;
}
}
}
else
{
do_reset = 1;
}
}
}
/* Overcurrent Change Interrupt */
if (hprt0.b.prtovrcurrchng)
{
hprt0_dup.b.prtovrcurrchng = 1;
retval |= 1;
}
if (do_reset)
{
USB_OTG_ResetPort(pdev);
}
/* Clear Port Interrupts */
USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32);
return retval;
}
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
/**
* @brief USB_OTG_USBH_handle_hc_n_Out_ISR
* Handles interrupt for a specific Host Channel
* @param pdev: Selected device
* @param hc_num: Channel number
* @retval status
*/
uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num)
{
USB_OTG_HCINTn_TypeDef hcint;
USB_OTG_HCINTMSK_TypeDef hcintmsk;
USB_OTG_HC_REGS *hcreg;
USB_OTG_HCCHAR_TypeDef hcchar;
hcreg = pdev->regs.HC_REGS[num];
hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK);
hcint.d32 = hcint.d32 & hcintmsk.d32;
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
if (hcint.b.ahberr)
{
CLEAR_HC_INT(hcreg ,ahberr);
UNMASK_HOST_INT_CHH (num);
}
else if (hcint.b.ack)
{
CLEAR_HC_INT(hcreg , ack);
}
else if (hcint.b.frmovrun)
{
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg ,frmovrun);
}
else if (hcint.b.xfercompl)
{
pdev->host.ErrCnt[num] = 0;
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg , xfercompl);
pdev->host.HC_Status[num] = HC_XFRC;
}
else if (hcint.b.stall)
{
CLEAR_HC_INT(hcreg , stall);
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
pdev->host.HC_Status[num] = HC_STALL;
}
else if (hcint.b.nak)
{
pdev->host.ErrCnt[num] = 0;
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg , nak);
pdev->host.HC_Status[num] = HC_NAK;
}
else if (hcint.b.xacterr)
{
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
pdev->host.ErrCnt[num] ++;
pdev->host.HC_Status[num] = HC_XACTERR;
CLEAR_HC_INT(hcreg , xacterr);
}
else if (hcint.b.nyet)
{
pdev->host.ErrCnt[num] = 0;
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg , nyet);
pdev->host.HC_Status[num] = HC_NYET;
}
else if (hcint.b.datatglerr)
{
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg , nak);
pdev->host.HC_Status[num] = HC_DATATGLERR;
CLEAR_HC_INT(hcreg , datatglerr);
}
else if (hcint.b.chhltd)
{
MASK_HOST_INT_CHH (num);
if(pdev->host.HC_Status[num] == HC_XFRC)
{
pdev->host.URB_State[num] = URB_DONE;
if (hcchar.b.eptype == EP_TYPE_BULK)
{
pdev->host.hc[num].toggle_out ^= 1;
}
}
else if(pdev->host.HC_Status[num] == HC_NAK)
{
pdev->host.URB_State[num] = URB_NOTREADY;
}
else if(pdev->host.HC_Status[num] == HC_NYET)
{
if(pdev->host.hc[num].do_ping == 1)
{
USB_OTG_HC_DoPing(pdev, num);
}
pdev->host.URB_State[num] = URB_NOTREADY;
}
else if(pdev->host.HC_Status[num] == HC_STALL)
{
pdev->host.URB_State[num] = URB_STALL;
}
else if(pdev->host.HC_Status[num] == HC_XACTERR)
{
if (pdev->host.ErrCnt[num] == 3)
{
pdev->host.URB_State[num] = URB_ERROR;
pdev->host.ErrCnt[num] = 0;
}
}
CLEAR_HC_INT(hcreg , chhltd);
}
return 1;
}
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
/**
* @brief USB_OTG_USBH_handle_hc_n_In_ISR
* Handles interrupt for a specific Host Channel
* @param pdev: Selected device
* @param hc_num: Channel number
* @retval status
*/
uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num)
{
USB_OTG_HCINTn_TypeDef hcint;
USB_OTG_HCINTMSK_TypeDef hcintmsk;
USB_OTG_HCCHAR_TypeDef hcchar;
USB_OTG_HCTSIZn_TypeDef hctsiz;
USB_OTG_HC_REGS *hcreg;
hcreg = pdev->regs.HC_REGS[num];
hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK);
hcint.d32 = hcint.d32 & hcintmsk.d32;
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
hcintmsk.d32 = 0;
if (hcint.b.ahberr)
{
CLEAR_HC_INT(hcreg ,ahberr);
UNMASK_HOST_INT_CHH (num);
}
else if (hcint.b.ack)
{
CLEAR_HC_INT(hcreg ,ack);
}
else if (hcint.b.stall)
{
UNMASK_HOST_INT_CHH (num);
pdev->host.HC_Status[num] = HC_STALL;
CLEAR_HC_INT(hcreg , nak); /* Clear the NAK Condition */
CLEAR_HC_INT(hcreg , stall); /* Clear the STALL Condition */
hcint.b.nak = 0; /* NOTE: When there is a 'stall', reset also nak,
else, the pdev->host.HC_Status = HC_STALL
will be overwritten by 'nak' in code below */
USB_OTG_HC_Halt(pdev, num);
}
else if (hcint.b.datatglerr)
{
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg , nak);
pdev->host.HC_Status[num] = HC_DATATGLERR;
CLEAR_HC_INT(hcreg , datatglerr);
}
if (hcint.b.frmovrun)
{
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg ,frmovrun);
}
else if (hcint.b.xfercompl)
{
if (pdev->cfg.dma_enable == 1)
{
hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCTSIZ);
pdev->host.XferCnt[num] = pdev->host.hc[num].xfer_len - hctsiz.b.xfersize;
}
pdev->host.HC_Status[num] = HC_XFRC;
pdev->host.ErrCnt [num]= 0;
CLEAR_HC_INT(hcreg , xfercompl);
if ((hcchar.b.eptype == EP_TYPE_CTRL)||
(hcchar.b.eptype == EP_TYPE_BULK))
{
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg , nak);
pdev->host.hc[num].toggle_in ^= 1;
}
else if(hcchar.b.eptype == EP_TYPE_INTR)
{
hcchar.b.oddfrm = 1;
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
pdev->host.URB_State[num] = URB_DONE;
}
}
else if (hcint.b.chhltd)
{
MASK_HOST_INT_CHH (num);
if(pdev->host.HC_Status[num] == HC_XFRC)
{
pdev->host.URB_State[num] = URB_DONE;
}
else if (pdev->host.HC_Status[num] == HC_STALL)
{
pdev->host.URB_State[num] = URB_STALL;
}
else if((pdev->host.HC_Status[num] == HC_XACTERR) ||
(pdev->host.HC_Status[num] == HC_DATATGLERR))
{
pdev->host.ErrCnt[num] = 0;
pdev->host.URB_State[num] = URB_ERROR;
}
else if(hcchar.b.eptype == EP_TYPE_INTR)
{
pdev->host.hc[num].toggle_in ^= 1;
}
CLEAR_HC_INT(hcreg , chhltd);
}
else if (hcint.b.xacterr)
{
UNMASK_HOST_INT_CHH (num);
pdev->host.ErrCnt[num] ++;
pdev->host.HC_Status[num] = HC_XACTERR;
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg , xacterr);
}
else if (hcint.b.nak)
{
if(hcchar.b.eptype == EP_TYPE_INTR)
{
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
}
else if ((hcchar.b.eptype == EP_TYPE_CTRL)||
(hcchar.b.eptype == EP_TYPE_BULK))
{
/* re-activate the channel */
hcchar.b.chen = 1;
hcchar.b.chdis = 0;
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
}
pdev->host.HC_Status[num] = HC_NAK;
CLEAR_HC_INT(hcreg , nak);
}
return 1;
}
/**
* @brief USB_OTG_USBH_handle_rx_qlvl_ISR
* Handles the Rx Status Queue Level Interrupt
* @param pdev: Selected device
* @retval status
*/
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GRXFSTS_TypeDef grxsts;
USB_OTG_GINTMSK_TypeDef intmsk;
USB_OTG_HCTSIZn_TypeDef hctsiz;
USB_OTG_HCCHAR_TypeDef hcchar;
__IO uint8_t channelnum =0;
uint32_t count;
/* Disable the Rx Status Queue Level interrupt */
intmsk.d32 = 0;
intmsk.b.rxstsqlvl = 1;
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP);
channelnum = grxsts.b.chnum;
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR);
switch (grxsts.b.pktsts)
{
case GRXSTS_PKTSTS_IN:
/* Read the data into the host buffer. */
if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0))
{
USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt);
/*manage multiple Xfer */
pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt;
pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt;
count = pdev->host.hc[channelnum].xfer_count;
pdev->host.XferCnt[channelnum] = count;
hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ);
if(hctsiz.b.pktcnt > 0)
{
/* re-activate the channel when more packets are expected */
hcchar.b.chen = 1;
hcchar.b.chdis = 0;
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32);
}
}
break;
case GRXSTS_PKTSTS_IN_XFER_COMP:
case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
case GRXSTS_PKTSTS_CH_HALTED:
default:
break;
}
/* Enable the Rx Status Queue Level interrupt */
intmsk.b.rxstsqlvl = 1;
USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
return 1;
}
/**
* @brief USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR
* Handles the incomplete Periodic transfer Interrupt
* @param pdev: Selected device
* @retval status
*/
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTSTS_TypeDef gintsts;
USB_OTG_HCCHAR_TypeDef hcchar;
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR);
hcchar.b.chen = 1;
hcchar.b.chdis = 1;
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32);
gintsts.d32 = 0;
/* Clear interrupt */
gintsts.b.incomplisoout = 1;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
return 1;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

141
stm/lib/usb_hcd_int.h
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@ -1,141 +0,0 @@
/**
******************************************************************************
* @file usb_hcd_int.h
* @author MCD Application Team
* @version V2.1.0
* @date 19-March-2012
* @brief Peripheral Device Interface Layer
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HCD_INT_H__
#define __HCD_INT_H__
/* Includes ------------------------------------------------------------------*/
#include "usb_hcd.h"
/** @addtogroup USB_OTG_DRIVER
* @{
*/
/** @defgroup USB_HCD_INT
* @brief This file is the
* @{
*/
/** @defgroup USB_HCD_INT_Exported_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_INT_Exported_Types
* @{
*/
typedef struct _USBH_HCD_INT
{
uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev);
uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev);
uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev);
}USBH_HCD_INT_cb_TypeDef;
extern USBH_HCD_INT_cb_TypeDef *USBH_HCD_INT_fops;
/**
* @}
*/
/** @defgroup USB_HCD_INT_Exported_Macros
* @{
*/
#define CLEAR_HC_INT(HC_REGS, intr) \
{\
USB_OTG_HCINTn_TypeDef hcint_clear; \
hcint_clear.d32 = 0; \
hcint_clear.b.intr = 1; \
USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\
}\
#define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \
INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
INTMSK.b.chhltd = 0; \
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);}
#define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \
INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
INTMSK.b.chhltd = 1; \
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);}
#define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \
INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
INTMSK.b.ack = 0; \
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, GINTMSK.d32);}
#define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef INTMSK; \
INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
INTMSK.b.ack = 1; \
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);}
/**
* @}
*/
/** @defgroup USB_HCD_INT_Exported_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USB_HCD_INT_Exported_FunctionsPrototype
* @{
*/
/* Callbacks handler */
void ConnectCallback_Handler(USB_OTG_CORE_HANDLE *pdev);
void Disconnect_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
void Overcurrent_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
/**
* @}
*/
#endif //__HCD_INT_H__
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

418
stm/lib/usb_otg.c
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@ -1,418 +0,0 @@
/**
******************************************************************************
* @file usb_otg.c
* @author MCD Application Team
* @version V2.1.0
* @date 19-March-2012
* @brief OTG Core Layer
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "usb_defines.h"
#include "usb_regs.h"
#include "usb_core.h"
#include "usb_otg.h"
/** @addtogroup USB_OTG_DRIVER
* @{
*/
/** @defgroup USB_OTG
* @brief This file is the interface between EFSL ans Host mass-storage class
* @{
*/
/** @defgroup USB_OTG_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USB_OTG_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USB_OTG_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USB_OTG_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USB_OTG_Private_FunctionPrototypes
* @{
*/
uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev);
/**
* @}
*/
/** @defgroup USB_OTG_Private_Functions
* @{
*/
/* OTG Interrupt Handler */
/**
* @brief STM32_USBO_OTG_ISR_Handler
*
* @param None
* @retval : None
*/
uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev)
{
uint32_t retval = 0;
USB_OTG_GINTSTS_TypeDef gintsts ;
gintsts.d32 = 0;
gintsts.d32 = USB_OTG_Read_itr(pdev);
if (gintsts.d32 == 0)
{
return 0;
}
if (gintsts.b.otgintr)
{
retval |= USB_OTG_HandleOTG_ISR(pdev);
}
if (gintsts.b.conidstschng)
{
retval |= USB_OTG_HandleConnectorIDStatusChange_ISR(pdev);
}
if (gintsts.b.sessreqintr)
{
retval |= USB_OTG_HandleSessionRequest_ISR(pdev);
}
return retval;
}
/**
* @brief USB_OTG_Read_itr
* returns the Core Interrupt register
* @param None
* @retval : status
*/
static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTSTS_TypeDef gintsts;
USB_OTG_GINTMSK_TypeDef gintmsk;
USB_OTG_GINTMSK_TypeDef gintmsk_common;
gintsts.d32 = 0;
gintmsk.d32 = 0;
gintmsk_common.d32 = 0;
/* OTG interrupts */
gintmsk_common.b.sessreqintr = 1;
gintmsk_common.b.conidstschng = 1;
gintmsk_common.b.otgintr = 1;
gintsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS);
gintmsk.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK);
return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32);
}
/**
* @brief USB_OTG_HandleOTG_ISR
* handles the OTG Interrupts
* @param None
* @retval : status
*/
static uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GOTGINT_TypeDef gotgint;
USB_OTG_GOTGCTL_TypeDef gotgctl;
gotgint.d32 = 0;
gotgctl.d32 = 0;
gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
if (gotgint.b.sesenddet)
{
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
if (USB_OTG_IsDeviceMode(pdev))
{
}
else if (USB_OTG_IsHostMode(pdev))
{
}
}
/* ----> SRP SUCCESS or FAILURE INTERRUPT <---- */
if (gotgint.b.sesreqsucstschng)
{
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
if (gotgctl.b.sesreqscs) /* Session request success */
{
if (USB_OTG_IsDeviceMode(pdev))
{
}
/* Clear Session Request */
gotgctl.d32 = 0;
gotgctl.b.sesreq = 1;
USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0);
}
else /* Session request failure */
{
if (USB_OTG_IsDeviceMode(pdev))
{
}
}
}
/* ----> HNP SUCCESS or FAILURE INTERRUPT <---- */
if (gotgint.b.hstnegsucstschng)
{
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
if (gotgctl.b.hstnegscs) /* Host negotiation success */
{
if (USB_OTG_IsHostMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */
{
}
}
else /* Host negotiation failure */
{
}
gotgint.b.hstnegsucstschng = 1; /* Ack "Host Negotiation Success Status Change" interrupt. */
}
/* ----> HOST NEGOTIATION DETECTED INTERRUPT <---- */
if (gotgint.b.hstnegdet)
{
if (USB_OTG_IsDeviceMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */
{
}
else
{
}
}
if (gotgint.b.adevtoutchng)
{}
if (gotgint.b.debdone)
{
USB_OTG_ResetPort(pdev);
}
/* Clear OTG INT */
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
return 1;
}
/**
* @brief USB_OTG_HandleConnectorIDStatusChange_ISR
* handles the Connector ID Status Change Interrupt
* @param None
* @retval : status
*/
static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTMSK_TypeDef gintmsk;
USB_OTG_GOTGCTL_TypeDef gotgctl;
USB_OTG_GINTSTS_TypeDef gintsts;
gintsts.d32 = 0 ;
gintmsk.d32 = 0 ;
gotgctl.d32 = 0 ;
gintmsk.b.sofintr = 1;
USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, gintmsk.d32, 0);
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts)
{
USB_OTG_DisableGlobalInt(pdev);
USB_OTG_CoreInitDev(pdev);
USB_OTG_EnableGlobalInt(pdev);
pdev->otg.OTG_State = B_PERIPHERAL;
}
else
{
USB_OTG_DisableGlobalInt(pdev);
USB_OTG_CoreInitHost(pdev);
USB_OTG_EnableGlobalInt(pdev);
pdev->otg.OTG_State = A_HOST;
}
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
return 1;
}
/**
* @brief USB_OTG_HandleSessionRequest_ISR
* Initiating the Session Request Protocol
* @param None
* @retval : status
*/
static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTSTS_TypeDef gintsts;
USB_OTG_GOTGCTL_TypeDef gotgctl;
gotgctl.d32 = 0;
gintsts.d32 = 0;
gotgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL );
if (USB_OTG_IsDeviceMode(pdev) && (gotgctl.b.bsesvld))
{
}
else if (gotgctl.b.asesvld)
{
}
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
return 1;
}
/**
* @brief USB_OTG_InitiateSRP
* Initiate an srp session
* @param None
* @retval : None
*/
void USB_OTG_InitiateSRP(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GOTGCTL_TypeDef otgctl;
otgctl.d32 = 0;
otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL );
if (otgctl.b.sesreq)
{
return; /* SRP in progress */
}
otgctl.b.sesreq = 1;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32);
}
/**
* @brief USB_OTG_InitiateHNP
* Initiate HNP
* @param None
* @retval : None
*/
void USB_OTG_InitiateHNP(USB_OTG_CORE_HANDLE *pdev , uint8_t state, uint8_t mode)
{
USB_OTG_GOTGCTL_TypeDef otgctl;
USB_OTG_HPRT0_TypeDef hprt0;
otgctl.d32 = 0;
hprt0.d32 = 0;
otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL );
if (mode)
{ /* Device mode */
if (state)
{
otgctl.b.devhnpen = 1; /* B-Dev has been enabled to perform HNP */
otgctl.b.hnpreq = 1; /* Initiate an HNP req. to the connected USB host*/
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32);
}
}
else
{ /* Host mode */
if (state)
{
otgctl.b.hstsethnpen = 1; /* A-Dev has enabled B-device for HNP */
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32);
/* Suspend the bus so that B-dev will disconnect indicating the initial condition for HNP to DWC_Core */
hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
hprt0.b.prtsusp = 1; /* The core clear this bit when disconnect interrupt generated (GINTSTS.DisconnInt = '1') */
USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
}
}
}
/**
* @brief USB_OTG_GetCurrentState
* Return current OTG State
* @param None
* @retval : None
*/
uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev)
{
return pdev->otg.OTG_State;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

99
stm/lib/usb_otg.h
View File

@ -1,99 +0,0 @@
/**
******************************************************************************
* @file usb_otg.h
* @author MCD Application Team
* @version V2.1.0
* @date 19-March-2012
* @brief OTG Core Header
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_OTG__
#define __USB_OTG__
/** @addtogroup USB_OTG_DRIVER
* @{
*/
/** @defgroup USB_OTG
* @brief This file is the
* @{
*/
/** @defgroup USB_OTG_Exported_Defines
* @{
*/
void USB_OTG_InitiateSRP(void);
void USB_OTG_InitiateHNP(uint8_t state , uint8_t mode);
void USB_OTG_Switchback (USB_OTG_CORE_DEVICE *pdev);
uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_DEVICE *pdev);
/**
* @}
*/
/** @defgroup USB_OTG_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup USB_OTG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USB_OTG_Exported_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USB_OTG_Exported_FunctionsPrototype
* @{
*/
/**
* @}
*/
#endif //__USB_OTG__
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/