stm32/system_stm32f0: Add support for using HSE and PLL as SYSCLK.
To configure the SYSCLK on an F0 enable one of: MICROPY_HW_CLK_USE_HSI48 MICROPY_HW_CLK_USE_HSE MICROPY_HW_CLK_USE_BYPASS
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@ -17,6 +17,7 @@
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#define MICROPY_HW_HAS_SWITCH (1)
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#define MICROPY_HW_HAS_SWITCH (1)
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// For system clock, board uses internal 48MHz, HSI48
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// For system clock, board uses internal 48MHz, HSI48
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#define MICROPY_HW_CLK_USE_HSI48 (1)
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// The board has an external 32kHz crystal
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// The board has an external 32kHz crystal
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#define MICROPY_HW_RTC_USE_LSE (1)
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#define MICROPY_HW_RTC_USE_LSE (1)
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@ -40,7 +40,7 @@
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******************************************************************************
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******************************************************************************
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*/
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*/
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#include STM32_HAL_H
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#include "py/mphal.h"
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#ifndef HSE_VALUE
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#ifndef HSE_VALUE
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#define HSE_VALUE (8000000)
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#define HSE_VALUE (8000000)
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@ -135,12 +135,37 @@ void SystemClock_Config(void) {
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// Set flash latency to 1 because SYSCLK > 24MHz
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// Set flash latency to 1 because SYSCLK > 24MHz
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FLASH->ACR = (FLASH->ACR & ~0x7) | 0x1;
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FLASH->ACR = (FLASH->ACR & ~0x7) | 0x1;
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#if MICROPY_HW_CLK_USE_HSI48
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// Use the 48MHz internal oscillator
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// Use the 48MHz internal oscillator
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RCC->CR2 |= RCC_CR2_HSI48ON;
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RCC->CR2 |= RCC_CR2_HSI48ON;
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while ((RCC->CR2 & RCC_CR2_HSI48RDY) == 0) {
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while ((RCC->CR2 & RCC_CR2_HSI48RDY) == 0) {
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}
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}
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RCC->CFGR |= 3 << RCC_CFGR_SW_Pos;
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const uint32_t sysclk_src = 3;
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while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != 0x03) {
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#else
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// Use HSE and the PLL to get a 48MHz SYSCLK
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#if MICROPY_HW_CLK_USE_BYPASS
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RCC->CR |= RCC_CR_HSEBYP;
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#endif
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RCC->CR |= RCC_CR_HSEON;
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while ((RCC->CR & RCC_CR_HSERDY) == 0) {
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// Wait for HSE to be ready
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}
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RCC->CFGR = ((48000000 / HSE_VALUE) - 2) << RCC_CFGR_PLLMUL_Pos | 2 << RCC_CFGR_PLLSRC_Pos;
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RCC->CFGR2 = 0; // Input clock not divided
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RCC->CR |= RCC_CR_PLLON; // Turn PLL on
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while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
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// Wait for PLL to lock
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}
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const uint32_t sysclk_src = 2;
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#endif
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// Select SYSCLK source
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RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
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while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
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// Wait for SYSCLK source to change
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// Wait for SYSCLK source to change
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}
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}
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