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return error status on more routines; minor simplification of freq setting

This commit is contained in:
Dan Halbert 2018-12-21 12:30:54 -05:00
parent bce6d124af
commit 0dfe2dbff0
1 changed files with 8 additions and 10 deletions
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18
ports/nrf/supervisor/qspi_flash.c
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@ -60,8 +60,8 @@ bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length)
.wipwait = false,
.wren = false
};
nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, response);
return true;
return nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, response) == NRFX_SUCCESS;
}
bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) {
@ -73,8 +73,7 @@ bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) {
.wipwait = false,
.wren = false // We do this manually.
};
nrfx_qspi_cinstr_xfer(&cinstr_cfg, data, NULL);
return true;
return nrfx_qspi_cinstr_xfer(&cinstr_cfg, data, NULL) == NRFX_SUCCESS;
}
bool spi_flash_sector_command(uint8_t command, uint32_t address) {
@ -146,15 +145,14 @@ void spi_flash_init_device(const external_flash_device* device) {
}
// Speed up as much as we can.
uint8_t sckfreq = 0;
// Start at 16 MHz and go down.
// At 32 MHz GD25Q16C doesn't work reliably on Feather 52840, even though it should work up to 104 MHz.
// sckfreq = 0 is 32 Mhz
// sckfreq = 1 is 16 MHz, etc.
uint8_t sckfreq = 1;
while (32000000 / (sckfreq + 1) > device->max_clock_speed_mhz * 1000000 && sckfreq < 16) {
sckfreq += 1;
}
// No more than 16 MHz. At 32 MHz GD25Q16C doesn't work reliably on Feather 52840, even though
// it should work up to 104 MHz.
// sckfreq = 0 is 32 Mhz
// sckfreq = 1 is 16 MHz, etc.
sckfreq = MAX(1, sckfreq);
NRF_QSPI->IFCONFIG1 &= ~QSPI_IFCONFIG1_SCKFREQ_Msk;
NRF_QSPI->IFCONFIG1 |= sckfreq << QSPI_IFCONFIG1_SCKFREQ_Pos;
}