stm32/boards/stm32f091_af.csv: Split labels that are multiple funcs.

This commit is contained in:
rolandvs 2018-06-13 12:50:10 +02:00 committed by Damien George
parent 48829cd3c6
commit 0d3de68669
1 changed files with 7 additions and 7 deletions

View File

@ -18,10 +18,10 @@ PortA,PA14,SWCLK,USART2_TX,,,,,,,,,,,,,,,
PortA,PA15,SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,USART4_RTS,,,,,,,,,,,, PortA,PA15,SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,USART4_RTS,,,,,,,,,,,,
PortB,PB0,EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,USART3_CK,,,,,,,,,,,,ADC1_IN8 PortB,PB0,EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,USART3_CK,,,,,,,,,,,,ADC1_IN8
PortB,PB1,TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,USART3_RTS,,,,,,,,,,,,ADC1_IN9 PortB,PB1,TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,USART3_RTS,,,,,,,,,,,,ADC1_IN9
PortB,PB2,,,,TSC_G3_IO4,,,,,,,,,,, PortB,PB2,,,,TSC_G3_IO4,,,,,,,,,,,,,
PortB,PB3,SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,USART5_TX,,,,,,,,,, PortB,PB3,SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,USART5_TX,,,,,,,,,,
PortB,PB4,SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,USART5_RX,TIM17_BKIN,,,,,,,,, PortB,PB4,SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,USART5_RX,TIM17_BKIN,,,,,,,,,
PortB,PB5,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,USART5_CK_RTS,,,,,,,,,, PortB,PB5,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,USART5_CK/USART5_RTS,,,,,,,,,,
PortB,PB6,USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,,,,,,,,,,, PortB,PB6,USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,,,,,,,,,,,
PortB,PB7,USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,USART4_CTS,,,,,,,,,, PortB,PB7,USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,USART4_CTS,,,,,,,,,,
PortB,PB8,CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,CAN1_RX,,,,,,,,,, PortB,PB8,CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,CAN1_RX,,,,,,,,,,
@ -60,10 +60,10 @@ PortD,PD8,USART3_TX,,,,,,,,,,,,,,,,
PortD,PD9,USART3_RX,,,,,,,,,,,,,,,, PortD,PD9,USART3_RX,,,,,,,,,,,,,,,,
PortD,PD10,USART3_CK,,,,,,,,,,,,,,,, PortD,PD10,USART3_CK,,,,,,,,,,,,,,,,
PortD,PD11,USART3_CTS,,,,,,,,,,,,,,,, PortD,PD11,USART3_CTS,,,,,,,,,,,,,,,,
PortD,PD12,USART3_RTS,TSC_G8_IO1,USART8_CK_RTS,,,,,,,,,,,,,, PortD,PD12,USART3_RTS,TSC_G8_IO1,USART8_CK/USART8_RTS,,,,,,,,,,,,,,
PortD,PD13,USART8_TX,TSC_G8_IO2,,,,,,,,,,,,,,, PortD,PD13,USART8_TX,TSC_G8_IO2,,,,,,,,,,,,,,,
PortD,PD14,USART8_RX,TSC_G8_IO3,,,,,,,,,,,,,,, PortD,PD14,USART8_RX,TSC_G8_IO3,,,,,,,,,,,,,,,
PortD,PD15,CRS_SYNC,TSC_G8_IO4,USART7_CK_RTS,,,,,,,,,,,,,, PortD,PD15,CRS_SYNC,TSC_G8_IO4,USART7_CK/USART7_RTS,,,,,,,,,,,,,,
PortE,PE0,TIM16_CH1,EVENTOUT,,,,,,,,,,,,,,, PortE,PE0,TIM16_CH1,EVENTOUT,,,,,,,,,,,,,,,
PortE,PE1,TIM17_CH1,EVENTOUT,,,,,,,,,,,,,,, PortE,PE1,TIM17_CH1,EVENTOUT,,,,,,,,,,,,,,,
PortE,PE2,TIM3_ETR,TSC_G7_IO1,,,,,,,,,,,,,,, PortE,PE2,TIM3_ETR,TSC_G7_IO1,,,,,,,,,,,,,,,
@ -71,7 +71,7 @@ PortE,PE3,TIM3_CH1,TSC_G7_IO2,,,,,,,,,,,,,,,
PortE,PE4,TIM3_CH2,TSC_G7_IO3,,,,,,,,,,,,,,, PortE,PE4,TIM3_CH2,TSC_G7_IO3,,,,,,,,,,,,,,,
PortE,PE5,TIM3_CH3,TSC_G7_IO4,,,,,,,,,,,,,,, PortE,PE5,TIM3_CH3,TSC_G7_IO4,,,,,,,,,,,,,,,
PortE,PE6,TIM3_CH4,,,,,,,,,,,,,,,, PortE,PE6,TIM3_CH4,,,,,,,,,,,,,,,,
PortE,PE7,TIM1_ETR,USART5_CK_RTS,,,,,,,,,,,,,,, PortE,PE7,TIM1_ETR,USART5_CK/USART5_RTS,,,,,,,,,,,,,,,
PortE,PE8,TIM1_CH1N,USART4_TX,,,,,,,,,,,,,,, PortE,PE8,TIM1_CH1N,USART4_TX,,,,,,,,,,,,,,,
PortE,PE9,TIM1_CH1,USART4_RX,,,,,,,,,,,,,,, PortE,PE9,TIM1_CH1,USART4_RX,,,,,,,,,,,,,,,
PortE,PE10,TIM1_CH2N,USART5_TX,,,,,,,,,,,,,,, PortE,PE10,TIM1_CH2N,USART5_TX,,,,,,,,,,,,,,,
@ -82,8 +82,8 @@ PortE,PE14,TIM1_CH4,SPI1_MISO/I2S1_MCK,,,,,,,,,,,,,,,
PortE,PE15,TIM1_BKIN,SPI1_MOSI/I2S1_SD,,,,,,,,,,,,,,, PortE,PE15,TIM1_BKIN,SPI1_MOSI/I2S1_SD,,,,,,,,,,,,,,,
PortF,PF0,CRS_SYNC,I2C1_SDA,,,,,,,,,,,,,,, PortF,PF0,CRS_SYNC,I2C1_SDA,,,,,,,,,,,,,,,
PortF,PF1,,I2C1_SCL,,,,,,,,,,,,,,, PortF,PF1,,I2C1_SCL,,,,,,,,,,,,,,,
PortF,PF2,EVENTOUT,USART7_TX,USART7_CK_RTS,,,,,,,,,,,,,, PortF,PF2,EVENTOUT,USART7_TX,USART7_CK/USART7_RTS,,,,,,,,,,,,,,
PortF,PF3,EVENTOUT,USART7_RX,USART6_CK_RTS,,,,,,,,,,,,,, PortF,PF3,EVENTOUT,USART7_RX,USART6_CK/USART6_RTS,,,,,,,,,,,,,,
PortF,PF6,,,,,,,,,,,,,,,,, PortF,PF6,,,,,,,,,,,,,,,,,
PortF,PF9,TIM15_CH1,USART6_TX,,,,,,,,,,,,,,, PortF,PF9,TIM15_CH1,USART6_TX,,,,,,,,,,,,,,,
PortF,PF10,TIM15_CH2,USART6_RX,,,,,,,,,,,,,,, PortF,PF10,TIM15_CH2,USART6_RX,,,,,,,,,,,,,,,

Can't render this file because it has a wrong number of fields in line 21.