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cc3200: Update HAL to SDK release version 1.1.0.

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This commit is contained in:
danicampora 2015-03-15 10:05:15 +01:00
parent dac79324b5
commit 0d0646d915
17 changed files with 3848 additions and 3583 deletions
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1
cc3200/bootmgr/bootloader.mk
View File

@ -19,6 +19,7 @@ BOOT_CPPDEFINES = -Dgcc -DBOOTLOADER -DTARGET_IS_CC3200 -DSL_TINY
BOOT_HAL_SRC_C = $(addprefix hal/,\
cpu.c \
interrupt.c \
pin.c \
prcm.c \
shamd5.c \
spi.c \

2
cc3200/hal/adc.h
View File

@ -48,7 +48,7 @@
//*****************************************************************************
#ifdef __cplusplus
extern "C"
//{
{
#endif
//*****************************************************************************

34
cc3200/hal/aes.c
View File

@ -377,6 +377,36 @@ AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata)
HWREG(ui32Base + AES_O_IV_IN_3) = *((uint32_t *)(pui8IVdata+12));
}
//*****************************************************************************
//
//! Reads the Initial Vector (IV) register, needed in some of the AES Modes.
//!
//! \param ui32Base is the base address of the AES module.
//! \param pui8IVdata is pointer to an array of 16 bytes.
//!
//! This functions reads the initial vector registers in the AES module.
//!
//! \return None.
//
//*****************************************************************************
void
AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata)
{
//
// Check the arguments.
//
ASSERT(ui32Base == AES_BASE);
//
// Write the initial vector registers.
//
*((uint32_t *)(pui8IVdata+ 0)) = HWREG(ui32Base + AES_O_IV_IN_0);
*((uint32_t *)(pui8IVdata+ 4)) = HWREG(ui32Base + AES_O_IV_IN_1);
*((uint32_t *)(pui8IVdata+ 8)) = HWREG(ui32Base + AES_O_IV_IN_2);
*((uint32_t *)(pui8IVdata+12)) = HWREG(ui32Base + AES_O_IV_IN_3);
}
//*****************************************************************************
//
//! Saves the tag registers to a user-defined location.
@ -792,12 +822,12 @@ AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,
//
// Write the data registers.
//
AESDataWrite(ui32Base, pui8Src + (ui32Count*ui32BlkCount) ,ui32ByteCount);
AESDataWrite(ui32Base, pui8Src + (16*ui32BlkCount) ,ui32ByteCount);
//
// Read the data registers.
//
AESDataRead(ui32Base, pui8Dest + (ui32Count*ui32BlkCount) ,ui32ByteCount);
AESDataRead(ui32Base, pui8Dest + (16*ui32BlkCount) ,ui32ByteCount);
}

1
cc3200/hal/aes.h
View File

@ -175,6 +175,7 @@ extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key,
uint32_t ui32Keysize);
extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key);
extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData);
extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length);
extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);

4
cc3200/hal/des.c
View File

@ -542,7 +542,7 @@ DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,
//
// Write the data registers.
//
DESDataWriteNonBlocking(ui32Base, pui8Src + (ui32Count*ui32BlkCount) ,
DESDataWriteNonBlocking(ui32Base, pui8Src + (8*ui32BlkCount) ,
ui32ByteCount);
//
// Wait for the output ready
@ -554,7 +554,7 @@ DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,
//
// Read the data registers.
//
DESDataReadNonBlocking(ui32Base, pui8Dest + (ui32Count*ui32BlkCount) ,
DESDataReadNonBlocking(ui32Base, pui8Dest + (8*ui32BlkCount) ,
ui32ByteCount);
}

146
cc3200/hal/i2s.c
View File

@ -127,9 +127,16 @@ static void I2SGBLEnable(unsigned long ulBase, unsigned long ulFlag)
void I2SEnable(unsigned long ulBase, unsigned long ulMode)
{
//
// Set FSYNC anc BitClk as output
// FSYNC and Bit clock are output only in master mode
//
HWREG(ulBase + MCASP_O_PDIR) |= 0x14000000;
if( HWREG(ulBase + MCASP_O_ACLKXCTL) & 0x20)
{
//
// Set FSYNC anc BitClk as output
//
HWREG(ulBase + MCASP_O_PDIR) |= 0x14000000;
}
if(ulMode & 0x2)
{
@ -159,18 +166,20 @@ void I2SEnable(unsigned long ulBase, unsigned long ulMode)
I2SGBLEnable(ulBase, MCASP_GBL_RFSYNC);
}
//
// Remove Tx HCLK reset
//
I2SGBLEnable(ulBase, MCASP_GBL_XHCLK);
//
// Remove Tx XCLK reset
//
I2SGBLEnable(ulBase, MCASP_GBL_XCLK);
if(ulMode & 0x1)
{
//
// Remove Tx HCLK reset
//
I2SGBLEnable(ulBase, MCASP_GBL_XHCLK);
//
// Remove Tx XCLK reset
//
I2SGBLEnable(ulBase, MCASP_GBL_XCLK);
//
// Enable Tx SERDES(s)
//
@ -180,12 +189,12 @@ void I2SEnable(unsigned long ulBase, unsigned long ulMode)
// Enable Tx state machine
//
I2SGBLEnable(ulBase, MCASP_GBL_XSM);
//
// Enable FSync generator
//
I2SGBLEnable(ulBase, MCASP_GBL_XFSYNC);
}
//
// Enable FSync generator
//
I2SGBLEnable(ulBase, MCASP_GBL_XFSYNC);
}
//*****************************************************************************
@ -390,8 +399,12 @@ long I2SDataGetNonBlocking(unsigned long ulBase, unsigned long ulDataLine,
//! format. The bit rate is provided in the \e ulBitClk parameter and the data
//! format in the \e ulConfig parameter.
//!
//! The \e ulConfig parameter is the logical OR of two values: the slot size
//! and the data read/write port select.
//! The \e ulConfig parameter is the logical OR of three values: the slot size
//! the data read/write port select, Master or Slave mode
//!
//! Follwoing selects the Master-Slave mode
//! -\b I2S_MODE_MASTER
//! -\b I2S_MODE_SLAVE
//!
//! Following selects the slot size:
//! -\b I2S_SLOT_SIZE_24
@ -409,6 +422,8 @@ void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,
{
unsigned long ulHClkDiv;
unsigned long ulClkDiv;
unsigned long ulSlotSize;
unsigned long ulBitMask;
//
// Calculate clock dividers
@ -429,39 +444,72 @@ void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,
ulClkDiv = ((ulI2SClk/(ulBitClk * (ulHClkDiv + 1))) & 0x1F);
}
HWREG(ulBase + MCASP_O_ACLKXCTL) = (0xA0|ulClkDiv);
//
//
//
ulClkDiv = ((ulConfig & I2S_MODE_SLAVE )?0x80:0xA0|ulClkDiv);
HWREG(ulBase + MCASP_O_ACLKXCTL) = ulClkDiv;
HWREG(ulBase + MCASP_O_AHCLKXCTL) = (0x8000|ulHClkDiv);
//
// Write the Tx format register
//
HWREG(ulBase + MCASP_O_TXFMT) = (0x18000 | (ulConfig & 0xFFFF));
HWREG(ulBase + MCASP_O_TXFMT) = (0x18000 | (ulConfig & 0x7FFF));
//
// Write the Rx format register
//
HWREG(ulBase + MCASP_O_RXFMT) = (0x18000 | ((ulConfig >> 16) &0xFFFF));
HWREG(ulBase + MCASP_O_RXFMT) = (0x18000 | ((ulConfig >> 16) &0x7FFF));
//
// Configure Tx FSync generator in I2S mode
// Check if in master mode
//
HWREG(ulBase + MCASP_O_TXFMCTL) = 0x113;
if( ulConfig & I2S_MODE_SLAVE)
{
//
// Configure Tx FSync generator in I2S mode
//
HWREG(ulBase + MCASP_O_TXFMCTL) = 0x111;
//
// Configure Rx FSync generator in I2S mode
//
HWREG(ulBase + MCASP_O_RXFMCTL) = 0x111;
}
else
{
//
// Configure Tx FSync generator in I2S mode
//
HWREG(ulBase + MCASP_O_TXFMCTL) = 0x113;
//
// Configure Rx FSync generator in I2S mode
//
HWREG(ulBase + MCASP_O_RXFMCTL) = 0x113;
}
//
// Configure Rx FSync generator in I2S mode
// Compute Slot Size
//
HWREG(ulBase + MCASP_O_RXFMCTL) = 0x113;
ulSlotSize = ((((ulConfig & 0xFF) >> 4) + 1) * 2);
//
// Creat the bit mask
//
ulBitMask = (0xFFFFFFFF >> (32 - ulSlotSize));
//
// Set Tx bit valid mask
//
HWREG(ulBase + MCASP_O_TXMASK) = 0xFFFFFFFF;
HWREG(ulBase + MCASP_O_TXMASK) = ulBitMask;
//
// Set Rx bit valid mask
//
HWREG(ulBase + MCASP_O_RXMASK) = 0xFFFFFFFF;
HWREG(ulBase + MCASP_O_RXMASK) = ulBitMask;
//
// Set Tx slot valid mask
@ -914,6 +962,48 @@ void I2SIntUnregister(unsigned long ulBase)
}
//*****************************************************************************
//
//! Set the active slots for Trasmitter
//!
//! \param ulBase is the base address of the I2S module.
//! \param ulActSlot is the bit-mask of activ slots
//!
//! This function sets the active slots for the transmitter. By default both
//! the slots are active. The parameter \e ulActSlot is logical OR follwoing
//! values:
//! -\b I2S_ACT_SLOT_EVEN
//! -\b I2S_ACT_SLOT_ODD
//!
//! \return None.
//
//*****************************************************************************
void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot)
{
HWREG(ulBase + MCASP_O_TXTDM) = ulActSlot;
}
//*****************************************************************************
//
//! Set the active slots for Receiver
//!
//! \param ulBase is the base address of the I2S module.
//! \param ulActSlot is the bit-mask of activ slots
//!
//! This function sets the active slots for the receiver. By default both
//! the slots are active. The parameter \e ulActSlot is logical OR follwoing
//! values:
//! -\b I2S_ACT_SLOT_EVEN
//! -\b I2S_ACT_SLOT_ODD
//!
//! \return None.
//
//*****************************************************************************
void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot)
{
HWREG(ulBase + MCASP_O_RXTDM) = ulActSlot;
}
//*****************************************************************************
//
// Close the Doxygen group.

20
cc3200/hal/i2s.h
View File

@ -64,12 +64,17 @@ extern "C"
// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter.
//
//*****************************************************************************
#define I2S_SLOT_SIZE_24 0x00B200B4
#define I2S_SLOT_SIZE_8 0x00300032
#define I2S_SLOT_SIZE_16 0x00700074
#define I2S_SLOT_SIZE_24 0x00B000B6
#define I2S_PORT_CPU 0x00000008
#define I2S_PORT_CPU 0x00080008
#define I2S_PORT_DMA 0x00000000
#define I2S_MODE_MASTER 0x00000000
#define I2S_MODE_SLAVE 0x00008000
//*****************************************************************************
//
// Values that can be passed as ulDataLine parameter.
@ -117,6 +122,15 @@ extern "C"
#define I2S_INT_RSTAFRM 0x00800000
#define I2S_INT_RDMA 0x40000000
//*****************************************************************************
//
// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet
//
//*****************************************************************************
#define I2S_ACT_SLOT_EVEN 0x00000001
#define I2S_ACT_SLOT_ODD 0x00000002
//*****************************************************************************
//
// Values that can be passed to I2SIntClear() as the
@ -188,6 +202,8 @@ extern unsigned long I2SIntStatus(unsigned long ulBase);
extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void I2SIntUnregister(unsigned long ulBase);
extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
//*****************************************************************************
//

2
cc3200/hal/pin.c
View File

@ -334,7 +334,7 @@ void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
//
// Isolate the output
//
HWREG(ulPad) |= 0xC00;
HWREG(ulPad) = 0xC00;
}
else

91
cc3200/hal/prcm.c
View File

@ -104,9 +104,24 @@
//*****************************************************************************
// Register Access and Updates
//
// Tick of SCC has a resolution of 32768Hz. Therefore, scaling SCC value by 32
// yields ~1 msec resolution. All operations of SCC in RTC context use ms unit.
//*****************************************************************************
// Tick of SCC has a resolution of 32768Hz, meaning 1 sec is equal to 32768
// clock ticks. Ideal way of getting time in millisecond will involve floating
// point arithmetic (division by 32.768). To avoid this, we simply divide it by
// 32, which will give a range from 0 -1023(instead of 0-999). To use this
// output correctly we have to take care of this inaccuracy externally.
// following wrapper can be used to convert the value from cycles to
// millisecond:
//
// CYCLES_U16MS(cycles) ((cycles *1000)/ 1024),
//
// Similarly, before setting the value, it must be first converted (from ms to
// cycles).
//
// U16MS_CYCLES(msec) ((msec *1024)/1000)
//
// Note: There is a precision loss of 1 ms with the above scheme.
//
//
#define SCC_U64MSEC_GET() (MAP_PRCMSlowClkCtrGet() >> 5)
#define SCC_U64MSEC_MATCH_SET(u64Msec) (MAP_PRCMSlowClkCtrMatchSet(u64Msec << 5))
#define SCC_U64MSEC_MATCH_GET() (MAP_PRCMSlowClkCtrMatchGet() >> 5)
@ -683,14 +698,24 @@ void PRCMLPDSRestoreInfoSet(unsigned long ulStackPtr, unsigned long ulProgCntr)
//! \sa PRCMLPDSRestoreInfoSet().
//!
//! \return None.
//!
//! \note The Test Power Domain is shutdown whenever the system
//! enters LPDS (by default). In order to avoid this and allow for
//! connecting back the debugger after waking up from LPDS,
//! the macro KEEP_TESTPD_ALIVE has to be defined while building the library.
//! This is recommended for development purposes only as it adds to
//! the current consumption of the system.
//!
//
//*****************************************************************************
void PRCMLPDSEnter(void)
{
#ifndef DEBUG
//
// Disable TestPD
//
HWREG(0x4402E168) |= (1<<9);
#endif
//
// Set bandgap duty cycle to 1
@ -700,8 +725,7 @@ void PRCMLPDSEnter(void)
//
// Request LPDS
//
HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ)
= APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ;
HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ;
__asm(" nop\n"
" nop\n"
@ -1846,6 +1870,63 @@ void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue)
UtilsDelay((80*200)/3);
}
//*****************************************************************************
//
//! \param ulDivider is clock frequency divider value
//! \param ulWidth is the width of the high pulse
//!
//! This function sets the input frequency for camera module.
//!
//! The frequency is calculated as follows:
//!
//! f_out = 240MHz/ulDivider;
//!
//! The parameter \e ulWidth sets the width of the high pulse.
//!
//! For e.g.:
//!
//! ulDivider = 4;
//! ulWidth = 2;
//!
//! f_out = 30 MHz and 50% duty cycle
//!
//! And,
//!
//! ulDivider = 4;
//! ulWidth = 1;
//!
//! f_out = 30 MHz and 25% duty cycle
//!
//! \return 0 on success, 1 on error
//
//*****************************************************************************
unsigned long PRCMCameraFreqSet(unsigned char ulDivider, unsigned char ulWidth)
{
if(ulDivider > ulWidth && ulWidth != 0 )
{
//
// Set the hifh pulse width
//
HWREG(ARCM_BASE +
APPS_RCM_O_CAMERA_CLK_GEN) = (((ulWidth & 0x07) -1) << 8);
//
// Set the low pulse width
//
HWREG(ARCM_BASE +
APPS_RCM_O_CAMERA_CLK_GEN) = ((ulDivider - ulWidth - 1) & 0x07);
//
// Return success
//
return 0;
}
//
// Success;
//
return 1;
}
//*****************************************************************************
//
// Close the Doxygen group.

1
cc3200/hal/prcm.h
View File

@ -265,6 +265,7 @@ extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec);
extern void PRCMCC3200MCUInit(void);
extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr);
extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue);
extern unsigned long PRCMCameraFreqSet(unsigned char ulDivider, unsigned char ulWidth);
//*****************************************************************************

11
cc3200/hal/rom_patch.h
View File

@ -84,4 +84,15 @@
#undef ROM_GPIODirModeGet
#undef ROM_GPIOIntTypeGet
#undef ROM_I2CMasterInitExpClk
#undef ROM_AESDataProcess
#undef ROM_DESDataProcess
#undef ROM_I2SEnable
#undef ROM_I2SConfigSetExpClk
#undef ROM_PinConfigSet
#undef ROM_PRCMLPDSEnter
#undef ROM_PRCMCC3200MCUInit
#undef ROM_SDHostIntStatus
#undef ROM_SDHostBlockCountSet
#undef ROM_UARTModemControlSet
#undef ROM_UARTModemControlClear

6
cc3200/hal/sdhost.c
View File

@ -512,7 +512,7 @@ SDHostIntStatus(unsigned long ulBase)
//
// Get DMA done interrupt status
//
ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET);
ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW);
ulIntStatus = (ulIntStatus << 30);
//
@ -562,7 +562,7 @@ SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags)
//! \param ulErrMask is the bit mask of card status errors to be enabled
//!
//! This function sets the card status error mask for response type R1, R1b,
//! R5, R5b and R6 response. The parameter \ulErrMask is the bit mask of card
//! R5, R5b and R6 response. The parameter \e ulErrMask is the bit mask of card
//! status errors to be enabled, if the corresponding bits in the 'card status'
//! field of a respose are set then the host controller indicates a card error
//! interrupt status. Only bits referenced as type E (error) in status field in
@ -732,7 +732,7 @@ SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount)
//
// Set the number of blocks
//
HWREG(ulBase + MMCHS_O_BLK) |= ((ulRegVal & 0x0000FFFF)|
HWREG(ulBase + MMCHS_O_BLK) = ((ulRegVal & 0x0000FFFF)|
(ulBlkCount << 16));
}

2
cc3200/hal/sdhost.h
View File

@ -75,7 +75,7 @@ extern "C"
#define SDHOST_INT_CEB 0x00040000
#define SDHOST_INT_DTO 0x00100000
#define SDHOST_INT_DCRC 0x00200000
#define SDHOST_INT_DEB 0x00300000
#define SDHOST_INT_DEB 0x00400000
#define SDHOST_INT_CERR 0x10000000
#define SDHOST_INT_BADA 0x20000000
#define SDHOST_INT_DMARD 0x40000000

45
cc3200/hal/timer.c
View File

@ -617,6 +617,45 @@ TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
HWREG(ulBase + TIMER_O_TBR));
}
//*****************************************************************************
//
//! Sets the current timer value.
//!
//! \param ulBase is the base address of the timer module.
//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
//! for 32-bit operation.
//! \param ulValue is the new value of the timer to be set.
//!
//! This function sets the current value of the specified timer.
//!
//! \return None.
//
//*****************************************************************************
void
TimerValueSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue)
{
//
// Check the arguments.
//
ASSERT(TimerBaseValid(ulBase));
ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
//
// Set the appropriate timer value.
//
if( (ulTimer == TIMER_A) )
{
HWREG(ulBase + TIMER_O_TAV) = ulValue;
}
else
{
HWREG(ulBase + TIMER_O_TBV) = ulValue;
}
}
//*****************************************************************************
//
//! Sets the timer match value.
@ -979,8 +1018,8 @@ TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//
//! Enables the events that can trigger a DMA request.
//!
//! \param ui32Base is the base address of the timer module.
//! \param ui32DMAEvent is a bit mask of the events that can trigger DMA.
//! \param ulBase is the base address of the timer module.
//! \param ulDMAEvent is a bit mask of the events that can trigger DMA.
//!
//! This function enables the timer events that can trigger the start of a DMA
//! sequence. The DMA trigger events are specified in the \e ui32DMAEvent
@ -1022,7 +1061,7 @@ TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent)
//
//! Returns the events that can trigger a DMA request.
//!
//! \param ui32Base is the base address of the timer module.
//! \param ulBase is the base address of the timer module.
//!
//! This function returns the timer events that can trigger the start of a DMA
//! sequence. The DMA trigger events are the logical OR of the following

2
cc3200/hal/timer.h
View File

@ -180,6 +180,8 @@ extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerValueSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);

12
cc3200/hal/uart.c
View File

@ -1167,13 +1167,8 @@ UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//
// Determine the interrupt number based on the UART port.
//
#if 1
ulInt = UARTIntNumberGet(ulBase);
#else
ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
#endif
ulInt = UARTIntNumberGet(ulBase);
//
// Register the interrupt handler.
@ -1216,12 +1211,7 @@ UARTIntUnregister(unsigned long ulBase)
//
// Determine the interrupt number based on the UART port.
//
#if 1
ulInt = UARTIntNumberGet(ulBase);
#else
ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
#endif
//
// Disable the interrupt.

3
cc3200/mods/modwlan.c
View File

@ -428,6 +428,9 @@ modwlan_Status_t wlan_sl_enable (SlWlanMode_t mode, const char *ssid, uint8_t ss
// Unregister mDNS services
ASSERT_ON_ERROR(sl_NetAppMDNSUnRegisterService(0, 0));
// Stop the internal HTTP server
sl_NetAppStop(SL_NET_APP_HTTP_SERVER_ID);
// Remove all 64 filters (8 * 8)
_WlanRxFilterOperationCommandBuff_t RxFilterIdMask;
memset ((void *)&RxFilterIdMask, 0 ,sizeof(RxFilterIdMask));