From 0bbb7a8199db3f75cbd1f6151c011cad8fc85071 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Thu, 28 Sep 2017 20:33:44 -0700 Subject: [PATCH] Add support for patching newer ASF4 code. (#292) * atmel-samd: Support patching after updating ASF4. This makes it possible to automatically fix newer code. * atmel-samd: Update ASF4 to include flash APIs for SAMD51. This is the first automatic update that has caused a few deletions where code was previously copied instead of moved. This is a prerequisite for #260. --- .../patches/samd21/assert_redefined.patch | 20 + .../asf4/patches/samd21/cast-align.patch | 12 + .../asf4/patches/samd21/cortex_sc.patch | 20 + .../asf4/patches/samd21/gclk_defined.patch | 11 + .../samd21/little_endian_redefined.patch | 22 + .../samd21/make_usb_cache_accessible.patch | 11 + .../asf4/patches/samd21/mark_used_no_c.patch | 20 + .../asf4/patches/samd21/sysctrl_fix.patch | 11 + .../asf4/patches/samd21/usb_undefined.patch | 22 + .../patches/samd51/assert_redefined.patch | 20 + .../asf4/patches/samd51/cast-align.patch | 12 + .../samd51/little_endian_redefined.patch | 99 + .../samd51/make_usb_cache_accessible.patch | 19 + .../asf4/patches/samd51/mark_used_no_c.patch | 20 + .../asf4/patches/samd51/usb_undefined.patch | 22 + .../asf4/samd21/CMSIS/Include/core_cmInstr.h | 2 +- atmel-samd/asf4/samd21/armcc/Makefile | 12 +- atmel-samd/asf4/samd21/driver_init.c | 44 +- atmel-samd/asf4/samd21/gcc/Makefile | 12 +- .../asf4/samd21/gcc/gcc/startup_samd21.c | 21 +- .../asf4/samd21/hal/include/hpl_dac_async.h | 2 +- .../asf4/samd21/hal/include/hpl_dac_sync.h | 2 +- .../asf4/samd21/hal/include/hpl_reset.h | 13 +- .../asf4/samd21/hal/src/hal_i2c_m_sync.c | 12 +- .../asf4/samd21/hal/src/hal_usb_device.c | 4 +- .../asf4/samd21/hpl/sercom/hpl_sercom.c | 14 +- atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c | 4 +- .../samd21a/gcc/gcc/samd21g18a_flash.ld | 142 -- .../samd21/samd21a/gcc/gcc/samd21g18a_sram.ld | 141 -- .../samd21/samd21a/gcc/gcc/startup_samd21.c | 254 --- .../asf4/samd21/samd21a/gcc/system_samd21.c | 63 - .../samd21a/include/component-version.h | 65 - .../samd21/samd21a/include/component/ac.h | 544 ----- .../samd21/samd21a/include/component/adc.h | 684 ------- .../samd21/samd21a/include/component/dac.h | 271 --- .../samd21/samd21a/include/component/dmac.h | 1072 ---------- .../samd21/samd21a/include/component/dsu.h | 536 ----- .../samd21/samd21a/include/component/eic.h | 666 ------ .../samd21/samd21a/include/component/evsys.h | 589 ------ .../samd21/samd21a/include/component/gclk.h | 295 --- .../samd21a/include/component/hmatrixb.h | 103 - .../samd21/samd21a/include/component/i2s.h | 624 ------ .../samd21/samd21a/include/component/mtb.h | 381 ---- .../samd21a/include/component/nvmctrl.h | 512 ----- .../samd21/samd21a/include/component/pac.h | 89 - .../samd21/samd21a/include/component/pm.h | 518 ----- .../samd21/samd21a/include/component/port.h | 379 ---- .../samd21/samd21a/include/component/rtc.h | 1053 ---------- .../samd21/samd21a/include/component/sercom.h | 1493 -------------- .../samd21a/include/component/sysctrl.h | 933 --------- .../samd21/samd21a/include/component/tc.h | 669 ------ .../samd21/samd21a/include/component/tcc.h | 1802 ----------------- .../samd21/samd21a/include/component/usb.h | 1790 ---------------- .../samd21/samd21a/include/component/wdt.h | 288 --- .../asf4/samd21/samd21a/include/instance/ac.h | 72 - .../samd21/samd21a/include/instance/adc.h | 84 - .../samd21/samd21a/include/instance/dac.h | 59 - .../samd21/samd21a/include/instance/dmac.h | 94 - .../samd21/samd21a/include/instance/dsu.h | 84 - .../samd21/samd21a/include/instance/eic.h | 63 - .../samd21/samd21a/include/instance/evsys.h | 179 -- .../samd21/samd21a/include/instance/gclk.h | 64 - .../samd21/samd21a/include/instance/i2s.h | 79 - .../samd21/samd21a/include/instance/mtb.h | 88 - .../samd21/samd21a/include/instance/nvmctrl.h | 76 - .../samd21/samd21a/include/instance/pac0.h | 44 - .../samd21/samd21a/include/instance/pac1.h | 44 - .../samd21/samd21a/include/instance/pac2.h | 44 - .../asf4/samd21/samd21a/include/instance/pm.h | 72 - .../samd21/samd21a/include/instance/port.h | 121 -- .../samd21/samd21a/include/instance/rtc.h | 102 - .../samd21a/include/instance/sbmatrix.h | 150 -- .../samd21/samd21a/include/instance/sercom0.h | 128 -- .../samd21/samd21a/include/instance/sercom1.h | 128 -- .../samd21/samd21a/include/instance/sercom2.h | 128 -- .../samd21/samd21a/include/instance/sercom3.h | 128 -- .../samd21/samd21a/include/instance/sercom4.h | 128 -- .../samd21/samd21a/include/instance/sercom5.h | 128 -- .../samd21/samd21a/include/instance/sysctrl.h | 106 - .../samd21/samd21a/include/instance/tc3.h | 96 - .../samd21/samd21a/include/instance/tc4.h | 96 - .../samd21/samd21a/include/instance/tc5.h | 96 - .../samd21/samd21a/include/instance/tc6.h | 96 - .../samd21/samd21a/include/instance/tc7.h | 96 - .../samd21/samd21a/include/instance/tcc0.h | 116 -- .../samd21/samd21a/include/instance/tcc1.h | 104 - .../samd21/samd21a/include/instance/tcc2.h | 100 - .../samd21/samd21a/include/instance/usb.h | 329 --- .../samd21/samd21a/include/instance/wdt.h | 56 - .../samd21/samd21a/include/pio/samd21e15a.h | 651 ------ .../samd21/samd21a/include/pio/samd21e16a.h | 651 ------ .../samd21/samd21a/include/pio/samd21e17a.h | 651 ------ .../samd21/samd21a/include/pio/samd21e18a.h | 651 ------ .../samd21/samd21a/include/pio/samd21g15a.h | 937 --------- .../samd21/samd21a/include/pio/samd21g16a.h | 937 --------- .../samd21/samd21a/include/pio/samd21g17a.h | 937 --------- .../samd21/samd21a/include/pio/samd21g17au.h | 882 -------- .../samd21/samd21a/include/pio/samd21g18a.h | 937 --------- .../samd21/samd21a/include/pio/samd21g18au.h | 882 -------- .../samd21/samd21a/include/pio/samd21j15a.h | 1225 ----------- .../samd21/samd21a/include/pio/samd21j16a.h | 1225 ----------- .../samd21/samd21a/include/pio/samd21j17a.h | 1225 ----------- .../samd21/samd21a/include/pio/samd21j18a.h | 1225 ----------- atmel-samd/asf4/samd21/samd21a/include/sam.h | 63 - .../asf4/samd21/samd21a/include/samd21.h | 69 - .../asf4/samd21/samd21a/include/samd21e15a.h | 552 ----- .../asf4/samd21/samd21a/include/samd21e16a.h | 552 ----- .../asf4/samd21/samd21a/include/samd21e17a.h | 552 ----- .../asf4/samd21/samd21a/include/samd21e18a.h | 552 ----- .../asf4/samd21/samd21a/include/samd21g15a.h | 564 ------ .../asf4/samd21/samd21a/include/samd21g16a.h | 564 ------ .../asf4/samd21/samd21a/include/samd21g17a.h | 564 ------ .../asf4/samd21/samd21a/include/samd21g17au.h | 576 ------ .../asf4/samd21/samd21a/include/samd21g18a.h | 564 ------ .../asf4/samd21/samd21a/include/samd21g18au.h | 576 ------ .../asf4/samd21/samd21a/include/samd21j15a.h | 576 ------ .../asf4/samd21/samd21a/include/samd21j16a.h | 576 ------ .../asf4/samd21/samd21a/include/samd21j17a.h | 576 ------ .../asf4/samd21/samd21a/include/samd21j18a.h | 576 ------ .../samd21/samd21a/include/system_samd21.h | 47 - .../samd21/usb/class/cdc/usb_protocol_cdc.h | 35 +- .../class/composite/device/composite_desc.h | 26 +- .../composite/device/usbd_composite_config.h | 248 +++ .../asf4/samd21/usb/class/msc/device/mscdf.c | 754 +++++++ .../asf4/samd21/usb/class/msc/device/mscdf.h | 123 ++ atmel-samd/asf4/samd21/usb/device/usbdc.c | 2 + atmel-samd/asf4/samd21/usb_start.c | 56 +- atmel-samd/asf4/samd21/usb_start.h | 15 + atmel-samd/asf4/samd51/armcc/Makefile | 25 +- .../asf4/samd51/atmel_start_config.atstart | 103 +- .../asf4/samd51/config/hpl_nvmctrl_config.h | 36 + .../asf4/samd51/config/hpl_sercom_config.h | 270 +-- .../samd51/config/peripheral_clk_config.h | 160 +- atmel-samd/asf4/samd51/driver_init.c | 84 +- atmel-samd/asf4/samd51/driver_init.h | 25 +- .../asf4/samd51/examples/driver_examples.c | 44 +- .../asf4/samd51/examples/driver_examples.h | 4 +- atmel-samd/asf4/samd51/gcc/Makefile | 25 +- .../asf4/samd51/gcc/gcc/samd51g19a_flash.ld | 19 +- .../asf4/samd51/gcc/gcc/samd51g19a_sram.ld | 19 +- .../asf4/samd51/gcc/gcc/startup_samd51.c | 15 +- atmel-samd/asf4/samd51/gcc/system_samd51.c | 15 +- .../asf4/samd51/hal/documentation/flash.rst | 52 + .../asf4/samd51/hal/include/hal_flash.h | 219 ++ .../asf4/samd51/hal/include/hpl_dac_async.h | 2 +- .../asf4/samd51/hal/include/hpl_dac_sync.h | 2 +- .../asf4/samd51/hal/include/hpl_flash.h | 228 +++ .../asf4/samd51/hal/include/hpl_reset.h | 16 +- .../asf4/samd51/hal/include/hpl_user_area.h | 133 ++ atmel-samd/asf4/samd51/hal/src/hal_flash.c | 324 +++ .../asf4/samd51/hal/src/hal_i2c_m_sync.c | 12 +- .../asf4/samd51/hal/src/hal_usb_device.c | 2 +- atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c | 1 - .../asf4/samd51/hpl/nvmctrl/hpl_nvmctrl.c | 699 +++++++ .../asf4/samd51/hpl/sercom/hpl_sercom.c | 14 +- atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c | 5 +- .../asf4/samd51/include/component-version.h | 4 +- atmel-samd/asf4/samd51/include/component/ac.h | 19 +- .../asf4/samd51/include/component/adc.h | 19 +- .../asf4/samd51/include/component/aes.h | 19 +- .../asf4/samd51/include/component/ccl.h | 19 +- .../asf4/samd51/include/component/cmcc.h | 19 +- .../asf4/samd51/include/component/dac.h | 19 +- .../asf4/samd51/include/component/dmac.h | 19 +- .../asf4/samd51/include/component/dsu.h | 19 +- .../asf4/samd51/include/component/eic.h | 19 +- .../asf4/samd51/include/component/evsys.h | 19 +- .../asf4/samd51/include/component/freqm.h | 19 +- .../asf4/samd51/include/component/gclk.h | 19 +- .../asf4/samd51/include/component/hmatrixb.h | 21 +- .../asf4/samd51/include/component/i2s.h | 19 +- .../asf4/samd51/include/component/icm.h | 19 +- .../asf4/samd51/include/component/mclk.h | 19 +- .../asf4/samd51/include/component/nvmctrl.h | 21 +- .../samd51/include/component/osc32kctrl.h | 19 +- .../asf4/samd51/include/component/oscctrl.h | 19 +- .../asf4/samd51/include/component/pac.h | 19 +- .../asf4/samd51/include/component/pcc.h | 19 +- .../asf4/samd51/include/component/pdec.h | 19 +- atmel-samd/asf4/samd51/include/component/pm.h | 19 +- .../asf4/samd51/include/component/port.h | 19 +- .../asf4/samd51/include/component/qspi.h | 19 +- .../asf4/samd51/include/component/ramecc.h | 19 +- .../asf4/samd51/include/component/rstc.h | 19 +- .../asf4/samd51/include/component/rtc.h | 19 +- .../asf4/samd51/include/component/sdhc.h | 19 +- .../asf4/samd51/include/component/sercom.h | 19 +- .../asf4/samd51/include/component/supc.h | 19 +- .../asf4/samd51/include/component/tal.h | 19 +- atmel-samd/asf4/samd51/include/component/tc.h | 19 +- .../asf4/samd51/include/component/tcc.h | 19 +- .../asf4/samd51/include/component/trng.h | 19 +- .../asf4/samd51/include/component/usb.h | 19 +- .../asf4/samd51/include/component/wdt.h | 19 +- atmel-samd/asf4/samd51/include/instance/ac.h | 19 +- .../asf4/samd51/include/instance/adc0.h | 20 +- .../asf4/samd51/include/instance/adc1.h | 19 +- atmel-samd/asf4/samd51/include/instance/aes.h | 19 +- atmel-samd/asf4/samd51/include/instance/ccl.h | 19 +- .../asf4/samd51/include/instance/cmcc.h | 19 +- atmel-samd/asf4/samd51/include/instance/dac.h | 19 +- .../asf4/samd51/include/instance/dmac.h | 19 +- atmel-samd/asf4/samd51/include/instance/dsu.h | 19 +- atmel-samd/asf4/samd51/include/instance/eic.h | 19 +- .../asf4/samd51/include/instance/evsys.h | 19 +- .../asf4/samd51/include/instance/freqm.h | 19 +- .../asf4/samd51/include/instance/gclk.h | 19 +- .../asf4/samd51/include/instance/hmatrix.h | 63 +- atmel-samd/asf4/samd51/include/instance/i2s.h | 19 +- atmel-samd/asf4/samd51/include/instance/icm.h | 19 +- .../asf4/samd51/include/instance/mclk.h | 19 +- .../asf4/samd51/include/instance/nvmctrl.h | 19 +- .../asf4/samd51/include/instance/osc32kctrl.h | 19 +- .../asf4/samd51/include/instance/oscctrl.h | 19 +- atmel-samd/asf4/samd51/include/instance/pac.h | 19 +- atmel-samd/asf4/samd51/include/instance/pcc.h | 19 +- .../asf4/samd51/include/instance/pdec.h | 19 +- atmel-samd/asf4/samd51/include/instance/pm.h | 19 +- .../asf4/samd51/include/instance/port.h | 19 +- .../asf4/samd51/include/instance/qspi.h | 19 +- .../asf4/samd51/include/instance/ramecc.h | 19 +- .../asf4/samd51/include/instance/rstc.h | 19 +- atmel-samd/asf4/samd51/include/instance/rtc.h | 19 +- .../asf4/samd51/include/instance/sdhc0.h | 19 +- .../asf4/samd51/include/instance/sdhc1.h | 19 +- .../asf4/samd51/include/instance/sercom0.h | 19 +- .../asf4/samd51/include/instance/sercom1.h | 19 +- .../asf4/samd51/include/instance/sercom2.h | 19 +- .../asf4/samd51/include/instance/sercom3.h | 19 +- .../asf4/samd51/include/instance/sercom4.h | 19 +- .../asf4/samd51/include/instance/sercom5.h | 19 +- .../asf4/samd51/include/instance/sercom6.h | 19 +- .../asf4/samd51/include/instance/sercom7.h | 19 +- .../asf4/samd51/include/instance/supc.h | 19 +- atmel-samd/asf4/samd51/include/instance/tal.h | 19 +- atmel-samd/asf4/samd51/include/instance/tc0.h | 19 +- atmel-samd/asf4/samd51/include/instance/tc1.h | 19 +- atmel-samd/asf4/samd51/include/instance/tc2.h | 19 +- atmel-samd/asf4/samd51/include/instance/tc3.h | 19 +- atmel-samd/asf4/samd51/include/instance/tc4.h | 19 +- atmel-samd/asf4/samd51/include/instance/tc5.h | 19 +- atmel-samd/asf4/samd51/include/instance/tc6.h | 19 +- atmel-samd/asf4/samd51/include/instance/tc7.h | 19 +- .../asf4/samd51/include/instance/tcc0.h | 19 +- .../asf4/samd51/include/instance/tcc1.h | 19 +- .../asf4/samd51/include/instance/tcc2.h | 19 +- .../asf4/samd51/include/instance/tcc3.h | 19 +- .../asf4/samd51/include/instance/tcc4.h | 19 +- .../asf4/samd51/include/instance/trng.h | 19 +- atmel-samd/asf4/samd51/include/instance/usb.h | 19 +- atmel-samd/asf4/samd51/include/instance/wdt.h | 19 +- .../asf4/samd51/include/pio/samd51g18a.h | 19 +- .../asf4/samd51/include/pio/samd51g19a.h | 19 +- .../asf4/samd51/include/pio/samd51j18a.h | 19 +- .../asf4/samd51/include/pio/samd51j19a.h | 19 +- .../asf4/samd51/include/pio/samd51j20a.h | 19 +- .../asf4/samd51/include/pio/samd51n19a.h | 19 +- .../asf4/samd51/include/pio/samd51n20a.h | 19 +- .../asf4/samd51/include/pio/samd51p19a.h | 19 +- .../asf4/samd51/include/pio/samd51p20a.h | 19 +- atmel-samd/asf4/samd51/include/samd51.h | 19 +- atmel-samd/asf4/samd51/include/samd51g18a.h | 24 +- atmel-samd/asf4/samd51/include/samd51g19a.h | 24 +- atmel-samd/asf4/samd51/include/samd51j18a.h | 24 +- atmel-samd/asf4/samd51/include/samd51j19a.h | 24 +- atmel-samd/asf4/samd51/include/samd51j20a.h | 24 +- atmel-samd/asf4/samd51/include/samd51n19a.h | 24 +- atmel-samd/asf4/samd51/include/samd51n20a.h | 24 +- atmel-samd/asf4/samd51/include/samd51p19a.h | 24 +- atmel-samd/asf4/samd51/include/samd51p20a.h | 24 +- .../asf4/samd51/include/system_samd51.h | 19 +- .../samd51/usb/class/cdc/usb_protocol_cdc.h | 35 +- .../class/composite/device/composite_desc.h | 26 +- .../composite/device/usbd_composite_config.h | 250 ++- .../asf4/samd51/usb/class/msc/device/mscdf.c | 754 +++++++ .../asf4/samd51/usb/class/msc/device/mscdf.h | 123 ++ atmel-samd/asf4/samd51/usb/device/usbdc.c | 2 + atmel-samd/asf4/samd51/usb_start.c | 54 +- atmel-samd/asf4/samd51/usb_start.h | 15 + .../boards/metro_m4_express/mpconfigboard.mk | 2 +- atmel-samd/supervisor/serial.c | 2 + atmel-samd/tools/samd51.json | 2 +- atmel-samd/tools/update_asf.py | 62 +- supervisor/port.h | 4 + 284 files changed, 6340 insertions(+), 42199 deletions(-) create mode 100644 atmel-samd/asf4/patches/samd21/assert_redefined.patch create mode 100644 atmel-samd/asf4/patches/samd21/cast-align.patch create mode 100644 atmel-samd/asf4/patches/samd21/cortex_sc.patch create mode 100644 atmel-samd/asf4/patches/samd21/gclk_defined.patch create mode 100644 atmel-samd/asf4/patches/samd21/little_endian_redefined.patch create mode 100644 atmel-samd/asf4/patches/samd21/make_usb_cache_accessible.patch create mode 100644 atmel-samd/asf4/patches/samd21/mark_used_no_c.patch create mode 100644 atmel-samd/asf4/patches/samd21/sysctrl_fix.patch create mode 100644 atmel-samd/asf4/patches/samd21/usb_undefined.patch create mode 100644 atmel-samd/asf4/patches/samd51/assert_redefined.patch create mode 100644 atmel-samd/asf4/patches/samd51/cast-align.patch create mode 100644 atmel-samd/asf4/patches/samd51/little_endian_redefined.patch create mode 100644 atmel-samd/asf4/patches/samd51/make_usb_cache_accessible.patch create mode 100644 atmel-samd/asf4/patches/samd51/mark_used_no_c.patch create mode 100644 atmel-samd/asf4/patches/samd51/usb_undefined.patch delete mode 100644 atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_flash.ld delete mode 100644 atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_sram.ld delete mode 100644 atmel-samd/asf4/samd21/samd21a/gcc/gcc/startup_samd21.c delete mode 100644 atmel-samd/asf4/samd21/samd21a/gcc/system_samd21.c delete mode 100644 atmel-samd/asf4/samd21/samd21a/include/component-version.h delete mode 100644 atmel-samd/asf4/samd21/samd21a/include/component/ac.h delete mode 100644 atmel-samd/asf4/samd21/samd21a/include/component/adc.h delete mode 100644 atmel-samd/asf4/samd21/samd21a/include/component/dac.h delete mode 100644 atmel-samd/asf4/samd21/samd21a/include/component/dmac.h delete mode 100644 atmel-samd/asf4/samd21/samd21a/include/component/dsu.h delete mode 100644 atmel-samd/asf4/samd21/samd21a/include/component/eic.h delete mode 100644 atmel-samd/asf4/samd21/samd21a/include/component/evsys.h delete mode 100644 atmel-samd/asf4/samd21/samd21a/include/component/gclk.h delete mode 100644 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+++ b/atmel-samd/asf4/patches/samd21/assert_redefined.patch @@ -0,0 +1,20 @@ +--- samd21_vanilla/hal/utils/include/utils_assert.h 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/hal/utils/include/utils_assert.h 2017-09-19 13:07:29.000000000 -0700 +@@ -72,7 +72,7 @@ + if (!(condition)) \ + __asm("BKPT #0"); + #else +-#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) ++#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line) + #endif + + #else /* DEBUG */ +@@ -95,7 +95,7 @@ + * \param[in] file File name + * \param[in] line Line number + */ +-void assert(const bool condition, const char *const file, const int line); ++void asf_assert(const bool condition, const char *const file, const int line); + + #ifdef __cplusplus + } diff --git a/atmel-samd/asf4/patches/samd21/cast-align.patch b/atmel-samd/asf4/patches/samd21/cast-align.patch new file mode 100644 index 0000000000..04ddf9bf53 --- /dev/null +++ b/atmel-samd/asf4/patches/samd21/cast-align.patch @@ -0,0 +1,12 @@ +--- samd21_vanilla/hal/src/hal_timer.c 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/hal/src/hal_timer.c 2017-09-19 13:07:29.000000000 -0700 +@@ -236,7 +236,10 @@ + */ + static void timer_process_counted(struct _timer_device *device) + { ++ #pragma GCC diagnostic push ++ #pragma GCC diagnostic ignored "-Wcast-align" + struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); ++ #pragma GCC diagnostic pop + struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); + uint32_t time = ++timer->time; diff --git a/atmel-samd/asf4/patches/samd21/cortex_sc.patch b/atmel-samd/asf4/patches/samd21/cortex_sc.patch new file mode 100644 index 0000000000..ed10e05732 --- /dev/null +++ b/atmel-samd/asf4/patches/samd21/cortex_sc.patch @@ -0,0 +1,20 @@ +--- samd21_vanilla/CMSIS/Include/core_cmInstr.h 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/CMSIS/Include/core_cmInstr.h 2017-09-19 13:07:29.000000000 -0700 +@@ -171,7 +171,7 @@ + #define __BKPT(value) __breakpoint(value) + + +-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) ++#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300) + + /** \brief Reverse bit order of value + +@@ -538,7 +538,7 @@ + #define __BKPT(value) __ASM volatile ("bkpt "#value) + + +-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) ++#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300) + + /** \brief Reverse bit order of value + diff --git a/atmel-samd/asf4/patches/samd21/gclk_defined.patch b/atmel-samd/asf4/patches/samd21/gclk_defined.patch new file mode 100644 index 0000000000..9a26609dde --- /dev/null +++ b/atmel-samd/asf4/patches/samd21/gclk_defined.patch @@ -0,0 +1,11 @@ +--- samd21_vanilla/hpl/gclk/hpl_gclk.c 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/hpl/gclk/hpl_gclk.c 2017-09-19 13:07:29.000000000 -0700 +@@ -147,7 +147,7 @@ + | CONF_GCLK_GEN_7_SRC + | GCLK_GENCTRL_ID(7)); + #endif +-#if CONF_GCLK_GEN_8_GENEN == 1 ++#if defined(CONF_GCLK_GEN_8_GENEN) && CONF_GCLK_GEN_8_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_8_DIV) | GCLK_GENDIV_ID(8)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) diff --git a/atmel-samd/asf4/patches/samd21/little_endian_redefined.patch b/atmel-samd/asf4/patches/samd21/little_endian_redefined.patch new file mode 100644 index 0000000000..48b7393505 --- /dev/null +++ b/atmel-samd/asf4/patches/samd21/little_endian_redefined.patch @@ -0,0 +1,22 @@ +--- samd21_vanilla/include/samd21e18a.h 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/include/samd21e18a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -210,7 +210,7 @@ + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++// #define LITTLE_ENDIAN 1 + #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ + #define __MPU_PRESENT 0 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +--- samd21_vanilla/include/samd21g18a.h 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/include/samd21g18a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -214,7 +214,7 @@ + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ + #define __MPU_PRESENT 0 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/atmel-samd/asf4/patches/samd21/make_usb_cache_accessible.patch b/atmel-samd/asf4/patches/samd21/make_usb_cache_accessible.patch new file mode 100644 index 0000000000..d80879160a --- /dev/null +++ b/atmel-samd/asf4/patches/samd21/make_usb_cache_accessible.patch @@ -0,0 +1,11 @@ +--- samd21_vanilla/hpl/usb/hpl_usb.c 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/hpl/usb/hpl_usb.c 2017-09-19 13:07:29.000000000 -0700 +@@ -300,7 +300,7 @@ + /** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ + #if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1 +-static uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; ++uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; + #else + #define _usb_ep1_cache NULL + #endif diff --git a/atmel-samd/asf4/patches/samd21/mark_used_no_c.patch b/atmel-samd/asf4/patches/samd21/mark_used_no_c.patch new file mode 100644 index 0000000000..8949d6ff64 --- /dev/null +++ b/atmel-samd/asf4/patches/samd21/mark_used_no_c.patch @@ -0,0 +1,20 @@ +--- samd21_vanilla/gcc/gcc/startup_samd21.c 2017-09-20 22:33:52.000000000 -0700 ++++ samd21/gcc/gcc/startup_samd21.c 2017-09-19 13:07:30.000000000 -0700 +@@ -104,7 +105,7 @@ + void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + + /* Exception Table */ +-__attribute__((section(".vectors"))) const DeviceVectors exception_table = { ++__attribute__((section(".vectors"), used)) const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void *)(&_estack), +@@ -234,7 +234,7 @@ + NVMCTRL->CTRLB.bit.MANW = 1; + + /* Initialize the C library */ +- __libc_init_array(); ++ //__libc_init_array(); + + /* Branch to main function */ + main(); diff --git a/atmel-samd/asf4/patches/samd21/sysctrl_fix.patch b/atmel-samd/asf4/patches/samd21/sysctrl_fix.patch new file mode 100644 index 0000000000..f271c21add --- /dev/null +++ b/atmel-samd/asf4/patches/samd21/sysctrl_fix.patch @@ -0,0 +1,11 @@ +--- samd21_vanilla/hpl/sysctrl/hpl_sysctrl.c 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/hpl/sysctrl/hpl_sysctrl.c 2017-09-19 13:07:29.000000000 -0700 +@@ -114,7 +114,7 @@ + + #if CONF_OSCULP32K_CONFIG == 1 + hri_sysctrl_write_OSCULP32K_reg(hw, +-#if OSC32K_OVERWRITE_CALIBRATION == 1 ++#if CONF_OSC32K_OVERWRITE_CALIBRATION == 1 + SYSCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) | + #else + SYSCTRL_OSCULP32K_CALIB(calib) | diff --git a/atmel-samd/asf4/patches/samd21/usb_undefined.patch b/atmel-samd/asf4/patches/samd21/usb_undefined.patch new file mode 100644 index 0000000000..ec677cb701 --- /dev/null +++ b/atmel-samd/asf4/patches/samd21/usb_undefined.patch @@ -0,0 +1,22 @@ +--- samd21_vanilla/usb/device/usbdc.c 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/usb/device/usbdc.c 2017-09-19 13:07:30.000000000 -0700 +@@ -739,7 +737,7 @@ + */ + int32_t usbdc_check_desces(struct usbdc_descriptors *desces) + { +-#if CONF_USBD_HS_SP ++#ifdef CONF_USBD_HS_SP + int32_t rc; + if (desces->hs == NULL && desces->ls_fs == NULL) { + return ERR_NOT_FOUND; +--- samd21_vanilla/usb/device/usbdc.h 2017-09-28 12:05:22.000000000 -0700 ++++ samd21/usb/device/usbdc.h 2017-09-19 13:07:30.000000000 -0700 +@@ -105,7 +105,7 @@ + /** Describes the USB device core descriptors. */ + struct usbdc_descriptors { + struct usbd_descriptors *ls_fs; +-#if CONF_USBD_HS_SP ++#ifdef CONF_USBD_HS_SP + struct usbd_descriptors *hs; + #endif + }; diff --git a/atmel-samd/asf4/patches/samd51/assert_redefined.patch b/atmel-samd/asf4/patches/samd51/assert_redefined.patch new file mode 100644 index 0000000000..58a2e62079 --- /dev/null +++ b/atmel-samd/asf4/patches/samd51/assert_redefined.patch @@ -0,0 +1,20 @@ +--- samd51_vanilla/hal/utils/include/utils_assert.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/hal/utils/include/utils_assert.h 2017-09-19 13:07:30.000000000 -0700 +@@ -72,7 +72,7 @@ + if (!(condition)) \ + __asm("BKPT #0"); + #else +-#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) ++#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line) + #endif + + #else /* DEBUG */ +@@ -95,7 +95,7 @@ + * \param[in] file File name + * \param[in] line Line number + */ +-void assert(const bool condition, const char *const file, const int line); ++void asf_assert(const bool condition, const char *const file, const int line); + + #ifdef __cplusplus + } diff --git a/atmel-samd/asf4/patches/samd51/cast-align.patch b/atmel-samd/asf4/patches/samd51/cast-align.patch new file mode 100644 index 0000000000..1418c9fb1e --- /dev/null +++ b/atmel-samd/asf4/patches/samd51/cast-align.patch @@ -0,0 +1,12 @@ +--- samd51_vanilla/hal/src/hal_timer.c 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/hal/src/hal_timer.c 2017-09-19 13:07:30.000000000 -0700 +@@ -236,7 +236,10 @@ + */ + static void timer_process_counted(struct _timer_device *device) + { ++ #pragma GCC diagnostic push ++ #pragma GCC diagnostic ignored "-Wcast-align" + struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); ++ #pragma GCC diagnostic pop + struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); + uint32_t time = ++timer->time; diff --git a/atmel-samd/asf4/patches/samd51/little_endian_redefined.patch b/atmel-samd/asf4/patches/samd51/little_endian_redefined.patch new file mode 100644 index 0000000000..0fb55caeab --- /dev/null +++ b/atmel-samd/asf4/patches/samd51/little_endian_redefined.patch @@ -0,0 +1,99 @@ +--- samd51_vanilla/include/samd51g18a.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/include/samd51g18a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -511,7 +512,7 @@ + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM4_REV 1 /*!< Core revision r0p1 */ + #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ +--- samd51_vanilla/include/samd51g19a.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/include/samd51g19a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -511,7 +512,7 @@ + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM4_REV 1 /*!< Core revision r0p1 */ + #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ +--- samd51_vanilla/include/samd51j18a.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/include/samd51j18a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -529,7 +530,7 @@ + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM4_REV 1 /*!< Core revision r0p1 */ + #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ +--- samd51_vanilla/include/samd51j19a.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/include/samd51j19a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -529,7 +530,7 @@ + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM4_REV 1 /*!< Core revision r0p1 */ + #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ +--- samd51_vanilla/include/samd51j20a.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/include/samd51j20a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -529,7 +530,7 @@ + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM4_REV 1 /*!< Core revision r0p1 */ + #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ +--- samd51_vanilla/include/samd51n19a.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/include/samd51n19a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -551,7 +552,7 @@ + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM4_REV 1 /*!< Core revision r0p1 */ + #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ +--- samd51_vanilla/include/samd51n20a.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/include/samd51n20a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -551,7 +552,7 @@ + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM4_REV 1 /*!< Core revision r0p1 */ + #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ +--- samd51_vanilla/include/samd51p19a.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/include/samd51p19a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -551,7 +552,7 @@ + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM4_REV 1 /*!< Core revision r0p1 */ + #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ +--- samd51_vanilla/include/samd51p20a.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/include/samd51p20a.h 2017-09-19 13:07:30.000000000 -0700 +@@ -551,7 +552,7 @@ + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +-#define LITTLE_ENDIAN 1 ++//#define LITTLE_ENDIAN 1 + #define __CM4_REV 1 /*!< Core revision r0p1 */ + #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ diff --git a/atmel-samd/asf4/patches/samd51/make_usb_cache_accessible.patch b/atmel-samd/asf4/patches/samd51/make_usb_cache_accessible.patch new file mode 100644 index 0000000000..f287c7c010 --- /dev/null +++ b/atmel-samd/asf4/patches/samd51/make_usb_cache_accessible.patch @@ -0,0 +1,19 @@ +--- samd51_vanilla/hpl/usb/hpl_usb.c 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/hpl/usb/hpl_usb.c 2017-09-19 13:07:30.000000000 -0700 +@@ -299,14 +299,14 @@ + /** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ + #if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1 +-static uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; ++uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; + #else + #define _usb_ep1_cache NULL + #endif + + /** Endpoint cache buffer for IN transactions (none-control). */ + #if CONF_USB_EP1_I_CACHE && CONF_USB_D_MAX_EP_N >= 1 +-static uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4]; ++uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4]; + #else + #define _usb_ep1_i_cache NULL + #endif diff --git a/atmel-samd/asf4/patches/samd51/mark_used_no_c.patch b/atmel-samd/asf4/patches/samd51/mark_used_no_c.patch new file mode 100644 index 0000000000..3380db976f --- /dev/null +++ b/atmel-samd/asf4/patches/samd51/mark_used_no_c.patch @@ -0,0 +1,20 @@ +--- samd51_vanilla/gcc/gcc/startup_samd51.c 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/gcc/gcc/startup_samd51.c 2017-09-19 13:07:30.000000000 -0700 +@@ -314,7 +315,7 @@ + #endif + + /* Exception Table */ +-__attribute__((section(".vectors"))) const DeviceVectors exception_table ++__attribute__((section(".vectors"), used)) const DeviceVectors exception_table + = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ +@@ -660,7 +661,7 @@ + #endif + + /* Initialize the C library */ +- __libc_init_array(); ++ //__libc_init_array(); + + /* Branch to main function */ + main(); diff --git a/atmel-samd/asf4/patches/samd51/usb_undefined.patch b/atmel-samd/asf4/patches/samd51/usb_undefined.patch new file mode 100644 index 0000000000..0ca9182ca5 --- /dev/null +++ b/atmel-samd/asf4/patches/samd51/usb_undefined.patch @@ -0,0 +1,22 @@ +--- samd51_vanilla/usb/device/usbdc.c 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/usb/device/usbdc.c 2017-09-19 13:07:30.000000000 -0700 +@@ -739,7 +741,7 @@ + */ + int32_t usbdc_check_desces(struct usbdc_descriptors *desces) + { +-#if CONF_USBD_HS_SP ++#ifdef CONF_USBD_HS_SP + int32_t rc; + if (desces->hs == NULL && desces->ls_fs == NULL) { + return ERR_NOT_FOUND; +--- samd51_vanilla/usb/device/usbdc.h 2017-09-20 22:33:52.000000000 -0700 ++++ samd51/usb/device/usbdc.h 2017-09-19 13:07:30.000000000 -0700 +@@ -105,7 +105,7 @@ + /** Describes the USB device core descriptors. */ + struct usbdc_descriptors { + struct usbd_descriptors *ls_fs; +-#if CONF_USBD_HS_SP ++#ifdef CONF_USBD_HS_SP + struct usbd_descriptors *hs; + #endif + }; diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h index 842be65ed3..ab045fee8a 100644 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h +++ b/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h @@ -523,7 +523,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - return (op1 >> op2) | (op1 << (32 - op2)); + return (op1 >> op2) | (op1 << (32 - op2)); } diff --git a/atmel-samd/asf4/samd21/armcc/Makefile b/atmel-samd/asf4/samd21/armcc/Makefile index fe17feaff2..5c51dc09bf 100644 --- a/atmel-samd/asf4/samd21/armcc/Makefile +++ b/atmel-samd/asf4/samd21/armcc/Makefile @@ -48,7 +48,8 @@ hpl/dac \ samd21a/armcc/Device/SAMD21/Source \ hpl/sercom \ hpl/nvmctrl \ -hpl/core +hpl/core \ +usb/class/msc/device # List the object files OBJS += \ @@ -58,6 +59,7 @@ usb/usb_protocol.o \ usb/class/hid/device/hiddf_generic.o \ usb/class/cdc/device/cdcdf_acm.o \ hpl/nvmctrl/hpl_nvmctrl.o \ +usb/class/msc/device/mscdf.o \ hal/src/hal_spi_m_sync.o \ hal/src/hal_timer.o \ hal/src/hal_pwm.o \ @@ -105,6 +107,7 @@ OBJS_AS_ARGS += \ "usb/class/hid/device/hiddf_generic.o" \ "usb/class/cdc/device/cdcdf_acm.o" \ "hpl/nvmctrl/hpl_nvmctrl.o" \ +"usb/class/msc/device/mscdf.o" \ "hal/src/hal_spi_m_sync.o" \ "hal/src/hal_timer.o" \ "hal/src/hal_pwm.o" \ @@ -160,6 +163,7 @@ DEPS_AS_ARGS += \ "hal/src/hal_i2c_m_sync.d" \ "hpl/usb/hpl_usb.d" \ "samd21a/armcc/Device/SAMD21/Source/system_samd21.d" \ +"usb/class/msc/device/mscdf.d" \ "hpl/nvmctrl/hpl_nvmctrl.d" \ "hal/src/hal_pwm.d" \ "hal/src/hal_timer.d" \ @@ -229,7 +233,7 @@ $(OBJS_AS_ARGS) @echo Building file: $< @echo ARMCC Compiler $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD21G18A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ --depend "$@" -o "$@" "$<" @echo Finished building: $< @@ -238,7 +242,7 @@ $(OBJS_AS_ARGS) @echo Building file: $< @echo ARMCC Assembler $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M0+ --pd "D__SAMD21G18A__ SETA 1" \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ --depend "$(@:%.o=%.d)" -o "$@" "$<" @echo Finished building: $< @@ -247,7 +251,7 @@ $(OBJS_AS_ARGS) @echo Building file: $< @echo ARMCC Preprocessing Assembler $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD21G18A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ --depend "$@" -o "$@" "$<" @echo Finished building: $< diff --git a/atmel-samd/asf4/samd21/driver_init.c b/atmel-samd/asf4/samd21/driver_init.c index 806b89415e..5ee0d0ef76 100644 --- a/atmel-samd/asf4/samd21/driver_init.c +++ b/atmel-samd/asf4/samd21/driver_init.c @@ -619,32 +619,32 @@ void system_init(void) // GPIO on PA30 // Set pin direction to input - // gpio_set_pin_direction(PA30, GPIO_DIRECTION_IN); - // - // gpio_set_pin_pull_mode(PA30, - // // Pull configuration - // // pad_pull_config - // // Off - // // Pull-up - // // Pull-down - // GPIO_PULL_OFF); - // - // gpio_set_pin_function(PA30, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(PA30, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA30, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA30, GPIO_PIN_FUNCTION_OFF); // GPIO on PA31 // Set pin direction to input - // gpio_set_pin_direction(PA31, GPIO_DIRECTION_IN); - // - // gpio_set_pin_pull_mode(PA31, - // // Pull configuration - // // pad_pull_config - // // Off - // // Pull-up - // // Pull-down - // GPIO_PULL_OFF); - // - // gpio_set_pin_function(PA31, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(PA31, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA31, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA31, GPIO_PIN_FUNCTION_OFF); // GPIO on PB02 diff --git a/atmel-samd/asf4/samd21/gcc/Makefile b/atmel-samd/asf4/samd21/gcc/Makefile index 8e31a0231a..85b5aee2db 100644 --- a/atmel-samd/asf4/samd21/gcc/Makefile +++ b/atmel-samd/asf4/samd21/gcc/Makefile @@ -48,7 +48,8 @@ hpl/dac \ samd21a/gcc \ hpl/sercom \ hpl/nvmctrl \ -hpl/core +hpl/core \ +usb/class/msc/device # List the object files OBJS += \ @@ -60,6 +61,7 @@ usb/class/hid/device/hiddf_generic.o \ usb/class/cdc/device/cdcdf_acm.o \ hal/utils/src/utils_syscalls.o \ hpl/nvmctrl/hpl_nvmctrl.o \ +usb/class/msc/device/mscdf.o \ hal/src/hal_spi_m_sync.o \ hal/src/hal_timer.o \ hal/src/hal_pwm.o \ @@ -108,6 +110,7 @@ OBJS_AS_ARGS += \ "usb/class/cdc/device/cdcdf_acm.o" \ "hal/utils/src/utils_syscalls.o" \ "hpl/nvmctrl/hpl_nvmctrl.o" \ +"usb/class/msc/device/mscdf.o" \ "hal/src/hal_spi_m_sync.o" \ "hal/src/hal_timer.o" \ "hal/src/hal_pwm.o" \ @@ -162,6 +165,7 @@ DEPS_AS_ARGS += \ "usb/class/hid/device/hiddf_mouse.d" \ "hal/src/hal_i2c_m_sync.d" \ "hpl/usb/hpl_usb.d" \ +"usb/class/msc/device/mscdf.d" \ "hpl/nvmctrl/hpl_nvmctrl.d" \ "hal/src/hal_pwm.d" \ "hal/src/hal_timer.d" \ @@ -241,7 +245,7 @@ $(OUTPUT_FILE_PATH): $(OBJS) @echo ARM/GNU C Compiler $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ -D__SAMD21G18A__ -mcpu=cortex-m0plus \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" @echo Finished building: $< @@ -250,7 +254,7 @@ $(OUTPUT_FILE_PATH): $(OBJS) @echo ARM/GNU Assembler $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ -D__SAMD21G18A__ -mcpu=cortex-m0plus \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" @echo Finished building: $< @@ -259,7 +263,7 @@ $(OUTPUT_FILE_PATH): $(OBJS) @echo ARM/GNU Preprocessing Assembler $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ -D__SAMD21G18A__ -mcpu=cortex-m0plus \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" @echo Finished building: $< diff --git a/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c b/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c index ddc0580d72..67c95dfe50 100644 --- a/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c +++ b/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c @@ -49,8 +49,8 @@ void __libc_init_array(void); void Dummy_Handler(void); /* Cortex-M0+ core handlers */ -void NMI_Handler(void) __attribute__((weak, alias("Guilty_Handler"))); -void HardFault_Handler(void) __attribute__((weak, alias("Guilty_Handler"))); +void NMI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); void SVC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); @@ -64,7 +64,7 @@ void EIC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); void NVMCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); void DMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); #ifdef ID_USB -void USB_Handler(void) __attribute__((weak, alias("Guilty_Handler"))); +void USB_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); #endif void EVSYS_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); void SERCOM0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); @@ -234,7 +234,7 @@ void Reset_Handler(void) NVMCTRL->CTRLB.bit.MANW = 1; /* Initialize the C library */ - // __libc_init_array(); + //__libc_init_array(); /* Branch to main function */ main(); @@ -247,19 +247,8 @@ void Reset_Handler(void) /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void Dummy_Handler(void) +void Dummy_Handler(void) { while (1) { - asm(""); - } -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Guilty_Handler(void) -{ - while (1) { - asm(""); } } diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h index fe55e60158..dc40a47f8b 100644 --- a/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h +++ b/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h @@ -3,7 +3,7 @@ * * \brief DAC related functionality declaration. * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. * * \asf_license_start * diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h index 49a7222bf4..a70b3ba649 100644 --- a/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h +++ b/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h @@ -3,7 +3,7 @@ * * \brief DAC related functionality declaration. * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. * * \asf_license_start * diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_reset.h b/atmel-samd/asf4/samd21/hal/include/hpl_reset.h index 868591ee68..7cb48aff0a 100644 --- a/atmel-samd/asf4/samd21/hal/include/hpl_reset.h +++ b/atmel-samd/asf4/samd21/hal/include/hpl_reset.h @@ -67,13 +67,12 @@ extern "C" { * The list of possible reset reasons. */ enum reset_reason { - RESET_REASON_POR = 1, - RESET_REASON_BOD12 = 2, - RESET_REASON_BOD33 = 4, - RESET_REASON_EXT = 8, - RESET_REASON_WDT = 16, - RESET_REASON_SYST = 32, - RESET_REASON_BACKUP = 64 + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64, }; /** diff --git a/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c index c72fe2758a..7fa26ac7fe 100644 --- a/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c +++ b/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c @@ -65,7 +65,11 @@ static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uin ret = _i2c_m_sync_transfer(&i2c->device, &msg); - return (((int32_t)n) > i2c->device.service.msg.len) ? (((int32_t)n) - i2c->device.service.msg.len) : ret; + if (ret) { + return ret; + } + + return n; } /** @@ -84,7 +88,11 @@ static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, co ret = _i2c_m_sync_transfer(&i2c->device, &msg); - return (((int32_t)n) > i2c->device.service.msg.len) ? (((int32_t)n) - i2c->device.service.msg.len) : ret; + if (ret) { + return ret; + } + + return n; } /** diff --git a/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c b/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c index f0efd9ff50..08ad12a305 100644 --- a/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c +++ b/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c @@ -460,7 +460,7 @@ int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer) case USB_EP_S_ERROR: return -USB_ERROR; case USB_EP_S_DISABLED: - return -USB_ERR_FUNC + 1; + return -USB_ERR_FUNC; default: /* USB_EP_S_X_xxxx */ return USB_BUSY; } @@ -546,7 +546,7 @@ static inline int32_t _usb_d_ep_halt_clr(const uint8_t ep) if (ep_index < 0) { return -USB_ERR_PARAM; } - if (ept->xfer.hdr.state == USB_EP_S_HALTED) { + if (_usb_d_dev_ep_stall(ep, USB_EP_STALL_GET)) { rc = _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); if (rc < 0) { return rc; diff --git a/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c b/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c index baec8a2b4c..e9898b1d98 100644 --- a/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c +++ b/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c @@ -2130,8 +2130,8 @@ static int32_t _spi_sync_enable(void *const hw) static int32_t _spi_async_enable(void *const hw) { _spi_sync_enable(hw); - NVIC_EnableIRQ(_sercom_get_irq_num(hw)); - NVIC_EnableIRQ(_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); return ERR_NONE; } @@ -2163,7 +2163,7 @@ static int32_t _spi_async_disable(void *const hw) _spi_sync_disable(hw); hri_sercomspi_clear_INTEN_reg( hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); - NVIC_DisableIRQ(_sercom_get_irq_num(hw)); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); return ERR_NONE; } @@ -2384,16 +2384,16 @@ int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) { - NVIC_DisableIRQ(_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ(_sercom_get_irq_num(dev->prvt)); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); return _spi_deinit(dev->prvt); } int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) { - NVIC_DisableIRQ(_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ(_sercom_get_irq_num(dev->prvt)); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); return _spi_deinit(dev->prvt); } diff --git a/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c b/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c index 6a9cd6627b..d134967d3c 100644 --- a/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c +++ b/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c @@ -1262,7 +1262,7 @@ static void _usb_d_dev_handle_stall(struct _usb_d_dev_ep *ept, const uint8_t ban uint8_t epn = USB_EP_GET_N(ept->ep); /* Clear interrupt enable. Leave status there for status check. */ _usbd_ep_int_stall_en(epn, bank_n, false); - _usb_d_dev_trans_done(ept, USB_TRANS_STALL); + dev_inst.ep_callbacks.done(ept->ep, USB_TRANS_STALL, ept->trans_count); } /** @@ -1402,7 +1402,7 @@ static inline void _usb_d_dev_handle_eps(uint32_t epint, struct _usb_d_dev_ep *e mask = hw->DEVICE.DeviceEndpoint[epn].EPINTENSET.reg; flags &= mask; if (flags) { - if (!_usb_d_dev_ep_is_busy(ept)) { + if ((ept->flags.bits.eptype == 0x1) && !_usb_d_dev_ep_is_busy(ept)) { _usb_d_dev_trans_setup_isr(ept, flags); } else if (_usb_d_dev_ep_is_in(ept)) { _usb_d_dev_trans_in_isr(ept, flags); diff --git a/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_flash.ld b/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_flash.ld deleted file mode 100644 index 2c94a53baf..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_flash.ld +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21G18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_sram.ld b/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_sram.ld deleted file mode 100644 index f0462a22da..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_sram.ld +++ /dev/null @@ -1,141 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21G18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/atmel-samd/asf4/samd21/samd21a/gcc/gcc/startup_samd21.c b/atmel-samd/asf4/samd21/samd21a/gcc/gcc/startup_samd21.c deleted file mode 100644 index b159549c83..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/gcc/gcc/startup_samd21.c +++ /dev/null @@ -1,254 +0,0 @@ -/** - * \file - * - * \brief gcc starttup file for SAMD21 - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "samd21.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -void NMI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SVC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SYSCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void EIC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void NVMCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void DMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_USB -void USB_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void EVSYS_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_SERCOM4 -void SERCOM4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_SERCOM5 -void SERCOM5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void TCC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TCC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TCC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_TC6 -void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC7 -void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_ADC -void ADC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_AC -void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_DAC -void DAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_PTC -void PTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__((section(".vectors"))) const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void *)(&_estack), - - .pfnReset_Handler = (void *)Reset_Handler, - .pfnNMI_Handler = (void *)NMI_Handler, - .pfnHardFault_Handler = (void *)HardFault_Handler, - .pvReservedM12 = (void *)(0UL), /* Reserved */ - .pvReservedM11 = (void *)(0UL), /* Reserved */ - .pvReservedM10 = (void *)(0UL), /* Reserved */ - .pvReservedM9 = (void *)(0UL), /* Reserved */ - .pvReservedM8 = (void *)(0UL), /* Reserved */ - .pvReservedM7 = (void *)(0UL), /* Reserved */ - .pvReservedM6 = (void *)(0UL), /* Reserved */ - .pfnSVC_Handler = (void *)SVC_Handler, - .pvReservedM4 = (void *)(0UL), /* Reserved */ - .pvReservedM3 = (void *)(0UL), /* Reserved */ - .pfnPendSV_Handler = (void *)PendSV_Handler, - .pfnSysTick_Handler = (void *)SysTick_Handler, - - /* Configurable interrupts */ - .pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */ - .pfnSYSCTRL_Handler = (void *)SYSCTRL_Handler, /* 1 System Control */ - .pfnWDT_Handler = (void *)WDT_Handler, /* 2 Watchdog Timer */ - .pfnRTC_Handler = (void *)RTC_Handler, /* 3 Real-Time Counter */ - .pfnEIC_Handler = (void *)EIC_Handler, /* 4 External Interrupt Controller */ - .pfnNVMCTRL_Handler = (void *)NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - .pfnDMAC_Handler = (void *)DMAC_Handler, /* 6 Direct Memory Access Controller */ -#ifdef ID_USB - .pfnUSB_Handler = (void *)USB_Handler, /* 7 Universal Serial Bus */ -#else - .pvReserved7 = (void *)(0UL), /* 7 Reserved */ -#endif - .pfnEVSYS_Handler = (void *)EVSYS_Handler, /* 8 Event System Interface */ - .pfnSERCOM0_Handler = (void *)SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - .pfnSERCOM1_Handler = (void *)SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - .pfnSERCOM2_Handler = (void *)SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - .pfnSERCOM3_Handler = (void *)SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ -#ifdef ID_SERCOM4 - .pfnSERCOM4_Handler = (void *)SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ -#else - .pvReserved13 = (void *)(0UL), /* 13 Reserved */ -#endif -#ifdef ID_SERCOM5 - .pfnSERCOM5_Handler = (void *)SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ -#else - .pvReserved14 = (void *)(0UL), /* 14 Reserved */ -#endif - .pfnTCC0_Handler = (void *)TCC0_Handler, /* 15 Timer Counter Control 0 */ - .pfnTCC1_Handler = (void *)TCC1_Handler, /* 16 Timer Counter Control 1 */ - .pfnTCC2_Handler = (void *)TCC2_Handler, /* 17 Timer Counter Control 2 */ - .pfnTC3_Handler = (void *)TC3_Handler, /* 18 Basic Timer Counter 0 */ - .pfnTC4_Handler = (void *)TC4_Handler, /* 19 Basic Timer Counter 1 */ - .pfnTC5_Handler = (void *)TC5_Handler, /* 20 Basic Timer Counter 2 */ -#ifdef ID_TC6 - .pfnTC6_Handler = (void *)TC6_Handler, /* 21 Basic Timer Counter 3 */ -#else - .pvReserved21 = (void *)(0UL), /* 21 Reserved */ -#endif -#ifdef ID_TC7 - .pfnTC7_Handler = (void *)TC7_Handler, /* 22 Basic Timer Counter 4 */ -#else - .pvReserved22 = (void *)(0UL), /* 22 Reserved */ -#endif -#ifdef ID_ADC - .pfnADC_Handler = (void *)ADC_Handler, /* 23 Analog Digital Converter */ -#else - .pvReserved23 = (void *)(0UL), /* 23 Reserved */ -#endif -#ifdef ID_AC - .pfnAC_Handler = (void *)AC_Handler, /* 24 Analog Comparators */ -#else - .pvReserved24 = (void *)(0UL), /* 24 Reserved */ -#endif -#ifdef ID_DAC - .pfnDAC_Handler = (void *)DAC_Handler, /* 25 Digital Analog Converter */ -#else - .pvReserved25 = (void *)(0UL), /* 25 Reserved */ -#endif -#ifdef ID_PTC - .pfnPTC_Handler = (void *)PTC_Handler, /* 26 Peripheral Touch Controller */ -#else - .pvReserved26 = (void *)(0UL), /* 26 Reserved */ -#endif - .pfnI2S_Handler = (void *)I2S_Handler, /* 27 Inter-IC Sound Interface */ - .pvReserved28 = (void *)(0UL) /* 28 Reserved */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *)&_sfixed; - SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Change default QOS values to have the best performance and correct USB behaviour */ - SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; -#if defined(ID_USB) - USB->DEVICE.QOSCTRL.bit.CQOS = 2; - USB->DEVICE.QOSCTRL.bit.DQOS = 2; -#endif - DMAC->QOSCTRL.bit.DQOS = 2; - DMAC->QOSCTRL.bit.FQOS = 2; - DMAC->QOSCTRL.bit.WRBQOS = 2; - - /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ - NVMCTRL->CTRLB.bit.MANW = 1; - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1) - ; -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/atmel-samd/asf4/samd21/samd21a/gcc/system_samd21.c b/atmel-samd/asf4/samd21/samd21a/gcc/system_samd21.c deleted file mode 100644 index 274ecccb83..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/gcc/system_samd21.c +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "samd21.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (1000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/atmel-samd/asf4/samd21/samd21a/include/component-version.h b/atmel-samd/asf4/samd21/samd21a/include/component-version.h deleted file mode 100644 index dcf909bae2..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/component-version.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * \brief Component version header file - * - * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 2 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION -// is at least 8 digits long. -// -#define COMPONENT_VERSION 00010002 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 276 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "1.2" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2017-02-07 19:08:26" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - diff --git a/atmel-samd/asf4/samd21/samd21a/include/component/ac.h b/atmel-samd/asf4/samd21/samd21a/include/component/ac.h deleted file mode 100644 index 80ea1abe1f..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/component/ac.h +++ /dev/null @@ -1,544 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_AC_COMPONENT_ -#define _SAMD21_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_AC Analog Comparators */ -/*@{*/ - -#define AC_U2205 -#define REV_AC 0x111 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE _U(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (_U(0x1) << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (_U(0x1) << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ -#define AC_CTRLA_RUNSTDBY_Msk (_U(0x1) << AC_CTRLA_RUNSTDBY_Pos) -#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) -#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ -#define AC_CTRLA_LPMUX (_U(0x1) << AC_CTRLA_LPMUX_Pos) -#define AC_CTRLA_MASK _U(0x87) /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE _U(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U(0x3) << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK _U(0x03) /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE _U(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U(0x3) << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U(0x1) << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ -#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ -#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ -#define AC_EVCTRL_COMPEI_Msk (_U(0x3) << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_MASK _U(0x0313) /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U(0x3) << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U(0x1) << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK _U(0x13) /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE _U(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U(0x3) << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U(0x1) << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK _U(0x13) /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U(0x3) << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (_U(0x1) << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK _U(0x13) /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE _U(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U(0x3) << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (_U(0x3) << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK _U(0x33) /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE _U(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U(0x3) << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ -#define AC_STATUSB_SYNCBUSY (_U(0x1) << AC_STATUSB_SYNCBUSY_Pos) -#define AC_STATUSB_MASK _U(0x83) /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ -#define AC_STATUSC_RESETVALUE _U(0x00) /**< \brief (AC_STATUSC reset_value) Status C */ - -#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ -#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos) -#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ -#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos) -#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ -#define AC_STATUSC_STATE_Msk (_U(0x3) << AC_STATUSC_STATE_Pos) -#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) -#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ -#define AC_STATUSC_WSTATE0_Msk (_U(0x3) << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) -#define AC_STATUSC_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSC) Signal is above window */ -#define AC_STATUSC_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSC) Signal is inside window */ -#define AC_STATUSC_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSC) Signal is below window */ -#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_MASK _U(0x33) /**< \brief (AC_STATUSC) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (_U(0x1) << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (_U(0x3) << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK _U(0x07) /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ENABLE:1; /*!< bit: 0 Enable */ - uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ - uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 14 Reserved */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t OUT:2; /*!< bit: 16..17 Output */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE _U(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (_U(0x1) << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (_U(0x1) << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (_U(0x3) << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_LOW_Val _U(0x0) /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val _U(0x1) /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (_U(0x3) << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (_U(0x7) << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U(0x4) /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U(0x7) /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (_U(0x3) << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (_U(0x1) << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (_U(0x3) << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYST (_U(0x1) << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (_U(0x7) << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_MASK _U(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE _U(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (_U(0x3F) << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK _U(0x3F) /**< \brief (AC_SCALER) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ - __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ - RoReg8 Reserved2[0x1]; - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ - RoReg8 Reserved3[0x3]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved4[0x8]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/component/adc.h b/atmel-samd/asf4/samd21/samd21a/include/component/adc.h deleted file mode 100644 index fe41521250..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/component/adc.h +++ /dev/null @@ -1,684 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_ADC_COMPONENT_ -#define _SAMD21_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2204 -#define REV_ADC 0x120 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE _U(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (_U(0x1) << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (_U(0x1) << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (_U(0x1) << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_MASK _U(0x07) /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (_U(0xF) << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INT1V_Val _U(0x0) /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U(0x1) /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U(0x3) /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U(0x4) /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (_U(0x1) << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK _U(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (_U(0x7) << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK _U(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ -#define ADC_SAMPCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_MASK _U(0x3F) /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE _U(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ -#define ADC_CTRLB_DIFFMODE (_U(0x1) << ADC_CTRLB_DIFFMODE_Pos) -#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (_U(0x1) << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (_U(0x1) << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ -#define ADC_CTRLB_CORREN (_U(0x1) << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (_U(0x3) << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val _U(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val _U(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val _U(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val _U(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (_U(0x7) << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) -#define ADC_CTRLB_PRESCALER_DIV4_Val _U(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val _U(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val _U(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val _U(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val _U(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val _U(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val _U(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV512_Val _U(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK _U(0x073F) /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ -#define ADC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ - -#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ -#define ADC_WINCTRL_WINMODE_Msk (_U(0x7) << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)) -#define ADC_WINCTRL_WINMODE_DISABLE_Val _U(0x0) /**< \brief (ADC_WINCTRL) No window mode (default) */ -#define ADC_WINCTRL_WINMODE_MODE1_Val _U(0x1) /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ -#define ADC_WINCTRL_WINMODE_MODE2_Val _U(0x2) /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE3_Val _U(0x3) /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE4_Val _U(0x4) /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ -#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_MASK _U(0x07) /**< \brief (ADC_WINCTRL) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE _U(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (_U(0x1) << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ -#define ADC_SWTRIG_START (_U(0x1) << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK _U(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ - uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ - uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE _U(0x00000000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN8_Val _U(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN9_Val _U(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN10_Val _U(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN11_Val _U(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN12_Val _U(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN13_Val _U(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN14_Val _U(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN15_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN16_Val _U(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN17_Val _U(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN18_Val _U(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN19_Val _U(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Reference */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U(0x1C) /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_IOGND_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) I/O Ground */ -#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ -#define ADC_INPUTCTRL_INPUTSCAN_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos) -#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)) -#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ -#define ADC_INPUTCTRL_INPUTOFFSET_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos) -#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)) -#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ -#define ADC_INPUTCTRL_GAIN_Msk (_U(0xF) << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)) -#define ADC_INPUTCTRL_GAIN_1X_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) 1x */ -#define ADC_INPUTCTRL_GAIN_2X_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) 2x */ -#define ADC_INPUTCTRL_GAIN_4X_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) 4x */ -#define ADC_INPUTCTRL_GAIN_8X_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) 8x */ -#define ADC_INPUTCTRL_GAIN_16X_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) 16x */ -#define ADC_INPUTCTRL_GAIN_DIV2_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) 1/2x */ -#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_MASK _U(0x0FFF1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ - uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ -#define ADC_EVCTRL_STARTEI (_U(0x1) << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ -#define ADC_EVCTRL_SYNCEI (_U(0x1) << ADC_EVCTRL_SYNCEI_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (_U(0x1) << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (_U(0x1) << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK _U(0x33) /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ -#define ADC_INTENCLR_RESRDY (_U(0x1) << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ -#define ADC_INTENCLR_OVERRUN (_U(0x1) << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ -#define ADC_INTENCLR_WINMON (_U(0x1) << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define ADC_INTENCLR_SYNCRDY (_U(0x1) << ADC_INTENCLR_SYNCRDY_Pos) -#define ADC_INTENCLR_MASK _U(0x0F) /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE _U(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (_U(0x1) << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (_U(0x1) << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (_U(0x1) << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ -#define ADC_INTENSET_SYNCRDY (_U(0x1) << ADC_INTENSET_SYNCRDY_Pos) -#define ADC_INTENSET_MASK _U(0x0F) /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ - __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ -#define ADC_INTFLAG_RESRDY (_U(0x1) << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ -#define ADC_INTFLAG_OVERRUN (_U(0x1) << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ -#define ADC_INTFLAG_WINMON (_U(0x1) << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ -#define ADC_INTFLAG_SYNCRDY (_U(0x1) << ADC_INTFLAG_SYNCRDY_Pos) -#define ADC_INTFLAG_MASK _U(0x0F) /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE _U(0x00) /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ -#define ADC_STATUS_SYNCBUSY (_U(0x1) << ADC_STATUS_SYNCBUSY_Pos) -#define ADC_STATUS_MASK _U(0x80) /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE _U(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (_U(0xFFFF) << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK _U(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (_U(0xFFFF) << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK _U(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (_U(0xFFFF) << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK _U(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (_U(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK _U(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK _U(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ - uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE _U(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ -#define ADC_CALIB_LINEARITY_CAL_Msk (_U(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos) -#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)) -#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ -#define ADC_CALIB_BIAS_CAL_Msk (_U(0x7) << ADC_CALIB_BIAS_CAL_Pos) -#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)) -#define ADC_CALIB_MASK _U(0x07FF) /**< \brief (ADC_CALIB) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (_U(0x1) << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK _U(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ - RoReg8 Reserved1[0x2]; - __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ - RoReg8 Reserved2[0x3]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ - RoReg8 Reserved3[0x3]; - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ - RoReg8 Reserved4[0x1]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ - RoReg8 Reserved5[0x2]; - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ - RoReg8 Reserved6[0x2]; - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/component/dac.h b/atmel-samd/asf4/samd21/samd21a/include/component/dac.h deleted file mode 100644 index ba84975eaf..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/component/dac.h +++ /dev/null @@ -1,271 +0,0 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_DAC_COMPONENT_ -#define _SAMD21_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DAC Digital Analog Converter */ -/*@{*/ - -#define DAC_U2214 -#define REV_DAC 0x110 - -/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (_U(0x1) << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ -#define DAC_CTRLA_ENABLE (_U(0x1) << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ -#define DAC_CTRLA_RUNSTDBY (_U(0x1) << DAC_CTRLA_RUNSTDBY_Pos) -#define DAC_CTRLA_MASK _U(0x07) /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ - uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ - uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ - uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ - uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ -#define DAC_CTRLB_EOEN (_U(0x1) << DAC_CTRLB_EOEN_Pos) -#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ -#define DAC_CTRLB_IOEN (_U(0x1) << DAC_CTRLB_IOEN_Pos) -#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ -#define DAC_CTRLB_LEFTADJ (_U(0x1) << DAC_CTRLB_LEFTADJ_Pos) -#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ -#define DAC_CTRLB_VPD (_U(0x1) << DAC_CTRLB_VPD_Pos) -#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ -#define DAC_CTRLB_BDWP (_U(0x1) << DAC_CTRLB_BDWP_Pos) -#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ -#define DAC_CTRLB_REFSEL_Msk (_U(0x3) << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_INT1V_Val _U(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */ -#define DAC_CTRLB_REFSEL_AVCC_Val _U(0x1) /**< \brief (DAC_CTRLB) AVCC */ -#define DAC_CTRLB_REFSEL_VREFP_Val _U(0x2) /**< \brief (DAC_CTRLB) External reference */ -#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK _U(0xDF) /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ - uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ -#define DAC_EVCTRL_STARTEI (_U(0x1) << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ -#define DAC_EVCTRL_EMPTYEO (_U(0x1) << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_MASK _U(0x03) /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN (_U(0x1) << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY (_U(0x1) << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define DAC_INTENCLR_SYNCRDY (_U(0x1) << DAC_INTENCLR_SYNCRDY_Pos) -#define DAC_INTENCLR_MASK _U(0x07) /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE _U(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN (_U(0x1) << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY (_U(0x1) << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ -#define DAC_INTENSET_SYNCRDY (_U(0x1) << DAC_INTENSET_SYNCRDY_Pos) -#define DAC_INTENSET_MASK _U(0x07) /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ - __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ - __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ -#define DAC_INTFLAG_UNDERRUN (_U(0x1) << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ -#define DAC_INTFLAG_EMPTY (_U(0x1) << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ -#define DAC_INTFLAG_SYNCRDY (_U(0x1) << DAC_INTFLAG_SYNCRDY_Pos) -#define DAC_INTFLAG_MASK _U(0x07) /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE _U(0x00) /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ -#define DAC_STATUS_SYNCBUSY (_U(0x1) << DAC_STATUS_SYNCBUSY_Pos) -#define DAC_STATUS_MASK _U(0x80) /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ -#define DAC_DATA_RESETVALUE _U(0x0000) /**< \brief (DAC_DATA reset_value) Data */ - -#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ -#define DAC_DATA_DATA_Msk (_U(0xFFFF) << DAC_DATA_DATA_Pos) -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_MASK _U(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ - -/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATABUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ -#define DAC_DATABUF_RESETVALUE _U(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */ - -#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (_U(0xFFFF) << DAC_DATABUF_DATABUF_Pos) -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_MASK _U(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ - -/** \brief DAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ - RoReg8 Reserved2[0x2]; - __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ -} Dac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/component/dmac.h b/atmel-samd/asf4/samd21/samd21a/include/component/dmac.h deleted file mode 100644 index 1d7c8c0eae..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/component/dmac.h +++ /dev/null @@ -1,1072 +0,0 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_DMAC_COMPONENT_ -#define _SAMD21_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2223 -#define REV_DMAC 0x100 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (_U(0x1) << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (_U(0x1) << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ -#define DMAC_CTRL_CRCENABLE (_U(0x1) << DMAC_CTRL_CRCENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (_U(0xF) << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK _U(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (_U(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (_U(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) No action */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_MASK _U(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (_U(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (_U(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_MASK _U(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (_U(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK _U(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_QOSCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ -#define DMAC_QOSCTRL_RESETVALUE _U(0x15) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ - -#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ -#define DMAC_QOSCTRL_WRBQOS_Msk (_U(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) -#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ -#define DMAC_QOSCTRL_FQOS_Msk (_U(0x3) << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) -#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_FQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_FQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ -#define DMAC_QOSCTRL_DQOS_Msk (_U(0x3) << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) -#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_DQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_DQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_MASK _U(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE _U(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK _U(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK _U(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE _U(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (_U(0xF) << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (_U(0x1) << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (_U(0x1) << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (_U(0x1) << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (_U(0x1) << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (_U(0x1) << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (_U(0x1) << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK _U(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE _U(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (_U(0xFFF) << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK _U(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (_U(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK _U(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (_U(0xFFF) << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK _U(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE _U(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (_U(0xF) << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (_U(0x1F) << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (_U(0x1) << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (_U(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK _U(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (_U(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (_U(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ -#define DMAC_CHID_RESETVALUE _U(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ - -#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ -#define DMAC_CHID_ID_Msk (_U(0xF) << DMAC_CHID_ID_Pos) -#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) -#define DMAC_CHID_MASK _U(0x0F) /**< \brief (DMAC_CHID) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ -#define DMAC_CHCTRLA_RESETVALUE _U(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (_U(0x1) << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (_U(0x1) << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_MASK _U(0x03) /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ -#define DMAC_CHCTRLB_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ - -#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ -#define DMAC_CHCTRLB_EVACT_Msk (_U(0x7) << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) -#define DMAC_CHCTRLB_EVACT_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_EVACT_TRIG_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ -#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_EVACT_RESUME_Val _U(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ -#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ -#define DMAC_CHCTRLB_EVIE (_U(0x1) << DMAC_CHCTRLB_EVIE_Pos) -#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ -#define DMAC_CHCTRLB_EVOE (_U(0x1) << DMAC_CHCTRLB_EVOE_Pos) -#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ -#define DMAC_CHCTRLB_LVL_Msk (_U(0x3) << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) -#define DMAC_CHCTRLB_LVL_LVL0_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ -#define DMAC_CHCTRLB_LVL_LVL1_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ -#define DMAC_CHCTRLB_LVL_LVL2_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ -#define DMAC_CHCTRLB_LVL_LVL3_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ -#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ -#define DMAC_CHCTRLB_TRIGSRC_Msk (_U(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) -#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ -#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ -#define DMAC_CHCTRLB_TRIGACT_Msk (_U(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) -#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ -#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ -#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (_U(0x3) << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK _U(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (_U(0x1) << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (_U(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (_U(0x1) << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK _U(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (_U(0x1) << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (_U(0x1) << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (_U(0x1) << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK _U(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (_U(0x1) << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (_U(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (_U(0x1) << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK _U(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ -#define DMAC_CHSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (_U(0x1) << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (_U(0x1) << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (_U(0x1) << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_MASK _U(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (_U(0x1) << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U(0x3) << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ -#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (_U(0x1) << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (_U(0x1) << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (_U(0x1) << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030D) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21e16a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21e16a.h deleted file mode 100644 index 7bb07c660b..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21e16a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16A_ -#define _SAMD21E16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions - * This file defines all structures and symbols for SAMD21E16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030C) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21e17a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21e17a.h deleted file mode 100644 index df037351ac..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21e17a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E17A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E17A_ -#define _SAMD21E17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions - * This file defines all structures and symbols for SAMD21E17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030B) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E17A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21e18a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21e18a.h deleted file mode 100644 index 8e7bcb7f48..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21e18a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E18A_ -#define _SAMD21E18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions - * This file defines all structures and symbols for SAMD21E18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030A) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E18A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g15a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g15a.h deleted file mode 100644 index 5131ac4c92..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21g15a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G15A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15A_ -#define _SAMD21G15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions - * This file defines all structures and symbols for SAMD21G15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010308) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G15A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g16a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g16a.h deleted file mode 100644 index 102128025a..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21g16a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G16A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16A_ -#define _SAMD21G16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions - * This file defines all structures and symbols for SAMD21G16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010307) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G16A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g17a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g17a.h deleted file mode 100644 index dc3b161284..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21g17a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G17A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G17A_ -#define _SAMD21G17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions - * This file defines all structures and symbols for SAMD21G17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010306) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g17au.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g17au.h deleted file mode 100644 index 46225b3bfd..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21g17au.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G17AU - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G17AU_ -#define _SAMD21G17AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions - * This file defines all structures and symbols for SAMD21G17AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g17au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010310) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17AU_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g18a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g18a.h deleted file mode 100644 index 2840b6e14b..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21g18a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G18A_ -#define _SAMD21G18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions - * This file defines all structures and symbols for SAMD21G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010305) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g18au.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g18au.h deleted file mode 100644 index 82c2532b60..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21g18au.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G18AU - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G18AU_ -#define _SAMD21G18AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions - * This file defines all structures and symbols for SAMD21G18AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g18au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030F) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18AU_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21j15a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21j15a.h deleted file mode 100644 index 80aba23ec0..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21j15a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J15A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J15A_ -#define _SAMD21J15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions - * This file defines all structures and symbols for SAMD21J15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010303) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J15A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21j16a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21j16a.h deleted file mode 100644 index b054d7ed86..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21j16a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J16A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J16A_ -#define _SAMD21J16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions - * This file defines all structures and symbols for SAMD21J16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010302) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J16A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21j17a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21j17a.h deleted file mode 100644 index bc85d9304e..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21j17a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J17A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J17A_ -#define _SAMD21J17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions - * This file defines all structures and symbols for SAMD21J17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010301) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J17A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21j18a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21j18a.h deleted file mode 100644 index ee9a8fa1e6..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/samd21j18a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J18A_ -#define _SAMD21J18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions - * This file defines all structures and symbols for SAMD21J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010300) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J18A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/system_samd21.h b/atmel-samd/asf4/samd21/samd21a/include/system_samd21.h deleted file mode 100644 index 223911ce69..0000000000 --- a/atmel-samd/asf4/samd21/samd21a/include/system_samd21.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SYSTEM_SAMD21_H_INCLUDED_ -#define _SYSTEM_SAMD21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAMD21_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h b/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h index 6017864cb2..5213bd843a 100644 --- a/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h +++ b/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h @@ -3,7 +3,7 @@ * * \brief USB Communication Device Class (CDC) protocol definitions * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * Copyright (c) 2015 - 2017 Atmel Corporation. All rights reserved. * * \asf_license_start * @@ -275,8 +275,8 @@ enum cdc_parity { CDC_PAR_NONE = 0, //!< No parity CDC_PAR_ODD = 1, //!< Odd parity CDC_PAR_EVEN = 2, //!< Even parity - CDC_PAR_MARK = 3, //!< Parity forced to 0 (space) - CDC_PAR_SPACE = 4 //!< Parity forced to 1 (mark) + CDC_PAR_MARK = 3, //!< Parity forced to 1 (mark) + CDC_PAR_SPACE = 4 //!< Parity forced to 0 (space) }; //@} @@ -404,4 +404,33 @@ COMPILER_PACK_RESET() //! @} +/** + * \brief Fill a CDC SetLineCoding request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_SetLineCoding_req(struct usb_req *req, uint8_t iface) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_CDC_SET_LINE_CODING; + req->wValue = 0; + req->wIndex = iface; + req->wLength = sizeof(usb_cdc_line_coding_t); +} + +/** + * \brief Fill a CDC SetControlLineState request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + * \param[in] ctrl Control Signal Bitmap + */ +static inline void usb_fill_SetControlLineState_req(struct usb_req *req, uint8_t iface, uint16_t ctrl) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_CDC_SET_CONTROL_LINE_STATE; + req->wValue = ctrl; + req->wIndex = iface; + req->wLength = 0; +} + #endif // _USB_PROTOCOL_CDC_H_ diff --git a/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h b/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h index 68db57af99..9838e40c18 100644 --- a/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h +++ b/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h @@ -3,7 +3,7 @@ * * \brief USB Device Stack Composite Class Descriptor Setting. * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. * * \page License * @@ -127,12 +127,29 @@ #define CONF_HID_GENERIC_IFC_DESC #endif +#if CONF_USB_COMPOSITE_MSC_EN == 1 +#define CONF_MSC_IFC_LEN 23 /* (9 + 7 * 2) */ +#define CONF_MSC_IFC_NUM 1 +#define CONF_USB_COMPOSITE_MSC_BIFCNUM (CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM + 1) +#define CONF_MSC_IFC_DESC \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BIFCNUM, 0x00, 0x02, 0x08, 0x06, 0x50, 0x00) \ + , USB_ENDP_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR, 0x02, CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ, 0), \ + USB_ENDP_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR, 0x02, CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ, 0), +#else +#define CONF_MSC_IFC_LEN 0 +#define CONF_MSC_IFC_NUM 0 +#define CONF_USB_COMPOSITE_MSC_BIFCNUM CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM +#define CONF_MSC_IFC_DESC +#endif + #define CONF_USB_COMPOSITE_TOTAL_LEN \ (USB_CONFIG_DESC_LEN + CONF_CDC_ACM_IFC_LEN + CONF_HID_MOUSE_IFC_LEN + CONF_HID_KEYBOARD_IFC_LEN \ - + CONF_HID_GENERIC_IFC_LEN) + + CONF_HID_GENERIC_IFC_LEN \ + + CONF_MSC_IFC_LEN) #define CONF_USB_COMPOSITE_IFC_NUM \ - (CONF_CDC_ACM_IFC_NUM + CONF_HID_MOUSE_IFC_NUM + CONF_HID_KEYBOARD_IFC_NUM + CONF_HID_GENERIC_IFC_NUM) + (CONF_CDC_ACM_IFC_NUM + CONF_HID_MOUSE_IFC_NUM + CONF_HID_KEYBOARD_IFC_NUM + CONF_HID_GENERIC_IFC_NUM \ + + CONF_MSC_IFC_NUM) #define COMPOSITE_DEV_DESC \ USB_DEV_DESC_BYTES(CONF_USB_COMPOSITE_BCDUSB, \ @@ -160,7 +177,8 @@ CONF_CDC_ACM_IFC_DESC \ CONF_HID_MOUSE_IFC_DESC \ CONF_HID_KEYBOARD_IFC_DESC \ - CONF_HID_GENERIC_IFC_DESC + CONF_HID_GENERIC_IFC_DESC \ + CONF_MSC_IFC_DESC /** USB Device descriptors and configuration descriptors */ #define COMPOSITE_DESCES_LS_FS \ diff --git a/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h b/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h index 1b29802b03..08f43b3799 100644 --- a/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h +++ b/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h @@ -19,6 +19,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_bmaxpksz0 #ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 #define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 @@ -128,6 +129,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_cdc_acm_epaddr #ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR #define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 @@ -138,6 +142,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_cdc_acm_comm_int_maxpksz #ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ #define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 @@ -151,6 +156,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_cdc_acm_data_bulkin_epaddr #ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR #define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 @@ -161,6 +169,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_cdc_acm_data_builin_maxpksz #ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ #define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 @@ -174,6 +183,9 @@ // <0x05=> EndpointAddress = 0x05 // <0x06=> EndpointAddress = 0x06 // <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + // usb_composite_cdc_acm_data_bulkout_epaddr #ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR #define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 @@ -184,10 +196,21 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_cdc_acm_data_buckout_maxpksz #ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ #define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 #endif + +// CDC ACM Echo Demo generation +// conf_usb_composite_cdc_echo_demo +// Invoke cdcdf_acm_demo_init(buf[wMaxPacketSize]) to enable the echo demo. +// Buf is packet buffer for data receive and echo back. +// The buffer is 4 byte aligned to support DMA. +#ifndef CONF_USB_COMPOSITE_CDC_ECHO_DEMO +#define CONF_USB_COMPOSITE_CDC_ECHO_DEMO 0 +#endif + // // HID Mouse Support @@ -204,6 +227,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_hid_mouse_intin_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR @@ -215,12 +241,21 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_hid_mouse_intin_maxpksz // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ #define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 #endif +// HID Mouse Move Demo generation +// conf_usb_composite_hid_mouse_demo +// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// Button1 and button3 are the pins used for mouse moving left and right. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_DEMO +#define CONF_USB_COMPOSITE_HID_MOUSE_DEMO 0 +#endif + // // HID Keyboard Support @@ -237,6 +272,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_hid_keyboard_intin_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR @@ -248,6 +286,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_hid_keyboard_intin_maxpksz // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ @@ -262,6 +301,9 @@ // <0x05=> EndpointAddress = 0x05 // <0x06=> EndpointAddress = 0x06 // <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + // usb_composite_hid_keyboard_intout_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR @@ -273,12 +315,21 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_hid_keyboard_intout_maxpksz // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ #define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 #endif +// HID Keyboard Caps Lock Demo generation +// conf_usb_composite_hid_keyboard_demo +// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// Buffon2 is the pin used for keyboard CAPS LOCK simulation. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO +#define CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO 0 +#endif + // // HID Generic Support @@ -306,6 +357,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_hid_generic_intin_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR @@ -317,6 +371,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_hid_generic_intin_maxpksz // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ @@ -331,6 +386,9 @@ // <0x05=> EndpointAddress = 0x05 // <0x06=> EndpointAddress = 0x06 // <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + // usb_composite_hid_generic_intout_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR @@ -350,6 +408,196 @@ // +// MSC Support +// usb_composite_msc_support +#ifndef CONF_USB_COMPOSITE_MSC_EN +#define CONF_USB_COMPOSITE_MSC_EN 0 +#endif + +// MSC BULK Endpoints wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_msc_bulk_maxpksz +#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ +#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ 0x0040 +#endif + +// MSC BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_msc_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR 0x86 +#endif + +// MSC BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_msc_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR 0x04 +#endif + +// Enable Demo code for Disk LUN handling +// usb_composite_msc_demo_en +#ifndef CONF_USB_COMPOSITE_MSC_LUN_DEMO +#define CONF_USB_COMPOSITE_MSC_LUN_DEMO 1 +#endif + +// Disk access cache/buffer of sectors if non-RAM disk enabled <1-64> +// conf_usb_msc_lun_buf_sectors +#ifndef CONF_USB_MSC_LUN_BUF_SECTORS +#define CONF_USB_MSC_LUN_BUF_SECTORS 4 +#endif + +// Enable Demo for RAM Disk +// conf_usb_msc_lun0_enable +#ifndef CONF_USB_MSC_LUN0_ENABLE +#define CONF_USB_MSC_LUN0_ENABLE 1 +#endif + +#ifndef CONF_USB_MSC_LUN0_TYPE +#define CONF_USB_MSC_LUN0_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun0_rmb +#ifndef CONF_USB_MSC_LUN0_RMB +#define CONF_USB_MSC_LUN0_RMB 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN0_ISO +#define CONF_USB_MSC_LUN0_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ECMA +#define CONF_USB_MSC_LUN0_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ANSI +#define CONF_USB_MSC_LUN0_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_REPO +#define CONF_USB_MSC_LUN0_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN0_FACTORY +#define CONF_USB_MSC_LUN0_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT +#define CONF_USB_MSC_LUN0_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT_VERSION +#define CONF_USB_MSC_LUN0_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <1-65535> +// Windows will not show disk less than 20K, so 22K is used to reserve more RAM for app +// conf_usb_msc_lun0_capacity + +#ifndef CONF_USB_MSC_LUN0_CAPACITY +#define CONF_USB_MSC_LUN0_CAPACITY 0x16 +#endif + +#ifndef CONF_USB_MSC_LUN0_BLOCK_SIZE +#define CONF_USB_MSC_LUN0_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for SD/MMC Disk +// SD/MMC stack must be added before enable SD/MMC demo +// SD/MMC insert/eject not supported by this simple demo +// conf_usb_msc_lun1_enable +#ifndef CONF_USB_MSC_LUN1_ENABLE +#define CONF_USB_MSC_LUN1_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN1_TYPE +#define CONF_USB_MSC_LUN1_TYPE 0x00 +#endif + +// The disk is removable +// SD/MMC stack must be added before enable SD/MMC demo +// SD/MMC insert/eject not supported by this simple demo +// conf_usb_msc_lun1_rmb +#ifndef CONF_USB_MSC_LUN1_RMB +#define CONF_USB_MSC_LUN1_RMB 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN1_ISO +#define CONF_USB_MSC_LUN1_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ECMA +#define CONF_USB_MSC_LUN1_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ANSI +#define CONF_USB_MSC_LUN1_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_REPO +#define CONF_USB_MSC_LUN1_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN1_FACTORY +#define CONF_USB_MSC_LUN1_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT +#define CONF_USB_MSC_LUN1_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT_VERSION +#define CONF_USB_MSC_LUN1_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_CAPACITY +#define CONF_USB_MSC_LUN1_CAPACITY 0x16 +#endif + +#ifndef CONF_USB_MSC_LUN1_BLOCK_SIZE +#define CONF_USB_MSC_LUN1_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) +#endif + +// + +// +// + // <<< end of configuration section >>> #endif // USBD_COMPOSITE_CONFIG_H diff --git a/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.c b/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.c new file mode 100644 index 0000000000..b398ba6090 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.c @@ -0,0 +1,754 @@ +/** + * \file + * + * \brief USB Device Stack MSC Function Implementation. + * + * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "mscdf.h" +#include + +#define MSCDF_VERSION 0x00000001u + +#define ERR_RPT_ZLP 0 /* Uses ZLP on IN error case */ + +/** MSC Class Transfer Stage Type */ +enum mscdf_xfer_stage_type { MSCDF_CMD_STAGE, MSCDF_DATA_STAGE, MSCDF_STATUS_STAGE }; + +/** USB Device MSC Function Specific Data */ +struct mscdf_func_data { + /** MSC Device Interface information */ + uint8_t func_iface; + /** MSC Device IN Endpoint */ + uint8_t func_ep_in; + /** MSC Device OUT Endpoint */ + uint8_t func_ep_out; + /** MSC Device Max LUN */ + uint8_t func_max_lun; + /** MSC Transfer Block Address */ + uint8_t *xfer_blk_addr; + /** MSC Transfer Block Size */ + uint32_t xfer_blk_size; + /** MSC Transfer Total Bytes */ + uint32_t xfer_tot_bytes; + /** MSC Transfer Stage */ + enum mscdf_xfer_stage_type xfer_stage; + /** MSC Transfer Busy Flag */ + bool xfer_busy; + /** MSC Device Enable Flag */ + bool enabled; +}; + +static struct usbdf_driver _mscdf; +static struct mscdf_func_data _mscdf_funcd; + +/* If callbacks are not registered: + * - Return default inquiry information + * - Return NOT FOUND for all other CBW + */ +static mscdf_inquiry_disk_t mscdf_inquiry_disk = NULL; +static mscdf_get_disk_capacity_t mscdf_get_disk_capacity = NULL; +static mscdf_eject_disk_t mscdf_eject_disk = NULL; +static mscdf_start_read_disk_t mscdf_read_disk = NULL; +static mscdf_start_write_disk_t mscdf_write_disk = NULL; +static mscdf_test_disk_ready_t mscdf_test_disk_ready = NULL; +static mscdf_xfer_blocks_done_t mscdf_xfer_blocks_done = NULL; + +COMPILER_ALIGNED(4) +static struct scsi_inquiry_data _inquiry_default = { + 0x00, /* Peripheral Qual / Peripheral Dev Type */ + SCSI_INQ_RMB, /* Flags 1 */ + 0x00, /* Version */ + 0x01, /* Flags 3 */ + 31, /* Additional Length (n-4) */ + 0x00, /* Flags 5 */ + 0x00, /* Flags 6 */ + 0x00, /* Flags 7 */ + {0, 0, 0, 0, 0, 0, 0, 0}, /* VID[8] */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* PID[16] */ + {0, 0, 0, 0} /* PREV[4] */ +}; + +COMPILER_ALIGNED(4) +static struct usb_msc_cbw mscdf_cbw; + +COMPILER_ALIGNED(4) +static struct usb_msc_csw mscdf_csw = {USB_CSW_SIGNATURE, 0, 0, 0}; + +COMPILER_ALIGNED(4) +static struct scsi_request_sense_data mscdf_sense_data + = {SCSI_SENSE_CURRENT, 0x00, 0x00, {0x00, 0x00, 0x00, 0x00}, 0x0A}; + +/** + * \brief USB MSC wait Command Block + */ +static bool mscdf_wait_cbw(void) +{ + _mscdf_funcd.xfer_stage = MSCDF_CMD_STAGE; + return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_out, (uint8_t *)&mscdf_cbw, 31, false); +} + +/** + * \brief USB MSC Send Command Status + */ +static bool mscdf_send_csw(void) +{ + _mscdf_funcd.xfer_stage = MSCDF_STATUS_STAGE; + return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_in, (uint8_t *)&mscdf_csw, sizeof(struct usb_msc_csw), false); +} + +#if ERR_RPT_ZLP +/** + * \brief USB MSC Send ZLP data + */ +static bool mscdf_send_zlp(void) +{ + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_in, (uint8_t *)&mscdf_csw, 0, true); +} +#define mscdf_terminate_in() mscdf_send_zlp() +#else +/** + * \brief USB MSC Halt IN endpoint + */ +static bool mscdf_halt_in(void) +{ + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + return ERR_NONE == usb_d_ep_halt(_mscdf_funcd.func_ep_in, USB_EP_HALT_SET); +} +#define mscdf_terminate_in() mscdf_halt_in() +#endif + +/** + * \brief USB MSC Request Sense + * \param[in] err_codes Error code + */ +static void mscdf_request_sense(int32_t err_codes) +{ + switch (err_codes) { + case ERR_NOT_FOUND: + mscdf_sense_data.sense_flag_key = SCSI_SK_NOT_READY; + mscdf_sense_data.AddSense = BE16(SCSI_ASC_MEDIUM_NOT_PRESENT); + break; + + case ERR_BUSY: + mscdf_sense_data.sense_flag_key = SCSI_SK_UNIT_ATTENTION; + mscdf_sense_data.AddSense = BE16(SCSI_ASC_NOT_READY_TO_READY_CHANGE); + break; + + case ERR_DENIED: + mscdf_sense_data.sense_flag_key = SCSI_SK_DATA_PROTECT; + mscdf_sense_data.AddSense = BE16(SCSI_ASC_WRITE_PROTECTED); + break; + + default: + mscdf_sense_data.sense_flag_key = SCSI_SK_ILLEGAL_REQUEST; + mscdf_sense_data.AddSense = BE16(SCSI_ASC_INVALID_COMMAND_OPERATION_CODE); + break; + } +} + +/** + * \brief USB MSC Stack invalid command process + */ +static bool mscdf_invalid_cmd(void) +{ + struct usb_msc_cbw *pcbw = &mscdf_cbw; + struct usb_msc_csw *pcsw = &mscdf_csw; + + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + + mscdf_request_sense(ERR_UNSUPPORTED_OP); + + if ((pcbw->bmCBWFlags & USB_EP_DIR_IN) && pcsw->dCSWDataResidue) { + return mscdf_terminate_in(); + } else { + return mscdf_send_csw(); + } +} + +/** + * \brief USB MSC Function Read / Write Data + * \param[in] count the amount of bytes has been transferred + * \return Operation status. + */ +static bool mscdf_read_write(uint32_t count) +{ + struct usb_msc_cbw *pcbw = &mscdf_cbw; + struct usb_msc_csw *pcsw = &mscdf_csw; + int32_t ret = ERR_UNSUPPORTED_OP; + uint32_t address, nblocks; + uint8_t ep; + + if (_mscdf_funcd.xfer_stage == MSCDF_CMD_STAGE) { + address = (uint32_t)(pcbw->CDB[2] << 24) + (uint32_t)(pcbw->CDB[3] << 16) + (uint32_t)(pcbw->CDB[4] << 8) + + pcbw->CDB[5]; + nblocks = (uint32_t)(pcbw->CDB[7] << 8) + pcbw->CDB[8]; + if (pcbw->CDB[0] == SBC_READ10) { + if (NULL != mscdf_read_disk) { + ret = mscdf_read_disk(pcbw->bCBWLUN, address, nblocks); + } else { + ret = ERR_NOT_FOUND; + } + } else if (pcbw->CDB[0] == SBC_WRITE10) { + if (NULL != mscdf_write_disk) { + ret = mscdf_write_disk(pcbw->bCBWLUN, address, nblocks); + } else { + ret = ERR_NOT_FOUND; + } + } + if (ERR_NONE == ret) { + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + return false; + } + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ret); + return mscdf_terminate_in(); + + } else if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { + if (count == 0) { + return mscdf_send_csw(); + } + if (pcsw->dCSWDataResidue < count || _mscdf_funcd.xfer_tot_bytes < count) { + return true; + } + + pcsw->dCSWDataResidue -= count; + _mscdf_funcd.xfer_tot_bytes -= count; + + if (_mscdf_funcd.xfer_tot_bytes == 0) { + _mscdf_funcd.xfer_busy = false; + if (NULL != mscdf_xfer_blocks_done) { + mscdf_xfer_blocks_done(pcbw->bCBWLUN); + } + if (pcsw->dCSWDataResidue == 0 && pcbw->CDB[0] == SBC_READ10) { + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + return mscdf_send_csw(); + } else { + return false; + } + } else { + _mscdf_funcd.xfer_blk_addr += count; + if (pcbw->CDB[0] == SBC_READ10) { + ep = _mscdf_funcd.func_ep_in; + } else { + ep = _mscdf_funcd.func_ep_out; + } + return usbdc_xfer(ep, _mscdf_funcd.xfer_blk_addr, _mscdf_funcd.xfer_tot_bytes, false); + } + } else { + return true; + } +} + +/** + * \brief Callback invoked when bulk IN data received + * \param[in] ep Endpoint number + * \param[in] rc transfer return status + * \param[in] count the amount of bytes has been transferred + * \return Operation status. + */ +static bool mscdf_cb_ep_bulk_in(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) +{ + struct usb_msc_cbw *pcbw = &mscdf_cbw; + (void)ep; + (void)rc; + + if (rc == USB_XFER_UNHALT) { + if (_mscdf_funcd.xfer_stage != MSCDF_CMD_STAGE) { + return mscdf_send_csw(); + } + } + + if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { + if (pcbw->CDB[0] == SBC_READ10) { + return mscdf_read_write(count); + } else { + return mscdf_send_csw(); + } + } else if (_mscdf_funcd.xfer_stage == MSCDF_STATUS_STAGE) { + return mscdf_wait_cbw(); + } else { + return true; + } +} + +/** + * \brief Callback invoked when bulk OUT data received + * \param[in] ep Endpoint number + * \param[in] rc transfer return status + * \param[in] count the amount of bytes has been transferred + * \return Operation status. + */ +static bool mscdf_cb_ep_bulk_out(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) +{ + struct usb_msc_cbw *pcbw = &mscdf_cbw; + struct usb_msc_csw *pcsw = &mscdf_csw; + uint8_t * pbuf = NULL; + int32_t ret; + + (void)ep; + if (rc == USB_XFER_UNHALT) { + return mscdf_wait_cbw(); + } + + if (_mscdf_funcd.xfer_stage == MSCDF_CMD_STAGE) { + if (pcbw->dCBWSignature == USB_CBW_SIGNATURE) { + pcsw->dCSWTag = pcbw->dCBWTag; + pcsw->dCSWDataResidue = pcbw->dCBWDataTransferLength; + + switch (pcbw->CDB[0]) { + case SPC_INQUIRY: + if (NULL != mscdf_inquiry_disk) { + pbuf = mscdf_inquiry_disk(pcbw->bCBWLUN); + } + if (NULL == pbuf) { + pbuf = (uint8_t *)&_inquiry_default; + } + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + return usbdc_xfer(_mscdf_funcd.func_ep_in, pbuf, 36, false); + + case SBC_READ_CAPACITY10: + if (NULL != mscdf_get_disk_capacity) { + pbuf = mscdf_get_disk_capacity(pcbw->bCBWLUN); + } + if (NULL != pbuf) { + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + _mscdf_funcd.xfer_blk_size + = (uint32_t)(pbuf[4] << 24) + (uint32_t)(pbuf[5] << 16) + (uint32_t)(pbuf[6] << 8) + pbuf[7]; + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + return usbdc_xfer(_mscdf_funcd.func_ep_in, pbuf, 8, false); + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ERR_NOT_FOUND); + return mscdf_terminate_in(); + } + + case SBC_READ10: + case SBC_WRITE10: + return mscdf_read_write(count); + + case SPC_PREVENT_ALLOW_MEDIUM_REMOVAL: + if (0x00 == pcbw->CDB[4]) { + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + return mscdf_send_csw(); + } + break; + + case SBC_START_STOP_UNIT: + if (0x02 == pcbw->CDB[4]) { + if (NULL != mscdf_eject_disk) { + ret = mscdf_eject_disk(pcbw->bCBWLUN); + if (ERR_NONE == ret) { + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ret); + } + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ERR_NOT_FOUND); + } + return mscdf_send_csw(); + } + break; + + case SPC_REQUEST_SENSE: + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + return usbdc_xfer(_mscdf_funcd.func_ep_in, + (uint8_t *)&mscdf_sense_data, + sizeof(struct scsi_request_sense_data), + false); + + case SPC_TEST_UNIT_READY: + if (NULL != mscdf_test_disk_ready) { + ret = mscdf_test_disk_ready(pcbw->bCBWLUN); + if (ERR_NONE == ret) { + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ret); + } + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ERR_NOT_FOUND); + } + return mscdf_send_csw(); + + default: + break; + } + return mscdf_invalid_cmd(); + } else { + return true; + } + } else if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { + return mscdf_read_write(count); + } else { + return true; + } +} + +/** + * \brief Enable MSC Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t mscdf_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct mscdf_func_data *func_data = (struct mscdf_func_data *)(drv->func_data); + + usb_ep_desc_t ep_desc; + usb_iface_desc_t ifc_desc; + uint8_t * ifc, *ep; + + ifc = desc->sod; + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if (MSC_CLASS == ifc_desc.bInterfaceClass) { + if (func_data->func_iface == ifc_desc.bInterfaceNumber) { /* Initialized */ + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface != 0xFF) { /* Occupied */ + return ERR_NO_RESOURCE; + } else { + func_data->func_iface = ifc_desc.bInterfaceNumber; + } + } else { /* Not supported by this function driver */ + return ERR_NOT_FOUND; + } + + /* Install endpoints */ + ep = usb_find_desc(ifc, desc->eod, USB_DT_ENDPOINT); + while (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in); + usb_d_ep_register_callback(func_data->func_ep_in, USB_D_EP_CB_XFER, (FUNC_PTR)mscdf_cb_ep_bulk_in); + } else { + func_data->func_ep_out = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_out); + usb_d_ep_register_callback(func_data->func_ep_out, USB_D_EP_CB_XFER, (FUNC_PTR)mscdf_cb_ep_bulk_out); + } + desc->sod = ep; + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + } + // Installed + _mscdf_funcd.enabled = true; + return mscdf_wait_cbw(); +} + +/** + * \brief Disable MSC Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t mscdf_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct mscdf_func_data *func_data = (struct mscdf_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + // Check interface + if (ifc_desc.bInterfaceClass != MSC_CLASS) { + return ERR_NOT_FOUND; + } + } + + if (func_data->func_iface != 0xFF) { + func_data->func_iface = 0xFF; + } + + if (func_data->func_ep_in != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in); + func_data->func_ep_in = 0xFF; + } + + if (func_data->func_ep_out != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_out); + func_data->func_ep_out = 0xFF; + } + + func_data->xfer_stage = MSCDF_CMD_STAGE; + func_data->xfer_busy = false; + func_data->enabled = false; + + return ERR_NONE; +} + +/** + * \brief MSC Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t mscdf_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return mscdf_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return mscdf_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the MSC class set request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t mscdf_set_req(uint8_t ep, struct usb_req *req) +{ + (void)ep; + switch (req->bRequest) { + case USB_REQ_MSC_BULK_RESET: + _mscdf_funcd.xfer_stage = MSCDF_CMD_STAGE; + usb_d_ep_halt(_mscdf_funcd.func_ep_in, USB_EP_HALT_SET); + usb_d_ep_halt(_mscdf_funcd.func_ep_out, USB_EP_HALT_SET); + return usbdc_xfer(0, NULL, 0, 0); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the MSC class get request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \param[in] stage USB control transfer stages. + * \return Operation status. + */ +static int32_t mscdf_get_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + uint16_t len = req->wLength; + + if (USB_DATA_STAGE == stage) { + return ERR_NONE; + } + + switch (req->bRequest) { + case USB_REQ_MSC_GET_MAX_LUN: + return usbdc_xfer(ep, &_mscdf_funcd.func_max_lun, len, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the MSC class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \param[in] stage USB control transfer stages. + * \return Operation status. + */ +static int32_t mscdf_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { /* class request */ + return ERR_NOT_FOUND; + } + if (req->wIndex == _mscdf_funcd.func_iface) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return mscdf_get_req(ep, req, stage); + } else { + return mscdf_set_req(ep, req); + } + } else { + return ERR_NOT_FOUND; + } +} + +/** USB Device MSC Handler Struct */ +static struct usbdc_handler mscdf_req_h = {NULL, (FUNC_PTR)mscdf_req}; + +/** + * \brief Initialize the USB MSC Function Driver + */ +int32_t mscdf_init(uint8_t max_lun) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _mscdf.ctrl = mscdf_ctrl; + _mscdf.func_data = &_mscdf_funcd; + _mscdf_funcd.func_max_lun = max_lun; + + usbdc_register_function(&_mscdf); + usbdc_register_handler(USBDC_HDL_REQ, &mscdf_req_h); + return ERR_NONE; +} + +/** + * \brief De-initialize the USB MSC Function Driver + */ +int32_t mscdf_deinit(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _mscdf.ctrl = NULL; + _mscdf.func_data = NULL; + + usbdc_unregister_function(&_mscdf); + usbdc_unregister_handler(USBDC_HDL_REQ, &mscdf_req_h); + return ERR_NONE; +} + +/** + * \brief USB MSC Function Register Callback + */ +int32_t mscdf_register_callback(enum mscdf_cb_type cb_type, FUNC_PTR func) +{ + switch (cb_type) { + case MSCDF_CB_INQUIRY_DISK: + mscdf_inquiry_disk = (mscdf_inquiry_disk_t)func; + break; + case MSCDF_CB_GET_DISK_CAPACITY: + mscdf_get_disk_capacity = (mscdf_get_disk_capacity_t)func; + break; + case MSCDF_CB_EJECT_DISK: + mscdf_eject_disk = (mscdf_eject_disk_t)func; + break; + case MSCDF_CB_START_READ_DISK: + mscdf_read_disk = (mscdf_start_read_disk_t)func; + break; + case MSCDF_CB_START_WRITE_DISK: + mscdf_write_disk = (mscdf_start_write_disk_t)func; + break; + case MSCDF_CB_TEST_DISK_READY: + mscdf_test_disk_ready = (mscdf_test_disk_ready_t)func; + break; + case MSCDF_CB_XFER_BLOCKS_DONE: + mscdf_xfer_blocks_done = (mscdf_xfer_blocks_done_t)func; + break; + default: + return ERR_INVALID_ARG; + } + return ERR_NONE; +} + +/** + * \brief Check whether MSC Function is enabled + */ +bool mscdf_is_enabled(void) +{ + return _mscdf_funcd.enabled; +} + +/** + * \brief Process the transfer between USB and Memory. + * + * Routine called by the main loop + */ +int32_t mscdf_xfer_blocks(bool rd, uint8_t *blk_addr, uint32_t blk_cnt) +{ + uint8_t ep; + + if (false == mscdf_is_enabled()) { + return ERR_DENIED; + } else if (true == _mscdf_funcd.xfer_busy) { + return ERR_BUSY; + } else { + _mscdf_funcd.xfer_blk_addr = blk_addr; + _mscdf_funcd.xfer_tot_bytes = _mscdf_funcd.xfer_blk_size * blk_cnt; + if (0 == _mscdf_funcd.xfer_tot_bytes) { + if (false == rd) { + /* For write command, this means no need for more data to receive. + * All the data have been written into disk. + */ + mscdf_csw.bCSWStatus = USB_CSW_STATUS_PASS; + return mscdf_send_csw(); + } else { + return ERR_INVALID_ARG; + } + } else { + if (NULL == blk_addr) { + return ERR_INVALID_ARG; + } + if (true == rd) { + ep = _mscdf_funcd.func_ep_in; + } else { + ep = _mscdf_funcd.func_ep_out; + } + _mscdf_funcd.xfer_busy = true; + usbdc_xfer(ep, blk_addr, _mscdf_funcd.xfer_tot_bytes, false); + return ERR_NONE; + } + } +} + +/** + * \brief Return version + */ +uint32_t mscdf_get_version(void) +{ + return MSCDF_VERSION; +} diff --git a/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.h b/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.h new file mode 100644 index 0000000000..5847a2604b --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief USB Device Stack MSC Function Definition. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_MSC_H_ +#define USBDF_MSC_H_ + +#include "usbdc.h" +#include "usb_protocol_msc.h" +#include "spc_protocol.h" +#include "sbc_protocol.h" + +/** MSC Class Callback Type */ +enum mscdf_cb_type { + MSCDF_CB_INQUIRY_DISK, + MSCDF_CB_GET_DISK_CAPACITY, + MSCDF_CB_START_READ_DISK, + MSCDF_CB_START_WRITE_DISK, + MSCDF_CB_EJECT_DISK, + MSCDF_CB_TEST_DISK_READY, + MSCDF_CB_XFER_BLOCKS_DONE +}; + +/** MSC Inquiry Disk Callback. */ +typedef uint8_t *(*mscdf_inquiry_disk_t)(uint8_t); + +/** MSC Get Disk Capacity Callback. */ +typedef uint8_t *(*mscdf_get_disk_capacity_t)(uint8_t); + +/** MSC Read Data From Disk Callback. */ +typedef int32_t (*mscdf_start_read_disk_t)(uint8_t, uint32_t, uint32_t); + +/** MSC Write Data To Disk Callback. */ +typedef int32_t (*mscdf_start_write_disk_t)(uint8_t, uint32_t, uint32_t); + +/** MSC Eject Disk Callback. */ +typedef int32_t (*mscdf_eject_disk_t)(uint8_t); + +/** MSC Test Disk Ready Callback. */ +typedef int32_t (*mscdf_test_disk_ready_t)(uint8_t); + +/** MSC Tansfer Block Done Callback. */ +typedef int32_t (*mscdf_xfer_blocks_done_t)(uint8_t); + +/** + * \brief Initialize the USB MSC Function Driver + * \param[in] max_lun max logic unit support + * \return Operation status. + */ +int32_t mscdf_init(uint8_t max_lun); + +/** + * \brief Deinitialize the USB MSC Function Driver + * \return Operation status. + */ +int32_t mscdf_deinit(void); + +/** + * \brief USB MSC Function Register Callback + * \param[in] cb_type Callback type of MSC Function + * \param[in] func Pointer to callback function + * \return Operation status. + */ +int32_t mscdf_register_callback(enum mscdf_cb_type cb_type, FUNC_PTR func); + +/** + * \brief Check whether MSC Function is enabled + * \return Operation status. + * \return true MSC Function is enabled + * \return false MSC Function is disabled + */ +bool mscdf_is_enabled(void); + +/** + * \brief USB MSC multi-blocks data transfer between USB and Memory. + * \param[in] rd true read disk command, false write disk command. + * \param[in] blk_addr transfer block address. + * \param[in] blk_cnt transfer block count. It is regarded as disk + * writing done when input blk_cnt as zero. + * \return Operation status. + */ +int32_t mscdf_xfer_blocks(bool rd, uint8_t *blk_addr, uint32_t blk_cnt); + +/** + * \brief Return version + */ +uint32_t mscdf_get_version(void); + +#endif /* USBDF_MSC_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/device/usbdc.c b/atmel-samd/asf4/samd21/usb/device/usbdc.c index f5243cad03..c9645541dc 100644 --- a/atmel-samd/asf4/samd21/usb/device/usbdc.c +++ b/atmel-samd/asf4/samd21/usb/device/usbdc.c @@ -262,6 +262,7 @@ static bool usbdc_clear_ftr_req(const uint8_t ep, const struct usb_req *req) return false; } usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_CLR); + usbdc_xfer(ep, NULL, 0, true); return true; default: return false; @@ -285,6 +286,7 @@ static bool usbdc_set_ftr_req(const uint8_t ep, const struct usb_req *req) return false; } usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_SET); + usbdc_xfer(ep, NULL, 0, true); return true; default: return false; diff --git a/atmel-samd/asf4/samd21/usb_start.c b/atmel-samd/asf4/samd21/usb_start.c index afd8f89b2b..683392806a 100644 --- a/atmel-samd/asf4/samd21/usb_start.c +++ b/atmel-samd/asf4/samd21/usb_start.c @@ -8,6 +8,8 @@ #include "atmel_start.h" #include "usb_start.h" +#define CONF_USB_MSC_MAX_LUN 0 + static uint8_t multi_desc_bytes[] = { /* Device descriptors and Configuration descriptors list. */ COMPOSITE_DESCES_LS_FS, @@ -18,33 +20,59 @@ static struct usbd_descriptors multi_desc = {multi_desc_bytes, multi_desc_bytes /** Ctrl endpoint buffer */ static uint8_t ctrl_buffer[64]; -/** - * \brief Composite Init - */ void composite_device_init(void) { /* usb stack init */ usbdc_init(ctrl_buffer); - /* usbdc_register_funcion inside */ +/* usbdc_register_funcion inside */ +#if CONF_USB_COMPOSITE_CDC_ACM_EN cdcdf_acm_init(); +#endif +#if CONF_USB_COMPOSITE_HID_MOUSE_EN + hiddf_mouse_init(); +#endif +#if CONF_USB_COMPOSITE_HID_KEYBOARD_EN + hiddf_keyboard_init(); +#endif +#if CONF_USB_COMPOSITE_MSC_EN + mscdf_init(CONF_USB_MSC_MAX_LUN); +#endif +} +void composite_device_start(void) +{ usbdc_start(&multi_desc); usbdc_attach(); } -/** - * Example of using Composite Function. - * \note - * In this example, we will use a PC as a USB host: - * - Connect the DEBUG USB on XPLAINED board to PC for program download. - * - Connect the TARGET USB on XPLAINED board to PC for running program. - */ void composite_device_example(void) { - while (!cdcdf_acm_is_enabled()) { - // wait cdc acm to be installed - }; + + /* Initialize */ + /* It's done with system init ... */ + + /* Before start do function related initializations */ + /* Add your code here ... */ + + /* Start device */ + composite_device_start(); + + /* Main loop */ + while (1) { + if (cdcdf_acm_is_enabled()) { + /* CDC ACM process*/ + } + if (hiddf_mouse_is_enabled()) { + /* HID Mouse process */ + } + if (hiddf_keyboard_is_enabled()) { + /* HID Keyboard process */ + }; + if (mscdf_is_enabled()) { + /* MSC process */ + } + } } void usb_init(void) diff --git a/atmel-samd/asf4/samd21/usb_start.h b/atmel-samd/asf4/samd21/usb_start.h index 9695f7ed78..912bf289c4 100644 --- a/atmel-samd/asf4/samd21/usb_start.h +++ b/atmel-samd/asf4/samd21/usb_start.h @@ -16,9 +16,24 @@ extern "C" { #include "hiddf_mouse.h" #include "hiddf_keyboard.h" #include "hiddf_generic.h" +#include "mscdf.h" #include "composite_desc.h" +/** + * \brief Initialize device and attach functions + */ void composite_device_init(void); +/** + * \brief Start the device + */ +void composite_device_start(void); +/** + * Example of using Composite Function. + * \note + * In this example, we will use a PC as a USB host: + * - Connect the DEBUG USB on XPLAINED board to PC for program download. + * - Connect the TARGET USB on XPLAINED board to PC for running program. + */ void composite_device_example(void); /** diff --git a/atmel-samd/asf4/samd51/armcc/Makefile b/atmel-samd/asf4/samd51/armcc/Makefile index e502d0314e..ff3779b499 100644 --- a/atmel-samd/asf4/samd51/armcc/Makefile +++ b/atmel-samd/asf4/samd51/armcc/Makefile @@ -50,17 +50,22 @@ usb/device \ hpl/pm \ hpl/dac \ hpl/sercom \ -hpl/core +hpl/nvmctrl \ +hpl/core \ +usb/class/msc/device # List the object files OBJS += \ hal/src/hal_io.o \ hpl/systick/hpl_systick.o \ +usb/usb_protocol.o \ usb/class/hid/device/hiddf_generic.o \ hpl/evsys/hpl_evsys.o \ hpl/core/hpl_core_m4.o \ usb/class/cdc/device/cdcdf_acm.o \ hpl/mclk/hpl_mclk.o \ +hpl/nvmctrl/hpl_nvmctrl.o \ +usb/class/msc/device/mscdf.o \ hal/src/hal_spi_m_sync.o \ hal/src/hal_timer.o \ hal/src/hal_pwm.o \ @@ -81,7 +86,7 @@ usb/class/hid/device/hiddf_keyboard.o \ hal/src/hal_usart_sync.o \ hpl/dac/hpl_dac.o \ hpl/gclk/hpl_gclk.o \ -usb/usb_protocol.o \ +hal/src/hal_flash.o \ hal/src/hal_init.o \ hal/src/hal_usb_device.o \ main.o \ @@ -106,11 +111,14 @@ hpl/adc/hpl_adc.o OBJS_AS_ARGS += \ "hal/src/hal_io.o" \ "hpl/systick/hpl_systick.o" \ +"usb/usb_protocol.o" \ "usb/class/hid/device/hiddf_generic.o" \ "hpl/evsys/hpl_evsys.o" \ "hpl/core/hpl_core_m4.o" \ "usb/class/cdc/device/cdcdf_acm.o" \ "hpl/mclk/hpl_mclk.o" \ +"hpl/nvmctrl/hpl_nvmctrl.o" \ +"usb/class/msc/device/mscdf.o" \ "hal/src/hal_spi_m_sync.o" \ "hal/src/hal_timer.o" \ "hal/src/hal_pwm.o" \ @@ -131,7 +139,7 @@ OBJS_AS_ARGS += \ "hal/src/hal_usart_sync.o" \ "hpl/dac/hpl_dac.o" \ "hpl/gclk/hpl_gclk.o" \ -"usb/usb_protocol.o" \ +"hal/src/hal_flash.o" \ "hal/src/hal_init.o" \ "hal/src/hal_usb_device.o" \ "main.o" \ @@ -157,6 +165,7 @@ OBJS_AS_ARGS += \ DEPS := $(OBJS:%.o=%.d) DEPS_AS_ARGS += \ +"usb/usb_protocol.d" \ "hal/utils/src/utils_event.d" \ "hal/src/hal_io.d" \ "hpl/ramecc/hpl_ramecc.d" \ @@ -167,6 +176,8 @@ DEPS_AS_ARGS += \ "hal/src/hal_i2c_m_sync.d" \ "hpl/usb/hpl_usb.d" \ "hal/src/hal_evsys.d" \ +"usb/class/msc/device/mscdf.d" \ +"hpl/nvmctrl/hpl_nvmctrl.d" \ "hal/src/hal_pwm.d" \ "hal/src/hal_timer.d" \ "hal/src/hal_spi_m_sync.d" \ @@ -178,7 +189,7 @@ DEPS_AS_ARGS += \ "hal/src/hal_delay.d" \ "hpl/core/hpl_init.d" \ "hpl/pm/hpl_pm.d" \ -"usb/usb_protocol.d" \ +"hal/src/hal_flash.d" \ "hpl/gclk/hpl_gclk.d" \ "hal/src/hal_usb_device.d" \ "usb_start.d" \ @@ -240,7 +251,7 @@ $(OBJS_AS_ARGS) @echo Building file: $< @echo ARMCC Compiler $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAMD51G19A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ --depend "$@" -o "$@" "$<" @echo Finished building: $< @@ -249,7 +260,7 @@ $(OBJS_AS_ARGS) @echo Building file: $< @echo ARMCC Assembler $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAMD51G19A__ SETA 1" \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ --depend "$(@:%.o=%.d)" -o "$@" "$<" @echo Finished building: $< @@ -258,7 +269,7 @@ $(OBJS_AS_ARGS) @echo Building file: $< @echo ARMCC Preprocessing Assembler $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAMD51G19A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ --depend "$@" -o "$@" "$<" @echo Finished building: $< diff --git a/atmel-samd/asf4/samd51/atmel_start_config.atstart b/atmel-samd/asf4/samd51/atmel_start_config.atstart index ba77962954..7a706ff04b 100644 --- a/atmel-samd/asf4/samd51/atmel_start_config.atstart +++ b/atmel-samd/asf4/samd51/atmel_start_config.atstart @@ -65,6 +65,15 @@ middlewares: USB_DEVICE_COMPOSITE_0: user_label: USB_DEVICE_COMPOSITE_0 configuration: + conf_usb_composite_cdc_echo_demo: false + conf_usb_composite_hid_keyboard_demo: false + conf_usb_composite_hid_mouse_demo: false + conf_usb_msc_lun0_capacity: 22 + conf_usb_msc_lun0_enable: true + conf_usb_msc_lun0_rmb: true + conf_usb_msc_lun1_enable: false + conf_usb_msc_lun1_rmb: true + conf_usb_msc_lun_buf_sectors: 4 usb_composite_bcddevice: 256 usb_composite_bcdusb: USB 2.0 version usb_composite_bconfigval: 1 @@ -98,6 +107,11 @@ middlewares: usb_composite_imanufact: 0 usb_composite_iproduct: 0 usb_composite_iserialnum: 0 + usb_composite_msc_bulk_maxpksz: 64 bytes + usb_composite_msc_bulkin_epaddr: EndpointAddress = 0x86 + usb_composite_msc_bulkout_epaddr: EndpointAddress = 0x04 + usb_composite_msc_demo_en: true + usb_composite_msc_support: false definition: Atmel:USB:0.0.1::USB_Device_Composite functionality: USB_Device_COMPOSITE api: USB:Device:COMPOSITE @@ -1264,6 +1278,19 @@ drivers: - name: CPU input: CPU configuration: {} + FLASH_0: + user_label: FLASH_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::NVMCTRL::driver_config_definition::Flash::HAL:Driver:FLASH + functionality: Flash + api: HAL:Driver:FLASH + configuration: + nvm_arch_cache0: false + nvm_arch_cache1: false + nvm_arch_sleepprm: Wake On Access + optional_signals: [] + variant: null + clocks: + domain_group: null OSC32KCTRL: user_label: OSC32KCTRL definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL @@ -1454,42 +1481,6 @@ drivers: configuration: core_gclk_selection: Generic clock generator 0 slow_gclk_selection: Generic clock generator 3 - I2C_0: - user_label: I2C_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync - functionality: I2C - api: HAL:Driver:I2C_Master_Sync - configuration: - i2c_master_advanced: false - i2c_master_arch_dbgstop: Keep running - i2c_master_arch_inactout: Disabled - i2c_master_arch_lowtout: false - i2c_master_arch_mexttoen: false - i2c_master_arch_runstdby: false - i2c_master_arch_sdahold: 300-600ns hold time - i2c_master_arch_sexttoen: false - i2c_master_arch_trise: 215 - i2c_master_baud_rate: 100000 - optional_signals: [] - variant: - specification: SDA=0, SCL=1 - required_signals: - - name: SERCOM0/PAD/0 - pad: PA08 - label: SDA - - name: SERCOM0/PAD/1 - pad: PA09 - label: SCL - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - - name: Slow - input: Generic clock generator 3 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 USART_0: user_label: USART_0 definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM1::driver_config_definition::UART::HAL:Driver:USART.Sync @@ -1534,6 +1525,42 @@ drivers: configuration: core_gclk_selection: Generic clock generator 0 slow_gclk_selection: Generic clock generator 3 + I2C_0: + user_label: I2C_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM2::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + functionality: I2C + api: HAL:Driver:I2C_Master_Sync + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: + specification: SDA=0, SCL=1 + required_signals: + - name: SERCOM2/PAD/0 + pad: PA09 + label: SDA + - name: SERCOM2/PAD/1 + pad: PA08 + label: SCL + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + - name: Slow + input: Generic clock generator 3 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 DELAY_0: user_label: DELAY_0 definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SysTick::driver_config_definition::Delay::HAL:Driver:Delay @@ -1665,13 +1692,13 @@ pads: PA08: name: PA08 definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA08 - mode: Peripheral IO + mode: I2C user_label: PA08 configuration: null PA09: name: PA09 definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA09 - mode: Peripheral IO + mode: I2C user_label: PA09 configuration: null PA24: diff --git a/atmel-samd/asf4/samd51/config/hpl_nvmctrl_config.h b/atmel-samd/asf4/samd51/config/hpl_nvmctrl_config.h new file mode 100644 index 0000000000..daaba85d40 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_nvmctrl_config.h @@ -0,0 +1,36 @@ +/* Auto-generated config file hpl_nvmctrl_config.h */ +#ifndef HPL_NVMCTRL_CONFIG_H +#define HPL_NVMCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Settings + +// Power Reduction Mode During Sleep +// <0x00=> Wake On Access +// <0x01=> Wake Up Instant +// <0x03=> Disabled +// nvm_arch_sleepprm +#ifndef CONF_NVM_SLEEPPRM +#define CONF_NVM_SLEEPPRM 0 +#endif + +// AHB0 Cache Disable +// Indicate whether AHB0 cache is disable or not +// nvm_arch_cache0 +#ifndef CONF_NVM_CACHE0 +#define CONF_NVM_CACHE0 0 +#endif + +// AHB1 Cache Disable +// Indicate whether AHB1 cache is disable or not +// nvm_arch_cache1 +#ifndef CONF_NVM_CACHE1 +#define CONF_NVM_CACHE1 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_NVMCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_sercom_config.h b/atmel-samd/asf4/samd51/config/hpl_sercom_config.h index 35037bd272..8458d9f5e9 100644 --- a/atmel-samd/asf4/samd51/config/hpl_sercom_config.h +++ b/atmel-samd/asf4/samd51/config/hpl_sercom_config.h @@ -166,141 +166,6 @@ #include -#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) -#endif - -#ifndef CONF_SERCOM_0_I2CM_ENABLE -#define CONF_SERCOM_0_I2CM_ENABLE 1 -#endif - -// Basic - -// I2C Bus clock speed (Hz) <1-400000> -// I2C Bus clock (SCL) speed measured in Hz -// i2c_master_baud_rate -#ifndef CONF_SERCOM_0_I2CM_BAUD -#define CONF_SERCOM_0_I2CM_BAUD 100000 -#endif - -// - -// Advanced -// i2c_master_advanced -#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG -#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 0 -#endif - -// TRise (ns) <0-300> -// Determined by the bus impedance, check electric characteristics in the datasheet -// Standard Fast Mode: typical 215ns, max 300ns -// Fast Mode +: typical 60ns, max 100ns -// High Speed Mode: typical 20ns, max 40ns -// i2c_master_arch_trise - -#ifndef CONF_SERCOM_0_I2CM_TRISE -#define CONF_SERCOM_0_I2CM_TRISE 215 -#endif - -// Master SCL Low Extended Time-Out (MEXTTOEN) -// This enables the master SCL low extend time-out -// i2c_master_arch_mexttoen -#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN -#define CONF_SERCOM_0_I2CM_MEXTTOEN 0 -#endif - -// Slave SCL Low Extend Time-Out (SEXTTOEN) -// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine -// i2c_master_arch_sexttoen -#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN -#define CONF_SERCOM_0_I2CM_SEXTTOEN 0 -#endif - -// SCL Low Time-Out (LOWTOUT) -// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold -// i2c_master_arch_lowtout -#ifndef CONF_SERCOM_0_I2CM_LOWTOUT -#define CONF_SERCOM_0_I2CM_LOWTOUT 0 -#endif - -// Inactive Time-Out (INACTOUT) -// <0x0=>Disabled -// <0x1=>5-6 SCL cycle time-out(50-60us) -// <0x2=>10-11 SCL cycle time-out(100-110us) -// <0x3=>20-21 SCL cycle time-out(200-210us) -// Defines if inactivity time-out should be enabled, and how long the time-out should be -// i2c_master_arch_inactout -#ifndef CONF_SERCOM_0_I2CM_INACTOUT -#define CONF_SERCOM_0_I2CM_INACTOUT 0x0 -#endif - -// SDA Hold Time (SDAHOLD) -// <0=>Disabled -// <1=>50-100ns hold time -// <2=>300-600ns hold time -// <3=>400-800ns hold time -// Defines the SDA hold time with respect to the negative edge of SCL -// i2c_master_arch_sdahold -#ifndef CONF_SERCOM_0_I2CM_SDAHOLD -#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2 -#endif - -// Run in stand-by -// Determine if the module shall run in standby sleep mode -// i2c_master_arch_runstdby -#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY -#define CONF_SERCOM_0_I2CM_RUNSTDBY 0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// i2c_master_arch_dbgstop -#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE -#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0 -#endif - -// - -#ifndef CONF_SERCOM_0_I2CM_SPEED -#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode -#endif -#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300 -#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns -#undef CONF_SERCOM_0_I2CM_TRISE -#define CONF_SERCOM_0_I2CM_TRISE 215 -#endif - -// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) -// BAUD + BAUDLOW = -------------------------------------------------------------------- -// i2c_scl_freq -// BAUD: register value low [7:0] -// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW -#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10) \ - - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000) \ - / 1000)) \ - * 10 \ - + 5) \ - / (CONF_SERCOM_0_I2CM_BAUD * 10)) -#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE -#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2) -#warning Requested I2C baudrate too low, please check -#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF -#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1 -#warning Requested I2C baudrate too high, please check -#define CONF_SERCOM_0_I2CM_BAUD_RATE 1 -#else -#define CONF_SERCOM_0_I2CM_BAUD_RATE \ - ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2)) -#endif -#endif - -#include - #ifndef CONF_SERCOM_1_USART_ENABLE #define CONF_SERCOM_1_USART_ENABLE 1 #endif @@ -548,6 +413,141 @@ #endif #endif +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_2_I2CM_BAUD +#define CONF_SERCOM_2_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_2_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_2_I2CM_ADVANCED_CONFIG 0 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_2_I2CM_TRISE +#define CONF_SERCOM_2_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_2_I2CM_MEXTTOEN +#define CONF_SERCOM_2_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_2_I2CM_SEXTTOEN +#define CONF_SERCOM_2_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_2_I2CM_LOWTOUT +#define CONF_SERCOM_2_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_2_I2CM_INACTOUT +#define CONF_SERCOM_2_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_2_I2CM_SDAHOLD +#define CONF_SERCOM_2_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_2_I2CM_RUNSTDBY +#define CONF_SERCOM_2_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_2_I2CM_SPEED +#define CONF_SERCOM_2_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_2_I2CM_TRISE < 215 || CONF_SERCOM_2_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_2_I2CM_TRISE +#define CONF_SERCOM_2_I2CM_TRISE 215 +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_2_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM2_CORE_FREQUENCY - (CONF_SERCOM_2_I2CM_BAUD * 10) \ + - (CONF_SERCOM_2_I2CM_TRISE * (CONF_SERCOM_2_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM2_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_2_I2CM_BAUD * 10)) +#ifndef CONF_SERCOM_2_I2CM_BAUD_RATE +#if CONF_SERCOM_2_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_2_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_2_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_2_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_2_I2CM_BAUD_RATE \ + ((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + // <<< end of configuration section >>> #endif // HPL_SERCOM_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/peripheral_clk_config.h b/atmel-samd/asf4/samd51/config/peripheral_clk_config.h index 2776054173..e68fad7679 100644 --- a/atmel-samd/asf4/samd51/config/peripheral_clk_config.h +++ b/atmel-samd/asf4/samd51/config/peripheral_clk_config.h @@ -707,86 +707,6 @@ // Generic clock generator 11 -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM0_CORE_SRC -#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM0_SLOW_SRC -#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY - * \brief SERCOM0's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY -#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 12000000 -#endif - -/** - * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY - * \brief SERCOM0's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - // Select the clock source for CORE. #ifndef CONF_GCLK_SERCOM1_CORE_SRC #define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val @@ -840,6 +760,86 @@ #define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 #endif +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 +#endif + // TC Clock Source // tc_gclk_selection diff --git a/atmel-samd/asf4/samd51/driver_init.c b/atmel-samd/asf4/samd51/driver_init.c index d41c76318a..cece74926c 100644 --- a/atmel-samd/asf4/samd51/driver_init.c +++ b/atmel-samd/asf4/samd51/driver_init.c @@ -20,10 +20,12 @@ struct adc_sync_descriptor ADC_0; struct dac_sync_descriptor DAC_0; -struct i2c_m_sync_desc I2C_0; +struct flash_descriptor FLASH_0; struct usart_sync_descriptor USART_0; +struct i2c_m_sync_desc I2C_0; + struct pwm_descriptor PWM_0; struct rand_sync_desc RAND_0; @@ -70,6 +72,18 @@ void EVENT_SYSTEM_0_init(void) event_system_init(); } +void FLASH_0_CLOCK_init(void) +{ + + hri_mclk_set_AHBMASK_NVMCTRL_bit(MCLK); +} + +void FLASH_0_init(void) +{ + FLASH_0_CLOCK_init(); + flash_init(&FLASH_0, NVMCTRL); +} + /** * \brief Timer initialization function * @@ -137,29 +151,6 @@ void SPI_0_init(void) SPI_0_PORT_init(); } -void I2C_0_PORT_init(void) -{ - - gpio_set_pin_function(PA08, PINMUX_PA08C_SERCOM0_PAD0); - - gpio_set_pin_function(PA09, PINMUX_PA09C_SERCOM0_PAD1); -} - -void I2C_0_CLOCK_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); -} - -void I2C_0_init(void) -{ - I2C_0_CLOCK_init(); - i2c_m_sync_init(&I2C_0, SERCOM0); - I2C_0_PORT_init(); -} - void USART_0_PORT_init(void) { @@ -183,6 +174,45 @@ void USART_0_init(void) USART_0_PORT_init(); } +void I2C_0_PORT_init(void) +{ + + gpio_set_pin_pull_mode(PA09, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA09, PINMUX_PA09D_SERCOM2_PAD0); + + gpio_set_pin_pull_mode(PA08, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA08, PINMUX_PA08D_SERCOM2_PAD1); +} + +void I2C_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); +} + +void I2C_0_init(void) +{ + I2C_0_CLOCK_init(); + i2c_m_sync_init(&I2C_0, SERCOM2); + I2C_0_PORT_init(); +} + void delay_driver_init(void) { delay_init(SysTick); @@ -341,14 +371,16 @@ void system_init(void) EVENT_SYSTEM_0_init(); + FLASH_0_init(); + TIMER_0_init(); SPI_0_init(); - I2C_0_init(); - USART_0_init(); + I2C_0_init(); + delay_driver_init(); PWM_0_init(); diff --git a/atmel-samd/asf4/samd51/driver_init.h b/atmel-samd/asf4/samd51/driver_init.h index bbae30a2ce..d00f923882 100644 --- a/atmel-samd/asf4/samd51/driver_init.h +++ b/atmel-samd/asf4/samd51/driver_init.h @@ -27,13 +27,15 @@ extern "C" { #include +#include + #include #include -#include - #include +#include + #include #include #include @@ -44,14 +46,16 @@ extern "C" { extern struct adc_sync_descriptor ADC_0; -extern struct dac_sync_descriptor DAC_0; +extern struct dac_sync_descriptor DAC_0; + +extern struct flash_descriptor FLASH_0; extern struct timer_descriptor TIMER_0; extern struct spi_m_sync_descriptor SPI_0; -extern struct i2c_m_sync_desc I2C_0; - extern struct usart_sync_descriptor USART_0; +extern struct i2c_m_sync_desc I2C_0; + extern struct pwm_descriptor PWM_0; extern struct rand_sync_desc RAND_0; @@ -64,18 +68,21 @@ void DAC_0_PORT_init(void); void DAC_0_CLOCK_init(void); void DAC_0_init(void); +void FLASH_0_init(void); +void FLASH_0_CLOCK_init(void); + void SPI_0_PORT_init(void); void SPI_0_CLOCK_init(void); void SPI_0_init(void); -void I2C_0_CLOCK_init(void); -void I2C_0_init(void); -void I2C_0_PORT_init(void); - void USART_0_PORT_init(void); void USART_0_CLOCK_init(void); void USART_0_init(void); +void I2C_0_CLOCK_init(void); +void I2C_0_init(void); +void I2C_0_PORT_init(void); + void delay_driver_init(void); void PWM_0_PORT_init(void); diff --git a/atmel-samd/asf4/samd51/examples/driver_examples.c b/atmel-samd/asf4/samd51/examples/driver_examples.c index 0b0b9ffef2..91ae2887ac 100644 --- a/atmel-samd/asf4/samd51/examples/driver_examples.c +++ b/atmel-samd/asf4/samd51/examples/driver_examples.c @@ -39,6 +39,30 @@ void DAC_0_example(void) } } +static uint8_t src_data[512]; +static uint8_t chk_data[512]; +/** + * Example of using FLASH_0 to read and write buffer. + */ +void FLASH_0_example(void) +{ + uint32_t page_size; + uint16_t i; + + /* Init source data */ + page_size = flash_get_page_size(&FLASH_0); + + for (i = 0; i < page_size; i++) { + src_data[i] = i; + } + + /* Write data to flash */ + flash_write(&FLASH_0, 0x3200, src_data, page_size); + + /* Read data from flash */ + flash_read(&FLASH_0, 0x3200, chk_data, page_size); +} + static struct timer_task TIMER_0_task1, TIMER_0_task2; /** * Example of using TIMER_0. @@ -79,16 +103,6 @@ void SPI_0_example(void) io_write(io, example_SPI_0, 12); } -void I2C_0_example(void) -{ - struct io_descriptor *I2C_0_io; - - i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); - i2c_m_sync_enable(&I2C_0); - i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); - io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); -} - /** * Example of using USART_0 to write "Hello World" using the IO abstraction. */ @@ -101,6 +115,16 @@ void USART_0_example(void) io_write(io, (uint8_t *)"Hello World!", 12); } +void I2C_0_example(void) +{ + struct io_descriptor *I2C_0_io; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); + i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); + io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); +} + void delay_example(void) { delay_ms(5000); diff --git a/atmel-samd/asf4/samd51/examples/driver_examples.h b/atmel-samd/asf4/samd51/examples/driver_examples.h index 31bcb9f10a..71fc42f74c 100644 --- a/atmel-samd/asf4/samd51/examples/driver_examples.h +++ b/atmel-samd/asf4/samd51/examples/driver_examples.h @@ -16,10 +16,12 @@ void ADC_0_example(void); void DAC_0_example(void); -void I2C_0_example(void); +void FLASH_0_example(void); void USART_0_example(void); +void I2C_0_example(void); + void delay_example(void); void PWM_0_example(void); diff --git a/atmel-samd/asf4/samd51/gcc/Makefile b/atmel-samd/asf4/samd51/gcc/Makefile index 74794ef1e7..7f98ae0b67 100644 --- a/atmel-samd/asf4/samd51/gcc/Makefile +++ b/atmel-samd/asf4/samd51/gcc/Makefile @@ -52,18 +52,23 @@ usb/device \ hpl/pm \ hpl/dac \ hpl/sercom \ -hpl/core +hpl/nvmctrl \ +hpl/core \ +usb/class/msc/device # List the object files OBJS += \ hal/src/hal_io.o \ hpl/systick/hpl_systick.o \ +usb/usb_protocol.o \ usb/class/hid/device/hiddf_generic.o \ hpl/evsys/hpl_evsys.o \ hpl/core/hpl_core_m4.o \ usb/class/cdc/device/cdcdf_acm.o \ hal/utils/src/utils_syscalls.o \ hpl/mclk/hpl_mclk.o \ +hpl/nvmctrl/hpl_nvmctrl.o \ +usb/class/msc/device/mscdf.o \ hal/src/hal_spi_m_sync.o \ hal/src/hal_timer.o \ hal/src/hal_pwm.o \ @@ -84,7 +89,7 @@ usb/class/hid/device/hiddf_keyboard.o \ hal/src/hal_usart_sync.o \ hpl/dac/hpl_dac.o \ hpl/gclk/hpl_gclk.o \ -usb/usb_protocol.o \ +hal/src/hal_flash.o \ hal/src/hal_init.o \ gcc/system_samd51.o \ gcc/gcc/startup_samd51.o \ @@ -111,12 +116,15 @@ hpl/adc/hpl_adc.o OBJS_AS_ARGS += \ "hal/src/hal_io.o" \ "hpl/systick/hpl_systick.o" \ +"usb/usb_protocol.o" \ "usb/class/hid/device/hiddf_generic.o" \ "hpl/evsys/hpl_evsys.o" \ "hpl/core/hpl_core_m4.o" \ "usb/class/cdc/device/cdcdf_acm.o" \ "hal/utils/src/utils_syscalls.o" \ "hpl/mclk/hpl_mclk.o" \ +"hpl/nvmctrl/hpl_nvmctrl.o" \ +"usb/class/msc/device/mscdf.o" \ "hal/src/hal_spi_m_sync.o" \ "hal/src/hal_timer.o" \ "hal/src/hal_pwm.o" \ @@ -137,7 +145,7 @@ OBJS_AS_ARGS += \ "hal/src/hal_usart_sync.o" \ "hpl/dac/hpl_dac.o" \ "hpl/gclk/hpl_gclk.o" \ -"usb/usb_protocol.o" \ +"hal/src/hal_flash.o" \ "hal/src/hal_init.o" \ "gcc/system_samd51.o" \ "gcc/gcc/startup_samd51.o" \ @@ -165,6 +173,7 @@ OBJS_AS_ARGS += \ DEPS := $(OBJS:%.o=%.d) DEPS_AS_ARGS += \ +"usb/usb_protocol.d" \ "hal/utils/src/utils_event.d" \ "hal/src/hal_io.d" \ "hpl/ramecc/hpl_ramecc.d" \ @@ -177,6 +186,8 @@ DEPS_AS_ARGS += \ "hal/src/hal_i2c_m_sync.d" \ "hpl/usb/hpl_usb.d" \ "hal/src/hal_evsys.d" \ +"usb/class/msc/device/mscdf.d" \ +"hpl/nvmctrl/hpl_nvmctrl.d" \ "hal/src/hal_pwm.d" \ "hal/src/hal_timer.d" \ "hal/src/hal_spi_m_sync.d" \ @@ -188,7 +199,7 @@ DEPS_AS_ARGS += \ "hal/src/hal_delay.d" \ "hpl/core/hpl_init.d" \ "hpl/pm/hpl_pm.d" \ -"usb/usb_protocol.d" \ +"hal/src/hal_flash.d" \ "hpl/gclk/hpl_gclk.d" \ "hal/src/hal_usb_device.d" \ "usb_start.d" \ @@ -260,7 +271,7 @@ $(OUTPUT_FILE_PATH): $(OBJS) @echo ARM/GNU C Compiler $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ -D__SAMD51G19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" @echo Finished building: $< @@ -269,7 +280,7 @@ $(OUTPUT_FILE_PATH): $(OBJS) @echo ARM/GNU Assembler $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ -D__SAMD51G19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" @echo Finished building: $< @@ -278,7 +289,7 @@ $(OUTPUT_FILE_PATH): $(OBJS) @echo ARM/GNU Preprocessing Assembler $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ -D__SAMD51G19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" @echo Finished building: $< diff --git a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld index 32e509ca8e..c1a2dd39bd 100644 --- a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld +++ b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld @@ -3,22 +3,23 @@ * * \brief Linker script for running in internal FLASH on the SAMD51G19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld index 204f7312e2..cf8e5a314c 100644 --- a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld +++ b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld @@ -3,22 +3,23 @@ * * \brief Linker script for running in internal SRAM on the SAMD51G19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c b/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c index 7963330820..2528e635fb 100644 --- a/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c +++ b/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c @@ -3,22 +3,23 @@ * * \brief gcc starttup file for SAMD51 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/gcc/system_samd51.c b/atmel-samd/asf4/samd51/gcc/system_samd51.c index fa7ed93972..07ddede562 100644 --- a/atmel-samd/asf4/samd51/gcc/system_samd51.c +++ b/atmel-samd/asf4/samd51/gcc/system_samd51.c @@ -3,22 +3,23 @@ * * \brief Low-level initialization functions called upon chip startup. * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/hal/documentation/flash.rst b/atmel-samd/asf4/samd51/hal/documentation/flash.rst new file mode 100644 index 0000000000..fcc86e63f8 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/flash.rst @@ -0,0 +1,52 @@ +The Flash Driver +================ + +Flash is a re-programmable memory that retains program and data +storage even with power off. + +User can write or read several bytes from any valid address in a flash. + +As to the erase/lock/unlock command, the input parameter of address should +be a bytes address aligned with the page start, otherwise, the command will fail +to be executed. At the meantime, the number of pages that can be locked or unlocked +at once depends on region size of the flash. User can get the real number +from the function return value which could be different for the different devices. + +Features +-------- + +* Initialization/de-initialization +* Writing/Reading bytes +* Locking/Unlocking/Erasing pages +* Notifications about errors or being ready for a new command + +Applications +------------ + +* Mini disk which can retain program and data storage +* Boot loader +* Non volatile storage + +Dependencies +------------ + +The peripheral which controls a re-programmable flash memory. + +Concurrency +----------- + +N/A + +Limitations +----------- + +User should pay attention to set a proper stack size in their application, +since the driver manages a temporary buffer in stack to cache unchanged data +when calling flash write and erase function. +Due to flash memory architecture of SAMD21/D20/L21/L22/C20/C21/D09/D10/D11/R21, +write operation erazes row content before each write. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/atmel-samd/asf4/samd51/hal/include/hal_flash.h b/atmel-samd/asf4/samd51/hal/include/hal_flash.h new file mode 100644 index 0000000000..2e6286389f --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_flash.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief Flash related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_FLASH_H_INCLUDED +#define _HAL_FLASH_H_INCLUDED + +#include + +/** + * \addtogroup doc_driver_hal_flash + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Forward declaration of flash_descriptor. */ +struct flash_descriptor; + +/** The callback types */ +enum flash_cb_type { + /** Callback type for ready to accept a new command */ + FLASH_CB_READY, + /** Callback type for error */ + FLASH_CB_ERROR, + FLASH_CB_N +}; + +/** \brief Prototype of callback on FLASH + * + */ +typedef void (*flash_cb_t)(struct flash_descriptor *const descr); + +/** \brief FLASH HAL callbacks + * + */ +struct flash_callbacks { + /** Callback invoked when ready to accept a new command */ + flash_cb_t cb_ready; + /** Callback invoked when error occurs */ + flash_cb_t cb_error; +}; + +/** \brief FLASH HAL driver struct for asynchronous access + */ +struct flash_descriptor { + /** Pointer to FLASH device instance */ + struct _flash_device dev; + /** Callbacks for asynchronous transfer */ + struct flash_callbacks callbacks; +}; + +/** \brief Initialize the FLASH HAL instance and hardware for callback mode + * + * Initialize FLASH HAL with interrupt mode (uses callbacks). + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] hw Pointer to the hardware base. + * \return Initialize status. + */ +int32_t flash_init(struct flash_descriptor *flash, void *const hw); + +/** \brief Deinitialize the FLASH HAL instance + * + * Abort transfer, disable and reset FLASH, and deinitialize software. + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \return Deinitialze status. + */ +int32_t flash_deinit(struct flash_descriptor *flash); + +/** \brief Writes a number of bytes to a page in the internal Flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to a buffer where the content + * will be written to the flash + * \param[in] length Number of bytes to write + * \return Write status. + */ +int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Appends a number of bytes to a page in the internal Flash + * + * This functions never erases the flash before writing. + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address to write to flash + * \param[in] buffer Pointer to a buffer with data to write to flash + * \param[in] length Number of bytes to append + * \return Append status. + */ +int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Reads a number of bytes to a page in the internal Flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read pages will be stored + * \param[in] length Number of bytes to read + * \return Read status. + */ +int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** \brief Register a function as FLASH transfer completion callback + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] type Callback type (\ref flash_cb_type). + * \param[in] func Pointer to callback function. + * \retval 0 Success + * \retval -1 Error + */ +int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func); + +/** \brief Execute lock in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be locked + * \param[in] page_nums Number of pages to be locked + * + * \return Real locked numbers of pages. + */ +int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** \brief Execute unlock in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be unlocked + * \param[in] page_nums Number of pages to be unlocked + * + * \return Real unlocked numbers of pages. + */ +int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** \brief Execute erase in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be erased + * \param[in] page_nums Number of pages to be erased + * \retval 0 Success + * \retval -1 Error + */ +int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** + * \brief Get the flash page size + * + * \param[in, out] flash Pointer to the HAL FLASH instance + * + * \return The flash page size + */ +uint32_t flash_get_page_size(struct flash_descriptor *flash); + +/** + * \brief Get the number of flash page + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * + * \return The flash total page numbers + */ +uint32_t flash_get_total_pages(struct flash_descriptor *flash); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t flash_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* ifndef _HAL_FLASH_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h index 252158296f..5d7d81303b 100644 --- a/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h +++ b/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h @@ -3,7 +3,7 @@ * * \brief DAC related functionality declaration. * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. * * \asf_license_start * diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h index ecbe78d59c..f59f2d73b9 100644 --- a/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h +++ b/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h @@ -3,7 +3,7 @@ * * \brief DAC related functionality declaration. * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. * * \asf_license_start * diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_flash.h b/atmel-samd/asf4/samd51/hal/include/hpl_flash.h new file mode 100644 index 0000000000..774bb5e0b2 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_flash.h @@ -0,0 +1,228 @@ +/** + * \file + * + * \brief FLASH related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_FLASH_H_INCLUDED +#define _HPL_FLASH_H_INCLUDED + +/** + * \addtogroup hpl__flash__group FLASH HPL APIs + * + */ + +/**@{*/ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief FLASH device structure + * + * The FLASH device structure forward declaration. + */ +struct _flash_device; + +/** The callback types */ +enum _flash_cb_type { FLASH_DEVICE_CB_READY, FLASH_DEVICE_CB_ERROR, FLASH_DEVICE_CB_N }; + +/** + * \brief FLASH interrupt handlers structure + */ +struct _flash_callback { + /** Ready to accept new command handler */ + void (*ready_cb)(struct _flash_device *device); + /** Error handler */ + void (*error_cb)(struct _flash_device *device); +}; + +/** + * \brief FLASH descriptor device structure. + */ +struct _flash_device { + struct _flash_callback flash_cb; /*!< Interrupt handers */ + struct _irq_descriptor irq; /*!< Interrupt descriptor */ + void * hw; /*!< Hardware module instance handler */ +}; + +/** + * \brief Initialize FLASH. + * + * This function does low level FLASH configuration. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialize status. + */ +int32_t _flash_init(struct _flash_device *const device, void *const hw); + +/** + * \brief Deinitialize FLASH. + * + * \param[in] device The pointer to FLASH device instance + */ +void _flash_deinit(struct _flash_device *const device); + +/** + * \brief Reads a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read page will be stored + * \param[in] length Number of bytes to read + */ +void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Writes a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] length Number of bytes to write + */ +void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Appends a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer with data to write to flash + * \param[in] length Number of bytes to write + */ +void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Execute lock in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be locked + * \param[in] page_nums Number of pages to be locked + * + * \return Real locked numbers of pages. + */ +int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** \brief Execute unlock in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be unlocked + * \param[in] page_nums Number of pages to be unlocked + * + * \return Real unlocked numbers of pages. + */ +int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** \brief check whether the region which is pointed by address + * is locked + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to check + * + * \return The lock status of assigned address. + */ +bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr); + +/** \brief Execute erase in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be erased + * \param[in] page_nums Number of pages to be erased + */ +void _flash_erase(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** + * \brief Get the flash page size. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash page size + */ +uint32_t _flash_get_page_size(struct _flash_device *const device); + +/** + * \brief Get the numbers of flash page. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash total page numbers + */ +uint32_t _flash_get_total_pages(struct _flash_device *const device); + +/** + * \brief Get the number of wait states for read and write operations. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The number of wait states for read and write operations + */ +uint8_t _flash_get_wait_state(struct _flash_device *const device); + +/** + * \brief Set the number of wait states for read and write operations. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] state The number of wait states + * + */ +void _flash_set_wait_state(struct _flash_device *const device, uint8_t state); + +/** + * \brief Enable/disable Flash interrupt + * + * param[in] device The pointer to Flash device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* _HPL_FLASH_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_reset.h b/atmel-samd/asf4/samd51/hal/include/hpl_reset.h index 010b7d944a..c9861cdcf8 100644 --- a/atmel-samd/asf4/samd51/hal/include/hpl_reset.h +++ b/atmel-samd/asf4/samd51/hal/include/hpl_reset.h @@ -67,14 +67,14 @@ extern "C" { * The list of possible reset reasons. */ enum reset_reason { - - RESET_REASON_POR = 1, - RESET_REASON_BODCORE = 2, - RESET_REASON_BODVDD = 4, - RESET_REASON_EXT = 8, - RESET_REASON_WDT = 16, - RESET_REASON_SYST = 32, - RESET_REASON_BACKUP = 64 + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_NVM = 8, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64, + RESET_REASON_BACKUP = 128 }; /** diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_user_area.h b/atmel-samd/asf4/samd51/hal/include/hpl_user_area.h new file mode 100644 index 0000000000..b5c419bff9 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_user_area.h @@ -0,0 +1,133 @@ +/** + * \file + * + * \brief Special user data area access + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USER_DATA_H_INCLUDED +#define _HPL_USER_DATA_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Read data from user data area + * + * The user data area could be the area that stores user data that is not erased + * with the flash contents, e.g., + * - NVM Software Calibration Area of SAM D/L/C family + * - User Signature of SAM E/S/V 70 + * + * \param[in] base The base address of the user area + * \param[in] offset The byte offset of the data to be read inside the area + * \param[out] buf Pointer to buffer to place the read data + * \param[in] size Size of data in number of bytes + * + * \return Operation status or bytes read. + * \retval ERR_NONE Data read successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, const uint32_t size); + +/** + * \brief Read no more than 32 bits data from user data area + * + * When reading bits, the bitfield can cross 32-bis boundaries. + * + * \param[in] base The base address of the user area + * \param[in] bit_offset Offset in number of bits + * \param[in] n_bits Number of bits to read + * \return data read, assert if anything wrong (address not in user area + * offset, size error, etc.). + */ +uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits); + +/** + * \brief Write data to user data area + * + * The user data area could be the area that stores user data that is not erased + * with the flash contents, e.g., + * - NVM Software Calibration Area of SAM D/L/C family + * - User Signature of SAM E/S/V 70 + * + * When assigned offset and size exceeds the data area, error is reported. + * + * \param[out] base The base address of the user area + * \param[in] offset The offset of the data to be written inside the area + * \param[in] buf Pointer to buffer to place the written data + * \param[in] size Size of data in number of bytes + * + * \return Operation status or bytes writting. + * \retval ERR_NONE Data written successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_DENIED Security bit is set + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size); + +/** + * \brief Write no more than 32 bits data to user data area + * + * When writting bits, the bitfield can cross 32-bis boundaries. + * + * \param[out] base The base address of the user area + * \param[in] bit_offset Offset in number of bits + * \param[in] bits The data content + * \param[in] n_bits Number of bits to write + * \return Operation result + * \retval ERR_NONE Data written successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_DENIED Security bit is set + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USER_DATA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/src/hal_flash.c b/atmel-samd/asf4/samd51/hal/src/hal_flash.c new file mode 100644 index 0000000000..f3cc4bbfe0 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_flash.c @@ -0,0 +1,324 @@ +/** + * \file + * + * \brief Flash functionality implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_flash.h" +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static void flash_ready(struct _flash_device *device); +static void flash_error(struct _flash_device *device); + +static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr); + +/** + * \brief Initialize the FLASH HAL instance and hardware for callback mode. + */ +int32_t flash_init(struct flash_descriptor *flash, void *const hw) +{ + int32_t rc; + + ASSERT(flash && hw); + + rc = _flash_init(&flash->dev, hw); + if (rc) { + return rc; + } + + flash->dev.flash_cb.ready_cb = flash_ready; + flash->dev.flash_cb.error_cb = flash_error; + + return ERR_NONE; +} + +/** + * \brief Deinitialize the FLASH HAL instance. + */ +int32_t flash_deinit(struct flash_descriptor *flash) +{ + ASSERT(flash); + + _flash_deinit(&flash->dev); + + return ERR_NONE; +} + +/** + * \brief Reads a number of bytes to a page in the internal Flash + */ +int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((src_addr > page_size * total_pages) || (src_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + _flash_read(&flash->dev, src_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Updates several bytes to the internal Flash + */ +int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + if (_flash_is_locked(&flash->dev, dst_addr)) { + return ERR_DENIED; + } + + _flash_write(&flash->dev, dst_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Appends a number of bytes to a page in the internal Flash + */ +int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + if (_flash_is_locked(&flash->dev, dst_addr)) { + return ERR_DENIED; + } + + _flash_append(&flash->dev, dst_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Execute erase in the internal flash + */ +int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + _flash_erase(&flash->dev, dst_addr, page_nums); + + return ERR_NONE; +} + +/** + * \brief Register a function as FLASH transfer completion callback + */ +int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func) +{ + ASSERT(flash); + + switch (type) { + case FLASH_CB_READY: + flash->callbacks.cb_ready = func; + break; + + case FLASH_CB_ERROR: + flash->callbacks.cb_error = func; + break; + + default: + return ERR_INVALID_ARG; + } + + _flash_set_irq_state(&flash->dev, (enum _flash_cb_type)type, NULL != func); + + return ERR_NONE; +} + +/** + * \brief Execute lock in the internal flash + */ +int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + return _flash_lock(&flash->dev, dst_addr, page_nums); +} + +/** + * \brief Execute unlock in the internal flash + */ +int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + return _flash_unlock(&flash->dev, dst_addr, page_nums); +} + +/** + * \brief Get the flash page size. + */ +uint32_t flash_get_page_size(struct flash_descriptor *flash) +{ + ASSERT(flash); + return _flash_get_page_size(&flash->dev); +} + +/** + * \brief Get the numbers of flash page. + */ +uint32_t flash_get_total_pages(struct flash_descriptor *flash) +{ + ASSERT(flash); + return _flash_get_total_pages(&flash->dev); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t flash_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal check the address whether it is aligned + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] flash_addr address to be check in flash + * + * \return whether it is valid + * \retval 0 Valid. + * \retval -1 Error, invalid. + */ +static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr) +{ + ASSERT(flash); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + + /* Check if the read address not aligned to the start of a page */ + if (flash_addr & (page_size - 1)) { + return ERR_BAD_ADDRESS; + } + return ERR_NONE; +} + +/** + * \internal Ready for a new flash command + * + * \param[in] device The pointer to flash device structure + */ +static void flash_ready(struct _flash_device *device) +{ + struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); + if (descr->callbacks.cb_ready) { + descr->callbacks.cb_ready(descr); + } +} + +/** + * \internal Error occurs in flash command + * + * \param[in] device The pointer to flash device structure + */ +static void flash_error(struct _flash_device *device) +{ + struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); + if (descr->callbacks.cb_error) { + descr->callbacks.cb_error(descr); + } +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c index c72fe2758a..7fa26ac7fe 100644 --- a/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c +++ b/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c @@ -65,7 +65,11 @@ static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uin ret = _i2c_m_sync_transfer(&i2c->device, &msg); - return (((int32_t)n) > i2c->device.service.msg.len) ? (((int32_t)n) - i2c->device.service.msg.len) : ret; + if (ret) { + return ret; + } + + return n; } /** @@ -84,7 +88,11 @@ static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, co ret = _i2c_m_sync_transfer(&i2c->device, &msg); - return (((int32_t)n) > i2c->device.service.msg.len) ? (((int32_t)n) - i2c->device.service.msg.len) : ret; + if (ret) { + return ret; + } + + return n; } /** diff --git a/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c b/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c index ad1c936185..08ad12a305 100644 --- a/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c +++ b/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c @@ -546,7 +546,7 @@ static inline int32_t _usb_d_ep_halt_clr(const uint8_t ep) if (ep_index < 0) { return -USB_ERR_PARAM; } - if (ept->xfer.hdr.state == USB_EP_S_HALTED) { + if (_usb_d_dev_ep_stall(ep, USB_EP_STALL_GET)) { rc = _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); if (rc < 0) { return rc; diff --git a/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c b/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c index 89ea5f3531..b35ee2aeae 100644 --- a/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c +++ b/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c @@ -223,7 +223,6 @@ int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw) int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw) { int32_t init_status; - uint8_t i = _adc_get_regs((uint32_t)hw); ASSERT(device); diff --git a/atmel-samd/asf4/samd51/hpl/nvmctrl/hpl_nvmctrl.c b/atmel-samd/asf4/samd51/hpl/nvmctrl/hpl_nvmctrl.c new file mode 100644 index 0000000000..2f7f01d5ed --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/nvmctrl/hpl_nvmctrl.c @@ -0,0 +1,699 @@ + +/** + * \file + * + * \brief Non-Volatile Memory Controller + * + * Copyright (C) 2016 -2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMIT ED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#define NVM_MEMORY ((volatile uint32_t *)FLASH_ADDR) +#define NVMCTRL_BLOCK_PAGES (NVMCTRL_BLOCK_SIZE / NVMCTRL_PAGE_SIZE) +#define NVMCTRL_REGIONS_NUM 32 +#define NVMCTRL_INTFLAG_ERR \ + (NVMCTRL_INTFLAG_ADDRE | NVMCTRL_INTFLAG_PROGE | NVMCTRL_INTFLAG_LOCKE | NVMCTRL_INTFLAG_ECCSE \ + | NVMCTRL_INTFLAG_NVME \ + | NVMCTRL_INTFLAG_SEESOVF) +/** + * \brief NVM configuration type + */ +struct nvm_configuration { + hri_nvmctrl_ctrlb_reg_t ctrla; /*!< Control B Register */ +}; + +/** + * \brief Array of NVM configurations + */ +static struct nvm_configuration _nvm + = {(CONF_NVM_CACHE0 << NVMCTRL_CTRLA_CACHEDIS0_Pos) | (CONF_NVM_CACHE1 << NVMCTRL_CTRLA_CACHEDIS1_Pos) + | (NVMCTRL_CTRLA_PRM(CONF_NVM_SLEEPPRM))}; + +/*!< Pointer to hpl device */ +static struct _flash_device *_nvm_dev = NULL; + +static void _flash_erase_block(void *const hw, const uint32_t dst_addr); +static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size); + +/** + * \brief Initialize NVM + */ +int32_t _flash_init(struct _flash_device *const device, void *const hw) +{ + uint32_t ctrla; + + ASSERT(device && (hw == NVMCTRL)); + + device->hw = hw; + ctrla = hri_nvmctrl_read_CTRLA_reg(hw); + ctrla &= ~(NVMCTRL_CTRLA_CACHEDIS0 | NVMCTRL_CTRLA_CACHEDIS1 | NVMCTRL_CTRLA_PRM_Msk); + ctrla |= _nvm.ctrla; + hri_nvmctrl_write_CTRLA_reg(hw, ctrla); + + _nvm_dev = device; + NVIC_DisableIRQ(NVMCTRL_0_IRQn); + NVIC_DisableIRQ(NVMCTRL_1_IRQn); + NVIC_ClearPendingIRQ(NVMCTRL_0_IRQn); + NVIC_ClearPendingIRQ(NVMCTRL_1_IRQn); + NVIC_EnableIRQ(NVMCTRL_0_IRQn); + NVIC_EnableIRQ(NVMCTRL_1_IRQn); + + return ERR_NONE; +} + +/** + * \brief De-initialize NVM + */ +void _flash_deinit(struct _flash_device *const device) +{ + device->hw = NULL; + NVIC_DisableIRQ(NVMCTRL_0_IRQn); + NVIC_DisableIRQ(NVMCTRL_1_IRQn); +} + +/** + * \brief Get the flash page size. + */ +uint32_t _flash_get_page_size(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)NVMCTRL_PAGE_SIZE; +} + +/** + * \brief Get the numbers of flash page. + */ +uint32_t _flash_get_total_pages(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)hri_nvmctrl_read_PARAM_NVMP_bf(device->hw); +} + +/** + * \brief Get the number of wait states for read and write operations. + */ +uint8_t _flash_get_wait_state(struct _flash_device *const device) +{ + return hri_nvmctrl_get_CTRLA_reg(device->hw, NVMCTRL_CTRLA_RWS_Msk); +} + +/** + * \brief Set the number of wait states for read and write operations. + */ +void _flash_set_wait_state(struct _flash_device *const device, uint8_t state) +{ + hri_nvmctrl_write_CTRLA_RWS_bf(device->hw, state); +} + +/** + * \brief Reads a number of bytes to a page in the internal Flash. + */ +void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + uint8_t *nvm_addr = (uint8_t *)NVM_MEMORY; + uint32_t i; + + /* Check if the module is busy */ + while (!hri_nvmctrl_get_STATUS_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + for (i = 0; i < length; i++) { + buffer[i] = nvm_addr[src_addr + i]; + } +} + +/** + * \brief Writes a number of bytes to a page in the internal Flash. + */ +void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint8_t tmp_buffer[NVMCTRL_BLOCK_PAGES][NVMCTRL_PAGE_SIZE]; + uint32_t block_start_addr, block_end_addr; + uint32_t i, j, k; + uint32_t wr_start_addr = dst_addr; + + do { + block_start_addr = wr_start_addr & ~(NVMCTRL_BLOCK_SIZE - 1); + block_end_addr = block_start_addr + NVMCTRL_BLOCK_SIZE - 1; + + /* store the erase data into temp buffer before write */ + for (i = 0; i < NVMCTRL_BLOCK_PAGES; i++) { + _flash_read(device, block_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); + } + + /* temp buffer update */ + j = (wr_start_addr - block_start_addr) / NVMCTRL_PAGE_SIZE; + k = wr_start_addr - block_start_addr - j * NVMCTRL_PAGE_SIZE; + while ((wr_start_addr <= block_end_addr) && (length > 0)) { + tmp_buffer[j][k] = *buffer; + k = (k + 1) % NVMCTRL_PAGE_SIZE; + + if (0 == k) { + j++; + } + + wr_start_addr++; + buffer++; + length--; + } + + /* erase row before write */ + _flash_erase_block(device->hw, block_start_addr); + + /* write buffer to flash */ + for (i = 0; i < NVMCTRL_BLOCK_PAGES; i++) { + _flash_program(device->hw, block_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); + } + } while (block_end_addr < (wr_start_addr + length - 1)); +} + +/** + * \brief Appends a number of bytes in the internal Flash. + */ +void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1); + uint32_t size; + uint32_t offset = 0; + + if (dst_addr != page_start_addr) { + /* Need to write some data to the end of a page */ + size = min(length, NVMCTRL_PAGE_SIZE - (dst_addr - page_start_addr)); + _flash_program(device->hw, dst_addr, buffer, size); + page_start_addr += NVMCTRL_PAGE_SIZE; + offset += size; + } + + while (offset < length) { + size = min(length - offset, NVMCTRL_PAGE_SIZE); + _flash_program(device->hw, page_start_addr, buffer + offset, size); + page_start_addr += NVMCTRL_PAGE_SIZE; + offset += size; + } +} + +/** + * \brief Execute erase in the internal flash + */ +void _flash_erase(struct _flash_device *const device, uint32_t dst_addr, uint32_t page_nums) +{ + uint8_t tmp_buffer[NVMCTRL_PAGE_SIZE]; + uint32_t block_start_addr; + uint32_t i; + + block_start_addr = dst_addr & ~(NVMCTRL_BLOCK_SIZE - 1); + + memset(tmp_buffer, 0xFF, NVMCTRL_PAGE_SIZE); + + /* when address is not aligned with block start address */ + if (dst_addr != block_start_addr) { + block_start_addr += NVMCTRL_BLOCK_SIZE; + for (i = 0; i < NVMCTRL_BLOCK_PAGES - 1; i++) { + _flash_write(device, dst_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); + + if (--page_nums == 0) { + return; + } + + dst_addr += NVMCTRL_PAGE_SIZE; + + if (dst_addr == block_start_addr) { + break; + } + } + } + + while (page_nums >= NVMCTRL_BLOCK_PAGES) { + _flash_erase_block(device->hw, block_start_addr); + block_start_addr += NVMCTRL_PAGE_SIZE; + page_nums -= NVMCTRL_BLOCK_PAGES; + } + + if (page_nums != 0) { + for (i = 0; i < page_nums; i++) { + _flash_write(device, block_start_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); + block_start_addr += NVMCTRL_PAGE_SIZE; + } + } +} + +/** + * \brief Execute lock in the internal flash + */ +int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) +{ + uint32_t region_pages; + uint32_t block_start_addr; + + region_pages = (uint32_t)FLASH_SIZE / (NVMCTRL_REGIONS_NUM * NVMCTRL_PAGE_SIZE); + block_start_addr = dst_addr & ~(NVMCTRL_BLOCK_SIZE - 1); + + if ((page_nums != region_pages) || (dst_addr != block_start_addr)) { + return ERR_INVALID_ARG; + } + + while (!hri_nvmctrl_get_STATUS_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr); + hri_nvmctrl_write_CTRLB_reg(device->hw, NVMCTRL_CTRLB_CMD_LR | NVMCTRL_CTRLB_CMDEX_KEY); + + return (int32_t)FLASH_SIZE / (NVMCTRL_REGIONS_NUM * NVMCTRL_PAGE_SIZE); +} + +/** + * \brief Execute unlock in the internal flash + */ +int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) +{ + uint32_t region_pages; + uint32_t block_start_addr; + + region_pages = (uint32_t)FLASH_SIZE / (NVMCTRL_REGIONS_NUM * NVMCTRL_PAGE_SIZE); + block_start_addr = dst_addr & ~(NVMCTRL_BLOCK_SIZE - 1); + + if ((page_nums != region_pages) || (dst_addr != block_start_addr)) { + return ERR_INVALID_ARG; + } + + while (!hri_nvmctrl_get_STATUS_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr); + hri_nvmctrl_write_CTRLB_reg(device->hw, NVMCTRL_CTRLB_CMD_UR | NVMCTRL_CTRLB_CMDEX_KEY); + + return (int32_t)FLASH_SIZE / (NVMCTRL_REGIONS_NUM * NVMCTRL_PAGE_SIZE); +} + +/** + * \brief check whether the region which is pointed by address + */ +bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr) +{ + uint16_t region_id; + + /* Get region for given page */ + region_id = dst_addr / (FLASH_SIZE / NVMCTRL_REGIONS_NUM); + + return !(hri_nvmctrl_get_RUNLOCK_reg(device->hw, 1 << region_id)); +} + +/** + * \brief Enable/disable Flash interrupt + */ +void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state) +{ + ASSERT(device); + + if (FLASH_DEVICE_CB_READY == type) { + hri_nvmctrl_write_INTEN_DONE_bit(device->hw, state); + } else if (FLASH_DEVICE_CB_ERROR == type) { + if (state) { + hri_nvmctrl_write_INTEN_reg(device->hw, NVMCTRL_INTFLAG_ERR); + } else { + hri_nvmctrl_clear_INTEN_reg(device->hw, NVMCTRL_INTFLAG_ERR); + } + } +} + +/** + * \internal erase a row in flash + * \param[in] hw The pointer to hardware instance + * \param[in] dst_addr Destination page address to erase + */ +static void _flash_erase_block(void *const hw, const uint32_t dst_addr) +{ + while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* Set address and command */ + hri_nvmctrl_write_ADDR_reg(hw, dst_addr); + hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_EB | NVMCTRL_CTRLB_CMDEX_KEY); +} + +/** + * \internal write a page in flash + * \param[in] hw The pointer to hardware instance + * \param[in] dst_addr Destination page address to write + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] size The size of data to write to a page + */ +static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size) +{ + uint32_t *ptr_read = (uint32_t *)buffer; + uint32_t nvm_address = dst_addr / 4; + uint16_t i; + + while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_PBC | NVMCTRL_CTRLB_CMDEX_KEY); + + while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* Writes to the page buffer must be 32 bits, perform manual copy + * to ensure alignment */ + for (i = 0; i < size; i += 4) { + NVM_MEMORY[nvm_address++] = *ptr_read; + ptr_read++; + } + + while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_ADDR_reg(hw, dst_addr); + hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_WP | NVMCTRL_CTRLB_CMDEX_KEY); +} + +/** + * \internal NVM interrupt handler + * + * \param[in] p The pointer to interrupt parameter + */ +static void _nvm_interrupt_handler(struct _flash_device *device) +{ + void *const hw = device->hw; + + if (hri_nvmctrl_get_INTFLAG_DONE_bit(hw)) { + hri_nvmctrl_clear_INTFLAG_DONE_bit(hw); + + if (NULL != device->flash_cb.ready_cb) { + device->flash_cb.ready_cb(device); + } + } else if (hri_nvmctrl_read_INTFLAG_reg(hw) && ~NVMCTRL_INTFLAG_ERR) { + hri_nvmctrl_clear_INTFLAG_reg(hw, NVMCTRL_INTFLAG_ERR); + + if (NULL != device->flash_cb.error_cb) { + device->flash_cb.error_cb(device); + } + } +} + +/** + * \internal NVM 0 interrupt handler + */ +void NVMCTRL_0_Handler(void) +{ + _nvm_interrupt_handler(_nvm_dev); +} + +/** + * \internal NVM 1 interrupt handler + */ +void NVMCTRL_1_Handler(void) +{ + _nvm_interrupt_handler(_nvm_dev); +} + +/* + The NVM User Row contains calibration data that are automatically read at device + power on. + The NVM User Row can be read at address 0x804000. + */ +#ifndef _NVM_USER_ROW_BASE +#define _NVM_USER_ROW_BASE 0x804000 +#endif +#define _NVM_USER_ROW_N_BITS 96 +#define _NVM_USER_ROW_N_BYTES (_NVM_USER_ROW_N_BITS / 8) +#define _NVM_USER_ROW_END (((uint8_t *)_NVM_USER_ROW_BASE) + _NVM_USER_ROW_N_BYTES - 1) +#define _IS_NVM_USER_ROW(b) \ + (((uint8_t *)(b) >= (uint8_t *)(_NVM_USER_ROW_BASE)) && ((uint8_t *)(b) <= (uint8_t *)(_NVM_USER_ROW_END))) +#define _IN_NVM_USER_ROW(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_USER_ROW_END)) + +/* + The NVM Software Calibration Area can be read at address 0x00800080. + The NVM Software Calibration Area can not be written. + */ +#ifndef _NVM_SW_CALIB_AREA_BASE +#define _NVM_SW_CALIB_AREA_BASE 0x00800080 +#endif +#define _NVM_SW_CALIB_AREA_N_BITS 45 +#define _NVM_SW_CALIB_AREA_N_BYTES (_NVM_SW_CALIB_AREA_N_BITS / 8) +#define _NVM_SW_CALIB_AREA_END (((uint8_t *)_NVM_SW_CALIB_AREA_BASE) + _NVM_SW_CALIB_AREA_N_BYTES - 1) +#define _IS_NVM_SW_CALIB_AREA(b) \ + (((uint8_t *)(b) >= (uint8_t *)_NVM_SW_CALIB_AREA_BASE) && ((uint8_t *)(b) <= (uint8_t *)_NVM_SW_CALIB_AREA_END)) +#define _IN_NVM_SW_CALIB_AREA(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_SW_CALIB_AREA_END)) + +/** + * \internal Read left aligned data bits + * \param[in] base Base address for the data + * \param[in] bit_offset Offset for the bitfield start + * \param[in] n_bits Number of bits in the bitfield + */ +static inline uint32_t _user_area_read_l32_bits(const volatile uint32_t *base, const uint32_t bit_offset, + const uint8_t n_bits) +{ + return base[bit_offset >> 5] & ((1 << n_bits) - 1); +} + +/** + * \internal Read right aligned data bits + * \param[in] base Base address for the data + * \param[in] bit_offset Offset for the bitfield start + * \param[in] n_bits Number of bits in the bitfield + */ +static inline uint32_t _user_area_read_r32_bits(const volatile uint32_t *base, const uint32_t bit_offset, + const uint8_t n_bits) +{ + return (base[bit_offset >> 5] >> (bit_offset & 0x1F)) & ((1 << n_bits) - 1); +} + +int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, uint32_t size) +{ + ASSERT(buf); + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, offset)) { + return ERR_BAD_ADDRESS; + } + + /* Cut off if request too many bytes */ + if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + if (!_IN_NVM_SW_CALIB_AREA(base, offset)) { + return ERR_BAD_ADDRESS; + } + + /* Cut off if request too many bytes */ + if (!_IN_NVM_SW_CALIB_AREA(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else { + return ERR_UNSUPPORTED_OP; + } + + /* Copy data */ + memcpy(buf, ((uint8_t *)base) + offset, size); + return ERR_NONE; +} + +uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits) +{ + volatile uint32_t *mem_base = (volatile uint32_t *)base; + uint32_t l_off, l_bits; + uint32_t r_off, r_bits; + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + ASSERT(_IN_NVM_USER_ROW(base, bit_offset >> 3) && _IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)); + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + ASSERT(_IN_NVM_SW_CALIB_AREA(base, bit_offset >> 3) + && _IN_NVM_SW_CALIB_AREA(base, (bit_offset + n_bits - 1) >> 3)); + } else { + ASSERT(false); + } + + /* Since the bitfield can cross 32-bits boundaries, + * left and right bits are read from 32-bit aligned address + * and then combined together. */ + l_off = bit_offset & (~(32 - 1)); + r_off = l_off + 32; + l_bits = 32 - (bit_offset & (32 - 1)); + + if (n_bits > l_bits) { + r_bits = n_bits - l_bits; + } else { + l_bits = n_bits; + r_bits = 0; + } + + return _user_area_read_r32_bits(mem_base, bit_offset, l_bits) + + (_user_area_read_l32_bits(mem_base, r_off, r_bits) << l_bits); +} + +/** \internal Write 96-bit user row + * \param[in] _row Pointer to 96-bit user row data. + */ +static int32_t _user_row_write_exec(const uint32_t *_row) +{ + Nvmctrl *hw = NVMCTRL; + uint32_t ctrla = hri_nvmctrl_read_CTRLA_reg(NVMCTRL); + + /* Denied if Security Bit is set */ + if (DSU->STATUSB.bit.PROT) { + return ERR_DENIED; + } + + /* Do Save */ + + /* - Prepare. */ + while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + hri_nvmctrl_clear_CTRLA_WMODE_bf(NVMCTRL, NVMCTRL_CTRLA_WMODE_Msk); + + /* - Erase AUX row. */ + hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)_NVM_USER_ROW_BASE); + hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_EP | NVMCTRL_CTRLB_CMDEX_KEY); + while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* - Page buffer clear & write. */ + hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_PBC | NVMCTRL_CTRLB_CMDEX_KEY); + while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + *((uint32_t *)NVMCTRL_USER) = _row[0]; + *(((uint32_t *)NVMCTRL_USER) + 1) = _row[1]; + *(((uint32_t *)NVMCTRL_USER) + 2) = _row[2]; + *(((uint32_t *)NVMCTRL_USER) + 3) = 0xFFFFFFFF; + + /* - Write AUX row. */ + hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)_NVM_USER_ROW_BASE); + hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_WQW | NVMCTRL_CTRLB_CMDEX_KEY); + while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* Restore CTRLA */ + hri_nvmctrl_write_CTRLA_reg(NVMCTRL, ctrla); + + return ERR_NONE; +} + +int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size) +{ + uint32_t _row[3]; /* Copy of user row. */ + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, offset)) { + return ERR_BAD_ADDRESS; + } else if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + return ERR_DENIED; + } else { + return ERR_UNSUPPORTED_OP; + } + + memcpy(_row, base, 12); /* Store previous data. */ + memcpy((uint8_t *)_row + offset, buf, size); /* Modify with buf data. */ + + return _user_row_write_exec(_row); +} + +int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits) +{ + uint32_t _row[3]; /* Copy of user row. */ + uint32_t l_off, l_bits; + uint32_t r_off, r_bits; + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, bit_offset >> 3)) { + return ERR_BAD_ADDRESS; + } else if (!_IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + return ERR_DENIED; + } else { + return ERR_UNSUPPORTED_OP; + } + + /* Since the bitfield can cross 32-bits boundaries, + * left and right bits are splitted for 32-bit aligned address + * and then saved. */ + l_off = bit_offset & (~(32 - 1)); + r_off = l_off + 32; + l_bits = 32 - (bit_offset & (32 - 1)); + + if (n_bits > l_bits) { + r_bits = n_bits - l_bits; + } else { + l_bits = n_bits; + r_bits = 0; + } + + memcpy(_row, base, 12); /* Store previous data. */ + + if (l_bits) { + uint32_t l_mask = ((1 << l_bits) - 1) << (bit_offset & (32 - 1)); + _row[bit_offset >> 5] &= ~l_mask; + _row[bit_offset >> 5] |= (bits << (bit_offset & (32 - 1))) & l_mask; + } + + if (r_bits) { + uint32_t r_mask = (1 << r_bits) - 1; + _row[r_off >> 5] &= ~r_mask; + _row[r_off >> 5] |= bits >> l_bits; + } + + return _user_row_write_exec(_row); +} diff --git a/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c b/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c index 9fe612f72b..6b67934ee4 100644 --- a/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c +++ b/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c @@ -2145,10 +2145,10 @@ static int32_t _spi_sync_enable(void *const hw) static int32_t _spi_async_enable(void *const hw) { _spi_sync_enable(hw); - NVIC_EnableIRQ(_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); uint8_t irq = _sercom_get_irq_num(hw); for (uint32_t i = 0; i < 4; i++) { - NVIC_EnableIRQ(irq++); + NVIC_EnableIRQ((IRQn_Type)irq++); } return ERR_NONE; @@ -2183,7 +2183,7 @@ static int32_t _spi_async_disable(void *const hw) hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); uint8_t irq = _sercom_get_irq_num(hw); for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ(irq++); + NVIC_DisableIRQ((IRQn_Type)irq++); } return ERR_NONE; @@ -2409,16 +2409,16 @@ int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) { - NVIC_DisableIRQ(_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ(_sercom_get_irq_num(dev->prvt)); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); return _spi_deinit(dev->prvt); } int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) { - NVIC_DisableIRQ(_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ(_sercom_get_irq_num(dev->prvt)); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); return _spi_deinit(dev->prvt); } diff --git a/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c b/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c index bdf245aa50..b9cec2e284 100644 --- a/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c +++ b/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c @@ -1261,7 +1261,7 @@ static void _usb_d_dev_handle_stall(struct _usb_d_dev_ep *ept, const uint8_t ban uint8_t epn = USB_EP_GET_N(ept->ep); /* Clear interrupt enable. Leave status there for status check. */ _usbd_ep_int_stall_en(epn, bank_n, false); - _usb_d_dev_trans_done(ept, USB_TRANS_STALL); + dev_inst.ep_callbacks.done(ept->ep, USB_TRANS_STALL, ept->trans_count); } /** @@ -1401,7 +1401,7 @@ static inline void _usb_d_dev_handle_eps(uint32_t epint, struct _usb_d_dev_ep *e mask = hw->DEVICE.DeviceEndpoint[epn].EPINTENSET.reg; flags &= mask; if (flags) { - if (!_usb_d_dev_ep_is_busy(ept)) { + if ((ept->flags.bits.eptype == 0x1) && !_usb_d_dev_ep_is_busy(ept)) { _usb_d_dev_trans_setup_isr(ept, flags); } else if (_usb_d_dev_ep_is_in(ept)) { _usb_d_dev_trans_in_isr(ept, flags); @@ -1944,7 +1944,6 @@ int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans) if (!_usb_is_addr4dma(trans->buf, trans->size) || (!_usb_is_aligned(trans->buf)) || (!dir && (trans->size < ept->size))) { if (!ept->cache) { - return -33; return -USB_ERR_FUNC; } /* Use cache all the time. */ diff --git a/atmel-samd/asf4/samd51/include/component-version.h b/atmel-samd/asf4/samd51/include/component-version.h index 43414ee1b6..80801fc128 100644 --- a/atmel-samd/asf4/samd51/include/component-version.h +++ b/atmel-samd/asf4/samd51/include/component-version.h @@ -44,7 +44,7 @@ // The build number does not refer to the component, but to the build number // of the device pack that provides the component. // -#define BUILD_NUMBER 66 +#define BUILD_NUMBER 70 // // The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. @@ -59,7 +59,7 @@ // "%Y-%m-%d %H:%M:%S" // // -#define COMPONENT_DATE_STRING "2017-05-22 10:59:01" +#define COMPONENT_DATE_STRING "2017-08-09 09:59:41" #endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/include/component/ac.h b/atmel-samd/asf4/samd51/include/component/ac.h index 7f7796beb3..24623d00ac 100644 --- a/atmel-samd/asf4/samd51/include/component/ac.h +++ b/atmel-samd/asf4/samd51/include/component/ac.h @@ -3,22 +3,23 @@ * * \brief Component description for AC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/adc.h b/atmel-samd/asf4/samd51/include/component/adc.h index a811491061..33c38ae3f8 100644 --- a/atmel-samd/asf4/samd51/include/component/adc.h +++ b/atmel-samd/asf4/samd51/include/component/adc.h @@ -3,22 +3,23 @@ * * \brief Component description for ADC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/aes.h b/atmel-samd/asf4/samd51/include/component/aes.h index 6d85768c93..5a74eac28b 100644 --- a/atmel-samd/asf4/samd51/include/component/aes.h +++ b/atmel-samd/asf4/samd51/include/component/aes.h @@ -3,22 +3,23 @@ * * \brief Component description for AES * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/ccl.h b/atmel-samd/asf4/samd51/include/component/ccl.h index 73967aef2c..890e81edf6 100644 --- a/atmel-samd/asf4/samd51/include/component/ccl.h +++ b/atmel-samd/asf4/samd51/include/component/ccl.h @@ -3,22 +3,23 @@ * * \brief Component description for CCL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/cmcc.h b/atmel-samd/asf4/samd51/include/component/cmcc.h index 1f7513be4f..92fa6813ef 100644 --- a/atmel-samd/asf4/samd51/include/component/cmcc.h +++ b/atmel-samd/asf4/samd51/include/component/cmcc.h @@ -3,22 +3,23 @@ * * \brief Component description for CMCC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/dac.h b/atmel-samd/asf4/samd51/include/component/dac.h index 72f4df29ff..c67efda303 100644 --- a/atmel-samd/asf4/samd51/include/component/dac.h +++ b/atmel-samd/asf4/samd51/include/component/dac.h @@ -3,22 +3,23 @@ * * \brief Component description for DAC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/dmac.h b/atmel-samd/asf4/samd51/include/component/dmac.h index 2ab792bcba..295b31fe48 100644 --- a/atmel-samd/asf4/samd51/include/component/dmac.h +++ b/atmel-samd/asf4/samd51/include/component/dmac.h @@ -3,22 +3,23 @@ * * \brief Component description for DMAC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/dsu.h b/atmel-samd/asf4/samd51/include/component/dsu.h index 9585bc447e..43ae26d208 100644 --- a/atmel-samd/asf4/samd51/include/component/dsu.h +++ b/atmel-samd/asf4/samd51/include/component/dsu.h @@ -3,22 +3,23 @@ * * \brief Component description for DSU * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/eic.h b/atmel-samd/asf4/samd51/include/component/eic.h index f3a92e921c..53d9e1c080 100644 --- a/atmel-samd/asf4/samd51/include/component/eic.h +++ b/atmel-samd/asf4/samd51/include/component/eic.h @@ -3,22 +3,23 @@ * * \brief Component description for EIC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/evsys.h b/atmel-samd/asf4/samd51/include/component/evsys.h index a9732fa783..c5fdcf53e3 100644 --- a/atmel-samd/asf4/samd51/include/component/evsys.h +++ b/atmel-samd/asf4/samd51/include/component/evsys.h @@ -3,22 +3,23 @@ * * \brief Component description for EVSYS * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/freqm.h b/atmel-samd/asf4/samd51/include/component/freqm.h index ccdea63840..3eca2144e0 100644 --- a/atmel-samd/asf4/samd51/include/component/freqm.h +++ b/atmel-samd/asf4/samd51/include/component/freqm.h @@ -3,22 +3,23 @@ * * \brief Component description for FREQM * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/gclk.h b/atmel-samd/asf4/samd51/include/component/gclk.h index b143ffd4da..6de7d5cdb3 100644 --- a/atmel-samd/asf4/samd51/include/component/gclk.h +++ b/atmel-samd/asf4/samd51/include/component/gclk.h @@ -3,22 +3,23 @@ * * \brief Component description for GCLK * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/hmatrixb.h b/atmel-samd/asf4/samd51/include/component/hmatrixb.h index 99e4b42eb5..e0526c0d8a 100644 --- a/atmel-samd/asf4/samd51/include/component/hmatrixb.h +++ b/atmel-samd/asf4/samd51/include/component/hmatrixb.h @@ -3,22 +3,23 @@ * * \brief Component description for HMATRIXB * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -74,7 +75,7 @@ typedef struct { #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { RoReg8 Reserved1[0x80]; - HmatrixbPrs Prs[5]; /**< \brief Offset: 0x080 HmatrixbPrs groups [CLK_AHB_ID] */ + HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ } Hmatrixb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/atmel-samd/asf4/samd51/include/component/i2s.h b/atmel-samd/asf4/samd51/include/component/i2s.h index 1df00524df..5583c69f60 100644 --- a/atmel-samd/asf4/samd51/include/component/i2s.h +++ b/atmel-samd/asf4/samd51/include/component/i2s.h @@ -3,22 +3,23 @@ * * \brief Component description for I2S * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/icm.h b/atmel-samd/asf4/samd51/include/component/icm.h index 14ed710a63..eb4b28e6ff 100644 --- a/atmel-samd/asf4/samd51/include/component/icm.h +++ b/atmel-samd/asf4/samd51/include/component/icm.h @@ -3,22 +3,23 @@ * * \brief Component description for ICM * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/mclk.h b/atmel-samd/asf4/samd51/include/component/mclk.h index bdc17d19f6..23f84a9b18 100644 --- a/atmel-samd/asf4/samd51/include/component/mclk.h +++ b/atmel-samd/asf4/samd51/include/component/mclk.h @@ -3,22 +3,23 @@ * * \brief Component description for MCLK * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/nvmctrl.h b/atmel-samd/asf4/samd51/include/component/nvmctrl.h index ab027e769c..50f95f5d04 100644 --- a/atmel-samd/asf4/samd51/include/component/nvmctrl.h +++ b/atmel-samd/asf4/samd51/include/component/nvmctrl.h @@ -3,22 +3,23 @@ * * \brief Component description for NVMCTRL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -636,6 +637,8 @@ typedef struct { #define SECTION_NVMCTRL_SW7 +#define SECTION_NVMCTRL_TEMP_LOG + #define SECTION_NVMCTRL_TEMP_LOG_W0 #define SECTION_NVMCTRL_TEMP_LOG_W1 diff --git a/atmel-samd/asf4/samd51/include/component/osc32kctrl.h b/atmel-samd/asf4/samd51/include/component/osc32kctrl.h index feb079c18b..8e41c450ed 100644 --- a/atmel-samd/asf4/samd51/include/component/osc32kctrl.h +++ b/atmel-samd/asf4/samd51/include/component/osc32kctrl.h @@ -3,22 +3,23 @@ * * \brief Component description for OSC32KCTRL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/oscctrl.h b/atmel-samd/asf4/samd51/include/component/oscctrl.h index ca2ad02454..ee9ad2113e 100644 --- a/atmel-samd/asf4/samd51/include/component/oscctrl.h +++ b/atmel-samd/asf4/samd51/include/component/oscctrl.h @@ -3,22 +3,23 @@ * * \brief Component description for OSCCTRL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/pac.h b/atmel-samd/asf4/samd51/include/component/pac.h index a383245d94..d8c27d2a41 100644 --- a/atmel-samd/asf4/samd51/include/component/pac.h +++ b/atmel-samd/asf4/samd51/include/component/pac.h @@ -3,22 +3,23 @@ * * \brief Component description for PAC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/pcc.h b/atmel-samd/asf4/samd51/include/component/pcc.h index 7f8143ccee..899c23da03 100644 --- a/atmel-samd/asf4/samd51/include/component/pcc.h +++ b/atmel-samd/asf4/samd51/include/component/pcc.h @@ -3,22 +3,23 @@ * * \brief Component description for PCC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/pdec.h b/atmel-samd/asf4/samd51/include/component/pdec.h index 53d3c6f85e..2cb862c05e 100644 --- a/atmel-samd/asf4/samd51/include/component/pdec.h +++ b/atmel-samd/asf4/samd51/include/component/pdec.h @@ -3,22 +3,23 @@ * * \brief Component description for PDEC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/pm.h b/atmel-samd/asf4/samd51/include/component/pm.h index 78c9284126..b6161047b5 100644 --- a/atmel-samd/asf4/samd51/include/component/pm.h +++ b/atmel-samd/asf4/samd51/include/component/pm.h @@ -3,22 +3,23 @@ * * \brief Component description for PM * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/port.h b/atmel-samd/asf4/samd51/include/component/port.h index 7c64027e41..9727dcb0ac 100644 --- a/atmel-samd/asf4/samd51/include/component/port.h +++ b/atmel-samd/asf4/samd51/include/component/port.h @@ -3,22 +3,23 @@ * * \brief Component description for PORT * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/qspi.h b/atmel-samd/asf4/samd51/include/component/qspi.h index 0ab56e5cd7..208a955d62 100644 --- a/atmel-samd/asf4/samd51/include/component/qspi.h +++ b/atmel-samd/asf4/samd51/include/component/qspi.h @@ -3,22 +3,23 @@ * * \brief Component description for QSPI * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/ramecc.h b/atmel-samd/asf4/samd51/include/component/ramecc.h index 46387ea887..c5f044685a 100644 --- a/atmel-samd/asf4/samd51/include/component/ramecc.h +++ b/atmel-samd/asf4/samd51/include/component/ramecc.h @@ -3,22 +3,23 @@ * * \brief Component description for RAMECC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/rstc.h b/atmel-samd/asf4/samd51/include/component/rstc.h index 32455d35ed..65f4ed76f1 100644 --- a/atmel-samd/asf4/samd51/include/component/rstc.h +++ b/atmel-samd/asf4/samd51/include/component/rstc.h @@ -3,22 +3,23 @@ * * \brief Component description for RSTC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/rtc.h b/atmel-samd/asf4/samd51/include/component/rtc.h index 506ef4c154..aafac662bc 100644 --- a/atmel-samd/asf4/samd51/include/component/rtc.h +++ b/atmel-samd/asf4/samd51/include/component/rtc.h @@ -3,22 +3,23 @@ * * \brief Component description for RTC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/sdhc.h b/atmel-samd/asf4/samd51/include/component/sdhc.h index 55a1dd8172..a42b9fc560 100644 --- a/atmel-samd/asf4/samd51/include/component/sdhc.h +++ b/atmel-samd/asf4/samd51/include/component/sdhc.h @@ -3,22 +3,23 @@ * * \brief Component description for SDHC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/sercom.h b/atmel-samd/asf4/samd51/include/component/sercom.h index e321891065..f884c127a5 100644 --- a/atmel-samd/asf4/samd51/include/component/sercom.h +++ b/atmel-samd/asf4/samd51/include/component/sercom.h @@ -3,22 +3,23 @@ * * \brief Component description for SERCOM * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/supc.h b/atmel-samd/asf4/samd51/include/component/supc.h index ae898d78bf..9963fa336a 100644 --- a/atmel-samd/asf4/samd51/include/component/supc.h +++ b/atmel-samd/asf4/samd51/include/component/supc.h @@ -3,22 +3,23 @@ * * \brief Component description for SUPC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/tal.h b/atmel-samd/asf4/samd51/include/component/tal.h index 81dfd265b2..dc904e5569 100644 --- a/atmel-samd/asf4/samd51/include/component/tal.h +++ b/atmel-samd/asf4/samd51/include/component/tal.h @@ -3,22 +3,23 @@ * * \brief Component description for TAL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/tc.h b/atmel-samd/asf4/samd51/include/component/tc.h index ded57ffc9e..f4c0daf344 100644 --- a/atmel-samd/asf4/samd51/include/component/tc.h +++ b/atmel-samd/asf4/samd51/include/component/tc.h @@ -3,22 +3,23 @@ * * \brief Component description for TC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/tcc.h b/atmel-samd/asf4/samd51/include/component/tcc.h index b60085cf5b..a32abe964d 100644 --- a/atmel-samd/asf4/samd51/include/component/tcc.h +++ b/atmel-samd/asf4/samd51/include/component/tcc.h @@ -3,22 +3,23 @@ * * \brief Component description for TCC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/trng.h b/atmel-samd/asf4/samd51/include/component/trng.h index c7a5ba380d..f81d228383 100644 --- a/atmel-samd/asf4/samd51/include/component/trng.h +++ b/atmel-samd/asf4/samd51/include/component/trng.h @@ -3,22 +3,23 @@ * * \brief Component description for TRNG * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/usb.h b/atmel-samd/asf4/samd51/include/component/usb.h index 5bed6c7e10..1c56e1dd02 100644 --- a/atmel-samd/asf4/samd51/include/component/usb.h +++ b/atmel-samd/asf4/samd51/include/component/usb.h @@ -3,22 +3,23 @@ * * \brief Component description for USB * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/component/wdt.h b/atmel-samd/asf4/samd51/include/component/wdt.h index 050250a1be..ce1947dcca 100644 --- a/atmel-samd/asf4/samd51/include/component/wdt.h +++ b/atmel-samd/asf4/samd51/include/component/wdt.h @@ -3,22 +3,23 @@ * * \brief Component description for WDT * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/ac.h b/atmel-samd/asf4/samd51/include/instance/ac.h index 24ef486e7a..bc5bd05e91 100644 --- a/atmel-samd/asf4/samd51/include/instance/ac.h +++ b/atmel-samd/asf4/samd51/include/instance/ac.h @@ -3,22 +3,23 @@ * * \brief Instance description for AC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/adc0.h b/atmel-samd/asf4/samd51/include/instance/adc0.h index 21b5d28008..6808fff9da 100644 --- a/atmel-samd/asf4/samd51/include/instance/adc0.h +++ b/atmel-samd/asf4/samd51/include/instance/adc0.h @@ -3,22 +3,23 @@ * * \brief Instance description for ADC0 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -94,6 +95,5 @@ #define ADC0_OPAMP01 0 // MUXPOS value to select OPAMP01 #define ADC0_PTAT 28 // MUXPOS value to select PTAT #define ADC0_TOUCH_IMPLEMENTED 1 // TOUCH implemented or not -#define ADC0_TOUCH_LINES_NUM 32 // Number of touch lines #endif /* _SAMD51_ADC0_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd51/include/instance/adc1.h b/atmel-samd/asf4/samd51/include/instance/adc1.h index 8d9deb497b..af572c0560 100644 --- a/atmel-samd/asf4/samd51/include/instance/adc1.h +++ b/atmel-samd/asf4/samd51/include/instance/adc1.h @@ -3,22 +3,23 @@ * * \brief Instance description for ADC1 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/aes.h b/atmel-samd/asf4/samd51/include/instance/aes.h index df35a8cef6..5ce5cb3373 100644 --- a/atmel-samd/asf4/samd51/include/instance/aes.h +++ b/atmel-samd/asf4/samd51/include/instance/aes.h @@ -3,22 +3,23 @@ * * \brief Instance description for AES * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/ccl.h b/atmel-samd/asf4/samd51/include/instance/ccl.h index 93d94bf476..5f76d1ae31 100644 --- a/atmel-samd/asf4/samd51/include/instance/ccl.h +++ b/atmel-samd/asf4/samd51/include/instance/ccl.h @@ -3,22 +3,23 @@ * * \brief Instance description for CCL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/cmcc.h b/atmel-samd/asf4/samd51/include/instance/cmcc.h index 33458a05b3..6744e27f86 100644 --- a/atmel-samd/asf4/samd51/include/instance/cmcc.h +++ b/atmel-samd/asf4/samd51/include/instance/cmcc.h @@ -3,22 +3,23 @@ * * \brief Instance description for CMCC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/dac.h b/atmel-samd/asf4/samd51/include/instance/dac.h index 31a834a8aa..15a7af4ab8 100644 --- a/atmel-samd/asf4/samd51/include/instance/dac.h +++ b/atmel-samd/asf4/samd51/include/instance/dac.h @@ -3,22 +3,23 @@ * * \brief Instance description for DAC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/dmac.h b/atmel-samd/asf4/samd51/include/instance/dmac.h index d621c312c6..078ebfb022 100644 --- a/atmel-samd/asf4/samd51/include/instance/dmac.h +++ b/atmel-samd/asf4/samd51/include/instance/dmac.h @@ -3,22 +3,23 @@ * * \brief Instance description for DMAC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/dsu.h b/atmel-samd/asf4/samd51/include/instance/dsu.h index b25ad15e01..dc0c3d2e63 100644 --- a/atmel-samd/asf4/samd51/include/instance/dsu.h +++ b/atmel-samd/asf4/samd51/include/instance/dsu.h @@ -3,22 +3,23 @@ * * \brief Instance description for DSU * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/eic.h b/atmel-samd/asf4/samd51/include/instance/eic.h index 353e170b03..d4d6d3eb42 100644 --- a/atmel-samd/asf4/samd51/include/instance/eic.h +++ b/atmel-samd/asf4/samd51/include/instance/eic.h @@ -3,22 +3,23 @@ * * \brief Instance description for EIC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/evsys.h b/atmel-samd/asf4/samd51/include/instance/evsys.h index a3a41406ea..59c14905b5 100644 --- a/atmel-samd/asf4/samd51/include/instance/evsys.h +++ b/atmel-samd/asf4/samd51/include/instance/evsys.h @@ -3,22 +3,23 @@ * * \brief Instance description for EVSYS * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/freqm.h b/atmel-samd/asf4/samd51/include/instance/freqm.h index 1dbe9d3885..0a94593175 100644 --- a/atmel-samd/asf4/samd51/include/instance/freqm.h +++ b/atmel-samd/asf4/samd51/include/instance/freqm.h @@ -3,22 +3,23 @@ * * \brief Instance description for FREQM * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/gclk.h b/atmel-samd/asf4/samd51/include/instance/gclk.h index 5f4f668ded..c04e384022 100644 --- a/atmel-samd/asf4/samd51/include/instance/gclk.h +++ b/atmel-samd/asf4/samd51/include/instance/gclk.h @@ -3,22 +3,23 @@ * * \brief Instance description for GCLK * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/hmatrix.h b/atmel-samd/asf4/samd51/include/instance/hmatrix.h index 6b80fe5780..9333d859ed 100644 --- a/atmel-samd/asf4/samd51/include/instance/hmatrix.h +++ b/atmel-samd/asf4/samd51/include/instance/hmatrix.h @@ -3,22 +3,23 @@ * * \brief Instance description for HMATRIX * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -41,6 +42,28 @@ #define REG_HMATRIX_PRBS3 (0x4100C09C) /**< \brief (HMATRIX) Priority B for Slave 3 */ #define REG_HMATRIX_PRAS4 (0x4100C0A0) /**< \brief (HMATRIX) Priority A for Slave 4 */ #define REG_HMATRIX_PRBS4 (0x4100C0A4) /**< \brief (HMATRIX) Priority B for Slave 4 */ +#define REG_HMATRIX_PRAS5 (0x4100C0A8) /**< \brief (HMATRIX) Priority A for Slave 5 */ +#define REG_HMATRIX_PRBS5 (0x4100C0AC) /**< \brief (HMATRIX) Priority B for Slave 5 */ +#define REG_HMATRIX_PRAS6 (0x4100C0B0) /**< \brief (HMATRIX) Priority A for Slave 6 */ +#define REG_HMATRIX_PRBS6 (0x4100C0B4) /**< \brief (HMATRIX) Priority B for Slave 6 */ +#define REG_HMATRIX_PRAS7 (0x4100C0B8) /**< \brief (HMATRIX) Priority A for Slave 7 */ +#define REG_HMATRIX_PRBS7 (0x4100C0BC) /**< \brief (HMATRIX) Priority B for Slave 7 */ +#define REG_HMATRIX_PRAS8 (0x4100C0C0) /**< \brief (HMATRIX) Priority A for Slave 8 */ +#define REG_HMATRIX_PRBS8 (0x4100C0C4) /**< \brief (HMATRIX) Priority B for Slave 8 */ +#define REG_HMATRIX_PRAS9 (0x4100C0C8) /**< \brief (HMATRIX) Priority A for Slave 9 */ +#define REG_HMATRIX_PRBS9 (0x4100C0CC) /**< \brief (HMATRIX) Priority B for Slave 9 */ +#define REG_HMATRIX_PRAS10 (0x4100C0D0) /**< \brief (HMATRIX) Priority A for Slave 10 */ +#define REG_HMATRIX_PRBS10 (0x4100C0D4) /**< \brief (HMATRIX) Priority B for Slave 10 */ +#define REG_HMATRIX_PRAS11 (0x4100C0D8) /**< \brief (HMATRIX) Priority A for Slave 11 */ +#define REG_HMATRIX_PRBS11 (0x4100C0DC) /**< \brief (HMATRIX) Priority B for Slave 11 */ +#define REG_HMATRIX_PRAS12 (0x4100C0E0) /**< \brief (HMATRIX) Priority A for Slave 12 */ +#define REG_HMATRIX_PRBS12 (0x4100C0E4) /**< \brief (HMATRIX) Priority B for Slave 12 */ +#define REG_HMATRIX_PRAS13 (0x4100C0E8) /**< \brief (HMATRIX) Priority A for Slave 13 */ +#define REG_HMATRIX_PRBS13 (0x4100C0EC) /**< \brief (HMATRIX) Priority B for Slave 13 */ +#define REG_HMATRIX_PRAS14 (0x4100C0F0) /**< \brief (HMATRIX) Priority A for Slave 14 */ +#define REG_HMATRIX_PRBS14 (0x4100C0F4) /**< \brief (HMATRIX) Priority B for Slave 14 */ +#define REG_HMATRIX_PRAS15 (0x4100C0F8) /**< \brief (HMATRIX) Priority A for Slave 15 */ +#define REG_HMATRIX_PRBS15 (0x4100C0FC) /**< \brief (HMATRIX) Priority B for Slave 15 */ #else #define REG_HMATRIX_PRAS0 (*(RwReg *)0x4100C080UL) /**< \brief (HMATRIX) Priority A for Slave 0 */ #define REG_HMATRIX_PRBS0 (*(RwReg *)0x4100C084UL) /**< \brief (HMATRIX) Priority B for Slave 0 */ @@ -52,6 +75,28 @@ #define REG_HMATRIX_PRBS3 (*(RwReg *)0x4100C09CUL) /**< \brief (HMATRIX) Priority B for Slave 3 */ #define REG_HMATRIX_PRAS4 (*(RwReg *)0x4100C0A0UL) /**< \brief (HMATRIX) Priority A for Slave 4 */ #define REG_HMATRIX_PRBS4 (*(RwReg *)0x4100C0A4UL) /**< \brief (HMATRIX) Priority B for Slave 4 */ +#define REG_HMATRIX_PRAS5 (*(RwReg *)0x4100C0A8UL) /**< \brief (HMATRIX) Priority A for Slave 5 */ +#define REG_HMATRIX_PRBS5 (*(RwReg *)0x4100C0ACUL) /**< \brief (HMATRIX) Priority B for Slave 5 */ +#define REG_HMATRIX_PRAS6 (*(RwReg *)0x4100C0B0UL) /**< \brief (HMATRIX) Priority A for Slave 6 */ +#define REG_HMATRIX_PRBS6 (*(RwReg *)0x4100C0B4UL) /**< \brief (HMATRIX) Priority B for Slave 6 */ +#define REG_HMATRIX_PRAS7 (*(RwReg *)0x4100C0B8UL) /**< \brief (HMATRIX) Priority A for Slave 7 */ +#define REG_HMATRIX_PRBS7 (*(RwReg *)0x4100C0BCUL) /**< \brief (HMATRIX) Priority B for Slave 7 */ +#define REG_HMATRIX_PRAS8 (*(RwReg *)0x4100C0C0UL) /**< \brief (HMATRIX) Priority A for Slave 8 */ +#define REG_HMATRIX_PRBS8 (*(RwReg *)0x4100C0C4UL) /**< \brief (HMATRIX) Priority B for Slave 8 */ +#define REG_HMATRIX_PRAS9 (*(RwReg *)0x4100C0C8UL) /**< \brief (HMATRIX) Priority A for Slave 9 */ +#define REG_HMATRIX_PRBS9 (*(RwReg *)0x4100C0CCUL) /**< \brief (HMATRIX) Priority B for Slave 9 */ +#define REG_HMATRIX_PRAS10 (*(RwReg *)0x4100C0D0UL) /**< \brief (HMATRIX) Priority A for Slave 10 */ +#define REG_HMATRIX_PRBS10 (*(RwReg *)0x4100C0D4UL) /**< \brief (HMATRIX) Priority B for Slave 10 */ +#define REG_HMATRIX_PRAS11 (*(RwReg *)0x4100C0D8UL) /**< \brief (HMATRIX) Priority A for Slave 11 */ +#define REG_HMATRIX_PRBS11 (*(RwReg *)0x4100C0DCUL) /**< \brief (HMATRIX) Priority B for Slave 11 */ +#define REG_HMATRIX_PRAS12 (*(RwReg *)0x4100C0E0UL) /**< \brief (HMATRIX) Priority A for Slave 12 */ +#define REG_HMATRIX_PRBS12 (*(RwReg *)0x4100C0E4UL) /**< \brief (HMATRIX) Priority B for Slave 12 */ +#define REG_HMATRIX_PRAS13 (*(RwReg *)0x4100C0E8UL) /**< \brief (HMATRIX) Priority A for Slave 13 */ +#define REG_HMATRIX_PRBS13 (*(RwReg *)0x4100C0ECUL) /**< \brief (HMATRIX) Priority B for Slave 13 */ +#define REG_HMATRIX_PRAS14 (*(RwReg *)0x4100C0F0UL) /**< \brief (HMATRIX) Priority A for Slave 14 */ +#define REG_HMATRIX_PRBS14 (*(RwReg *)0x4100C0F4UL) /**< \brief (HMATRIX) Priority B for Slave 14 */ +#define REG_HMATRIX_PRAS15 (*(RwReg *)0x4100C0F8UL) /**< \brief (HMATRIX) Priority A for Slave 15 */ +#define REG_HMATRIX_PRBS15 (*(RwReg *)0x4100C0FCUL) /**< \brief (HMATRIX) Priority B for Slave 15 */ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for HMATRIX peripheral ========== */ diff --git a/atmel-samd/asf4/samd51/include/instance/i2s.h b/atmel-samd/asf4/samd51/include/instance/i2s.h index 4957cfeb91..833a2b101b 100644 --- a/atmel-samd/asf4/samd51/include/instance/i2s.h +++ b/atmel-samd/asf4/samd51/include/instance/i2s.h @@ -3,22 +3,23 @@ * * \brief Instance description for I2S * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/icm.h b/atmel-samd/asf4/samd51/include/instance/icm.h index 7525f5cc7f..08a8e8c01e 100644 --- a/atmel-samd/asf4/samd51/include/instance/icm.h +++ b/atmel-samd/asf4/samd51/include/instance/icm.h @@ -3,22 +3,23 @@ * * \brief Instance description for ICM * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/mclk.h b/atmel-samd/asf4/samd51/include/instance/mclk.h index e84f031e76..65e68bcf79 100644 --- a/atmel-samd/asf4/samd51/include/instance/mclk.h +++ b/atmel-samd/asf4/samd51/include/instance/mclk.h @@ -3,22 +3,23 @@ * * \brief Instance description for MCLK * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/nvmctrl.h b/atmel-samd/asf4/samd51/include/instance/nvmctrl.h index b49e16592c..efd120920b 100644 --- a/atmel-samd/asf4/samd51/include/instance/nvmctrl.h +++ b/atmel-samd/asf4/samd51/include/instance/nvmctrl.h @@ -3,22 +3,23 @@ * * \brief Instance description for NVMCTRL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/osc32kctrl.h b/atmel-samd/asf4/samd51/include/instance/osc32kctrl.h index 03d2068305..1313a0c67d 100644 --- a/atmel-samd/asf4/samd51/include/instance/osc32kctrl.h +++ b/atmel-samd/asf4/samd51/include/instance/osc32kctrl.h @@ -3,22 +3,23 @@ * * \brief Instance description for OSC32KCTRL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/oscctrl.h b/atmel-samd/asf4/samd51/include/instance/oscctrl.h index e1b6c9a639..5e8d00066b 100644 --- a/atmel-samd/asf4/samd51/include/instance/oscctrl.h +++ b/atmel-samd/asf4/samd51/include/instance/oscctrl.h @@ -3,22 +3,23 @@ * * \brief Instance description for OSCCTRL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/pac.h b/atmel-samd/asf4/samd51/include/instance/pac.h index a1866ef8ab..3d35951e74 100644 --- a/atmel-samd/asf4/samd51/include/instance/pac.h +++ b/atmel-samd/asf4/samd51/include/instance/pac.h @@ -3,22 +3,23 @@ * * \brief Instance description for PAC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/pcc.h b/atmel-samd/asf4/samd51/include/instance/pcc.h index 0414681f7f..1148237444 100644 --- a/atmel-samd/asf4/samd51/include/instance/pcc.h +++ b/atmel-samd/asf4/samd51/include/instance/pcc.h @@ -3,22 +3,23 @@ * * \brief Instance description for PCC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/pdec.h b/atmel-samd/asf4/samd51/include/instance/pdec.h index 41b1ab9095..0b207a2204 100644 --- a/atmel-samd/asf4/samd51/include/instance/pdec.h +++ b/atmel-samd/asf4/samd51/include/instance/pdec.h @@ -3,22 +3,23 @@ * * \brief Instance description for PDEC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/pm.h b/atmel-samd/asf4/samd51/include/instance/pm.h index 9942ca4fe4..534aee29f8 100644 --- a/atmel-samd/asf4/samd51/include/instance/pm.h +++ b/atmel-samd/asf4/samd51/include/instance/pm.h @@ -3,22 +3,23 @@ * * \brief Instance description for PM * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/port.h b/atmel-samd/asf4/samd51/include/instance/port.h index b8dfe92d76..85c913108a 100644 --- a/atmel-samd/asf4/samd51/include/instance/port.h +++ b/atmel-samd/asf4/samd51/include/instance/port.h @@ -3,22 +3,23 @@ * * \brief Instance description for PORT * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/qspi.h b/atmel-samd/asf4/samd51/include/instance/qspi.h index c604518e90..a85bf3bfa7 100644 --- a/atmel-samd/asf4/samd51/include/instance/qspi.h +++ b/atmel-samd/asf4/samd51/include/instance/qspi.h @@ -3,22 +3,23 @@ * * \brief Instance description for QSPI * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/ramecc.h b/atmel-samd/asf4/samd51/include/instance/ramecc.h index 6f5f3dcdbd..c162e1e8d1 100644 --- a/atmel-samd/asf4/samd51/include/instance/ramecc.h +++ b/atmel-samd/asf4/samd51/include/instance/ramecc.h @@ -3,22 +3,23 @@ * * \brief Instance description for RAMECC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/rstc.h b/atmel-samd/asf4/samd51/include/instance/rstc.h index a36433b6a8..f1e5d7db78 100644 --- a/atmel-samd/asf4/samd51/include/instance/rstc.h +++ b/atmel-samd/asf4/samd51/include/instance/rstc.h @@ -3,22 +3,23 @@ * * \brief Instance description for RSTC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/rtc.h b/atmel-samd/asf4/samd51/include/instance/rtc.h index 15da68d752..c31c674528 100644 --- a/atmel-samd/asf4/samd51/include/instance/rtc.h +++ b/atmel-samd/asf4/samd51/include/instance/rtc.h @@ -3,22 +3,23 @@ * * \brief Instance description for RTC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sdhc0.h b/atmel-samd/asf4/samd51/include/instance/sdhc0.h index ae52a297c9..c7f723da5c 100644 --- a/atmel-samd/asf4/samd51/include/instance/sdhc0.h +++ b/atmel-samd/asf4/samd51/include/instance/sdhc0.h @@ -3,22 +3,23 @@ * * \brief Instance description for SDHC0 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sdhc1.h b/atmel-samd/asf4/samd51/include/instance/sdhc1.h index 92b7677271..94eeaaab2c 100644 --- a/atmel-samd/asf4/samd51/include/instance/sdhc1.h +++ b/atmel-samd/asf4/samd51/include/instance/sdhc1.h @@ -3,22 +3,23 @@ * * \brief Instance description for SDHC1 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sercom0.h b/atmel-samd/asf4/samd51/include/instance/sercom0.h index 7b3e4902fa..cd440c5648 100644 --- a/atmel-samd/asf4/samd51/include/instance/sercom0.h +++ b/atmel-samd/asf4/samd51/include/instance/sercom0.h @@ -3,22 +3,23 @@ * * \brief Instance description for SERCOM0 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sercom1.h b/atmel-samd/asf4/samd51/include/instance/sercom1.h index 6252cf09a1..ebf29a0fa6 100644 --- a/atmel-samd/asf4/samd51/include/instance/sercom1.h +++ b/atmel-samd/asf4/samd51/include/instance/sercom1.h @@ -3,22 +3,23 @@ * * \brief Instance description for SERCOM1 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sercom2.h b/atmel-samd/asf4/samd51/include/instance/sercom2.h index 3ba6570d6c..674e63b700 100644 --- a/atmel-samd/asf4/samd51/include/instance/sercom2.h +++ b/atmel-samd/asf4/samd51/include/instance/sercom2.h @@ -3,22 +3,23 @@ * * \brief Instance description for SERCOM2 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sercom3.h b/atmel-samd/asf4/samd51/include/instance/sercom3.h index 1954696961..9edd4e9242 100644 --- a/atmel-samd/asf4/samd51/include/instance/sercom3.h +++ b/atmel-samd/asf4/samd51/include/instance/sercom3.h @@ -3,22 +3,23 @@ * * \brief Instance description for SERCOM3 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sercom4.h b/atmel-samd/asf4/samd51/include/instance/sercom4.h index b89b229fbb..20665abba0 100644 --- a/atmel-samd/asf4/samd51/include/instance/sercom4.h +++ b/atmel-samd/asf4/samd51/include/instance/sercom4.h @@ -3,22 +3,23 @@ * * \brief Instance description for SERCOM4 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sercom5.h b/atmel-samd/asf4/samd51/include/instance/sercom5.h index 51b3325cab..7705b5f5ca 100644 --- a/atmel-samd/asf4/samd51/include/instance/sercom5.h +++ b/atmel-samd/asf4/samd51/include/instance/sercom5.h @@ -3,22 +3,23 @@ * * \brief Instance description for SERCOM5 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sercom6.h b/atmel-samd/asf4/samd51/include/instance/sercom6.h index ffe8c123a9..0d86569e86 100644 --- a/atmel-samd/asf4/samd51/include/instance/sercom6.h +++ b/atmel-samd/asf4/samd51/include/instance/sercom6.h @@ -3,22 +3,23 @@ * * \brief Instance description for SERCOM6 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/sercom7.h b/atmel-samd/asf4/samd51/include/instance/sercom7.h index 5f531fb5e4..22bccde20d 100644 --- a/atmel-samd/asf4/samd51/include/instance/sercom7.h +++ b/atmel-samd/asf4/samd51/include/instance/sercom7.h @@ -3,22 +3,23 @@ * * \brief Instance description for SERCOM7 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/supc.h b/atmel-samd/asf4/samd51/include/instance/supc.h index ec5cebbde6..495c6a3995 100644 --- a/atmel-samd/asf4/samd51/include/instance/supc.h +++ b/atmel-samd/asf4/samd51/include/instance/supc.h @@ -3,22 +3,23 @@ * * \brief Instance description for SUPC * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tal.h b/atmel-samd/asf4/samd51/include/instance/tal.h index b2f75ff2f8..9facace8e0 100644 --- a/atmel-samd/asf4/samd51/include/instance/tal.h +++ b/atmel-samd/asf4/samd51/include/instance/tal.h @@ -3,22 +3,23 @@ * * \brief Instance description for TAL * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tc0.h b/atmel-samd/asf4/samd51/include/instance/tc0.h index 0fd858973f..7b3d2b8594 100644 --- a/atmel-samd/asf4/samd51/include/instance/tc0.h +++ b/atmel-samd/asf4/samd51/include/instance/tc0.h @@ -3,22 +3,23 @@ * * \brief Instance description for TC0 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tc1.h b/atmel-samd/asf4/samd51/include/instance/tc1.h index 987c1c34e2..544a7055ae 100644 --- a/atmel-samd/asf4/samd51/include/instance/tc1.h +++ b/atmel-samd/asf4/samd51/include/instance/tc1.h @@ -3,22 +3,23 @@ * * \brief Instance description for TC1 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tc2.h b/atmel-samd/asf4/samd51/include/instance/tc2.h index 7be1a4cde9..2578fbfdb2 100644 --- a/atmel-samd/asf4/samd51/include/instance/tc2.h +++ b/atmel-samd/asf4/samd51/include/instance/tc2.h @@ -3,22 +3,23 @@ * * \brief Instance description for TC2 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tc3.h b/atmel-samd/asf4/samd51/include/instance/tc3.h index 0950ecb3d5..6ef2009d5d 100644 --- a/atmel-samd/asf4/samd51/include/instance/tc3.h +++ b/atmel-samd/asf4/samd51/include/instance/tc3.h @@ -3,22 +3,23 @@ * * \brief Instance description for TC3 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tc4.h b/atmel-samd/asf4/samd51/include/instance/tc4.h index 1b3aca282e..392bc74abd 100644 --- a/atmel-samd/asf4/samd51/include/instance/tc4.h +++ b/atmel-samd/asf4/samd51/include/instance/tc4.h @@ -3,22 +3,23 @@ * * \brief Instance description for TC4 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tc5.h b/atmel-samd/asf4/samd51/include/instance/tc5.h index 27b0cfb4ac..7e28247abb 100644 --- a/atmel-samd/asf4/samd51/include/instance/tc5.h +++ b/atmel-samd/asf4/samd51/include/instance/tc5.h @@ -3,22 +3,23 @@ * * \brief Instance description for TC5 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tc6.h b/atmel-samd/asf4/samd51/include/instance/tc6.h index d42f65f0af..df6718fc82 100644 --- a/atmel-samd/asf4/samd51/include/instance/tc6.h +++ b/atmel-samd/asf4/samd51/include/instance/tc6.h @@ -3,22 +3,23 @@ * * \brief Instance description for TC6 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tc7.h b/atmel-samd/asf4/samd51/include/instance/tc7.h index 339c2f51a3..3de53eeb5d 100644 --- a/atmel-samd/asf4/samd51/include/instance/tc7.h +++ b/atmel-samd/asf4/samd51/include/instance/tc7.h @@ -3,22 +3,23 @@ * * \brief Instance description for TC7 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tcc0.h b/atmel-samd/asf4/samd51/include/instance/tcc0.h index bf4900d982..edcfc368eb 100644 --- a/atmel-samd/asf4/samd51/include/instance/tcc0.h +++ b/atmel-samd/asf4/samd51/include/instance/tcc0.h @@ -3,22 +3,23 @@ * * \brief Instance description for TCC0 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tcc1.h b/atmel-samd/asf4/samd51/include/instance/tcc1.h index 96cc6e6dfd..0c9ce3e881 100644 --- a/atmel-samd/asf4/samd51/include/instance/tcc1.h +++ b/atmel-samd/asf4/samd51/include/instance/tcc1.h @@ -3,22 +3,23 @@ * * \brief Instance description for TCC1 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tcc2.h b/atmel-samd/asf4/samd51/include/instance/tcc2.h index eb9af59ac8..31f86e2de5 100644 --- a/atmel-samd/asf4/samd51/include/instance/tcc2.h +++ b/atmel-samd/asf4/samd51/include/instance/tcc2.h @@ -3,22 +3,23 @@ * * \brief Instance description for TCC2 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tcc3.h b/atmel-samd/asf4/samd51/include/instance/tcc3.h index 1ffa0a06c3..f492436f65 100644 --- a/atmel-samd/asf4/samd51/include/instance/tcc3.h +++ b/atmel-samd/asf4/samd51/include/instance/tcc3.h @@ -3,22 +3,23 @@ * * \brief Instance description for TCC3 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/tcc4.h b/atmel-samd/asf4/samd51/include/instance/tcc4.h index 9c12d95ea4..84d55b8c90 100644 --- a/atmel-samd/asf4/samd51/include/instance/tcc4.h +++ b/atmel-samd/asf4/samd51/include/instance/tcc4.h @@ -3,22 +3,23 @@ * * \brief Instance description for TCC4 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/trng.h b/atmel-samd/asf4/samd51/include/instance/trng.h index b320025bc7..86008b962c 100644 --- a/atmel-samd/asf4/samd51/include/instance/trng.h +++ b/atmel-samd/asf4/samd51/include/instance/trng.h @@ -3,22 +3,23 @@ * * \brief Instance description for TRNG * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/usb.h b/atmel-samd/asf4/samd51/include/instance/usb.h index 32a311a21c..9776c79fc7 100644 --- a/atmel-samd/asf4/samd51/include/instance/usb.h +++ b/atmel-samd/asf4/samd51/include/instance/usb.h @@ -3,22 +3,23 @@ * * \brief Instance description for USB * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/instance/wdt.h b/atmel-samd/asf4/samd51/include/instance/wdt.h index 3590a7c375..98a2ca13d7 100644 --- a/atmel-samd/asf4/samd51/include/instance/wdt.h +++ b/atmel-samd/asf4/samd51/include/instance/wdt.h @@ -3,22 +3,23 @@ * * \brief Instance description for WDT * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/pio/samd51g18a.h b/atmel-samd/asf4/samd51/include/pio/samd51g18a.h index 7df83ceb71..109c04ba5d 100644 --- a/atmel-samd/asf4/samd51/include/pio/samd51g18a.h +++ b/atmel-samd/asf4/samd51/include/pio/samd51g18a.h @@ -3,22 +3,23 @@ * * \brief Peripheral I/O description for SAMD51G18A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/pio/samd51g19a.h b/atmel-samd/asf4/samd51/include/pio/samd51g19a.h index 75bbb8ba04..86babdbe79 100644 --- a/atmel-samd/asf4/samd51/include/pio/samd51g19a.h +++ b/atmel-samd/asf4/samd51/include/pio/samd51g19a.h @@ -3,22 +3,23 @@ * * \brief Peripheral I/O description for SAMD51G19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/pio/samd51j18a.h b/atmel-samd/asf4/samd51/include/pio/samd51j18a.h index dd802f85fe..d8fa56d5ba 100644 --- a/atmel-samd/asf4/samd51/include/pio/samd51j18a.h +++ b/atmel-samd/asf4/samd51/include/pio/samd51j18a.h @@ -3,22 +3,23 @@ * * \brief Peripheral I/O description for SAMD51J18A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/pio/samd51j19a.h b/atmel-samd/asf4/samd51/include/pio/samd51j19a.h index 76191476af..d5a76b4e37 100644 --- a/atmel-samd/asf4/samd51/include/pio/samd51j19a.h +++ b/atmel-samd/asf4/samd51/include/pio/samd51j19a.h @@ -3,22 +3,23 @@ * * \brief Peripheral I/O description for SAMD51J19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/pio/samd51j20a.h b/atmel-samd/asf4/samd51/include/pio/samd51j20a.h index 51bedee2fc..59828db2a7 100644 --- a/atmel-samd/asf4/samd51/include/pio/samd51j20a.h +++ b/atmel-samd/asf4/samd51/include/pio/samd51j20a.h @@ -3,22 +3,23 @@ * * \brief Peripheral I/O description for SAMD51J20A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/pio/samd51n19a.h b/atmel-samd/asf4/samd51/include/pio/samd51n19a.h index 6f169eee10..265f482eb5 100644 --- a/atmel-samd/asf4/samd51/include/pio/samd51n19a.h +++ b/atmel-samd/asf4/samd51/include/pio/samd51n19a.h @@ -3,22 +3,23 @@ * * \brief Peripheral I/O description for SAMD51N19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/pio/samd51n20a.h b/atmel-samd/asf4/samd51/include/pio/samd51n20a.h index 8ec9a1ddd7..6f3a1d63c3 100644 --- a/atmel-samd/asf4/samd51/include/pio/samd51n20a.h +++ b/atmel-samd/asf4/samd51/include/pio/samd51n20a.h @@ -3,22 +3,23 @@ * * \brief Peripheral I/O description for SAMD51N20A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/pio/samd51p19a.h b/atmel-samd/asf4/samd51/include/pio/samd51p19a.h index 195771bda4..82cae824d5 100644 --- a/atmel-samd/asf4/samd51/include/pio/samd51p19a.h +++ b/atmel-samd/asf4/samd51/include/pio/samd51p19a.h @@ -3,22 +3,23 @@ * * \brief Peripheral I/O description for SAMD51P19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/pio/samd51p20a.h b/atmel-samd/asf4/samd51/include/pio/samd51p20a.h index 2551b2873b..6e1477e468 100644 --- a/atmel-samd/asf4/samd51/include/pio/samd51p20a.h +++ b/atmel-samd/asf4/samd51/include/pio/samd51p20a.h @@ -3,22 +3,23 @@ * * \brief Peripheral I/O description for SAMD51P20A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/samd51.h b/atmel-samd/asf4/samd51/include/samd51.h index 4869ad9b47..d08ac64cb8 100644 --- a/atmel-samd/asf4/samd51/include/samd51.h +++ b/atmel-samd/asf4/samd51/include/samd51.h @@ -3,22 +3,23 @@ * * \brief Top header file for SAMD51 * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/include/samd51g18a.h b/atmel-samd/asf4/samd51/include/samd51g18a.h index 239f73e94a..3be17b5436 100644 --- a/atmel-samd/asf4/samd51/include/samd51g18a.h +++ b/atmel-samd/asf4/samd51/include/samd51g18a.h @@ -3,22 +3,23 @@ * * \brief Header file for SAMD51G18A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -510,7 +511,7 @@ void SDHC0_Handler ( void ); * \brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -//#define LITTLE_ENDIAN 1 +//#define LITTLE_ENDIAN 1 #define __CM4_REV 1 /*!< Core revision r0p1 */ #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ #define __FPU_PRESENT 1 /*!< FPU present or not */ @@ -738,6 +739,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -863,6 +865,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -1017,6 +1020,7 @@ void SDHC0_Handler ( void ); #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ #define DSU_DID_RESETVALUE _UL_(0x60060008) +#define ADC0_TOUCH_LINES_NUM 22 #define PORT_GROUPS 2 /* ************************************************************************** */ diff --git a/atmel-samd/asf4/samd51/include/samd51g19a.h b/atmel-samd/asf4/samd51/include/samd51g19a.h index ab62fabad8..cc236e8dac 100644 --- a/atmel-samd/asf4/samd51/include/samd51g19a.h +++ b/atmel-samd/asf4/samd51/include/samd51g19a.h @@ -3,22 +3,23 @@ * * \brief Header file for SAMD51G19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -510,7 +511,7 @@ void SDHC0_Handler ( void ); * \brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -//#define LITTLE_ENDIAN 1 +//#define LITTLE_ENDIAN 1 #define __CM4_REV 1 /*!< Core revision r0p1 */ #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ #define __FPU_PRESENT 1 /*!< FPU present or not */ @@ -738,6 +739,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -863,6 +865,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -1017,6 +1020,7 @@ void SDHC0_Handler ( void ); #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ #define DSU_DID_RESETVALUE _UL_(0x60060007) +#define ADC0_TOUCH_LINES_NUM 22 #define PORT_GROUPS 2 /* ************************************************************************** */ diff --git a/atmel-samd/asf4/samd51/include/samd51j18a.h b/atmel-samd/asf4/samd51/include/samd51j18a.h index 0d33551e35..a4ea155966 100644 --- a/atmel-samd/asf4/samd51/include/samd51j18a.h +++ b/atmel-samd/asf4/samd51/include/samd51j18a.h @@ -3,22 +3,23 @@ * * \brief Header file for SAMD51J18A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -528,7 +529,7 @@ void SDHC0_Handler ( void ); * \brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -//#define LITTLE_ENDIAN 1 +//#define LITTLE_ENDIAN 1 #define __CM4_REV 1 /*!< Core revision r0p1 */ #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ #define __FPU_PRESENT 1 /*!< FPU present or not */ @@ -768,6 +769,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -901,6 +903,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -1059,6 +1062,7 @@ void SDHC0_Handler ( void ); #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ #define DSU_DID_RESETVALUE _UL_(0x60060006) +#define ADC0_TOUCH_LINES_NUM 32 #define PORT_GROUPS 2 /* ************************************************************************** */ diff --git a/atmel-samd/asf4/samd51/include/samd51j19a.h b/atmel-samd/asf4/samd51/include/samd51j19a.h index 7748fcd0c7..c7fae83e1d 100644 --- a/atmel-samd/asf4/samd51/include/samd51j19a.h +++ b/atmel-samd/asf4/samd51/include/samd51j19a.h @@ -3,22 +3,23 @@ * * \brief Header file for SAMD51J19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -528,7 +529,7 @@ void SDHC0_Handler ( void ); * \brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -//#define LITTLE_ENDIAN 1 +//#define LITTLE_ENDIAN 1 #define __CM4_REV 1 /*!< Core revision r0p1 */ #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ #define __FPU_PRESENT 1 /*!< FPU present or not */ @@ -768,6 +769,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -901,6 +903,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -1059,6 +1062,7 @@ void SDHC0_Handler ( void ); #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ #define DSU_DID_RESETVALUE _UL_(0x60060005) +#define ADC0_TOUCH_LINES_NUM 32 #define PORT_GROUPS 2 /* ************************************************************************** */ diff --git a/atmel-samd/asf4/samd51/include/samd51j20a.h b/atmel-samd/asf4/samd51/include/samd51j20a.h index 17fcd94667..ea57a41724 100644 --- a/atmel-samd/asf4/samd51/include/samd51j20a.h +++ b/atmel-samd/asf4/samd51/include/samd51j20a.h @@ -3,22 +3,23 @@ * * \brief Header file for SAMD51J20A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -528,7 +529,7 @@ void SDHC0_Handler ( void ); * \brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -//#define LITTLE_ENDIAN 1 +//#define LITTLE_ENDIAN 1 #define __CM4_REV 1 /*!< Core revision r0p1 */ #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ #define __FPU_PRESENT 1 /*!< FPU present or not */ @@ -768,6 +769,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -901,6 +903,7 @@ void SDHC0_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -1059,6 +1062,7 @@ void SDHC0_Handler ( void ); #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ #define DSU_DID_RESETVALUE _UL_(0x60060004) +#define ADC0_TOUCH_LINES_NUM 32 #define PORT_GROUPS 2 /* ************************************************************************** */ diff --git a/atmel-samd/asf4/samd51/include/samd51n19a.h b/atmel-samd/asf4/samd51/include/samd51n19a.h index 0c9220cc93..08d4f12963 100644 --- a/atmel-samd/asf4/samd51/include/samd51n19a.h +++ b/atmel-samd/asf4/samd51/include/samd51n19a.h @@ -3,22 +3,23 @@ * * \brief Header file for SAMD51N19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -550,7 +551,7 @@ void SDHC1_Handler ( void ); * \brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -//#define LITTLE_ENDIAN 1 +//#define LITTLE_ENDIAN 1 #define __CM4_REV 1 /*!< Core revision r0p1 */ #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ #define __FPU_PRESENT 1 /*!< FPU present or not */ @@ -800,6 +801,7 @@ void SDHC1_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -938,6 +940,7 @@ void SDHC1_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -1101,6 +1104,7 @@ void SDHC1_Handler ( void ); #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ #define DSU_DID_RESETVALUE _UL_(0x60060003) +#define ADC0_TOUCH_LINES_NUM 32 #define PORT_GROUPS 3 /* ************************************************************************** */ diff --git a/atmel-samd/asf4/samd51/include/samd51n20a.h b/atmel-samd/asf4/samd51/include/samd51n20a.h index e392a7fb4b..9947b773a0 100644 --- a/atmel-samd/asf4/samd51/include/samd51n20a.h +++ b/atmel-samd/asf4/samd51/include/samd51n20a.h @@ -3,22 +3,23 @@ * * \brief Header file for SAMD51N20A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -550,7 +551,7 @@ void SDHC1_Handler ( void ); * \brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -//#define LITTLE_ENDIAN 1 +//#define LITTLE_ENDIAN 1 #define __CM4_REV 1 /*!< Core revision r0p1 */ #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ #define __FPU_PRESENT 1 /*!< FPU present or not */ @@ -800,6 +801,7 @@ void SDHC1_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -938,6 +940,7 @@ void SDHC1_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -1101,6 +1104,7 @@ void SDHC1_Handler ( void ); #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ #define DSU_DID_RESETVALUE _UL_(0x60060002) +#define ADC0_TOUCH_LINES_NUM 32 #define PORT_GROUPS 3 /* ************************************************************************** */ diff --git a/atmel-samd/asf4/samd51/include/samd51p19a.h b/atmel-samd/asf4/samd51/include/samd51p19a.h index 62c58fd524..97b776c7d2 100644 --- a/atmel-samd/asf4/samd51/include/samd51p19a.h +++ b/atmel-samd/asf4/samd51/include/samd51p19a.h @@ -3,22 +3,23 @@ * * \brief Header file for SAMD51P19A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -550,7 +551,7 @@ void SDHC1_Handler ( void ); * \brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -//#define LITTLE_ENDIAN 1 +//#define LITTLE_ENDIAN 1 #define __CM4_REV 1 /*!< Core revision r0p1 */ #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ #define __FPU_PRESENT 1 /*!< FPU present or not */ @@ -800,6 +801,7 @@ void SDHC1_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -938,6 +940,7 @@ void SDHC1_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -1101,6 +1104,7 @@ void SDHC1_Handler ( void ); #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ #define DSU_DID_RESETVALUE _UL_(0x60060001) +#define ADC0_TOUCH_LINES_NUM 32 #define PORT_GROUPS 4 /* ************************************************************************** */ diff --git a/atmel-samd/asf4/samd51/include/samd51p20a.h b/atmel-samd/asf4/samd51/include/samd51p20a.h index 35bc1a5118..9b19e2aa44 100644 --- a/atmel-samd/asf4/samd51/include/samd51p20a.h +++ b/atmel-samd/asf4/samd51/include/samd51p20a.h @@ -3,22 +3,23 @@ * * \brief Header file for SAMD51P20A * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * @@ -550,7 +551,7 @@ void SDHC1_Handler ( void ); * \brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -//#define LITTLE_ENDIAN 1 +//#define LITTLE_ENDIAN 1 #define __CM4_REV 1 /*!< Core revision r0p1 */ #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ #define __FPU_PRESENT 1 /*!< FPU present or not */ @@ -800,6 +801,7 @@ void SDHC1_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -938,6 +940,7 @@ void SDHC1_Handler ( void ); #define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ #define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ #define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ #define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ #define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ #define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ @@ -1101,6 +1104,7 @@ void SDHC1_Handler ( void ); #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ #define DSU_DID_RESETVALUE _UL_(0x60060000) +#define ADC0_TOUCH_LINES_NUM 32 #define PORT_GROUPS 4 /* ************************************************************************** */ diff --git a/atmel-samd/asf4/samd51/include/system_samd51.h b/atmel-samd/asf4/samd51/include/system_samd51.h index 2f4d2ad583..cfbd2b921b 100644 --- a/atmel-samd/asf4/samd51/include/system_samd51.h +++ b/atmel-samd/asf4/samd51/include/system_samd51.h @@ -3,22 +3,23 @@ * * \brief Low-level initialization functions called upon chip startup * - * Copyright (c) 2017 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2017 Microchip Technology Inc. * * \asf_license_start * * \page License * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * + * + * http://www.apache.org/licenses/LICENSE-2.0 + * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * diff --git a/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h b/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h index 6017864cb2..5213bd843a 100644 --- a/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h +++ b/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h @@ -3,7 +3,7 @@ * * \brief USB Communication Device Class (CDC) protocol definitions * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * Copyright (c) 2015 - 2017 Atmel Corporation. All rights reserved. * * \asf_license_start * @@ -275,8 +275,8 @@ enum cdc_parity { CDC_PAR_NONE = 0, //!< No parity CDC_PAR_ODD = 1, //!< Odd parity CDC_PAR_EVEN = 2, //!< Even parity - CDC_PAR_MARK = 3, //!< Parity forced to 0 (space) - CDC_PAR_SPACE = 4 //!< Parity forced to 1 (mark) + CDC_PAR_MARK = 3, //!< Parity forced to 1 (mark) + CDC_PAR_SPACE = 4 //!< Parity forced to 0 (space) }; //@} @@ -404,4 +404,33 @@ COMPILER_PACK_RESET() //! @} +/** + * \brief Fill a CDC SetLineCoding request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_SetLineCoding_req(struct usb_req *req, uint8_t iface) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_CDC_SET_LINE_CODING; + req->wValue = 0; + req->wIndex = iface; + req->wLength = sizeof(usb_cdc_line_coding_t); +} + +/** + * \brief Fill a CDC SetControlLineState request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + * \param[in] ctrl Control Signal Bitmap + */ +static inline void usb_fill_SetControlLineState_req(struct usb_req *req, uint8_t iface, uint16_t ctrl) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_CDC_SET_CONTROL_LINE_STATE; + req->wValue = ctrl; + req->wIndex = iface; + req->wLength = 0; +} + #endif // _USB_PROTOCOL_CDC_H_ diff --git a/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h b/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h index 68db57af99..9838e40c18 100644 --- a/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h +++ b/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h @@ -3,7 +3,7 @@ * * \brief USB Device Stack Composite Class Descriptor Setting. * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. * * \page License * @@ -127,12 +127,29 @@ #define CONF_HID_GENERIC_IFC_DESC #endif +#if CONF_USB_COMPOSITE_MSC_EN == 1 +#define CONF_MSC_IFC_LEN 23 /* (9 + 7 * 2) */ +#define CONF_MSC_IFC_NUM 1 +#define CONF_USB_COMPOSITE_MSC_BIFCNUM (CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM + 1) +#define CONF_MSC_IFC_DESC \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BIFCNUM, 0x00, 0x02, 0x08, 0x06, 0x50, 0x00) \ + , USB_ENDP_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR, 0x02, CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ, 0), \ + USB_ENDP_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR, 0x02, CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ, 0), +#else +#define CONF_MSC_IFC_LEN 0 +#define CONF_MSC_IFC_NUM 0 +#define CONF_USB_COMPOSITE_MSC_BIFCNUM CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM +#define CONF_MSC_IFC_DESC +#endif + #define CONF_USB_COMPOSITE_TOTAL_LEN \ (USB_CONFIG_DESC_LEN + CONF_CDC_ACM_IFC_LEN + CONF_HID_MOUSE_IFC_LEN + CONF_HID_KEYBOARD_IFC_LEN \ - + CONF_HID_GENERIC_IFC_LEN) + + CONF_HID_GENERIC_IFC_LEN \ + + CONF_MSC_IFC_LEN) #define CONF_USB_COMPOSITE_IFC_NUM \ - (CONF_CDC_ACM_IFC_NUM + CONF_HID_MOUSE_IFC_NUM + CONF_HID_KEYBOARD_IFC_NUM + CONF_HID_GENERIC_IFC_NUM) + (CONF_CDC_ACM_IFC_NUM + CONF_HID_MOUSE_IFC_NUM + CONF_HID_KEYBOARD_IFC_NUM + CONF_HID_GENERIC_IFC_NUM \ + + CONF_MSC_IFC_NUM) #define COMPOSITE_DEV_DESC \ USB_DEV_DESC_BYTES(CONF_USB_COMPOSITE_BCDUSB, \ @@ -160,7 +177,8 @@ CONF_CDC_ACM_IFC_DESC \ CONF_HID_MOUSE_IFC_DESC \ CONF_HID_KEYBOARD_IFC_DESC \ - CONF_HID_GENERIC_IFC_DESC + CONF_HID_GENERIC_IFC_DESC \ + CONF_MSC_IFC_DESC /** USB Device descriptors and configuration descriptors */ #define COMPOSITE_DESCES_LS_FS \ diff --git a/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h b/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h index 1b29802b03..6b18e443dc 100644 --- a/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h +++ b/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h @@ -19,6 +19,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_bmaxpksz0 #ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 #define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 @@ -117,7 +118,7 @@ // CDC ACM Support // usb_composite_cdc_acm_support #ifndef CONF_USB_COMPOSITE_CDC_ACM_EN -#define CONF_USB_COMPOSITE_CDC_ACM_EN 1 +#define CONF_USB_COMPOSITE_CDC_ACM_EN 0 #endif // CDC ACM Comm Interrupt IN Endpoint Address @@ -128,6 +129,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_cdc_acm_epaddr #ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR #define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 @@ -138,6 +142,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_cdc_acm_comm_int_maxpksz #ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ #define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 @@ -151,6 +156,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_cdc_acm_data_bulkin_epaddr #ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR #define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 @@ -161,6 +169,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_cdc_acm_data_builin_maxpksz #ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ #define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 @@ -174,6 +183,9 @@ // <0x05=> EndpointAddress = 0x05 // <0x06=> EndpointAddress = 0x06 // <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + // usb_composite_cdc_acm_data_bulkout_epaddr #ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR #define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 @@ -184,10 +196,21 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_cdc_acm_data_buckout_maxpksz #ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ #define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 #endif + +// CDC ACM Echo Demo generation +// conf_usb_composite_cdc_echo_demo +// Invoke cdcdf_acm_demo_init(buf[wMaxPacketSize]) to enable the echo demo. +// Buf is packet buffer for data receive and echo back. +// The buffer is 4 byte aligned to support DMA. +#ifndef CONF_USB_COMPOSITE_CDC_ECHO_DEMO +#define CONF_USB_COMPOSITE_CDC_ECHO_DEMO 0 +#endif + // // HID Mouse Support @@ -204,6 +227,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_hid_mouse_intin_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR @@ -215,12 +241,21 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_hid_mouse_intin_maxpksz // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ #define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 #endif +// HID Mouse Move Demo generation +// conf_usb_composite_hid_mouse_demo +// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// Button1 and button3 are the pins used for mouse moving left and right. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_DEMO +#define CONF_USB_COMPOSITE_HID_MOUSE_DEMO 0 +#endif + // // HID Keyboard Support @@ -237,6 +272,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_hid_keyboard_intin_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR @@ -248,6 +286,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_hid_keyboard_intin_maxpksz // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ @@ -262,6 +301,9 @@ // <0x05=> EndpointAddress = 0x05 // <0x06=> EndpointAddress = 0x06 // <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + // usb_composite_hid_keyboard_intout_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR @@ -273,12 +315,21 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_hid_keyboard_intout_maxpksz // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ #define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 #endif +// HID Keyboard Caps Lock Demo generation +// conf_usb_composite_hid_keyboard_demo +// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// Buffon2 is the pin used for keyboard CAPS LOCK simulation. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO +#define CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO 0 +#endif + // // HID Generic Support @@ -306,6 +357,9 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + // usb_composite_hid_generic_intin_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR @@ -317,6 +371,7 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes + // usb_composite_hid_generic_intin_maxpksz // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ @@ -331,6 +386,9 @@ // <0x05=> EndpointAddress = 0x05 // <0x06=> EndpointAddress = 0x06 // <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + // usb_composite_hid_generic_intout_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. #ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR @@ -350,6 +408,196 @@ // +// MSC Support +// usb_composite_msc_support +#ifndef CONF_USB_COMPOSITE_MSC_EN +#define CONF_USB_COMPOSITE_MSC_EN 0 +#endif + +// MSC BULK Endpoints wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_msc_bulk_maxpksz +#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ +#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ 0x40 +#endif + +// MSC BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_msc_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR 0x86 +#endif + +// MSC BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_msc_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR 0x4 +#endif + +// Enable Demo code for Disk LUN handling +// usb_composite_msc_demo_en +#ifndef CONF_USB_COMPOSITE_MSC_LUN_DEMO +#define CONF_USB_COMPOSITE_MSC_LUN_DEMO 1 +#endif + +// Disk access cache/buffer of sectors if non-RAM disk enabled <1-64> +// conf_usb_msc_lun_buf_sectors +#ifndef CONF_USB_MSC_LUN_BUF_SECTORS +#define CONF_USB_MSC_LUN_BUF_SECTORS 4 +#endif + +// Enable Demo for RAM Disk +// conf_usb_msc_lun0_enable +#ifndef CONF_USB_MSC_LUN0_ENABLE +#define CONF_USB_MSC_LUN0_ENABLE 1 +#endif + +#ifndef CONF_USB_MSC_LUN0_TYPE +#define CONF_USB_MSC_LUN0_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun0_rmb +#ifndef CONF_USB_MSC_LUN0_RMB +#define CONF_USB_MSC_LUN0_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN0_ISO +#define CONF_USB_MSC_LUN0_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ECMA +#define CONF_USB_MSC_LUN0_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ANSI +#define CONF_USB_MSC_LUN0_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_REPO +#define CONF_USB_MSC_LUN0_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN0_FACTORY +#define CONF_USB_MSC_LUN0_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT +#define CONF_USB_MSC_LUN0_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT_VERSION +#define CONF_USB_MSC_LUN0_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <1-65535> +// Windows will not show disk less than 20K, so 22K is used to reserve more RAM for app +// conf_usb_msc_lun0_capacity + +#ifndef CONF_USB_MSC_LUN0_CAPACITY +#define CONF_USB_MSC_LUN0_CAPACITY 0x16 +#endif + +#ifndef CONF_USB_MSC_LUN0_BLOCK_SIZE +#define CONF_USB_MSC_LUN0_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for SD/MMC Disk +// SD/MMC stack must be added before enable SD/MMC demo +// SD/MMC insert/eject not supported by this simple demo +// conf_usb_msc_lun1_enable +#ifndef CONF_USB_MSC_LUN1_ENABLE +#define CONF_USB_MSC_LUN1_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN1_TYPE +#define CONF_USB_MSC_LUN1_TYPE 0x00 +#endif + +// The disk is removable +// SD/MMC stack must be added before enable SD/MMC demo +// SD/MMC insert/eject not supported by this simple demo +// conf_usb_msc_lun1_rmb +#ifndef CONF_USB_MSC_LUN1_RMB +#define CONF_USB_MSC_LUN1_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN1_ISO +#define CONF_USB_MSC_LUN1_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ECMA +#define CONF_USB_MSC_LUN1_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ANSI +#define CONF_USB_MSC_LUN1_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_REPO +#define CONF_USB_MSC_LUN1_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN1_FACTORY +#define CONF_USB_MSC_LUN1_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT +#define CONF_USB_MSC_LUN1_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT_VERSION +#define CONF_USB_MSC_LUN1_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_CAPACITY +#define CONF_USB_MSC_LUN1_CAPACITY 0x16 +#endif + +#ifndef CONF_USB_MSC_LUN1_BLOCK_SIZE +#define CONF_USB_MSC_LUN1_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) +#endif + +// + +// +// + // <<< end of configuration section >>> #endif // USBD_COMPOSITE_CONFIG_H diff --git a/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.c b/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.c new file mode 100644 index 0000000000..b398ba6090 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.c @@ -0,0 +1,754 @@ +/** + * \file + * + * \brief USB Device Stack MSC Function Implementation. + * + * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "mscdf.h" +#include + +#define MSCDF_VERSION 0x00000001u + +#define ERR_RPT_ZLP 0 /* Uses ZLP on IN error case */ + +/** MSC Class Transfer Stage Type */ +enum mscdf_xfer_stage_type { MSCDF_CMD_STAGE, MSCDF_DATA_STAGE, MSCDF_STATUS_STAGE }; + +/** USB Device MSC Function Specific Data */ +struct mscdf_func_data { + /** MSC Device Interface information */ + uint8_t func_iface; + /** MSC Device IN Endpoint */ + uint8_t func_ep_in; + /** MSC Device OUT Endpoint */ + uint8_t func_ep_out; + /** MSC Device Max LUN */ + uint8_t func_max_lun; + /** MSC Transfer Block Address */ + uint8_t *xfer_blk_addr; + /** MSC Transfer Block Size */ + uint32_t xfer_blk_size; + /** MSC Transfer Total Bytes */ + uint32_t xfer_tot_bytes; + /** MSC Transfer Stage */ + enum mscdf_xfer_stage_type xfer_stage; + /** MSC Transfer Busy Flag */ + bool xfer_busy; + /** MSC Device Enable Flag */ + bool enabled; +}; + +static struct usbdf_driver _mscdf; +static struct mscdf_func_data _mscdf_funcd; + +/* If callbacks are not registered: + * - Return default inquiry information + * - Return NOT FOUND for all other CBW + */ +static mscdf_inquiry_disk_t mscdf_inquiry_disk = NULL; +static mscdf_get_disk_capacity_t mscdf_get_disk_capacity = NULL; +static mscdf_eject_disk_t mscdf_eject_disk = NULL; +static mscdf_start_read_disk_t mscdf_read_disk = NULL; +static mscdf_start_write_disk_t mscdf_write_disk = NULL; +static mscdf_test_disk_ready_t mscdf_test_disk_ready = NULL; +static mscdf_xfer_blocks_done_t mscdf_xfer_blocks_done = NULL; + +COMPILER_ALIGNED(4) +static struct scsi_inquiry_data _inquiry_default = { + 0x00, /* Peripheral Qual / Peripheral Dev Type */ + SCSI_INQ_RMB, /* Flags 1 */ + 0x00, /* Version */ + 0x01, /* Flags 3 */ + 31, /* Additional Length (n-4) */ + 0x00, /* Flags 5 */ + 0x00, /* Flags 6 */ + 0x00, /* Flags 7 */ + {0, 0, 0, 0, 0, 0, 0, 0}, /* VID[8] */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* PID[16] */ + {0, 0, 0, 0} /* PREV[4] */ +}; + +COMPILER_ALIGNED(4) +static struct usb_msc_cbw mscdf_cbw; + +COMPILER_ALIGNED(4) +static struct usb_msc_csw mscdf_csw = {USB_CSW_SIGNATURE, 0, 0, 0}; + +COMPILER_ALIGNED(4) +static struct scsi_request_sense_data mscdf_sense_data + = {SCSI_SENSE_CURRENT, 0x00, 0x00, {0x00, 0x00, 0x00, 0x00}, 0x0A}; + +/** + * \brief USB MSC wait Command Block + */ +static bool mscdf_wait_cbw(void) +{ + _mscdf_funcd.xfer_stage = MSCDF_CMD_STAGE; + return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_out, (uint8_t *)&mscdf_cbw, 31, false); +} + +/** + * \brief USB MSC Send Command Status + */ +static bool mscdf_send_csw(void) +{ + _mscdf_funcd.xfer_stage = MSCDF_STATUS_STAGE; + return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_in, (uint8_t *)&mscdf_csw, sizeof(struct usb_msc_csw), false); +} + +#if ERR_RPT_ZLP +/** + * \brief USB MSC Send ZLP data + */ +static bool mscdf_send_zlp(void) +{ + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_in, (uint8_t *)&mscdf_csw, 0, true); +} +#define mscdf_terminate_in() mscdf_send_zlp() +#else +/** + * \brief USB MSC Halt IN endpoint + */ +static bool mscdf_halt_in(void) +{ + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + return ERR_NONE == usb_d_ep_halt(_mscdf_funcd.func_ep_in, USB_EP_HALT_SET); +} +#define mscdf_terminate_in() mscdf_halt_in() +#endif + +/** + * \brief USB MSC Request Sense + * \param[in] err_codes Error code + */ +static void mscdf_request_sense(int32_t err_codes) +{ + switch (err_codes) { + case ERR_NOT_FOUND: + mscdf_sense_data.sense_flag_key = SCSI_SK_NOT_READY; + mscdf_sense_data.AddSense = BE16(SCSI_ASC_MEDIUM_NOT_PRESENT); + break; + + case ERR_BUSY: + mscdf_sense_data.sense_flag_key = SCSI_SK_UNIT_ATTENTION; + mscdf_sense_data.AddSense = BE16(SCSI_ASC_NOT_READY_TO_READY_CHANGE); + break; + + case ERR_DENIED: + mscdf_sense_data.sense_flag_key = SCSI_SK_DATA_PROTECT; + mscdf_sense_data.AddSense = BE16(SCSI_ASC_WRITE_PROTECTED); + break; + + default: + mscdf_sense_data.sense_flag_key = SCSI_SK_ILLEGAL_REQUEST; + mscdf_sense_data.AddSense = BE16(SCSI_ASC_INVALID_COMMAND_OPERATION_CODE); + break; + } +} + +/** + * \brief USB MSC Stack invalid command process + */ +static bool mscdf_invalid_cmd(void) +{ + struct usb_msc_cbw *pcbw = &mscdf_cbw; + struct usb_msc_csw *pcsw = &mscdf_csw; + + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + + mscdf_request_sense(ERR_UNSUPPORTED_OP); + + if ((pcbw->bmCBWFlags & USB_EP_DIR_IN) && pcsw->dCSWDataResidue) { + return mscdf_terminate_in(); + } else { + return mscdf_send_csw(); + } +} + +/** + * \brief USB MSC Function Read / Write Data + * \param[in] count the amount of bytes has been transferred + * \return Operation status. + */ +static bool mscdf_read_write(uint32_t count) +{ + struct usb_msc_cbw *pcbw = &mscdf_cbw; + struct usb_msc_csw *pcsw = &mscdf_csw; + int32_t ret = ERR_UNSUPPORTED_OP; + uint32_t address, nblocks; + uint8_t ep; + + if (_mscdf_funcd.xfer_stage == MSCDF_CMD_STAGE) { + address = (uint32_t)(pcbw->CDB[2] << 24) + (uint32_t)(pcbw->CDB[3] << 16) + (uint32_t)(pcbw->CDB[4] << 8) + + pcbw->CDB[5]; + nblocks = (uint32_t)(pcbw->CDB[7] << 8) + pcbw->CDB[8]; + if (pcbw->CDB[0] == SBC_READ10) { + if (NULL != mscdf_read_disk) { + ret = mscdf_read_disk(pcbw->bCBWLUN, address, nblocks); + } else { + ret = ERR_NOT_FOUND; + } + } else if (pcbw->CDB[0] == SBC_WRITE10) { + if (NULL != mscdf_write_disk) { + ret = mscdf_write_disk(pcbw->bCBWLUN, address, nblocks); + } else { + ret = ERR_NOT_FOUND; + } + } + if (ERR_NONE == ret) { + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + return false; + } + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ret); + return mscdf_terminate_in(); + + } else if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { + if (count == 0) { + return mscdf_send_csw(); + } + if (pcsw->dCSWDataResidue < count || _mscdf_funcd.xfer_tot_bytes < count) { + return true; + } + + pcsw->dCSWDataResidue -= count; + _mscdf_funcd.xfer_tot_bytes -= count; + + if (_mscdf_funcd.xfer_tot_bytes == 0) { + _mscdf_funcd.xfer_busy = false; + if (NULL != mscdf_xfer_blocks_done) { + mscdf_xfer_blocks_done(pcbw->bCBWLUN); + } + if (pcsw->dCSWDataResidue == 0 && pcbw->CDB[0] == SBC_READ10) { + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + return mscdf_send_csw(); + } else { + return false; + } + } else { + _mscdf_funcd.xfer_blk_addr += count; + if (pcbw->CDB[0] == SBC_READ10) { + ep = _mscdf_funcd.func_ep_in; + } else { + ep = _mscdf_funcd.func_ep_out; + } + return usbdc_xfer(ep, _mscdf_funcd.xfer_blk_addr, _mscdf_funcd.xfer_tot_bytes, false); + } + } else { + return true; + } +} + +/** + * \brief Callback invoked when bulk IN data received + * \param[in] ep Endpoint number + * \param[in] rc transfer return status + * \param[in] count the amount of bytes has been transferred + * \return Operation status. + */ +static bool mscdf_cb_ep_bulk_in(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) +{ + struct usb_msc_cbw *pcbw = &mscdf_cbw; + (void)ep; + (void)rc; + + if (rc == USB_XFER_UNHALT) { + if (_mscdf_funcd.xfer_stage != MSCDF_CMD_STAGE) { + return mscdf_send_csw(); + } + } + + if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { + if (pcbw->CDB[0] == SBC_READ10) { + return mscdf_read_write(count); + } else { + return mscdf_send_csw(); + } + } else if (_mscdf_funcd.xfer_stage == MSCDF_STATUS_STAGE) { + return mscdf_wait_cbw(); + } else { + return true; + } +} + +/** + * \brief Callback invoked when bulk OUT data received + * \param[in] ep Endpoint number + * \param[in] rc transfer return status + * \param[in] count the amount of bytes has been transferred + * \return Operation status. + */ +static bool mscdf_cb_ep_bulk_out(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) +{ + struct usb_msc_cbw *pcbw = &mscdf_cbw; + struct usb_msc_csw *pcsw = &mscdf_csw; + uint8_t * pbuf = NULL; + int32_t ret; + + (void)ep; + if (rc == USB_XFER_UNHALT) { + return mscdf_wait_cbw(); + } + + if (_mscdf_funcd.xfer_stage == MSCDF_CMD_STAGE) { + if (pcbw->dCBWSignature == USB_CBW_SIGNATURE) { + pcsw->dCSWTag = pcbw->dCBWTag; + pcsw->dCSWDataResidue = pcbw->dCBWDataTransferLength; + + switch (pcbw->CDB[0]) { + case SPC_INQUIRY: + if (NULL != mscdf_inquiry_disk) { + pbuf = mscdf_inquiry_disk(pcbw->bCBWLUN); + } + if (NULL == pbuf) { + pbuf = (uint8_t *)&_inquiry_default; + } + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + return usbdc_xfer(_mscdf_funcd.func_ep_in, pbuf, 36, false); + + case SBC_READ_CAPACITY10: + if (NULL != mscdf_get_disk_capacity) { + pbuf = mscdf_get_disk_capacity(pcbw->bCBWLUN); + } + if (NULL != pbuf) { + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + _mscdf_funcd.xfer_blk_size + = (uint32_t)(pbuf[4] << 24) + (uint32_t)(pbuf[5] << 16) + (uint32_t)(pbuf[6] << 8) + pbuf[7]; + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + return usbdc_xfer(_mscdf_funcd.func_ep_in, pbuf, 8, false); + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ERR_NOT_FOUND); + return mscdf_terminate_in(); + } + + case SBC_READ10: + case SBC_WRITE10: + return mscdf_read_write(count); + + case SPC_PREVENT_ALLOW_MEDIUM_REMOVAL: + if (0x00 == pcbw->CDB[4]) { + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + return mscdf_send_csw(); + } + break; + + case SBC_START_STOP_UNIT: + if (0x02 == pcbw->CDB[4]) { + if (NULL != mscdf_eject_disk) { + ret = mscdf_eject_disk(pcbw->bCBWLUN); + if (ERR_NONE == ret) { + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ret); + } + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ERR_NOT_FOUND); + } + return mscdf_send_csw(); + } + break; + + case SPC_REQUEST_SENSE: + _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + return usbdc_xfer(_mscdf_funcd.func_ep_in, + (uint8_t *)&mscdf_sense_data, + sizeof(struct scsi_request_sense_data), + false); + + case SPC_TEST_UNIT_READY: + if (NULL != mscdf_test_disk_ready) { + ret = mscdf_test_disk_ready(pcbw->bCBWLUN); + if (ERR_NONE == ret) { + pcsw->bCSWStatus = USB_CSW_STATUS_PASS; + pcsw->dCSWDataResidue = 0; + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ret); + } + } else { + pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; + mscdf_request_sense(ERR_NOT_FOUND); + } + return mscdf_send_csw(); + + default: + break; + } + return mscdf_invalid_cmd(); + } else { + return true; + } + } else if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { + return mscdf_read_write(count); + } else { + return true; + } +} + +/** + * \brief Enable MSC Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t mscdf_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct mscdf_func_data *func_data = (struct mscdf_func_data *)(drv->func_data); + + usb_ep_desc_t ep_desc; + usb_iface_desc_t ifc_desc; + uint8_t * ifc, *ep; + + ifc = desc->sod; + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if (MSC_CLASS == ifc_desc.bInterfaceClass) { + if (func_data->func_iface == ifc_desc.bInterfaceNumber) { /* Initialized */ + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface != 0xFF) { /* Occupied */ + return ERR_NO_RESOURCE; + } else { + func_data->func_iface = ifc_desc.bInterfaceNumber; + } + } else { /* Not supported by this function driver */ + return ERR_NOT_FOUND; + } + + /* Install endpoints */ + ep = usb_find_desc(ifc, desc->eod, USB_DT_ENDPOINT); + while (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in); + usb_d_ep_register_callback(func_data->func_ep_in, USB_D_EP_CB_XFER, (FUNC_PTR)mscdf_cb_ep_bulk_in); + } else { + func_data->func_ep_out = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_out); + usb_d_ep_register_callback(func_data->func_ep_out, USB_D_EP_CB_XFER, (FUNC_PTR)mscdf_cb_ep_bulk_out); + } + desc->sod = ep; + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + } + // Installed + _mscdf_funcd.enabled = true; + return mscdf_wait_cbw(); +} + +/** + * \brief Disable MSC Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t mscdf_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct mscdf_func_data *func_data = (struct mscdf_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + // Check interface + if (ifc_desc.bInterfaceClass != MSC_CLASS) { + return ERR_NOT_FOUND; + } + } + + if (func_data->func_iface != 0xFF) { + func_data->func_iface = 0xFF; + } + + if (func_data->func_ep_in != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in); + func_data->func_ep_in = 0xFF; + } + + if (func_data->func_ep_out != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_out); + func_data->func_ep_out = 0xFF; + } + + func_data->xfer_stage = MSCDF_CMD_STAGE; + func_data->xfer_busy = false; + func_data->enabled = false; + + return ERR_NONE; +} + +/** + * \brief MSC Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t mscdf_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return mscdf_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return mscdf_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the MSC class set request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t mscdf_set_req(uint8_t ep, struct usb_req *req) +{ + (void)ep; + switch (req->bRequest) { + case USB_REQ_MSC_BULK_RESET: + _mscdf_funcd.xfer_stage = MSCDF_CMD_STAGE; + usb_d_ep_halt(_mscdf_funcd.func_ep_in, USB_EP_HALT_SET); + usb_d_ep_halt(_mscdf_funcd.func_ep_out, USB_EP_HALT_SET); + return usbdc_xfer(0, NULL, 0, 0); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the MSC class get request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \param[in] stage USB control transfer stages. + * \return Operation status. + */ +static int32_t mscdf_get_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + uint16_t len = req->wLength; + + if (USB_DATA_STAGE == stage) { + return ERR_NONE; + } + + switch (req->bRequest) { + case USB_REQ_MSC_GET_MAX_LUN: + return usbdc_xfer(ep, &_mscdf_funcd.func_max_lun, len, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the MSC class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \param[in] stage USB control transfer stages. + * \return Operation status. + */ +static int32_t mscdf_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { /* class request */ + return ERR_NOT_FOUND; + } + if (req->wIndex == _mscdf_funcd.func_iface) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return mscdf_get_req(ep, req, stage); + } else { + return mscdf_set_req(ep, req); + } + } else { + return ERR_NOT_FOUND; + } +} + +/** USB Device MSC Handler Struct */ +static struct usbdc_handler mscdf_req_h = {NULL, (FUNC_PTR)mscdf_req}; + +/** + * \brief Initialize the USB MSC Function Driver + */ +int32_t mscdf_init(uint8_t max_lun) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _mscdf.ctrl = mscdf_ctrl; + _mscdf.func_data = &_mscdf_funcd; + _mscdf_funcd.func_max_lun = max_lun; + + usbdc_register_function(&_mscdf); + usbdc_register_handler(USBDC_HDL_REQ, &mscdf_req_h); + return ERR_NONE; +} + +/** + * \brief De-initialize the USB MSC Function Driver + */ +int32_t mscdf_deinit(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _mscdf.ctrl = NULL; + _mscdf.func_data = NULL; + + usbdc_unregister_function(&_mscdf); + usbdc_unregister_handler(USBDC_HDL_REQ, &mscdf_req_h); + return ERR_NONE; +} + +/** + * \brief USB MSC Function Register Callback + */ +int32_t mscdf_register_callback(enum mscdf_cb_type cb_type, FUNC_PTR func) +{ + switch (cb_type) { + case MSCDF_CB_INQUIRY_DISK: + mscdf_inquiry_disk = (mscdf_inquiry_disk_t)func; + break; + case MSCDF_CB_GET_DISK_CAPACITY: + mscdf_get_disk_capacity = (mscdf_get_disk_capacity_t)func; + break; + case MSCDF_CB_EJECT_DISK: + mscdf_eject_disk = (mscdf_eject_disk_t)func; + break; + case MSCDF_CB_START_READ_DISK: + mscdf_read_disk = (mscdf_start_read_disk_t)func; + break; + case MSCDF_CB_START_WRITE_DISK: + mscdf_write_disk = (mscdf_start_write_disk_t)func; + break; + case MSCDF_CB_TEST_DISK_READY: + mscdf_test_disk_ready = (mscdf_test_disk_ready_t)func; + break; + case MSCDF_CB_XFER_BLOCKS_DONE: + mscdf_xfer_blocks_done = (mscdf_xfer_blocks_done_t)func; + break; + default: + return ERR_INVALID_ARG; + } + return ERR_NONE; +} + +/** + * \brief Check whether MSC Function is enabled + */ +bool mscdf_is_enabled(void) +{ + return _mscdf_funcd.enabled; +} + +/** + * \brief Process the transfer between USB and Memory. + * + * Routine called by the main loop + */ +int32_t mscdf_xfer_blocks(bool rd, uint8_t *blk_addr, uint32_t blk_cnt) +{ + uint8_t ep; + + if (false == mscdf_is_enabled()) { + return ERR_DENIED; + } else if (true == _mscdf_funcd.xfer_busy) { + return ERR_BUSY; + } else { + _mscdf_funcd.xfer_blk_addr = blk_addr; + _mscdf_funcd.xfer_tot_bytes = _mscdf_funcd.xfer_blk_size * blk_cnt; + if (0 == _mscdf_funcd.xfer_tot_bytes) { + if (false == rd) { + /* For write command, this means no need for more data to receive. + * All the data have been written into disk. + */ + mscdf_csw.bCSWStatus = USB_CSW_STATUS_PASS; + return mscdf_send_csw(); + } else { + return ERR_INVALID_ARG; + } + } else { + if (NULL == blk_addr) { + return ERR_INVALID_ARG; + } + if (true == rd) { + ep = _mscdf_funcd.func_ep_in; + } else { + ep = _mscdf_funcd.func_ep_out; + } + _mscdf_funcd.xfer_busy = true; + usbdc_xfer(ep, blk_addr, _mscdf_funcd.xfer_tot_bytes, false); + return ERR_NONE; + } + } +} + +/** + * \brief Return version + */ +uint32_t mscdf_get_version(void) +{ + return MSCDF_VERSION; +} diff --git a/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.h b/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.h new file mode 100644 index 0000000000..5847a2604b --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief USB Device Stack MSC Function Definition. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_MSC_H_ +#define USBDF_MSC_H_ + +#include "usbdc.h" +#include "usb_protocol_msc.h" +#include "spc_protocol.h" +#include "sbc_protocol.h" + +/** MSC Class Callback Type */ +enum mscdf_cb_type { + MSCDF_CB_INQUIRY_DISK, + MSCDF_CB_GET_DISK_CAPACITY, + MSCDF_CB_START_READ_DISK, + MSCDF_CB_START_WRITE_DISK, + MSCDF_CB_EJECT_DISK, + MSCDF_CB_TEST_DISK_READY, + MSCDF_CB_XFER_BLOCKS_DONE +}; + +/** MSC Inquiry Disk Callback. */ +typedef uint8_t *(*mscdf_inquiry_disk_t)(uint8_t); + +/** MSC Get Disk Capacity Callback. */ +typedef uint8_t *(*mscdf_get_disk_capacity_t)(uint8_t); + +/** MSC Read Data From Disk Callback. */ +typedef int32_t (*mscdf_start_read_disk_t)(uint8_t, uint32_t, uint32_t); + +/** MSC Write Data To Disk Callback. */ +typedef int32_t (*mscdf_start_write_disk_t)(uint8_t, uint32_t, uint32_t); + +/** MSC Eject Disk Callback. */ +typedef int32_t (*mscdf_eject_disk_t)(uint8_t); + +/** MSC Test Disk Ready Callback. */ +typedef int32_t (*mscdf_test_disk_ready_t)(uint8_t); + +/** MSC Tansfer Block Done Callback. */ +typedef int32_t (*mscdf_xfer_blocks_done_t)(uint8_t); + +/** + * \brief Initialize the USB MSC Function Driver + * \param[in] max_lun max logic unit support + * \return Operation status. + */ +int32_t mscdf_init(uint8_t max_lun); + +/** + * \brief Deinitialize the USB MSC Function Driver + * \return Operation status. + */ +int32_t mscdf_deinit(void); + +/** + * \brief USB MSC Function Register Callback + * \param[in] cb_type Callback type of MSC Function + * \param[in] func Pointer to callback function + * \return Operation status. + */ +int32_t mscdf_register_callback(enum mscdf_cb_type cb_type, FUNC_PTR func); + +/** + * \brief Check whether MSC Function is enabled + * \return Operation status. + * \return true MSC Function is enabled + * \return false MSC Function is disabled + */ +bool mscdf_is_enabled(void); + +/** + * \brief USB MSC multi-blocks data transfer between USB and Memory. + * \param[in] rd true read disk command, false write disk command. + * \param[in] blk_addr transfer block address. + * \param[in] blk_cnt transfer block count. It is regarded as disk + * writing done when input blk_cnt as zero. + * \return Operation status. + */ +int32_t mscdf_xfer_blocks(bool rd, uint8_t *blk_addr, uint32_t blk_cnt); + +/** + * \brief Return version + */ +uint32_t mscdf_get_version(void); + +#endif /* USBDF_MSC_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/device/usbdc.c b/atmel-samd/asf4/samd51/usb/device/usbdc.c index f5243cad03..c9645541dc 100644 --- a/atmel-samd/asf4/samd51/usb/device/usbdc.c +++ b/atmel-samd/asf4/samd51/usb/device/usbdc.c @@ -262,6 +262,7 @@ static bool usbdc_clear_ftr_req(const uint8_t ep, const struct usb_req *req) return false; } usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_CLR); + usbdc_xfer(ep, NULL, 0, true); return true; default: return false; @@ -285,6 +286,7 @@ static bool usbdc_set_ftr_req(const uint8_t ep, const struct usb_req *req) return false; } usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_SET); + usbdc_xfer(ep, NULL, 0, true); return true; default: return false; diff --git a/atmel-samd/asf4/samd51/usb_start.c b/atmel-samd/asf4/samd51/usb_start.c index 1ccfaafb6b..683392806a 100644 --- a/atmel-samd/asf4/samd51/usb_start.c +++ b/atmel-samd/asf4/samd51/usb_start.c @@ -8,6 +8,8 @@ #include "atmel_start.h" #include "usb_start.h" +#define CONF_USB_MSC_MAX_LUN 0 + static uint8_t multi_desc_bytes[] = { /* Device descriptors and Configuration descriptors list. */ COMPOSITE_DESCES_LS_FS, @@ -18,29 +20,59 @@ static struct usbd_descriptors multi_desc = {multi_desc_bytes, multi_desc_bytes /** Ctrl endpoint buffer */ static uint8_t ctrl_buffer[64]; -/** - * \brief Composite Init - */ void composite_device_init(void) { /* usb stack init */ usbdc_init(ctrl_buffer); - /* usbdc_register_funcion inside */ +/* usbdc_register_funcion inside */ +#if CONF_USB_COMPOSITE_CDC_ACM_EN + cdcdf_acm_init(); +#endif +#if CONF_USB_COMPOSITE_HID_MOUSE_EN + hiddf_mouse_init(); +#endif +#if CONF_USB_COMPOSITE_HID_KEYBOARD_EN + hiddf_keyboard_init(); +#endif +#if CONF_USB_COMPOSITE_MSC_EN + mscdf_init(CONF_USB_MSC_MAX_LUN); +#endif +} +void composite_device_start(void) +{ usbdc_start(&multi_desc); usbdc_attach(); } -/** - * Example of using Composite Function. - * \note - * In this example, we will use a PC as a USB host: - * - Connect the DEBUG USB on XPLAINED board to PC for program download. - * - Connect the TARGET USB on XPLAINED board to PC for running program. - */ void composite_device_example(void) { + + /* Initialize */ + /* It's done with system init ... */ + + /* Before start do function related initializations */ + /* Add your code here ... */ + + /* Start device */ + composite_device_start(); + + /* Main loop */ + while (1) { + if (cdcdf_acm_is_enabled()) { + /* CDC ACM process*/ + } + if (hiddf_mouse_is_enabled()) { + /* HID Mouse process */ + } + if (hiddf_keyboard_is_enabled()) { + /* HID Keyboard process */ + }; + if (mscdf_is_enabled()) { + /* MSC process */ + } + } } void usb_init(void) diff --git a/atmel-samd/asf4/samd51/usb_start.h b/atmel-samd/asf4/samd51/usb_start.h index 9695f7ed78..912bf289c4 100644 --- a/atmel-samd/asf4/samd51/usb_start.h +++ b/atmel-samd/asf4/samd51/usb_start.h @@ -16,9 +16,24 @@ extern "C" { #include "hiddf_mouse.h" #include "hiddf_keyboard.h" #include "hiddf_generic.h" +#include "mscdf.h" #include "composite_desc.h" +/** + * \brief Initialize device and attach functions + */ void composite_device_init(void); +/** + * \brief Start the device + */ +void composite_device_start(void); +/** + * Example of using Composite Function. + * \note + * In this example, we will use a PC as a USB host: + * - Connect the DEBUG USB on XPLAINED board to PC for program download. + * - Connect the TARGET USB on XPLAINED board to PC for running program. + */ void composite_device_example(void); /** diff --git a/atmel-samd/boards/metro_m4_express/mpconfigboard.mk b/atmel-samd/boards/metro_m4_express/mpconfigboard.mk index 24557e3e09..fd299c7f90 100644 --- a/atmel-samd/boards/metro_m4_express/mpconfigboard.mk +++ b/atmel-samd/boards/metro_m4_express/mpconfigboard.mk @@ -1,4 +1,4 @@ -LD_FILE = boards/samd51x20-external-flash.ld +LD_FILE = boards/samd51x20-bootloader-external-flash.ld USB_VID = 0x239A USB_PID = 0x8015 diff --git a/atmel-samd/supervisor/serial.c b/atmel-samd/supervisor/serial.c index 40c0f5212f..67f06baa4f 100644 --- a/atmel-samd/supervisor/serial.c +++ b/atmel-samd/supervisor/serial.c @@ -45,6 +45,8 @@ // } // } +// SAMD51 addresses: 0x008061FC, 0x00806010, 0x00806014, 0x00806018 + void serial_init(void) { init_usb(); } diff --git a/atmel-samd/tools/samd51.json b/atmel-samd/tools/samd51.json index 5fe35c0730..dee0685021 100644 --- a/atmel-samd/tools/samd51.json +++ b/atmel-samd/tools/samd51.json @@ -1 +1 @@ -{"jsonForm":"=1","formatVersion":2,"board":{"identifier":"CustomBoard","device":"SAMD51G19A-MF"},"identifier":"","name":"My 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(XOSC1)","gclk_arch_gen_7_runstdby":false,"gclk_gen_7_div_sel":false,"gclk_arch_gen_7_oe":false,"gclk_arch_gen_7_oov":false,"gclk_arch_gen_7_idc":false,"gclk_arch_gen_7_enable":false,"gclk_gen_7_div":1,"enable_gclk_gen_8":false,"gclk_gen_8_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_8_runstdby":false,"gclk_gen_8_div_sel":false,"gclk_arch_gen_8_oe":false,"gclk_arch_gen_8_oov":false,"gclk_arch_gen_8_idc":false,"gclk_arch_gen_8_enable":false,"gclk_gen_8_div":1,"enable_gclk_gen_9":false,"gclk_gen_9_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_9_runstdby":false,"gclk_gen_9_div_sel":false,"gclk_arch_gen_9_oe":false,"gclk_arch_gen_9_oov":false,"gclk_arch_gen_9_idc":false,"gclk_arch_gen_9_enable":false,"gclk_gen_9_div":1,"enable_gclk_gen_10":false,"gclk_gen_10_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_10_runstdby":false,"gclk_gen_10_div_sel":false,"gclk_arch_gen_10_oe":false,"gclk_arch_gen_10_oov":false,"gclk_arch_gen_10_idc":false,"gclk_arch_gen_10_enable":false,"gclk_gen_10_div":1,"enable_gclk_gen_11":false,"gclk_gen_11_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_11_runstdby":false,"gclk_gen_11_div_sel":false,"gclk_arch_gen_11_oe":false,"gclk_arch_gen_11_oov":false,"gclk_arch_gen_11_idc":false,"gclk_arch_gen_11_enable":false,"gclk_gen_11_div":1},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::GCLK::driver_definition::GCLK::HAL:HPL:GCLK","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK","module":"GCLK"}},{"functionality":null,"identifier":"OSC32KCTRL","user_label":"OSC32KCTRL","api":"HAL:HPL:OSC32KCTRL","configuration":{"enable_rtc_source":false,"rtc_source_oscillator":"32kHz Ultra Low Power Internal Oscillator (OSCULP32K)","rtc_1khz_selection":true,"enable_xosc32k":false,"xosc32k_arch_enable":false,"xosc32k_arch_startup":"62592us","xosc32k_arch_ondemand":true,"xosc32k_arch_runstdby":false,"xosc32k_arch_en1k":false,"xosc32k_arch_en32k":false,"xosc32k_arch_swben":false,"xosc32k_arch_cfden":false,"xosc32k_arch_cfdeo":false,"xosc32k_arch_xtalen":false,"xosc32k_arch_cgm":"Standard mode","enable_osculp32k":true,"osculp32k_calib_enable":false,"osculp32k_calib":0},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::OSC32KCTRL::driver_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL","module":"OSC32KCTRL"}},{"functionality":null,"identifier":"MCLK","user_label":"MCLK","api":"HAL:HPL:MCLK","configuration":{"enable_cpu_clock":true,"cpu_clock_source":"Generic clock generator 0","cpu_div":"1","mclk_arch_lpdiv":"Divide by 4","mclk_arch_bupdiv":"Divide by 8","mclk_arch_hsdiv":"Divide by 1","nvm_wait_states":"0"},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::MCLK::driver_definition::MCLK::HAL:HPL:MCLK","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK","module":"MCLK"},"clocks":{"domain_group":{"nodes":[{"name":"CPU","input":"CPU"}],"configuration":{}}}},{"functionality":null,"identifier":"DMAC","user_label":"DMAC","api":"HAL:HPL:DMAC","configuration":{"dmac_enable":false,"dmac_lvlen0":true,"dmac_rrlvlen0":"Static arbitration scheme for channel with priority 0","dmac_lvlpri0":0,"dmac_lvlen1":true,"dmac_rrlvlen1":"Static arbitration scheme for channel with priority 1","dmac_lvlpri1":0,"dmac_lvlen2":true,"dmac_rrlvlen2":"Static arbitration scheme for channel with priority 2","dmac_lvlpri2":0,"dmac_lvlen3":true,"dmac_rrlvlen3":"Static arbitration scheme for channel with priority 3","dmac_lvlpri3":0,"dmac_dbgrun":false,"dmac_channel_0_settings":false,"dmac_runstdby_0":false,"dmac_trigact_0":"One trigger required for each block transfer","dmac_trifsrc_0":"Only software/event triggers","dmac_lvl_0":"Channel priority 0","dmac_evoe_0":false,"dmac_evie_0":false,"dmac_evact_0":"No action","dmac_stepsize_0":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_0":"Step size settings apply to the destination address","dmac_srcinc_0":false,"dmac_dstinc_0":false,"dmac_beatsize_0":"8-bit bus transfer","dmac_blockact_0":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_0":"Event generation disabled","dmac_channel_1_settings":false,"dmac_runstdby_1":false,"dmac_trigact_1":"One trigger required for each block transfer","dmac_trifsrc_1":"Only software/event triggers","dmac_lvl_1":"Channel priority 0","dmac_evoe_1":false,"dmac_evie_1":false,"dmac_evact_1":"No action","dmac_stepsize_1":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_1":"Step size settings apply to the destination address","dmac_srcinc_1":false,"dmac_dstinc_1":false,"dmac_beatsize_1":"8-bit bus transfer","dmac_blockact_1":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_1":"Event generation disabled","dmac_channel_2_settings":false,"dmac_runstdby_2":false,"dmac_trigact_2":"One trigger required for each block transfer","dmac_trifsrc_2":"Only software/event triggers","dmac_lvl_2":"Channel priority 0","dmac_evoe_2":false,"dmac_evie_2":false,"dmac_evact_2":"No action","dmac_stepsize_2":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_2":"Step size settings apply to the destination address","dmac_srcinc_2":false,"dmac_dstinc_2":false,"dmac_beatsize_2":"8-bit bus transfer","dmac_blockact_2":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_2":"Event generation disabled","dmac_channel_3_settings":false,"dmac_runstdby_3":false,"dmac_trigact_3":"One trigger required for each block transfer","dmac_trifsrc_3":"Only software/event triggers","dmac_lvl_3":"Channel priority 0","dmac_evoe_3":false,"dmac_evie_3":false,"dmac_evact_3":"No action","dmac_stepsize_3":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_3":"Step size settings apply to the destination address","dmac_srcinc_3":false,"dmac_dstinc_3":false,"dmac_beatsize_3":"8-bit bus transfer","dmac_blockact_3":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_3":"Event generation disabled","dmac_channel_4_settings":false,"dmac_runstdby_4":false,"dmac_trigact_4":"One trigger required for each block transfer","dmac_trifsrc_4":"Only software/event triggers","dmac_lvl_4":"Channel priority 0","dmac_evoe_4":false,"dmac_evie_4":false,"dmac_evact_4":"No action","dmac_stepsize_4":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_4":"Step size settings apply to the destination address","dmac_srcinc_4":false,"dmac_dstinc_4":false,"dmac_beatsize_4":"8-bit bus transfer","dmac_blockact_4":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_4":"Event generation disabled","dmac_channel_5_settings":false,"dmac_runstdby_5":false,"dmac_trigact_5":"One trigger required for each block transfer","dmac_trifsrc_5":"Only software/event triggers","dmac_lvl_5":"Channel priority 0","dmac_evoe_5":false,"dmac_evie_5":false,"dmac_evact_5":"No action","dmac_stepsize_5":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_5":"Step size settings apply to the destination address","dmac_srcinc_5":false,"dmac_dstinc_5":false,"dmac_beatsize_5":"8-bit bus transfer","dmac_blockact_5":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_5":"Event generation disabled","dmac_channel_6_settings":false,"dmac_runstdby_6":false,"dmac_trigact_6":"One trigger required for each block transfer","dmac_trifsrc_6":"Only software/event triggers","dmac_lvl_6":"Channel priority 0","dmac_evoe_6":false,"dmac_evie_6":false,"dmac_evact_6":"No action","dmac_stepsize_6":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_6":"Step size settings apply to the destination address","dmac_srcinc_6":false,"dmac_dstinc_6":false,"dmac_beatsize_6":"8-bit bus transfer","dmac_blockact_6":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_6":"Event generation disabled","dmac_channel_7_settings":false,"dmac_runstdby_7":false,"dmac_trigact_7":"One trigger required for each block transfer","dmac_trifsrc_7":"Only software/event triggers","dmac_lvl_7":"Channel priority 0","dmac_evoe_7":false,"dmac_evie_7":false,"dmac_evact_7":"No action","dmac_stepsize_7":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_7":"Step size settings apply to the destination address","dmac_srcinc_7":false,"dmac_dstinc_7":false,"dmac_beatsize_7":"8-bit bus transfer","dmac_blockact_7":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_7":"Event generation disabled","dmac_channel_8_settings":false,"dmac_runstdby_8":false,"dmac_trigact_8":"One trigger required for each block transfer","dmac_trifsrc_8":"Only software/event triggers","dmac_lvl_8":"Channel priority 0","dmac_evoe_8":false,"dmac_evie_8":false,"dmac_evact_8":"No action","dmac_stepsize_8":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_8":"Step size settings apply to the destination address","dmac_srcinc_8":false,"dmac_dstinc_8":false,"dmac_beatsize_8":"8-bit bus transfer","dmac_blockact_8":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_8":"Event generation disabled","dmac_channel_9_settings":false,"dmac_runstdby_9":false,"dmac_trigact_9":"One trigger required for each block transfer","dmac_trifsrc_9":"Only software/event triggers","dmac_lvl_9":"Channel priority 0","dmac_evoe_9":false,"dmac_evie_9":false,"dmac_evact_9":"No action","dmac_stepsize_9":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_9":"Step size settings apply to the destination address","dmac_srcinc_9":false,"dmac_dstinc_9":false,"dmac_beatsize_9":"8-bit bus transfer","dmac_blockact_9":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_9":"Event generation disabled","dmac_channel_10_settings":false,"dmac_runstdby_10":false,"dmac_trigact_10":"One trigger required for each block transfer","dmac_trifsrc_10":"Only software/event triggers","dmac_lvl_10":"Channel priority 0","dmac_evoe_10":false,"dmac_evie_10":false,"dmac_evact_10":"No action","dmac_stepsize_10":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_10":"Step size settings apply to the destination address","dmac_srcinc_10":false,"dmac_dstinc_10":false,"dmac_beatsize_10":"8-bit bus transfer","dmac_blockact_10":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_10":"Event generation disabled","dmac_channel_11_settings":false,"dmac_runstdby_11":false,"dmac_trigact_11":"One trigger required for each block transfer","dmac_trifsrc_11":"Only software/event triggers","dmac_lvl_11":"Channel priority 0","dmac_evoe_11":false,"dmac_evie_11":false,"dmac_evact_11":"No action","dmac_stepsize_11":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_11":"Step size settings apply to the destination address","dmac_srcinc_11":false,"dmac_dstinc_11":false,"dmac_beatsize_11":"8-bit bus transfer","dmac_blockact_11":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_11":"Event generation disabled","dmac_channel_12_settings":false,"dmac_runstdby_12":false,"dmac_trigact_12":"One trigger required for each block transfer","dmac_trifsrc_12":"Only software/event triggers","dmac_lvl_12":"Channel priority 0","dmac_evoe_12":false,"dmac_evie_12":false,"dmac_evact_12":"No action","dmac_stepsize_12":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_12":"Step size settings apply to the destination address","dmac_srcinc_12":false,"dmac_dstinc_12":false,"dmac_beatsize_12":"8-bit bus transfer","dmac_blockact_12":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_12":"Event generation disabled","dmac_channel_13_settings":false,"dmac_runstdby_13":false,"dmac_trigact_13":"One trigger required for each block transfer","dmac_trifsrc_13":"Only software/event triggers","dmac_lvl_13":"Channel priority 0","dmac_evoe_13":false,"dmac_evie_13":false,"dmac_evact_13":"No action","dmac_stepsize_13":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_13":"Step size settings apply to the destination address","dmac_srcinc_13":false,"dmac_dstinc_13":false,"dmac_beatsize_13":"8-bit bus transfer","dmac_blockact_13":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_13":"Event generation disabled","dmac_channel_14_settings":false,"dmac_runstdby_14":false,"dmac_trigact_14":"One trigger required for each block transfer","dmac_trifsrc_14":"Only software/event triggers","dmac_lvl_14":"Channel priority 0","dmac_evoe_14":false,"dmac_evie_14":false,"dmac_evact_14":"No action","dmac_stepsize_14":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_14":"Step size settings apply to the destination address","dmac_srcinc_14":false,"dmac_dstinc_14":false,"dmac_beatsize_14":"8-bit bus transfer","dmac_blockact_14":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_14":"Event generation disabled","dmac_channel_15_settings":false,"dmac_runstdby_15":false,"dmac_trigact_15":"One trigger required for each block transfer","dmac_trifsrc_15":"Only software/event triggers","dmac_lvl_15":"Channel priority 0","dmac_evoe_15":false,"dmac_evie_15":false,"dmac_evact_15":"No action","dmac_stepsize_15":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_15":"Step size settings apply to the destination address","dmac_srcinc_15":false,"dmac_dstinc_15":false,"dmac_beatsize_15":"8-bit bus transfer","dmac_blockact_15":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_15":"Event generation disabled","dmac_channel_16_settings":false,"dmac_runstdby_16":false,"dmac_trigact_16":"One trigger required for each block transfer","dmac_trifsrc_16":"Only software/event triggers","dmac_lvl_16":"Channel priority 0","dmac_evoe_16":false,"dmac_evie_16":false,"dmac_evact_16":"No action","dmac_stepsize_16":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_16":"Step size settings apply to the destination address","dmac_srcinc_16":false,"dmac_dstinc_16":false,"dmac_beatsize_16":"8-bit bus transfer","dmac_blockact_16":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_16":"Event generation disabled","dmac_channel_17_settings":false,"dmac_runstdby_17":false,"dmac_trigact_17":"One trigger required for each block transfer","dmac_trifsrc_17":"Only software/event triggers","dmac_lvl_17":"Channel priority 0","dmac_evoe_17":false,"dmac_evie_17":false,"dmac_evact_17":"No action","dmac_stepsize_17":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_17":"Step size settings apply to the destination address","dmac_srcinc_17":false,"dmac_dstinc_17":false,"dmac_beatsize_17":"8-bit bus transfer","dmac_blockact_17":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_17":"Event generation disabled","dmac_channel_18_settings":false,"dmac_runstdby_18":false,"dmac_trigact_18":"One trigger required for each block transfer","dmac_trifsrc_18":"Only software/event triggers","dmac_lvl_18":"Channel priority 0","dmac_evoe_18":false,"dmac_evie_18":false,"dmac_evact_18":"No action","dmac_stepsize_18":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_18":"Step size settings apply to the destination address","dmac_srcinc_18":false,"dmac_dstinc_18":false,"dmac_beatsize_18":"8-bit bus transfer","dmac_blockact_18":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_18":"Event generation disabled","dmac_channel_19_settings":false,"dmac_runstdby_19":false,"dmac_trigact_19":"One trigger required for each block transfer","dmac_trifsrc_19":"Only software/event triggers","dmac_lvl_19":"Channel priority 0","dmac_evoe_19":false,"dmac_evie_19":false,"dmac_evact_19":"No action","dmac_stepsize_19":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_19":"Step size settings apply to the destination address","dmac_srcinc_19":false,"dmac_dstinc_19":false,"dmac_beatsize_19":"8-bit bus transfer","dmac_blockact_19":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_19":"Event generation disabled","dmac_channel_20_settings":false,"dmac_runstdby_20":false,"dmac_trigact_20":"One trigger required for each block transfer","dmac_trifsrc_20":"Only software/event triggers","dmac_lvl_20":"Channel priority 0","dmac_evoe_20":false,"dmac_evie_20":false,"dmac_evact_20":"No action","dmac_stepsize_20":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_20":"Step size settings apply to the destination address","dmac_srcinc_20":false,"dmac_dstinc_20":false,"dmac_beatsize_20":"8-bit bus transfer","dmac_blockact_20":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_20":"Event generation disabled","dmac_channel_21_settings":false,"dmac_runstdby_21":false,"dmac_trigact_21":"One trigger required for each block transfer","dmac_trifsrc_21":"Only software/event triggers","dmac_lvl_21":"Channel priority 0","dmac_evoe_21":false,"dmac_evie_21":false,"dmac_evact_21":"No action","dmac_stepsize_21":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_21":"Step size settings apply to the destination address","dmac_srcinc_21":false,"dmac_dstinc_21":false,"dmac_beatsize_21":"8-bit bus transfer","dmac_blockact_21":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_21":"Event generation disabled","dmac_channel_22_settings":false,"dmac_runstdby_22":false,"dmac_trigact_22":"One trigger required for each block transfer","dmac_trifsrc_22":"Only software/event triggers","dmac_lvl_22":"Channel priority 0","dmac_evoe_22":false,"dmac_evie_22":false,"dmac_evact_22":"No action","dmac_stepsize_22":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_22":"Step size settings apply to the destination address","dmac_srcinc_22":false,"dmac_dstinc_22":false,"dmac_beatsize_22":"8-bit bus transfer","dmac_blockact_22":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_22":"Event generation disabled","dmac_channel_23_settings":false,"dmac_runstdby_23":false,"dmac_trigact_23":"One trigger required for each block transfer","dmac_trifsrc_23":"Only software/event triggers","dmac_lvl_23":"Channel priority 0","dmac_evoe_23":false,"dmac_evie_23":false,"dmac_evact_23":"No action","dmac_stepsize_23":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_23":"Step size settings apply to the destination address","dmac_srcinc_23":false,"dmac_dstinc_23":false,"dmac_beatsize_23":"8-bit bus transfer","dmac_blockact_23":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_23":"Event generation disabled","dmac_channel_24_settings":false,"dmac_runstdby_24":false,"dmac_trigact_24":"One trigger required for each block transfer","dmac_trifsrc_24":"Only software/event triggers","dmac_lvl_24":"Channel priority 0","dmac_evoe_24":false,"dmac_evie_24":false,"dmac_evact_24":"No action","dmac_stepsize_24":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_24":"Step size settings apply to the destination address","dmac_srcinc_24":false,"dmac_dstinc_24":false,"dmac_beatsize_24":"8-bit bus transfer","dmac_blockact_24":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_24":"Event generation disabled","dmac_channel_25_settings":false,"dmac_runstdby_25":false,"dmac_trigact_25":"One trigger required for each block transfer","dmac_trifsrc_25":"Only software/event triggers","dmac_lvl_25":"Channel priority 0","dmac_evoe_25":false,"dmac_evie_25":false,"dmac_evact_25":"No action","dmac_stepsize_25":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_25":"Step size settings apply to the destination address","dmac_srcinc_25":false,"dmac_dstinc_25":false,"dmac_beatsize_25":"8-bit bus transfer","dmac_blockact_25":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_25":"Event generation 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1","nvm_wait_states":"0"},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::MCLK::driver_definition::MCLK::HAL:HPL:MCLK","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK","module":"MCLK"},"clocks":{"domain_group":{"configuration":null,"nodes":[{"name":"CPU","input":"CPU"}]}}},{"functionality":null,"identifier":"RAMECC","user_label":"RAMECC","api":"HAL:HPL:RAMECC","configuration":{},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::RAMECC::driver_definition::RAMECC::HAL:HPL:RAMECC","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC","module":"RAMECC"}},{"functionality":null,"identifier":"OSCCTRL","user_label":"OSCCTRL","api":"HAL:HPL:OSCCTRL","configuration":{"enable_xosc0":false,"xosc0_frequency":12000000,"xosc0_arch_enable":false,"xosc0_arch_startup":"31us","xosc0_arch_swben":false,"xosc0_arch_cfden":false,"xosc0_arch_enalc":false,"xosc0_arch_lowbufgain":false,"xosc0_arch_ondemand":false,"xosc0_arch_runstdby":false,"xosc0_arch_xtalen":false,"enable_xosc1":true,"xosc1_frequency":12000000,"xosc1_arch_enable":true,"xosc1_arch_startup":"31us","xosc1_arch_swben":false,"xosc1_arch_cfden":false,"xosc1_arch_enalc":false,"xosc1_arch_lowbufgain":false,"xosc1_arch_ondemand":false,"xosc1_arch_runstdby":false,"xosc1_arch_xtalen":true,"enable_dfll":false,"dfll_ref_clock":"Generic clock generator 3","dfll_arch_enable":false,"dfll_arch_ondemand":false,"dfll_arch_runstdby":false,"dfll_arch_usbcrm":false,"dfll_arch_waitlock":true,"dfll_arch_bplckc":false,"dfll_arch_qldis":false,"dfll_arch_ccdis":false,"dfll_arch_llaw":false,"dfll_arch_stable":false,"dfll_mode":"Open Loop Mode","dfll_arch_cstep":1,"dfll_arch_fstep":1,"dfll_mul":0,"dfll_arch_calibration":false,"dfll_arch_coarse":31,"dfll_arch_fine":128,"enable_fdpll0":false,"fdpll0_ref_clock":"32kHz External Crystal Oscillator (XOSC32K)","fdpll0_arch_enable":false,"fdpll0_arch_ondemand":false,"fdpll0_arch_runstdby":false,"fdpll0_ldrfrac":13,"fdpll0_ldr":1463,"fdpll0_clock_div":0,"fdpll0_arch_dcoen":false,"fdpll0_clock_dcofilter":0,"fdpll0_arch_lbypass":false,"fdpll0_arch_ltime":"No time-out, automatic lock","fdpll0_arch_refclk":"XOSC32K clock reference","fdpll0_arch_wuf":false,"fdpll0_arch_filter":0,"enable_fdpll1":false,"fdpll1_ref_clock":"32kHz External Crystal Oscillator (XOSC32K)","fdpll1_arch_enable":false,"fdpll1_arch_ondemand":false,"fdpll1_arch_runstdby":false,"fdpll1_ldrfrac":13,"fdpll1_ldr":1463,"fdpll1_clock_div":0,"fdpll1_arch_dcoen":false,"fdpll1_clock_dcofilter":0,"fdpll1_arch_lbypass":false,"fdpll1_arch_ltime":"No time-out, automatic lock","fdpll1_arch_refclk":"XOSC32K clock reference","fdpll1_arch_wuf":false,"fdpll1_arch_filter":0},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::OSCCTRL::driver_definition::OSCCTRL::HAL:HPL:OSCCTRL","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL","module":"OSCCTRL"}},{"functionality":null,"identifier":"DMAC","user_label":"DMAC","api":"HAL:HPL:DMAC","configuration":{"dmac_enable":false,"dmac_lvlen0":true,"dmac_rrlvlen0":"Static arbitration scheme for channel with priority 0","dmac_lvlpri0":0,"dmac_lvlen1":true,"dmac_rrlvlen1":"Static arbitration scheme for channel with priority 1","dmac_lvlpri1":0,"dmac_lvlen2":true,"dmac_rrlvlen2":"Static arbitration scheme for channel with priority 2","dmac_lvlpri2":0,"dmac_lvlen3":true,"dmac_rrlvlen3":"Static arbitration scheme for channel with priority 3","dmac_lvlpri3":0,"dmac_dbgrun":false,"dmac_channel_0_settings":false,"dmac_runstdby_0":false,"dmac_trigact_0":"One trigger required for each block transfer","dmac_trifsrc_0":"Only software/event triggers","dmac_lvl_0":"Channel priority 0","dmac_evoe_0":false,"dmac_evie_0":false,"dmac_evact_0":"No action","dmac_stepsize_0":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_0":"Step size settings apply to the destination address","dmac_srcinc_0":false,"dmac_dstinc_0":false,"dmac_beatsize_0":"8-bit bus transfer","dmac_blockact_0":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_0":"Event generation disabled","dmac_channel_1_settings":false,"dmac_runstdby_1":false,"dmac_trigact_1":"One trigger required for each block transfer","dmac_trifsrc_1":"Only software/event triggers","dmac_lvl_1":"Channel priority 0","dmac_evoe_1":false,"dmac_evie_1":false,"dmac_evact_1":"No action","dmac_stepsize_1":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_1":"Step size settings apply to the destination address","dmac_srcinc_1":false,"dmac_dstinc_1":false,"dmac_beatsize_1":"8-bit bus transfer","dmac_blockact_1":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_1":"Event generation disabled","dmac_channel_2_settings":false,"dmac_runstdby_2":false,"dmac_trigact_2":"One trigger required for each block transfer","dmac_trifsrc_2":"Only software/event triggers","dmac_lvl_2":"Channel priority 0","dmac_evoe_2":false,"dmac_evie_2":false,"dmac_evact_2":"No action","dmac_stepsize_2":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_2":"Step size settings apply to the destination address","dmac_srcinc_2":false,"dmac_dstinc_2":false,"dmac_beatsize_2":"8-bit bus transfer","dmac_blockact_2":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_2":"Event generation disabled","dmac_channel_3_settings":false,"dmac_runstdby_3":false,"dmac_trigact_3":"One trigger required for each block transfer","dmac_trifsrc_3":"Only software/event triggers","dmac_lvl_3":"Channel priority 0","dmac_evoe_3":false,"dmac_evie_3":false,"dmac_evact_3":"No action","dmac_stepsize_3":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_3":"Step size settings apply to the destination address","dmac_srcinc_3":false,"dmac_dstinc_3":false,"dmac_beatsize_3":"8-bit bus transfer","dmac_blockact_3":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_3":"Event generation disabled","dmac_channel_4_settings":false,"dmac_runstdby_4":false,"dmac_trigact_4":"One trigger required for each block transfer","dmac_trifsrc_4":"Only software/event triggers","dmac_lvl_4":"Channel priority 0","dmac_evoe_4":false,"dmac_evie_4":false,"dmac_evact_4":"No action","dmac_stepsize_4":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_4":"Step size settings apply to the destination address","dmac_srcinc_4":false,"dmac_dstinc_4":false,"dmac_beatsize_4":"8-bit bus transfer","dmac_blockact_4":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_4":"Event generation disabled","dmac_channel_5_settings":false,"dmac_runstdby_5":false,"dmac_trigact_5":"One trigger required for each block transfer","dmac_trifsrc_5":"Only software/event triggers","dmac_lvl_5":"Channel priority 0","dmac_evoe_5":false,"dmac_evie_5":false,"dmac_evact_5":"No action","dmac_stepsize_5":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_5":"Step size settings apply to the destination address","dmac_srcinc_5":false,"dmac_dstinc_5":false,"dmac_beatsize_5":"8-bit bus transfer","dmac_blockact_5":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_5":"Event generation disabled","dmac_channel_6_settings":false,"dmac_runstdby_6":false,"dmac_trigact_6":"One trigger required for each block transfer","dmac_trifsrc_6":"Only software/event triggers","dmac_lvl_6":"Channel priority 0","dmac_evoe_6":false,"dmac_evie_6":false,"dmac_evact_6":"No action","dmac_stepsize_6":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_6":"Step size settings apply to the destination address","dmac_srcinc_6":false,"dmac_dstinc_6":false,"dmac_beatsize_6":"8-bit bus transfer","dmac_blockact_6":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_6":"Event generation disabled","dmac_channel_7_settings":false,"dmac_runstdby_7":false,"dmac_trigact_7":"One trigger required for each block transfer","dmac_trifsrc_7":"Only software/event triggers","dmac_lvl_7":"Channel priority 0","dmac_evoe_7":false,"dmac_evie_7":false,"dmac_evact_7":"No action","dmac_stepsize_7":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_7":"Step size settings apply to the destination address","dmac_srcinc_7":false,"dmac_dstinc_7":false,"dmac_beatsize_7":"8-bit bus transfer","dmac_blockact_7":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_7":"Event generation disabled","dmac_channel_8_settings":false,"dmac_runstdby_8":false,"dmac_trigact_8":"One trigger required for each block transfer","dmac_trifsrc_8":"Only software/event triggers","dmac_lvl_8":"Channel priority 0","dmac_evoe_8":false,"dmac_evie_8":false,"dmac_evact_8":"No action","dmac_stepsize_8":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_8":"Step size settings apply to the destination address","dmac_srcinc_8":false,"dmac_dstinc_8":false,"dmac_beatsize_8":"8-bit bus transfer","dmac_blockact_8":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_8":"Event generation disabled","dmac_channel_9_settings":false,"dmac_runstdby_9":false,"dmac_trigact_9":"One trigger required for each block transfer","dmac_trifsrc_9":"Only software/event triggers","dmac_lvl_9":"Channel priority 0","dmac_evoe_9":false,"dmac_evie_9":false,"dmac_evact_9":"No action","dmac_stepsize_9":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_9":"Step size settings apply to the destination address","dmac_srcinc_9":false,"dmac_dstinc_9":false,"dmac_beatsize_9":"8-bit bus transfer","dmac_blockact_9":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_9":"Event generation disabled","dmac_channel_10_settings":false,"dmac_runstdby_10":false,"dmac_trigact_10":"One trigger required for each block transfer","dmac_trifsrc_10":"Only software/event triggers","dmac_lvl_10":"Channel priority 0","dmac_evoe_10":false,"dmac_evie_10":false,"dmac_evact_10":"No action","dmac_stepsize_10":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_10":"Step size settings apply to the destination address","dmac_srcinc_10":false,"dmac_dstinc_10":false,"dmac_beatsize_10":"8-bit bus transfer","dmac_blockact_10":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_10":"Event generation disabled","dmac_channel_11_settings":false,"dmac_runstdby_11":false,"dmac_trigact_11":"One trigger required for each block transfer","dmac_trifsrc_11":"Only software/event triggers","dmac_lvl_11":"Channel priority 0","dmac_evoe_11":false,"dmac_evie_11":false,"dmac_evact_11":"No action","dmac_stepsize_11":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_11":"Step size settings apply to the destination address","dmac_srcinc_11":false,"dmac_dstinc_11":false,"dmac_beatsize_11":"8-bit bus transfer","dmac_blockact_11":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_11":"Event generation disabled","dmac_channel_12_settings":false,"dmac_runstdby_12":false,"dmac_trigact_12":"One trigger required for each block transfer","dmac_trifsrc_12":"Only software/event triggers","dmac_lvl_12":"Channel priority 0","dmac_evoe_12":false,"dmac_evie_12":false,"dmac_evact_12":"No action","dmac_stepsize_12":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_12":"Step size settings apply to the destination address","dmac_srcinc_12":false,"dmac_dstinc_12":false,"dmac_beatsize_12":"8-bit bus transfer","dmac_blockact_12":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_12":"Event generation disabled","dmac_channel_13_settings":false,"dmac_runstdby_13":false,"dmac_trigact_13":"One trigger required for each block transfer","dmac_trifsrc_13":"Only software/event triggers","dmac_lvl_13":"Channel priority 0","dmac_evoe_13":false,"dmac_evie_13":false,"dmac_evact_13":"No action","dmac_stepsize_13":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_13":"Step size settings apply to the destination address","dmac_srcinc_13":false,"dmac_dstinc_13":false,"dmac_beatsize_13":"8-bit bus transfer","dmac_blockact_13":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_13":"Event generation disabled","dmac_channel_14_settings":false,"dmac_runstdby_14":false,"dmac_trigact_14":"One trigger required for each block transfer","dmac_trifsrc_14":"Only software/event triggers","dmac_lvl_14":"Channel priority 0","dmac_evoe_14":false,"dmac_evie_14":false,"dmac_evact_14":"No action","dmac_stepsize_14":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_14":"Step size settings apply to the destination address","dmac_srcinc_14":false,"dmac_dstinc_14":false,"dmac_beatsize_14":"8-bit bus transfer","dmac_blockact_14":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_14":"Event generation disabled","dmac_channel_15_settings":false,"dmac_runstdby_15":false,"dmac_trigact_15":"One trigger required for each block transfer","dmac_trifsrc_15":"Only software/event triggers","dmac_lvl_15":"Channel priority 0","dmac_evoe_15":false,"dmac_evie_15":false,"dmac_evact_15":"No action","dmac_stepsize_15":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_15":"Step size settings apply to the destination address","dmac_srcinc_15":false,"dmac_dstinc_15":false,"dmac_beatsize_15":"8-bit bus transfer","dmac_blockact_15":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_15":"Event generation disabled","dmac_channel_16_settings":false,"dmac_runstdby_16":false,"dmac_trigact_16":"One trigger required for each block transfer","dmac_trifsrc_16":"Only software/event triggers","dmac_lvl_16":"Channel priority 0","dmac_evoe_16":false,"dmac_evie_16":false,"dmac_evact_16":"No action","dmac_stepsize_16":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_16":"Step size settings apply to the destination address","dmac_srcinc_16":false,"dmac_dstinc_16":false,"dmac_beatsize_16":"8-bit bus transfer","dmac_blockact_16":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_16":"Event generation disabled","dmac_channel_17_settings":false,"dmac_runstdby_17":false,"dmac_trigact_17":"One trigger required for each block transfer","dmac_trifsrc_17":"Only software/event triggers","dmac_lvl_17":"Channel priority 0","dmac_evoe_17":false,"dmac_evie_17":false,"dmac_evact_17":"No action","dmac_stepsize_17":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_17":"Step size settings apply to the destination address","dmac_srcinc_17":false,"dmac_dstinc_17":false,"dmac_beatsize_17":"8-bit bus transfer","dmac_blockact_17":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_17":"Event generation disabled","dmac_channel_18_settings":false,"dmac_runstdby_18":false,"dmac_trigact_18":"One trigger required for each block transfer","dmac_trifsrc_18":"Only software/event triggers","dmac_lvl_18":"Channel priority 0","dmac_evoe_18":false,"dmac_evie_18":false,"dmac_evact_18":"No action","dmac_stepsize_18":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_18":"Step size settings apply to the destination address","dmac_srcinc_18":false,"dmac_dstinc_18":false,"dmac_beatsize_18":"8-bit bus transfer","dmac_blockact_18":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_18":"Event generation disabled","dmac_channel_19_settings":false,"dmac_runstdby_19":false,"dmac_trigact_19":"One trigger required for each block transfer","dmac_trifsrc_19":"Only software/event triggers","dmac_lvl_19":"Channel priority 0","dmac_evoe_19":false,"dmac_evie_19":false,"dmac_evact_19":"No action","dmac_stepsize_19":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_19":"Step size settings apply to the destination address","dmac_srcinc_19":false,"dmac_dstinc_19":false,"dmac_beatsize_19":"8-bit bus transfer","dmac_blockact_19":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_19":"Event generation disabled","dmac_channel_20_settings":false,"dmac_runstdby_20":false,"dmac_trigact_20":"One trigger required for each block transfer","dmac_trifsrc_20":"Only software/event triggers","dmac_lvl_20":"Channel priority 0","dmac_evoe_20":false,"dmac_evie_20":false,"dmac_evact_20":"No action","dmac_stepsize_20":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_20":"Step size settings apply to the destination address","dmac_srcinc_20":false,"dmac_dstinc_20":false,"dmac_beatsize_20":"8-bit bus transfer","dmac_blockact_20":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_20":"Event generation disabled","dmac_channel_21_settings":false,"dmac_runstdby_21":false,"dmac_trigact_21":"One trigger required for each block transfer","dmac_trifsrc_21":"Only software/event triggers","dmac_lvl_21":"Channel priority 0","dmac_evoe_21":false,"dmac_evie_21":false,"dmac_evact_21":"No action","dmac_stepsize_21":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_21":"Step size settings apply to the destination address","dmac_srcinc_21":false,"dmac_dstinc_21":false,"dmac_beatsize_21":"8-bit bus transfer","dmac_blockact_21":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_21":"Event generation disabled","dmac_channel_22_settings":false,"dmac_runstdby_22":false,"dmac_trigact_22":"One trigger required for each block transfer","dmac_trifsrc_22":"Only software/event triggers","dmac_lvl_22":"Channel priority 0","dmac_evoe_22":false,"dmac_evie_22":false,"dmac_evact_22":"No action","dmac_stepsize_22":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_22":"Step size settings apply to the destination address","dmac_srcinc_22":false,"dmac_dstinc_22":false,"dmac_beatsize_22":"8-bit bus transfer","dmac_blockact_22":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_22":"Event generation disabled","dmac_channel_23_settings":false,"dmac_runstdby_23":false,"dmac_trigact_23":"One trigger required for each block transfer","dmac_trifsrc_23":"Only software/event triggers","dmac_lvl_23":"Channel priority 0","dmac_evoe_23":false,"dmac_evie_23":false,"dmac_evact_23":"No action","dmac_stepsize_23":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_23":"Step size settings apply to the destination address","dmac_srcinc_23":false,"dmac_dstinc_23":false,"dmac_beatsize_23":"8-bit bus transfer","dmac_blockact_23":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_23":"Event generation disabled","dmac_channel_24_settings":false,"dmac_runstdby_24":false,"dmac_trigact_24":"One trigger required for each block transfer","dmac_trifsrc_24":"Only software/event triggers","dmac_lvl_24":"Channel priority 0","dmac_evoe_24":false,"dmac_evie_24":false,"dmac_evact_24":"No action","dmac_stepsize_24":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_24":"Step size settings apply to the destination address","dmac_srcinc_24":false,"dmac_dstinc_24":false,"dmac_beatsize_24":"8-bit bus transfer","dmac_blockact_24":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_24":"Event generation disabled","dmac_channel_25_settings":false,"dmac_runstdby_25":false,"dmac_trigact_25":"One trigger required for each block transfer","dmac_trifsrc_25":"Only software/event triggers","dmac_lvl_25":"Channel priority 0","dmac_evoe_25":false,"dmac_evie_25":false,"dmac_evact_25":"No action","dmac_stepsize_25":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_25":"Step size settings apply to the destination address","dmac_srcinc_25":false,"dmac_dstinc_25":false,"dmac_beatsize_25":"8-bit bus transfer","dmac_blockact_25":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_25":"Event generation disabled","dmac_channel_26_settings":false,"dmac_runstdby_26":false,"dmac_trigact_26":"One trigger required for each block transfer","dmac_trifsrc_26":"Only software/event triggers","dmac_lvl_26":"Channel priority 0","dmac_evoe_26":false,"dmac_evie_26":false,"dmac_evact_26":"No action","dmac_stepsize_26":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_26":"Step size settings apply to the destination address","dmac_srcinc_26":false,"dmac_dstinc_26":false,"dmac_beatsize_26":"8-bit bus transfer","dmac_blockact_26":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_26":"Event generation disabled","dmac_channel_27_settings":false,"dmac_runstdby_27":false,"dmac_trigact_27":"One trigger required for each block transfer","dmac_trifsrc_27":"Only software/event triggers","dmac_lvl_27":"Channel priority 0","dmac_evoe_27":false,"dmac_evie_27":false,"dmac_evact_27":"No action","dmac_stepsize_27":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_27":"Step size settings apply to the destination address","dmac_srcinc_27":false,"dmac_dstinc_27":false,"dmac_beatsize_27":"8-bit bus transfer","dmac_blockact_27":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_27":"Event generation disabled","dmac_channel_28_settings":false,"dmac_runstdby_28":false,"dmac_trigact_28":"One trigger required for each block transfer","dmac_trifsrc_28":"Only software/event triggers","dmac_lvl_28":"Channel priority 0","dmac_evoe_28":false,"dmac_evie_28":false,"dmac_evact_28":"No action","dmac_stepsize_28":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_28":"Step size settings apply to the destination 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0"}]}}},{"functionality":"RAND","identifier":"RAND_0","user_label":"RAND_0","api":"HAL:Driver:RAND_Sync","configuration":{"trng_runstdby":false,"trng_datardyeo":false},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::TRNG::driver_definition::RAND::HAL:Driver:RAND.Sync","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::TRNG::driver_config_definition::RAND::HAL:Driver:RAND.Sync","module":"TRNG"}},{"functionality":"USB","identifier":"USB_DEVICE_INSTANCE","user_label":"USB_DEVICE_INSTANCE","api":"HAL:Driver:USB_Device","configuration":{"usb_arch_ep4_cache":"Cached by 64 bytes buffer","usb_arch_ep1_cache":"Cached by 64 bytes buffer","usb_arch_ep5_cache":"Cached by 64 bytes buffer","usb_ep5_I_CACHE":"No cache","usb_ep2_I_CACHE":"No cache","usb_ep4_I_CACHE":"No cache","usb_arch_ep7_cache":"Cached by 64 bytes buffer","usb_arch_ep2_cache":"Cached by 64 bytes buffer","usbd_num_ep_sp":"4 (EP0 + 3 endpoints)","usb_ep7_I_CACHE":"No cache","usb_arch_ep0_cache":"Cached by 64 bytes buffer","usbd_arch_max_ep_n":"2 (EP 0x82 or 0x02)","usb_ep1_I_CACHE":"No cache","usb_ep3_I_CACHE":"No cache","usbd_arch_speed":"Full speed","usb_arch_ep6_cache":"Cached by 64 bytes buffer","usb_ep6_I_CACHE":"No cache","usb_arch_ep3_cache":"Cached by 64 bytes buffer"},"dependencies":{},"optional_signals":[],"variant":{"specification":"default","required_signals":[{"label":"Data-","identifier":"USB_DEVICE_INSTANCE:Data-","name":"USB/DM","pad":"PA24","configuration":null,"definition":"","mode":"Enabled"},{"label":"Data+","identifier":"USB_DEVICE_INSTANCE:Data+","name":"USB/DP","pad":"PA25","configuration":null,"definition":"","mode":"Enabled"}]},"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::USB::driver_definition::USB.Device::HAL:Driver:USB.Device","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device","module":"USB"},"clocks":{"domain_group":{"configuration":null,"nodes":[{"name":"USB","input":"Generic clock generator 0"}]}}},{"functionality":"Flash","identifier":"FLASH_0","user_label":"FLASH_0","api":"HAL:Driver:FLASH","configuration":{"nvm_arch_sleepprm":"Wake On Access","nvm_arch_cache0":false,"nvm_arch_cache1":false},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::NVMCTRL::driver_definition::Flash::HAL:Driver:FLASH","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::NVMCTRL::driver_config_definition::Flash::HAL:Driver:FLASH","module":"NVMCTRL"}}],"pads":[{"name":"PA00","user_label":"PA00","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA00","mode":"Peripheral IO","configuration":null},{"name":"PA01","user_label":"PA01","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA01","mode":"Peripheral IO","configuration":null},{"name":"PA04","user_label":"PA04","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA04","mode":"Digital output","configuration":null},{"name":"PA05","user_label":"PA05","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA05","mode":"Digital output","configuration":null},{"name":"PA06","user_label":"PA06","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA06","mode":"Digital input","configuration":null},{"name":"PA08","user_label":"PA08","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA08","mode":"I2C","configuration":null},{"name":"PA09","user_label":"PA09","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA09","mode":"I2C","configuration":null},{"name":"PA24","user_label":"PA24","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA24","mode":"Advanced","configuration":null},{"name":"PA25","user_label":"PA25","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA25","mode":"Advanced","configuration":null}]} diff --git a/atmel-samd/tools/update_asf.py b/atmel-samd/tools/update_asf.py index 20868532b4..7b7bac10fe 100644 --- a/atmel-samd/tools/update_asf.py +++ b/atmel-samd/tools/update_asf.py @@ -1,7 +1,9 @@ import requests import zipfile import os.path +import shutil import sys +import subprocess for chip in ["samd21", "samd51"]: r = None @@ -16,39 +18,37 @@ for chip in ["samd21", "samd51"]: sys.exit(1) with open(filename, "wb") as out: out.write(r.content) + + # Extract to a temporary location and patch it before replacing the existing location. z = zipfile.ZipFile(filename) - z.extractall("asf4/" + chip) - print(z) + tmp_dir = "asf4/" + chip + "_vanilla" + z.extractall(tmp_dir) - # delete the zip on success - #os.remove(filename) + # Remove all carriage returns. + for dirpath, dirnames, filenames in os.walk(tmp_dir): + for fn in filenames: + fn = os.path.join(dirpath, fn) + subprocess.run(["sed", "-i", "s/\r//g", fn]) -# Remove LITTLE_ENDIAN define from ASF because it conflicts with GCC. -for fn in os.listdir("asf4/samd51/include"): - contents = [] - path = "asf4/samd51/include/" + fn - if not os.path.isfile(path): - continue - with open(path, "r") as f: - for line in f: - if line.startswith("#define LITTLE_ENDIAN"): - contents.append("//" + line) - else: - contents.append(line) - with open(path, "w") as f: - for line in contents: - f.write(line) + # Move files to match SAMD51 structure. + if chip == "samd21": + shutil.move("asf4/samd21_vanilla/samd21a/include", "asf4/samd21_vanilla") + shutil.move("asf4/samd21_vanilla/samd21a/gcc/gcc", "asf4/samd21_vanilla/gcc") + shutil.move("asf4/samd21_vanilla/samd21a/gcc/system_samd21.c", "asf4/samd21_vanilla/gcc") -# Replace ASF's assert with asf_assert so it doesn't conflict with the C macro. + ok = True + for patch in os.listdir("asf4/patches/" + chip): + patch = "patches/" + chip + "/" + patch + print(patch) + result = subprocess.run(["patch", "-l", "-F", "10", "-u", "-p", "1", "-d", tmp_dir, "-i", "../" + patch]) + ok = ok and result.returncode == 0 + print() -for chip in ["samd21", "samd51"]: - contents = [] - path = "asf4/" + chip + "/hal/utils/include/utils_assert.h" - with open(path, "r") as f: - for line in f: - contents.append(line.replace(" assert(", " asf_assert(")) - with open(path, "w") as f: - for line in contents: - f.write(line) - -# samd21/samd21a/include is copied to samd21/include to match samd51 + if ok: + real_dir = "asf4/" + chip + shutil.rmtree(real_dir) + shutil.move(tmp_dir, real_dir) + # delete the zip on success + os.remove(filename) + else: + print("A patch failed!") diff --git a/supervisor/port.h b/supervisor/port.h index 465b5a27d0..2f7bc64448 100644 --- a/supervisor/port.h +++ b/supervisor/port.h @@ -50,7 +50,11 @@ extern uint32_t _estack; extern uint32_t _ebss; safe_mode_t port_init(void); + +// Reset the microcontroller. void reset_port(void); + +// Reset the rest of the board. void reset_board(void); #endif // MICROPY_INCLUDED_SUPERVISOR_PORT_H