stm32/boards: Remove trailing spaces, and add newline at end of file.

Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George 2021-09-10 16:06:59 +10:00
parent 4c31d0ab60
commit 0a51073724
7 changed files with 7 additions and 7 deletions

View File

@ -85,4 +85,4 @@ T2,PE0
T3,PA10
USB_VBUS,PA9
USB_DM,PA11
USB_DP,PA12
USB_DP,PA12

1 MB1_AN PA2
85 T3 PA10
86 USB_VBUS PA9
87 USB_DM PA11
88 USB_DP PA12

View File

@ -115,4 +115,4 @@ PH1,PH1
SW,C13
LED_RED,B14
LED_GREEN,B0
LED_BLUE,B7
LED_BLUE,B7

1 PA0 PA0
115 SW C13
116 LED_RED B14
117 LED_GREEN B0
118 LED_BLUE B7

View File

@ -27,7 +27,7 @@
#define MICROPY_HW_UART3_RTS (pin_D12)
#define MICROPY_HW_UART3_CTS (pin_D11)
#if MICROPY_HW_HAS_SWITCH == 0
// NOTE: A0 also connects to the user switch. To use UART4 you should
// NOTE: A0 also connects to the user switch. To use UART4 you should
// set MICROPY_HW_HAS_SWITCH to 0, and also remove SB20 (on the back
// of the board near the USER switch).
#define MICROPY_HW_UART4_TX (pin_A0)

View File

@ -31,7 +31,7 @@
#define MICROPY_HW_UART3_RTS (pin_D12)
#define MICROPY_HW_UART3_CTS (pin_D11)
#if MICROPY_HW_HAS_SWITCH == 0
// NOTE: A0 also connects to the user switch. To use UART4 you should
// NOTE: A0 also connects to the user switch. To use UART4 you should
// set MICROPY_HW_HAS_SWITCH to 0, and also remove SB20 (on the back
// of the board near the USER switch).
#define MICROPY_HW_UART4_TX (pin_A0)

View File

@ -85,7 +85,7 @@ extern struct _spi_bdev_t spi_bdev;
// LEDs
#define MICROPY_HW_LED1 (pin_J13) // red
#define MICROPY_HW_LED2 (pin_J5) // green
#define MICROPY_HW_LED2 (pin_J5) // green
#define MICROPY_HW_LED3 (pin_A12) // green
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin))
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))

View File

@ -10,7 +10,7 @@ MEMORY
FLASH_FS (r) : ORIGIN = 0x08020000, LENGTH = 128K /* sector 1, 128K */
FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K /* sectors 6*128 + 8*128 */
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for storage cache */
RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* AXI SRAM */
RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* AXI SRAM */
RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
}

View File

@ -25,4 +25,4 @@ PortB,PB6,,LPTIM1_ETR,,,I2C1_SCL,,,USART1_TX,,TSC_G2_IO3,,,,SAI1_FS_B,TIM16_CH1N
PortB,PB7,,LPTIM1_IN2,,,I2C1_SDA,,,USART1_RX,,TSC_G2_IO4,,,,,,EVENTOUT,,COMP2_INM,
PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT,,,
PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT,,,
PortH,PH3,,,,,,,,,,,,,,,,EVENTOUT,,,
PortH,PH3,,,,,,,,,,,,,,,,EVENTOUT,,,

1 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
25 PortB PB7 LPTIM1_IN2 I2C1_SDA USART1_RX TSC_G2_IO4 EVENTOUT COMP2_INM
26 PortC PC14 EVENTOUT
27 PortC PC15 EVENTOUT
28 PortH PH3 EVENTOUT