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py/emitnative: Ensure load_subscr does not clobber existing REG_ARG_2. 

Follow up from a similar fix in 426785a19e

Fixes issue #6314.

Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George 2022-11-11 12:25:32 +11:00
parent 451ded8d7b
commit 0698dd72ea
3 changed files with 17 additions and 4 deletions
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3
py/emitnative.c
View File

@ -1527,6 +1527,7 @@ STATIC void emit_native_load_subscr(emit_t *emit) {
break;
}
#endif
need_reg_single(emit, reg_index, 0);
ASM_MOV_REG_IMM(emit->as, reg_index, index_value);
ASM_ADD_REG_REG(emit->as, reg_index, reg_base); // add index to base
reg_base = reg_index;
@ -1544,6 +1545,7 @@ STATIC void emit_native_load_subscr(emit_t *emit) {
break;
}
#endif
need_reg_single(emit, reg_index, 0);
ASM_MOV_REG_IMM(emit->as, reg_index, index_value << 1);
ASM_ADD_REG_REG(emit->as, reg_index, reg_base); // add 2*index to base
reg_base = reg_index;
@ -1561,6 +1563,7 @@ STATIC void emit_native_load_subscr(emit_t *emit) {
break;
}
#endif
need_reg_single(emit, reg_index, 0);
ASM_MOV_REG_IMM(emit->as, reg_index, index_value << 2);
ASM_ADD_REG_REG(emit->as, reg_index, reg_base); // add 4*index to base
reg_base = reg_index;

17
tests/micropython/viper_subscr_multi.py
View File

@ -6,15 +6,24 @@ def f1(b: ptr8):
b[0] += b[1]
b = bytearray(b"\x01\x02")
f1(b)
print(b)
@micropython.viper
def f2(b: ptr8, i: int):
b[0] += b[i]
b = bytearray(b"\x01\x02")
f1(b)
print(b)
b = bytearray(b"\x01\x02")
f2(b, 1)
print(b)
@micropython.viper
def f3(b: ptr8) -> int:
return b[0] << 24 | b[1] << 16 | b[2] << 8 | b[3]
print(hex(f3(b"\x01\x02\x03\x04")))

1
tests/micropython/viper_subscr_multi.py.exp
View File

@ -1,2 +1,3 @@
bytearray(b'\x03\x02')
bytearray(b'\x03\x02')
0x1020304