esp32/esp32_ulp: Enable FSM ULP for S2 and S3 chips.
This commit enables the ULP for the S2 and S3 chips. Note this is the FSM (Finite State Machine) ULP. Signed-off-by: Patrick Joy <patrick@joytech.com.au>
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@ -279,6 +279,14 @@ For more details see Espressif's `ESP-IDF RMT documentation.
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Ultra-Low-Power co-processor
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Ultra-Low-Power co-processor
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----------------------------
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----------------------------
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This class gives access to the Ultra Low Power (ULP) co-processor on the ESP32,
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ESP32-S2 and ESP32-S3 chips.
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.. warning::
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This class does not provide access to the RISCV ULP co-processor available
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on the ESP32-S2 and ESP32-S3 chips.
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.. class:: ULP()
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.. class:: ULP()
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This class provides access to the Ultra-Low-Power co-processor.
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This class provides access to the Ultra-Low-Power co-processor.
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@ -26,7 +26,8 @@
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#include "py/runtime.h"
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#include "py/runtime.h"
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#include "esp32/ulp.h"
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#include "esp32/ulp.h"
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#include "esp_err.h"
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#include "esp_err.h"
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@ -87,7 +88,13 @@ STATIC const mp_rom_map_elem_t esp32_ulp_locals_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_set_wakeup_period), MP_ROM_PTR(&esp32_ulp_set_wakeup_period_obj) },
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{ MP_ROM_QSTR(MP_QSTR_set_wakeup_period), MP_ROM_PTR(&esp32_ulp_set_wakeup_period_obj) },
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{ MP_ROM_QSTR(MP_QSTR_load_binary), MP_ROM_PTR(&esp32_ulp_load_binary_obj) },
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{ MP_ROM_QSTR(MP_QSTR_load_binary), MP_ROM_PTR(&esp32_ulp_load_binary_obj) },
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{ MP_ROM_QSTR(MP_QSTR_run), MP_ROM_PTR(&esp32_ulp_run_obj) },
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{ MP_ROM_QSTR(MP_QSTR_run), MP_ROM_PTR(&esp32_ulp_run_obj) },
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#if CONFIG_IDF_TARGET_ESP32
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{ MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) },
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{ MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) },
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#elif CONFIG_IDF_TARGET_ESP32S2
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{ MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM) },
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#elif CONFIG_IDF_TARGET_ESP32S3
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{ MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM) },
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#endif
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};
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};
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STATIC MP_DEFINE_CONST_DICT(esp32_ulp_locals_dict, esp32_ulp_locals_dict_table);
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STATIC MP_DEFINE_CONST_DICT(esp32_ulp_locals_dict, esp32_ulp_locals_dict_table);
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@ -217,7 +217,7 @@ STATIC const mp_rom_map_elem_t esp32_module_globals_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_NVS), MP_ROM_PTR(&esp32_nvs_type) },
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{ MP_ROM_QSTR(MP_QSTR_NVS), MP_ROM_PTR(&esp32_nvs_type) },
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{ MP_ROM_QSTR(MP_QSTR_Partition), MP_ROM_PTR(&esp32_partition_type) },
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{ MP_ROM_QSTR(MP_QSTR_Partition), MP_ROM_PTR(&esp32_partition_type) },
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{ MP_ROM_QSTR(MP_QSTR_RMT), MP_ROM_PTR(&esp32_rmt_type) },
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{ MP_ROM_QSTR(MP_QSTR_RMT), MP_ROM_PTR(&esp32_rmt_type) },
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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{ MP_ROM_QSTR(MP_QSTR_ULP), MP_ROM_PTR(&esp32_ulp_type) },
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{ MP_ROM_QSTR(MP_QSTR_ULP), MP_ROM_PTR(&esp32_ulp_type) },
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#endif
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#endif
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