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esp32/esp32_ulp: Enable FSM ULP for S2 and S3 chips.

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This commit enables the ULP for the S2 and S3 chips.

Note this is the FSM (Finite State Machine) ULP.

Signed-off-by: Patrick Joy <patrick@joytech.com.au>
This commit is contained in:
patrick 2023-05-17 01:06:04 +10:00 committed by Damien George
parent 3a7ad64267
commit 05e143dbdd
3 changed files with 17 additions and 2 deletions
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8
docs/library/esp32.rst
View File

@ -279,6 +279,14 @@ For more details see Espressif's `ESP-IDF RMT documentation.
Ultra-Low-Power co-processor
----------------------------
This class gives access to the Ultra Low Power (ULP) co-processor on the ESP32,
ESP32-S2 and ESP32-S3 chips.
.. warning::
This class does not provide access to the RISCV ULP co-processor available
on the ESP32-S2 and ESP32-S3 chips.
.. class:: ULP()
This class provides access to the Ultra-Low-Power co-processor.

9
ports/esp32/esp32_ulp.c
View File

@ -26,7 +26,8 @@
#include "py/runtime.h"
#if CONFIG_IDF_TARGET_ESP32
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#include "esp32/ulp.h"
#include "esp_err.h"
@ -87,7 +88,13 @@ STATIC const mp_rom_map_elem_t esp32_ulp_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_set_wakeup_period), MP_ROM_PTR(&esp32_ulp_set_wakeup_period_obj) },
{ MP_ROM_QSTR(MP_QSTR_load_binary), MP_ROM_PTR(&esp32_ulp_load_binary_obj) },
{ MP_ROM_QSTR(MP_QSTR_run), MP_ROM_PTR(&esp32_ulp_run_obj) },
#if CONFIG_IDF_TARGET_ESP32
{ MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) },
#elif CONFIG_IDF_TARGET_ESP32S2
{ MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM) },
#elif CONFIG_IDF_TARGET_ESP32S3
{ MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM) },
#endif
};
STATIC MP_DEFINE_CONST_DICT(esp32_ulp_locals_dict, esp32_ulp_locals_dict_table);

2
ports/esp32/modesp32.c
View File

@ -217,7 +217,7 @@ STATIC const mp_rom_map_elem_t esp32_module_globals_table[] = {
{ MP_ROM_QSTR(MP_QSTR_NVS), MP_ROM_PTR(&esp32_nvs_type) },
{ MP_ROM_QSTR(MP_QSTR_Partition), MP_ROM_PTR(&esp32_partition_type) },
{ MP_ROM_QSTR(MP_QSTR_RMT), MP_ROM_PTR(&esp32_rmt_type) },
#if CONFIG_IDF_TARGET_ESP32
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
{ MP_ROM_QSTR(MP_QSTR_ULP), MP_ROM_PTR(&esp32_ulp_type) },
#endif