From 02fbb0a4553e5a03bd5a818fa511487ff72e6753 Mon Sep 17 00:00:00 2001 From: forester3 Date: Tue, 31 Jul 2018 09:46:38 +0900 Subject: [PATCH] stm32/boards/STM32F7DISC: Enable onboard SDRAM. The default SYSCLK frequency is reduced to 192MHz because SDRAM requires it to be 200MHz or less. --- .../stm32/boards/STM32F7DISC/mpconfigboard.h | 79 +++++++++++++++++-- ports/stm32/boards/STM32F7DISC/pins.csv | 38 +++++++++ .../boards/STM32F7DISC/stm32f7xx_hal_conf.h | 2 +- 3 files changed, 112 insertions(+), 7 deletions(-) diff --git a/ports/stm32/boards/STM32F7DISC/mpconfigboard.h b/ports/stm32/boards/STM32F7DISC/mpconfigboard.h index 7b506a3056..ceacd852f2 100644 --- a/ports/stm32/boards/STM32F7DISC/mpconfigboard.h +++ b/ports/stm32/boards/STM32F7DISC/mpconfigboard.h @@ -12,19 +12,21 @@ void STM32F7DISC_board_early_init(void); // HSE is 25MHz -// VCOClock = HSE * PLLN / PLLM = 25 MHz * 432 / 25 = 432 MHz -// SYSCLK = VCOClock / PLLP = 432 MHz / 2 = 216 MHz -// USB/SDMMC/RNG Clock = VCOClock / PLLQ = 432 MHz / 9 = 48 MHz +// VCOClock = HSE * PLLN / PLLM = 25 MHz * 384 / 25 = 384 MHz +// SYSCLK = VCOClock / PLLP = 384 MHz / 2 = 192 MHz +// USB/SDMMC/RNG Clock = VCOClock / PLLQ = 384 MHz / 8 = 48 MHz +// Note: SDRAM requires SYSCLK <= 200MHz +// SYSCLK can be increased to 216MHz if SDRAM is disabled #define MICROPY_HW_CLK_PLLM (25) -#define MICROPY_HW_CLK_PLLN (432) +#define MICROPY_HW_CLK_PLLN (384) #define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2) -#define MICROPY_HW_CLK_PLLQ (9) +#define MICROPY_HW_CLK_PLLQ (8) // From the reference manual, for 2.7V to 3.6V // 151-180 MHz => 5 wait states // 181-210 MHz => 6 wait states // 211-216 MHz => 7 wait states -#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_7 // 210-216 MHz needs 7 wait states +#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_6 // 181-210 MHz => 6 wait states // UART config #define MICROPY_HW_UART1_TX (pin_A9) @@ -78,3 +80,68 @@ void STM32F7DISC_board_early_init(void); #define MICROPY_HW_USB_FS (1) /*#define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_J12)*/ #define MICROPY_HW_USB_OTG_ID_PIN (pin_A10) + +// SDRAM +#define MICROPY_HW_SDRAM_SIZE (64 / 8 * 1024 * 1024) // 64 Mbit +#define MICROPY_HW_SDRAM_STARTUP_TEST (1) + +// Timing configuration for 90 Mhz (11.90ns) of SD clock frequency (180Mhz/2) +#define MICROPY_HW_SDRAM_TIMING_TMRD (2) +#define MICROPY_HW_SDRAM_TIMING_TXSR (7) +#define MICROPY_HW_SDRAM_TIMING_TRAS (4) +#define MICROPY_HW_SDRAM_TIMING_TRC (7) +#define MICROPY_HW_SDRAM_TIMING_TWR (2) +#define MICROPY_HW_SDRAM_TIMING_TRP (2) +#define MICROPY_HW_SDRAM_TIMING_TRCD (2) +#define MICROPY_HW_SDRAM_REFRESH_RATE (64) // ms + +#define MICROPY_HW_SDRAM_BURST_LENGTH 1 +#define MICROPY_HW_SDRAM_CAS_LATENCY 2 +#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM 8 +#define MICROPY_HW_SDRAM_ROW_BITS_NUM 12 +#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH 16 +#define MICROPY_HW_SDRAM_INTERN_BANKS_NUM 4 +#define MICROPY_HW_SDRAM_CLOCK_PERIOD 2 +#define MICROPY_HW_SDRAM_RPIPE_DELAY 0 +#define MICROPY_HW_SDRAM_RBURST (1) +#define MICROPY_HW_SDRAM_WRITE_PROTECTION (0) +#define MICROPY_HW_SDRAM_AUTOREFRESH_NUM (8) + +#define MICROPY_HW_FMC_SDCKE0 (pin_C3) +#define MICROPY_HW_FMC_SDNE0 (pin_H3) +#define MICROPY_HW_FMC_SDCLK (pin_G8) +#define MICROPY_HW_FMC_SDNCAS (pin_G15) +#define MICROPY_HW_FMC_SDNRAS (pin_F11) +#define MICROPY_HW_FMC_SDNWE (pin_H5) +#define MICROPY_HW_FMC_BA0 (pin_G4) +#define MICROPY_HW_FMC_BA1 (pin_G5) +#define MICROPY_HW_FMC_NBL0 (pin_E0) +#define MICROPY_HW_FMC_NBL1 (pin_E1) +#define MICROPY_HW_FMC_A0 (pin_F0) +#define MICROPY_HW_FMC_A1 (pin_F1) +#define MICROPY_HW_FMC_A2 (pin_F2) +#define MICROPY_HW_FMC_A3 (pin_F3) +#define MICROPY_HW_FMC_A4 (pin_F4) +#define MICROPY_HW_FMC_A5 (pin_F5) +#define MICROPY_HW_FMC_A6 (pin_F12) +#define MICROPY_HW_FMC_A7 (pin_F13) +#define MICROPY_HW_FMC_A8 (pin_F14) +#define MICROPY_HW_FMC_A9 (pin_F15) +#define MICROPY_HW_FMC_A10 (pin_G0) +#define MICROPY_HW_FMC_A11 (pin_G1) +#define MICROPY_HW_FMC_D0 (pin_D14) +#define MICROPY_HW_FMC_D1 (pin_D15) +#define MICROPY_HW_FMC_D2 (pin_D0) +#define MICROPY_HW_FMC_D3 (pin_D1) +#define MICROPY_HW_FMC_D4 (pin_E7) +#define MICROPY_HW_FMC_D5 (pin_E8) +#define MICROPY_HW_FMC_D6 (pin_E9) +#define MICROPY_HW_FMC_D7 (pin_E10) +#define MICROPY_HW_FMC_D8 (pin_E11) +#define MICROPY_HW_FMC_D9 (pin_E12) +#define MICROPY_HW_FMC_D10 (pin_E13) +#define MICROPY_HW_FMC_D11 (pin_E14) +#define MICROPY_HW_FMC_D12 (pin_E15) +#define MICROPY_HW_FMC_D13 (pin_D8) +#define MICROPY_HW_FMC_D14 (pin_D9) +#define MICROPY_HW_FMC_D15 (pin_D10) diff --git a/ports/stm32/boards/STM32F7DISC/pins.csv b/ports/stm32/boards/STM32F7DISC/pins.csv index 8b49003f7c..dfafe67f52 100644 --- a/ports/stm32/boards/STM32F7DISC/pins.csv +++ b/ports/stm32/boards/STM32F7DISC/pins.csv @@ -53,3 +53,41 @@ VCP_TX,PA9 VCP_RX,PB7 CAN_TX,PB13 CAN_RX,PB12 +SDRAM_SDCKE0,PC3 +SDRAM_SDNE0,PH3 +SDRAM_SDCLK,PG8 +SDRAM_SDNCAS,PG15 +SDRAM_SDNRAS,PF11 +SDRAM_SDNWE,PH5 +SDRAM_BA0,PG4 +SDRAM_BA1,PG5 +SDRAM_NBL0,PE0 +SDRAM_NBL1,PE1 +SDRAM_A0,PF0 +SDRAM_A1,PF1 +SDRAM_A2,PF2 +SDRAM_A3,PF3 +SDRAM_A4,PF4 +SDRAM_A5,PF5 +SDRAM_A6,PF12 +SDRAM_A7,PF13 +SDRAM_A8,PF14 +SDRAM_A9,PF15 +SDRAM_A10,PG0 +SDRAM_A11,PG1 +SDRAM_D0,PD14 +SDRAM_D1,PD15 +SDRAM_D2,PD0 +SDRAM_D3,PD1 +SDRAM_D4,PE7 +SDRAM_D5,PE8 +SDRAM_D6,PE9 +SDRAM_D7,PE10 +SDRAM_D8,PE11 +SDRAM_D9,PE12 +SDRAM_D10,PE13 +SDRAM_D11,PE14 +SDRAM_D12,PE15 +SDRAM_D13,PD8 +SDRAM_D14,PD9 +SDRAM_D15,PD10 diff --git a/ports/stm32/boards/STM32F7DISC/stm32f7xx_hal_conf.h b/ports/stm32/boards/STM32F7DISC/stm32f7xx_hal_conf.h index ff968bca99..1593390672 100644 --- a/ports/stm32/boards/STM32F7DISC/stm32f7xx_hal_conf.h +++ b/ports/stm32/boards/STM32F7DISC/stm32f7xx_hal_conf.h @@ -65,7 +65,7 @@ /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ +#define HAL_SDRAM_MODULE_ENABLED /* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED