Fix devices include by splitting type from defines
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supervisor/shared/external_flash/device.h
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78
supervisor/shared/external_flash/device.h
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018 Scott Shawcroft for Adafruit Industries LLC
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_DEVICE_H
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#define MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_DEVICE_H
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#include <stdbool.h>
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#include <stdint.h>
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typedef struct {
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uint32_t total_size;
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uint16_t start_up_time_us;
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// Three response bytes to 0x9f JEDEC ID command.
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uint8_t manufacturer_id;
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uint8_t memory_type;
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uint8_t capacity;
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// Max clock speed for all operations and the fastest read mode.
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uint8_t max_clock_speed_mhz;
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// Bitmask for Quad Enable bit if present. 0x00 otherwise. This is for the highest byte in the
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// status register.
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uint8_t quad_enable_bit_mask;
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bool has_sector_protection : 1;
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// Supports the 0x0b fast read command with 8 dummy cycles.
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bool supports_fast_read : 1;
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// Supports the fast read, quad output command 0x6b with 8 dummy cycles.
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bool supports_qspi : 1;
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// Supports the quad input page program command 0x32. This is known as 1-1-4 because it only
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// uses all four lines for data.
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bool supports_qspi_writes : 1;
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// Requires a separate command 0x31 to write to the second byte of the status register.
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// Otherwise two byte are written via 0x01.
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bool write_status_register_split : 1;
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// True when the status register is a single byte. This implies the Quad Enable bit is in the
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// first byte and the Read Status Register 2 command (0x35) is unsupported.
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bool single_status_byte : 1;
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// Does not support using a ready bit within the status register
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bool no_ready_bit : 1;
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// Does not support the erase command (0x20)
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bool no_erase_cmd : 1;
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// Device does not have a reset command
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bool no_reset_cmd : 1;
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} external_flash_device;
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#endif // MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_DEVICE_H
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@ -26,55 +26,6 @@
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#ifndef MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_DEVICES_H
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#define MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_DEVICES_H
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#include <stdbool.h>
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#include <stdint.h>
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typedef struct {
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uint32_t total_size;
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uint16_t start_up_time_us;
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// Three response bytes to 0x9f JEDEC ID command.
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uint8_t manufacturer_id;
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uint8_t memory_type;
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uint8_t capacity;
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// Max clock speed for all operations and the fastest read mode.
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uint8_t max_clock_speed_mhz;
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// Bitmask for Quad Enable bit if present. 0x00 otherwise. This is for the highest byte in the
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// status register.
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uint8_t quad_enable_bit_mask;
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bool has_sector_protection : 1;
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// Supports the 0x0b fast read command with 8 dummy cycles.
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bool supports_fast_read : 1;
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// Supports the fast read, quad output command 0x6b with 8 dummy cycles.
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bool supports_qspi : 1;
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// Supports the quad input page program command 0x32. This is known as 1-1-4 because it only
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// uses all four lines for data.
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bool supports_qspi_writes : 1;
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// Requires a separate command 0x31 to write to the second byte of the status register.
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// Otherwise two byte are written via 0x01.
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bool write_status_register_split : 1;
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// True when the status register is a single byte. This implies the Quad Enable bit is in the
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// first byte and the Read Status Register 2 command (0x35) is unsupported.
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bool single_status_byte : 1;
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// Does not support using a ready bit within the status register
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bool no_ready_bit : 1;
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// Does not support the erase command (0x20)
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bool no_erase_cmd : 1;
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// Device does not have a reset command
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bool no_reset_cmd : 1;
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} external_flash_device;
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{% for device in nvms %}
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#define {{ device.sku }} { \
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.total_size = {{ device.total_size }}, \
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@ -27,6 +27,7 @@
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#include <stdint.h>
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#include <string.h>
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#include "genhdr/devices.h"
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#include "supervisor/flash.h"
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#include "supervisor/spi_flash_api.h"
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#include "supervisor/shared/external_flash/common_commands.h"
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@ -29,7 +29,7 @@
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#include <stdbool.h>
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#include <stdint.h>
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#include "genhdr/devices.h"
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#include "shared/external_flash/device.h"
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#include "shared-bindings/busio/SPI.h"
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@ -54,7 +54,6 @@ $(HEADER_BUILD)/devices.h : ../../supervisor/shared/external_flash/devices.h.jin
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$(Q)install -d $(BUILD)/genhdr
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$(Q)$(PYTHON3) ../../tools/gen_nvm_devices.py $< $@
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$(BUILD)/supervisor/shared/external_flash/spi_flash.o: $(HEADER_BUILD)/devices.h
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$(BUILD)/supervisor/shared/external_flash/external_flash.o: $(HEADER_BUILD)/devices.h
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endif
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