From 28769f260951a9b7e8c1735602cc217f97ec81db Mon Sep 17 00:00:00 2001 From: Daniel Tralamazza Date: Wed, 22 Jun 2016 22:34:11 +0200 Subject: [PATCH 001/809] init --- nrf52/.gitignore | 1 + nrf52/Makefile | 141 +++++++ nrf52/README.md | 46 +++ nrf52/boards/D52Q/README.md | 3 + nrf52/boards/D52Q/build.mk | 5 + nrf52/boards/D52Q/d52q_board.c | 7 + nrf52/boards/D52Q/nrf52_board.h | 9 + nrf52/boards/PCA10040/README.md | 3 + nrf52/boards/PCA10040/build.mk | 7 + nrf52/boards/PCA10040/nrf52_board.h | 9 + nrf52/boards/PCA10040/pca10040_board.c | 7 + nrf52/gcc_nrf52_s132.ld | 23 ++ nrf52/main.c | 59 +++ nrf52/mods/build.mk | 4 + nrf52/mods/builtin.c | 54 +++ nrf52/mp_functions.c | 21 + nrf52/mpconfigport.h | 96 +++++ nrf52/mphalport.h | 2 + nrf52/nordic/.gitignore | 7 + nrf52/nordic/build.mk | 105 +++++ nrf52/nordic/gcc_startup_nrf52.S | 524 +++++++++++++++++++++++++ nrf52/nrf52_app_error.c | 19 + nrf52/nrf52_ble.c | 481 +++++++++++++++++++++++ nrf52/nrf52_ble.h | 4 + nrf52/pstorage_platform.h | 72 ++++ nrf52/qstrdefsport.h | 0 26 files changed, 1709 insertions(+) create mode 100644 nrf52/.gitignore create mode 100644 nrf52/Makefile create mode 100644 nrf52/README.md create mode 100644 nrf52/boards/D52Q/README.md create mode 100644 nrf52/boards/D52Q/build.mk create mode 100644 nrf52/boards/D52Q/d52q_board.c create mode 100644 nrf52/boards/D52Q/nrf52_board.h create mode 100644 nrf52/boards/PCA10040/README.md create mode 100644 nrf52/boards/PCA10040/build.mk create mode 100644 nrf52/boards/PCA10040/nrf52_board.h create mode 100644 nrf52/boards/PCA10040/pca10040_board.c create mode 100644 nrf52/gcc_nrf52_s132.ld create mode 100644 nrf52/main.c create mode 100644 nrf52/mods/build.mk create mode 100644 nrf52/mods/builtin.c create mode 100644 nrf52/mp_functions.c create mode 100644 nrf52/mpconfigport.h create mode 100644 nrf52/mphalport.h create mode 100644 nrf52/nordic/.gitignore create mode 100644 nrf52/nordic/build.mk create mode 100644 nrf52/nordic/gcc_startup_nrf52.S create mode 100644 nrf52/nrf52_app_error.c create mode 100644 nrf52/nrf52_ble.c create mode 100644 nrf52/nrf52_ble.h create mode 100644 nrf52/pstorage_platform.h create mode 100644 nrf52/qstrdefsport.h diff --git a/nrf52/.gitignore b/nrf52/.gitignore new file mode 100644 index 0000000000..d16386367f --- /dev/null +++ b/nrf52/.gitignore @@ -0,0 +1 @@ +build/ \ No newline at end of file diff --git a/nrf52/Makefile b/nrf52/Makefile new file mode 100644 index 0000000000..cd4251e1d4 --- /dev/null +++ b/nrf52/Makefile @@ -0,0 +1,141 @@ +include ../py/mkenv.mk + +CROSS_COMPILE ?= arm-none-eabi- + +BTYPE ?= debug + +ifeq (${BTYPE}, release) +DEFINES += NDEBUG +CFLAGS += -Os +# CFLAGS += -flto +else +ifeq (${BTYPE}, debug) +DEBUG := 1 +DEFINES += DEBUG +CFLAGS += -Og -g +else +$(error Invalid BTYPE specified) +endif +endif + +BOARD ?= PCA10040 + +BUILD = build/${BOARD}/${BTYPE} + +LINKER_PATH = . +LINKER_SCRIPT = gcc_nrf52_s132.ld + +# don't set PROG as it's used by mkrules.mk +PROGRAM ?= ${BUILD}/firmware + +# qstr definitions (must come before including py.mk) +QSTR_DEFS = qstrdefsport.h + +# include py core make definitions +include ../py/py.mk + +ifeq ($(wildcard boards/${BOARD}/.),) +$(error Invalid BOARD specified) +else +# include board makefile (if any) +-include boards/${BOARD}/build.mk +endif + +# include nordic makefile +include nordic/build.mk + +SRC_C += \ + main.c \ + mp_functions.c \ + nrf52_app_error.c \ + nrf52_ble.c \ + lib/mp-readline/readline.c \ + lib/utils/pyexec.c \ + lib/utils/stdout_helpers.c + +# XXX I simply copied gcc_startup_nrf52.s to .S so mkrules can compile it +OBJ += $(PY_O) $(addprefix ${BUILD}/, $(SRC_C:.c=.o)) + +INC += -I. +INC += -I.. +INC += -I${BUILD} +INC += -Iboards/${BOARD} +INC += -I../lib/mp-readline + +# transform all DEFINES entry in -DDEFINE c flags +CFLAGS += $(patsubst %,-D%,${DEFINES}) +CFLAGS += ${INC} +CFLAGS += -Wall -Werror -std=gnu99 +CFLAGS += -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -fsingle-precision-constant +CFLAGS += -ffunction-sections -fdata-sections -fno-strict-aliasing +CFLAGS += -fno-builtin --short-enums + +LDFLAGS += -Wl,-Map=${PROGRAM}.map +LDFLAGS += -mthumb -mabi=aapcs -L${LINKER_PATH} -T${LINKER_SCRIPT} +LDFLAGS += -mcpu=cortex-m4 +LDFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16 +LDFLAGS += -Wl,--gc-sections +LDFLAGS += --specs=nano.specs -lc -lnosys + +# mkenv doesn't set these +OBJDUMP = $(CROSS_COMPILE)objdump +GDB = $(CROSS_COMPILE)gdb + + +all: ${PROGRAM}.hex ${PROGRAM}.bin +.PHONY: all + +${PROGRAM}.elf: ${OBJ} + $(ECHO) "LINK $@" + ${Q}${CC} -o $@ ${CFLAGS} ${LDFLAGS} $^ ${LDLIBS} +ifndef DEBUG + ${Q}$(STRIP) $(STRIPFLAGS_EXTRA) $@ +endif + ${Q}$(SIZE) $@ + +%.hex: %.elf + ${Q}${OBJCOPY} -O ihex $< $@ + +%.bin: %.elf + ${Q}${OBJCOPY} -O binary $< $@ + +%.jlink: %.hex + ${OBJDUMP} -h $< | \ + awk '$$1 ~ /^[0-9]+$$/ {addr="0x"$$5; if (!min || addr < min) min = addr} END { printf "\ + loadbin %s,%s\n\ + sleep 100\n\ + r\n\ + g\n\ + exit\n", f, min}' f="$<" > $@ + +%-all.jlink: %.jlink ${SOFTDEV_HEX} + @[ -e "${SOFTDEV_HEX}" ] || echo "cannot find softdevice hex image '${SOFTDEV_HEX}'" >&2 + # w4 0x4001e504, 0x2 -> enable erase: CONFIG.WEN = EEN + # w4 0x4001e50c, 0x1 -> erase all: ERASEALL = 1 + printf "\ + device nrf52\n\ + halt\n\ + w4 0x4001e504, 0x2\n\ + w4 0x4001e50c, 0x1\n\ + sleep 100\n\ + r\n\ + loadbin %s,0\n" ${SOFTDEV_HEX} > $@ + cat $< >> $@ + +flash: ${PROGRAM}.hex ${PROGRAM}.jlink + JLinkExe -device nrf52 -if SWD ${PROGRAM}.jlink +.PHONY: flash + +flash-all: ${PROGRAM}.hex ${PROGRAM}-all.jlink + JLinkExe -device nrf52 -if SWD ${PROGRAM}-all.jlink +.PHONY: flash-all + +gdbserver: ${PROGRAM}.elf + JLinkGDBServer -device nrf52 -if SWD +.PHONY: gdbserver + +gdb: ${PROGRAM}.elf + ${GDB} ${PROGRAM}.elf -ex 'target remote :2331' +.PHONY: gdb + +include ../py/mkrules.mk diff --git a/nrf52/README.md b/nrf52/README.md new file mode 100644 index 0000000000..8ff64ed02b --- /dev/null +++ b/nrf52/README.md @@ -0,0 +1,46 @@ +# nRF52 Port + +WIP + +## requirements + +- GNU make +- ARM GCC for embedded development +- JLink Segger command line tools +- Download and unzip the Nordic SDK 11 under `nordic/` + + +## quickstart + +Plug your board and type: + + $> make flash-all + + +## debugging + + $> make gdbserver + +in another terminal + + $> make gdb + +in yet another terminal (for the RTT messages) + + $> telnet 127.0.0.1 19021 + + +## TODO + +- BLE peripheral + - Advertisement + - Manage services/characteristics + - Notifications/Indications +- HAL + - UART + - TWI + - SPI + - ADC + - Flash + - GPIO + - I2S \ No newline at end of file diff --git a/nrf52/boards/D52Q/README.md b/nrf52/boards/D52Q/README.md new file mode 100644 index 0000000000..9ede1e781e --- /dev/null +++ b/nrf52/boards/D52Q/README.md @@ -0,0 +1,3 @@ +# Dynasteam D52Q dev board + +(insert picture) \ No newline at end of file diff --git a/nrf52/boards/D52Q/build.mk b/nrf52/boards/D52Q/build.mk new file mode 100644 index 0000000000..4e331ce75a --- /dev/null +++ b/nrf52/boards/D52Q/build.mk @@ -0,0 +1,5 @@ + +D52Q_SRC_C += \ + d52q_board.c + +OBJ += $(addprefix ${BUILD}/boards/D52Q/, $(D52Q_SRC_C:.c=.o)) diff --git a/nrf52/boards/D52Q/d52q_board.c b/nrf52/boards/D52Q/d52q_board.c new file mode 100644 index 0000000000..438f09a0df --- /dev/null +++ b/nrf52/boards/D52Q/d52q_board.c @@ -0,0 +1,7 @@ +#include "nrf52_board.h" + + +void +nrf52_board_init(void) +{ +} diff --git a/nrf52/boards/D52Q/nrf52_board.h b/nrf52/boards/D52Q/nrf52_board.h new file mode 100644 index 0000000000..8d20b72844 --- /dev/null +++ b/nrf52/boards/D52Q/nrf52_board.h @@ -0,0 +1,9 @@ +#pragma once + +#include "nrf_sdm.h" + +// Low frequency clock source to be used by the SoftDevice +#define NRF_CLOCK_LFCLKSRC {.source = NRF_CLOCK_LF_SRC_XTAL, \ + .rc_ctiv = 0, \ + .rc_temp_ctiv = 0, \ + .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM} diff --git a/nrf52/boards/PCA10040/README.md b/nrf52/boards/PCA10040/README.md new file mode 100644 index 0000000000..e6bf1f8f51 --- /dev/null +++ b/nrf52/boards/PCA10040/README.md @@ -0,0 +1,3 @@ +# Nordic nRF52 DK + +[Link](https://www.nordicsemi.com/eng/Products/Bluetooth-low-energy/nRF52-DK) \ No newline at end of file diff --git a/nrf52/boards/PCA10040/build.mk b/nrf52/boards/PCA10040/build.mk new file mode 100644 index 0000000000..b6b3acd79e --- /dev/null +++ b/nrf52/boards/PCA10040/build.mk @@ -0,0 +1,7 @@ + +PCA10040_SRC_C += \ + pca10040_board.c + +OBJ += $(addprefix ${BUILD}/boards/PCA10040/, $(PCA10040_SRC_C:.c=.o)) + +DEFINES += BOARD_PCA10040 diff --git a/nrf52/boards/PCA10040/nrf52_board.h b/nrf52/boards/PCA10040/nrf52_board.h new file mode 100644 index 0000000000..8d20b72844 --- /dev/null +++ b/nrf52/boards/PCA10040/nrf52_board.h @@ -0,0 +1,9 @@ +#pragma once + +#include "nrf_sdm.h" + +// Low frequency clock source to be used by the SoftDevice +#define NRF_CLOCK_LFCLKSRC {.source = NRF_CLOCK_LF_SRC_XTAL, \ + .rc_ctiv = 0, \ + .rc_temp_ctiv = 0, \ + .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM} diff --git a/nrf52/boards/PCA10040/pca10040_board.c b/nrf52/boards/PCA10040/pca10040_board.c new file mode 100644 index 0000000000..438f09a0df --- /dev/null +++ b/nrf52/boards/PCA10040/pca10040_board.c @@ -0,0 +1,7 @@ +#include "nrf52_board.h" + + +void +nrf52_board_init(void) +{ +} diff --git a/nrf52/gcc_nrf52_s132.ld b/nrf52/gcc_nrf52_s132.ld new file mode 100644 index 0000000000..02585fe969 --- /dev/null +++ b/nrf52/gcc_nrf52_s132.ld @@ -0,0 +1,23 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x1c000, LENGTH = 0x64000 + RAM (rwx) : ORIGIN = 0x20002080, LENGTH = 0xdf80 +} + +SECTIONS +{ + .fs_data : + { + PROVIDE(__start_fs_data = .); + KEEP(*(.fs_data)) + PROVIDE(__stop_fs_data = .); + } > RAM +} INSERT AFTER .data; + +/* found in the nordic SDK components/toolchain/gcc */ +INCLUDE "nrf5x_common.ld" diff --git a/nrf52/main.c b/nrf52/main.c new file mode 100644 index 0000000000..9bc4177767 --- /dev/null +++ b/nrf52/main.c @@ -0,0 +1,59 @@ +#include "py/nlr.h" +#include "py/compile.h" +#include "py/runtime.h" +#include "py/repl.h" +#include "py/gc.h" +#include "lib/utils/pyexec.h" + +#include "nrf52_board.h" +#include "nrf52_ble.h" + +static char *stack_top; +static char heap[4 * 1024]; + +void nrf52_board_init(void); + +void +gc_collect(void) +{ + // WARNING: This gc_collect implementation doesn't try to get root + // pointers from CPU registers, and thus may function incorrectly. + void *dummy; + gc_collect_start(); + gc_collect_root(&dummy, ((mp_uint_t)stack_top - (mp_uint_t)&dummy) / sizeof(mp_uint_t)); + gc_collect_end(); + gc_dump_info(); +} + +int +main(int argc, char **argv) +{ + int stack_dummy; + stack_top = (char*)&stack_dummy; + + #if MICROPY_ENABLE_GC + gc_init(heap, heap + sizeof(heap)); + #endif + + nrf52_board_init(); + nrf52_ble_init(); + + mp_init(); + + #if MICROPY_REPL_EVENT_DRIVEN + pyexec_event_repl_init(); + for (;;) { + int c = mp_hal_stdin_rx_chr(); + if (pyexec_event_repl_process_char(c)) { + break; + } + } + #else + pyexec_friendly_repl(); + #endif + + mp_deinit(); + + NVIC_SystemReset(); + return 0; +} diff --git a/nrf52/mods/build.mk b/nrf52/mods/build.mk new file mode 100644 index 0000000000..13b2d7acdf --- /dev/null +++ b/nrf52/mods/build.mk @@ -0,0 +1,4 @@ +MODS_SRC_C += \ + builtin.c + +OBJ += $(addprefix ${BUILD}/mods/, $(MODS_SRC_C:.c=.o)) diff --git a/nrf52/mods/builtin.c b/nrf52/mods/builtin.c new file mode 100644 index 0000000000..0dfaff1a93 --- /dev/null +++ b/nrf52/mods/builtin.c @@ -0,0 +1,54 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2015 Daniel Campora + * Copyright (c) 2016 Daniel Tralamazza + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "lib/utils/pyhelp.h" +#include "py/runtime.h" +#include "extmod/vfs_fat_file.h" +#include "py/mphal.h" + +// MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, fatfs_builtin_open); + + +STATIC const char help_text[] = "Welcome to MicroPython!\n" + "For online help please visit http://micropython.org/help/.\n" + "For further help on a specific object, type help(obj)\n"; + +STATIC mp_obj_t pyb_help(uint n_args, const mp_obj_t *args) { + if (n_args == 0) { + // print a general help message + mp_hal_stdout_tx_str(help_text); + } + else { + // try to print something sensible about the given object + pyhelp_print_obj(args[0]); + } + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_builtin_help_obj, 0, 1, pyb_help); diff --git a/nrf52/mp_functions.c b/nrf52/mp_functions.c new file mode 100644 index 0000000000..1c217809fe --- /dev/null +++ b/nrf52/mp_functions.c @@ -0,0 +1,21 @@ +// NOTE: the objective is to move these functions to their respective final implementations + +#include "py/obj.h" +#include "py/lexer.h" + +void nlr_jump_fail(void *val) { +} + + +mp_import_stat_t mp_import_stat(const char *path) { + return MP_IMPORT_STAT_NO_EXIST; +} + +mp_lexer_t *mp_lexer_new_from_file(const char *filename) { + return NULL; +} + +mp_obj_t mp_builtin_open(uint n_args, const mp_obj_t *args, mp_map_t *kwargs) { + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open); diff --git a/nrf52/mpconfigport.h b/nrf52/mpconfigport.h new file mode 100644 index 0000000000..c5cf2fc46f --- /dev/null +++ b/nrf52/mpconfigport.h @@ -0,0 +1,96 @@ +#include + +// options to control how Micro Python is built + +#define MICROPY_QSTR_BYTES_IN_HASH (1) +// #define MICROPY_QSTR_EXTRA_POOL mp_qstr_frozen_const_pool +#define MICROPY_ALLOC_PATH_MAX (256) +#define MICROPY_ALLOC_PARSE_CHUNK_INIT (16) +#define MICROPY_EMIT_X64 (0) +#define MICROPY_EMIT_THUMB (0) +#define MICROPY_EMIT_INLINE_THUMB (0) +#define MICROPY_COMP_MODULE_CONST (0) +#define MICROPY_COMP_CONST (0) +#define MICROPY_COMP_DOUBLE_TUPLE_ASSIGN (0) +#define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0) +#define MICROPY_MEM_STATS (0) +#define MICROPY_DEBUG_PRINTERS (0) +#define MICROPY_ENABLE_GC (1) +#define MICROPY_REPL_EVENT_DRIVEN (0) +#define MICROPY_HELPER_REPL (1) +#define MICROPY_HELPER_LEXER_UNIX (0) +#define MICROPY_ENABLE_SOURCE_LINE (0) +#define MICROPY_ENABLE_DOC_STRING (0) +#define MICROPY_ERROR_REPORTING (MICROPY_ERROR_REPORTING_TERSE) +#define MICROPY_BUILTIN_METHOD_CHECK_SELF_ARG (0) +#define MICROPY_PY_ASYNC_AWAIT (0) +#define MICROPY_PY_BUILTINS_BYTEARRAY (0) +#define MICROPY_PY_BUILTINS_MEMORYVIEW (0) +#define MICROPY_PY_BUILTINS_ENUMERATE (0) +#define MICROPY_PY_BUILTINS_FILTER (0) +#define MICROPY_PY_BUILTINS_FROZENSET (0) +#define MICROPY_PY_BUILTINS_REVERSED (0) +#define MICROPY_PY_BUILTINS_SET (0) +#define MICROPY_PY_BUILTINS_SLICE (0) +#define MICROPY_PY_BUILTINS_PROPERTY (0) +#define MICROPY_PY_BUILTINS_MIN_MAX (0) +#define MICROPY_PY___FILE__ (0) +#define MICROPY_PY_GC (0) +#define MICROPY_PY_ARRAY (0) +#define MICROPY_PY_ATTRTUPLE (0) +#define MICROPY_PY_COLLECTIONS (0) +#define MICROPY_PY_MATH (0) +#define MICROPY_PY_CMATH (0) +#define MICROPY_PY_IO (0) +#define MICROPY_PY_STRUCT (0) +#define MICROPY_PY_SYS (0) +#define MICROPY_MODULE_FROZEN_MPY (0) +#define MICROPY_CPYTHON_COMPAT (0) +#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_NONE) +#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_NONE) + +// type definitions for the specific machine + +#define BYTES_PER_WORD (4) + +#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1)) + +// This port is intended to be 32-bit, but unfortunately, int32_t for +// different targets may be defined in different ways - either as int +// or as long. This requires different printf formatting specifiers +// to print such value. So, we avoid int32_t and use int directly. +#define UINT_FMT "%u" +#define INT_FMT "%d" +typedef int mp_int_t; // must be pointer size +typedef unsigned mp_uint_t; // must be pointer size + +typedef void *machine_ptr_t; // must be of pointer size +typedef const void *machine_const_ptr_t; // must be of pointer size +typedef long mp_off_t; + +#define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len) + +// extra built in names to add to the global namespace +extern const struct _mp_obj_fun_builtin_t mp_builtin_open_obj; +#define MICROPY_PORT_BUILTINS \ + { MP_OBJ_NEW_QSTR(MP_QSTR_open), (mp_obj_t)&mp_builtin_open_obj }, + +// We need to provide a declaration/definition of alloca() +#include + +#define MICROPY_HW_BOARD_NAME "minimal" +#define MICROPY_HW_MCU_NAME "NRF52832" + +#ifdef __linux__ +#define MICROPY_MIN_USE_STDOUT (1) +#endif + +#ifdef __thumb__ +#define MICROPY_MIN_USE_CORTEX_CPU (1) +#define MICROPY_MIN_USE_STM32_MCU (1) +#endif + +#define MP_STATE_PORT MP_STATE_VM + +#define MICROPY_PORT_ROOT_POINTERS \ + const char *readline_hist[8]; diff --git a/nrf52/mphalport.h b/nrf52/mphalport.h new file mode 100644 index 0000000000..60d68bd2d6 --- /dev/null +++ b/nrf52/mphalport.h @@ -0,0 +1,2 @@ +static inline mp_uint_t mp_hal_ticks_ms(void) { return 0; } +static inline void mp_hal_set_interrupt_char(char c) {} diff --git a/nrf52/nordic/.gitignore b/nrf52/nordic/.gitignore new file mode 100644 index 0000000000..7d72dd27b9 --- /dev/null +++ b/nrf52/nordic/.gitignore @@ -0,0 +1,7 @@ +# Ignore everything in this directory +* + +# Except +!.gitignore +!build.mk +!gcc_startup_nrf52.S \ No newline at end of file diff --git a/nrf52/nordic/build.mk b/nrf52/nordic/build.mk new file mode 100644 index 0000000000..4c9a6a6268 --- /dev/null +++ b/nrf52/nordic/build.mk @@ -0,0 +1,105 @@ +# this file's folder +SDK_DIR := $(abspath $(dir $(lastword ${MAKEFILE_LIST}))) + +# -D in CFLAGS +DEFINES += __HEAP_SIZE=0 +DEFINES += BLE_STACK_SUPPORT_REQD +DEFINES += CONFIG_GPIO_AS_PINRESET +DEFINES += NRF52 +DEFINES += NRF52_PAN_12 +DEFINES += NRF52_PAN_15 +DEFINES += NRF52_PAN_20 +DEFINES += NRF52_PAN_30 +DEFINES += NRF52_PAN_31 +DEFINES += NRF52_PAN_36 +DEFINES += NRF52_PAN_51 +DEFINES += NRF52_PAN_53 +DEFINES += NRF52_PAN_54 +DEFINES += NRF52_PAN_55 +DEFINES += NRF52_PAN_58 +DEFINES += NRF52_PAN_62 +DEFINES += NRF52_PAN_63 +DEFINES += NRF52_PAN_64 +DEFINES += S132 +DEFINES += SOFTDEVICE_PRESENT +DEFINES += SWI_DISABLE0 + +# nordic SDK C sources (relative path) +SDK_SRC_C += \ + components/ble/ble_advertising/ble_advertising.c \ + components/ble/ble_services/ble_nus/ble_nus.c \ + components/ble/common/ble_advdata.c \ + components/ble/common/ble_conn_params.c \ + components/ble/common/ble_conn_state.c \ + components/ble/common/ble_srv_common.c \ + components/ble/peer_manager/gatt_cache_manager.c \ + components/ble/peer_manager/gattc_cache_manager.c \ + components/ble/peer_manager/gatts_cache_manager.c \ + components/ble/peer_manager/id_manager.c \ + components/ble/peer_manager/peer_data.c \ + components/ble/peer_manager/peer_data_storage.c \ + components/ble/peer_manager/peer_database.c \ + components/ble/peer_manager/peer_id.c \ + components/ble/peer_manager/peer_manager.c \ + components/ble/peer_manager/pm_buffer.c \ + components/ble/peer_manager/pm_mutex.c \ + components/ble/peer_manager/security_dispatcher.c \ + components/ble/peer_manager/security_manager.c \ + components/drivers_nrf/delay/nrf_delay.c \ + components/drivers_nrf/pstorage/pstorage.c \ + components/libraries/fds/fds.c \ + components/libraries/fifo/app_fifo.c \ + components/libraries/fstorage/fstorage.c \ + components/libraries/timer/app_timer.c \ + components/libraries/util/app_util_platform.c \ + components/libraries/util/sdk_mapped_flags.c \ + components/softdevice/common/softdevice_handler/softdevice_handler.c \ + components/toolchain/system_nrf52.c + +# add segger RTT +ifeq (${BTYPE}, debug) +DEFINES += USE_RTT +SDK_SRC_C += \ + external/segger_rtt/RTT_Syscalls_GCC.c \ + external/segger_rtt/SEGGER_RTT.c \ + external/segger_rtt/SEGGER_RTT_printf.c +endif + +# # nordic SDK ASM sources (relative path) +# SDK_SRC_ASM += \ +# components/toolchain/gcc/gcc_startup_nrf52.s + +# include source folders (sort removes duplicates) +SDK_INC_DIRS += $(sort $(dir ${SDK_SRC_C})) +# ble.h +SDK_INC_DIRS += components/softdevice/s132/headers +# nrf52.h compiler_abstraction.h +SDK_INC_DIRS += components/device +# core_cm4.h +SDK_INC_DIRS += components/toolchain/CMSIS/Include +# section_vars.h +SDK_INC_DIRS += components/libraries/experimental_section_vars +# fstorage_config.h +SDK_INC_DIRS += components/libraries/fstorage/config +# nrf_drv_config.h +SDK_INC_DIRS += components/drivers_nrf/config +# app_util.h +SDK_INC_DIRS += components/libraries/util +# fds_config.h +SDK_INC_DIRS += components/libraries/fds/config + +# include full path +INC += $(patsubst %,-I${SDK_DIR}/%, ${SDK_INC_DIRS}) + +# object folder +NORDIC_BUILD = ${BUILD}/nordic + +OBJ += $(addprefix ${NORDIC_BUILD}/, $(SDK_SRC_C:.c=.o)) +# OBJ += $(addprefix ${NORDIC_BUILD}/, $(SDK_SRC_ASM:.s=.o)) +OBJ += ${NORDIC_BUILD}/gcc_startup_nrf52.o + +# linker script folder +LDFLAGS += -L${SDK_DIR}/components/toolchain/gcc + +# softdevice .hex file +SOFTDEV_HEX ?= $(lastword $(wildcard nordic/components/softdevice/s132/hex/s132*softdevice.hex)) diff --git a/nrf52/nordic/gcc_startup_nrf52.S b/nrf52/nordic/gcc_startup_nrf52.S new file mode 100644 index 0000000000..995771c50a --- /dev/null +++ b/nrf52/nordic/gcc_startup_nrf52.S @@ -0,0 +1,524 @@ +/* Copyright (c) 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + .syntax unified + .arch armv7e-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 8192 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 8192 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SVC_Handler + .long DebugMonitor_Handler + .long 0 /*Reserved */ + .long PendSV_Handler + .long SysTick_Handler + + /* External Interrupts */ + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .long NFCT_IRQHandler + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_EGU2_IRQHandler + .long SWI3_EGU3_IRQHandler + .long SWI4_EGU4_IRQHandler + .long SWI5_EGU5_IRQHandler + .long TIMER3_IRQHandler + .long TIMER4_IRQHandler + .long PWM0_IRQHandler + .long PDM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long MWU_IRQHandler + .long PWM1_IRQHandler + .long PWM2_IRQHandler + .long SPIM2_SPIS2_SPI2_IRQHandler + .long RTC2_IRQHandler + .long I2S_IRQHandler + .long FPU_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to. + * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ + * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__bss_start__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 + +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + bl SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler,.-Reset_Handler + + .section ".text" + + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + + .weak MemoryManagement_Handler + .type MemoryManagement_Handler, %function +MemoryManagement_Handler: + b . + .size MemoryManagement_Handler, . - MemoryManagement_Handler + + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + + .weak DebugMonitor_Handler + .type DebugMonitor_Handler, %function +DebugMonitor_Handler: + b . + .size DebugMonitor_Handler, . - DebugMonitor_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ POWER_CLOCK_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + IRQ NFCT_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ SWI2_EGU2_IRQHandler + IRQ SWI3_EGU3_IRQHandler + IRQ SWI4_EGU4_IRQHandler + IRQ SWI5_EGU5_IRQHandler + IRQ TIMER3_IRQHandler + IRQ TIMER4_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + IRQ MWU_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM2_IRQHandler + IRQ SPIM2_SPIS2_SPI2_IRQHandler + IRQ RTC2_IRQHandler + IRQ I2S_IRQHandler + IRQ FPU_IRQHandler + + .end diff --git a/nrf52/nrf52_app_error.c b/nrf52/nrf52_app_error.c new file mode 100644 index 0000000000..5775a3e3a3 --- /dev/null +++ b/nrf52/nrf52_app_error.c @@ -0,0 +1,19 @@ +#include +#include "app_error.h" + + +void +#ifdef DEBUG +app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) +#else +app_error_handler_bare(ret_code_t error_code) +#endif +{ +#ifdef DEBUG + for (;;) { + /* FOREVER */ + } +#else + NVIC_SystemReset(); +#endif +} diff --git a/nrf52/nrf52_ble.c b/nrf52/nrf52_ble.c new file mode 100644 index 0000000000..386e601f30 --- /dev/null +++ b/nrf52/nrf52_ble.c @@ -0,0 +1,481 @@ +#include "nrf52_ble.h" +#include "nrf52_board.h" + +#include "app_error.h" +#include "app_fifo.h" +#include "app_timer.h" +#include "ble_advertising.h" +#include "ble_conn_params.h" +#include "ble_conn_state.h" +#include "ble_hci.h" +#include "ble_nus.h" +#include "ble_srv_common.h" +#include "fds.h" +#include "fds.h" +#include "fstorage.h" +#include "peer_manager.h" +#include "softdevice_handler.h" + + +#define CENTRAL_LINK_COUNT 0 /**< Number of central links used by the application. When changing this number remember to adjust the RAM settings*/ +#define PERIPHERAL_LINK_COUNT 1 /**< Number of peripheral links used by the application. When changing this number remember to adjust the RAM settings*/ + +#define DEVICE_NAME "micropython" + +#define MIN_CONN_INTERVAL MSEC_TO_UNITS(20, UNIT_1_25_MS) /**< Minimum acceptable connection interval (0.02 seconds). */ +#define MAX_CONN_INTERVAL MSEC_TO_UNITS(200, UNIT_1_25_MS) /**< Maximum acceptable connection interval (0.2 second). */ +#define SLAVE_LATENCY 0 /**< Slave latency. */ +#define CONN_SUP_TIMEOUT MSEC_TO_UNITS(3000, UNIT_10_MS) /**< Connection supervisory timeout (3 seconds). */ + +#define APP_ADV_INTERVAL MSEC_TO_UNITS(25, UNIT_0_625_MS) +#define APP_ADV_TIMEOUT_IN_SECONDS 180 + +#define APP_TIMER_PRESCALER 0 /**< Value of the RTC1 PRESCALER register. */ +#define APP_TIMER_OP_QUEUE_SIZE 4 /**< Size of timer operation queues. */ + +#define FIRST_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(5000, APP_TIMER_PRESCALER) /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (5 seconds). */ +#define NEXT_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(30000, APP_TIMER_PRESCALER) /**< Time between each call to sd_ble_gap_conn_param_update after the first call (30 seconds). */ +#define MAX_CONN_PARAMS_UPDATE_COUNT 3 + +#define SEC_PARAM_BOND 1 /**< Perform bonding. */ +#define SEC_PARAM_MITM 0 /**< Man In The Middle protection not required. */ +#define SEC_PARAM_LESC 0 /**< LE Secure Connections not enabled. */ +#define SEC_PARAM_KEYPRESS 0 /**< Keypress notifications not enabled. */ +#define SEC_PARAM_IO_CAPABILITIES BLE_GAP_IO_CAPS_NONE /**< No I/O capabilities. */ +#define SEC_PARAM_OOB 0 /**< Out Of Band data not available. */ +#define SEC_PARAM_MIN_KEY_SIZE 7 /**< Minimum encryption key size. */ +#define SEC_PARAM_MAX_KEY_SIZE 16 /**< Maximum encryption key size. */ + +#define NUS_RX_FIFO_BUFFER_SIZE 64 + +static ble_uuid_t m_adv_uuids[] = {{BLE_UUID_NUS_SERVICE, 0}}; /**< Universally unique service identifiers. */ + +static ble_nus_t m_nus; +static app_fifo_t m_nus_rx_fifo; +static uint8_t m_nus_rx_fifo_buffer[NUS_RX_FIFO_BUFFER_SIZE]; + + +static void +ble_evt_dispatch(ble_evt_t * p_ble_evt) +{ + ble_conn_state_on_ble_evt(p_ble_evt); + pm_on_ble_evt(p_ble_evt); + ble_conn_params_on_ble_evt(p_ble_evt); + ble_advertising_on_ble_evt(p_ble_evt); + ble_nus_on_ble_evt(&m_nus, p_ble_evt); +} + +static void +sys_evt_dispatch(uint32_t sys_evt) +{ + fs_sys_event_handler(sys_evt); + ble_advertising_on_sys_evt(sys_evt); +} + +static void +ble_stack_init(void) +{ + nrf_clock_lf_cfg_t clock_lf_cfg = NRF_CLOCK_LFCLKSRC; + + // Initialize the SoftDevice handler module. + SOFTDEVICE_HANDLER_INIT(&clock_lf_cfg, NULL); + + ble_enable_params_t ble_enable_params; + uint32_t err_code = softdevice_enable_get_default_config(CENTRAL_LINK_COUNT, + PERIPHERAL_LINK_COUNT, + &ble_enable_params); + APP_ERROR_CHECK(err_code); + + //Check the ram settings against the used number of links + CHECK_RAM_START_ADDR(CENTRAL_LINK_COUNT, PERIPHERAL_LINK_COUNT); + + // Enable BLE stack. + err_code = softdevice_enable(&ble_enable_params); + APP_ERROR_CHECK(err_code); + + // Register with the SoftDevice handler module for BLE events. + err_code = softdevice_ble_evt_handler_set(ble_evt_dispatch); + APP_ERROR_CHECK(err_code); + + // Register with the SoftDevice handler module for BLE events. + err_code = softdevice_sys_evt_handler_set(sys_evt_dispatch); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for the GAP initialization. + * + * @details This function sets up all the necessary GAP (Generic Access Profile) parameters of the + * device including the device name, appearance, and the preferred connection parameters. + */ +static void +gap_params_init(void) +{ + uint32_t err_code; + ble_gap_conn_params_t gap_conn_params; + ble_gap_conn_sec_mode_t sec_mode; + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); + + err_code = sd_ble_gap_device_name_set(&sec_mode, + (const uint8_t *)DEVICE_NAME, + strlen(DEVICE_NAME)); + APP_ERROR_CHECK(err_code); + + err_code = sd_ble_gap_appearance_set(BLE_APPEARANCE_UNKNOWN); + APP_ERROR_CHECK(err_code); + + memset(&gap_conn_params, 0, sizeof(gap_conn_params)); + + gap_conn_params.min_conn_interval = MIN_CONN_INTERVAL; + gap_conn_params.max_conn_interval = MAX_CONN_INTERVAL; + gap_conn_params.slave_latency = SLAVE_LATENCY; + gap_conn_params.conn_sup_timeout = CONN_SUP_TIMEOUT; + + err_code = sd_ble_gap_ppcp_set(&gap_conn_params); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for handling advertising events. + * + * @details This function will be called for advertising events which are passed to the application. + * + * @param[in] ble_adv_evt Advertising event. + */ +static void +on_adv_evt(ble_adv_evt_t ble_adv_evt) +{ + switch (ble_adv_evt) + { + case BLE_ADV_EVT_FAST: + break; + case BLE_ADV_EVT_IDLE: + break; + default: + break; + } +} + +/**@brief Function for initializing the Advertising functionality. + */ +static void +advertising_init(void) +{ + uint32_t err_code; + ble_advdata_t advdata; + + // Build advertising data struct to pass into @ref ble_advertising_init. + memset(&advdata, 0, sizeof(advdata)); + + advdata.name_type = BLE_ADVDATA_FULL_NAME; + advdata.include_appearance = true; + advdata.flags = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE; + advdata.uuids_complete.uuid_cnt = sizeof(m_adv_uuids) / sizeof(m_adv_uuids[0]); + advdata.uuids_complete.p_uuids = m_adv_uuids; + + ble_adv_modes_config_t options = {0}; + options.ble_adv_fast_enabled = BLE_ADV_FAST_ENABLED; + options.ble_adv_fast_interval = APP_ADV_INTERVAL; + options.ble_adv_fast_timeout = APP_ADV_TIMEOUT_IN_SECONDS; + + err_code = ble_advertising_init(&advdata, NULL, &options, on_adv_evt, NULL); + APP_ERROR_CHECK(err_code); +} + +static void +nus_data_handler(ble_nus_t * p_nus, uint8_t * p_data, uint16_t length) +{ + for (uint32_t i = 0; i < length; i++) { + // XXX + app_fifo_put(&m_nus_rx_fifo, p_data[i]); + } +} + +static void +services_init(void) +{ + uint32_t err_code; + ble_nus_init_t nus_init = {0}; + nus_init.data_handler = nus_data_handler; + err_code = ble_nus_init(&m_nus, &nus_init); + APP_ERROR_CHECK(err_code); + + m_adv_uuids[0].type = m_nus.uuid_type; + + err_code = app_fifo_init(&m_nus_rx_fifo, m_nus_rx_fifo_buffer, NUS_RX_FIFO_BUFFER_SIZE); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for handling a Connection Parameters error. + * + * @param[in] nrf_error Error code containing information about what went wrong. + */ +static void conn_params_error_handler(uint32_t nrf_error) +{ + APP_ERROR_HANDLER(nrf_error); +} + +/**@brief Function for initializing the Connection Parameters module. + */ +static void +conn_params_init(void) +{ + uint32_t err_code; + ble_conn_params_init_t cp_init; + + memset(&cp_init, 0, sizeof(cp_init)); + + cp_init.p_conn_params = NULL; + cp_init.first_conn_params_update_delay = FIRST_CONN_PARAMS_UPDATE_DELAY; + cp_init.next_conn_params_update_delay = NEXT_CONN_PARAMS_UPDATE_DELAY; + cp_init.max_conn_params_update_count = MAX_CONN_PARAMS_UPDATE_COUNT; + cp_init.start_on_notify_cccd_handle = BLE_GATT_HANDLE_INVALID; + cp_init.disconnect_on_fail = true; + cp_init.evt_handler = NULL; + cp_init.error_handler = conn_params_error_handler; + + err_code = ble_conn_params_init(&cp_init); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for starting advertising. + */ +static void +advertising_start(void) +{ + uint32_t err_code = ble_advertising_start(BLE_ADV_MODE_FAST); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for handling Peer Manager events. + * + * @param[in] p_evt Peer Manager event. + */ +static void +pm_evt_handler(pm_evt_t const * p_evt) +{ + ret_code_t err_code; + + switch(p_evt->evt_id) + { + case PM_EVT_BONDED_PEER_CONNECTED: + err_code = pm_peer_rank_highest(p_evt->peer_id); + if (err_code != NRF_ERROR_BUSY) + { + APP_ERROR_CHECK(err_code); + } + break;//PM_EVT_BONDED_PEER_CONNECTED + + case PM_EVT_CONN_SEC_START: + break;//PM_EVT_CONN_SEC_START + + case PM_EVT_CONN_SEC_SUCCEEDED: + { + NRF_LOG_PRINTF_DEBUG("Link secured. Role: %d. conn_handle: %d, Procedure: %d\r\n", + ble_conn_state_role(p_evt->conn_handle), + p_evt->conn_handle, + p_evt->params.conn_sec_succeeded.procedure); + err_code = pm_peer_rank_highest(p_evt->peer_id); + if (err_code != NRF_ERROR_BUSY) + { + APP_ERROR_CHECK(err_code); + } + } + break;//PM_EVT_CONN_SEC_SUCCEEDED + + case PM_EVT_CONN_SEC_FAILED: + { + /** In some cases, when securing fails, it can be restarted directly. Sometimes it can + * be restarted, but only after changing some Security Parameters. Sometimes, it cannot + * be restarted until the link is disconnected and reconnected. Sometimes it is + * impossible, to secure the link, or the peer device does not support it. How to + * handle this error is highly application dependent. */ + switch (p_evt->params.conn_sec_failed.error) + { + case PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING: + // Rebond if one party has lost its keys. + err_code = pm_conn_secure(p_evt->conn_handle, true); + if (err_code != NRF_ERROR_INVALID_STATE) + { + APP_ERROR_CHECK(err_code); + } + break;//PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING + + default: + break; + } + } + break;//PM_EVT_CONN_SEC_FAILED + + case PM_EVT_CONN_SEC_CONFIG_REQ: + { + // Reject pairing request from an already bonded peer. + pm_conn_sec_config_t conn_sec_config = {.allow_repairing = false}; + pm_conn_sec_config_reply(p_evt->conn_handle, &conn_sec_config); + } + break;//PM_EVT_CONN_SEC_CONFIG_REQ + + case PM_EVT_STORAGE_FULL: + { + // Run garbage collection on the flash. + err_code = fds_gc(); + if (err_code == FDS_ERR_BUSY || err_code == FDS_ERR_NO_SPACE_IN_QUEUES) + { + // Retry. + } + else + { + APP_ERROR_CHECK(err_code); + } + } + break;//PM_EVT_STORAGE_FULL + + case PM_EVT_ERROR_UNEXPECTED: + // Assert. + APP_ERROR_CHECK(p_evt->params.error_unexpected.error); + break;//PM_EVT_ERROR_UNEXPECTED + + case PM_EVT_PEER_DATA_UPDATE_SUCCEEDED: + break;//PM_EVT_PEER_DATA_UPDATE_SUCCEEDED + + case PM_EVT_PEER_DATA_UPDATE_FAILED: + // Assert. + APP_ERROR_CHECK_BOOL(false); + break;//PM_EVT_PEER_DATA_UPDATE_FAILED + + case PM_EVT_PEER_DELETE_SUCCEEDED: + break;//PM_EVT_PEER_DELETE_SUCCEEDED + + case PM_EVT_PEER_DELETE_FAILED: + // Assert. + APP_ERROR_CHECK(p_evt->params.peer_delete_failed.error); + break;//PM_EVT_PEER_DELETE_FAILED + + case PM_EVT_PEERS_DELETE_SUCCEEDED: + advertising_start(); + break;//PM_EVT_PEERS_DELETE_SUCCEEDED + + case PM_EVT_PEERS_DELETE_FAILED: + // Assert. + APP_ERROR_CHECK(p_evt->params.peers_delete_failed_evt.error); + break;//PM_EVT_PEERS_DELETE_FAILED + + case PM_EVT_LOCAL_DB_CACHE_APPLIED: + break;//PM_EVT_LOCAL_DB_CACHE_APPLIED + + case PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED: + // The local database has likely changed, send service changed indications. + pm_local_database_has_changed(); + break;//PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED + + case PM_EVT_SERVICE_CHANGED_IND_SENT: + break;//PM_EVT_SERVICE_CHANGED_IND_SENT + + case PM_EVT_SERVICE_CHANGED_IND_CONFIRMED: + break;//PM_EVT_SERVICE_CHANGED_IND_CONFIRMED + + default: + // No implementation needed. + break; + } +} + +static void +peer_manager_init(bool erase_bonds) +{ + ble_gap_sec_params_t sec_param; + ret_code_t err_code; + + err_code = pm_init(); + APP_ERROR_CHECK(err_code); + + if (erase_bonds) + { + err_code = pm_peers_delete(); + APP_ERROR_CHECK(err_code); + } + + memset(&sec_param, 0, sizeof(ble_gap_sec_params_t)); + + // Security parameters to be used for all security procedures. + sec_param.bond = SEC_PARAM_BOND; + sec_param.mitm = SEC_PARAM_MITM; + sec_param.lesc = SEC_PARAM_LESC; + sec_param.keypress = SEC_PARAM_KEYPRESS; + sec_param.io_caps = SEC_PARAM_IO_CAPABILITIES; + sec_param.oob = SEC_PARAM_OOB; + sec_param.min_key_size = SEC_PARAM_MIN_KEY_SIZE; + sec_param.max_key_size = SEC_PARAM_MAX_KEY_SIZE; + sec_param.kdist_own.enc = 1; + sec_param.kdist_own.id = 1; + sec_param.kdist_peer.enc = 1; + sec_param.kdist_peer.id = 1; + + err_code = pm_sec_params_set(&sec_param); + APP_ERROR_CHECK(err_code); + + err_code = pm_register(pm_evt_handler); + APP_ERROR_CHECK(err_code); +} + +static void +timers_init() +{ + APP_TIMER_INIT(APP_TIMER_PRESCALER, APP_TIMER_OP_QUEUE_SIZE, false); +} + +void +nrf52_ble_init(void) +{ + timers_init(); + ble_stack_init(); + peer_manager_init(false); + gap_params_init(); + services_init(); + advertising_init(); + conn_params_init(); + + advertising_start(); +} + +static void +power_manage() +{ + uint32_t err_code = sd_app_evt_wait(); + APP_ERROR_CHECK(err_code); +} + +// ########################### MP IO functions ########################### + +void +mp_hal_stdout_tx_strn(const char *str, size_t len) +{ + uint32_t err_code; + uint8_t *buf = (uint8_t *)str; + size_t send_len; + + while (len > 0) { + if (len >= BLE_NUS_MAX_DATA_LEN) + send_len = BLE_NUS_MAX_DATA_LEN; + else + send_len = len; + err_code = ble_nus_string_send(&m_nus, buf, send_len); + if (err_code == NRF_SUCCESS) { + len -= send_len; + buf += send_len; + } else if (err_code != NRF_ERROR_INVALID_STATE) { + APP_ERROR_CHECK(err_code); + } + } +} + +int +mp_hal_stdin_rx_chr() +{ + uint8_t byte; + for (;;) { + if (app_fifo_get(&m_nus_rx_fifo, &byte) == NRF_SUCCESS) { + return byte; + } + power_manage(); + } +} diff --git a/nrf52/nrf52_ble.h b/nrf52/nrf52_ble.h new file mode 100644 index 0000000000..26f9d86400 --- /dev/null +++ b/nrf52/nrf52_ble.h @@ -0,0 +1,4 @@ +#pragma once + + +void nrf52_ble_init(void); diff --git a/nrf52/pstorage_platform.h b/nrf52/pstorage_platform.h new file mode 100644 index 0000000000..4de11876b8 --- /dev/null +++ b/nrf52/pstorage_platform.h @@ -0,0 +1,72 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + + /** @cond To make doxygen skip this file */ + +/** @file + * This header contains defines with respect persistent storage that are specific to + * persistent storage implementation and application use case. + */ +#ifndef PSTORAGE_PL_H__ +#define PSTORAGE_PL_H__ + +#include +#include "nrf.h" + +static __INLINE uint16_t pstorage_flash_page_size() +{ + return (uint16_t)NRF_FICR->CODEPAGESIZE; +} + +#define PSTORAGE_FLASH_PAGE_SIZE pstorage_flash_page_size() /**< Size of one flash page. */ +#define PSTORAGE_FLASH_EMPTY_MASK 0xFFFFFFFF /**< Bit mask that defines an empty address in flash. */ + +static __INLINE uint32_t pstorage_flash_page_end() +{ + uint32_t bootloader_addr = NRF_UICR->NRFFW[0]; + + return ((bootloader_addr != PSTORAGE_FLASH_EMPTY_MASK) ? + (bootloader_addr/ PSTORAGE_FLASH_PAGE_SIZE) : NRF_FICR->CODESIZE); +} + +#define PSTORAGE_FLASH_PAGE_END pstorage_flash_page_end() + +#define PSTORAGE_NUM_OF_PAGES 1 /**< Number of flash pages allocated for the pstorage module excluding the swap page, configurable based on system requirements. */ +#define PSTORAGE_MIN_BLOCK_SIZE 0x0010 /**< Minimum size of block that can be registered with the module. Should be configured based on system requirements, recommendation is not have this value to be at least size of word. */ + +#define PSTORAGE_DATA_START_ADDR ((PSTORAGE_FLASH_PAGE_END - PSTORAGE_NUM_OF_PAGES - 1) \ + * PSTORAGE_FLASH_PAGE_SIZE) /**< Start address for persistent data, configurable according to system requirements. */ +#define PSTORAGE_DATA_END_ADDR ((PSTORAGE_FLASH_PAGE_END - 1) * PSTORAGE_FLASH_PAGE_SIZE) /**< End address for persistent data, configurable according to system requirements. */ +#define PSTORAGE_SWAP_ADDR PSTORAGE_DATA_END_ADDR /**< Top-most page is used as swap area for clear and update. */ + +#define PSTORAGE_MAX_BLOCK_SIZE PSTORAGE_FLASH_PAGE_SIZE /**< Maximum size of block that can be registered with the module. Should be configured based on system requirements. And should be greater than or equal to the minimum size. */ +#define PSTORAGE_CMD_QUEUE_SIZE 10 /**< Maximum number of flash access commands that can be maintained by the module for all applications. Configurable. */ + + +/** Abstracts persistently memory block identifier. */ +typedef uint32_t pstorage_block_t; + +typedef struct +{ + uint32_t module_id; /**< Module ID.*/ + pstorage_block_t block_id; /**< Block ID.*/ +} pstorage_handle_t; + +typedef uint16_t pstorage_size_t; /** Size of length and offset fields. */ + +/**@brief Handles Flash Access Result Events. To be called in the system event dispatcher of the application. */ +void pstorage_sys_event_handler (uint32_t sys_evt); + +#endif // PSTORAGE_PL_H__ + +/** @} */ +/** @endcond */ diff --git a/nrf52/qstrdefsport.h b/nrf52/qstrdefsport.h new file mode 100644 index 0000000000..e69de29bb2 From 4f7b5eab7f4e379a2d0eb4676c64630568ec57d2 Mon Sep 17 00:00:00 2001 From: Daniel Tralamazza Date: Thu, 3 Nov 2016 18:42:54 +0100 Subject: [PATCH 002/809] remove dup declaration mp_builtin_open_obj --- nrf52/mpconfigport.h | 1 - 1 file changed, 1 deletion(-) diff --git a/nrf52/mpconfigport.h b/nrf52/mpconfigport.h index c5cf2fc46f..346876b7d9 100644 --- a/nrf52/mpconfigport.h +++ b/nrf52/mpconfigport.h @@ -71,7 +71,6 @@ typedef long mp_off_t; #define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len) // extra built in names to add to the global namespace -extern const struct _mp_obj_fun_builtin_t mp_builtin_open_obj; #define MICROPY_PORT_BUILTINS \ { MP_OBJ_NEW_QSTR(MP_QSTR_open), (mp_obj_t)&mp_builtin_open_obj }, From 70956ea9691d358f552f685c33f9c34f068654ac Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 16 Nov 2016 21:38:25 +0100 Subject: [PATCH 003/809] Base support for nrf51 and nrf52 base without depending on SDK. SoftDevice usage optional. --- nrf5/Makefile | 167 + nrf5/boards/common.ld | 103 + nrf5/boards/nrf51822_aa.ld | 28 + nrf5/boards/nrf51822_aa_s110.ld | 28 + nrf5/boards/nrf51822_ac.ld | 28 + nrf5/boards/nrf51822_ac_s110.ld | 28 + nrf5/boards/nrf51822_ac_s120.ld | 28 + nrf5/boards/nrf51822_ac_s130.ld | 28 + nrf5/boards/nrf52832_aa.ld | 27 + nrf5/boards/nrf52832_aa_s132.ld | 27 + nrf5/boards/nrf52832_aa_s1xx.ld | 129 + nrf5/boards/pca10000/mpconfigboard.h | 60 + nrf5/boards/pca10000/mpconfigboard.mk | 3 + nrf5/boards/pca10000/mpconfigboard_s110.mk | 4 + nrf5/boards/pca10001/mpconfigboard.h | 59 + nrf5/boards/pca10001/mpconfigboard.mk | 3 + nrf5/boards/pca10028/mpconfigboard.h | 60 + nrf5/boards/pca10028/mpconfigboard.mk | 3 + nrf5/boards/pca10028/mpconfigboard_s110.mk | 4 + nrf5/boards/pca10028/mpconfigboard_s120.mk | 4 + nrf5/boards/pca10028/mpconfigboard_s130.mk | 4 + nrf5/boards/pca10031/mpconfigboard.h | 60 + nrf5/boards/pca10031/mpconfigboard.mk | 3 + nrf5/boards/pca10031/mpconfigboard_s110.mk | 4 + nrf5/boards/pca10031/mpconfigboard_s120.mk | 4 + nrf5/boards/pca10031/mpconfigboard_s130.mk | 4 + nrf5/boards/pca10040/mpconfigboard.h | 60 + nrf5/boards/pca10040/mpconfigboard.mk | 3 + nrf5/boards/pca10040/mpconfigboard_s132.mk | 4 + nrf5/boards/pca10040/mpconfigboard_s1xx.mk | 4 + nrf5/device/compiler_abstraction.h | 144 + nrf5/device/nrf.h | 66 + nrf5/device/nrf51/nrf51.h | 1193 ++ nrf5/device/nrf51/nrf51_bitfields.h | 6128 +++++++++ nrf5/device/nrf51/nrf51_deprecated.h | 440 + nrf5/device/nrf51/startup_nrf51.s | 222 + nrf5/device/nrf51/system_nrf51.c | 151 + nrf5/device/nrf51/system_nrf51.h | 69 + nrf5/device/nrf52/nrf51_to_nrf52.h | 952 ++ nrf5/device/nrf52/nrf52.h | 2091 +++ nrf5/device/nrf52/nrf52_bitfields.h | 12630 +++++++++++++++++++ nrf5/device/nrf52/nrf52_name_change.h | 75 + nrf5/device/nrf52/startup_nrf52.s | 250 + nrf5/device/nrf52/system_nrf52.c | 308 + nrf5/device/nrf52/system_nrf52.h | 69 + nrf5/gccollect.c | 52 + nrf5/gccollect.h | 44 + nrf5/hal/hal_uart.c | 125 + nrf5/hal/hal_uart.h | 135 + nrf5/hal/hal_uarte.c | 220 + nrf5/help.c | 62 + nrf5/led.c | 154 + nrf5/led.h | 52 + nrf5/main.c | 161 + nrf5/mkrules.mk | 10 + nrf5/modpyb.c | 48 + nrf5/mpconfigport.h | 185 + nrf5/mphalport.c | 74 + nrf5/mphalport.h | 110 + nrf5/qstrdefsport.h | 27 + nrf5/softdevice/help_sd.h | 38 + nrf5/softdevice/modble.c | 96 + nrf5/softdevice/softdevice.c | 201 + nrf5/softdevice/softdevice.h | 38 + nrf5/uart.c | 442 + nrf5/uart.h | 47 + 66 files changed, 28080 insertions(+) create mode 100644 nrf5/Makefile create mode 100644 nrf5/boards/common.ld create mode 100644 nrf5/boards/nrf51822_aa.ld create mode 100644 nrf5/boards/nrf51822_aa_s110.ld create mode 100644 nrf5/boards/nrf51822_ac.ld create mode 100644 nrf5/boards/nrf51822_ac_s110.ld create mode 100644 nrf5/boards/nrf51822_ac_s120.ld create mode 100644 nrf5/boards/nrf51822_ac_s130.ld create mode 100644 nrf5/boards/nrf52832_aa.ld create mode 100644 nrf5/boards/nrf52832_aa_s132.ld create mode 100644 nrf5/boards/nrf52832_aa_s1xx.ld create mode 100644 nrf5/boards/pca10000/mpconfigboard.h create mode 100644 nrf5/boards/pca10000/mpconfigboard.mk create mode 100644 nrf5/boards/pca10000/mpconfigboard_s110.mk create mode 100644 nrf5/boards/pca10001/mpconfigboard.h create mode 100644 nrf5/boards/pca10001/mpconfigboard.mk create mode 100644 nrf5/boards/pca10028/mpconfigboard.h create mode 100644 nrf5/boards/pca10028/mpconfigboard.mk create mode 100644 nrf5/boards/pca10028/mpconfigboard_s110.mk create mode 100644 nrf5/boards/pca10028/mpconfigboard_s120.mk create mode 100644 nrf5/boards/pca10028/mpconfigboard_s130.mk create mode 100644 nrf5/boards/pca10031/mpconfigboard.h create mode 100644 nrf5/boards/pca10031/mpconfigboard.mk create mode 100644 nrf5/boards/pca10031/mpconfigboard_s110.mk create mode 100644 nrf5/boards/pca10031/mpconfigboard_s120.mk create mode 100644 nrf5/boards/pca10031/mpconfigboard_s130.mk create mode 100644 nrf5/boards/pca10040/mpconfigboard.h create mode 100644 nrf5/boards/pca10040/mpconfigboard.mk create mode 100644 nrf5/boards/pca10040/mpconfigboard_s132.mk create mode 100644 nrf5/boards/pca10040/mpconfigboard_s1xx.mk create mode 100644 nrf5/device/compiler_abstraction.h create mode 100644 nrf5/device/nrf.h create mode 100644 nrf5/device/nrf51/nrf51.h create mode 100644 nrf5/device/nrf51/nrf51_bitfields.h create mode 100644 nrf5/device/nrf51/nrf51_deprecated.h create mode 100644 nrf5/device/nrf51/startup_nrf51.s create mode 100644 nrf5/device/nrf51/system_nrf51.c create mode 100644 nrf5/device/nrf51/system_nrf51.h create mode 100644 nrf5/device/nrf52/nrf51_to_nrf52.h create mode 100644 nrf5/device/nrf52/nrf52.h create mode 100644 nrf5/device/nrf52/nrf52_bitfields.h create mode 100644 nrf5/device/nrf52/nrf52_name_change.h create mode 100644 nrf5/device/nrf52/startup_nrf52.s create mode 100644 nrf5/device/nrf52/system_nrf52.c create mode 100644 nrf5/device/nrf52/system_nrf52.h create mode 100644 nrf5/gccollect.c create mode 100644 nrf5/gccollect.h create mode 100644 nrf5/hal/hal_uart.c create mode 100644 nrf5/hal/hal_uart.h create mode 100644 nrf5/hal/hal_uarte.c create mode 100644 nrf5/help.c create mode 100644 nrf5/led.c create mode 100644 nrf5/led.h create mode 100644 nrf5/main.c create mode 100644 nrf5/mkrules.mk create mode 100644 nrf5/modpyb.c create mode 100644 nrf5/mpconfigport.h create mode 100644 nrf5/mphalport.c create mode 100644 nrf5/mphalport.h create mode 100644 nrf5/qstrdefsport.h create mode 100644 nrf5/softdevice/help_sd.h create mode 100644 nrf5/softdevice/modble.c create mode 100644 nrf5/softdevice/softdevice.c create mode 100644 nrf5/softdevice/softdevice.h create mode 100644 nrf5/uart.c create mode 100644 nrf5/uart.h diff --git a/nrf5/Makefile b/nrf5/Makefile new file mode 100644 index 0000000000..5e6c2ca374 --- /dev/null +++ b/nrf5/Makefile @@ -0,0 +1,167 @@ +# Select the board to build for: if not given on the command line, +# then default to pca10040. +BOARD ?= pca10040 +ifeq ($(wildcard boards/$(BOARD)/.),) +$(error Invalid BOARD specified) +endif + +# If SoftDevice is selected, try to use that one. +SD ?= none +SD_LOWER = $(shell echo $(SD) | tr '[:upper:]' '[:lower:]') + +# TODO: Verify that it is a valid target. + + +ifeq ($(SD), none) + # If the build directory is not given, make it reflect the board name. + BUILD ?= build-$(BOARD) + include ../py/mkenv.mk + include boards/$(BOARD)/mpconfigboard.mk +else + # If the build directory is not given, make it reflect the board name. + BUILD ?= build-$(BOARD)-$(SD_LOWER) + include ../py/mkenv.mk + include boards/$(BOARD)/mpconfigboard_$(SD_LOWER).mk +endif + +# qstr definitions (must come before including py.mk) +QSTR_DEFS = qstrdefsport.h + +# include py core make definitions +include ../py/py.mk + +CROSS_COMPILE = arm-none-eabi- + +MCU_VARIANT_LOWER = $(shell echo $(MCU_VARIANT) | tr '[:upper:]' '[:lower:]') + +INC = -I. +INC += -I.. +INC += -I$(BUILD) +INC += -I./device +INC += -I./../lib/cmsis/inc +INC += -I./device +INC += -I./device/$(MCU_VARIANT_LOWER) +INC += -I./hal +INC += -I./hal/$(MCU_VARIANT_LOWER) +INC += -I./drivers +INC += -I../lib/mp-readline + +NRF_DEFINES = -D$(MCU_VARIANT) +NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET + +CFLAGS_CORTEX_M = -mthumb -mabi=aapcs -fsingle-precision-constant -Wdouble-promotion + +CFLAGS_MCU_m4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard + +CFLAGS_MCU_m0 = $(CFLAGS_CORTEX_M) --short-enums -mtune=cortex-m0 -mcpu=cortex-m0 -mfloat-abi=soft -fno-builtin + +CFLAGS = $(CFLAGS_MCU_$(MCU_SERIES)) +CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) +CFLAGS += -Iboards/$(BOARD) + +LDFLAGS = $(CFLAGS) +LDFLAGS += -Xlinker -Map=$(@:.elf=.map) +LDFLAGS += -mthumb -mabi=aapcs -T $(LD_FILE) +LDFLAGS += -mcpu=cortex-m0 + +#Debugging/Optimization +ifeq ($(DEBUG), 1) +CFLAGS += -O0 -ggdb +LDFLAGS += -O0 +else +CFLAGS += -Os -DNDEBUG +LDFLAGS += -Os +endif + +LIBS = + +SRC_LIB = $(addprefix lib/,\ + libc/string0.c \ + mp-readline/readline.c \ + utils/pyexec.c \ + utils/pyhelp.c \ + ) + +SRC_C = \ + main.c \ + device/$(MCU_VARIANT_LOWER)/system_$(MCU_VARIANT_LOWER).c \ + modpyb.c \ + led.c \ + mphalport.c \ + uart.c \ + help.c \ + gccollect.c \ + +ifeq ($(NRF_SOFTDEVICE),NRF_S1XX_SOFTDEVICE) + SRC_C += \ + hal/hal_uarte.c \ + softdevice/modble.c \ + softdevice/softdevice.c + + CFLAGS += -I./softdevice + CFLAGS += -I./softdevice/s1xx/headers + CFLAGS += -I./softdevice/s1xx/headers/nrf52 + CFLAGS += -DBLUETOOTH_SD=100 + CFLAGS += -DBLUETOOTH_SD_DEBUG=1 + +else ifeq ($(NRF_SOFTDEVICE),NRF_S132_SOFTDEVICE) + SRC_C += \ + hal/hal_uarte.c \ + softdevice/modble.c \ + softdevice/softdevice.c + + CFLAGS += -I./softdevice + CFLAGS += -I./softdevice/s132/headers + CFLAGS += -I./softdevice/s132/headers/nrf52 + CFLAGS += -DBLUETOOTH_SD=132 + CFLAGS += -DBLUETOOTH_SD_DEBUG=1 +else ifeq ($(NRF_SOFTDEVICE),NRF_S110_SOFTDEVICE) + SRC_C += \ + hal/hal_uart.c \ + softdevice/modble.c \ + softdevice/softdevice.c + + CFLAGS += -I./softdevice + CFLAGS += -I./softdevice/s110/headers + CFLAGS += -DBLUETOOTH_SD=110 + CFLAGS += -DBLUETOOTH_SD_DEBUG=1 +else ifeq ($(NRF_SOFTDEVICE),NRF_S130_SOFTDEVICE) + SRC_C += \ + hal/hal_uart.c \ + softdevice/modble.c \ + softdevice/softdevice.c + + CFLAGS += -I./softdevice + CFLAGS += -I./softdevice/s130/headers + CFLAGS += -DBLUETOOTH_SD=130 + CFLAGS += -DBLUETOOTH_SD_DEBUG=1 +else + SRC_C += \ + hal/hal_uart.c +endif + +SRC_S = \ + device/$(MCU_VARIANT_LOWER)/startup_$(MCU_VARIANT_LOWER).s \ + +OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o)) +OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o)) + + + +.phony: all flash + +all: $(BUILD)/firmware.elf binary hex + +flash: $(BUILD)/firmware.elf + nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT_LOWER) + nrfjprog --pinreset -f $(MCU_VARIANT_LOWER) + +$(BUILD)/firmware.elf: $(OBJ) + $(ECHO) "LINK $@" + $(Q)$(CC) $(LDFLAGS) -o $@ $(OBJ) $(LIBS) + $(Q)$(SIZE) $@ + +SRC_QSTR += $(SRC_C) $(SRC_MOD) $(SRC_LIB) + +include ../py/mkrules.mk +include mkrules.mk diff --git a/nrf5/boards/common.ld b/nrf5/boards/common.ld new file mode 100644 index 0000000000..fd2dc70461 --- /dev/null +++ b/nrf5/boards/common.ld @@ -0,0 +1,103 @@ +/* define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + } >FLASH_ISR + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + /* *(.glue_7) */ /* glue arm to thumb code */ + /* *(.glue_7t) */ /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + } >FLASH_TEXT + + /* + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + */ + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + _ram_start = .; /* create a global symbol at ram start for garbage collector */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM AT> FLASH_TEXT + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start; used by startup code */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ + } >RAM + + /* this is to define the start of the heap, and make sure we have a minimum size */ + .heap : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + _heap_start = .; /* define a global symbol at heap start */ + . = . + _minimum_heap_size; + } >RAM + + /* this just checks there is enough RAM for the stack */ + .stack : + { + . = ALIGN(4); + . = . + _minimum_stack_size; + . = ALIGN(4); + } >RAM + + /* Remove information from the standard libraries */ + /* + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + */ + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/nrf5/boards/nrf51822_aa.ld b/nrf5/boards/nrf51822_aa.ld new file mode 100644 index 0000000000..ddbd5847fb --- /dev/null +++ b/nrf5/boards/nrf51822_aa.ld @@ -0,0 +1,28 @@ +/* + GNU linker script for NRF52 blank w/ no SoftDevice +*/ +/* Specify the memory areas */ +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x00000000, LENGTH = 0x000400 /* sector 0, 1 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03FC00 /* 255 KiB */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x004000 /* 16 KiB */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 10K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20001000; /* tunable */ + +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf51822_aa_s110.ld b/nrf5/boards/nrf51822_aa_s110.ld new file mode 100644 index 0000000000..ef9a2c2f44 --- /dev/null +++ b/nrf5/boards/nrf51822_aa_s110.ld @@ -0,0 +1,28 @@ +/* + GNU linker script for NRF51822 AA w/ S110 8.0.0 SoftDevice +*/ +/* Specify the memory areas */ +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 175 KiB */ + RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x002000 /* 9.89 KiB */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 4K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20003000; /* tunable */ + +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf51822_ac.ld b/nrf5/boards/nrf51822_ac.ld new file mode 100644 index 0000000000..51fd503b58 --- /dev/null +++ b/nrf5/boards/nrf51822_ac.ld @@ -0,0 +1,28 @@ +/* + GNU linker script for NRF52 blank w/ no SoftDevice +*/ +/* Specify the memory areas */ +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x00000000, LENGTH = 0x000400 /* sector 0, 1 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03F000 /* 255 KiB */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x008000 /* 32 KiB */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 10K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20001000; /* tunable */ + +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf51822_ac_s110.ld b/nrf5/boards/nrf51822_ac_s110.ld new file mode 100644 index 0000000000..e1863c8bab --- /dev/null +++ b/nrf5/boards/nrf51822_ac_s110.ld @@ -0,0 +1,28 @@ +/* + GNU linker script for NRF51822 AC w/ S110 8.0.0 SoftDevice +*/ +/* Specify the memory areas */ +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 175 KiB */ + RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x006000 /* 9.89 KiB */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 4K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20003000; /* tunable */ + +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf51822_ac_s120.ld b/nrf5/boards/nrf51822_ac_s120.ld new file mode 100644 index 0000000000..e7a67f2b08 --- /dev/null +++ b/nrf5/boards/nrf51822_ac_s120.ld @@ -0,0 +1,28 @@ +/* + GNU linker script for NRF51822 AC w/ S120 2.1.0 SoftDevice +*/ +/* Specify the memory areas */ +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x0001D000, LENGTH = 0x000400 /* sector 0, 1 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x0001D400, LENGTH = 0x027c00 /* 139 KiB */ + RAM (xrw) : ORIGIN = 0x20002800, LENGTH = 0x005800 /* 22 KiB */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 4K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20003000; /* tunable */ + +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf51822_ac_s130.ld b/nrf5/boards/nrf51822_ac_s130.ld new file mode 100644 index 0000000000..f0e3bdbabb --- /dev/null +++ b/nrf5/boards/nrf51822_ac_s130.ld @@ -0,0 +1,28 @@ +/* + GNU linker script for NRF51822 AC w/ S130 2.0.0 SoftDevice +*/ +/* Specify the memory areas */ +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x0001b000, LENGTH = 0x000400 /* sector 0, 1 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x0001b400, LENGTH = 0x024c00 /* 147 KiB */ + RAM (xrw) : ORIGIN = 0x20001870, LENGTH = 0x002970 /* 9.89 KiB */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 6K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20002000; /* tunable */ + +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf52832_aa.ld b/nrf5/boards/nrf52832_aa.ld new file mode 100644 index 0000000000..cfdbe073cf --- /dev/null +++ b/nrf5/boards/nrf52832_aa.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for NRF52 blank w/ no SoftDevice +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 256 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x00000000, LENGTH = 0x001000 /* sector 0, 4 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x07F000 /* 508 KiB */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x010000 /* 64 KiB */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20005000; /* tunable */ + +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf52832_aa_s132.ld b/nrf5/boards/nrf52832_aa_s132.ld new file mode 100644 index 0000000000..9aabfac28e --- /dev/null +++ b/nrf5/boards/nrf52832_aa_s132.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for NRF52 w/ s132 3.0.0 SoftDevice +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x0001f000, LENGTH = 0x001000 /* sector 0, 4 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 /* 396 KiB */ + RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 57.89 KiB, give 8KiB headroom for softdevice */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20005000; /* tunable */ + +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf52832_aa_s1xx.ld b/nrf5/boards/nrf52832_aa_s1xx.ld new file mode 100644 index 0000000000..781492085c --- /dev/null +++ b/nrf5/boards/nrf52832_aa_s1xx.ld @@ -0,0 +1,129 @@ +/* + GNU linker script for NRF52 w/ s1xx prototype3 softdevice (IPv6) +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0001F000, LENGTH = 0x61000 + FLASH_ISR (rx) : ORIGIN = 0x0001F000, LENGTH = 0x00400 + FLASH_TEXT (rx) : ORIGIN = 0x0001F400, LENGTH = 0x60c00 + RAM (xrw) : ORIGIN = 0x20002800, LENGTH = 0x0D800 +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 6K; +_minimum_heap_size = 16K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20005000; /* tunable */ + +/* define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + } >FLASH_ISR + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + /* *(.glue_7) */ /* glue arm to thumb code */ + /* *(.glue_7t) */ /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + } >FLASH_TEXT + + /* + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + */ + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + _ram_start = .; /* create a global symbol at ram start for garbage collector */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM AT> FLASH_TEXT + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start; used by startup code */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ + } >RAM + + /* this is to define the start of the heap, and make sure we have a minimum size */ + .heap : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + _heap_start = .; /* define a global symbol at heap start */ + . = . + _minimum_heap_size; + } >RAM + + /* this just checks there is enough RAM for the stack */ + .stack : + { + . = ALIGN(4); + . = . + _minimum_stack_size; + . = ALIGN(4); + } >RAM + + /* Remove information from the standard libraries */ + /* + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + */ + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf5/boards/pca10000/mpconfigboard.h new file mode 100644 index 0000000000..f922fe8761 --- /dev/null +++ b/nrf5/boards/pca10000/mpconfigboard.h @@ -0,0 +1,60 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define PCA10000 + +#define MICROPY_HW_BOARD_NAME "PCA10000" +#define MICROPY_HW_MCU_NAME "NRF51822" +#define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" + +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_TRICOLOR (1) +#define MICROPY_HW_LED_PULLUP (1) + +#define MICROPY_HW_LED_RED (21) // RED +#define MICROPY_HW_LED_GREEN (22) // GREEN +#define MICROPY_HW_LED_BLUE (23) // BLUE + +// UART config +#define MICROPY_HW_UART1_RX (11) +#define MICROPY_HW_UART1_TX (9) +#define MICROPY_HW_UART1_CTS (10) +#define MICROPY_HW_UART1_RTS (8) +#define MICROPY_HW_UART1_HWFC (0) + +#define HELP_TEXT_BOARD_LED "1,2,3" diff --git a/nrf5/boards/pca10000/mpconfigboard.mk b/nrf5/boards/pca10000/mpconfigboard.mk new file mode 100644 index 0000000000..915ac0992c --- /dev/null +++ b/nrf5/boards/pca10000/mpconfigboard.mk @@ -0,0 +1,3 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_aa.ld diff --git a/nrf5/boards/pca10000/mpconfigboard_s110.mk b/nrf5/boards/pca10000/mpconfigboard_s110.mk new file mode 100644 index 0000000000..f3d9fc9ce4 --- /dev/null +++ b/nrf5/boards/pca10000/mpconfigboard_s110.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_aa_s110.ld +NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE diff --git a/nrf5/boards/pca10001/mpconfigboard.h b/nrf5/boards/pca10001/mpconfigboard.h new file mode 100644 index 0000000000..4e723efcb7 --- /dev/null +++ b/nrf5/boards/pca10001/mpconfigboard.h @@ -0,0 +1,59 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define PCA10001 + +#define MICROPY_HW_BOARD_NAME "PCA10001" +#define MICROPY_HW_MCU_NAME "NRF51822" +#define MICROPY_PY_SYS_PLATFORM "nrf51-DK" + +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_COUNT (2) +#define MICROPY_HW_LED_PULLUP (0) + +#define MICROPY_HW_LED1 (18) // LED1 +#define MICROPY_HW_LED2 (19) // LED2 + +// UART config +#define MICROPY_HW_UART1_RX (11) +#define MICROPY_HW_UART1_TX (9) +#define MICROPY_HW_UART1_CTS (10) +#define MICROPY_HW_UART1_RTS (8) +#define MICROPY_HW_UART1_HWFC (1) + +#define HELP_TEXT_BOARD_LED "1,2" diff --git a/nrf5/boards/pca10001/mpconfigboard.mk b/nrf5/boards/pca10001/mpconfigboard.mk new file mode 100644 index 0000000000..915ac0992c --- /dev/null +++ b/nrf5/boards/pca10001/mpconfigboard.mk @@ -0,0 +1,3 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_aa.ld diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h new file mode 100644 index 0000000000..cde989bc25 --- /dev/null +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -0,0 +1,60 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define PCA10028 + +#define MICROPY_HW_BOARD_NAME "PCA10028" +#define MICROPY_HW_MCU_NAME "NRF51822" +#define MICROPY_PY_SYS_PLATFORM "nrf51-DK" + +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_PULLUP (1) + +#define MICROPY_HW_LED1 (21) // LED1 +#define MICROPY_HW_LED2 (22) // LED2 +#define MICROPY_HW_LED3 (23) // LED3 +#define MICROPY_HW_LED4 (24) // LED4 + +// UART config +#define MICROPY_HW_UART1_RX (11) +#define MICROPY_HW_UART1_TX (9) +#define MICROPY_HW_UART1_CTS (10) +#define MICROPY_HW_UART1_RTS (8) +#define MICROPY_HW_UART1_HWFC (0) + +#define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10028/mpconfigboard.mk b/nrf5/boards/pca10028/mpconfigboard.mk new file mode 100644 index 0000000000..7a221a10e7 --- /dev/null +++ b/nrf5/boards/pca10028/mpconfigboard.mk @@ -0,0 +1,3 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_ac.ld diff --git a/nrf5/boards/pca10028/mpconfigboard_s110.mk b/nrf5/boards/pca10028/mpconfigboard_s110.mk new file mode 100644 index 0000000000..5684d66f79 --- /dev/null +++ b/nrf5/boards/pca10028/mpconfigboard_s110.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_ac_s110.ld +NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE \ No newline at end of file diff --git a/nrf5/boards/pca10028/mpconfigboard_s120.mk b/nrf5/boards/pca10028/mpconfigboard_s120.mk new file mode 100644 index 0000000000..ce8df7382a --- /dev/null +++ b/nrf5/boards/pca10028/mpconfigboard_s120.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_ac_s120.ld +NRF_SOFTDEVICE = NRF_S120_SOFTDEVICE diff --git a/nrf5/boards/pca10028/mpconfigboard_s130.mk b/nrf5/boards/pca10028/mpconfigboard_s130.mk new file mode 100644 index 0000000000..47b423f764 --- /dev/null +++ b/nrf5/boards/pca10028/mpconfigboard_s130.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_ac_s130.ld +NRF_SOFTDEVICE = NRF_S130_SOFTDEVICE diff --git a/nrf5/boards/pca10031/mpconfigboard.h b/nrf5/boards/pca10031/mpconfigboard.h new file mode 100644 index 0000000000..2cda988ff0 --- /dev/null +++ b/nrf5/boards/pca10031/mpconfigboard.h @@ -0,0 +1,60 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define PCA10031 + +#define MICROPY_HW_BOARD_NAME "PCA10031" +#define MICROPY_HW_MCU_NAME "NRF51822" +#define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" + +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_TRICOLOR (1) +#define MICROPY_HW_LED_PULLUP (1) + +#define MICROPY_HW_LED_RED (21) // RED +#define MICROPY_HW_LED_GREEN (22) // GREEN +#define MICROPY_HW_LED_BLUE (23) // BLUE + +// UART config +#define MICROPY_HW_UART1_RX (11) +#define MICROPY_HW_UART1_TX (9) +#define MICROPY_HW_UART1_CTS (10) +#define MICROPY_HW_UART1_RTS (8) +#define MICROPY_HW_UART1_HWFC (0) + +#define HELP_TEXT_BOARD_LED "1,2,3" diff --git a/nrf5/boards/pca10031/mpconfigboard.mk b/nrf5/boards/pca10031/mpconfigboard.mk new file mode 100644 index 0000000000..7a221a10e7 --- /dev/null +++ b/nrf5/boards/pca10031/mpconfigboard.mk @@ -0,0 +1,3 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_ac.ld diff --git a/nrf5/boards/pca10031/mpconfigboard_s110.mk b/nrf5/boards/pca10031/mpconfigboard_s110.mk new file mode 100644 index 0000000000..5684d66f79 --- /dev/null +++ b/nrf5/boards/pca10031/mpconfigboard_s110.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_ac_s110.ld +NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE \ No newline at end of file diff --git a/nrf5/boards/pca10031/mpconfigboard_s120.mk b/nrf5/boards/pca10031/mpconfigboard_s120.mk new file mode 100644 index 0000000000..ce8df7382a --- /dev/null +++ b/nrf5/boards/pca10031/mpconfigboard_s120.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_ac_s120.ld +NRF_SOFTDEVICE = NRF_S120_SOFTDEVICE diff --git a/nrf5/boards/pca10031/mpconfigboard_s130.mk b/nrf5/boards/pca10031/mpconfigboard_s130.mk new file mode 100644 index 0000000000..47b423f764 --- /dev/null +++ b/nrf5/boards/pca10031/mpconfigboard_s130.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m0 +MCU_VARIANT = NRF51 +LD_FILE = boards/nrf51822_ac_s130.ld +NRF_SOFTDEVICE = NRF_S130_SOFTDEVICE diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h new file mode 100644 index 0000000000..af655f0209 --- /dev/null +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -0,0 +1,60 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define PCA10040 + +#define MICROPY_HW_BOARD_NAME "PCA10040" +#define MICROPY_HW_MCU_NAME "NRF52832" +#define MICROPY_PY_SYS_PLATFORM "nrf52-DK" + +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_PULLUP (1) + +#define MICROPY_HW_LED1 (17) // LED1 +#define MICROPY_HW_LED2 (18) // LED2 +#define MICROPY_HW_LED3 (19) // LED3 +#define MICROPY_HW_LED4 (20) // LED4 + +// UART config +#define MICROPY_HW_UART1_RX (8) +#define MICROPY_HW_UART1_TX (6) +#define MICROPY_HW_UART1_CTS (7) +#define MICROPY_HW_UART1_RTS (5) +#define MICROPY_HW_UART1_HWFC (1) + +#define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10040/mpconfigboard.mk b/nrf5/boards/pca10040/mpconfigboard.mk new file mode 100644 index 0000000000..6c9796e710 --- /dev/null +++ b/nrf5/boards/pca10040/mpconfigboard.mk @@ -0,0 +1,3 @@ +MCU_SERIES = m4 +MCU_VARIANT = NRF52 +LD_FILE = boards/nrf52832_aa.ld diff --git a/nrf5/boards/pca10040/mpconfigboard_s132.mk b/nrf5/boards/pca10040/mpconfigboard_s132.mk new file mode 100644 index 0000000000..65f3c58c3c --- /dev/null +++ b/nrf5/boards/pca10040/mpconfigboard_s132.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m4 +MCU_VARIANT = NRF52 +LD_FILE = boards/nrf52832_aa_s132.ld +NRF_SOFTDEVICE = NRF_S132_SOFTDEVICE diff --git a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk new file mode 100644 index 0000000000..efd61002ad --- /dev/null +++ b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m4 +MCU_VARIANT = NRF52 +LD_FILE = boards/nrf52832_aa_s1xx.ld +NRF_SOFTDEVICE = NRF_S1XX_SOFTDEVICE diff --git a/nrf5/device/compiler_abstraction.h b/nrf5/device/compiler_abstraction.h new file mode 100644 index 0000000000..df9f3dbdee --- /dev/null +++ b/nrf5/device/compiler_abstraction.h @@ -0,0 +1,144 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _COMPILER_ABSTRACTION_H +#define _COMPILER_ABSTRACTION_H + +/*lint ++flb "Enter library region" */ + +#if defined ( __CC_ARM ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #define GET_SP() __current_sp() + +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #define GET_SP() __get_SP() + +#elif defined ( __GNUC__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + #define GET_SP() gcc_current_sp() + + static inline unsigned int gcc_current_sp(void) + { + register unsigned sp __ASM("sp"); + return sp; + } + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + /* Not defined for TASKING. */ + #ifndef __PACKED + #define __PACKED + #endif + + #define GET_SP() __get_MSP() + +#endif + +/*lint --flb "Leave library region" */ + +#endif diff --git a/nrf5/device/nrf.h b/nrf5/device/nrf.h new file mode 100644 index 0000000000..6c9676cc48 --- /dev/null +++ b/nrf5/device/nrf.h @@ -0,0 +1,66 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_H +#define NRF_H + +/* MDK version */ +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 9 +#define MDK_MICRO_VERSION 0 + +#if defined(_WIN32) + /* Do not include nrf51 specific files when building for PC host */ +#elif defined(__unix) + /* Do not include nrf51 specific files when building for PC host */ +#elif defined(__APPLE__) + /* Do not include nrf51 specific files when building for PC host */ +#else + + /* Family selection for family includes. */ + #if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + #elif defined (NRF52) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" + #else + #error "Device family must be defined. See nrf.h." + #endif /* NRF51, NRF52 */ + + #include "compiler_abstraction.h" + +#endif /* _WIN32 || __unix || __APPLE__ */ + +#endif /* NRF_H */ + diff --git a/nrf5/device/nrf51/nrf51.h b/nrf5/device/nrf51/nrf51.h new file mode 100644 index 0000000000..e657fa75c0 --- /dev/null +++ b/nrf5/device/nrf51/nrf51.h @@ -0,0 +1,1193 @@ + +/****************************************************************************************************//** + * @file nrf51.h + * + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for + * nrf51 from Nordic Semiconductor. + * + * @version V522 + * @date 30. September 2016 + * + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nrf51.svd' Version 522, + * + * @par Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + +/** @addtogroup nrf51 + * @{ + */ + +#ifndef NRF51_H +#define NRF51_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UART0_IRQn = 2, /*!< 2 UART0 */ + SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ + SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + ADC_IRQn = 7, /*!< 7 ADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ + SWI0_IRQn = 20, /*!< 20 SWI0 */ + SWI1_IRQn = 21, /*!< 21 SWI1 */ + SWI2_IRQn = 22, /*!< 22 SWI2 */ + SWI3_IRQn = 23, /*!< 23 SWI3 */ + SWI4_IRQn = 24, /*!< 24 SWI4 */ + SWI5_IRQn = 25 /*!< 25 SWI5 */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ +#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_nrf51.h" /*!< nrf51 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + +typedef struct { + __O uint32_t EN; /*!< Enable channel group. */ + __O uint32_t DIS; /*!< Disable channel group. */ +} PPI_TASKS_CHG_Type; + +typedef struct { + __IO uint32_t EEP; /*!< Channel event end-point. */ + __IO uint32_t TEP; /*!< Channel task end-point. */ +} PPI_CH_Type; + + +/* ================================================================================ */ +/* ================ POWER ================ */ +/* ================================================================================ */ + + +/** + * @brief Power Control. (POWER) + */ + +typedef struct { /*!< POWER Structure */ + __I uint32_t RESERVED0[30]; + __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */ + __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */ + __I uint32_t RESERVED1[34]; + __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[61]; + __IO uint32_t RESETREAS; /*!< Reset reason. */ + __I uint32_t RESERVED4[9]; + __I uint32_t RAMSTATUS; /*!< Ram status register. */ + __I uint32_t RESERVED5[53]; + __O uint32_t SYSTEMOFF; /*!< System off register. */ + __I uint32_t RESERVED6[3]; + __IO uint32_t POFCON; /*!< Power failure configuration. */ + __I uint32_t RESERVED7[2]; + __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained + register. */ + __I uint32_t RESERVED8; + __IO uint32_t RAMON; /*!< Ram on/off. */ + __I uint32_t RESERVED9[7]; + __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register + is a retained register. */ + __I uint32_t RESERVED10[3]; + __IO uint32_t RAMONB; /*!< Ram on/off. */ + __I uint32_t RESERVED11[8]; + __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */ + __I uint32_t RESERVED12[291]; + __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */ +} NRF_POWER_Type; + + +/* ================================================================================ */ +/* ================ CLOCK ================ */ +/* ================================================================================ */ + + +/** + * @brief Clock control. (CLOCK) + */ + +typedef struct { /*!< CLOCK Structure */ + __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */ + __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */ + __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */ + __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */ + __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */ + __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */ + __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */ + __I uint32_t RESERVED0[57]; + __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */ + __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */ + __I uint32_t RESERVED1; + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */ + __I uint32_t RESERVED2[124]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */ + __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */ + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */ + __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */ + __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is + triggered. */ + __I uint32_t RESERVED5[62]; + __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */ + __I uint32_t RESERVED6[7]; + __IO uint32_t CTIV; /*!< Calibration timer interval. */ + __I uint32_t RESERVED7[5]; + __IO uint32_t XTALFREQ; /*!< Crystal frequency. */ +} NRF_CLOCK_Type; + + +/* ================================================================================ */ +/* ================ MPU ================ */ +/* ================================================================================ */ + + +/** + * @brief Memory Protection Unit. (MPU) + */ + +typedef struct { /*!< MPU Structure */ + __I uint32_t RESERVED0[330]; + __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */ + __IO uint32_t RLENR0; /*!< Length of RAM region 0. */ + __I uint32_t RESERVED1[52]; + __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */ + __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */ +} NRF_MPU_Type; + + +/* ================================================================================ */ +/* ================ RADIO ================ */ +/* ================================================================================ */ + + +/** + * @brief The radio. (RADIO) + */ + +typedef struct { /*!< RADIO Structure */ + __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */ + __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */ + __O uint32_t TASKS_START; /*!< Start radio. */ + __O uint32_t TASKS_STOP; /*!< Stop radio. */ + __O uint32_t TASKS_DISABLE; /*!< Disable radio. */ + __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */ + __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */ + __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */ + __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */ + __I uint32_t RESERVED0[55]; + __IO uint32_t EVENTS_READY; /*!< Ready event. */ + __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */ + __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */ + __IO uint32_t EVENTS_END; /*!< End event. */ + __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */ + __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */ + __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */ + __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI + sample is ready for readout at the RSSISAMPLE register. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */ + __I uint32_t RESERVED2[53]; + __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */ + __I uint32_t RESERVED3[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED4[61]; + __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */ + __I uint32_t RESERVED5; + __I uint32_t RXMATCH; /*!< Received address. */ + __I uint32_t RXCRC; /*!< Received CRC. */ + __I uint32_t DAI; /*!< Device address match index. */ + __I uint32_t RESERVED6[60]; + __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */ + __IO uint32_t FREQUENCY; /*!< Frequency. */ + __IO uint32_t TXPOWER; /*!< Output power. */ + __IO uint32_t MODE; /*!< Data rate and modulation. */ + __IO uint32_t PCNF0; /*!< Packet configuration 0. */ + __IO uint32_t PCNF1; /*!< Packet configuration 1. */ + __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */ + __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */ + __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */ + __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */ + __IO uint32_t TXADDRESS; /*!< Transmit address select. */ + __IO uint32_t RXADDRESSES; /*!< Receive address select. */ + __IO uint32_t CRCCNF; /*!< CRC configuration. */ + __IO uint32_t CRCPOLY; /*!< CRC polynomial. */ + __IO uint32_t CRCINIT; /*!< CRC initial value. */ + __IO uint32_t TEST; /*!< Test features enable register. */ + __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */ + __I uint32_t RSSISAMPLE; /*!< RSSI sample. */ + __I uint32_t RESERVED7; + __I uint32_t STATE; /*!< Current radio state. */ + __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */ + __I uint32_t RESERVED8[2]; + __IO uint32_t BCC; /*!< Bit counter compare. */ + __I uint32_t RESERVED9[39]; + __IO uint32_t DAB[8]; /*!< Device address base segment. */ + __IO uint32_t DAP[8]; /*!< Device address prefix. */ + __IO uint32_t DACNF; /*!< Device address match configuration. */ + __I uint32_t RESERVED10[56]; + __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */ + __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */ + __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */ + __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */ + __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */ + __I uint32_t RESERVED11[561]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_RADIO_Type; + + +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter. (UART) + */ + +typedef struct { /*!< UART Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */ + __I uint32_t RESERVED1[56]; + __IO uint32_t EVENTS_CTS; /*!< CTS activated. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */ + __I uint32_t RESERVED2[4]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */ + __I uint32_t RESERVED3; + __IO uint32_t EVENTS_ERROR; /*!< Error detected. */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */ + __I uint32_t RESERVED5[46]; + __IO uint32_t SHORTS; /*!< Shortcuts for UART. */ + __I uint32_t RESERVED6[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED7[93]; + __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */ + __I uint32_t RESERVED8[31]; + __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */ + __I uint32_t RESERVED9; + __IO uint32_t PSELRTS; /*!< Pin select for RTS. */ + __IO uint32_t PSELTXD; /*!< Pin select for TXD. */ + __IO uint32_t PSELCTS; /*!< Pin select for CTS. */ + __IO uint32_t PSELRXD; /*!< Pin select for RXD. */ + __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. + Once read the character is consumed. If read when no character + available, the UART will stop working. */ + __O uint32_t TXD; /*!< TXD register. */ + __I uint32_t RESERVED10; + __IO uint32_t BAUDRATE; /*!< UART Baudrate. */ + __I uint32_t RESERVED11[17]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */ + __I uint32_t RESERVED12[675]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_UART_Type; + + +/* ================================================================================ */ +/* ================ SPI ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI master 0. (SPI) + */ + +typedef struct { /*!< SPI Structure */ + __I uint32_t RESERVED0[66]; + __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */ + __I uint32_t RESERVED1[126]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable SPI. */ + __I uint32_t RESERVED3; + __IO uint32_t PSELSCK; /*!< Pin select for SCK. */ + __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ + __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ + __I uint32_t RESERVED4; + __I uint32_t RXD; /*!< RX data. */ + __IO uint32_t TXD; /*!< TX data. */ + __I uint32_t RESERVED5; + __IO uint32_t FREQUENCY; /*!< SPI frequency */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED7[681]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_SPI_Type; + + +/* ================================================================================ */ +/* ================ TWI ================ */ +/* ================================================================================ */ + + +/** + * @brief Two-wire interface master 0. (TWI) + */ + +typedef struct { /*!< TWI Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */ + __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */ + __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */ + __I uint32_t RESERVED4[4]; + __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */ + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */ + __I uint32_t RESERVED8[45]; + __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ + __I uint32_t RESERVED9[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED10[110]; + __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */ + __I uint32_t RESERVED11[14]; + __IO uint32_t ENABLE; /*!< Enable two-wire master. */ + __I uint32_t RESERVED12; + __IO uint32_t PSELSCL; /*!< Pin select for SCL. */ + __IO uint32_t PSELSDA; /*!< Pin select for SDA. */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RX data register. */ + __IO uint32_t TXD; /*!< TX data register. */ + __I uint32_t RESERVED14; + __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */ + __I uint32_t RESERVED15[24]; + __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */ + __I uint32_t RESERVED16[668]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_TWI_Type; + + +/* ================================================================================ */ +/* ================ SPIS ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI slave 1. (SPIS) + */ + +typedef struct { /*!< SPIS Structure */ + __I uint32_t RESERVED0[9]; + __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */ + __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */ + __I uint32_t RESERVED1[54]; + __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED3[5]; + __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */ + __I uint32_t RESERVED4[53]; + __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */ + __I uint32_t RESERVED5[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED6[61]; + __I uint32_t SEMSTAT; /*!< Semaphore status. */ + __I uint32_t RESERVED7[15]; + __IO uint32_t STATUS; /*!< Status from last transaction. */ + __I uint32_t RESERVED8[47]; + __IO uint32_t ENABLE; /*!< Enable SPIS. */ + __I uint32_t RESERVED9; + __IO uint32_t PSELSCK; /*!< Pin select for SCK. */ + __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ + __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ + __IO uint32_t PSELCSN; /*!< Pin select for CSN. */ + __I uint32_t RESERVED10[7]; + __IO uint32_t RXDPTR; /*!< RX data pointer. */ + __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */ + __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ + __I uint32_t RESERVED11; + __IO uint32_t TXDPTR; /*!< TX data pointer. */ + __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */ + __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ + __I uint32_t RESERVED12; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED13; + __IO uint32_t DEF; /*!< Default character. */ + __I uint32_t RESERVED14[24]; + __IO uint32_t ORC; /*!< Over-read character. */ + __I uint32_t RESERVED15[654]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_SPIS_Type; + + +/* ================================================================================ */ +/* ================ GPIOTE ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO tasks and events. (GPIOTE) + */ + +typedef struct { /*!< GPIOTE Structure */ + __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */ + __I uint32_t RESERVED1[27]; + __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */ + __I uint32_t RESERVED2[97]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[129]; + __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */ + __I uint32_t RESERVED4[695]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_GPIOTE_Type; + + +/* ================================================================================ */ +/* ================ ADC ================ */ +/* ================================================================================ */ + + +/** + * @brief Analog to digital converter. (ADC) + */ + +typedef struct { /*!< ADC Structure */ + __O uint32_t TASKS_START; /*!< Start an ADC conversion. */ + __O uint32_t TASKS_STOP; /*!< Stop ADC. */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[61]; + __I uint32_t BUSY; /*!< ADC busy register. */ + __I uint32_t RESERVED3[63]; + __IO uint32_t ENABLE; /*!< ADC enable. */ + __IO uint32_t CONFIG; /*!< ADC configuration register. */ + __I uint32_t RESULT; /*!< Result of ADC conversion. */ + __I uint32_t RESERVED4[700]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_ADC_Type; + + +/* ================================================================================ */ +/* ================ TIMER ================ */ +/* ================================================================================ */ + + +/** + * @brief Timer 0. (TIMER) + */ + +typedef struct { /*!< TIMER Structure */ + __O uint32_t TASKS_START; /*!< Start Timer. */ + __O uint32_t TASKS_STOP; /*!< Stop Timer. */ + __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */ + __O uint32_t TASKS_CLEAR; /*!< Clear timer. */ + __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */ + __I uint32_t RESERVED0[11]; + __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ + __I uint32_t RESERVED1[60]; + __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ + __I uint32_t RESERVED2[44]; + __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */ + __I uint32_t RESERVED3[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED4[126]; + __IO uint32_t MODE; /*!< Timer Mode selection. */ + __IO uint32_t BITMODE; /*!< Sets timer behaviour. */ + __I uint32_t RESERVED5; + __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source + clock frequency is divided by 2^SCALE. */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CC[4]; /*!< Capture/compare registers. */ + __I uint32_t RESERVED7[683]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_TIMER_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief Real time counter 0. (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __O uint32_t TASKS_START; /*!< Start RTC Counter. */ + __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */ + __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */ + __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */ + __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */ + __I uint32_t RESERVED1[14]; + __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ + __I uint32_t RESERVED2[109]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[13]; + __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */ + __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives + the value of EVTEN. */ + __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register + gives the value of EVTEN. */ + __I uint32_t RESERVED4[110]; + __I uint32_t COUNTER; /*!< Current COUNTER value. */ + __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). + Must be written when RTC is STOPed. */ + __I uint32_t RESERVED5[13]; + __IO uint32_t CC[4]; /*!< Capture/compare registers. */ + __I uint32_t RESERVED6[683]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_RTC_Type; + + +/* ================================================================================ */ +/* ================ TEMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Temperature Sensor. (TEMP) + */ + +typedef struct { /*!< TEMP Structure */ + __O uint32_t TASKS_START; /*!< Start temperature measurement. */ + __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[127]; + __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */ + __I uint32_t RESERVED3[700]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_TEMP_Type; + + +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ + + +/** + * @brief Random Number Generator. (RNG) + */ + +typedef struct { /*!< RNG Structure */ + __O uint32_t TASKS_START; /*!< Start the random number generator. */ + __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */ + __I uint32_t RESERVED1[63]; + __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */ + __I uint32_t RESERVED3[126]; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t VALUE; /*!< RNG random number. */ + __I uint32_t RESERVED4[700]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_RNG_Type; + + +/* ================================================================================ */ +/* ================ ECB ================ */ +/* ================================================================================ */ + + +/** + * @brief AES ECB Mode Encryption. (ECB) + */ + +typedef struct { /*!< ECB Structure */ + __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this + will not initiate a new encryption and the ERRORECB event will + be triggered. */ + __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running, + this will will trigger the ERRORECB event. */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */ + __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an + error. */ + __I uint32_t RESERVED1[127]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[126]; + __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */ + __I uint32_t RESERVED3[701]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_ECB_Type; + + +/* ================================================================================ */ +/* ================ AAR ================ */ +/* ================================================================================ */ + + +/** + * @brief Accelerated Address Resolver. (AAR) + */ + +typedef struct { /*!< AAR Structure */ + __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK + data structure. */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */ + __I uint32_t RESERVED1[61]; + __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */ + __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */ + __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[61]; + __I uint32_t STATUS; /*!< Resolution status. */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable AAR. */ + __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */ + __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */ + __I uint32_t RESERVED5; + __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during + resolution. A minimum of 3 bytes must be reserved. */ + __I uint32_t RESERVED6[697]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_AAR_Type; + + +/* ================================================================================ */ +/* ================ CCM ================ */ +/* ================================================================================ */ + + +/** + * @brief AES CCM Mode Encryption. (CCM) + */ + +typedef struct { /*!< CCM Structure */ + __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by + itself when completed. */ + __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when + completed. */ + __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */ + __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */ + __IO uint32_t EVENTS_ERROR; /*!< Error happened. */ + __I uint32_t RESERVED1[61]; + __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[61]; + __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< CCM enable. */ + __IO uint32_t MODE; /*!< Operation mode. */ + __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */ + __IO uint32_t INPTR; /*!< Pointer to the input packet. */ + __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during + resolution. A minimum of 43 bytes must be reserved. */ + __I uint32_t RESERVED5[697]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_CCM_Type; + + +/* ================================================================================ */ +/* ================ WDT ================ */ +/* ================================================================================ */ + + +/** + * @brief Watchdog Timer. (WDT) + */ + +typedef struct { /*!< WDT Structure */ + __O uint32_t TASKS_START; /*!< Start the watchdog. */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[61]; + __I uint32_t RUNSTATUS; /*!< Watchdog running status. */ + __I uint32_t REQSTATUS; /*!< Request status. */ + __I uint32_t RESERVED3[63]; + __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */ + __IO uint32_t RREN; /*!< Reload request enable. */ + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED4[60]; + __O uint32_t RR[8]; /*!< Reload requests registers. */ + __I uint32_t RESERVED5[631]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_WDT_Type; + + +/* ================================================================================ */ +/* ================ QDEC ================ */ +/* ================================================================================ */ + + +/** + * @brief Rotary decoder. (QDEC) + */ + +typedef struct { /*!< QDEC Structure */ + __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */ + __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */ + __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers, + and clears the ACC registers. */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */ + __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and + ACC register different than zero. */ + __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */ + __I uint32_t RESERVED1[61]; + __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable the QDEC. */ + __IO uint32_t LEDPOL; /*!< LED output pin polarity. */ + __IO uint32_t SAMPLEPER; /*!< Sample period. */ + __I int32_t SAMPLE; /*!< Motion sample value. */ + __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */ + __I int32_t ACC; /*!< Accumulated valid transitions register. */ + __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC + task. */ + __IO uint32_t PSELLED; /*!< Pin select for LED output. */ + __IO uint32_t PSELA; /*!< Pin select for phase A input. */ + __IO uint32_t PSELB; /*!< Pin select for phase B input. */ + __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */ + __I uint32_t RESERVED4[5]; + __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */ + __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */ + __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC + task. */ + __I uint32_t RESERVED5[684]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_QDEC_Type; + + +/* ================================================================================ */ +/* ================ LPCOMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Low power comparator. (LPCOMP) + */ + +typedef struct { /*!< LPCOMP Structure */ + __O uint32_t TASKS_START; /*!< Start the comparator. */ + __O uint32_t TASKS_STOP; /*!< Stop the comparator. */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */ + __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */ + __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ + __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Result of last compare. */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */ + __IO uint32_t PSEL; /*!< Input pin select. */ + __IO uint32_t REFSEL; /*!< Reference select. */ + __IO uint32_t EXTREFSEL; /*!< External reference select. */ + __I uint32_t RESERVED5[4]; + __IO uint32_t ANADETECT; /*!< Analog detect configuration. */ + __I uint32_t RESERVED6[694]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_LPCOMP_Type; + + +/* ================================================================================ */ +/* ================ SWI ================ */ +/* ================================================================================ */ + + +/** + * @brief SW Interrupts. (SWI) + */ + +typedef struct { /*!< SWI Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_SWI_Type; + + +/* ================================================================================ */ +/* ================ NVMC ================ */ +/* ================================================================================ */ + + +/** + * @brief Non Volatile Memory Controller. (NVMC) + */ + +typedef struct { /*!< NVMC Structure */ + __I uint32_t RESERVED0[256]; + __I uint32_t READY; /*!< Ready flag. */ + __I uint32_t RESERVED1[64]; + __IO uint32_t CONFIG; /*!< Configuration register. */ + + union { + __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */ + __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */ + }; + __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */ + __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */ + __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */ +} NRF_NVMC_Type; + + +/* ================================================================================ */ +/* ================ PPI ================ */ +/* ================================================================================ */ + + +/** + * @brief PPI controller. (PPI) + */ + +typedef struct { /*!< PPI Structure */ + PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */ + __I uint32_t RESERVED0[312]; + __IO uint32_t CHEN; /*!< Channel enable. */ + __IO uint32_t CHENSET; /*!< Channel enable set. */ + __IO uint32_t CHENCLR; /*!< Channel enable clear. */ + __I uint32_t RESERVED1; + PPI_CH_Type CH[16]; /*!< PPI Channel. */ + __I uint32_t RESERVED2[156]; + __IO uint32_t CHG[4]; /*!< Channel group configuration. */ +} NRF_PPI_Type; + + +/* ================================================================================ */ +/* ================ FICR ================ */ +/* ================================================================================ */ + + +/** + * @brief Factory Information Configuration. (FICR) + */ + +typedef struct { /*!< FICR Structure */ + __I uint32_t RESERVED0[4]; + __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */ + __I uint32_t CODESIZE; /*!< Code memory size in pages. */ + __I uint32_t RESERVED1[4]; + __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */ + __I uint32_t PPFC; /*!< Pre-programmed factory code present. */ + __I uint32_t RESERVED2; + __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */ + + union { + __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is + kept for backward compatinility purposes. Use SIZERAMBLOCKS + instead. */ + __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */ + }; + __I uint32_t RESERVED3[5]; + __I uint32_t CONFIGID; /*!< Configuration identifier. */ + __I uint32_t DEVICEID[2]; /*!< Device identifier. */ + __I uint32_t RESERVED4[6]; + __I uint32_t ER[4]; /*!< Encryption root. */ + __I uint32_t IR[4]; /*!< Identity root. */ + __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */ + __I uint32_t DEVICEADDR[2]; /*!< Device address. */ + __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */ + __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit + mode. */ + __I uint32_t RESERVED5[10]; + __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit + mode. */ +} NRF_FICR_Type; + + +/* ================================================================================ */ +/* ================ UICR ================ */ +/* ================================================================================ */ + + +/** + * @brief User Information Configuration. (UICR) + */ + +typedef struct { /*!< UICR Structure */ + __IO uint32_t CLENR0; /*!< Length of code region 0. */ + __IO uint32_t RBPCONF; /*!< Readback protection configuration. */ + __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */ + __I uint32_t RESERVED0; + __I uint32_t FWID; /*!< Firmware ID. */ + + union { + __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */ + __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */ + }; + __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */ + __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */ +} NRF_UICR_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + + +/** + * @brief General purpose input and output. (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __I uint32_t RESERVED0[321]; + __IO uint32_t OUT; /*!< Write GPIO port. */ + __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */ + __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */ + __I uint32_t IN; /*!< Read GPIO port. */ + __IO uint32_t DIR; /*!< Direction of GPIO pins. */ + __IO uint32_t DIRSET; /*!< DIR set register. */ + __IO uint32_t DIRCLR; /*!< DIR clear register. */ + __I uint32_t RESERVED1[120]; + __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */ +} NRF_GPIO_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_MPU_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_ADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI_BASE 0x40014000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_GPIO_BASE 0x50000000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) +#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE) +#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) +#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) +#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) +#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) +#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) +#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group nrf51 */ +/** @} */ /* End of group Nordic Semiconductor */ + +#ifdef __cplusplus +} +#endif + + +#endif /* nrf51_H */ + diff --git a/nrf5/device/nrf51/nrf51_bitfields.h b/nrf5/device/nrf51/nrf51_bitfields.h new file mode 100644 index 0000000000..6505a0bb06 --- /dev/null +++ b/nrf5/device/nrf51/nrf51_bitfields.h @@ -0,0 +1,6128 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __NRF51_BITS_H +#define __NRF51_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver. */ + +/* Register: AAR_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on NOTRESOLVED event. */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on RESOLVED event. */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on END event. */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: AAR_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on NOTRESOLVED event. */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on RESOLVED event. */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on ENDKSGEN event. */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status. */ + +/* Bits 3..0 : The IRK used last time an address was resolved. */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR. */ + +/* Bits 1..0 : Enable AAR. */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */ +#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */ + +/* Register: AAR_NIRK */ +/* Description: Number of Identity root Keys in the IRK data structure. */ + +/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: ADC */ +/* Description: Analog to digital converter. */ + +/* Register: ADC_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 0 : Enable interrupt on END event. */ +#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: ADC_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 0 : Disable interrupt on END event. */ +#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: ADC_BUSY */ +/* Description: ADC busy register. */ + +/* Bit 0 : ADC busy register. */ +#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */ +#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */ +#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */ +#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */ + +/* Register: ADC_ENABLE */ +/* Description: ADC enable. */ + +/* Bits 1..0 : ADC enable. */ +#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */ +#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */ + +/* Register: ADC_CONFIG */ +/* Description: ADC configuration register. */ + +/* Bits 17..16 : ADC external reference pin selection. */ +#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */ +#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */ +#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */ +#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */ + +/* Bits 15..8 : ADC analog pin selection. */ +#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */ +#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */ + +/* Bits 6..5 : ADC reference selection. */ +#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */ +#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */ +#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */ +#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */ +#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */ + +/* Bits 4..2 : ADC input selection. */ +#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */ +#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */ +#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */ + +/* Bits 1..0 : ADC resolution. */ +#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */ +#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */ +#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */ +#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */ +#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */ + +/* Register: ADC_RESULT */ +/* Description: Result of ADC conversion. */ + +/* Bits 9..0 : Result of ADC conversion. */ +#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ + +/* Register: ADC_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption. */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcuts for the CCM. */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: CCM_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on ERROR event. */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on ENDCRYPT event. */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on ENDKSGEN event. */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: CCM_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on ERROR event. */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on ENDCRYPT event. */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on ENDKSGEN event. */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: CCM_MICSTATUS */ +/* Description: CCM RX MIC check result. */ + +/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */ + +/* Register: CCM_ENABLE */ +/* Description: CCM enable. */ + +/* Bits 1..0 : CCM enable. */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */ +#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */ + +/* Register: CCM_MODE */ +/* Description: Operation mode. */ + +/* Bit 0 : CCM mode operation. */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */ + +/* Register: CCM_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control. */ + +/* Register: CLOCK_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 4 : Enable interrupt on CTTO event. */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 3 : Enable interrupt on DONE event. */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 4 : Disable interrupt on CTTO event. */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 3 : Disable interrupt on DONE event. */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Task HFCLKSTART trigger status. */ + +/* Bit 0 : Task HFCLKSTART trigger status. */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: High frequency clock status. */ + +/* Bit 16 : State for the HFCLK. */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */ + +/* Bit 0 : Active clock source for the HF clock. */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Task LFCLKSTART triggered status. */ + +/* Bit 0 : Task LFCLKSTART triggered status. */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: Low frequency clock status. */ + +/* Bit 16 : State for the LF clock. */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */ + +/* Bits 1..0 : Active clock source for the LF clock. */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ + +/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK clock. */ + +/* Bits 1..0 : Clock source. */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval. */ + +/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_XTALFREQ */ +/* Description: Crystal frequency. */ + +/* Bits 7..0 : External Xtal frequency selection. */ +#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ +#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ +#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ +#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption. */ + +/* Register: ECB_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 1 : Enable interrupt on ERRORECB event. */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on ENDECB event. */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: ECB_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 1 : Disable interrupt on ERRORECB event. */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on ENDECB event. */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: ECB_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: FICR */ +/* Description: Factory Information Configuration. */ + +/* Register: FICR_PPFC */ +/* Description: Pre-programmed factory code present. */ + +/* Bits 7..0 : Pre-programmed factory code present. */ +#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ +#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ +#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ +#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ + +/* Register: FICR_CONFIGID */ +/* Description: Configuration identifier. */ + +/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */ +#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */ +#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */ + +/* Bits 15..0 : Hardware Identification Number. */ +#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ +#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type. */ + +/* Bit 0 : Device address type. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */ + +/* Register: FICR_OVERRIDEEN */ +/* Description: Radio calibration override enable. */ + +/* Bit 3 : Override default values for BLE_1Mbit mode. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ + +/* Bit 0 : Override default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ + + +/* Peripheral: GPIO */ +/* Description: General purpose input and output. */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register. */ + +/* Bit 31 : Set as output pin 31. */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */ + +/* Bit 30 : Set as output pin 30. */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */ + +/* Bit 29 : Set as output pin 29. */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */ + +/* Bit 28 : Set as output pin 28. */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */ + +/* Bit 27 : Set as output pin 27. */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */ + +/* Bit 26 : Set as output pin 26. */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */ + +/* Bit 25 : Set as output pin 25. */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */ + +/* Bit 24 : Set as output pin 24. */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */ + +/* Bit 23 : Set as output pin 23. */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */ + +/* Bit 22 : Set as output pin 22. */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */ + +/* Bit 21 : Set as output pin 21. */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */ + +/* Bit 20 : Set as output pin 20. */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */ + +/* Bit 19 : Set as output pin 19. */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */ + +/* Bit 18 : Set as output pin 18. */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */ + +/* Bit 17 : Set as output pin 17. */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */ + +/* Bit 16 : Set as output pin 16. */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */ + +/* Bit 15 : Set as output pin 15. */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */ + +/* Bit 14 : Set as output pin 14. */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */ + +/* Bit 13 : Set as output pin 13. */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */ + +/* Bit 12 : Set as output pin 12. */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */ + +/* Bit 11 : Set as output pin 11. */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */ + +/* Bit 10 : Set as output pin 10. */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */ + +/* Bit 9 : Set as output pin 9. */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */ + +/* Bit 8 : Set as output pin 8. */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */ + +/* Bit 7 : Set as output pin 7. */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */ + +/* Bit 6 : Set as output pin 6. */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */ + +/* Bit 5 : Set as output pin 5. */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */ + +/* Bit 4 : Set as output pin 4. */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */ + +/* Bit 3 : Set as output pin 3. */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */ + +/* Bit 2 : Set as output pin 2. */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */ + +/* Bit 1 : Set as output pin 1. */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */ + +/* Bit 0 : Set as output pin 0. */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register. */ + +/* Bit 31 : Set as input pin 31. */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 30 : Set as input pin 30. */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 29 : Set as input pin 29. */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 28 : Set as input pin 28. */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 27 : Set as input pin 27. */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 26 : Set as input pin 26. */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 25 : Set as input pin 25. */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 24 : Set as input pin 24. */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 23 : Set as input pin 23. */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 22 : Set as input pin 22. */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 21 : Set as input pin 21. */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 20 : Set as input pin 20. */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 19 : Set as input pin 19. */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 18 : Set as input pin 18. */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 17 : Set as input pin 17. */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 16 : Set as input pin 16. */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 15 : Set as input pin 15. */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 14 : Set as input pin 14. */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 13 : Set as input pin 13. */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 12 : Set as input pin 12. */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 11 : Set as input pin 11. */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 10 : Set as input pin 10. */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 9 : Set as input pin 9. */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 8 : Set as input pin 8. */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 7 : Set as input pin 7. */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 6 : Set as input pin 6. */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 5 : Set as input pin 5. */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 4 : Set as input pin 4. */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 3 : Set as input pin 3. */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 2 : Set as input pin 2. */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 1 : Set as input pin 1. */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 0 : Set as input pin 0. */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Configuration of GPIO pins. */ + +/* Bits 17..16 : Pin sensing mechanism. */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */ +#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */ +#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */ + +/* Bits 10..8 : Drive configuration. */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */ + +/* Bits 3..2 : Pull-up or -down configuration. */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */ +#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */ +#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */ + +/* Bit 1 : Connect or disconnect input path. */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */ + +/* Bit 0 : Pin direction. */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO tasks and events. */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 31 : Enable interrupt on PORT event. */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 3 : Enable interrupt on IN[3] event. */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on IN[2] event. */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on IN[1] event. */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on IN[0] event. */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 31 : Disable interrupt on PORT event. */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 3 : Disable interrupt on IN[3] event. */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on IN[2] event. */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on IN[1] event. */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on IN[0] event. */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Channel configuration registers. */ + +/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */ + +/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ + +/* Bits 12..8 : Pin select. */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */ +#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */ +#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */ + +/* Register: GPIOTE_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low power comparator. */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcuts for the LPCOMP. */ + +/* Bit 4 : Shortcut between CROSS event and STOP task. */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between UP event and STOP task. */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 2 : Shortcut between DOWN event and STOP task. */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 1 : Shortcut between RADY event and STOP task. */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 3 : Enable interrupt on CROSS event. */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on UP event. */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on DOWN event. */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on READY event. */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 3 : Disable interrupt on CROSS event. */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on UP event. */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on DOWN event. */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on READY event. */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: LPCOMP_RESULT */ +/* Description: Result of last compare. */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is bellow the reference threshold. */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable the LPCOMP. */ + +/* Bits 1..0 : Enable or disable LPCOMP. */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */ +#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select. */ + +/* Bits 2..0 : Analog input pin select. */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select. */ + +/* Bits 2..0 : Reference select. */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select. */ + +/* Bit 0 : External analog reference pin selection. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration. */ + +/* Bits 1..0 : Analog detect configuration. */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */ + +/* Register: LPCOMP_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: MPU */ +/* Description: Memory Protection Unit. */ + +/* Register: MPU_PERR0 */ +/* Description: Configuration of peripherals in mpu regions. */ + +/* Bit 31 : PPI region configuration. */ +#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */ +#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */ +#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 30 : NVMC region configuration. */ +#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */ +#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */ +#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 19 : LPCOMP region configuration. */ +#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 18 : QDEC region configuration. */ +#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ +#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */ +#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 17 : RTC1 region configuration. */ +#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */ +#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */ +#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 16 : WDT region configuration. */ +#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */ +#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */ +#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 15 : CCM and AAR region configuration. */ +#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */ +#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */ +#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 14 : ECB region configuration. */ +#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */ +#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */ +#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 13 : RNG region configuration. */ +#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */ +#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */ +#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 12 : TEMP region configuration. */ +#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */ +#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */ +#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 11 : RTC0 region configuration. */ +#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */ +#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */ +#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 10 : TIMER2 region configuration. */ +#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */ +#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */ +#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 9 : TIMER1 region configuration. */ +#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */ +#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */ +#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 8 : TIMER0 region configuration. */ +#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */ +#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */ +#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 7 : ADC region configuration. */ +#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */ +#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */ +#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 6 : GPIOTE region configuration. */ +#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */ +#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */ +#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 4 : SPI1 and TWI1 region configuration. */ +#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */ +#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */ +#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 3 : SPI0 and TWI0 region configuration. */ +#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */ +#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */ +#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 2 : UART0 region configuration. */ +#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */ +#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */ +#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 1 : RADIO region configuration. */ +#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */ +#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */ +#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 0 : POWER_CLOCK region configuration. */ +#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */ +#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */ +#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Register: MPU_PROTENSET0 */ +/* Description: Erase and write protection bit enable set register. */ + +/* Bit 31 : Protection enable for region 31. */ +#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ +#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */ +#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 30 : Protection enable for region 30. */ +#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */ +#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */ +#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 29 : Protection enable for region 29. */ +#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */ +#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */ +#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 28 : Protection enable for region 28. */ +#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */ +#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */ +#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 27 : Protection enable for region 27. */ +#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */ +#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */ +#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 26 : Protection enable for region 26. */ +#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */ +#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */ +#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 25 : Protection enable for region 25. */ +#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */ +#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */ +#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 24 : Protection enable for region 24. */ +#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */ +#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */ +#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 23 : Protection enable for region 23. */ +#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */ +#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */ +#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 22 : Protection enable for region 22. */ +#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */ +#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */ +#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 21 : Protection enable for region 21. */ +#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */ +#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */ +#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 20 : Protection enable for region 20. */ +#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */ +#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */ +#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 19 : Protection enable for region 19. */ +#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */ +#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */ +#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 18 : Protection enable for region 18. */ +#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */ +#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */ +#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 17 : Protection enable for region 17. */ +#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */ +#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */ +#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 16 : Protection enable for region 16. */ +#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */ +#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */ +#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 15 : Protection enable for region 15. */ +#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */ +#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */ +#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 14 : Protection enable for region 14. */ +#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */ +#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */ +#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 13 : Protection enable for region 13. */ +#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */ +#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */ +#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 12 : Protection enable for region 12. */ +#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */ +#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */ +#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 11 : Protection enable for region 11. */ +#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */ +#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */ +#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 10 : Protection enable for region 10. */ +#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */ +#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */ +#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 9 : Protection enable for region 9. */ +#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */ +#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */ +#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 8 : Protection enable for region 8. */ +#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */ +#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */ +#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 7 : Protection enable for region 7. */ +#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */ +#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */ +#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 6 : Protection enable for region 6. */ +#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */ +#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */ +#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 5 : Protection enable for region 5. */ +#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */ +#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */ +#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 4 : Protection enable for region 4. */ +#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */ +#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */ +#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 3 : Protection enable for region 3. */ +#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */ +#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */ +#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 2 : Protection enable for region 2. */ +#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */ +#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */ +#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 1 : Protection enable for region 1. */ +#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */ +#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */ +#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 0 : Protection enable for region 0. */ +#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */ +#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */ +#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ + +/* Register: MPU_PROTENSET1 */ +/* Description: Erase and write protection bit enable set register. */ + +/* Bit 31 : Protection enable for region 63. */ +#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ +#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */ +#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 30 : Protection enable for region 62. */ +#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */ +#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */ +#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 29 : Protection enable for region 61. */ +#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */ +#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */ +#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 28 : Protection enable for region 60. */ +#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */ +#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */ +#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 27 : Protection enable for region 59. */ +#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */ +#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */ +#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 26 : Protection enable for region 58. */ +#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */ +#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */ +#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 25 : Protection enable for region 57. */ +#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */ +#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */ +#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 24 : Protection enable for region 56. */ +#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */ +#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */ +#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 23 : Protection enable for region 55. */ +#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */ +#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */ +#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 22 : Protection enable for region 54. */ +#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */ +#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */ +#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 21 : Protection enable for region 53. */ +#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */ +#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */ +#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 20 : Protection enable for region 52. */ +#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */ +#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */ +#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 19 : Protection enable for region 51. */ +#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */ +#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */ +#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 18 : Protection enable for region 50. */ +#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */ +#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */ +#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 17 : Protection enable for region 49. */ +#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */ +#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */ +#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 16 : Protection enable for region 48. */ +#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */ +#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */ +#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 15 : Protection enable for region 47. */ +#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */ +#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */ +#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 14 : Protection enable for region 46. */ +#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */ +#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */ +#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 13 : Protection enable for region 45. */ +#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */ +#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */ +#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 12 : Protection enable for region 44. */ +#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */ +#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */ +#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 11 : Protection enable for region 43. */ +#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */ +#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */ +#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 10 : Protection enable for region 42. */ +#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */ +#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */ +#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 9 : Protection enable for region 41. */ +#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */ +#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */ +#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 8 : Protection enable for region 40. */ +#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */ +#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */ +#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 7 : Protection enable for region 39. */ +#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */ +#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */ +#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 6 : Protection enable for region 38. */ +#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */ +#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */ +#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 5 : Protection enable for region 37. */ +#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */ +#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */ +#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 4 : Protection enable for region 36. */ +#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */ +#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */ +#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 3 : Protection enable for region 35. */ +#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */ +#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */ +#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 2 : Protection enable for region 34. */ +#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */ +#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */ +#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 1 : Protection enable for region 33. */ +#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */ +#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */ +#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 0 : Protection enable for region 32. */ +#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */ +#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */ +#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ + +/* Register: MPU_DISABLEINDEBUG */ +/* Description: Disable erase and write protection mechanism in debug mode. */ + +/* Bit 0 : Disable protection mechanism in debug mode. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ + +/* Register: MPU_PROTBLOCKSIZE */ +/* Description: Erase and write protection block size. */ + +/* Bits 1..0 : Erase and write protection block size. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller. */ + +/* Register: NVMC_READY */ +/* Description: Ready flag. */ + +/* Bit 0 : NVMC ready. */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register. */ + +/* Bits 1..0 : Program write enable. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */ +#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */ +#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory. */ + +/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for start erasing User Information Congfiguration Registers. */ + +/* Bit 0 : It can only be used when all contents of code region 1 are erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */ + + +/* Peripheral: POWER */ +/* Description: Power Control. */ + +/* Register: POWER_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on POFWARN event. */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: POWER_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on POFWARN event. */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason. */ + +/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */ + +/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */ + +/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */ + +/* Bit 3 : Reset from CPU lock-up detected. */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */ + +/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */ + +/* Bit 1 : Reset from watchdog detected. */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */ + +/* Bit 0 : Reset from pin-reset detected. */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Ram status register. */ + +/* Bit 3 : RAM block 3 status. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ + +/* Bit 2 : RAM block 2 status. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ + +/* Bit 1 : RAM block 1 status. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ + +/* Bit 0 : RAM block 0 status. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System off register. */ + +/* Bit 0 : Enter system off mode. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */ + +/* Register: POWER_POFCON */ +/* Description: Power failure configuration. */ + +/* Bits 2..1 : Set threshold level. */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */ +#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */ +#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */ +#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */ + +/* Bit 0 : Power failure comparator enable. */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register. This register is a retained register. */ + +/* Bits 7..0 : General purpose retention register. */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_RAMON */ +/* Description: Ram on/off. */ + +/* Bit 17 : RAM block 1 behaviour in OFF mode. */ +#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */ +#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */ + +/* Bit 16 : RAM block 0 behaviour in OFF mode. */ +#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ +#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ + +/* Bit 1 : RAM block 1 behaviour in ON mode. */ +#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */ +#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */ + +/* Bit 0 : RAM block 0 behaviour in ON mode. */ +#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */ +#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */ + +/* Register: POWER_RESET */ +/* Description: Pin reset functionality configuration register. This register is a retained register. */ + +/* Bit 0 : Enable or disable pin reset in debug interface mode. */ +#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ +#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ +#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ +#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ + +/* Register: POWER_RAMONB */ +/* Description: Ram on/off. */ + +/* Bit 17 : RAM block 3 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ + +/* Bit 16 : RAM block 2 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ + +/* Bit 1 : RAM block 3 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ + +/* Bit 0 : RAM block 2 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ + +/* Register: POWER_DCDCEN */ +/* Description: DCDC converter enable configuration register. */ + +/* Bit 0 : Enable DCDC converter. */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ + +/* Register: POWER_DCDCFORCE */ +/* Description: DCDC power-up force register. */ + +/* Bit 1 : DCDC power-up force on. */ +#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ + +/* Bit 0 : DCDC power-up force off. */ +#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ + + +/* Peripheral: PPI */ +/* Description: PPI controller. */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable. */ + +/* Bit 31 : Enable PPI channel 31. */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 30 : Enable PPI channel 30. */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 29 : Enable PPI channel 29. */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 28 : Enable PPI channel 28. */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 27 : Enable PPI channel 27. */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 26 : Enable PPI channel 26. */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 25 : Enable PPI channel 25. */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 24 : Enable PPI channel 24. */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 23 : Enable PPI channel 23. */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 22 : Enable PPI channel 22. */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 21 : Enable PPI channel 21. */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 20 : Enable PPI channel 20. */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 15 : Enable PPI channel 15. */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 14 : Enable PPI channel 14. */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 13 : Enable PPI channel 13. */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 12 : Enable PPI channel 12. */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 11 : Enable PPI channel 11. */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 10 : Enable PPI channel 10. */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 9 : Enable PPI channel 9. */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 8 : Enable PPI channel 8. */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 7 : Enable PPI channel 7. */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 6 : Enable PPI channel 6. */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 5 : Enable PPI channel 5. */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 4 : Enable PPI channel 4. */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 3 : Enable PPI channel 3. */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */ + +/* Bit 2 : Enable PPI channel 2. */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 1 : Enable PPI channel 1. */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 0 : Enable PPI channel 0. */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set. */ + +/* Bit 31 : Enable PPI channel 31. */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 30 : Enable PPI channel 30. */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 29 : Enable PPI channel 29. */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 28 : Enable PPI channel 28. */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 27 : Enable PPI channel 27. */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 26 : Enable PPI channel 26. */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 25 : Enable PPI channel 25. */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 24 : Enable PPI channel 24. */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 23 : Enable PPI channel 23. */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 22 : Enable PPI channel 22. */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 21 : Enable PPI channel 21. */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 20 : Enable PPI channel 20. */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 15 : Enable PPI channel 15. */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 14 : Enable PPI channel 14. */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 13 : Enable PPI channel 13. */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 12 : Enable PPI channel 12. */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 11 : Enable PPI channel 11. */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 10 : Enable PPI channel 10. */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 9 : Enable PPI channel 9. */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 8 : Enable PPI channel 8. */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 7 : Enable PPI channel 7. */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 6 : Enable PPI channel 6. */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 5 : Enable PPI channel 5. */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 4 : Enable PPI channel 4. */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 3 : Enable PPI channel 3. */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 2 : Enable PPI channel 2. */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 1 : Enable PPI channel 1. */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 0 : Enable PPI channel 0. */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear. */ + +/* Bit 31 : Disable PPI channel 31. */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 30 : Disable PPI channel 30. */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 29 : Disable PPI channel 29. */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 28 : Disable PPI channel 28. */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 27 : Disable PPI channel 27. */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 26 : Disable PPI channel 26. */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 25 : Disable PPI channel 25. */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 24 : Disable PPI channel 24. */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 23 : Disable PPI channel 23. */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 22 : Disable PPI channel 22. */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 21 : Disable PPI channel 21. */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 20 : Disable PPI channel 20. */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 15 : Disable PPI channel 15. */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 14 : Disable PPI channel 14. */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 13 : Disable PPI channel 13. */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 12 : Disable PPI channel 12. */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 11 : Disable PPI channel 11. */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 10 : Disable PPI channel 10. */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 9 : Disable PPI channel 9. */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 8 : Disable PPI channel 8. */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 7 : Disable PPI channel 7. */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 6 : Disable PPI channel 6. */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 5 : Disable PPI channel 5. */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 4 : Disable PPI channel 4. */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 3 : Disable PPI channel 3. */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 2 : Disable PPI channel 2. */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 1 : Disable PPI channel 1. */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 0 : Disable PPI channel 0. */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */ + +/* Register: PPI_CHG */ +/* Description: Channel group configuration. */ + +/* Bit 31 : Include CH31 in channel group. */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */ + +/* Bit 30 : Include CH30 in channel group. */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */ + +/* Bit 29 : Include CH29 in channel group. */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */ + +/* Bit 28 : Include CH28 in channel group. */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */ + +/* Bit 27 : Include CH27 in channel group. */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */ + +/* Bit 26 : Include CH26 in channel group. */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */ + +/* Bit 25 : Include CH25 in channel group. */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */ + +/* Bit 24 : Include CH24 in channel group. */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */ + +/* Bit 23 : Include CH23 in channel group. */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */ + +/* Bit 22 : Include CH22 in channel group. */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */ + +/* Bit 21 : Include CH21 in channel group. */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */ + +/* Bit 20 : Include CH20 in channel group. */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */ + +/* Bit 15 : Include CH15 in channel group. */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */ + +/* Bit 14 : Include CH14 in channel group. */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */ + +/* Bit 13 : Include CH13 in channel group. */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */ + +/* Bit 12 : Include CH12 in channel group. */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */ + +/* Bit 11 : Include CH11 in channel group. */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */ + +/* Bit 10 : Include CH10 in channel group. */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */ + +/* Bit 9 : Include CH9 in channel group. */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */ + +/* Bit 8 : Include CH8 in channel group. */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */ + +/* Bit 7 : Include CH7 in channel group. */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */ + +/* Bit 6 : Include CH6 in channel group. */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */ + +/* Bit 5 : Include CH5 in channel group. */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */ + +/* Bit 4 : Include CH4 in channel group. */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */ + +/* Bit 3 : Include CH3 in channel group. */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */ + +/* Bit 2 : Include CH2 in channel group. */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */ + +/* Bit 1 : Include CH1 in channel group. */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */ + +/* Bit 0 : Include CH0 in channel group. */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */ + + +/* Peripheral: QDEC */ +/* Description: Rotary decoder. */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcuts for the QDEC. */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: QDEC_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on ACCOF event. */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on REPORTRDY event. */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on SAMPLERDY event. */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: QDEC_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on ACCOF event. */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on REPORTRDY event. */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on SAMPLERDY event. */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the QDEC. */ + +/* Bit 0 : Enable or disable QDEC. */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity. */ + +/* Bit 0 : LED output pin polarity. */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period. */ + +/* Bits 2..0 : Sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value. */ + +/* Bits 31..0 : Last sample taken in compliment to 2. */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to generate an EVENT_REPORTRDY. */ + +/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable debouncer input filters. */ + +/* Bit 0 : Enable debounce input filters. */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time LED is switched ON before the sample. */ + +/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Accumulated double (error) transitions register. */ + +/* Bits 3..0 : Accumulated double (error) transitions. */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */ + +/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + +/* Register: QDEC_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: RADIO */ +/* Description: The radio. */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcuts for the radio. */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 5 : Shortcut between END event and START task. */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task. */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task. */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 1 : Shortcut between END event and DISABLE task. */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between READY event and START task. */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: RADIO_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 10 : Enable interrupt on BCMATCH event. */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 7 : Enable interrupt on RSSIEND event. */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 6 : Enable interrupt on DEVMISS event. */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 5 : Enable interrupt on DEVMATCH event. */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : Enable interrupt on DISABLED event. */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 3 : Enable interrupt on END event. */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on PAYLOAD event. */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on ADDRESS event. */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on READY event. */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: RADIO_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 10 : Disable interrupt on BCMATCH event. */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 7 : Disable interrupt on RSSIEND event. */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 6 : Disable interrupt on DEVMISS event. */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 5 : Disable interrupt on DEVMATCH event. */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on DISABLED event. */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 3 : Disable interrupt on END event. */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on PAYLOAD event. */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on ADDRESS event. */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on READY event. */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status of received packet. */ + +/* Bit 0 : CRC status of received packet. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address. */ + +/* Bits 2..0 : Logical address in which previous packet was received. */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: Received CRC. */ + +/* Bits 23..0 : CRC field of previously received packet. */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index. */ + +/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency. */ + +/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power. */ + +/* Bits 7..0 : Radio output power. Decision point: TXEN task. */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation. */ + +/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */ +#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */ +#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */ +#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration 0. */ + +/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration 1. */ + +/* Bit 25 : Packet whitening enable. */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */ + +/* Bit 24 : On air endianness of packet length field. Decision point: START task. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload in number of bytes. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0 to 3. */ + +/* Bits 31..24 : Address prefix 3. Decision point: START task. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. Decision point: START task. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. Decision point: START task. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. Decision point: START task. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4 to 7. */ + +/* Bits 31..24 : Address prefix 7. Decision point: START task. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. Decision point: START task. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. Decision point: START task. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. Decision point: START task. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select. */ + +/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select. */ + +/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration. */ + +/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ + +/* Bits 1..0 : CRC length. Decision point: START task. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial. */ + +/* Bits 23..0 : CRC polynomial. Decision point: START task. */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value. */ + +/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TEST */ +/* Description: Test features enable register. */ + +/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ +#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ +#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ + +/* Bit 0 : Constant carrier. Decision point: TXEN task. */ +#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ +#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ + +/* Register: RADIO_TIFS */ +/* Description: Inter Frame Spacing in microseconds. */ + +/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample. */ + +/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state. */ + +/* Bits 3..0 : Current radio state. */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */ +#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */ +#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */ +#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */ +#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */ +#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */ +#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */ +#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */ +#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value. */ + +/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_DAP */ +/* Description: Device address prefix. */ + +/* Bits 15..0 : Device address prefix. */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration. */ + +/* Bit 15 : TxAdd for device address 7. */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6. */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5. */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4. */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3. */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2. */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1. */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0. */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7. */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */ + +/* Bit 6 : Enable or disable device address matching using device address 6. */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */ + +/* Bit 5 : Enable or disable device address matching using device address 5. */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */ + +/* Bit 4 : Enable or disable device address matching using device address 4. */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */ + +/* Bit 3 : Enable or disable device address matching using device address 3. */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */ + +/* Bit 2 : Enable or disable device address matching using device address 2. */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */ + +/* Bit 1 : Enable or disable device address matching using device address 1. */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */ + +/* Bit 0 : Enable or disable device address matching using device address 0. */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */ + +/* Register: RADIO_OVERRIDE0 */ +/* Description: Trim value override register 0. */ + +/* Bits 31..0 : Trim value override 0. */ +#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ +#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ + +/* Register: RADIO_OVERRIDE1 */ +/* Description: Trim value override register 1. */ + +/* Bits 31..0 : Trim value override 1. */ +#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ +#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ + +/* Register: RADIO_OVERRIDE2 */ +/* Description: Trim value override register 2. */ + +/* Bits 31..0 : Trim value override 2. */ +#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ +#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ + +/* Register: RADIO_OVERRIDE3 */ +/* Description: Trim value override register 3. */ + +/* Bits 31..0 : Trim value override 3. */ +#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ +#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ + +/* Register: RADIO_OVERRIDE4 */ +/* Description: Trim value override register 4. */ + +/* Bit 31 : Enable or disable override of default trim values. */ +#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ +#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ +#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ + +/* Bits 27..0 : Trim value override 4. */ +#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ +#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator. */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcuts for the RNG. */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task. */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: RNG_INTENSET */ +/* Description: Interrupt enable set register */ + +/* Bit 0 : Enable interrupt on VALRDY event. */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: RNG_INTENCLR */ +/* Description: Interrupt enable clear register */ + +/* Bit 0 : Disable interrupt on VALRDY event. */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 0 : Digital error correction enable. */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */ + +/* Register: RNG_VALUE */ +/* Description: RNG random number. */ + +/* Bits 7..0 : Generated random number. */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + +/* Register: RNG_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0. */ + +/* Register: RTC_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on COMPARE[3] event. */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 18 : Enable interrupt on COMPARE[2] event. */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 17 : Enable interrupt on COMPARE[1] event. */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 16 : Enable interrupt on COMPARE[0] event. */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on OVRFLW event. */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on TICK event. */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: RTC_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on COMPARE[3] event. */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 18 : Disable interrupt on COMPARE[2] event. */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 17 : Disable interrupt on COMPARE[1] event. */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 16 : Disable interrupt on COMPARE[0] event. */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on OVRFLW event. */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on TICK event. */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: RTC_EVTEN */ +/* Description: Configures event enable routing to PPI for each RTC event. */ + +/* Bit 19 : COMPARE[3] event enable. */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 18 : COMPARE[2] event enable. */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 17 : COMPARE[1] event enable. */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 16 : COMPARE[0] event enable. */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 1 : OVRFLW event enable. */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 0 : TICK event enable. */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */ + +/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */ + +/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */ + +/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */ + +/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */ + +/* Bit 1 : Enable routing to PPI of OVRFLW event. */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */ + +/* Bit 0 : Enable routing to PPI of TICK event. */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ + +/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 1 : Disable routing to PPI of OVRFLW event. */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 0 : Disable routing to PPI of TICK event. */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value. */ + +/* Bits 23..0 : Counter value. */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ + +/* Bits 11..0 : RTC PRESCALER value. */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Capture/compare registers. */ + +/* Bits 23..0 : Compare value. */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + +/* Register: RTC_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: SPI */ +/* Description: SPI master 0. */ + +/* Register: SPI_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on READY event. */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPI_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on READY event. */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI. */ + +/* Bits 2..0 : Enable or disable SPI. */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */ +#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */ + +/* Register: SPI_RXD */ +/* Description: RX data. */ + +/* Bits 7..0 : RX data from last transfer. */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TX data. */ + +/* Bits 7..0 : TX data for next transfer. */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency */ + +/* Bits 31..0 : SPI data rate. */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPI_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: SPIS */ +/* Description: SPI slave 1. */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcuts for SPIS. */ + +/* Bit 2 : Shortcut between END event and the ACQUIRE task. */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: SPIS_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 10 : Enable interrupt on ACQUIRED event. */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : enable interrupt on ENDRX event. */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on END event. */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPIS_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 10 : Disable interrupt on ACQUIRED event. */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on ENDRX event. */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on END event. */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status. */ + +/* Bits 1..0 : Semaphore status. */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction. */ + +/* Bit 1 : RX buffer overflow detected, and prevented. */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */ + +/* Bit 0 : TX buffer overread detected, and prevented. */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPIS. */ + +/* Bits 2..0 : Enable or disable SPIS. */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */ +#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */ + +/* Register: SPIS_MAXRX */ +/* Description: Maximum number of bytes in the receive buffer. */ + +/* Bits 7..0 : Maximum number of bytes in the receive buffer. */ +#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */ +#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */ + +/* Register: SPIS_AMOUNTRX */ +/* Description: Number of bytes received in last granted transaction. */ + +/* Bits 7..0 : Number of bytes received in last granted transaction. */ +#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */ +#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */ + +/* Register: SPIS_MAXTX */ +/* Description: Maximum number of bytes in the transmit buffer. */ + +/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */ +#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */ +#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */ + +/* Register: SPIS_AMOUNTTX */ +/* Description: Number of bytes transmitted in last granted transaction. */ + +/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */ +#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */ +#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPIS_DEF */ +/* Description: Default character. */ + +/* Bits 7..0 : Default character. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character. */ + +/* Bits 7..0 : Over-read character. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + +/* Register: SPIS_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor. */ + +/* Register: TEMP_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 0 : Enable interrupt on DATARDY event. */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: TEMP_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 0 : Disable interrupt on DATARDY event. */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: TEMP_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: TIMER */ +/* Description: Timer 0. */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcuts for Timer. */ + +/* Bit 11 : Shortcut between CC[3] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 10 : Shortcut between CC[2] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 9 : Shortcut between CC[1] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 8 : Shortcut between CC[0] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: TIMER_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on COMPARE[3] */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 18 : Enable interrupt on COMPARE[2] */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 17 : Enable interrupt on COMPARE[1] */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 16 : Enable interrupt on COMPARE[0] */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: TIMER_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on COMPARE[3] */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 18 : Disable interrupt on COMPARE[2] */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 17 : Disable interrupt on COMPARE[1] */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 16 : Disable interrupt on COMPARE[0] */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: TIMER_MODE */ +/* Description: Timer Mode selection. */ + +/* Bit 0 : Select Normal or Counter mode. */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */ + +/* Register: TIMER_BITMODE */ +/* Description: Sets timer behaviour. */ + +/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */ +#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */ +#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */ +#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */ + +/* Register: TIMER_PRESCALER */ +/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */ + +/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: TWI */ +/* Description: Two-wire interface master 0. */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcuts for TWI. */ + +/* Bit 1 : Shortcut between BB event and the STOP task. */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between BB event and the SUSPEND task. */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: TWI_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 18 : Enable interrupt on SUSPENDED event. */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 14 : Enable interrupt on BB event. */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 9 : Enable interrupt on ERROR event. */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 7 : Enable interrupt on TXDSENT event. */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on READY event. */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on STOPPED event. */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: TWI_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 18 : Disable interrupt on SUSPENDED event. */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 14 : Disable interrupt on BB event. */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 9 : Disable interrupt on ERROR event. */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 7 : Disable interrupt on TXDSENT event. */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on RXDREADY event. */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on STOPPED event. */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: TWI_ERRORSRC */ +/* Description: Two-wire error source. Write error field to 1 to clear error. */ + +/* Bit 2 : NACK received after sending a data byte. */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 1 : NACK received after sending the address. */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ + +/* Register: TWI_ENABLE */ +/* Description: Enable two-wire master. */ + +/* Bits 2..0 : Enable or disable W2M */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */ +#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */ + +/* Register: TWI_RXD */ +/* Description: RX data register. */ + +/* Bits 7..0 : RX data from last transfer. */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TX data register. */ + +/* Bits 7..0 : TX data for next transfer. */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: Two-wire frequency. */ + +/* Bits 31..0 : Two-wire master clock frequency. */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the two-wire transfer. */ + +/* Bits 6..0 : Two-wire address. */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWI_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter. */ + +/* Register: UART_SHORTS */ +/* Description: Shortcuts for UART. */ + +/* Bit 4 : Shortcut between NCTS event and STOPRX task. */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between CTS event and STARTRX task. */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: UART_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 17 : Enable interrupt on RXTO event. */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 9 : Enable interrupt on ERROR event. */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 7 : Enable interrupt on TXRDY event. */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on RXRDY event. */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on NCTS event. */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on CTS event. */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: UART_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 17 : Disable interrupt on RXTO event. */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 9 : Disable interrupt on ERROR event. */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 7 : Disable interrupt on TXRDY event. */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on RXRDY event. */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on NCTS event. */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on CTS event. */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source. Write error field to 1 to clear error. */ + +/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART and acquire IOs. */ + +/* Bits 2..0 : Enable or disable UART and acquire IOs. */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */ +#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ + +/* Register: UART_RXD */ +/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ + +/* Bits 7..0 : RX data from previous transfer. Double buffered. */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register. */ + +/* Bits 7..0 : TX data for transfer. */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: UART Baudrate. */ + +/* Bits 31..0 : UART baudrate. */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control register. */ + +/* Bits 3..1 : Include parity bit. */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */ +#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */ + +/* Bit 0 : Hardware flow control. */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */ + +/* Register: UART_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: UICR */ +/* Description: User Information Configuration. */ + +/* Register: UICR_RBPCONF */ +/* Description: Readback protection configuration. */ + +/* Bits 15..8 : Readback protect all code in the device. */ +#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ +#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ +#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ + +/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ +#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ +#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ +#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ +#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ + +/* Register: UICR_XTALFREQ */ +/* Description: Reset value for CLOCK XTALFREQ register. */ + +/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ +#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ +#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ +#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ +#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ + +/* Register: UICR_FWID */ +/* Description: Firmware ID. */ + +/* Bits 15..0 : Identification number for the firmware loaded into the chip. */ +#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */ +#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer. */ + +/* Register: WDT_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 0 : Enable interrupt on TIMEOUT event. */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: WDT_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 0 : Disable interrupt on TIMEOUT event. */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Watchdog running status. */ + +/* Bit 0 : Watchdog running status. */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status. */ + +/* Bit 7 : Request status for RR[7]. */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */ + +/* Bit 6 : Request status for RR[6]. */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */ + +/* Bit 5 : Request status for RR[5]. */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */ + +/* Bit 4 : Request status for RR[4]. */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */ + +/* Bit 3 : Request status for RR[3]. */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */ + +/* Bit 2 : Request status for RR[2]. */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */ + +/* Bit 1 : Request status for RR[1]. */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */ + +/* Bit 0 : Request status for RR[0]. */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */ + +/* Register: WDT_RREN */ +/* Description: Reload request enable. */ + +/* Bit 7 : Enable or disable RR[7] register. */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */ + +/* Bit 6 : Enable or disable RR[6] register. */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */ + +/* Bit 5 : Enable or disable RR[5] register. */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */ + +/* Bit 4 : Enable or disable RR[4] register. */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */ + +/* Bit 3 : Enable or disable RR[3] register. */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */ + +/* Bit 2 : Enable or disable RR[2] register. */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */ + +/* Bit 1 : Enable or disable RR[1] register. */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */ + +/* Bit 0 : Enable or disable RR[0] register. */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */ + +/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */ + +/* Register: WDT_RR */ +/* Description: Reload requests registers. */ + +/* Bits 31..0 : Reload register. */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */ + +/* Register: WDT_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/nrf5/device/nrf51/nrf51_deprecated.h b/nrf5/device/nrf51/nrf51_deprecated.h new file mode 100644 index 0000000000..1a7860f693 --- /dev/null +++ b/nrf5/device/nrf51/nrf51_deprecated.h @@ -0,0 +1,440 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF51_DEPRECATED_H +#define NRF51_DEPRECATED_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and + * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. + */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* LPCOMP */ +/* The interrupt ISR was renamed. Adding old name to the macros. */ +#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn LPCOMP_IRQn +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + + +/* MPU */ +/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */ +#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos +#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk +#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1 +#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0 + + +/* POWER */ +/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_OFFRAM3_Pos (19UL) +#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) +#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) +#define POWER_RAMON_OFFRAM3_RAM3On (1UL) +/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_OFFRAM2_Pos (18UL) +#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) +#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) +#define POWER_RAMON_OFFRAM2_RAM2On (1UL) +/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_ONRAM3_Pos (3UL) +#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) +#define POWER_RAMON_ONRAM3_RAM3Off (0UL) +#define POWER_RAMON_ONRAM3_RAM3On (1UL) +/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_ONRAM2_Pos (2UL) +#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) +#define POWER_RAMON_ONRAM2_RAM2Off (0UL) +#define POWER_RAMON_ONRAM2_RAM2On (1UL) + + +/* RADIO */ +/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */ +#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos +#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk +#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled +#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled +/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */ +#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos +#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk +#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled +#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled + + +/* FICR */ +/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */ +#define SIZERAMBLOCK0 SIZERAMBLOCKS +#define SIZERAMBLOCK1 SIZERAMBLOCKS +#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ +#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_DEPRECATED_H */ + diff --git a/nrf5/device/nrf51/startup_nrf51.s b/nrf5/device/nrf51/startup_nrf51.s new file mode 100644 index 0000000000..b20f3745fa --- /dev/null +++ b/nrf5/device/nrf51/startup_nrf51.s @@ -0,0 +1,222 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 + +.global __Vectors +.global Default_Handler + +.word _sidata +.word _sdata +.word _edata +.word _sbss +.word _ebss + +/* Reset Handler */ + + .equ NRF_POWER_RAMON_ADDRESS, 0x40000524 + .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554 + .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3 + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + .fnstart + + movs R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk + ldr R0, =NRF_POWER_RAMON_ADDRESS + ldr R2, [R0] + orrs R2, R1 + str R2, [R0] + + ldr R0, =NRF_POWER_RAMONB_ADDRESS + ldr R2, [R0] + orrs R2, R1 + str R2, [R0] + + ldr r1, =_sidata + ldr r2, =_sdata + ldr r3, =_edata + + subs r3, r2 + ble LC0 + +LC1: + subs r3, 4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt LC1 + +LC0: + bl SystemInit + bl main + bx lr + + .pool + .cantunwind + .fnend + .size Reset_Handler,.-Reset_Handler + +/* Default Handler */ + + .section ".text" + .section .text.Default_Handler,"ax",%progbits +Default_Handler: + b . + .size Default_Handler, .-Default_Handler + + +/* Vector Table */ + + .section .isr_vector,"a",%progbits + .type __Vectors, %object + .size __Vectors, .-__Vectors + +__Vectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word POWER_CLOCK_IRQHandler + .word RADIO_IRQHandler + .word UART0_IRQHandler + .word SPI0_TWI0_IRQHandler + .word SPI1_TWI1_IRQHandler + .word 0 + .word GPIOTE_IRQHandler + .word ADC_IRQHandler + .word TIMER0_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word RTC0_IRQHandler + .word TEMP_IRQHandler + .word RNG_IRQHandler + .word ECB_IRQHandler + .word CCM_AAR_IRQHandler + .word WDT_IRQHandler + .word RTC1_IRQHandler + .word QDEC_IRQHandler + .word LPCOMP_IRQHandler + .word SWI0_IRQHandler + .word SWI1_IRQHandler + .word SWI2_IRQHandler + .word SWI3_IRQHandler + .word SWI4_IRQHandler + .word SWI5_IRQHandler + +/* Dummy Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ POWER_CLOCK_IRQHandler + IRQ RADIO_IRQHandler + IRQ UART0_IRQHandler + IRQ SPI0_TWI0_IRQHandler + IRQ SPI1_TWI1_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ ADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ LPCOMP_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_IRQHandler + + .end diff --git a/nrf5/device/nrf51/system_nrf51.c b/nrf5/device/nrf51/system_nrf51.c new file mode 100644 index 0000000000..0ad09d5ff7 --- /dev/null +++ b/nrf5/device/nrf51/system_nrf51.c @@ -0,0 +1,151 @@ +/* Copyright (c) 2012 ARM LIMITED + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of ARM nor the names of its contributors may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include +#include +#include "nrf.h" +#include "system_nrf51.h" + +/*lint ++flb "Enter library region" */ + + +#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ + +static bool is_manual_peripheral_setup_needed(void); +static bool is_disabled_in_debug_needed(void); +static bool is_peripheral_domain_setup_needed(void); + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +void SystemInit(void) +{ + /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register. + It can also be done in the application main() function. */ + + /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required + to enable the use of peripherals" found at Product Anomaly document for your device found at + https://www.nordicsemi.com/. The side effect of executing these instructions in the devices + that do not need it is that the new peripherals in the second generation devices (LPCOMP for + example) will not be available. */ + if (is_manual_peripheral_setup_needed()) + { + *(uint32_t volatile *)0x40000504 = 0xC007FFDF; + *(uint32_t volatile *)0x40006C18 = 0x00008000; + } + + /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG + register is incorrect" found at Product Anomaly document for your device found at + https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ + if (is_disabled_in_debug_needed()) + { + NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; + } + + /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices, + as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document + for your device found at https://www.nordicsemi.com/. */ + if (is_peripheral_domain_setup_needed()){ + if (*(uint32_t volatile *)0x4006EC00 != 1){ + *(uint32_t volatile *)0x4006EC00 = 0x9375; + while (*(uint32_t volatile *)0x4006EC00 != 1){ + } + } + *(uint32_t volatile *)0x4006EC14 = 0xC0; + } +} + + +static bool is_manual_peripheral_setup_needed(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + } + + return false; +} + +static bool is_disabled_in_debug_needed(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + } + + return false; +} + +static bool is_peripheral_domain_setup_needed(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xA0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xD0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + } + + return false; +} + +/*lint --flb "Leave library region" */ diff --git a/nrf5/device/nrf51/system_nrf51.h b/nrf5/device/nrf51/system_nrf51.h new file mode 100644 index 0000000000..71c403962e --- /dev/null +++ b/nrf5/device/nrf51/system_nrf51.h @@ -0,0 +1,69 @@ +/* Copyright (c) 2012 ARM LIMITED + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of ARM nor the names of its contributors may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef SYSTEM_NRF51_H +#define SYSTEM_NRF51_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF51_H */ diff --git a/nrf5/device/nrf52/nrf51_to_nrf52.h b/nrf5/device/nrf52/nrf51_to_nrf52.h new file mode 100644 index 0000000000..72dfd91fc0 --- /dev/null +++ b/nrf5/device/nrf52/nrf51_to_nrf52.h @@ -0,0 +1,952 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF51_TO_NRF52_H +#define NRF51_TO_NRF52_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#define UART0_IRQHandler UARTE0_UART0_IRQHandler +#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define ADC_IRQHandler SAADC_IRQHandler +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#define SWI5_IRQHandler SWI5_EGU5_IRQHandler + +#define UART0_IRQn UARTE0_UART0_IRQn +#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#define ADC_IRQn SAADC_IRQn +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define SWI0_IRQn SWI0_EGU0_IRQn +#define SWI1_IRQn SWI1_EGU1_IRQn +#define SWI2_IRQn SWI2_EGU2_IRQn +#define SWI3_IRQn SWI3_EGU3_IRQn +#define SWI4_IRQn SWI4_EGU4_IRQn +#define SWI5_IRQn SWI5_EGU5_IRQn + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#define RBPCONF APPROTECT + +#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled + + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#define NRF_GPIO NRF_P0 +#define NRF_GPIO_BASE NRF_P0_BASE + + +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#define PSELLED PSEL.LED +#define PSELA PSEL.A +#define PSELB PSEL.B + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#define PSELSCK PSEL.SCK +#define PSELMISO PSEL.MISO +#define PSELMOSI PSEL.MOSI +#define PSELCSN PSEL.CSN + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#define RXDPTR RXD.PTR +#define MAXRX RXD.MAXCNT +#define AMOUNTRX RXD.AMOUNT + +#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#define TXDPTR TXD.PTR +#define MAXTX TXD.MAXCNT +#define AMOUNTTX TXD.AMOUNT + +#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk + + +/* MPU */ +/* Part of MPU module was renamed BPROT, while the rest was eliminated. */ +#define NRF_MPU NRF_BPROT + +/* Register DISABLEINDEBUG macros were affected. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled + +/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ +#define PROTENSET0 CONFIG0 +#define PROTENSET1 CONFIG1 + +#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos +#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk +#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled +#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled +#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled + +#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos +#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk +#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled +#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled +#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled + +#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos +#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk +#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled +#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled +#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled + +#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos +#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk +#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled +#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled +#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled + +#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos +#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk +#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled +#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled +#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled + +#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos +#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk +#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled +#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled +#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled + +#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos +#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk +#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled +#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled +#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled + +#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos +#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk +#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled +#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled +#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled + +#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos +#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk +#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled +#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled +#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled + +#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos +#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk +#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled +#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled +#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled + +#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos +#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk +#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled +#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled +#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled + +#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos +#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk +#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled +#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled +#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled + +#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos +#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk +#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled +#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled +#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled + +#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos +#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk +#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled +#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled +#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled + +#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos +#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk +#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled +#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled +#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled + +#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos +#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk +#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled +#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled +#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled + +#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos +#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk +#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled +#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled +#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled + +#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos +#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk +#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled +#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled +#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled + +#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos +#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk +#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled +#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled +#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled + +#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos +#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk +#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled +#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled +#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled + +#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos +#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk +#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled +#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled +#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled + +#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos +#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk +#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled +#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled +#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled + +#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos +#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk +#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled +#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled +#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled + +#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos +#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk +#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled +#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled +#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled + +#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos +#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk +#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled +#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled +#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled + +#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos +#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk +#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled +#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled +#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled + +#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos +#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk +#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled +#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled +#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled + +#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos +#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk +#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled +#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled +#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled + +#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos +#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk +#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled +#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled +#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled + +#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos +#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk +#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled +#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled +#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled + +#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos +#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk +#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled +#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled +#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled + +#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos +#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk +#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled +#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled +#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled + +#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos +#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk +#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled +#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled +#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled + +#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos +#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk +#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled +#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled +#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled + +#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos +#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk +#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled +#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled +#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled + +#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos +#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk +#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled +#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled +#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled + +#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos +#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk +#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled +#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled +#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled + +#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos +#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk +#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled +#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled +#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled + +#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos +#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk +#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled +#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled +#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled + +#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos +#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk +#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled +#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled +#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled + +#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos +#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk +#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled +#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled +#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled + +#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos +#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk +#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled +#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled +#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled + +#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos +#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk +#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled +#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled +#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled + +#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos +#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk +#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled +#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled +#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled + +#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos +#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk +#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled +#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled +#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled + +#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos +#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk +#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled +#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled +#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled + +#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos +#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk +#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled +#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled +#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled + +#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos +#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk +#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled +#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled +#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled + +#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos +#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk +#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled +#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled +#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled + +#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos +#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk +#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled +#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled +#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled + +#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos +#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk +#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled +#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled +#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled + +#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos +#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk +#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled +#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled +#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled + +#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos +#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk +#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled +#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled +#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled + +#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos +#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk +#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled +#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled +#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled + +#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos +#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk +#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled +#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled +#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled + +#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos +#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk +#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled +#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled +#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled + +#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos +#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk +#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled +#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled +#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled + +#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos +#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk +#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled +#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled +#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled + +#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos +#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk +#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled +#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled +#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled + +#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos +#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk +#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled +#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled +#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled + +#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos +#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk +#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled +#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled +#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled + +#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos +#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk +#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled +#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled +#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled + +#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos +#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk +#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled +#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled +#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled + +#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos +#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk +#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled +#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled +#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled + + +/* From nrf51_deprecated.h */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* IRQ */ +/* COMP module was eliminated. Adapted to nrf52 headers. */ +#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn + + +/* REFSEL register redefined enumerated values and added some more. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd + + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52_H */ + diff --git a/nrf5/device/nrf52/nrf52.h b/nrf5/device/nrf52/nrf52.h new file mode 100644 index 0000000000..760fd29ba6 --- /dev/null +++ b/nrf5/device/nrf52/nrf52.h @@ -0,0 +1,2091 @@ + +/****************************************************************************************************//** + * @file nrf52.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * nrf52 from Nordic Semiconductor. + * + * @version V1 + * @date 30. September 2016 + * + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nrf52.svd' Version 1, + * + * @par Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + +/** @addtogroup nrf52 + * @{ + */ + +#ifndef NRF52_H +#define NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ---------------------- nrf52 Specific Interrupt Numbers ---------------------- */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38 /*!< 38 FPU */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_nrf52.h" /*!< nrf52 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + +typedef struct { + __I uint32_t PART; /*!< Part code */ + __I uint32_t VARIANT; /*!< Part Variant, Hardware version and Production configuration */ + __I uint32_t PACKAGE; /*!< Package option */ + __I uint32_t RAM; /*!< RAM variant */ + __I uint32_t FLASH; /*!< Flash variant */ + __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */ +} FICR_INFO_Type; + +typedef struct { + __I uint32_t A0; /*!< Slope definition A0. */ + __I uint32_t A1; /*!< Slope definition A1. */ + __I uint32_t A2; /*!< Slope definition A2. */ + __I uint32_t A3; /*!< Slope definition A3. */ + __I uint32_t A4; /*!< Slope definition A4. */ + __I uint32_t A5; /*!< Slope definition A5. */ + __I uint32_t B0; /*!< y-intercept B0. */ + __I uint32_t B1; /*!< y-intercept B1. */ + __I uint32_t B2; /*!< y-intercept B2. */ + __I uint32_t B3; /*!< y-intercept B3. */ + __I uint32_t B4; /*!< y-intercept B4. */ + __I uint32_t B5; /*!< y-intercept B5. */ + __I uint32_t T0; /*!< Segment end T0. */ + __I uint32_t T1; /*!< Segment end T1. */ + __I uint32_t T2; /*!< Segment end T2. */ + __I uint32_t T3; /*!< Segment end T3. */ + __I uint32_t T4; /*!< Segment end T4. */ +} FICR_TEMP_Type; + +typedef struct { + __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; + +typedef struct { + __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */ + __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */ + __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */ + __I uint32_t RESERVED0; +} POWER_RAM_Type; + +typedef struct { + __IO uint32_t RTS; /*!< Pin select for RTS signal */ + __IO uint32_t TXD; /*!< Pin select for TXD signal */ + __IO uint32_t CTS; /*!< Pin select for CTS signal */ + __IO uint32_t RXD; /*!< Pin select for RXD signal */ +} UARTE_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ +} SPIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_TXD_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t CSN; /*!< Pin select for CSN signal */ +} SPIS_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< RXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< TXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; + +typedef struct { + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_TXD_Type; + +typedef struct { + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIS_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< RXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< TXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI */ + __IO uint32_t MISO; /*!< Pin select for MISO */ +} SPI_PSEL_Type; + +typedef struct { + __IO uint32_t RX; /*!< Result of last incoming frames */ +} NFCT_FRAMESTATUS_Type; + +typedef struct { + __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */ + __IO uint32_t AMOUNT; /*!< Size of outgoing frame */ +} NFCT_TXD_Type; + +typedef struct { + __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */ + __I uint32_t AMOUNT; /*!< Size of last incoming frame */ +} NFCT_RXD_Type; + +typedef struct { + __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */ + __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; + +typedef struct { + __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */ + __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */ + __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */ + __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring + a channel */ +} SAADC_CH_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */ + __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */ +} SAADC_RESULT_Type; + +typedef struct { + __IO uint32_t LED; /*!< Pin select for LED signal */ + __IO uint32_t A; /*!< Pin select for A signal */ + __IO uint32_t B; /*!< Pin select for B signal */ +} QDEC_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of this + sequence */ + __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in this + sequence */ + __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between + samples loaded into compare register */ + __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */ + __I uint32_t RESERVED1[4]; +} PWM_SEQ_Type; + +typedef struct { + __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel + 0 */ +} PWM_PSEL_Type; + +typedef struct { + __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */ + __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */ + __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */ +} PDM_SAMPLE_Type; + +typedef struct { + __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */ + __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */ +} PPI_TASKS_CHG_Type; + +typedef struct { + __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */ + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_CH_Type; + +typedef struct { + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_FORK_Type; + +typedef struct { + __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */ +} MWU_EVENTS_REGION_Type; + +typedef struct { + __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0 + detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */ +} MWU_EVENTS_PREGION_Type; + +typedef struct { + __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, write access detected while corresponding subregion was enabled + for watching */ + __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, read access detected while corresponding subregion was enabled + for watching */ +} MWU_PERREGION_Type; + +typedef struct { + __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */ + __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */ + __I uint32_t RESERVED2[2]; +} MWU_REGION_Type; + +typedef struct { + __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */ + __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */ + __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */ + __I uint32_t RESERVED3; +} MWU_PREGION_Type; + +typedef struct { + __IO uint32_t MODE; /*!< I2S mode. */ + __IO uint32_t RXEN; /*!< Reception (RX) enable. */ + __IO uint32_t TXEN; /*!< Transmission (TX) enable. */ + __IO uint32_t MCKEN; /*!< Master clock generator enable. */ + __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */ + __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */ + __IO uint32_t SWIDTH; /*!< Sample width. */ + __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */ + __IO uint32_t FORMAT; /*!< Frame format. */ + __IO uint32_t CHANNELS; /*!< Enable channels. */ +} I2S_CONFIG_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Receive buffer RAM start address. */ +} I2S_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */ +} I2S_TXD_Type; + +typedef struct { + __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; + +typedef struct { + __IO uint32_t MCK; /*!< Pin select for MCK signal. */ + __IO uint32_t SCK; /*!< Pin select for SCK signal. */ + __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */ + __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */ + __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */ +} I2S_PSEL_Type; + + +/* ================================================================================ */ +/* ================ FICR ================ */ +/* ================================================================================ */ + + +/** + * @brief Factory Information Configuration Registers (FICR) + */ + +typedef struct { /*!< FICR Structure */ + __I uint32_t RESERVED0[4]; + __I uint32_t CODEPAGESIZE; /*!< Code memory page size */ + __I uint32_t CODESIZE; /*!< Code memory size */ + __I uint32_t RESERVED1[18]; + __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */ + __I uint32_t RESERVED2[6]; + __I uint32_t ER[4]; /*!< Description collection[0]: Encryption Root, word 0 */ + __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */ + __I uint32_t DEVICEADDRTYPE; /*!< Device address type */ + __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */ + __I uint32_t RESERVED3[21]; + FICR_INFO_Type INFO; /*!< Device info */ + __I uint32_t RESERVED4[185]; + FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */ + __I uint32_t RESERVED5[2]; + FICR_NFC_Type NFC; /*!< Unspecified */ +} NRF_FICR_Type; + + +/* ================================================================================ */ +/* ================ UICR ================ */ +/* ================================================================================ */ + + +/** + * @brief User Information Configuration Registers (UICR) + */ + +typedef struct { /*!< UICR Structure */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t UNUSED1; /*!< Unspecified */ + __IO uint32_t UNUSED2; /*!< Unspecified */ + __I uint32_t RESERVED0; + __IO uint32_t UNUSED3; /*!< Unspecified */ + __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */ + __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */ + __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */ + __I uint32_t RESERVED1[64]; + __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function (see + POWER chapter for details) */ + __IO uint32_t APPROTECT; /*!< Access Port protection */ + __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna + or GPIO */ +} NRF_UICR_Type; + + +/* ================================================================================ */ +/* ================ BPROT ================ */ +/* ================================================================================ */ + + +/** + * @brief Block Protect (BPROT) + */ + +typedef struct { /*!< BPROT Structure */ + __I uint32_t RESERVED0[384]; + __IO uint32_t CONFIG0; /*!< Block protect configuration register 0 */ + __IO uint32_t CONFIG1; /*!< Block protect configuration register 1 */ + __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug interface mode */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t CONFIG2; /*!< Block protect configuration register 2 */ + __IO uint32_t CONFIG3; /*!< Block protect configuration register 3 */ +} NRF_BPROT_Type; + + +/* ================================================================================ */ +/* ================ POWER ================ */ +/* ================================================================================ */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< POWER Structure */ + __I uint32_t RESERVED0[30]; + __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */ + __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */ + __I uint32_t RESERVED1[34]; + __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */ + __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */ + __I uint32_t RESERVED3[122]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[61]; + __IO uint32_t RESETREAS; /*!< Reset reason */ + __I uint32_t RESERVED5[9]; + __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */ + __I uint32_t RESERVED6[53]; + __O uint32_t SYSTEMOFF; /*!< System OFF register */ + __I uint32_t RESERVED7[3]; + __IO uint32_t POFCON; /*!< Power failure comparator configuration */ + __I uint32_t RESERVED8[2]; + __IO uint32_t GPREGRET; /*!< General purpose retention register */ + __IO uint32_t GPREGRET2; /*!< General purpose retention register */ + __IO uint32_t RAMON; /*!< Deprecated register - RAM on/off register (this register is + retained) */ + __I uint32_t RESERVED9[11]; + __IO uint32_t RAMONB; /*!< Deprecated register - RAM on/off register (this register is + retained) */ + __I uint32_t RESERVED10[8]; + __IO uint32_t DCDCEN; /*!< DC/DC enable register */ + __I uint32_t RESERVED11[225]; + POWER_RAM_Type RAM[8]; /*!< Unspecified */ +} NRF_POWER_Type; + + +/* ================================================================================ */ +/* ================ CLOCK ================ */ +/* ================================================================================ */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< CLOCK Structure */ + __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */ + __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */ + __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */ + __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */ + __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC oscillator */ + __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ + __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ + __I uint32_t RESERVED0[57]; + __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */ + __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ + __I uint32_t RESERVED1; + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ + __I uint32_t RESERVED2[124]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ + __I uint32_t HFCLKSTAT; /*!< HFCLK status */ + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ + __I uint32_t LFCLKSTAT; /*!< LFCLK status */ + __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + __I uint32_t RESERVED5[62]; + __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ + __I uint32_t RESERVED6[7]; + __IO uint32_t CTIV; /*!< Calibration timer interval */ + __I uint32_t RESERVED7[8]; + __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */ +} NRF_CLOCK_Type; + + +/* ================================================================================ */ +/* ================ RADIO ================ */ +/* ================================================================================ */ + + +/** + * @brief 2.4 GHz Radio (RADIO) + */ + +typedef struct { /*!< RADIO Structure */ + __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */ + __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */ + __O uint32_t TASKS_START; /*!< Start RADIO */ + __O uint32_t TASKS_STOP; /*!< Stop RADIO */ + __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */ + __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal + strength. */ + __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */ + __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */ + __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */ + __I uint32_t RESERVED0[55]; + __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */ + __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */ + __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */ + __IO uint32_t EVENTS_END; /*!< Packet sent or received */ + __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */ + __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */ + __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */ + __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */ + __I uint32_t RESERVED2; + __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */ + __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */ + __I uint32_t RESERVED3[50]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED4[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[61]; + __I uint32_t CRCSTATUS; /*!< CRC status */ + __I uint32_t RESERVED6; + __I uint32_t RXMATCH; /*!< Received address */ + __I uint32_t RXCRC; /*!< CRC field of previously received packet */ + __I uint32_t DAI; /*!< Device address match index */ + __I uint32_t RESERVED7[60]; + __IO uint32_t PACKETPTR; /*!< Packet pointer */ + __IO uint32_t FREQUENCY; /*!< Frequency */ + __IO uint32_t TXPOWER; /*!< Output power */ + __IO uint32_t MODE; /*!< Data rate and modulation */ + __IO uint32_t PCNF0; /*!< Packet configuration register 0 */ + __IO uint32_t PCNF1; /*!< Packet configuration register 1 */ + __IO uint32_t BASE0; /*!< Base address 0 */ + __IO uint32_t BASE1; /*!< Base address 1 */ + __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */ + __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */ + __IO uint32_t TXADDRESS; /*!< Transmit address select */ + __IO uint32_t RXADDRESSES; /*!< Receive address select */ + __IO uint32_t CRCCNF; /*!< CRC configuration */ + __IO uint32_t CRCPOLY; /*!< CRC polynomial */ + __IO uint32_t CRCINIT; /*!< CRC initial value */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */ + __I uint32_t RSSISAMPLE; /*!< RSSI sample */ + __I uint32_t RESERVED8; + __I uint32_t STATE; /*!< Current radio state */ + __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */ + __I uint32_t RESERVED9[2]; + __IO uint32_t BCC; /*!< Bit counter compare */ + __I uint32_t RESERVED10[39]; + __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */ + __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */ + __IO uint32_t DACNF; /*!< Device address match configuration */ + __I uint32_t RESERVED11[3]; + __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */ + __I uint32_t RESERVED12[618]; + __IO uint32_t POWER; /*!< Peripheral power control */ +} NRF_RADIO_Type; + + +/* ================================================================================ */ +/* ================ UARTE ================ */ +/* ================================================================================ */ + + +/** + * @brief UART with EasyDMA (UARTE) + */ + +typedef struct { /*!< UARTE Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[7]; + __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */ + __I uint32_t RESERVED1[52]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD (but potentially not yet transferred to + Data RAM) */ + __I uint32_t RESERVED2; + __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ + __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */ + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */ + __I uint32_t RESERVED6; + __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */ + __I uint32_t RESERVED7[41]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[93]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED10[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED11; + UARTE_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[3]; + __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED13[3]; + UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED14; + UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED15[7]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; + + +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART) + */ + +typedef struct { /*!< UART Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ + __I uint32_t RESERVED1[56]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ + __I uint32_t RESERVED2[4]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ + __I uint32_t RESERVED3; + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5[46]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED6[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED7[93]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED8[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED9; + __IO uint32_t PSELRTS; /*!< Pin select for RTS */ + __IO uint32_t PSELTXD; /*!< Pin select for TXD */ + __IO uint32_t PSELCTS; /*!< Pin select for CTS */ + __IO uint32_t PSELRXD; /*!< Pin select for RXD */ + __I uint32_t RXD; /*!< RXD register */ + __O uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED10; + __IO uint32_t BAUDRATE; /*!< Baud rate */ + __I uint32_t RESERVED11[17]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UART_Type; + + +/* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM) + */ + +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */ + __I uint32_t RESERVED6[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started */ + __I uint32_t RESERVED7[44]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[125]; + __IO uint32_t ENABLE; /*!< Enable SPIM */ + __I uint32_t RESERVED10; + SPIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED11[4]; + __IO uint32_t FREQUENCY; /*!< SPI frequency */ + __I uint32_t RESERVED12[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED13[26]; + __IO uint32_t ORC; /*!< Over-read character. Character clocked out in case and over-read + of the TXD buffer. */ +} NRF_SPIM_Type; + + +/* ================================================================================ */ +/* ================ SPIS ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI Slave 0 (SPIS) + */ + +typedef struct { /*!< SPIS Structure */ + __I uint32_t RESERVED0[9]; + __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */ + __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */ + __I uint32_t RESERVED1[54]; + __IO uint32_t EVENTS_END; /*!< Granted transaction completed */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED3[5]; + __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */ + __I uint32_t RESERVED4[53]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED5[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED6[61]; + __I uint32_t SEMSTAT; /*!< Semaphore status register */ + __I uint32_t RESERVED7[15]; + __IO uint32_t STATUS; /*!< Status from last transaction */ + __I uint32_t RESERVED8[47]; + __IO uint32_t ENABLE; /*!< Enable SPI slave */ + __I uint32_t RESERVED9; + SPIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED10[7]; + SPIS_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED11; + SPIS_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED12; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED13; + __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored + transaction. */ + __I uint32_t RESERVED14[24]; + __IO uint32_t ORC; /*!< Over-read character */ +} NRF_SPIS_Type; + + +/* ================================================================================ */ +/* ================ TWIM ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM) + */ + +typedef struct { /*!< TWIM Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is + not suspended. */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[8]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been + issued, TWI traffic is now suspended. */ + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[2]; + __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */ + __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */ + __I uint32_t RESERVED7[39]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED10[14]; + __IO uint32_t ENABLE; /*!< Enable TWIM */ + __I uint32_t RESERVED11; + TWIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[5]; + __IO uint32_t FREQUENCY; /*!< TWI frequency */ + __I uint32_t RESERVED13[3]; + TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[13]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWIM_Type; + + +/* ================================================================================ */ +/* ================ TWIS ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS) + */ + +typedef struct { /*!< TWIS Structure */ + __I uint32_t RESERVED0[5]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED2[3]; + __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */ + __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */ + __I uint32_t RESERVED3[51]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[9]; + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_WRITE; /*!< Write command received */ + __IO uint32_t EVENTS_READ; /*!< Read command received */ + __I uint32_t RESERVED7[37]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[113]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t MATCH; /*!< Status register indicating which address had a match */ + __I uint32_t RESERVED10[10]; + __IO uint32_t ENABLE; /*!< Enable TWIS */ + __I uint32_t RESERVED11; + TWIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[9]; + TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED13; + TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[14]; + __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */ + __I uint32_t RESERVED15; + __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */ + __I uint32_t RESERVED16[10]; + __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read + of the transmit buffer. */ +} NRF_TWIS_Type; + + +/* ================================================================================ */ +/* ================ SPI ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI) + */ + +typedef struct { /*!< SPI Structure */ + __I uint32_t RESERVED0[66]; + __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ + __I uint32_t RESERVED1[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable SPI */ + __I uint32_t RESERVED3; + SPI_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED4; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED5; + __IO uint32_t FREQUENCY; /*!< SPI frequency */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CONFIG; /*!< Configuration register */ +} NRF_SPI_Type; + + +/* ================================================================================ */ +/* ================ TWI ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI) + */ + +typedef struct { /*!< TWI Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ + __I uint32_t RESERVED4[4]; + __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or + received */ + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ + __I uint32_t RESERVED8[45]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED9[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED10[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED11[14]; + __IO uint32_t ENABLE; /*!< Enable TWI */ + __I uint32_t RESERVED12; + __IO uint32_t PSELSCL; /*!< Pin select for SCL */ + __IO uint32_t PSELSDA; /*!< Pin select for SDA */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED14; + __IO uint32_t FREQUENCY; /*!< TWI frequency */ + __I uint32_t RESERVED15[24]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWI_Type; + + +/* ================================================================================ */ +/* ================ NFCT ================ */ +/* ================================================================================ */ + + +/** + * @brief NFC-A compatible radio (NFCT) + */ + +typedef struct { /*!< NFCT Structure */ + __O uint32_t TASKS_ACTIVATE; /*!< Activate NFC peripheral for incoming and outgoing frames, change + state to activated */ + __O uint32_t TASKS_DISABLE; /*!< Disable NFC peripheral */ + __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */ + __O uint32_t TASKS_STARTTX; /*!< Start transmission of a outgoing frame, change state to transmit */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */ + __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */ + __I uint32_t RESERVED2[53]; + __IO uint32_t EVENTS_READY; /*!< The NFC peripheral is ready to receive and send frames */ + __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */ + __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */ + __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */ + __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */ + __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */ + __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data have been checked (CRC, parity) and transferred + to RAM, and EasyDMA has ended accessing the RX buffer */ + __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details + on the source of the error. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains + details on the source of the error. */ + __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ + __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended + accessing the TX buffer */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */ + __I uint32_t RESERVED5[3]; + __IO uint32_t EVENTS_COLLISION; /*!< NFC Auto collision resolution error reported. */ + __IO uint32_t EVENTS_SELECTED; /*!< NFC Auto collision resolution successfully completed */ + __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */ + __I uint32_t RESERVED6[43]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED7[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED8[62]; + __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */ + __I uint32_t RESERVED9; + NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */ + __I uint32_t RESERVED10[8]; + __I uint32_t CURRENTLOADCTRL; /*!< Current value driven to the NFC Load Control */ + __I uint32_t RESERVED11[2]; + __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */ + __I uint32_t RESERVED12[49]; + __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */ + __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */ + __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */ + __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */ + __IO uint32_t MAXLEN; /*!< Size of allocated for TXD and RXD data storage buffer in Data + RAM */ + NFCT_TXD_Type TXD; /*!< Unspecified */ + NFCT_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED13[26]; + __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */ + __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */ + __I uint32_t RESERVED14; + __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */ + __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; + + +/* ================================================================================ */ +/* ================ GPIOTE ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< GPIOTE Structure */ + __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it high. */ + __I uint32_t RESERVED1[4]; + __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it low. */ + __I uint32_t RESERVED2[32]; + __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified + in CONFIG[0].PSEL */ + __I uint32_t RESERVED3[23]; + __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism + enabled */ + __I uint32_t RESERVED4[97]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[129]; + __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n] + and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; + + +/* ================================================================================ */ +/* ================ SAADC ================ */ +/* ================================================================================ */ + + +/** + * @brief Analog to Digital Converter (SAADC) + */ + +typedef struct { /*!< SAADC Structure */ + __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */ + __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */ + __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */ + __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */ + __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */ + __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode, + multiple conversions might be needed for a result to be transferred + to RAM. */ + __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */ + __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */ + __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */ + SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED1[106]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t STATUS; /*!< Status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t ENABLE; /*!< Enable or disable ADC */ + __I uint32_t RESERVED4[3]; + SAADC_CH_Type CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED5[24]; + __IO uint32_t RESOLUTION; /*!< Resolution configuration */ + __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined + with SCAN. The RESOLUTION is applied before averaging, thus + for high OVERSAMPLE a higher RESOLUTION should be used. */ + __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */ + __I uint32_t RESERVED6[12]; + SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */ +} NRF_SAADC_Type; + + +/* ================================================================================ */ +/* ================ TIMER ================ */ +/* ================================================================================ */ + + +/** + * @brief Timer/Counter 0 (TIMER) + */ + +typedef struct { /*!< TIMER Structure */ + __O uint32_t TASKS_START; /*!< Start Timer */ + __O uint32_t TASKS_STOP; /*!< Stop Timer */ + __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */ + __O uint32_t TASKS_CLEAR; /*!< Clear time */ + __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */ + __I uint32_t RESERVED0[11]; + __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */ + __I uint32_t RESERVED1[58]; + __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[42]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[126]; + __IO uint32_t MODE; /*!< Timer mode selection */ + __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */ + __I uint32_t RESERVED5; + __IO uint32_t PRESCALER; /*!< Timer prescaler register */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */ +} NRF_TIMER_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief Real time counter 0 (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __O uint32_t TASKS_START; /*!< Start RTC COUNTER */ + __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */ + __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */ + __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */ + __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */ + __I uint32_t RESERVED1[14]; + __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[109]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[13]; + __IO uint32_t EVTEN; /*!< Enable or disable event routing */ + __IO uint32_t EVTENSET; /*!< Enable event routing */ + __IO uint32_t EVTENCLR; /*!< Disable event routing */ + __I uint32_t RESERVED4[110]; + __I uint32_t COUNTER; /*!< Current COUNTER value */ + __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must + be written when RTC is stopped */ + __I uint32_t RESERVED5[13]; + __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */ +} NRF_RTC_Type; + + +/* ================================================================================ */ +/* ================ TEMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< TEMP Structure */ + __O uint32_t TASKS_START; /*!< Start temperature measurement */ + __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[127]; + __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */ + __I uint32_t RESERVED3[5]; + __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */ + __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */ + __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */ + __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */ + __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */ + __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */ + __I uint32_t RESERVED4[2]; + __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */ + __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */ + __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */ + __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */ + __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */ + __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */ + __I uint32_t RESERVED5[2]; + __IO uint32_t T0; /*!< End point of 1st piece wise linear function */ + __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */ + __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */ + __IO uint32_t T3; /*!< End point of 4th piece wise linear function */ + __IO uint32_t T4; /*!< End point of 5th piece wise linear function */ +} NRF_TEMP_Type; + + +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< RNG Structure */ + __O uint32_t TASKS_START; /*!< Task starting the random number generator */ + __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to + the VALUE register */ + __I uint32_t RESERVED1[63]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[126]; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t VALUE; /*!< Output random number */ +} NRF_RNG_Type; + + +/* ================================================================================ */ +/* ================ ECB ================ */ +/* ================================================================================ */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< ECB Structure */ + __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */ + __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */ + __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to + an error */ + __I uint32_t RESERVED1[127]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[126]; + __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */ +} NRF_ECB_Type; + + +/* ================================================================================ */ +/* ================ CCM ================ */ +/* ================================================================================ */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< CCM Structure */ + __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by + itself when completed. */ + __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself + when completed. */ + __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */ + __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */ + __IO uint32_t EVENTS_ERROR; /*!< CCM error event */ + __I uint32_t RESERVED1[61]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t MICSTATUS; /*!< MIC check result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable */ + __IO uint32_t MODE; /*!< Operation mode */ + __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */ + __IO uint32_t INPTR; /*!< Input pointer */ + __IO uint32_t OUTPTR; /*!< Output pointer */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ +} NRF_CCM_Type; + + +/* ================================================================================ */ +/* ================ AAR ================ */ +/* ================================================================================ */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< AAR Structure */ + __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK + data structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ + __I uint32_t RESERVED1[61]; + __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ + __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ + __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t STATUS; /*!< Resolution status */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable AAR */ + __IO uint32_t NIRK; /*!< Number of IRKs */ + __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ + __I uint32_t RESERVED5; + __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ +} NRF_AAR_Type; + + +/* ================================================================================ */ +/* ================ WDT ================ */ +/* ================================================================================ */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< WDT Structure */ + __O uint32_t TASKS_START; /*!< Start the watchdog */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t RUNSTATUS; /*!< Run status */ + __I uint32_t REQSTATUS; /*!< Request status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t CRV; /*!< Counter reload value */ + __IO uint32_t RREN; /*!< Enable register for reload request registers */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED4[60]; + __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */ +} NRF_WDT_Type; + + +/* ================================================================================ */ +/* ================ QDEC ================ */ +/* ================================================================================ */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< QDEC Structure */ + __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */ + __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */ + __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */ + __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */ + __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */ + __I uint32_t RESERVED0[59]; + __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to + the SAMPLE register */ + __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */ + __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */ + __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */ + __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */ + __I uint32_t RESERVED1[59]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */ + __IO uint32_t LEDPOL; /*!< LED output pin polarity */ + __IO uint32_t SAMPLEPER; /*!< Sample period */ + __I int32_t SAMPLE; /*!< Motion sample value */ + __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events + can be generated */ + __I int32_t ACC; /*!< Register accumulating the valid transitions */ + __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC + task */ + QDEC_PSEL_Type PSEL; /*!< Unspecified */ + __IO uint32_t DBFEN; /*!< Enable input debounce filters */ + __I uint32_t RESERVED4[5]; + __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */ + __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */ + __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL + task */ +} NRF_QDEC_Type; + + +/* ================================================================================ */ +/* ================ COMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< COMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< COMP enable */ + __IO uint32_t PSEL; /*!< Pin select */ + __IO uint32_t REFSEL; /*!< Reference source select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[8]; + __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */ + __IO uint32_t MODE; /*!< Mode configuration */ + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ + __IO uint32_t ISOURCE; /*!< Current source select on analog input */ +} NRF_COMP_Type; + + +/* ================================================================================ */ +/* ================ LPCOMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Low Power Comparator (LPCOMP) + */ + +typedef struct { /*!< LPCOMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable LPCOMP */ + __IO uint32_t PSEL; /*!< Input pin select */ + __IO uint32_t REFSEL; /*!< Reference select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[4]; + __IO uint32_t ANADETECT; /*!< Analog detect configuration */ + __I uint32_t RESERVED6[5]; + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ +} NRF_LPCOMP_Type; + + +/* ================================================================================ */ +/* ================ SWI ================ */ +/* ================================================================================ */ + + +/** + * @brief Software interrupt 0 (SWI) + */ + +typedef struct { /*!< SWI Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_SWI_Type; + + +/* ================================================================================ */ +/* ================ EGU ================ */ +/* ================================================================================ */ + + +/** + * @brief Event Generator Unit 0 (EGU) + */ + +typedef struct { /*!< EGU Structure */ + __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding + TRIGGERED[0] event */ + __I uint32_t RESERVED0[48]; + __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering + the corresponding TRIGGER[0] task */ + __I uint32_t RESERVED1[112]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ +} NRF_EGU_Type; + + +/* ================================================================================ */ +/* ================ PWM ================ */ +/* ================================================================================ */ + + +/** + * @brief Pulse Width Modulation Unit 0 (PWM) + */ + +typedef struct { /*!< PWM Structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current + PWM period, and stops sequence playback */ + __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all + enabled channels from sequence 0, and starts playing that sequence + at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes + PWM generation to start it was not running. */ + __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels + if DECODER.MODE=NextStep. Does not cause PWM generation to start + it was not running. */ + __I uint32_t RESERVED1[60]; + __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer + generated */ + __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence + 0 */ + __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence + 0, when last value from RAM has been applied to wave counter */ + __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */ + __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times + defined in LOOP.CNT */ + __I uint32_t RESERVED2[56]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[125]; + __IO uint32_t ENABLE; /*!< PWM module enable register */ + __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */ + __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */ + __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */ + __IO uint32_t DECODER; /*!< Configuration of the decoder */ + __IO uint32_t LOOP; /*!< Amount of playback of a loop */ + __I uint32_t RESERVED5[2]; + PWM_SEQ_Type SEQ[2]; /*!< Unspecified */ + PWM_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_PWM_Type; + + +/* ================================================================================ */ +/* ================ PDM ================ */ +/* ================================================================================ */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< PDM Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */ + __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */ + __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */ + __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT + (or the last sample after a STOP task has been received) to + Data RAM */ + __I uint32_t RESERVED1[125]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< PDM module enable register */ + __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */ + __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */ + __I uint32_t RESERVED3[3]; + __IO uint32_t GAINL; /*!< Left output gain adjustment */ + __IO uint32_t GAINR; /*!< Right output gain adjustment */ + __I uint32_t RESERVED4[8]; + PDM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED5[6]; + PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */ +} NRF_PDM_Type; + + +/* ================================================================================ */ +/* ================ NVMC ================ */ +/* ================================================================================ */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< NVMC Structure */ + __I uint32_t RESERVED0[256]; + __I uint32_t READY; /*!< Ready flag */ + __I uint32_t RESERVED1[64]; + __IO uint32_t CONFIG; /*!< Configuration register */ + + union { + __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */ + }; + __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */ + __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */ + __I uint32_t RESERVED2[10]; + __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */ + __I uint32_t RESERVED3; + __IO uint32_t IHIT; /*!< I-Code cache hit counter. */ + __IO uint32_t IMISS; /*!< I-Code cache miss counter. */ +} NRF_NVMC_Type; + + +/* ================================================================================ */ +/* ================ PPI ================ */ +/* ================================================================================ */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< PPI Structure */ + PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */ + __I uint32_t RESERVED0[308]; + __IO uint32_t CHEN; /*!< Channel enable register */ + __IO uint32_t CHENSET; /*!< Channel enable set register */ + __IO uint32_t CHENCLR; /*!< Channel enable clear register */ + __I uint32_t RESERVED1; + PPI_CH_Type CH[20]; /*!< PPI Channel */ + __I uint32_t RESERVED2[148]; + __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */ + __I uint32_t RESERVED3[62]; + PPI_FORK_Type FORK[32]; /*!< Fork */ +} NRF_PPI_Type; + + +/* ================================================================================ */ +/* ================ MWU ================ */ +/* ================================================================================ */ + + +/** + * @brief Memory Watch Unit (MWU) + */ + +typedef struct { /*!< MWU Structure */ + __I uint32_t RESERVED0[64]; + MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED1[16]; + MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED2[100]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[5]; + __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */ + __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */ + __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */ + __I uint32_t RESERVED4[53]; + MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED5[64]; + __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */ + __IO uint32_t REGIONENSET; /*!< Enable regions watch */ + __IO uint32_t REGIONENCLR; /*!< Disable regions watch */ + __I uint32_t RESERVED6[57]; + MWU_REGION_Type REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED7[32]; + MWU_PREGION_Type PREGION[2]; /*!< Unspecified */ +} NRF_MWU_Type; + + +/* ================================================================================ */ +/* ================ I2S ================ */ +/* ================================================================================ */ + + +/** + * @brief Inter-IC Sound (I2S) + */ + +typedef struct { /*!< I2S Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when + this is enabled. */ + __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this + task will cause the {event:STOPPED} event to be generated. */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __I uint32_t RESERVED2[122]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable I2S module. */ + I2S_CONFIG_Type CONFIG; /*!< Unspecified */ + __I uint32_t RESERVED4[3]; + I2S_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED5; + I2S_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED6[3]; + I2S_RXTXD_Type RXTXD; /*!< Unspecified */ + __I uint32_t RESERVED7[3]; + I2S_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_I2S_Type; + + +/* ================================================================================ */ +/* ================ FPU ================ */ +/* ================================================================================ */ + + +/** + * @brief FPU (FPU) + */ + +typedef struct { /*!< FPU Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_FPU_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO Port 1 (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __I uint32_t RESERVED0[321]; + __IO uint32_t OUT; /*!< Write GPIO port */ + __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */ + __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */ + __I uint32_t IN; /*!< Read GPIO port */ + __IO uint32_t DIR; /*!< Direction of GPIO pins */ + __IO uint32_t DIRSET; /*!< DIR set register */ + __IO uint32_t DIRCLR; /*!< DIR clear register */ + __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria + set in the PIN_CNF[n].SENSE registers */ + __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */ + __I uint32_t RESERVED1[118]; + __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */ +} NRF_GPIO_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_BPROT_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_P0_BASE 0x50000000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) +#define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE) +#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) +#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) +#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE) +#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) +#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) +#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) +#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) +#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) +#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE) +#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) +#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) +#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) +#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) +#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) +#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE) +#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group nrf52 */ +/** @} */ /* End of group Nordic Semiconductor */ + +#ifdef __cplusplus +} +#endif + + +#endif /* nrf52_H */ + diff --git a/nrf5/device/nrf52/nrf52_bitfields.h b/nrf5/device/nrf52/nrf52_bitfields.h new file mode 100644 index 0000000000..d01120711c --- /dev/null +++ b/nrf5/device/nrf52/nrf52_bitfields.h @@ -0,0 +1,12630 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __NRF52_BITS_H +#define __NRF52_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for END event */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for END event */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: BPROT */ +/* Description: Block Protect */ + +/* Register: BPROT_CONFIG0 */ +/* Description: Block protect configuration register 0 */ + +/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */ + +/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */ + +/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */ + +/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */ + +/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */ + +/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */ + +/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */ + +/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */ + +/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */ + +/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */ + +/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */ + +/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */ + +/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */ + +/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */ + +/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */ + +/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */ + +/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */ + +/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */ + +/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */ + +/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */ + +/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */ + +/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */ + +/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */ + +/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */ + +/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */ + +/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */ + +/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */ + +/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */ + +/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */ + +/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */ + +/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */ + +/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */ + +/* Register: BPROT_CONFIG1 */ +/* Description: Block protect configuration register 1 */ + +/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */ +#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */ +#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */ +#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */ +#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */ +#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */ +#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */ +#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */ +#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */ +#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */ +#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */ +#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */ +#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */ +#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */ +#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */ +#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */ +#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */ +#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */ +#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */ +#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */ +#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */ +#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */ +#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */ +#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */ +#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */ +#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */ +#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */ +#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */ +#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */ +#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */ +#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */ +#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */ +#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_DISABLEINDEBUG */ +/* Description: Disable protection mechanism in debug interface mode */ + +/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */ + +/* Register: BPROT_CONFIG2 */ +/* Description: Block protect configuration register 2 */ + +/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */ +#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */ +#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */ +#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */ +#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */ +#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */ +#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */ +#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */ +#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */ +#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */ +#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */ +#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */ +#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */ +#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */ +#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */ +#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */ +#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */ +#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */ +#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */ +#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */ +#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */ +#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */ +#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */ +#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */ +#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */ +#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */ +#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */ +#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */ +#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */ +#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */ +#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */ +#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */ +#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */ +#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */ +#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */ +#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */ +#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */ +#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */ +#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */ +#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */ +#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */ +#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */ +#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */ +#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */ +#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */ +#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */ +#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */ +#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */ +#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */ +#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */ +#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */ +#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */ +#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */ +#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */ +#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */ +#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */ +#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */ +#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */ +#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */ +#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */ +#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */ +#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */ +#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */ +#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */ +#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_CONFIG3 */ +/* Description: Block protect configuration register 3 */ + +/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */ +#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */ +#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */ +#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */ +#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */ +#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */ +#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */ +#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */ +#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */ +#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */ +#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */ +#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */ +#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */ +#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */ +#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */ +#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */ +#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */ +#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */ +#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */ +#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */ +#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */ +#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */ +#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */ +#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */ +#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */ +#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */ +#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */ +#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */ +#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */ +#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */ +#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */ +#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */ +#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */ +#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */ +#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */ +#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */ +#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */ +#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */ +#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */ +#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */ +#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */ +#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */ +#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */ +#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */ +#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */ +#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */ +#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */ +#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */ +#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */ +#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */ +#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */ +#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */ +#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */ +#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */ +#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */ +#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */ +#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */ +#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */ +#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */ +#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */ +#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */ +#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */ +#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */ +#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */ +#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for ERROR event */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for ERROR event */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */ + +/* Bit 16 : Data rate that the CCM shall run in synch with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */ + +/* Bit 0 : The mode of operation to be used */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for CTTO event */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DONE event */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for CTTO event */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DONE event */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_TRACECONFIG */ +/* Description: Clocking options for the Trace Port debug interface */ + +/* Bits 17..16 : Pin multiplexing of trace signals. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */ + +/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for CROSS event */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for UP event */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for DOWN event */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation mode */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power mode */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + +/* Register: COMP_ISOURCE */ +/* Description: Current source select on analog input */ + +/* Bits 1..0 : Comparator hysteresis */ +#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */ +#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event Generator Unit 0 */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory Information Configuration Registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection[0]: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection[0]: Encryption Root, word 0 */ + +/* Bits 31..0 : Encryption Root, word n */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection[0]: Identity Root, word 0 */ + +/* Bits 31..0 : Identity Root, word n */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection[0]: Device address 0 */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part Variant, Hardware version and Production configuration */ + +/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ +#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2001UL) /*!< CIxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: y-intercept B0. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: y-intercept B1. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: y-intercept B2. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: y-intercept B3. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: y-intercept B4. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: y-intercept B5. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_NFC_TAGHEADER0 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 3 */ +#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ +#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ + +/* Bits 23..16 : Unique identifier byte 2 */ +#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ +#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ + +/* Bits 15..8 : Unique identifier byte 1 */ +#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ +#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ + +/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ +#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ +#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ + +/* Register: FICR_NFC_TAGHEADER1 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 7 */ +#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ +#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ + +/* Bits 23..16 : Unique identifier byte 6 */ +#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ +#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ + +/* Bits 15..8 : Unique identifier byte 5 */ +#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ +#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ + +/* Bits 7..0 : Unique identifier byte 4 */ +#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ +#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ + +/* Register: FICR_NFC_TAGHEADER2 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 11 */ +#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ +#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ + +/* Bits 23..16 : Unique identifier byte 10 */ +#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ +#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ + +/* Bits 15..8 : Unique identifier byte 9 */ +#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ +#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ + +/* Bits 7..0 : Unique identifier byte 8 */ +#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ +#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ + +/* Register: FICR_NFC_TAGHEADER3 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 15 */ +#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ +#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ + +/* Bits 23..16 : Unique identifier byte 14 */ +#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ +#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ + +/* Bits 15..8 : Unique identifier byte 13 */ +#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ +#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ + +/* Bits 7..0 : Unique identifier byte 12 */ +#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ +#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to Enable interrupt for PORT event */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to Disable interrupt for PORT event */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: I2S */ +/* Description: Inter-IC Sound */ + +/* Register: I2S_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ +#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for STOPPED event */ +#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ +#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */ +#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */ +#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */ +#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ + +/* Register: I2S_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */ +#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */ +#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */ +#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Register: I2S_ENABLE */ +/* Description: Enable I2S module. */ + +/* Bit 0 : Enable I2S module. */ +#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_CONFIG_MODE */ +/* Description: I2S mode. */ + +/* Bit 0 : I2S mode. */ +#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ +#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ + +/* Register: I2S_CONFIG_RXEN */ +/* Description: Reception (RX) enable. */ + +/* Bit 0 : Reception (RX) enable. */ +#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ +#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: I2S_CONFIG_TXEN */ +/* Description: Transmission (TX) enable. */ + +/* Bit 0 : Transmission (TX) enable. */ +#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ +#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ + +/* Register: I2S_CONFIG_MCKEN */ +/* Description: Master clock generator enable. */ + +/* Bit 0 : Master clock generator enable. */ +#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ +#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ + +/* Register: I2S_CONFIG_MCKFREQ */ +/* Description: Master clock generator frequency. */ + +/* Bits 31..0 : Master clock generator frequency. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ + +/* Register: I2S_CONFIG_RATIO */ +/* Description: MCK / LRCK ratio. */ + +/* Bits 3..0 : MCK / LRCK ratio. */ +#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ +#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ +#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ +#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ +#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ +#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ +#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ +#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ +#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ + +/* Register: I2S_CONFIG_SWIDTH */ +/* Description: Sample width. */ + +/* Bits 1..0 : Sample width. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ + +/* Register: I2S_CONFIG_ALIGN */ +/* Description: Alignment of sample within a frame. */ + +/* Bit 0 : Alignment of sample within a frame. */ +#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ + +/* Register: I2S_CONFIG_FORMAT */ +/* Description: Frame format. */ + +/* Bit 0 : Frame format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ + +/* Register: I2S_CONFIG_CHANNELS */ +/* Description: Enable channels. */ + +/* Bits 1..0 : Enable channels. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ + +/* Register: I2S_RXD_PTR */ +/* Description: Receive buffer RAM start address. */ + +/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ +#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_TXD_PTR */ +/* Description: Transmit buffer RAM start address. */ + +/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ +#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_RXTXD_MAXCNT */ +/* Description: Size of RXD and TXD buffers. */ + +/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: I2S_PSEL_MCK */ +/* Description: Pin select for MCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SCK */ +/* Description: Pin select for SCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_LRCK */ +/* Description: Pin select for LRCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDIN */ +/* Description: Pin select for SDIN signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDOUT */ +/* Description: Pin select for SDOUT signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low Power Comparator */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: LPCOMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable LPCOMP */ + +/* Bits 1..0 : Enable or disable LPCOMP */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select */ + +/* Bits 2..0 : Analog pin select */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select */ + +/* Bits 3..0 : Reference select */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */ +#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration */ + +/* Bits 1..0 : Analog detect configuration */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */ + +/* Register: LPCOMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis enable */ +#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */ + + +/* Peripheral: MWU */ +/* Description: Memory Watch Unit */ + +/* Register: MWU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ +#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ +#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ +#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ +#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ +#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ +#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ +#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ +#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ +#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ +#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ +#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ +#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */ +#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */ +#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */ +#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */ +#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */ +#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */ +#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */ +#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */ +#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */ +#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */ +#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */ +#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */ +#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */ +#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */ +#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */ +#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */ +#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */ +#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */ +#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */ +#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */ +#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */ +#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */ +#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */ +#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */ +#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_NMIEN */ +/* Description: Enable or disable non-maskable interrupt */ + +/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_NMIENSET */ +/* Description: Enable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_NMIENCLR */ +/* Description: Disable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_PERREGION_SUBSTATWA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Register: MWU_PERREGION_SUBSTATRA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Register: MWU_REGIONEN */ +/* Description: Enable/disable regions watch */ + +/* Bit 27 : Enable/disable read access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable/disable write access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable/disable read access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable/disable write access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable/disable read access watch in region[3] */ +#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable/disable write access watch in region[3] */ +#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable/disable read access watch in region[2] */ +#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable/disable write access watch in region[2] */ +#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable/disable read access watch in region[1] */ +#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable/disable write access watch in region[1] */ +#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable/disable read access watch in region[0] */ +#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable/disable write access watch in region[0] */ +#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENSET */ +/* Description: Enable regions watch */ + +/* Bit 27 : Enable read access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable write access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable read access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable write access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable read access watch in region[3] */ +#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable write access watch in region[3] */ +#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable read access watch in region[2] */ +#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable write access watch in region[2] */ +#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable read access watch in region[1] */ +#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable write access watch in region[1] */ +#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable read access watch in region[0] */ +#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable write access watch in region[0] */ +#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENCLR */ +/* Description: Disable regions watch */ + +/* Bit 27 : Disable read access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 26 : Disable write access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 25 : Disable read access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 24 : Disable write access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 7 : Disable read access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 6 : Disable write access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 5 : Disable read access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 4 : Disable write access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 3 : Disable read access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 2 : Disable write access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 1 : Disable read access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 0 : Disable write access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Register: MWU_REGION_START */ +/* Description: Description cluster[0]: Start address for region 0 */ + +/* Bits 31..0 : Start address for region */ +#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_REGION_END */ +/* Description: Description cluster[0]: End address of region 0 */ + +/* Bits 31..0 : End address of region. */ +#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_START */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_PREGION_END */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_SUBS */ +/* Description: Description cluster[0]: Subregions of region 0 */ + +/* Bit 31 : Include or exclude subregion 31 in region */ +#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude subregion 30 in region */ +#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude subregion 29 in region */ +#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude subregion 28 in region */ +#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude subregion 27 in region */ +#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude subregion 26 in region */ +#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude subregion 25 in region */ +#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude subregion 24 in region */ +#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude subregion 23 in region */ +#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude subregion 22 in region */ +#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude subregion 21 in region */ +#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude subregion 20 in region */ +#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude subregion 19 in region */ +#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude subregion 18 in region */ +#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude subregion 17 in region */ +#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude subregion 16 in region */ +#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude subregion 15 in region */ +#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude subregion 14 in region */ +#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude subregion 13 in region */ +#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude subregion 12 in region */ +#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude subregion 11 in region */ +#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude subregion 10 in region */ +#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude subregion 9 in region */ +#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude subregion 8 in region */ +#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude subregion 7 in region */ +#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude subregion 6 in region */ +#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude subregion 5 in region */ +#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude subregion 4 in region */ +#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude subregion 3 in region */ +#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude subregion 2 in region */ +#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude subregion 1 in region */ +#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude subregion 0 in region */ +#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */ + + +/* Peripheral: NFCT */ +/* Description: NFC-A compatible radio */ + +/* Register: NFCT_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: NFCT_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 20 : Enable or disable interrupt for STARTED event */ +#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for SELECTED event */ +#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for COLLISION event */ +#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for ENDTX event */ +#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for ENDRX event */ +#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for RXERROR event */ +#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for ERROR event */ +#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ +#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ +#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ +#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ +#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ +#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ +#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: NFCT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 20 : Write '1' to Enable interrupt for STARTED event */ +#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */ +#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */ +#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */ +#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */ +#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */ +#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for ERROR event */ +#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */ +#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */ +#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */ +#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */ +#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */ +#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */ +#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: NFCT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 20 : Write '1' to Disable interrupt for STARTED event */ +#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */ +#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */ +#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */ +#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */ +#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */ +#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for ERROR event */ +#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */ +#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */ +#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */ +#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */ +#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */ +#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */ +#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: NFCT_ERRORSTATUS */ +/* Description: NFC Error Status register */ + +/* Bit 3 : Field level is too low at min load resistance */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */ + +/* Bit 2 : Field level is too high at max load resistance */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */ + +/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */ + +/* Register: NFCT_FRAMESTATUS_RX */ +/* Description: Result of last incoming frames */ + +/* Bit 3 : Overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */ + +/* Bit 2 : Parity status of received frame */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */ + +/* Bit 0 : No valid End of Frame detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ + +/* Register: NFCT_CURRENTLOADCTRL */ +/* Description: Current value driven to the NFC Load Control */ + +/* Bits 5..0 : Current value driven to the NFC Load Control */ +#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */ +#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */ + +/* Register: NFCT_FIELDPRESENT */ +/* Description: Indicates the presence or not of a valid field */ + +/* Bit 1 : Indicates if the low level has locked to the field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */ + +/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */ + +/* Register: NFCT_FRAMEDELAYMIN */ +/* Description: Minimum frame delay */ + +/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ + +/* Register: NFCT_FRAMEDELAYMAX */ +/* Description: Maximum frame delay */ + +/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ + +/* Register: NFCT_FRAMEDELAYMODE */ +/* Description: Configuration register for the Frame Delay Timer */ + +/* Bits 1..0 : Configuration register for the Frame Delay Timer */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */ + +/* Register: NFCT_PACKETPTR */ +/* Description: Packet pointer for TXD and RXD data storage in Data RAM */ + +/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */ +#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: NFCT_MAXLEN */ +/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */ + +/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */ +#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: NFCT_TXD_FRAMECONFIG */ +/* Description: Configuration of outgoing frames */ + +/* Bit 4 : CRC mode for outgoing frames */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */ + +/* Bit 2 : Adding SoF or not in TX frames */ +#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */ +#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */ + +/* Bit 1 : Discarding unused bits in start or at end of a Frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */ + +/* Bit 0 : Adding parity or not in the frame */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */ + +/* Register: NFCT_TXD_AMOUNT */ +/* Description: Size of outgoing frame */ + +/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ + +/* Register: NFCT_RXD_FRAMECONFIG */ +/* Description: Configuration of incoming frames */ + +/* Bit 4 : CRC mode for incoming frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */ + +/* Bit 2 : SoF expected or not in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */ + +/* Bit 0 : Parity expected or not in RX frame */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */ + +/* Register: NFCT_RXD_AMOUNT */ +/* Description: Size of last incoming frame */ + +/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ + +/* Register: NFCT_NFCID1_LAST */ +/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */ + +/* Bits 31..24 : NFCID1 byte W */ +#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */ +#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */ + +/* Bits 23..16 : NFCID1 byte X */ +#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */ +#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */ + +/* Bits 15..8 : NFCID1 byte Y */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */ + +/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */ + +/* Register: NFCT_NFCID1_2ND_LAST */ +/* Description: Second last NFCID1 part (7 or 10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte T */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */ + +/* Bits 15..8 : NFCID1 byte U */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */ + +/* Bits 7..0 : NFCID1 byte V */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */ + +/* Register: NFCT_NFCID1_3RD_LAST */ +/* Description: Third last NFCID1 part (10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte Q */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */ + +/* Bits 15..8 : NFCID1 byte R */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */ + +/* Bits 7..0 : NFCID1 byte S */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ + +/* Register: NFCT_SENSRES */ +/* Description: NFC-A SENS_RES auto-response settings */ + +/* Bits 15..12 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ +#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ + +/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ +#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ + +/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */ +#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */ + +/* Bit 5 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ +#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ + +/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */ + +/* Register: NFCT_SELRES */ +/* Description: NFC-A SEL_RES auto-response settings */ + +/* Bit 7 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ +#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ + +/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ +#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + +/* Bits 4..3 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ +#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ + +/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */ +#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */ +#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */ + +/* Bits 1..0 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ +#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in Code area */ + +/* Bits 31..0 : Register for starting erase of a page in Code area */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing User Information Configuration Registers */ + +/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ICACHECNF */ +/* Description: I-Code cache configuration register. */ + +/* Bit 8 : Cache profiling enable */ +#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ + +/* Bit 0 : Cache enable */ +#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ +#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ + +/* Register: NVMC_IHIT */ +/* Description: I-Code cache hit counter. */ + +/* Bits 31..0 : Number of cache hits */ +#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ +#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ + +/* Register: NVMC_IMISS */ +/* Description: I-Code cache miss counter. */ + +/* Bits 31..0 : Number of cache misses */ +#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ +#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port 1 */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection[0]: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for END event */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for END event */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for END event */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */ +#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */ +#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ +#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Deprecated register - RAM status register */ + +/* Bit 3 : RAM block 3 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */ + +/* Bit 2 : RAM block 2 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */ + +/* Bit 1 : RAM block 1 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ + +/* Bit 0 : RAM block 0 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power failure comparator configuration */ + +/* Bits 4..1 : Power failure comparator threshold setting */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure comparator */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_RAMON */ +/* Description: Deprecated register - RAM on/off register (this register is retained) */ + +/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */ +#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */ +#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */ +#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */ +#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */ +#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */ +#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */ +#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */ +#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */ + +/* Register: POWER_RAMONB */ +/* Description: Deprecated register - RAM on/off register (this register is retained) */ + +/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */ + +/* Register: POWER_DCDCEN */ +/* Description: DC/DC enable register */ + +/* Bit 0 : Enable or disable DC/DC converter */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster[0]: RAM0 power control register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster[0]: RAM0 power control set register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster[0]: RAM0 power control clear register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster[0]: Channel 0 event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection[0]: Channel group 0 */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: PWM */ +/* Description: Pulse Width Modulation Unit 0 */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up or up and down as wave counter mode */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Pre-scaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Amount of playback of a loop */ + +/* Bits 15..0 : Amount of playback of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster[0]: Beginning address in Data RAM of this sequence */ + +/* Bits 31..0 : Beginning address in Data RAM of this sequence */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster[0]: Amount of values (duty cycles) in this sequence */ + +/* Bits 14..0 : Amount of values (duty cycles) in this sequence */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register */ + +/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster[0]: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection[0]: Output pin select for PWM channel 0 */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz Radio */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between END event and START task */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between END event and DISABLE task */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and START task */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for END event */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for END event */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power. */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bit 8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Inter Frame Spacing in us */ + +/* Bits 7..0 : Inter Frame Spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection[0]: Device address base segment 0 */ + +/* Bits 31..0 : Device address base segment 0 */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection[0]: Device address prefix 0 */ + +/* Bits 15..0 : Device address prefix 0 */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TICK event */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TICK event */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable event routing for OVRFLW event */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable event routing for TICK event */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable event routing for TICK event */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable event routing for TICK event */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection[0]: Compare register 0 */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Analog to Digital Converter */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for STOPPED event */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for DONE event */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for END event */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for DONE event */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for DONE event */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable ADC */ + +/* Bit 0 : Enable or disable ADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster[0]: Input positive pin selection for CH[0] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster[0]: Input negative pin selection for CH[0] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster[0]: Input configuration for CH[0] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster[0]: High/low limits for event monitoring a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 14..0 : Maximum number of buffer words to transfer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of buffer words transferred since last START */ + +/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for READY event */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for READY event */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bits 31..0 : Pin number configuration for SPI SCK signal */ +#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */ +#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */ +#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI */ + +/* Bits 31..0 : Pin number configuration for SPI MOSI signal */ +#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */ +#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */ +#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO */ + +/* Bits 31..0 : Pin number configuration for SPI MISO signal */ +#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */ +#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */ +#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 17 : Shortcut between END event and START task */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for STARTED event */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for END event */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for STARTED event */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for END event */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ + +/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 2 : Shortcut between END event and ACQUIRE task */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 7..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 7..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection[0]: Capture/Compare register 0 */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface 0 */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between BB event and STOP task */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between BB event and SUSPEND task */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for BB event */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for BB event */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSELSCL */ +/* Description: Pin select for SCL */ + +/* Bits 31..0 : Pin number configuration for TWI SCL signal */ +#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */ +#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */ +#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: TWI_PSELSDA */ +/* Description: Pin select for SDA */ + +/* Bits 31..0 : Pin number configuration for TWI SDA signal */ +#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */ +#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */ +#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 12 : Shortcut between LASTRX event and STOP task */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between LASTTX event and STOP task */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for LASTTX event */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for LASTRX event */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 14 : Shortcut between READ event and SUSPEND task */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for READ event */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for WRITE event */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to Enable interrupt for READ event */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for WRITE event */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to Disable interrupt for READ event */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for WRITE event */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection[0]: TWI slave address 0 */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between NCTS event and STOPRX task */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between CTS event and STARTRX task */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSELRTS */ +/* Description: Pin select for RTS */ + +/* Bits 31..0 : Pin number configuration for UART RTS signal */ +#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */ +#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */ +#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELTXD */ +/* Description: Pin select for TXD */ + +/* Bits 31..0 : Pin number configuration for UART TXD signal */ +#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */ +#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */ +#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELCTS */ +/* Description: Pin select for CTS */ + +/* Bits 31..0 : Pin number configuration for UART CTS signal */ +#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */ +#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */ +#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELRXD */ +/* Description: Pin select for RXD */ + +/* Bits 31..0 : Pin number configuration for UART RXD signal */ +#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */ +#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */ +#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate */ + +/* Bits 31..0 : Baud rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for RXTO event */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for ENDTX event */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for ENDRX event */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for NCTS event */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for CTS event */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User Information Configuration Registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection[0]: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection[0]: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection[0]: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access Port protection */ + +/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + +/* Register: UICR_NFCPINS */ +/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ + +/* Bit 0 : Setting of pins dedicated to NFC functionality */ +#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection[0]: Reload request 0 */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/nrf5/device/nrf52/nrf52_name_change.h b/nrf5/device/nrf52/nrf52_name_change.h new file mode 100644 index 0000000000..c75d821faf --- /dev/null +++ b/nrf5/device/nrf52/nrf52_name_change.h @@ -0,0 +1,75 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF52_NAME_CHANGE_H +#define NRF52_NAME_CHANGE_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and + * nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead. + */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + +/* FICR */ +/* Renamed name of the package. */ +#define FICR_INFO_PACKAGE_PACKAGE_CH FICR_INFO_PACKAGE_PACKAGE_CI + + +/*lint --flb "Leave library region" */ + +#endif /* NRF52_NAME_CHANGE_H */ + diff --git a/nrf5/device/nrf52/startup_nrf52.s b/nrf5/device/nrf52/startup_nrf52.s new file mode 100644 index 0000000000..1f39a39530 --- /dev/null +++ b/nrf5/device/nrf52/startup_nrf52.s @@ -0,0 +1,250 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +.syntax unified +.arch armv6-m + +.section .stack +.align 3 + +.global __Vectors +.global Default_Handler + +.word _sidata +.word _sdata +.word _edata +.word _sbss +.word _ebss + +/* Reset Handler */ + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + .fnstart + + ldr r1, =_sidata + ldr r2, =_sdata + ldr r3, =_edata + + subs r3, r2 + ble LC0 + +LC1: + subs r3, 4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt LC1 + +LC0: + bl SystemInit + bl main + bx lr + + .pool + .cantunwind + .fnend + .size Reset_Handler,.-Reset_Handler + +/* Default Handler */ + + .section ".text" + .section .text.Default_Handler,"ax",%progbits +Default_Handler: + b . + .size Default_Handler, .-Default_Handler + +/* Vector Table */ + + .section .isr_vector,"a",%progbits + .type __Vectors, %object + .size __Vectors, .-__Vectors + +__Vectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word POWER_CLOCK_IRQHandler + .word RADIO_IRQHandler + .word UARTE0_UART0_IRQHandler + .word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .word NFCT_IRQHandler + .word GPIOTE_IRQHandler + .word SAADC_IRQHandler + .word TIMER0_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word RTC0_IRQHandler + .word TEMP_IRQHandler + .word RNG_IRQHandler + .word ECB_IRQHandler + .word CCM_AAR_IRQHandler + .word WDT_IRQHandler + .word RTC1_IRQHandler + .word QDEC_IRQHandler + .word COMP_LPCOMP_IRQHandler + .word SWI0_EGU0_IRQHandler + .word SWI1_EGU1_IRQHandler + .word SWI2_EGU2_IRQHandler + .word SWI3_EGU3_IRQHandler + .word SWI4_EGU4_IRQHandler + .word SWI5_EGU5_IRQHandler + .word TIMER3_IRQHandler + .word TIMER4_IRQHandler + .word PWM0_IRQHandler + .word PDM_IRQHandler + .word 0 + .word 0 + .word MWU_IRQHandler + .word PWM1_IRQHandler + .word PWM2_IRQHandler + .word SPIM2_SPIS2_SPI2_IRQHandler + .word RTC2_IRQHandler + .word I2S_IRQHandler + +/* Dummy Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + + .weak MemoryManagement_Handler + .type MemoryManagement_Handler, %function +MemoryManagement_Handler: + B . + .size MemoryManagement_Handler, . - MemoryManagement_Handler + + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ POWER_CLOCK_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + IRQ NFCT_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ SWI2_EGU2_IRQHandler + IRQ SWI3_EGU3_IRQHandler + IRQ SWI4_EGU4_IRQHandler + IRQ SWI5_EGU5_IRQHandler + IRQ TIMER3_IRQHandler + IRQ TIMER4_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + IRQ MWU_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM2_IRQHandler + IRQ SPIM2_SPIS2_SPI2_IRQHandler + IRQ RTC2_IRQHandler + IRQ I2S_IRQHandler + + .end diff --git a/nrf5/device/nrf52/system_nrf52.c b/nrf5/device/nrf52/system_nrf52.c new file mode 100644 index 0000000000..b96b41717c --- /dev/null +++ b/nrf5/device/nrf52/system_nrf52.c @@ -0,0 +1,308 @@ +/* Copyright (c) 2012 ARM LIMITED + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of ARM nor the names of its contributors may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +#include +#include "nrf.h" +#include "system_nrf52.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK_64M (64000000UL) + +static bool errata_16(void); +static bool errata_31(void); +static bool errata_32(void); +static bool errata_36(void); +static bool errata_37(void); +static bool errata_57(void); +static bool errata_66(void); +static bool errata_108(void); + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_16()){ + *(volatile uint32_t *)0x4007C074 = 3131961357ul; + } + + /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_31()){ + *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; + } + + /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_32()){ + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } + + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + + /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_37()){ + *(volatile uint32_t *)0x400005A0 = 0x3; + } + + /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_57()){ + *(volatile uint32_t *)0x40005610 = 0x00000005; + *(volatile uint32_t *)0x40005688 = 0x00000001; + *(volatile uint32_t *)0x40005618 = 0x00000000; + *(volatile uint32_t *)0x40005614 = 0x0000003F; + } + + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + + /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_108()){ + *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F; + } + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, + two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as + normal GPIOs. */ + #if defined (CONFIG_NFCT_PINS_AS_GPIOS) + if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[0] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[1] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product + Specification to see which one). */ + #if defined (ENABLE_SWO) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + SystemCoreClockUpdate(); +} + + +static bool errata_16(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + } + + return false; +} + +static bool errata_31(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + +static bool errata_32(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + } + + return false; +} + +static bool errata_36(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + +static bool errata_37(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + } + + return false; +} + +static bool errata_57(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + } + + return false; +} + +static bool errata_66(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + + +static bool errata_108(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + + +/*lint --flb "Leave library region" */ diff --git a/nrf5/device/nrf52/system_nrf52.h b/nrf5/device/nrf52/system_nrf52.h new file mode 100644 index 0000000000..9201e7926b --- /dev/null +++ b/nrf5/device/nrf52/system_nrf52.h @@ -0,0 +1,69 @@ +/* Copyright (c) 2012 ARM LIMITED + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of ARM nor the names of its contributors may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef SYSTEM_NRF52_H +#define SYSTEM_NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52_H */ diff --git a/nrf5/gccollect.c b/nrf5/gccollect.c new file mode 100644 index 0000000000..7f1d055685 --- /dev/null +++ b/nrf5/gccollect.c @@ -0,0 +1,52 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/obj.h" +#include "py/gc.h" +#include "gccollect.h" + +static inline uint32_t get_msp(void) +{ + register uint32_t result; + __asm volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + +void gc_collect(void) { + // start the GC + gc_collect_start(); + + mp_uint_t sp = get_msp(); // Get stack pointer + + // trace the stack, including the registers (since they live on the stack in this function) + gc_collect_root((void**)sp, ((uint32_t)&_ram_end - sp) / sizeof(uint32_t)); + + // end the GC + gc_collect_end(); +} diff --git a/nrf5/gccollect.h b/nrf5/gccollect.h new file mode 100644 index 0000000000..be5419a56f --- /dev/null +++ b/nrf5/gccollect.h @@ -0,0 +1,44 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef GC_COLLECT_H__ +#define GC_COLLECT_H__ + +extern uint32_t _etext; +extern uint32_t _sidata; +extern uint32_t _ram_start; +extern uint32_t _sdata; +extern uint32_t _edata; +extern uint32_t _sbss; +extern uint32_t _ebss; +extern uint32_t _heap_start; +extern uint32_t _heap_end; +extern uint32_t _estack; +extern uint32_t _ram_end; + +void gc_collect(void); + +#endif diff --git a/nrf5/hal/hal_uart.c b/nrf5/hal/hal_uart.c new file mode 100644 index 0000000000..56a6d889fd --- /dev/null +++ b/nrf5/hal/hal_uart.c @@ -0,0 +1,125 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "mphalport.h" +#include "hal_uart.h" + +#ifdef NRF51 +#include "nrf51.h" +#include "nrf51_bitfields.h" +#define UART_BASE ((NRF_UART_Type *) NRF_UART0_BASE) +#define UART_IRQ_NUM UART0_IRQn +#else +#include "nrf52.h" +#include "nrf52_bitfields.h" +#define UART_BASE ((NRF_UART_Type *) NRF_UART0_BASE) +#define UART_IRQ_NUM UARTE0_UART0_IRQn +#endif + +uint32_t hal_uart_baudrate_lookup[] = { + UART_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud. + UART_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud. + UART_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud. + UART_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud. + UART_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud. + UART_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud. + UART_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud. + UART_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud. + UART_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud. + UART_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud. + UART_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud. + UART_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud. + UART_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud. + UART_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud. + UART_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud. + UART_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud. +}; + +void nrf_uart_char_write(uint8_t ch) { + UART_BASE->TXD = (uint8_t)ch; + while (UART_BASE->EVENTS_TXDRDY != 1) { + // Blocking wait. + } + + // Clear the TX flag. + UART_BASE->EVENTS_TXDRDY = 0; +} + +uint8_t nrf_uart_char_read(void) { + while (UART_BASE->EVENTS_RXDRDY != 1) { + // Wait for RXD data. + } + + UART_BASE->EVENTS_RXDRDY = 0; + return (uint8_t)UART_BASE->RXD; +} + +void nrf_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { + int i = 0; + uint8_t ch = p_buffer[i++]; + while (i < num_of_bytes) { + nrf_uart_char_write(ch); + ch = p_buffer[i++]; + } + cb(); +} + +void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { + int i = 0; + while (i < num_of_bytes) { + uint8_t ch = nrf_uart_char_read(); + p_buffer[i] = ch; + i++; + } + cb(); +} + +void nrf_uart_init(hal_uart_init_t const * p_uart_init) { + hal_gpio_cfg_pin_output(p_uart_init->tx_pin); + hal_gpio_cfg_pin_input(p_uart_init->rx_pin, HAL_GPIO_PULL_DISABLED); + + UART_BASE->PSELTXD = p_uart_init->tx_pin; + UART_BASE->PSELRXD = p_uart_init->rx_pin; + + if (p_uart_init->flow_control) { + hal_gpio_cfg_pin_output(p_uart_init->rts_pin); + hal_gpio_cfg_pin_input(p_uart_init->cts_pin, HAL_GPIO_PULL_DISABLED); + + UART_BASE->PSELCTS = p_uart_init->cts_pin; + UART_BASE->PSELRTS = p_uart_init->rts_pin; + UART_BASE->CONFIG = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos); + } + + UART_BASE->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]); + UART_BASE->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos); + UART_BASE->EVENTS_TXDRDY = 0; + UART_BASE->EVENTS_RXDRDY = 0; + UART_BASE->TASKS_STARTTX = 1; + UART_BASE->TASKS_STARTRX = 1; +} diff --git a/nrf5/hal/hal_uart.h b/nrf5/hal/hal_uart.h new file mode 100644 index 0000000000..ddcbdd5700 --- /dev/null +++ b/nrf5/hal/hal_uart.h @@ -0,0 +1,135 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_UART_H__ +#define HAL_UART_H__ + +#include +#include + +#include "nrf.h" + +#if NRF51 + +#define UART_HWCONTROL_NONE ((uint32_t)UART_CONFIG_HWFC_Disabled << UART_CONFIG_HWFC_Pos) +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) + +#elif NRF52 + +#define UART_HWCONTROL_NONE ((uint32_t)UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos) +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) +#else +#error "Device not supported." +#endif +typedef enum { + HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ + HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_UART_STATE_ERROR = 0x04 /*!< Error */ +} HAL_UART_StateTypeDef; + +typedef enum +{ + HAL_UART_ERROR_NONE = 0x00, /*!< No error */ + HAL_UART_ERROR_ORE = 0x01, /*!< Overrun error. A start bit is received while the previous data still lies in RXD. (Previous data is lost.) */ + HAL_UART_ERROR_PE = 0x02, /*!< Parity error. A character with bad parity is received, if HW parity check is enabled. */ + HAL_UART_ERROR_FE = 0x04, /*!< Frame error. A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ + HAL_UART_ERROR_BE = 0x08, /*!< Break error. The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit.). */ +} HAL_UART_ErrorTypeDef; + +typedef enum { + HAL_UART_BAUD_1K2 = 0, /**< 1200 baud */ + HAL_UART_BAUD_2K4, /**< 2400 baud */ + HAL_UART_BAUD_4K8, /**< 4800 baud */ + HAL_UART_BAUD_9K6, /**< 9600 baud */ + HAL_UART_BAUD_14K4, /**< 14.4 kbaud */ + HAL_UART_BAUD_19K2, /**< 19.2 kbaud */ + HAL_UART_BAUD_28K8, /**< 28.8 kbaud */ + HAL_UART_BAUD_38K4, /**< 38.4 kbaud */ + HAL_UART_BAUD_57K6, /**< 57.6 kbaud */ + HAL_UART_BAUD_76K8, /**< 76.8 kbaud */ + HAL_UART_BAUD_115K2, /**< 115.2 kbaud */ + HAL_UART_BAUD_230K4, /**< 230.4 kbaud */ + HAL_UART_BAUD_250K0, /**< 250.0 kbaud */ + HAL_UART_BAUD_500K0, /**< 500.0 kbaud */ + HAL_UART_BAUD_1M0 /**< 1 mbaud */ +} hal_uart_baudrate_t; + +typedef struct { + uint32_t baud_rate; + uint32_t flow_control; +} UART_InitTypeDef; + +typedef struct +{ + NRF_UART_Type *instance; /* UART registers base address */ + UART_InitTypeDef init; /* UART communication parameters */ + uint8_t *p_tx_buff; /* Pointer to UART Tx transfer Buffer */ + uint16_t tx_xfer_size; /* UART Tx Transfer size */ + uint16_t tx_xfer_count; /* UART Tx Transfer Counter */ + uint8_t *p_rx_buff; /* Pointer to UART Rx transfer Buffer */ + uint16_t rx_xfer_size; /* UART Rx Transfer size */ + uint16_t rx_xfer_count; /* UART Rx Transfer Counter */ + __IO HAL_UART_StateTypeDef state; /* UART communication state */ + __IO HAL_UART_ErrorTypeDef error_code; /* UART Error code */ + +} UART_HandleTypeDef; + +typedef struct { + uint8_t rx_pin; /**< RX pin number. */ + uint8_t tx_pin; /**< TX pin number. */ + uint8_t rts_pin; /**< RTS pin number, only used if flow control is enabled. */ + uint8_t cts_pin; /**< CTS pin number, only used if flow control is enabled. */ + bool flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ + bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ + uint32_t baud_rate; /**< Baud rate configuration. */ + uint32_t irq_priority; /**< UARTE IRQ priority. */ +} hal_uart_init_t; + + +typedef void (*uart_complete_cb)(void); + +void nrf_uart_init(hal_uart_init_t const * p_uart_init); + +void nrf_uart_char_write(uint8_t ch); + +uint8_t nrf_uart_char_read(void); + +void nrf_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb); + +void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb); + +#endif // UART_H__ diff --git a/nrf5/hal/hal_uarte.c b/nrf5/hal/hal_uarte.c new file mode 100644 index 0000000000..9e2535b22f --- /dev/null +++ b/nrf5/hal/hal_uarte.c @@ -0,0 +1,220 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include "mphalport.h" + +#include "hal_uart.h" +#include "nrf52.h" +#include "nrf52_bitfields.h" + +#define UARTE_BASE ((NRF_UARTE_Type *) NRF_UARTE0_BASE) +#define UART_IRQ_NUM UARTE0_UART0_IRQn + +#define TX_BUF_SIZE 1 +#define RX_BUF_SIZE 1 + +static uart_complete_cb dma_read_cb = NULL; +static uart_complete_cb dma_write_cb = NULL; + +uint32_t hal_uart_baudrate_lookup[] = { + UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud. + UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud. + UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud. + UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud. + UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud. + UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud. + UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud. + UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud. + UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud. + UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud. + UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud. + UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud. + UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud. + UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud. + UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud. + UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud. +}; + +__STATIC_INLINE void nrf_uart_irq_clear(void) { + NVIC_ClearPendingIRQ(UART_IRQ_NUM); +} + +__STATIC_INLINE void nrf_uart_irq_enable(uint8_t priority) { + NVIC_SetPriority(UART_IRQ_NUM, priority); + nrf_uart_irq_clear(); + NVIC_EnableIRQ(UART_IRQ_NUM); +} + +void nrf_sendchar(int ch) { + nrf_uart_char_write(ch); +} + +void nrf_uart_init(hal_uart_init_t const * p_uart_init) { + hal_gpio_cfg_pin_output(p_uart_init->tx_pin); + hal_gpio_pin_set(p_uart_init->tx_pin); + hal_gpio_cfg_pin_input(p_uart_init->rx_pin, HAL_GPIO_PULL_DISABLED); + + UARTE_BASE->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]); + + uint32_t hwfc = (p_uart_init->flow_control) + ? (UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos) + : (UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos); + + uint32_t parity = (p_uart_init->use_parity) + ? (UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos) + : (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos); + + UARTE_BASE->CONFIG = (uint32_t)hwfc | (uint32_t)parity; + + UARTE_BASE->PSEL.RXD = p_uart_init->rx_pin; + UARTE_BASE->PSEL.TXD = p_uart_init->tx_pin; + + if (hwfc) { + hal_gpio_cfg_pin_input(p_uart_init->cts_pin, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin_output(p_uart_init->rts_pin); + hal_gpio_pin_set(p_uart_init->rts_pin); + + UARTE_BASE->PSEL.RTS = p_uart_init->rts_pin; + UARTE_BASE->PSEL.CTS = p_uart_init->cts_pin; + } + + nrf_uart_irq_enable(p_uart_init->irq_priority); + + UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); + UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); + + UARTE_BASE->ENABLE = (UARTE_ENABLE_ENABLE_Enabled << UARTE_ENABLE_ENABLE_Pos); + + UARTE_BASE->EVENTS_ENDTX = 0; + UARTE_BASE->EVENTS_ENDRX = 0; +} + +void nrf_uart_char_write(uint8_t ch) { + static volatile uint8_t m_tx_buf[TX_BUF_SIZE]; + (void)m_tx_buf; + + UARTE_BASE->INTENCLR = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); + + m_tx_buf[0] = ch; + + UARTE_BASE->TXD.PTR = (uint32_t)((uint8_t *)m_tx_buf); + UARTE_BASE->TXD.MAXCNT = (uint32_t)sizeof(m_tx_buf); + + UARTE_BASE->TASKS_STARTTX = 1; + + while((0 == UARTE_BASE->EVENTS_ENDTX)); + + UARTE_BASE->EVENTS_ENDTX = 0; + UARTE_BASE->TASKS_STOPTX = 1; + + UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); +} + +uint8_t nrf_uart_char_read(void) { + static volatile uint8_t m_rx_buf[RX_BUF_SIZE]; + + UARTE_BASE->INTENCLR = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); + + UARTE_BASE->RXD.PTR = (uint32_t)((uint8_t *)m_rx_buf); + UARTE_BASE->RXD.MAXCNT = (uint32_t)sizeof(m_rx_buf); + + UARTE_BASE->TASKS_STARTRX = 1; + + while ((0 == UARTE_BASE->EVENTS_ENDRX)); + + UARTE_BASE->EVENTS_ENDRX = 0; + UARTE_BASE->TASKS_STOPRX = 1; + + UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); + + return (uint8_t)m_rx_buf[0]; +} + +void nrf_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { + dma_write_cb = cb; + + UARTE_BASE->TXD.PTR = (uint32_t)p_buffer; + UARTE_BASE->TXD.MAXCNT = num_of_bytes; + UARTE_BASE->TASKS_STARTTX = 1; + + while((0 == UARTE_BASE->EVENTS_ENDTX)); + + UARTE_BASE->EVENTS_ENDTX = 0; + UARTE_BASE->TASKS_STOPTX = 1; + + UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); + +} + +void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { + dma_read_cb = cb; + + UARTE_BASE->RXD.PTR = (uint32_t)(p_buffer); + UARTE_BASE->RXD.MAXCNT = num_of_bytes; + UARTE_BASE->TASKS_STARTRX = 1; + + while ((0 == UARTE_BASE->EVENTS_ENDRX)); + + UARTE_BASE->EVENTS_ENDRX = 0; + UARTE_BASE->TASKS_STOPRX = 1; + + UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); + +} + +static void dma_read_complete(void) { + UARTE_BASE->TASKS_STOPRX = 1; + + if (dma_read_cb != NULL) { + uart_complete_cb temp_cb = dma_read_cb; + dma_read_cb = NULL; + temp_cb(); + } +} + +static void dma_write_complete(void) { + UARTE_BASE->TASKS_STOPTX = 1; + + if (dma_write_cb != NULL) { + uart_complete_cb temp_cb = dma_write_cb; + dma_write_cb = NULL; + temp_cb(); + } +} + +void UARTE0_UART0_IRQHandler(void) { + if ((UARTE_BASE->EVENTS_ENDRX) && + (UARTE_BASE->INTEN & UARTE_INTENSET_ENDRX_Msk)) { + UARTE_BASE->EVENTS_ENDRX = 0; + dma_read_complete(); + } else if ((UARTE_BASE->EVENTS_ENDTX) && + (UARTE_BASE->INTEN & UARTE_INTENSET_ENDTX_Msk)) { + UARTE_BASE->EVENTS_ENDTX = 0; + dma_write_complete(); + } +} diff --git a/nrf5/help.c b/nrf5/help.c new file mode 100644 index 0000000000..c5b47a47c0 --- /dev/null +++ b/nrf5/help.c @@ -0,0 +1,62 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "lib/utils/pyhelp.h" +#include "mpconfigboard.h" + +#if BLUETOOTH_SD +#include "help_sd.h" +#endif + +STATIC const char help_text[] = +"Welcome to MicroPython!\n" +"\n" +"For online help please visit http://micropython.org/help/.\n" +"\n" +"Quick overview of commands for the board:\n" +" pyb.LED(n) -- create an LED object for LED n (n=" HELP_TEXT_BOARD_LED ")\n" +"\n" +#if BLUETOOTH_SD +HELP_TEXT_SD +#endif +"For further help on a specific object, type help(obj)\n" +; + +STATIC mp_obj_t pyb_help(uint n_args, const mp_obj_t *args) { + if (n_args == 0) { + // print a general help message + printf("%s", help_text); + + } else { + // try to print something sensible about the given object + pyhelp_print_obj(args[0]); + } + + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_builtin_help_obj, 0, 1, pyb_help); diff --git a/nrf5/led.c b/nrf5/led.c new file mode 100644 index 0000000000..38dbe1b97c --- /dev/null +++ b/nrf5/led.c @@ -0,0 +1,154 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" + +#include "mphalport.h" +#include "led.h" +#include "mpconfigboard.h" + +#define LED_OFF(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_set(led) : hal_gpio_pin_clear(led); } +#define LED_ON(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_clear(led) : hal_gpio_pin_set(led); } + +typedef struct _pyb_led_obj_t { + mp_obj_base_t base; + mp_uint_t led_id; + mp_uint_t hw_pin; +} pyb_led_obj_t; + +STATIC const pyb_led_obj_t pyb_led_obj[] = { +#if MICROPY_HW_LED_TRICOLOR + {{&pyb_led_type}, PYB_LED_RED, MICROPY_HW_LED_RED}, + {{&pyb_led_type}, PYB_LED_GREEN, MICROPY_HW_LED_GREEN}, + {{&pyb_led_type}, PYB_LED_BLUE, MICROPY_HW_LED_BLUE}, +#elif (MICROPY_HW_LED_COUNT == 1) + {{&pyb_led_type}, PYB_LED1, MICROPY_HW_LED1}, +#elif (MICROPY_HW_LED_COUNT == 2) + {{&pyb_led_type}, PYB_LED1, MICROPY_HW_LED1}, + {{&pyb_led_type}, PYB_LED2, MICROPY_HW_LED2}, +#else + {{&pyb_led_type}, PYB_LED1, MICROPY_HW_LED1}, + {{&pyb_led_type}, PYB_LED2, MICROPY_HW_LED2}, + {{&pyb_led_type}, PYB_LED3, MICROPY_HW_LED3}, + {{&pyb_led_type}, PYB_LED4, MICROPY_HW_LED4}, +#endif +}; + +#define NUM_LEDS MP_ARRAY_SIZE(pyb_led_obj) + +void led_init(void) { + for (uint8_t i = 0; i < NUM_LEDS; i++) { + LED_OFF(pyb_led_obj[i].hw_pin); + hal_gpio_cfg_pin_output(pyb_led_obj[i].hw_pin); + } +} + +void led_state(pyb_led_obj_t * led_obj, int state) { + if (state == 1) { + LED_ON(led_obj->hw_pin); + } else { + LED_OFF(led_obj->hw_pin); + } +} + +void led_toggle(pyb_led_obj_t * led_obj) { + hal_gpio_pin_toggle(led_obj->hw_pin); +} + + + +/******************************************************************************/ +/* Micro Python bindings */ + +void led_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + pyb_led_obj_t *self = self_in; + mp_printf(print, "LED(%lu)", self->led_id); +} + +/// \classmethod \constructor(id) +/// Create an LED object associated with the given LED: +/// +/// - `id` is the LED number, 1-4. +STATIC mp_obj_t led_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // check arguments + mp_arg_check_num(n_args, n_kw, 1, 1, false); + + // get led number + mp_int_t led_id = mp_obj_get_int(args[0]); + + // check led number + if (!(1 <= led_id && led_id <= NUM_LEDS)) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "LED(%d) does not exist", led_id)); + } + + // return static led object + return (mp_obj_t)&pyb_led_obj[led_id - 1]; +} + +/// \method on() +/// Turn the LED on. +mp_obj_t led_obj_on(mp_obj_t self_in) { + pyb_led_obj_t *self = self_in; + led_state(self, 1); + return mp_const_none; +} + +/// \method off() +/// Turn the LED off. +mp_obj_t led_obj_off(mp_obj_t self_in) { + pyb_led_obj_t *self = self_in; + led_state(self, 0); + return mp_const_none; +} + +/// \method toggle() +/// Toggle the LED between on and off. +mp_obj_t led_obj_toggle(mp_obj_t self_in) { + pyb_led_obj_t *self = self_in; + led_toggle(self); + return mp_const_none; +} + +STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_on_obj, led_obj_on); +STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_off_obj, led_obj_off); +STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_toggle_obj, led_obj_toggle); + +STATIC const mp_map_elem_t led_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_on), (mp_obj_t)&led_obj_on_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_off), (mp_obj_t)&led_obj_off_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_toggle), (mp_obj_t)&led_obj_toggle_obj }, +}; + +STATIC MP_DEFINE_CONST_DICT(led_locals_dict, led_locals_dict_table); + +const mp_obj_type_t pyb_led_type = { + { &mp_type_type }, + .name = MP_QSTR_LED, + .print = led_obj_print, + .make_new = led_obj_make_new, + .locals_dict = (mp_obj_t)&led_locals_dict, +}; + diff --git a/nrf5/led.h b/nrf5/led.h new file mode 100644 index 0000000000..7bc0d7fa9d --- /dev/null +++ b/nrf5/led.h @@ -0,0 +1,52 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LED_H +#define LED_H + +typedef enum { +#if MICROPY_HW_LED_TRICOLOR + PYB_LED_RED = 1, + PYB_LED_GREEN = 2, + PYB_LED_BLUE = 3 +#elif (MICROPY_HW_LED_COUNT == 1) + PYB_LED1 = 1, +#elif (MICROPY_HW_LED_COUNT == 2) + PYB_LED1 = 1, + PYB_LED2 = 2, +#else + PYB_LED1 = 1, + PYB_LED2 = 2, + PYB_LED3 = 3, + PYB_LED4 = 4 +#endif +} pyb_led_t; + +void led_init(void); + +extern const mp_obj_type_t pyb_led_type; + +#endif // LED_H diff --git a/nrf5/main.c b/nrf5/main.c new file mode 100644 index 0000000000..db55581834 --- /dev/null +++ b/nrf5/main.c @@ -0,0 +1,161 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include +#include +#include + +#include "py/nlr.h" +#include "py/lexer.h" +#include "py/parse.h" +#include "py/obj.h" +#include "py/runtime.h" +#include "py/stackctrl.h" +#include "py/gc.h" +#include "py/compile.h" +#include "lib/utils/pyexec.h" +#include "readline.h" +#include "gccollect.h" +#include "led.h" +#include "uart.h" +#include "nrf.h" + +void do_str(const char *src, mp_parse_input_kind_t input_kind) { + mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0); + if (lex == NULL) { + printf("MemoryError: lexer could not allocate memory\n"); + return; + } + + nlr_buf_t nlr; + if (nlr_push(&nlr) == 0) { + qstr source_name = lex->source_name; + mp_parse_tree_t pn = mp_parse(lex, input_kind); + mp_obj_t module_fun = mp_compile(&pn, source_name, MP_EMIT_OPT_NONE, true); + mp_call_function_0(module_fun); + nlr_pop(); + } else { + // uncaught exception + mp_obj_print_exception(&mp_plat_print, (mp_obj_t)nlr.ret_val); + } +} + +extern uint32_t _heap_start; +extern uint32_t _heap_end; + +int main(int argc, char **argv) { + + // Stack limit should be less than real stack size, so we have a chance + // to recover from limit hit. (Limit is measured in bytes.) + mp_stack_set_limit((char*)&_ram_end - (char*)&_heap_end - 1024); + + led_init(); + + gc_init(&_heap_start, &_heap_end); + mp_init(); + mp_obj_list_init(mp_sys_path, 0); + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script) + mp_obj_list_init(mp_sys_argv, 0); + + readline_init0(); + + uart_init0(); + { + mp_obj_t args[2] = { + MP_OBJ_NEW_SMALL_INT(PYB_UART_1), + MP_OBJ_NEW_SMALL_INT(115200), + }; + MP_STATE_PORT(pyb_stdio_uart) = pyb_uart_type.make_new((mp_obj_t)&pyb_uart_type, MP_ARRAY_SIZE(args), 0, args); + } + +#if MICROPY_HW_LED_TRICOLOR + do_str("import pyb\r\n" \ + "pyb.LED(1).on()", + MP_PARSE_FILE_INPUT); +#else + + do_str("import pyb\r\n" \ + "pyb.LED(1).on()\r\n" \ + "pyb.LED(3).on()", + MP_PARSE_FILE_INPUT); +#endif + + // Main script is finished, so now go into REPL mode. + // The REPL mode can change, or it can request a soft reset. + for (;;) { + if (pyexec_friendly_repl() != 0) { + break; + } + } + + mp_deinit(); + + return 0; +} + +void HardFault_Handler(void) +{ +#if NRF52 + static volatile uint32_t reg; + static volatile uint32_t reg2; + static volatile uint32_t bfar; + reg = SCB->HFSR; + reg2 = SCB->CFSR; + bfar = SCB->BFAR; + for (int i = 0; i < 0; i++) + { + (void)reg; + (void)reg2; + (void)bfar; + } +#endif +} + +mp_lexer_t *mp_lexer_new_from_file(const char *filename) { + return NULL; +} + +mp_import_stat_t mp_import_stat(const char *path) { + return MP_IMPORT_STAT_NO_EXIST; +} + +mp_obj_t mp_builtin_open(uint n_args, const mp_obj_t *args, mp_map_t *kwargs) { + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open); + +void nlr_jump_fail(void *val) { +} + +void NORETURN __fatal_error(const char *msg) { + while (1); +} + +void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) { + printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line); + __fatal_error("Assertion failed"); +} + +void _start(void) {main(0, NULL);} diff --git a/nrf5/mkrules.mk b/nrf5/mkrules.mk new file mode 100644 index 0000000000..6ae98cdc8d --- /dev/null +++ b/nrf5/mkrules.mk @@ -0,0 +1,10 @@ +OUTPUT_FILENAME = firmware + +## Create binary .bin file from the .out file +binary: + $(OBJCOPY) -O binary $(BUILD)/$(OUTPUT_FILENAME).elf $(BUILD)/$(OUTPUT_FILENAME).bin + +## Create binary .hex file from the .out file +hex: + $(OBJCOPY) -O ihex $(BUILD)/$(OUTPUT_FILENAME).elf $(BUILD)/$(OUTPUT_FILENAME).hex + diff --git a/nrf5/modpyb.c b/nrf5/modpyb.c new file mode 100644 index 0000000000..d7b2e24b2d --- /dev/null +++ b/nrf5/modpyb.c @@ -0,0 +1,48 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/builtin.h" +#include "lib/utils/pyexec.h" +#include "py/runtime.h" +#include "py/obj.h" +#include "uart.h" +#include "led.h" + +STATIC const mp_map_elem_t pyb_module_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_pyb) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_LED), (mp_obj_t)&pyb_led_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_repl_info), (mp_obj_t)&pyb_set_repl_info_obj}, + { MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&pyb_uart_type } +/* { MP_OBJ_NEW_QSTR(MP_QSTR_main), (mp_obj_t)&pyb_main_obj }*/ +}; + + +STATIC MP_DEFINE_CONST_DICT(pyb_module_globals, pyb_module_globals_table); + +const mp_obj_module_t pyb_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&pyb_module_globals, +}; diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h new file mode 100644 index 0000000000..9a8865dce0 --- /dev/null +++ b/nrf5/mpconfigport.h @@ -0,0 +1,185 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NRF5_MPCONFIGPORT_H__ +#define NRF5_MPCONFIGPORT_H__ + +#include + +// options to control how Micro Python is built +// options to control how Micro Python is built + +#define MICROPY_ALLOC_PATH_MAX (512) +#define MICROPY_PERSISTENT_CODE_LOAD (0) +#define MICROPY_EMIT_THUMB (0) +#define MICROPY_EMIT_INLINE_THUMB (0) +#define MICROPY_COMP_MODULE_CONST (0) +#define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0) +#define MICROPY_ENABLE_GC (1) +#define MICROPY_ENABLE_FINALISER (0) +#define MICROPY_STACK_CHECK (0) +#define MICROPY_HELPER_REPL (1) +#define MICROPY_REPL_EMACS_KEYS (0) +#define MICROPY_REPL_AUTO_INDENT (0) +#define MICROPY_ENABLE_SOURCE_LINE (0) +#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_NONE) +#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_NONE) +#define MICROPY_OPT_COMPUTED_GOTO (0) +#define MICROPY_OPT_CACHE_MAP_LOOKUP_IN_BYTECODE (0) +#define MICROPY_OPT_MPZ_BITWISE (0) + +// fatfs configuration used in ffconf.h +#define MICROPY_FATFS_ENABLE_LFN (0) +#define MICROPY_FATFS_LFN_CODE_PAGE (437) /* 1=SFN/ANSI 437=LFN/U.S.(OEM) */ +#define MICROPY_FATFS_USE_LABEL (0) +#define MICROPY_FATFS_RPATH (0) +#define MICROPY_FATFS_VOLUMES (0) +#define MICROPY_FATFS_MULTI_PARTITION (0) +#define MICROPY_FSUSERMOUNT (0) + +#define MICROPY_STREAMS_NON_BLOCK (1) +#define MICROPY_MODULE_WEAK_LINKS (1) +#define MICROPY_CAN_OVERRIDE_BUILTINS (1) +#define MICROPY_USE_INTERNAL_ERRNO (1) +#define MICROPY_PY_FUNCTION_ATTRS (1) +#define MICROPY_PY_BUILTINS_STR_UNICODE (0) +#define MICROPY_PY_BUILTINS_STR_CENTER (0) +#define MICROPY_PY_BUILTINS_STR_PARTITION (0) +#define MICROPY_PY_BUILTINS_STR_SPLITLINES (0) +#define MICROPY_PY_BUILTINS_MEMORYVIEW (0) +#define MICROPY_PY_BUILTINS_FROZENSET (0) +#define MICROPY_PY_BUILTINS_EXECFILE (0) +#define MICROPY_PY_BUILTINS_COMPILE (1) +#define MICROPY_PY_ALL_SPECIAL_METHODS (0) +#define MICROPY_PY_MICROPYTHON_MEM_INFO (0) +#define MICROPY_PY_ARRAY_SLICE_ASSIGN (0) +#define MICROPY_PY_BUILTINS_SLICE_ATTRS (0) +#define MICROPY_PY_SYS_EXIT (1) +#define MICROPY_PY_SYS_MAXSIZE (1) +#define MICROPY_PY_SYS_STDFILES (0) +#define MICROPY_PY_SYS_STDIO_BUFFER (0) +#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (0) +#define MICROPY_PY_MATH_SPECIAL_FUNCTIONS (0) +#define MICROPY_PY_CMATH (0) +#define MICROPY_PY_IO (0) +#define MICROPY_PY_IO_FILEIO (0) +#define MICROPY_PY_UERRNO (0) +#define MICROPY_PY_UBINASCII (0) +#define MICROPY_PY_URANDOM (0) +#define MICROPY_PY_URANDOM_EXTRA_FUNCS (0) +#define MICROPY_PY_UCTYPES (0) +#define MICROPY_PY_UZLIB (0) +#define MICROPY_PY_UJSON (0) +#define MICROPY_PY_URE (0) +#define MICROPY_PY_UHEAPQ (0) +#define MICROPY_PY_UHASHLIB (0) +#define MICROPY_PY_UTIME_MP_HAL (0) +#define MICROPY_PY_MACHINE (0) +#define MICROPY_PY_MACHINE_PULSE (0) +#define MICROPY_PY_MACHINE_I2C (0) +#define MICROPY_PY_MACHINE_SPI (0) +#define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) +#define MICROPY_PY_FRAMEBUF (0) + +#ifndef MICROPY_PY_USOCKET +#define MICROPY_PY_USOCKET (0) +#endif + +#ifndef MICROPY_PY_NETWORK +#define MICROPY_PY_NETWORK (0) +#endif + +#define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) +#define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0) + +// type definitions for the specific machine + +#define BYTES_PER_WORD (4) + +#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1)) + +#define MP_SSIZE_MAX (0x7fffffff) + +#define UINT_FMT "%u" +#define INT_FMT "%d" +#define HEX2_FMT "%02x" + +typedef int mp_int_t; // must be pointer size +typedef unsigned int mp_uint_t; // must be pointer size +typedef long mp_off_t; + +// board specific definitions +#include "mpconfigboard.h" + +// extra built in modules to add to the list of known ones +extern const struct _mp_obj_module_t pyb_module; + +#if BLUETOOTH_SD +extern const struct _mp_obj_module_t ble_module; +#define MICROPY_PORT_BUILTIN_MODULES \ + { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_ble), (mp_obj_t)&ble_module }, \ + +#else +extern const struct _mp_obj_module_t ble_module; +#define MICROPY_PORT_BUILTIN_MODULES \ + { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \ + +#endif // BLUETOOTH_SD + +// extra built in names to add to the global namespace +#define MICROPY_PORT_BUILTINS \ + { MP_OBJ_NEW_QSTR(MP_QSTR_help), (mp_obj_t)&mp_builtin_help_obj }, \ + +// extra constants +#define MICROPY_PORT_CONSTANTS \ + { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_ble), (mp_obj_t)&ble_module }, \ + +#define MP_STATE_PORT MP_STATE_VM + +#define MICROPY_PORT_ROOT_POINTERS \ + const char *readline_hist[8]; \ + mp_obj_t pyb_config_main; \ + mp_obj_t pin_class_mapper; \ + mp_obj_t pin_class_map_dict; \ + /* Used to do callbacks to Python code on interrupt */ \ + struct _pyb_timer_obj_t *pyb_timer_obj_all[14]; \ + \ + /* stdio is repeated on this UART object if it's not null */ \ + struct _pyb_uart_obj_t *pyb_stdio_uart; \ + \ + /* pointers to all UART objects (if they have been created) */ \ + struct _pyb_uart_obj_t *pyb_uart_obj_all[1]; \ + +#define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len) + +// We need to provide a declaration/definition of alloca() +#include + +#include "mpconfigboard.h" + +#endif diff --git a/nrf5/mphalport.c b/nrf5/mphalport.c new file mode 100644 index 0000000000..54283adde7 --- /dev/null +++ b/nrf5/mphalport.c @@ -0,0 +1,74 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include +#include + +#include "py/mpstate.h" +#include "py/mphal.h" +#include "py/mperrno.h" +#include "uart.h" + +// this table converts from HAL_StatusTypeDef to POSIX errno +const byte mp_hal_status_to_errno_table[4] = { + [HAL_OK] = 0, + [HAL_ERROR] = MP_EIO, + [HAL_BUSY] = MP_EBUSY, + [HAL_TIMEOUT] = MP_ETIMEDOUT, +}; + +NORETURN void mp_hal_raise(HAL_StatusTypeDef status) { + nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(mp_hal_status_to_errno_table[status]))); +} + +void mp_hal_set_interrupt_char(int c) { + +} + +int mp_hal_stdin_rx_chr(void) { + for (;;) { + if (MP_STATE_PORT(pyb_stdio_uart) != NULL && uart_rx_any(MP_STATE_PORT(pyb_stdio_uart))) { + return uart_rx_char(MP_STATE_PORT(pyb_stdio_uart)); + } + } + + return 0; +} + +void mp_hal_stdout_tx_str(const char *str) { + mp_hal_stdout_tx_strn(str, strlen(str)); +} + +void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) { + if (MP_STATE_PORT(pyb_stdio_uart) != NULL) { + uart_tx_strn(MP_STATE_PORT(pyb_stdio_uart), str, len); + } +} + +void mp_hal_stdout_tx_strn_cooked(const char *str, mp_uint_t len) { + if (MP_STATE_PORT(pyb_stdio_uart) != NULL) { + uart_tx_strn_cooked(MP_STATE_PORT(pyb_stdio_uart), str, len); + } +} diff --git a/nrf5/mphalport.h b/nrf5/mphalport.h new file mode 100644 index 0000000000..47fb617c47 --- /dev/null +++ b/nrf5/mphalport.h @@ -0,0 +1,110 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __NRF52_HAL +#define __NRF52_HAL + +#include + +#include "py/mpconfig.h" +#include "nrf.h" + +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + + +#ifdef NRF51 +#define GPIO_BASE ((NRF_GPIO_Type *)NRF_GPIO_BASE) +#else +#define GPIO_BASE ((NRF_GPIO_Type *)NRF_P0_BASE) +#endif + +typedef enum { + HAL_GPIO_PULL_DISABLED = (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos), + HAL_GPIO_PULL_DOWN = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos), + HAL_GPIO_PULL_UP = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) +} hal_gpio_pull_t; + +static inline void hal_gpio_cfg_pin_output(uint32_t pin_number) { + GPIO_BASE->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); +} + +static inline void hal_gpio_cfg_pin_input(uint32_t pin_number, hal_gpio_pull_t pull) { + GPIO_BASE->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | pull + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); +} + + +static inline void hal_gpio_out_set(uint32_t pin_mask) { + GPIO_BASE->OUTSET = pin_mask; +} + +static inline void hal_gpio_pin_set(uint32_t pin) { + GPIO_BASE->OUTSET = (1 << pin); +} + +static inline void hal_gpio_pin_clear(uint32_t pin) { + GPIO_BASE->OUTCLR = (1 << pin); +} + +static inline void hal_gpio_pin_toggle(uint32_t pin) { + uint32_t pin_mask = (1 << pin); + + if (GPIO_BASE->OUT ^ pin_mask) { + GPIO_BASE->OUTSET = pin_mask; + } else { + GPIO_BASE->OUTCLR = pin_mask; + } +} + +static inline uint32_t hal_tick_fake(void) { + return 0; +} + +#define mp_hal_ticks_ms hal_tick_fake // TODO: implement. Right now, return 0 always + +extern const unsigned char mp_hal_status_to_errno_table[4]; + +NORETURN void mp_hal_raise(HAL_StatusTypeDef status); +void mp_hal_set_interrupt_char(int c); // -1 to disable + +int mp_hal_stdin_rx_chr(void); +void mp_hal_stdout_tx_str(const char *str); + +#endif + diff --git a/nrf5/qstrdefsport.h b/nrf5/qstrdefsport.h new file mode 100644 index 0000000000..5138fbfb5d --- /dev/null +++ b/nrf5/qstrdefsport.h @@ -0,0 +1,27 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// qstrs specific to this port diff --git a/nrf5/softdevice/help_sd.h b/nrf5/softdevice/help_sd.h new file mode 100644 index 0000000000..ff6c1ad044 --- /dev/null +++ b/nrf5/softdevice/help_sd.h @@ -0,0 +1,38 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HELP_SD_H__ +#define HELP_SD_H__ + +#define HELP_TEXT_SD \ +"If compiled with SD= the additional commands are\n" \ +"available:\n" \ +" ble.enable() -- enable softdevice\n" \ +" ble.disable() -- disable softdevice\n" \ +" ble.advertise() -- Start advertising Eddystone beacon\n" \ +"\n" + +#endif diff --git a/nrf5/softdevice/modble.c b/nrf5/softdevice/modble.c new file mode 100644 index 0000000000..9b5b3b047f --- /dev/null +++ b/nrf5/softdevice/modble.c @@ -0,0 +1,96 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include "py/runtime.h" + +#include "led.h" +#include "mpconfigboard.h" +#include "softdevice.h" + +/// \method enable() +/// Enable BLE softdevice. +mp_obj_t ble_obj_enable(void) { + printf("SoftDevice enabled\n"); + uint32_t err_code = softdevice_enable(); + if (err_code < 0) { + // TODO: raise exception. + } + return mp_const_none; +} + +/// \method disable() +/// Disable BLE softdevice. +mp_obj_t ble_obj_disable(void) { + softdevice_disable(); + return mp_const_none; +} + +/// \method enabled() +/// Get state of whether the softdevice is enabled or not. +mp_obj_t ble_obj_enabled(void) { + uint8_t is_enabled = softdevice_enabled(); + mp_int_t enabled = is_enabled; + return MP_OBJ_NEW_SMALL_INT(enabled); +} + +/// \method disable() +/// Print device address. +mp_obj_t ble_obj_address_print(void) { + softdevice_address_get(); + return mp_const_none; +} + +/// \method advertise() +/// Bluetooth Low Energy advertise. +mp_obj_t ble_obj_advertise(void) { + softdevice_advertise(); + return mp_const_none; +} + +STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_enable_obj, ble_obj_enable); +STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_disable_obj, ble_obj_disable); +STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_enabled_obj, ble_obj_enabled); +STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_address_print_obj, ble_obj_address_print); +STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_advertise_obj, ble_obj_advertise); + +STATIC const mp_map_elem_t ble_module_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ble) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_enable), (mp_obj_t)&ble_obj_enable_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_disable), (mp_obj_t)&ble_obj_disable_obj}, + { MP_OBJ_NEW_QSTR(MP_QSTR_enabled), (mp_obj_t)&ble_obj_enabled_obj}, + { MP_OBJ_NEW_QSTR(MP_QSTR_address_print), (mp_obj_t)&ble_obj_address_print_obj}, + { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)&ble_obj_advertise_obj}, +}; + + +STATIC MP_DEFINE_CONST_DICT(ble_module_globals, ble_module_globals_table); + +const mp_obj_module_t ble_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&ble_module_globals, +}; diff --git a/nrf5/softdevice/softdevice.c b/nrf5/softdevice/softdevice.c new file mode 100644 index 0000000000..965bac4c6d --- /dev/null +++ b/nrf5/softdevice/softdevice.c @@ -0,0 +1,201 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include "softdevice.h" +#include "mpconfigport.h" +#include "nrf_sdm.h" +#include "ble_gap.h" +#include "ble.h" // sd_ble_uuid_encode + +#if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) +#include "nrf_nvic.h" + +#if NRF51 +nrf_nvic_state_t nrf_nvic_state;; +#else +nrf_nvic_state_t nrf_nvic_state; +#endif // NRF51 + +#endif // (BLUETOOTH_SD != 100) + +#if (BLUETOOTH_SD == 100 ) || (BLUETOOTH_SD == 110) +void softdevice_assert_handler(uint32_t pc, uint16_t line_number, const uint8_t * p_file_name) { + printf("ERROR: SoftDevice assert!!!"); +} +#else +void softdevice_assert_handler(uint32_t id, uint32_t pc, uint32_t info) { + printf("ERROR: SoftDevice assert!!!"); +} +#endif +uint32_t softdevice_enable(void) { +#if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) + memset(&nrf_nvic_state, 0, sizeof(nrf_nvic_state_t)); +#endif + +#if (BLUETOOTH_SD == 100) || (BLUETOOTH_SD == 110) + uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, + softdevice_assert_handler); +#else + nrf_clock_lf_cfg_t clock_config = { + .source = NRF_CLOCK_LF_SRC_XTAL, + .rc_ctiv = 0, + .rc_temp_ctiv = 0, + .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM + }; + + uint32_t err_code = sd_softdevice_enable(&clock_config, + softdevice_assert_handler); +#endif + + printf("SoftDevice enable status: " UINT_FMT "\n", (uint16_t)err_code); + +#if NRF51 + err_code = sd_nvic_EnableIRQ(SWI2_IRQn); +#else + err_code = sd_nvic_EnableIRQ(SWI2_EGU2_IRQn); +#endif + + printf("IRQ enable status: " UINT_FMT "\n", (uint16_t)err_code); + + // Enable BLE stack. + ble_enable_params_t ble_enable_params; + memset(&ble_enable_params, 0x00, sizeof(ble_enable_params)); + ble_enable_params.gatts_enable_params.attr_tab_size = BLE_GATTS_ATTR_TAB_SIZE_DEFAULT; + ble_enable_params.gatts_enable_params.service_changed = 0; + + +#if (BLUETOOTH_SD == 100) || (BLUETOOTH_SD == 110) + err_code = sd_ble_enable(&ble_enable_params); +#else + +#if (BLUETOOTH_SD == 132) + uint32_t app_ram_start = 0x200039c0; + err_code = sd_ble_enable(&ble_enable_params, &app_ram_start); // 8K SD headroom from linker script. + printf("BLE ram size: " UINT_FMT "\n", (uint16_t)app_ram_start); +#else + err_code = sd_ble_enable(&ble_enable_params, (uint32_t *)0x20001870); +#endif + +#endif + + printf("BLE enable status: " UINT_FMT "\n", (uint16_t)err_code); + + return err_code; +} + +void softdevice_disable(void) { + sd_softdevice_disable(); +} + +uint8_t softdevice_enabled(void) { + uint8_t is_enabled; + uint32_t err_code = sd_softdevice_is_enabled(&is_enabled); + +#if BLUETOOTH_SD_DEBUG + printf("Is enabled status: " UINT_FMT "\n", (uint16_t)err_code); +#endif + + return is_enabled; +} + +void softdevice_address_get(void) { + ble_gap_addr_t local_ble_addr; +#if (BLUETOOTH_SD != 132) + uint32_t err_code = sd_ble_gap_address_get(&local_ble_addr); +#else + uint32_t err_code = sd_ble_gap_addr_get(&local_ble_addr); +#endif + printf("ble address, type: " HEX2_FMT ", " \ + "address: " HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT ":" \ + HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT "\n", \ + local_ble_addr.addr_type, \ + local_ble_addr.addr[5], local_ble_addr.addr[4], local_ble_addr.addr[3], \ + local_ble_addr.addr[2], local_ble_addr.addr[1], local_ble_addr.addr[0]); + + (void)err_code; +} + +#define EDDYSTONE_UUID 0xFEAA // UUID for Eddystone beacons, Big Endian. + +// URL Frame Type, fixed at 0x10. +// RSSI, 0xEE = -18 dB is the approximate signal strength at 0 m. +// URL prefix, 0x00 = "http://www". +// URL +// URL suffix, 0x01 = ".com" +#define EDDYSTONE_DATA 0x10, 0xEE, 0x00, 'm', 'i', 'c', 'r', 'o', 'p', 'y', 't', 'h', 'o', 'n', 0x01 + +#define BLE_ADV_AD_TYPE_FIELD_SIZE 1 +#define BLE_AD_TYPE_FLAGS_DATA_SIZE 1 + +#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) +#define UNIT_0_625_MS (625) +#define APP_CFG_NON_CONN_ADV_TIMEOUT 0 // Disable timeout. +#define NON_CONNECTABLE_ADV_INTERVAL MSEC_TO_UNITS(100, UNIT_0_625_MS) + +void softdevice_advertise(void) { + ble_uuid_t adv_uuids[] = {{.uuid = EDDYSTONE_UUID, .type = BLE_UUID_TYPE_BLE}}; + uint8_t encoded_size; + uint8_t uuid_encoded[2]; + uint32_t err_code = sd_ble_uuid_encode(&adv_uuids[0], &encoded_size, uuid_encoded); + + printf("Encoded UUID size: " UINT_FMT ": result: " HEX2_FMT "\n", encoded_size, (uint16_t)err_code); + printf("Encoded UUID: " HEX2_FMT " " HEX2_FMT "\n", uuid_encoded[0], uuid_encoded[1]); + + uint8_t eddystone_data[] = {EDDYSTONE_DATA}; // Temp buffer to calculate the size. + + uint8_t adv_data[] = { + (uint8_t)(BLE_ADV_AD_TYPE_FIELD_SIZE + BLE_AD_TYPE_FLAGS_DATA_SIZE), + BLE_GAP_AD_TYPE_FLAGS, + BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE, + 3, + BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE, + uuid_encoded[0], uuid_encoded[1], + (uint8_t)(BLE_ADV_AD_TYPE_FIELD_SIZE + sizeof(eddystone_data) + 2), + BLE_GAP_AD_TYPE_SERVICE_DATA, + uuid_encoded[0], uuid_encoded[1], + EDDYSTONE_DATA + }; + + // Scan response data not set. + err_code = sd_ble_gap_adv_data_set(adv_data, sizeof(adv_data), NULL, 0); + printf("Set Adv data status: " UINT_FMT ", size: " UINT_FMT "\n", (uint16_t)err_code, sizeof(adv_data)); + + ble_gap_adv_params_t m_adv_params; + + // Initialize advertising params. + memset(&m_adv_params, 0, sizeof(m_adv_params)); + m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_NONCONN_IND; + m_adv_params.p_peer_addr = NULL; // Undirected advertisement. + m_adv_params.fp = BLE_GAP_ADV_FP_ANY; + m_adv_params.interval = NON_CONNECTABLE_ADV_INTERVAL; + m_adv_params.timeout = APP_CFG_NON_CONN_ADV_TIMEOUT; + + err_code = sd_ble_gap_adv_start(&m_adv_params); + + printf("Advertisment start status: " UINT_FMT "\n", (uint16_t)err_code); +} diff --git a/nrf5/softdevice/softdevice.h b/nrf5/softdevice/softdevice.h new file mode 100644 index 0000000000..decc7e296f --- /dev/null +++ b/nrf5/softdevice/softdevice.h @@ -0,0 +1,38 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +uint32_t softdevice_enable(void); + +void softdevice_disable(void); + +uint8_t softdevice_enabled(void); + +void softdevice_address_get(void); + +void softdevice_advertise(void); + diff --git a/nrf5/uart.c b/nrf5/uart.c new file mode 100644 index 0000000000..76fb4e8a47 --- /dev/null +++ b/nrf5/uart.c @@ -0,0 +1,442 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include +#include +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/stream.h" +#include "py/mperrno.h" +#include "py/mphal.h" + +#include "uart.h" +#include "mpconfigboard.h" +#include "nrf.h" +#include "mphalport.h" +#include "hal_uart.h" + +#define CHAR_WIDTH_8BIT (0) +#define CHAR_WIDTH_9BIT (1) + +struct _pyb_uart_obj_t { + mp_obj_base_t base; + UART_HandleTypeDef uart; + IRQn_Type irqn; + pyb_uart_t uart_id : 8; + bool is_enabled : 1; + byte char_width; // 0 for 7,8 bit chars, 1 for 9 bit chars + uint16_t char_mask; // 0x7f for 7 bit, 0xff for 8 bit, 0x1ff for 9 bit + uint16_t timeout; // timeout waiting for first char + uint16_t timeout_char; // timeout waiting between chars + uint16_t read_buf_len; // len in chars; buf can hold len-1 chars + volatile uint16_t read_buf_head; // indexes first empty slot + uint16_t read_buf_tail; // indexes first full slot (not full if equals head) + byte *read_buf; // byte or uint16_t, depending on char size +}; + +STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in); + +void uart_init0(void) { + for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) { + MP_STATE_PORT(pyb_uart_obj_all)[i] = NULL; + } +} + +// unregister all interrupt sources +void uart_deinit(void) { + for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) { + pyb_uart_obj_t *uart_obj = MP_STATE_PORT(pyb_uart_obj_all)[i]; + if (uart_obj != NULL) { + pyb_uart_deinit(uart_obj); + } + } +} + +/// \method deinit() +/// Turn off the UART bus. +STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in) { + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_deinit_obj, pyb_uart_deinit); + +//// assumes Init parameters have been set up correctly +STATIC bool uart_init2(pyb_uart_obj_t * uart_obj) { + uart_obj->is_enabled = true; + + return true; +} + +void uart_irq_handler(mp_uint_t uart_id) { + +} + +bool uart_rx_any(pyb_uart_obj_t *uart_obj) { + // TODO: uart will block for now. + return true; +} + +// Waits at most timeout milliseconds for at least 1 char to become ready for +// reading (from buf or for direct reading). +// Returns true if something available, false if not. +STATIC bool uart_rx_wait(pyb_uart_obj_t *self, uint32_t timeout) { + return false; +} + +int uart_rx_char(pyb_uart_obj_t *self) { + return (int)nrf_uart_char_read(); +} + +STATIC void uart_tx_char(pyb_uart_obj_t * self, int c) { + nrf_uart_char_write((char)c); +} + + +void uart_tx_strn(pyb_uart_obj_t *uart_obj, const char *str, uint len) { + for (const char *top = str + len; str < top; str++) { + uart_tx_char(uart_obj, *str); + } +} + +void uart_tx_strn_cooked(pyb_uart_obj_t *uart_obj, const char *str, uint len) { + for (const char *top = str + len; str < top; str++) { + if (*str == '\n') { + uart_tx_char(uart_obj, '\r'); + } + uart_tx_char(uart_obj, *str); + } +} + +/******************************************************************************/ +/* Micro Python bindings */ + +STATIC void pyb_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { +} + +/// \method init(baudrate, bits=8, parity=None, stop=1, *, timeout=1000, timeout_char=0, read_buf_len=64) +/// +/// Initialise the UART bus with the given parameters: +/// +/// - `baudrate` is the clock rate. +/// - `bits` is the number of bits per byte, 7, 8 or 9. +/// - `parity` is the parity, `None`, 0 (even) or 1 (odd). +/// - `stop` is the number of stop bits, 1 or 2. +/// - `timeout` is the timeout in milliseconds to wait for the first character. +/// - `timeout_char` is the timeout in milliseconds to wait between characters. +/// - `read_buf_len` is the character length of the read buffer (0 to disable). +STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_baudrate, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 9600} }, + { MP_QSTR_bits, MP_ARG_INT, {.u_int = 8} }, + { MP_QSTR_parity, MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_stop, MP_ARG_INT, {.u_int = 1} }, + { MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UART_HWCONTROL_NONE} }, + { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} }, + { MP_QSTR_timeout_char, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_read_buf_len, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 64} }, + }; + + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // set the UART configuration values + memset(&self->uart, 0, sizeof(self->uart)); + UART_InitTypeDef *init = &self->uart.init; + + // baudrate + init->baud_rate = args[0].u_int; + + // flow control + init->flow_control = args[4].u_int; + + // init UART (if it fails, it's because the port doesn't exist) + if (!uart_init2(self)) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%d) does not exist", self->uart_id)); + } + + // set timeouts + self->timeout = args[5].u_int; + self->timeout_char = args[6].u_int; + + // setup the read buffer + m_del(byte, self->read_buf, self->read_buf_len << self->char_width); + + self->read_buf_head = 0; + self->read_buf_tail = 0; + + if (args[7].u_int <= 0) { + // no read buffer + self->read_buf_len = 0; + self->read_buf = NULL; + } else { + // read buffer using interrupts + self->read_buf_len = args[7].u_int; + self->read_buf = m_new(byte, args[7].u_int << self->char_width); + } + + hal_uart_init_t uart_init = { + .rx_pin = MICROPY_HW_UART1_RX, + .tx_pin = MICROPY_HW_UART1_TX, + .rts_pin = MICROPY_HW_UART1_RTS, + .cts_pin = MICROPY_HW_UART1_CTS, +#if MICROPY_HW_UART1_HWFC + .flow_control = true, +#else + .flow_control = false, +#endif + .use_parity = false, + .baud_rate = HAL_UART_BAUD_115K2, +#if (BLUETOOTH_SD == 100) + .irq_priority = 3 +#else + .irq_priority = 6 +#endif + }; + + nrf_uart_init(&uart_init); + + return mp_const_none; +} + +/// \classmethod \constructor(bus, ...) +/// +/// Construct a UART object. +STATIC mp_obj_t pyb_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // check arguments + mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true); + + // work out port + int uart_id = 0; + + if (MP_OBJ_IS_STR(args[0])) { + const char *port = mp_obj_str_get_str(args[0]); + if (0) { + + } else if (strcmp(port, "COM1") == 0) { + uart_id = PYB_UART_1; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%s) does not exist", port)); + } + } else { + uart_id = mp_obj_get_int(args[0]); + if (uart_id < 1 || uart_id > MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all))) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%d) does not exist", uart_id)); + } + } + + pyb_uart_obj_t *self; + if (MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1] == NULL) { + // create new UART object + self = m_new0(pyb_uart_obj_t, 1); + self->base.type = &pyb_uart_type; + self->uart_id = uart_id; + MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1] = self; + } else { + // reference existing UART object + self = MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1]; + } + + if (n_args > 1 || n_kw > 0) { + // start the peripheral + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + pyb_uart_init_helper(self, n_args - 1, args + 1, &kw_args); + } + + return self; +} + + +/// \method any() +/// Return `True` if any characters waiting, else `False`. +STATIC mp_obj_t pyb_uart_any(mp_obj_t self_in) { + pyb_uart_obj_t *self = self_in; + if (uart_rx_any(self)) { + return mp_const_true; + } else { + return mp_const_false; + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_any_obj, pyb_uart_any); + +/// \method writechar(char) +/// Write a single character on the bus. `char` is an integer to write. +/// Return value: `None`. +STATIC mp_obj_t pyb_uart_writechar(mp_obj_t self_in, mp_obj_t char_in) { + pyb_uart_obj_t *self = self_in; + + // get the character to write (might be 9 bits) + uint16_t data = mp_obj_get_int(char_in); + + for (int i = 0; i < 2; i++) { + uart_tx_char(self, (int)(&data)[i]); + } + + self->uart.instance->TASKS_STOPTX = 0; + + HAL_StatusTypeDef status = self->uart.instance->EVENTS_ERROR; + + if (status != HAL_OK) { + mp_hal_raise(status); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_uart_writechar_obj, pyb_uart_writechar); + +/// \method readchar() +/// Receive a single character on the bus. +/// Return value: The character read, as an integer. Returns -1 on timeout. +STATIC mp_obj_t pyb_uart_readchar(mp_obj_t self_in) { + pyb_uart_obj_t *self = self_in; + + if (uart_rx_wait(self, self->timeout)) { + return MP_OBJ_NEW_SMALL_INT(uart_rx_char(self)); + } else { + // return -1 on timeout + return MP_OBJ_NEW_SMALL_INT(-1); + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_readchar_obj, pyb_uart_readchar); + +// uart.sendbreak() +STATIC mp_obj_t pyb_uart_sendbreak(mp_obj_t self_in) { + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_sendbreak_obj, pyb_uart_sendbreak); + +STATIC const mp_map_elem_t pyb_uart_locals_dict_table[] = { + // instance methods + + //{ MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&pyb_uart_init_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_deinit), (mp_obj_t)&pyb_uart_deinit_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_any), (mp_obj_t)&pyb_uart_any_obj }, + + /// \method read([nbytes]) + { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&mp_stream_read_obj }, + /// \method readall() + { MP_OBJ_NEW_QSTR(MP_QSTR_readall), (mp_obj_t)&mp_stream_readall_obj }, + /// \method readline() + { MP_OBJ_NEW_QSTR(MP_QSTR_readline), (mp_obj_t)&mp_stream_unbuffered_readline_obj}, + /// \method readinto(buf[, nbytes]) + { MP_OBJ_NEW_QSTR(MP_QSTR_readinto), (mp_obj_t)&mp_stream_readinto_obj }, + /// \method writechar(buf) + { MP_OBJ_NEW_QSTR(MP_QSTR_writechar), (mp_obj_t)&pyb_uart_writechar_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readchar), (mp_obj_t)&pyb_uart_readchar_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_sendbreak), (mp_obj_t)&pyb_uart_sendbreak_obj }, + + // class constants +/* + { MP_OBJ_NEW_QSTR(MP_QSTR_RTS), MP_OBJ_NEW_SMALL_INT(UART_HWCONTROL_RTS) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CTS), MP_OBJ_NEW_SMALL_INT(UART_HWCONTROL_CTS) }, +*/ +}; + +STATIC MP_DEFINE_CONST_DICT(pyb_uart_locals_dict, pyb_uart_locals_dict_table); + +STATIC mp_uint_t pyb_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) { + pyb_uart_obj_t *self = self_in; + byte *buf = buf_in; + + // check that size is a multiple of character width + if (size & self->char_width) { + *errcode = MP_EIO; + return MP_STREAM_ERROR; + } + + // convert byte size to char size + size >>= self->char_width; + + // make sure we want at least 1 char + if (size == 0) { + return 0; + } + + // read the data + byte * orig_buf = buf; + for (;;) { + int data = uart_rx_char(self); + + *buf++ = data; + + if (--size == 0) { + // return number of bytes read + return buf - orig_buf; + } + } +} + +STATIC mp_uint_t pyb_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) { + pyb_uart_obj_t *self = self_in; + const byte *buf = buf_in; + + // check that size is a multiple of character width + if (size & self->char_width) { + *errcode = MP_EIO; + return MP_STREAM_ERROR; + } + + for (int i = 0; i < size; i++) { + uart_tx_char(self, (int)((uint8_t *)buf)[i]); + } + + HAL_StatusTypeDef status = self->uart.instance->EVENTS_ERROR; + + if (status == HAL_OK) { + // return number of bytes written + return size; + } else { + *errcode = mp_hal_status_to_errno_table[status]; + return MP_STREAM_ERROR; + } +} + +STATIC mp_uint_t pyb_uart_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) { + pyb_uart_obj_t *self = self_in; + (void)self; + return MP_STREAM_ERROR; +} + +STATIC const mp_stream_p_t uart_stream_p = { + .read = pyb_uart_read, + .write = pyb_uart_write, + .ioctl = pyb_uart_ioctl, + .is_text = false, +}; + +const mp_obj_type_t pyb_uart_type = { + { &mp_type_type }, + .name = MP_QSTR_UART, + .print = pyb_uart_print, + .make_new = pyb_uart_make_new, + .getiter = mp_identity, + .iternext = mp_stream_unbuffered_iter, + .protocol = &uart_stream_p, + .locals_dict = (mp_obj_t)&pyb_uart_locals_dict, +}; + diff --git a/nrf5/uart.h b/nrf5/uart.h new file mode 100644 index 0000000000..6243bfe969 --- /dev/null +++ b/nrf5/uart.h @@ -0,0 +1,47 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef UART_H__ +#define UART_H__ + +typedef enum { + PYB_UART_NONE = 0, + PYB_UART_1 = 1, +} pyb_uart_t; + +typedef struct _pyb_uart_obj_t pyb_uart_obj_t; +extern const mp_obj_type_t pyb_uart_type; + +void uart_init0(void); +void uart_deinit(void); +void uart_irq_handler(mp_uint_t uart_id); + +bool uart_rx_any(pyb_uart_obj_t *uart_obj); +int uart_rx_char(pyb_uart_obj_t *uart_obj); +void uart_tx_strn(pyb_uart_obj_t *uart_obj, const char *str, uint len); +void uart_tx_strn_cooked(pyb_uart_obj_t *uart_obj, const char *str, uint len); + +#endif From 0ab5ef426bb6739fa3ec4d0e5057360e14f92ed2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 16 Nov 2016 21:45:34 +0100 Subject: [PATCH 004/809] Updating modble.c method doc of address_print() to reflect the actual function name. --- nrf5/softdevice/modble.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/softdevice/modble.c b/nrf5/softdevice/modble.c index 9b5b3b047f..80a113e077 100644 --- a/nrf5/softdevice/modble.c +++ b/nrf5/softdevice/modble.c @@ -58,7 +58,7 @@ mp_obj_t ble_obj_enabled(void) { return MP_OBJ_NEW_SMALL_INT(enabled); } -/// \method disable() +/// \method address_print() /// Print device address. mp_obj_t ble_obj_address_print(void) { softdevice_address_get(); From ae99d95c1a076d7df265b57b0c65b604fea4045a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 16 Nov 2016 22:51:53 +0100 Subject: [PATCH 005/809] Updating Makefile by removing unwanted LDFLAG setting cpu to cortex-m0 in all cases. --- nrf5/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 5e6c2ca374..3da0ef0933 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -62,7 +62,6 @@ CFLAGS += -Iboards/$(BOARD) LDFLAGS = $(CFLAGS) LDFLAGS += -Xlinker -Map=$(@:.elf=.map) LDFLAGS += -mthumb -mabi=aapcs -T $(LD_FILE) -LDFLAGS += -mcpu=cortex-m0 #Debugging/Optimization ifeq ($(DEBUG), 1) From 3e31d31f3ed1e606f8dfc2641965c5eb8d7e1800 Mon Sep 17 00:00:00 2001 From: Daniel Tralamazza Date: Wed, 16 Nov 2016 23:39:40 +0100 Subject: [PATCH 006/809] move softdevice (SD) specific code from the main Makefile to their respective board/SD makefiles --- nrf5/Makefile | 51 +--------------------- nrf5/boards/pca10000/mpconfigboard.mk | 3 ++ nrf5/boards/pca10000/mpconfigboard_s110.mk | 10 +++++ nrf5/boards/pca10001/mpconfigboard.mk | 3 ++ nrf5/boards/pca10028/mpconfigboard.mk | 3 ++ nrf5/boards/pca10028/mpconfigboard_s110.mk | 13 +++++- nrf5/boards/pca10028/mpconfigboard_s120.mk | 10 +++++ nrf5/boards/pca10028/mpconfigboard_s130.mk | 10 +++++ nrf5/boards/pca10031/mpconfigboard.mk | 3 ++ nrf5/boards/pca10031/mpconfigboard_s110.mk | 12 ++++- nrf5/boards/pca10031/mpconfigboard_s120.mk | 10 +++++ nrf5/boards/pca10031/mpconfigboard_s130.mk | 10 +++++ nrf5/boards/pca10040/mpconfigboard.mk | 3 ++ nrf5/boards/pca10040/mpconfigboard_s132.mk | 11 +++++ nrf5/boards/pca10040/mpconfigboard_s1xx.mk | 11 +++++ 15 files changed, 111 insertions(+), 52 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 3da0ef0933..4ed1fcbb21 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -81,7 +81,7 @@ SRC_LIB = $(addprefix lib/,\ utils/pyhelp.c \ ) -SRC_C = \ +SRC_C += \ main.c \ device/$(MCU_VARIANT_LOWER)/system_$(MCU_VARIANT_LOWER).c \ modpyb.c \ @@ -91,54 +91,6 @@ SRC_C = \ help.c \ gccollect.c \ -ifeq ($(NRF_SOFTDEVICE),NRF_S1XX_SOFTDEVICE) - SRC_C += \ - hal/hal_uarte.c \ - softdevice/modble.c \ - softdevice/softdevice.c - - CFLAGS += -I./softdevice - CFLAGS += -I./softdevice/s1xx/headers - CFLAGS += -I./softdevice/s1xx/headers/nrf52 - CFLAGS += -DBLUETOOTH_SD=100 - CFLAGS += -DBLUETOOTH_SD_DEBUG=1 - -else ifeq ($(NRF_SOFTDEVICE),NRF_S132_SOFTDEVICE) - SRC_C += \ - hal/hal_uarte.c \ - softdevice/modble.c \ - softdevice/softdevice.c - - CFLAGS += -I./softdevice - CFLAGS += -I./softdevice/s132/headers - CFLAGS += -I./softdevice/s132/headers/nrf52 - CFLAGS += -DBLUETOOTH_SD=132 - CFLAGS += -DBLUETOOTH_SD_DEBUG=1 -else ifeq ($(NRF_SOFTDEVICE),NRF_S110_SOFTDEVICE) - SRC_C += \ - hal/hal_uart.c \ - softdevice/modble.c \ - softdevice/softdevice.c - - CFLAGS += -I./softdevice - CFLAGS += -I./softdevice/s110/headers - CFLAGS += -DBLUETOOTH_SD=110 - CFLAGS += -DBLUETOOTH_SD_DEBUG=1 -else ifeq ($(NRF_SOFTDEVICE),NRF_S130_SOFTDEVICE) - SRC_C += \ - hal/hal_uart.c \ - softdevice/modble.c \ - softdevice/softdevice.c - - CFLAGS += -I./softdevice - CFLAGS += -I./softdevice/s130/headers - CFLAGS += -DBLUETOOTH_SD=130 - CFLAGS += -DBLUETOOTH_SD_DEBUG=1 -else - SRC_C += \ - hal/hal_uart.c -endif - SRC_S = \ device/$(MCU_VARIANT_LOWER)/startup_$(MCU_VARIANT_LOWER).s \ @@ -146,7 +98,6 @@ OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o)) - .phony: all flash all: $(BUILD)/firmware.elf binary hex diff --git a/nrf5/boards/pca10000/mpconfigboard.mk b/nrf5/boards/pca10000/mpconfigboard.mk index 915ac0992c..5cc291bb92 100644 --- a/nrf5/boards/pca10000/mpconfigboard.mk +++ b/nrf5/boards/pca10000/mpconfigboard.mk @@ -1,3 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_aa.ld + +SRC_C += \ + hal/hal_uart.c diff --git a/nrf5/boards/pca10000/mpconfigboard_s110.mk b/nrf5/boards/pca10000/mpconfigboard_s110.mk index f3d9fc9ce4..32ba77b08e 100644 --- a/nrf5/boards/pca10000/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10000/mpconfigboard_s110.mk @@ -2,3 +2,13 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_aa_s110.ld NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE + +SRC_C += \ + hal/hal_uart.c \ + softdevice/modble.c \ + softdevice/softdevice.c + +CFLAGS += -I./softdevice +CFLAGS += -I./softdevice/s110/headers +CFLAGS += -DBLUETOOTH_SD=110 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10001/mpconfigboard.mk b/nrf5/boards/pca10001/mpconfigboard.mk index 915ac0992c..5cc291bb92 100644 --- a/nrf5/boards/pca10001/mpconfigboard.mk +++ b/nrf5/boards/pca10001/mpconfigboard.mk @@ -1,3 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_aa.ld + +SRC_C += \ + hal/hal_uart.c diff --git a/nrf5/boards/pca10028/mpconfigboard.mk b/nrf5/boards/pca10028/mpconfigboard.mk index 7a221a10e7..293efb4583 100644 --- a/nrf5/boards/pca10028/mpconfigboard.mk +++ b/nrf5/boards/pca10028/mpconfigboard.mk @@ -1,3 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac.ld + +SRC_C += \ + hal/hal_uart.c diff --git a/nrf5/boards/pca10028/mpconfigboard_s110.mk b/nrf5/boards/pca10028/mpconfigboard_s110.mk index 5684d66f79..57db65658b 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s110.mk @@ -1,4 +1,15 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s110.ld -NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE \ No newline at end of file +NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE + + +SRC_C += \ + hal/hal_uart.c \ + softdevice/modble.c \ + softdevice/softdevice.c + +CFLAGS += -I./softdevice +CFLAGS += -I./softdevice/s110/headers +CFLAGS += -DBLUETOOTH_SD=110 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10028/mpconfigboard_s120.mk b/nrf5/boards/pca10028/mpconfigboard_s120.mk index ce8df7382a..6113ee2ae7 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s120.mk @@ -2,3 +2,13 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s120.ld NRF_SOFTDEVICE = NRF_S120_SOFTDEVICE + +SRC_C += \ + hal/hal_uart.c \ + softdevice/modble.c \ + softdevice/softdevice.c + +CFLAGS += -I./softdevice +CFLAGS += -I./softdevice/s120/headers +CFLAGS += -DBLUETOOTH_SD=120 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10028/mpconfigboard_s130.mk b/nrf5/boards/pca10028/mpconfigboard_s130.mk index 47b423f764..ae41658107 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s130.mk @@ -2,3 +2,13 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s130.ld NRF_SOFTDEVICE = NRF_S130_SOFTDEVICE + +SRC_C += \ + hal/hal_uart.c \ + softdevice/modble.c \ + softdevice/softdevice.c + +CFLAGS += -I./softdevice +CFLAGS += -I./softdevice/s130/headers +CFLAGS += -DBLUETOOTH_SD=130 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10031/mpconfigboard.mk b/nrf5/boards/pca10031/mpconfigboard.mk index 7a221a10e7..293efb4583 100644 --- a/nrf5/boards/pca10031/mpconfigboard.mk +++ b/nrf5/boards/pca10031/mpconfigboard.mk @@ -1,3 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac.ld + +SRC_C += \ + hal/hal_uart.c diff --git a/nrf5/boards/pca10031/mpconfigboard_s110.mk b/nrf5/boards/pca10031/mpconfigboard_s110.mk index 5684d66f79..0dc8a25900 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s110.mk @@ -1,4 +1,14 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s110.ld -NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE \ No newline at end of file +NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE + +SRC_C += \ + hal/hal_uart.c \ + softdevice/modble.c \ + softdevice/softdevice.c + +CFLAGS += -I./softdevice +CFLAGS += -I./softdevice/s110/headers +CFLAGS += -DBLUETOOTH_SD=110 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10031/mpconfigboard_s120.mk b/nrf5/boards/pca10031/mpconfigboard_s120.mk index ce8df7382a..6113ee2ae7 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s120.mk @@ -2,3 +2,13 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s120.ld NRF_SOFTDEVICE = NRF_S120_SOFTDEVICE + +SRC_C += \ + hal/hal_uart.c \ + softdevice/modble.c \ + softdevice/softdevice.c + +CFLAGS += -I./softdevice +CFLAGS += -I./softdevice/s120/headers +CFLAGS += -DBLUETOOTH_SD=120 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10031/mpconfigboard_s130.mk b/nrf5/boards/pca10031/mpconfigboard_s130.mk index 47b423f764..ae41658107 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s130.mk @@ -2,3 +2,13 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s130.ld NRF_SOFTDEVICE = NRF_S130_SOFTDEVICE + +SRC_C += \ + hal/hal_uart.c \ + softdevice/modble.c \ + softdevice/softdevice.c + +CFLAGS += -I./softdevice +CFLAGS += -I./softdevice/s130/headers +CFLAGS += -DBLUETOOTH_SD=130 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10040/mpconfigboard.mk b/nrf5/boards/pca10040/mpconfigboard.mk index 6c9796e710..bbdbe3a931 100644 --- a/nrf5/boards/pca10040/mpconfigboard.mk +++ b/nrf5/boards/pca10040/mpconfigboard.mk @@ -1,3 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = NRF52 LD_FILE = boards/nrf52832_aa.ld + +SRC_C += \ + hal/hal_uart.c diff --git a/nrf5/boards/pca10040/mpconfigboard_s132.mk b/nrf5/boards/pca10040/mpconfigboard_s132.mk index 65f3c58c3c..1ba1848f61 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s132.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s132.mk @@ -2,3 +2,14 @@ MCU_SERIES = m4 MCU_VARIANT = NRF52 LD_FILE = boards/nrf52832_aa_s132.ld NRF_SOFTDEVICE = NRF_S132_SOFTDEVICE + +SRC_C += \ + hal/hal_uarte.c \ + softdevice/modble.c \ + softdevice/softdevice.c + +CFLAGS += -I./softdevice +CFLAGS += -I./softdevice/s132/headers +CFLAGS += -I./softdevice/s132/headers/nrf52 +CFLAGS += -DBLUETOOTH_SD=132 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk index efd61002ad..9b67142f78 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk @@ -2,3 +2,14 @@ MCU_SERIES = m4 MCU_VARIANT = NRF52 LD_FILE = boards/nrf52832_aa_s1xx.ld NRF_SOFTDEVICE = NRF_S1XX_SOFTDEVICE + +SRC_C += \ + hal/hal_uarte.c \ + softdevice/modble.c \ + softdevice/softdevice.c + +CFLAGS += -I./softdevice +CFLAGS += -I./softdevice/s1xx/headers +CFLAGS += -I./softdevice/s1xx/headers/nrf52 +CFLAGS += -DBLUETOOTH_SD=100 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 From 839d04f76843ed27631ff801c7aaaa6441c78047 Mon Sep 17 00:00:00 2001 From: Daniel Tralamazza Date: Wed, 16 Nov 2016 23:39:56 +0100 Subject: [PATCH 007/809] ignore default build folders --- nrf5/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 nrf5/.gitignore diff --git a/nrf5/.gitignore b/nrf5/.gitignore new file mode 100644 index 0000000000..3168dd4aba --- /dev/null +++ b/nrf5/.gitignore @@ -0,0 +1 @@ +build-*/ \ No newline at end of file From 60686a3b7547521988226386e94e32294a74597b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 17 Nov 2016 00:29:16 +0100 Subject: [PATCH 008/809] Fixing main Makefile CFLAGS concatination error when setting softdevice param --- nrf5/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 4ed1fcbb21..f258e160f7 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -55,7 +55,7 @@ CFLAGS_MCU_m4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-s CFLAGS_MCU_m0 = $(CFLAGS_CORTEX_M) --short-enums -mtune=cortex-m0 -mcpu=cortex-m0 -mfloat-abi=soft -fno-builtin -CFLAGS = $(CFLAGS_MCU_$(MCU_SERIES)) +CFLAGS += $(CFLAGS_MCU_$(MCU_SERIES)) CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) CFLAGS += -Iboards/$(BOARD) From ea75d9919f61303bccb52e6ea1ba7fb059a12f95 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 17 Nov 2016 00:33:37 +0100 Subject: [PATCH 009/809] Removing unused 'NRF_SOFTDEVICE' compile variable from all board .mk softdevice targets. --- nrf5/boards/pca10000/mpconfigboard_s110.mk | 1 - nrf5/boards/pca10028/mpconfigboard_s110.mk | 2 -- nrf5/boards/pca10028/mpconfigboard_s120.mk | 1 - nrf5/boards/pca10028/mpconfigboard_s130.mk | 1 - nrf5/boards/pca10031/mpconfigboard_s110.mk | 1 - nrf5/boards/pca10031/mpconfigboard_s120.mk | 1 - nrf5/boards/pca10031/mpconfigboard_s130.mk | 1 - nrf5/boards/pca10040/mpconfigboard_s132.mk | 1 - nrf5/boards/pca10040/mpconfigboard_s1xx.mk | 1 - 9 files changed, 10 deletions(-) diff --git a/nrf5/boards/pca10000/mpconfigboard_s110.mk b/nrf5/boards/pca10000/mpconfigboard_s110.mk index 32ba77b08e..b706522ccf 100644 --- a/nrf5/boards/pca10000/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10000/mpconfigboard_s110.mk @@ -1,7 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_aa_s110.ld -NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE SRC_C += \ hal/hal_uart.c \ diff --git a/nrf5/boards/pca10028/mpconfigboard_s110.mk b/nrf5/boards/pca10028/mpconfigboard_s110.mk index 57db65658b..c2bd3b42ef 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s110.mk @@ -1,8 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s110.ld -NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE - SRC_C += \ hal/hal_uart.c \ diff --git a/nrf5/boards/pca10028/mpconfigboard_s120.mk b/nrf5/boards/pca10028/mpconfigboard_s120.mk index 6113ee2ae7..629f8c6178 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s120.mk @@ -1,7 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s120.ld -NRF_SOFTDEVICE = NRF_S120_SOFTDEVICE SRC_C += \ hal/hal_uart.c \ diff --git a/nrf5/boards/pca10028/mpconfigboard_s130.mk b/nrf5/boards/pca10028/mpconfigboard_s130.mk index ae41658107..d4bc2e48c8 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s130.mk @@ -1,7 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s130.ld -NRF_SOFTDEVICE = NRF_S130_SOFTDEVICE SRC_C += \ hal/hal_uart.c \ diff --git a/nrf5/boards/pca10031/mpconfigboard_s110.mk b/nrf5/boards/pca10031/mpconfigboard_s110.mk index 0dc8a25900..c2bd3b42ef 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s110.mk @@ -1,7 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s110.ld -NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE SRC_C += \ hal/hal_uart.c \ diff --git a/nrf5/boards/pca10031/mpconfigboard_s120.mk b/nrf5/boards/pca10031/mpconfigboard_s120.mk index 6113ee2ae7..629f8c6178 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s120.mk @@ -1,7 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s120.ld -NRF_SOFTDEVICE = NRF_S120_SOFTDEVICE SRC_C += \ hal/hal_uart.c \ diff --git a/nrf5/boards/pca10031/mpconfigboard_s130.mk b/nrf5/boards/pca10031/mpconfigboard_s130.mk index ae41658107..d4bc2e48c8 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s130.mk @@ -1,7 +1,6 @@ MCU_SERIES = m0 MCU_VARIANT = NRF51 LD_FILE = boards/nrf51822_ac_s130.ld -NRF_SOFTDEVICE = NRF_S130_SOFTDEVICE SRC_C += \ hal/hal_uart.c \ diff --git a/nrf5/boards/pca10040/mpconfigboard_s132.mk b/nrf5/boards/pca10040/mpconfigboard_s132.mk index 1ba1848f61..28f6549a28 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s132.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s132.mk @@ -1,7 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = NRF52 LD_FILE = boards/nrf52832_aa_s132.ld -NRF_SOFTDEVICE = NRF_S132_SOFTDEVICE SRC_C += \ hal/hal_uarte.c \ diff --git a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk index 9b67142f78..73f9dc9018 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk @@ -1,7 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = NRF52 LD_FILE = boards/nrf52832_aa_s1xx.ld -NRF_SOFTDEVICE = NRF_S1XX_SOFTDEVICE SRC_C += \ hal/hal_uarte.c \ From 227998f9cd330f7d94870d97d363702a56dead0f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 13 Dec 2016 20:14:48 +0100 Subject: [PATCH 010/809] Renaming softdevice folder to sdk. --- nrf5/{softdevice => sdk}/help_sd.h | 0 nrf5/{softdevice => sdk}/modble.c | 0 nrf5/{softdevice => sdk}/softdevice.c | 0 nrf5/{softdevice => sdk}/softdevice.h | 0 4 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/{softdevice => sdk}/help_sd.h (100%) rename nrf5/{softdevice => sdk}/modble.c (100%) rename nrf5/{softdevice => sdk}/softdevice.c (100%) rename nrf5/{softdevice => sdk}/softdevice.h (100%) diff --git a/nrf5/softdevice/help_sd.h b/nrf5/sdk/help_sd.h similarity index 100% rename from nrf5/softdevice/help_sd.h rename to nrf5/sdk/help_sd.h diff --git a/nrf5/softdevice/modble.c b/nrf5/sdk/modble.c similarity index 100% rename from nrf5/softdevice/modble.c rename to nrf5/sdk/modble.c diff --git a/nrf5/softdevice/softdevice.c b/nrf5/sdk/softdevice.c similarity index 100% rename from nrf5/softdevice/softdevice.c rename to nrf5/sdk/softdevice.c diff --git a/nrf5/softdevice/softdevice.h b/nrf5/sdk/softdevice.h similarity index 100% rename from nrf5/softdevice/softdevice.h rename to nrf5/sdk/softdevice.h From d7dc0b789d3c6987dc44b8d43f541f77c1e7f164 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 13 Dec 2016 20:27:26 +0100 Subject: [PATCH 011/809] nrf5: Updating port with new content. SPI, SDcard (trough sdcard.py), Pin, and machine module. Also adding some basic modules depending on SDK and bluetooth stack from nordic semiconductor. NUS is module copied from original port by tralamazza, and new basic module for 6lowpan over BLE which can be used by modnetwork and modusocket. Basic BLE module to enable bluetooth stack and start a eddystone advertisment is kept, and still works without SDK, even if in the SDK folder (its placed there as it needs bluetooth stack from an SDK). --- nrf5/Makefile | 145 +- nrf5/boards/common.ld | 6 +- nrf5/boards/make-pins.py | 398 ++++ nrf5/boards/nrf51822_aa.ld | 6 +- nrf5/boards/nrf51822_aa_s110.ld | 6 +- nrf5/boards/nrf51822_ac_s110.ld | 4 +- nrf5/boards/nrf51822_ac_s120.ld | 2 +- nrf5/boards/nrf51822_ac_s130.ld | 4 +- nrf5/boards/nrf51_prefix.c | 32 + nrf5/boards/nrf52832_aa_s132.ld | 2 +- nrf5/boards/nrf52832_aa_s1xx.ld | 118 +- nrf5/boards/nrf52_prefix.c | 32 + nrf5/boards/pca10000/mpconfigboard.h | 2 + nrf5/boards/pca10000/mpconfigboard.mk | 4 +- nrf5/boards/pca10000/mpconfigboard_s110.mk | 12 +- nrf5/boards/pca10000/nrf51_hal_conf.h | 7 + nrf5/boards/pca10000/pins.csv | 7 + nrf5/boards/pca10001/mpconfigboard.mk | 5 +- nrf5/boards/pca10001/mpconfigboard_s110.mk | 3 + nrf5/boards/pca10001/nrf51_hal_conf.h | 8 + nrf5/boards/pca10001/pins.csv | 32 + nrf5/boards/pca10028/mpconfigboard.h | 10 + nrf5/boards/pca10028/mpconfigboard.mk | 4 +- nrf5/boards/pca10028/mpconfigboard_s110.mk | 11 +- nrf5/boards/pca10028/mpconfigboard_s120.mk | 12 +- nrf5/boards/pca10028/mpconfigboard_s130.mk | 11 +- nrf5/boards/pca10028/nrf51_hal_conf.h | 8 + nrf5/boards/pca10028/pins.csv | 32 + nrf5/boards/pca10031/mpconfigboard.h | 8 + nrf5/boards/pca10031/mpconfigboard.mk | 5 +- nrf5/boards/pca10031/mpconfigboard_s110.mk | 11 +- nrf5/boards/pca10031/mpconfigboard_s120.mk | 11 +- nrf5/boards/pca10031/mpconfigboard_s130.mk | 11 +- nrf5/boards/pca10031/nrf51_hal_conf.h | 8 + nrf5/boards/pca10031/pins.csv | 13 + nrf5/boards/pca10040/mpconfigboard.h | 8 + nrf5/boards/pca10040/mpconfigboard.mk | 4 +- nrf5/boards/pca10040/mpconfigboard_s132.mk | 12 +- nrf5/boards/pca10040/mpconfigboard_s1xx.mk | 12 +- nrf5/boards/pca10040/nrf52_hal_conf.h | 10 + nrf5/boards/pca10040/pins.csv | 30 + nrf5/builtin_open.c | 30 + nrf5/device/nrf52/startup_nrf52.s | 30 +- nrf5/fatfs_port.c | 46 + nrf5/gccollect.h | 1 + nrf5/hal/hal_spi.c | 122 ++ nrf5/hal/hal_spi.h | 105 + nrf5/hal/hal_spie.c | 135 ++ nrf5/hal/hal_time.c | 116 + nrf5/hal/hal_time.h | 32 + nrf5/hal/hal_uart.c | 4 + nrf5/hal/hal_uarte.c | 24 +- nrf5/hal/nrf51_hal.h | 31 + nrf5/hal/nrf52_hal.h | 31 + nrf5/help.c | 1 + nrf5/led.c | 1 + nrf5/led.h | 1 + nrf5/lexerfatfs.c | 35 + nrf5/main.c | 76 +- nrf5/modmachine.c | 185 ++ nrf5/modmachine.h | 42 + nrf5/modnetwork.c | 97 + nrf5/modnetwork.h | 81 + nrf5/modpyb.c | 5 +- nrf5/modules/mountsd.py | 9 + nrf5/modules/sdcard.py | 278 +++ nrf5/moduos.c | 411 ++++ nrf5/modusocket.c | 480 ++++ nrf5/modutime.c | 52 + nrf5/mpconfigport.h | 85 +- nrf5/mphalport.c | 5 + nrf5/mphalport.h | 37 +- nrf5/nrf51_af.csv | 32 + nrf5/nrf52_af.csv | 32 + nrf5/pin.c | 611 ++++++ nrf5/pin.h | 101 + nrf5/pin_defs_nrf5.h | 58 + nrf5/pin_named_pins.c | 92 + nrf5/sdk/help_sd.h | 8 + nrf5/sdk/iot_0.9.0/build.mk | 118 + nrf5/sdk/iot_0.9.0/modnwble6lowpan.c | 217 ++ nrf5/sdk/iot_0.9.0/sdk.mk | 12 + nrf5/sdk/iot_0.9.0/sdk_config.h | 46 + nrf5/sdk/iot_0.9.0/sdkhelp.c | 256 +++ nrf5/sdk/iot_0.9.0/sdkhelp.h | 27 + nrf5/sdk/modble.c | 14 +- nrf5/sdk/nrf5_sdk_conf.h | 40 + nrf5/sdk/sdk_10.0.0/sdk.mk | 17 + nrf5/sdk/sdk_12.1.0/build.mk | 103 + nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld | 40 + nrf5/sdk/sdk_12.1.0/nrf52_app_error.c | 19 + nrf5/sdk/sdk_12.1.0/nrf52_ble.c | 487 +++++ nrf5/sdk/sdk_12.1.0/nrf52_ble.h | 4 + nrf5/sdk/sdk_12.1.0/nrf52_board.h | 9 + nrf5/sdk/sdk_12.1.0/sdk.mk | 19 + nrf5/sdk/sdk_12.1.0/sdk_config.h | 2299 ++++++++++++++++++++ nrf5/sdk/sdk_common.mk | 27 + nrf5/sdk/softdevice.c | 10 +- nrf5/sdk/softdevice.h | 10 +- nrf5/spi.c | 326 +++ nrf5/spi.h | 32 + nrf5/uart.c | 2 + nrf5/uart.h | 1 + 103 files changed, 8409 insertions(+), 314 deletions(-) create mode 100644 nrf5/boards/make-pins.py create mode 100644 nrf5/boards/nrf51_prefix.c create mode 100644 nrf5/boards/nrf52_prefix.c create mode 100644 nrf5/boards/pca10000/nrf51_hal_conf.h create mode 100644 nrf5/boards/pca10000/pins.csv create mode 100644 nrf5/boards/pca10001/mpconfigboard_s110.mk create mode 100644 nrf5/boards/pca10001/nrf51_hal_conf.h create mode 100644 nrf5/boards/pca10001/pins.csv create mode 100644 nrf5/boards/pca10028/nrf51_hal_conf.h create mode 100644 nrf5/boards/pca10028/pins.csv create mode 100644 nrf5/boards/pca10031/nrf51_hal_conf.h create mode 100644 nrf5/boards/pca10031/pins.csv create mode 100644 nrf5/boards/pca10040/nrf52_hal_conf.h create mode 100644 nrf5/boards/pca10040/pins.csv create mode 100644 nrf5/builtin_open.c create mode 100644 nrf5/fatfs_port.c create mode 100644 nrf5/hal/hal_spi.c create mode 100644 nrf5/hal/hal_spi.h create mode 100644 nrf5/hal/hal_spie.c create mode 100644 nrf5/hal/hal_time.c create mode 100644 nrf5/hal/hal_time.h create mode 100644 nrf5/hal/nrf51_hal.h create mode 100644 nrf5/hal/nrf52_hal.h create mode 100644 nrf5/lexerfatfs.c create mode 100644 nrf5/modmachine.c create mode 100644 nrf5/modmachine.h create mode 100644 nrf5/modnetwork.c create mode 100644 nrf5/modnetwork.h create mode 100644 nrf5/modules/mountsd.py create mode 100644 nrf5/modules/sdcard.py create mode 100644 nrf5/moduos.c create mode 100644 nrf5/modusocket.c create mode 100644 nrf5/modutime.c create mode 100644 nrf5/nrf51_af.csv create mode 100644 nrf5/nrf52_af.csv create mode 100644 nrf5/pin.c create mode 100644 nrf5/pin.h create mode 100644 nrf5/pin_defs_nrf5.h create mode 100644 nrf5/pin_named_pins.c create mode 100644 nrf5/sdk/iot_0.9.0/build.mk create mode 100644 nrf5/sdk/iot_0.9.0/modnwble6lowpan.c create mode 100644 nrf5/sdk/iot_0.9.0/sdk.mk create mode 100644 nrf5/sdk/iot_0.9.0/sdk_config.h create mode 100644 nrf5/sdk/iot_0.9.0/sdkhelp.c create mode 100644 nrf5/sdk/iot_0.9.0/sdkhelp.h create mode 100644 nrf5/sdk/nrf5_sdk_conf.h create mode 100644 nrf5/sdk/sdk_10.0.0/sdk.mk create mode 100644 nrf5/sdk/sdk_12.1.0/build.mk create mode 100644 nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld create mode 100644 nrf5/sdk/sdk_12.1.0/nrf52_app_error.c create mode 100644 nrf5/sdk/sdk_12.1.0/nrf52_ble.c create mode 100644 nrf5/sdk/sdk_12.1.0/nrf52_ble.h create mode 100644 nrf5/sdk/sdk_12.1.0/nrf52_board.h create mode 100644 nrf5/sdk/sdk_12.1.0/sdk.mk create mode 100644 nrf5/sdk/sdk_12.1.0/sdk_config.h create mode 100644 nrf5/sdk/sdk_common.mk create mode 100644 nrf5/spi.c create mode 100644 nrf5/spi.h diff --git a/nrf5/Makefile b/nrf5/Makefile index f258e160f7..1685573f60 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -5,66 +5,89 @@ ifeq ($(wildcard boards/$(BOARD)/.),) $(error Invalid BOARD specified) endif +check_defined = \ + $(strip $(foreach 1,$1, \ + $(call __check_defined,$1,$(strip $(value 2))))) +__check_defined = \ + $(if $(value $1),, \ + $(error Undefined $1$(if $2, ($2)))) + # If SoftDevice is selected, try to use that one. -SD ?= none +SD ?= SD_LOWER = $(shell echo $(SD) | tr '[:upper:]' '[:lower:]') # TODO: Verify that it is a valid target. -ifeq ($(SD), none) +ifeq ($(SD), ) # If the build directory is not given, make it reflect the board name. BUILD ?= build-$(BOARD) include ../py/mkenv.mk include boards/$(BOARD)/mpconfigboard.mk else + $(call check_defined, SDK_ROOT, path to SDK containing softdevice) # If the build directory is not given, make it reflect the board name. BUILD ?= build-$(BOARD)-$(SD_LOWER) include ../py/mkenv.mk include boards/$(BOARD)/mpconfigboard_$(SD_LOWER).mk + + include sdk/sdk_common.mk endif # qstr definitions (must come before including py.mk) -QSTR_DEFS = qstrdefsport.h +QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h + +FROZEN_MPY_DIR = modules # include py core make definitions include ../py/py.mk + +FATFS_DIR = lib/fatfs +MPY_CROSS = ../mpy-cross/mpy-cross +MPY_TOOL = ../tools/mpy-tool.py + CROSS_COMPILE = arm-none-eabi- -MCU_VARIANT_LOWER = $(shell echo $(MCU_VARIANT) | tr '[:upper:]' '[:lower:]') +MCU_VARIANT_UPPER = $(shell echo $(MCU_VARIANT) | tr '[:lower:]' '[:upper:]') -INC = -I. +INC += -I. INC += -I.. INC += -I$(BUILD) INC += -I./device INC += -I./../lib/cmsis/inc INC += -I./device -INC += -I./device/$(MCU_VARIANT_LOWER) +INC += -I./device/$(MCU_VARIANT) INC += -I./hal -INC += -I./hal/$(MCU_VARIANT_LOWER) +INC += -I./hal/$(MCU_VARIANT) INC += -I./drivers INC += -I../lib/mp-readline -NRF_DEFINES = -D$(MCU_VARIANT) +NRF_DEFINES = -D$(MCU_VARIANT_UPPER) NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET CFLAGS_CORTEX_M = -mthumb -mabi=aapcs -fsingle-precision-constant -Wdouble-promotion -CFLAGS_MCU_m4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard +CFLAGS_MCU_m4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections CFLAGS_MCU_m0 = $(CFLAGS_CORTEX_M) --short-enums -mtune=cortex-m0 -mcpu=cortex-m0 -mfloat-abi=soft -fno-builtin + CFLAGS += $(CFLAGS_MCU_$(MCU_SERIES)) CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) +CFLAGS += -fno-strict-aliasing CFLAGS += -Iboards/$(BOARD) +CFLAGS += -DNRF5_HAL_H='<$(MCU_VARIANT)_hal.h>' +CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool +CFLAGS += -DMICROPY_MODULE_FROZEN_MPY LDFLAGS = $(CFLAGS) LDFLAGS += -Xlinker -Map=$(@:.elf=.map) -LDFLAGS += -mthumb -mabi=aapcs -T $(LD_FILE) +LDFLAGS += -mthumb -mabi=aapcs -T $(LD_FILE) -L boards/ #Debugging/Optimization ifeq ($(DEBUG), 1) +#ASMFLAGS += -g -gtabs+ CFLAGS += -O0 -ggdb LDFLAGS += -O0 else @@ -72,46 +95,132 @@ CFLAGS += -Os -DNDEBUG LDFLAGS += -Os endif -LIBS = +LIBS += \ SRC_LIB = $(addprefix lib/,\ libc/string0.c \ mp-readline/readline.c \ utils/pyexec.c \ - utils/pyhelp.c \ + utils/pyhelp.c \ + timeutils/timeutils.c \ + fatfs/ff.c \ + fatfs/option/ccsbcs.c \ + netutils/netutils.c \ + ) + +SRC_HAL = $(addprefix hal/,\ + hal_uart.c \ + hal_uarte.c \ + hal_spi.c \ + hal_spie.c \ + hal_time.c \ ) SRC_C += \ main.c \ - device/$(MCU_VARIANT_LOWER)/system_$(MCU_VARIANT_LOWER).c \ modpyb.c \ led.c \ mphalport.c \ uart.c \ + spi.c \ help.c \ gccollect.c \ + pin_named_pins.c \ + modmachine.c \ + pin.c \ + modutime.c \ + moduos.c \ + fatfs_port.c \ + builtin_open.c \ + lexerfatfs.c \ + modusocket.c \ + modnetwork.c \ + +#ifeq ($(SD), ) + +SRC_C += \ + device/$(MCU_VARIANT)/system_$(MCU_VARIANT).c \ SRC_S = \ - device/$(MCU_VARIANT_LOWER)/startup_$(MCU_VARIANT_LOWER).s \ + device/$(MCU_VARIANT)/startup_$(MCU_VARIANT).s \ -OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o)) +#endif + +FROZEN_MPY_PY_FILES := $(shell find -L $(FROZEN_MPY_DIR) -type f -name '*.py') +FROZEN_MPY_MPY_FILES := $(addprefix $(BUILD)/,$(FROZEN_MPY_PY_FILES:.py=.mpy)) + +OBJ += $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(SRC_HAL:.c=.o)) +OBJ += $(BUILD)/pins_gen.o +OBJ += $(BUILD)/$(BUILD)/frozen_mpy.o -.phony: all flash +$(BUILD)/$(FATFS_DIR)/ff.o: COPT += -Os +$(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os + +.phony: all flash sd all: $(BUILD)/firmware.elf binary hex flash: $(BUILD)/firmware.elf - nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT_LOWER) - nrfjprog --pinreset -f $(MCU_VARIANT_LOWER) + nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT) + nrfjprog --pinreset -f $(MCU_VARIANT) + +sd: + nrfjprog --eraseall -f $(MCU_VARIANT) + nrfjprog --program $(SOFTDEV_HEX) -f $(MCU_VARIANT) + nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT) + nrfjprog --pinreset -f $(MCU_VARIANT) $(BUILD)/firmware.elf: $(OBJ) $(ECHO) "LINK $@" $(Q)$(CC) $(LDFLAGS) -o $@ $(OBJ) $(LIBS) $(Q)$(SIZE) $@ +# List of sources for qstr extraction SRC_QSTR += $(SRC_C) $(SRC_MOD) $(SRC_LIB) +# Append any auto-generated sources that are needed by sources listed in +# SRC_QSTR +SRC_QSTR_AUTO_DEPS += + +# Making OBJ use an order-only depenedency on the generated pins.h file +# has the side effect of making the pins.h file before we actually compile +# any of the objects. The normal dependency generation will deal with the +# case when pins.h is modified. But when it doesn't exist, we don't know +# which source files might need it. +$(OBJ): | $(HEADER_BUILD)/pins.h + +# Use a pattern rule here so that make will only call make-pins.py once to make +# both pins_$(BOARD).c and pins.h +$(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h $(HEADER_BUILD)/%_af_const.h $(BUILD)/%_qstr.h: boards/$(BOARD)/%.csv $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD) + $(ECHO) "Create $@" + $(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE) --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) --qstr $(GEN_PINS_QSTR) --af-const $(GEN_PINS_AF_CONST) --af-py $(GEN_PINS_AF_PY) > $(GEN_PINS_SRC) + +$(BUILD)/pins_gen.o: $(BUILD)/pins_gen.c + $(call compile_c) + +MAKE_PINS = boards/make-pins.py +BOARD_PINS = boards/$(BOARD)/pins.csv +AF_FILE = $(MCU_VARIANT)_af.csv +PREFIX_FILE = boards/$(MCU_VARIANT)_prefix.c +GEN_PINS_SRC = $(BUILD)/pins_gen.c +GEN_PINS_HDR = $(HEADER_BUILD)/pins.h +GEN_PINS_QSTR = $(BUILD)/pins_qstr.h +GEN_PINS_AF_CONST = $(HEADER_BUILD)/pins_af_const.h +GEN_PINS_AF_PY = $(BUILD)/pins_af.py + +# to build .mpy files from .py files +$(BUILD)/$(FROZEN_MPY_DIR)/%.mpy: $(FROZEN_MPY_DIR)/%.py + @$(ECHO) "MPY $<" + $(Q)$(MKDIR) -p $(dir $@) + $(Q)$(MPY_CROSS) -o $@ -s $(^:$(FROZEN_MPY_DIR)/%=%) $^ + +# to build frozen_mpy.c from all .mpy files +$(BUILD)/frozen_mpy.c: $(FROZEN_MPY_MPY_FILES) $(BUILD)/genhdr/qstrdefs.generated.h + @$(ECHO) "Creating $@" + $(Q)$(PYTHON) $(MPY_TOOL) -f -q $(BUILD)/genhdr/qstrdefs.preprocessed.h -mlongint-impl mpz $(FROZEN_MPY_MPY_FILES) > $@ + include ../py/mkrules.mk include mkrules.mk diff --git a/nrf5/boards/common.ld b/nrf5/boards/common.ld index fd2dc70461..c6e4952b45 100644 --- a/nrf5/boards/common.ld +++ b/nrf5/boards/common.ld @@ -40,13 +40,13 @@ SECTIONS */ /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); + _sidata = .; /* This is the initialized data section The program executes knowing that the data is in the RAM but the loader puts the initial values in the FLASH (inidata). It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : + .data : AT (_sidata) { . = ALIGN(4); _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ @@ -56,7 +56,7 @@ SECTIONS . = ALIGN(4); _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT + } >RAM /* Uninitialized data section */ .bss : diff --git a/nrf5/boards/make-pins.py b/nrf5/boards/make-pins.py new file mode 100644 index 0000000000..11f9ffb3fd --- /dev/null +++ b/nrf5/boards/make-pins.py @@ -0,0 +1,398 @@ +#!/usr/bin/env python +"""Creates the pin file for the nRF5.""" + +from __future__ import print_function + +import argparse +import sys +import csv + +SUPPORTED_FN = { + 'UART' : ['RX', 'TX', 'CTS', 'RTS'] +} + +def parse_port_pin(name_str): + """Parses a string and returns a (port-num, pin-num) tuple.""" + if len(name_str) < 3: + raise ValueError("Expecting pin name to be at least 4 charcters.") + if name_str[0] != 'P': + raise ValueError("Expecting pin name to start with P") + if name_str[1] not in ('A'): + raise ValueError("Expecting pin port to be in A") + port = ord(name_str[1]) - ord('A') + pin_str = name_str[2:].split('/')[0] + if not pin_str.isdigit(): + raise ValueError("Expecting numeric pin number.") + return (port, int(pin_str)) + +def split_name_num(name_num): + num = None + for num_idx in range(len(name_num) - 1, -1, -1): + if not name_num[num_idx].isdigit(): + name = name_num[0:num_idx + 1] + num_str = name_num[num_idx + 1:] + if len(num_str) > 0: + num = int(num_str) + break + return name, num + + +class AlternateFunction(object): + """Holds the information associated with a pins alternate function.""" + + def __init__(self, idx, af_str): + self.idx = idx + self.af_str = af_str + + self.func = '' + self.fn_num = None + self.pin_type = '' + self.supported = False + + af_words = af_str.split('_', 1) + self.func, self.fn_num = split_name_num(af_words[0]) + if len(af_words) > 1: + self.pin_type = af_words[1] + if self.func in SUPPORTED_FN: + pin_types = SUPPORTED_FN[self.func] + if self.pin_type in pin_types: + self.supported = True + + def is_supported(self): + return self.supported + + def ptr(self): + """Returns the numbered function (i.e. USART6) for this AF.""" + if self.fn_num is None: + return self.func + return '{:s}{:d}'.format(self.func, self.fn_num) + + def mux_name(self): + return 'AF{:d}_{:s}'.format(self.idx, self.ptr()) + + def print(self): + """Prints the C representation of this AF.""" + if self.supported: + print(' AF', end='') + else: + print(' //', end='') + fn_num = self.fn_num + if fn_num is None: + fn_num = 0 + print('({:2d}, {:8s}, {:2d}, {:10s}, {:8s}), // {:s}'.format(self.idx, + self.func, fn_num, self.pin_type, self.ptr(), self.af_str)) + + def qstr_list(self): + return [self.mux_name()] + + +class Pin(object): + """Holds the information associated with a pin.""" + + def __init__(self, port, pin): + self.port = port + self.pin = pin + self.alt_fn = [] + self.alt_fn_count = 0 + self.adc_num = 0 + self.adc_channel = 0 + self.board_pin = False + + def port_letter(self): + return chr(self.port + ord('A')) + + def cpu_pin_name(self): + return '{:s}{:d}'.format(self.port_letter(), self.pin) + + def is_board_pin(self): + return self.board_pin + + def set_is_board_pin(self): + self.board_pin = True + + def parse_adc(self, adc_str): + if (adc_str[:3] != 'ADC'): + return + (adc,channel) = adc_str.split('_') + for idx in range(3, len(adc)): + adc_num = int(adc[idx]) # 1, 2, or 3 + self.adc_num |= (1 << (adc_num - 1)) + self.adc_channel = int(channel[2:]) + + def parse_af(self, af_idx, af_strs_in): + if len(af_strs_in) == 0: + return + # If there is a slash, then the slash separates 2 aliases for the + # same alternate function. + af_strs = af_strs_in.split('/') + for af_str in af_strs: + alt_fn = AlternateFunction(af_idx, af_str) + self.alt_fn.append(alt_fn) + if alt_fn.is_supported(): + self.alt_fn_count += 1 + + def alt_fn_name(self, null_if_0=False): + if null_if_0 and self.alt_fn_count == 0: + return 'NULL' + return 'pin_{:s}_af'.format(self.cpu_pin_name()) + + def adc_num_str(self): + str = '' + for adc_num in range(1,4): + if self.adc_num & (1 << (adc_num - 1)): + if len(str) > 0: + str += ' | ' + str += 'PIN_ADC' + str += chr(ord('0') + adc_num) + if len(str) == 0: + str = '0' + return str + + def print(self): + if self.alt_fn_count == 0: + print("// ", end='') + print('const pin_af_obj_t {:s}[] = {{'.format(self.alt_fn_name())) + for alt_fn in self.alt_fn: + alt_fn.print() + if self.alt_fn_count == 0: + print("// ", end='') + print('};') + print('') + print('const pin_obj_t pin_{:s} = PIN({:s}, {:d}, {:s}, {:s}, {:d});'.format( + self.cpu_pin_name(), self.port_letter(), self.pin, + self.alt_fn_name(null_if_0=True), + self.adc_num_str(), self.adc_channel)) + print('') + + def print_header(self, hdr_file): + hdr_file.write('extern const pin_obj_t pin_{:s};\n'. + format(self.cpu_pin_name())) + if self.alt_fn_count > 0: + hdr_file.write('extern const pin_af_obj_t pin_{:s}_af[];\n'. + format(self.cpu_pin_name())) + + def qstr_list(self): + result = [] + for alt_fn in self.alt_fn: + if alt_fn.is_supported(): + result += alt_fn.qstr_list() + return result + + +class NamedPin(object): + + def __init__(self, name, pin): + self._name = name + self._pin = pin + + def pin(self): + return self._pin + + def name(self): + return self._name + + +class Pins(object): + + def __init__(self): + self.cpu_pins = [] # list of NamedPin objects + self.board_pins = [] # list of NamedPin objects + + def find_pin(self, port_num, pin_num): + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.port == port_num and pin.pin == pin_num: + return pin + + def parse_af_file(self, filename, pinname_col, af_col): + with open(filename, 'r') as csvfile: + rows = csv.reader(csvfile) + for row in rows: + try: + (port_num, pin_num) = parse_port_pin(row[pinname_col]) + except: + continue + pin = Pin(port_num, pin_num) + for af_idx in range(af_col, len(row)): + if af_idx >= af_col: + pin.parse_af(af_idx - af_col, row[af_idx]) + self.cpu_pins.append(NamedPin(pin.cpu_pin_name(), pin)) + + def parse_board_file(self, filename): + with open(filename, 'r') as csvfile: + rows = csv.reader(csvfile) + for row in rows: + try: + (port_num, pin_num) = parse_port_pin(row[1]) + except: + continue + pin = self.find_pin(port_num, pin_num) + if pin: + pin.set_is_board_pin() + self.board_pins.append(NamedPin(row[0], pin)) + + def print_named(self, label, named_pins): + print('STATIC const mp_map_elem_t pin_{:s}_pins_locals_dict_table[] = {{'.format(label)) + for named_pin in named_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + print(' {{ MP_OBJ_NEW_QSTR(MP_QSTR_{:s}), (mp_obj_t)&pin_{:s} }},'.format(named_pin.name(), pin.cpu_pin_name())) + print('};') + print('MP_DEFINE_CONST_DICT(pin_{:s}_pins_locals_dict, pin_{:s}_pins_locals_dict_table);'.format(label, label)); + + def print(self): + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + pin.print() + self.print_named('cpu', self.cpu_pins) + print('') + self.print_named('board', self.board_pins) + + def print_adc(self, adc_num): + print(''); + print('const pin_obj_t * const pin_adc{:d}[] = {{'.format(adc_num)) + for channel in range(16): + adc_found = False + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if (pin.is_board_pin() and + (pin.adc_num & (1 << (adc_num - 1))) and (pin.adc_channel == channel)): + print(' &pin_{:s}, // {:d}'.format(pin.cpu_pin_name(), channel)) + adc_found = True + break + if not adc_found: + print(' NULL, // {:d}'.format(channel)) + print('};') + + + def print_header(self, hdr_filename): + with open(hdr_filename, 'wt') as hdr_file: + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + pin.print_header(hdr_file) + hdr_file.write('extern const pin_obj_t * const pin_adc1[];\n') + hdr_file.write('extern const pin_obj_t * const pin_adc2[];\n') + hdr_file.write('extern const pin_obj_t * const pin_adc3[];\n') + + def print_qstr(self, qstr_filename): + with open(qstr_filename, 'wt') as qstr_file: + qstr_set = set([]) + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + qstr_set |= set(pin.qstr_list()) + qstr_set |= set([named_pin.name()]) + for named_pin in self.board_pins: + qstr_set |= set([named_pin.name()]) + for qstr in sorted(qstr_set): + print('Q({})'.format(qstr), file=qstr_file) + + + def print_af_hdr(self, af_const_filename): + with open(af_const_filename, 'wt') as af_const_file: + af_hdr_set = set([]) + mux_name_width = 0 + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + for af in pin.alt_fn: + if af.is_supported(): + mux_name = af.mux_name() + af_hdr_set |= set([mux_name]) + if len(mux_name) > mux_name_width: + mux_name_width = len(mux_name) + for mux_name in sorted(af_hdr_set): + key = 'MP_OBJ_NEW_QSTR(MP_QSTR_{}),'.format(mux_name) + val = 'MP_OBJ_NEW_SMALL_INT(GPIO_{})'.format(mux_name) + print(' { %-*s %s },' % (mux_name_width + 26, key, val), + file=af_const_file) + + def print_af_py(self, af_py_filename): + with open(af_py_filename, 'wt') as af_py_file: + print('PINS_AF = (', file=af_py_file); + for named_pin in self.board_pins: + print(" ('%s', " % named_pin.name(), end='', file=af_py_file) + for af in named_pin.pin().alt_fn: + if af.is_supported(): + print("(%d, '%s'), " % (af.idx, af.af_str), end='', file=af_py_file) + print('),', file=af_py_file) + print(')', file=af_py_file) + + +def main(): + parser = argparse.ArgumentParser( + prog="make-pins.py", + usage="%(prog)s [options] [command]", + description="Generate board specific pin file" + ) + parser.add_argument( + "-a", "--af", + dest="af_filename", + help="Specifies the alternate function file for the chip", + default="nrf.csv" + ) + parser.add_argument( + "--af-const", + dest="af_const_filename", + help="Specifies header file for alternate function constants.", + default="build/pins_af_const.h" + ) + parser.add_argument( + "--af-py", + dest="af_py_filename", + help="Specifies the filename for the python alternate function mappings.", + default="build/pins_af.py" + ) + parser.add_argument( + "-b", "--board", + dest="board_filename", + help="Specifies the board file", + ) + parser.add_argument( + "-p", "--prefix", + dest="prefix_filename", + help="Specifies beginning portion of generated pins file", + default="nrf52_prefix.c" + ) + parser.add_argument( + "-q", "--qstr", + dest="qstr_filename", + help="Specifies name of generated qstr header file", + default="build/pins_qstr.h" + ) + parser.add_argument( + "-r", "--hdr", + dest="hdr_filename", + help="Specifies name of generated pin header file", + default="build/pins.h" + ) + args = parser.parse_args(sys.argv[1:]) + + pins = Pins() + + print('// This file was automatically generated by make-pins.py') + print('//') + if args.af_filename: + print('// --af {:s}'.format(args.af_filename)) + pins.parse_af_file(args.af_filename, 1, 2) + + if args.board_filename: + print('// --board {:s}'.format(args.board_filename)) + pins.parse_board_file(args.board_filename) + + if args.prefix_filename: + print('// --prefix {:s}'.format(args.prefix_filename)) + print('') + with open(args.prefix_filename, 'r') as prefix_file: + print(prefix_file.read()) + pins.print() + pins.print_header(args.hdr_filename) + pins.print_qstr(args.qstr_filename) + pins.print_af_hdr(args.af_const_filename) + pins.print_af_py(args.af_py_filename) + + +if __name__ == "__main__": + main() diff --git a/nrf5/boards/nrf51822_aa.ld b/nrf5/boards/nrf51822_aa.ld index ddbd5847fb..e25ae3b874 100644 --- a/nrf5/boards/nrf51822_aa.ld +++ b/nrf5/boards/nrf51822_aa.ld @@ -13,8 +13,8 @@ MEMORY } /* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 2K; -_minimum_heap_size = 10K; +_minimum_stack_size = 4K; +_minimum_heap_size = 8K; /* top end of the stack */ @@ -23,6 +23,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20001000; /* tunable */ +_heap_end = 0x20002000; /* tunable */ INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf51822_aa_s110.ld b/nrf5/boards/nrf51822_aa_s110.ld index ef9a2c2f44..e798bf3afe 100644 --- a/nrf5/boards/nrf51822_aa_s110.ld +++ b/nrf5/boards/nrf51822_aa_s110.ld @@ -8,10 +8,10 @@ MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */ - FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 175 KiB */ - RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x002000 /* 9.89 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 159 KiB */ + RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x002000 /* 8 KiB */ } - + /* produce a link error if there is not this amount of RAM for these sections */ _minimum_stack_size = 2K; _minimum_heap_size = 4K; diff --git a/nrf5/boards/nrf51822_ac_s110.ld b/nrf5/boards/nrf51822_ac_s110.ld index e1863c8bab..ec1aff397d 100644 --- a/nrf5/boards/nrf51822_ac_s110.ld +++ b/nrf5/boards/nrf51822_ac_s110.ld @@ -8,8 +8,8 @@ MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */ - FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 175 KiB */ - RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x006000 /* 9.89 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 159 KiB */ + RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x006000 /* 24 KiB */ } /* produce a link error if there is not this amount of RAM for these sections */ diff --git a/nrf5/boards/nrf51822_ac_s120.ld b/nrf5/boards/nrf51822_ac_s120.ld index e7a67f2b08..3de7083fd7 100644 --- a/nrf5/boards/nrf51822_ac_s120.ld +++ b/nrf5/boards/nrf51822_ac_s120.ld @@ -8,7 +8,7 @@ MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ FLASH_ISR (rx) : ORIGIN = 0x0001D000, LENGTH = 0x000400 /* sector 0, 1 KiB */ - FLASH_TEXT (rx) : ORIGIN = 0x0001D400, LENGTH = 0x027c00 /* 139 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x0001D400, LENGTH = 0x022c00 /* 139 KiB */ RAM (xrw) : ORIGIN = 0x20002800, LENGTH = 0x005800 /* 22 KiB */ } diff --git a/nrf5/boards/nrf51822_ac_s130.ld b/nrf5/boards/nrf51822_ac_s130.ld index f0e3bdbabb..1845f973ff 100644 --- a/nrf5/boards/nrf51822_ac_s130.ld +++ b/nrf5/boards/nrf51822_ac_s130.ld @@ -1,5 +1,5 @@ /* - GNU linker script for NRF51822 AC w/ S130 2.0.0 SoftDevice + GNU linker script for NRF51822 AC w/ S130 2.0.1 SoftDevice */ /* Specify the memory areas */ SEARCH_DIR(.) @@ -9,7 +9,7 @@ MEMORY FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ FLASH_ISR (rx) : ORIGIN = 0x0001b000, LENGTH = 0x000400 /* sector 0, 1 KiB */ FLASH_TEXT (rx) : ORIGIN = 0x0001b400, LENGTH = 0x024c00 /* 147 KiB */ - RAM (xrw) : ORIGIN = 0x20001870, LENGTH = 0x002970 /* 9.89 KiB */ + RAM (xrw) : ORIGIN = 0x200013c8, LENGTH = 0x006c38 /* 27 KiB */ } /* produce a link error if there is not this amount of RAM for these sections */ diff --git a/nrf5/boards/nrf51_prefix.c b/nrf5/boards/nrf51_prefix.c new file mode 100644 index 0000000000..402bde1a60 --- /dev/null +++ b/nrf5/boards/nrf51_prefix.c @@ -0,0 +1,32 @@ +// nrf51_prefix.c becomes the initial portion of the generated pins file. + +#include + +#include "py/obj.h" +#include "py/mphal.h" +#include "pin.h" + +#define AF(af_idx, af_fn, af_unit, af_type, af_ptr) \ +{ \ + { &pin_af_type }, \ + .name = MP_QSTR_AF ## af_idx ## _ ## af_fn ## af_unit, \ + .idx = (af_idx), \ + .fn = AF_FN_ ## af_fn, \ + .unit = (af_unit), \ + .type = AF_PIN_TYPE_ ## af_fn ## _ ## af_type, \ + .af_fn = (af_ptr) \ +} + +#define PIN(p_port, p_pin, p_af, p_adc_num, p_adc_channel) \ +{ \ + { &pin_type }, \ + .name = MP_QSTR_ ## p_port ## p_pin, \ + .port = PORT_ ## p_port, \ + .pin = (p_pin), \ + .num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \ + .pin_mask = (1 << p_pin), \ + .gpio = GPIO_BASE, \ + .af = p_af, \ + .adc_num = p_adc_num, \ + .adc_channel = p_adc_channel, \ +} diff --git a/nrf5/boards/nrf52832_aa_s132.ld b/nrf5/boards/nrf52832_aa_s132.ld index 9aabfac28e..629ed12c9c 100644 --- a/nrf5/boards/nrf52832_aa_s132.ld +++ b/nrf5/boards/nrf52832_aa_s132.ld @@ -8,7 +8,7 @@ MEMORY FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */ FLASH_ISR (rx) : ORIGIN = 0x0001f000, LENGTH = 0x001000 /* sector 0, 4 KiB */ FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 /* 396 KiB */ - RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 57.89 KiB, give 8KiB headroom for softdevice */ + RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 49.5 KiB, give 8KiB headroom for softdevice */ } /* produce a link error if there is not this amount of RAM for these sections */ diff --git a/nrf5/boards/nrf52832_aa_s1xx.ld b/nrf5/boards/nrf52832_aa_s1xx.ld index 781492085c..c2188afd47 100644 --- a/nrf5/boards/nrf52832_aa_s1xx.ld +++ b/nrf5/boards/nrf52832_aa_s1xx.ld @@ -5,15 +5,15 @@ /* Specify the memory areas */ MEMORY { - FLASH (rx) : ORIGIN = 0x0001F000, LENGTH = 0x61000 - FLASH_ISR (rx) : ORIGIN = 0x0001F000, LENGTH = 0x00400 - FLASH_TEXT (rx) : ORIGIN = 0x0001F400, LENGTH = 0x60c00 - RAM (xrw) : ORIGIN = 0x20002800, LENGTH = 0x0D800 + FLASH (rx) : ORIGIN = 0x0001F000, LENGTH = 0x061000 /* entire flash, 512 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x0001F000, LENGTH = 0x000400 /* sector 0, 4 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x0001F400, LENGTH = 0x060c00 /* 396 KiB */ + RAM (xrw) : ORIGIN = 0x20002800, LENGTH = 0x00D800 /* 54 KiB */ } /* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 6K; -_minimum_heap_size = 16K; +_minimum_stack_size = 16K; +_minimum_heap_size = 20K; /* top end of the stack */ @@ -22,108 +22,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20005000; /* tunable */ +_heap_end = 0x20008800; /* tunable */ -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } >FLASH - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - */ - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - _ram_start = .; /* create a global symbol at ram start for garbage collector */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - _heap_start = .; /* define a global symbol at heap start */ - . = . + _minimum_heap_size; - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - /* Remove information from the standard libraries */ - /* - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - */ - - .ARM.attributes 0 : { *(.ARM.attributes) } -} +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/nrf52_prefix.c b/nrf5/boards/nrf52_prefix.c new file mode 100644 index 0000000000..6bb07dd3a1 --- /dev/null +++ b/nrf5/boards/nrf52_prefix.c @@ -0,0 +1,32 @@ +// nrf52_prefix.c becomes the initial portion of the generated pins file. + +#include + +#include "py/obj.h" +#include "py/mphal.h" +#include "pin.h" + +#define AF(af_idx, af_fn, af_unit, af_type, af_ptr) \ +{ \ + { &pin_af_type }, \ + .name = MP_QSTR_AF ## af_idx ## _ ## af_fn ## af_unit, \ + .idx = (af_idx), \ + .fn = AF_FN_ ## af_fn, \ + .unit = (af_unit), \ + .type = AF_PIN_TYPE_ ## af_fn ## _ ## af_type, \ + .af_fn = (af_ptr) \ +} + +#define PIN(p_port, p_pin, p_af, p_adc_num, p_adc_channel) \ +{ \ + { &pin_type }, \ + .name = MP_QSTR_ ## p_port ## p_pin, \ + .port = PORT_ ## p_port, \ + .pin = (p_pin), \ + .num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \ + .pin_mask = (1 << p_pin), \ + .gpio = GPIO_BASE, \ + .af = p_af, \ + .adc_num = p_adc_num, \ + .adc_channel = p_adc_channel, \ +} diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf5/boards/pca10000/mpconfigboard.h index f922fe8761..2e2326da20 100644 --- a/nrf5/boards/pca10000/mpconfigboard.h +++ b/nrf5/boards/pca10000/mpconfigboard.h @@ -30,6 +30,8 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" +#define MICROPY_PY_MACHINE_SPI (0) + #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/pca10000/mpconfigboard.mk b/nrf5/boards/pca10000/mpconfigboard.mk index 5cc291bb92..d2a566aea8 100644 --- a/nrf5/boards/pca10000/mpconfigboard.mk +++ b/nrf5/boards/pca10000/mpconfigboard.mk @@ -1,6 +1,4 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_aa.ld -SRC_C += \ - hal/hal_uart.c diff --git a/nrf5/boards/pca10000/mpconfigboard_s110.mk b/nrf5/boards/pca10000/mpconfigboard_s110.mk index b706522ccf..5a3fa8e1c3 100644 --- a/nrf5/boards/pca10000/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10000/mpconfigboard_s110.mk @@ -1,13 +1,3 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_aa_s110.ld - -SRC_C += \ - hal/hal_uart.c \ - softdevice/modble.c \ - softdevice/softdevice.c - -CFLAGS += -I./softdevice -CFLAGS += -I./softdevice/s110/headers -CFLAGS += -DBLUETOOTH_SD=110 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10000/nrf51_hal_conf.h b/nrf5/boards/pca10000/nrf51_hal_conf.h new file mode 100644 index 0000000000..1848c81034 --- /dev/null +++ b/nrf5/boards/pca10000/nrf51_hal_conf.h @@ -0,0 +1,7 @@ +#ifndef NRF51_HAL_CONF_H__ +#define NRF51_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED + +#endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10000/pins.csv b/nrf5/boards/pca10000/pins.csv new file mode 100644 index 0000000000..cc3f62db1a --- /dev/null +++ b/nrf5/boards/pca10000/pins.csv @@ -0,0 +1,7 @@ +UART_RTS,PA8 +UART_TX,PA9 +UART_CTS,PA10 +UART_RX,PA11 +LED_RED,PA21 +LED_GREEN,PA22 +LED_BLUE,PA23 \ No newline at end of file diff --git a/nrf5/boards/pca10001/mpconfigboard.mk b/nrf5/boards/pca10001/mpconfigboard.mk index 5cc291bb92..40a74fd176 100644 --- a/nrf5/boards/pca10001/mpconfigboard.mk +++ b/nrf5/boards/pca10001/mpconfigboard.mk @@ -1,6 +1,3 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_aa.ld - -SRC_C += \ - hal/hal_uart.c diff --git a/nrf5/boards/pca10001/mpconfigboard_s110.mk b/nrf5/boards/pca10001/mpconfigboard_s110.mk new file mode 100644 index 0000000000..5a3fa8e1c3 --- /dev/null +++ b/nrf5/boards/pca10001/mpconfigboard_s110.mk @@ -0,0 +1,3 @@ +MCU_SERIES = m0 +MCU_VARIANT = nrf51 +LD_FILE = boards/nrf51822_aa_s110.ld diff --git a/nrf5/boards/pca10001/nrf51_hal_conf.h b/nrf5/boards/pca10001/nrf51_hal_conf.h new file mode 100644 index 0000000000..67cbc983ba --- /dev/null +++ b/nrf5/boards/pca10001/nrf51_hal_conf.h @@ -0,0 +1,8 @@ +#ifndef NRF51_HAL_CONF_H__ +#define NRF51_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED + +#endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10001/pins.csv b/nrf5/boards/pca10001/pins.csv new file mode 100644 index 0000000000..2b16969869 --- /dev/null +++ b/nrf5/boards/pca10001/pins.csv @@ -0,0 +1,32 @@ +PA0,PA0 +PA1,PA1 +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA5,PA5 +PA6,PA6 +PA7,PA7 +UART_RTS,PA8 +UART_TX,PA9 +UART_CTS,PA10 +UART_RX,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 \ No newline at end of file diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index cde989bc25..b854e685e3 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -30,6 +30,9 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" +#define MICROPY_PY_USOCKET (0) +#define MICROPY_PY_NETWORK (0) + #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) @@ -57,4 +60,11 @@ #define MICROPY_HW_UART1_RTS (8) #define MICROPY_HW_UART1_HWFC (0) +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (1) // A3 +#define MICROPY_HW_SPI0_MOSI (2) // A2 +#define MICROPY_HW_SPI0_MISO (3) // A1 +#define MICROPY_HW_SPI0_NSS (4) // A4 + #define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10028/mpconfigboard.mk b/nrf5/boards/pca10028/mpconfigboard.mk index 293efb4583..ac92424ec7 100644 --- a/nrf5/boards/pca10028/mpconfigboard.mk +++ b/nrf5/boards/pca10028/mpconfigboard.mk @@ -1,6 +1,4 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_ac.ld -SRC_C += \ - hal/hal_uart.c diff --git a/nrf5/boards/pca10028/mpconfigboard_s110.mk b/nrf5/boards/pca10028/mpconfigboard_s110.mk index c2bd3b42ef..54766bd429 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s110.mk @@ -1,13 +1,4 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_ac_s110.ld -SRC_C += \ - hal/hal_uart.c \ - softdevice/modble.c \ - softdevice/softdevice.c - -CFLAGS += -I./softdevice -CFLAGS += -I./softdevice/s110/headers -CFLAGS += -DBLUETOOTH_SD=110 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10028/mpconfigboard_s120.mk b/nrf5/boards/pca10028/mpconfigboard_s120.mk index 629f8c6178..e9b7770dd0 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s120.mk @@ -1,13 +1,3 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_ac_s120.ld - -SRC_C += \ - hal/hal_uart.c \ - softdevice/modble.c \ - softdevice/softdevice.c - -CFLAGS += -I./softdevice -CFLAGS += -I./softdevice/s120/headers -CFLAGS += -DBLUETOOTH_SD=120 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10028/mpconfigboard_s130.mk b/nrf5/boards/pca10028/mpconfigboard_s130.mk index d4bc2e48c8..3f55086b49 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s130.mk @@ -1,13 +1,4 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_ac_s130.ld -SRC_C += \ - hal/hal_uart.c \ - softdevice/modble.c \ - softdevice/softdevice.c - -CFLAGS += -I./softdevice -CFLAGS += -I./softdevice/s130/headers -CFLAGS += -DBLUETOOTH_SD=130 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10028/nrf51_hal_conf.h b/nrf5/boards/pca10028/nrf51_hal_conf.h new file mode 100644 index 0000000000..67cbc983ba --- /dev/null +++ b/nrf5/boards/pca10028/nrf51_hal_conf.h @@ -0,0 +1,8 @@ +#ifndef NRF51_HAL_CONF_H__ +#define NRF51_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED + +#endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10028/pins.csv b/nrf5/boards/pca10028/pins.csv new file mode 100644 index 0000000000..2b16969869 --- /dev/null +++ b/nrf5/boards/pca10028/pins.csv @@ -0,0 +1,32 @@ +PA0,PA0 +PA1,PA1 +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA5,PA5 +PA6,PA6 +PA7,PA7 +UART_RTS,PA8 +UART_TX,PA9 +UART_CTS,PA10 +UART_RX,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 \ No newline at end of file diff --git a/nrf5/boards/pca10031/mpconfigboard.h b/nrf5/boards/pca10031/mpconfigboard.h index 2cda988ff0..743375ea0e 100644 --- a/nrf5/boards/pca10031/mpconfigboard.h +++ b/nrf5/boards/pca10031/mpconfigboard.h @@ -57,4 +57,12 @@ #define MICROPY_HW_UART1_RTS (8) #define MICROPY_HW_UART1_HWFC (0) +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (15) // A15 +#define MICROPY_HW_SPI0_MOSI (16) // A16 +#define MICROPY_HW_SPI0_MISO (17) // A17 +#define MICROPY_HW_SPI0_NSS (18) // A18 + + #define HELP_TEXT_BOARD_LED "1,2,3" diff --git a/nrf5/boards/pca10031/mpconfigboard.mk b/nrf5/boards/pca10031/mpconfigboard.mk index 293efb4583..72a21aa76f 100644 --- a/nrf5/boards/pca10031/mpconfigboard.mk +++ b/nrf5/boards/pca10031/mpconfigboard.mk @@ -1,6 +1,3 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_ac.ld - -SRC_C += \ - hal/hal_uart.c diff --git a/nrf5/boards/pca10031/mpconfigboard_s110.mk b/nrf5/boards/pca10031/mpconfigboard_s110.mk index c2bd3b42ef..54766bd429 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s110.mk @@ -1,13 +1,4 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_ac_s110.ld -SRC_C += \ - hal/hal_uart.c \ - softdevice/modble.c \ - softdevice/softdevice.c - -CFLAGS += -I./softdevice -CFLAGS += -I./softdevice/s110/headers -CFLAGS += -DBLUETOOTH_SD=110 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10031/mpconfigboard_s120.mk b/nrf5/boards/pca10031/mpconfigboard_s120.mk index 629f8c6178..dc1de98188 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s120.mk @@ -1,13 +1,4 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_ac_s120.ld -SRC_C += \ - hal/hal_uart.c \ - softdevice/modble.c \ - softdevice/softdevice.c - -CFLAGS += -I./softdevice -CFLAGS += -I./softdevice/s120/headers -CFLAGS += -DBLUETOOTH_SD=120 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10031/mpconfigboard_s130.mk b/nrf5/boards/pca10031/mpconfigboard_s130.mk index d4bc2e48c8..3f55086b49 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s130.mk @@ -1,13 +1,4 @@ MCU_SERIES = m0 -MCU_VARIANT = NRF51 +MCU_VARIANT = nrf51 LD_FILE = boards/nrf51822_ac_s130.ld -SRC_C += \ - hal/hal_uart.c \ - softdevice/modble.c \ - softdevice/softdevice.c - -CFLAGS += -I./softdevice -CFLAGS += -I./softdevice/s130/headers -CFLAGS += -DBLUETOOTH_SD=130 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10031/nrf51_hal_conf.h b/nrf5/boards/pca10031/nrf51_hal_conf.h new file mode 100644 index 0000000000..67cbc983ba --- /dev/null +++ b/nrf5/boards/pca10031/nrf51_hal_conf.h @@ -0,0 +1,8 @@ +#ifndef NRF51_HAL_CONF_H__ +#define NRF51_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED + +#endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10031/pins.csv b/nrf5/boards/pca10031/pins.csv new file mode 100644 index 0000000000..b27a12b91a --- /dev/null +++ b/nrf5/boards/pca10031/pins.csv @@ -0,0 +1,13 @@ +UART_RTS,PA8 +UART_TX,PA9 +UART_CTS,PA10 +UART_RX,PA11 +LED_RED,PA21 +LED_GREEN,PA22 +LED_BLUE,PA23 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 \ No newline at end of file diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index af655f0209..8dd0d43d0c 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -57,4 +57,12 @@ #define MICROPY_HW_UART1_RTS (5) #define MICROPY_HW_UART1_HWFC (1) +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (25) // A25 (Arduino D13) +#define MICROPY_HW_SPI0_MOSI (23) // A23 (Arduino D11) +#define MICROPY_HW_SPI0_MISO (24) // A24 (Arduino D12) +#define MICROPY_HW_SPI0_NSS (22) // A22 (Arduino D10) + + #define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10040/mpconfigboard.mk b/nrf5/boards/pca10040/mpconfigboard.mk index bbdbe3a931..3b6af95f75 100644 --- a/nrf5/boards/pca10040/mpconfigboard.mk +++ b/nrf5/boards/pca10040/mpconfigboard.mk @@ -1,6 +1,4 @@ MCU_SERIES = m4 -MCU_VARIANT = NRF52 +MCU_VARIANT = nrf52 LD_FILE = boards/nrf52832_aa.ld -SRC_C += \ - hal/hal_uart.c diff --git a/nrf5/boards/pca10040/mpconfigboard_s132.mk b/nrf5/boards/pca10040/mpconfigboard_s132.mk index 28f6549a28..090a08b4b6 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s132.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s132.mk @@ -1,14 +1,4 @@ MCU_SERIES = m4 -MCU_VARIANT = NRF52 +MCU_VARIANT = nrf52 LD_FILE = boards/nrf52832_aa_s132.ld -SRC_C += \ - hal/hal_uarte.c \ - softdevice/modble.c \ - softdevice/softdevice.c - -CFLAGS += -I./softdevice -CFLAGS += -I./softdevice/s132/headers -CFLAGS += -I./softdevice/s132/headers/nrf52 -CFLAGS += -DBLUETOOTH_SD=132 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk index 73f9dc9018..81727fe5de 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk @@ -1,14 +1,4 @@ MCU_SERIES = m4 -MCU_VARIANT = NRF52 +MCU_VARIANT = nrf52 LD_FILE = boards/nrf52832_aa_s1xx.ld -SRC_C += \ - hal/hal_uarte.c \ - softdevice/modble.c \ - softdevice/softdevice.c - -CFLAGS += -I./softdevice -CFLAGS += -I./softdevice/s1xx/headers -CFLAGS += -I./softdevice/s1xx/headers/nrf52 -CFLAGS += -DBLUETOOTH_SD=100 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 diff --git a/nrf5/boards/pca10040/nrf52_hal_conf.h b/nrf5/boards/pca10040/nrf52_hal_conf.h new file mode 100644 index 0000000000..b879b974aa --- /dev/null +++ b/nrf5/boards/pca10040/nrf52_hal_conf.h @@ -0,0 +1,10 @@ +#ifndef NRF52_HAL_CONF_H__ +#define NRF52_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +// #define HAL_UARTE_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +// #define HAL_SPIE_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED + +#endif // NRF52_HAL_CONF_H__ diff --git a/nrf5/boards/pca10040/pins.csv b/nrf5/boards/pca10040/pins.csv new file mode 100644 index 0000000000..c177133983 --- /dev/null +++ b/nrf5/boards/pca10040/pins.csv @@ -0,0 +1,30 @@ +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA5,PA5 +PA6,PA6 +PA7,PA7 +PA8,PA8 +PA9,PA9 +PA10,PA10 +PA11,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 \ No newline at end of file diff --git a/nrf5/builtin_open.c b/nrf5/builtin_open.c new file mode 100644 index 0000000000..697eec8eaa --- /dev/null +++ b/nrf5/builtin_open.c @@ -0,0 +1,30 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "extmod/vfs_fat_file.h" + +MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, fatfs_builtin_open); diff --git a/nrf5/device/nrf52/startup_nrf52.s b/nrf5/device/nrf52/startup_nrf52.s index 1f39a39530..28906b7d9f 100644 --- a/nrf5/device/nrf52/startup_nrf52.s +++ b/nrf5/device/nrf52/startup_nrf52.s @@ -52,20 +52,36 @@ Reset_Handler: ldr r1, =_sidata ldr r2, =_sdata - ldr r3, =_edata + ldr r3, =_sbss subs r3, r2 - ble LC0 + ble CopyDone + b CopyData -LC1: - subs r3, 4 +CopyData: + subs r3, #4 ldr r0, [r1,r3] str r0, [r2,r3] - bgt LC1 + bgt CopyData + +CopyDone: + ldr r1, =_sbss + ldr r2, =_ebss + + movs r0, 0 + + subs r2, r1 + ble ZeroDone + +ZeroLoop: + subs r2, #4 + str r0, [r1, r2] + bgt ZeroLoop + +ZeroDone: -LC0: bl SystemInit - bl main + bl _start bx lr .pool diff --git a/nrf5/fatfs_port.c b/nrf5/fatfs_port.c new file mode 100644 index 0000000000..c7b15a703c --- /dev/null +++ b/nrf5/fatfs_port.c @@ -0,0 +1,46 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mphal.h" +#include "py/runtime.h" +#include "lib/fatfs/ff.h" /* FatFs lower layer API */ +#include "lib/fatfs/diskio.h" /* FatFs lower layer API */ +//#include "rtc.h" + +const PARTITION VolToPart[MICROPY_FATFS_VOLUMES] = { + {0, 1}, // Logical drive 0 ==> Physical drive 0, 1st partition + {1, 0}, // Logical drive 1 ==> Physical drive 1 (auto detection) + {2, 0}, // Logical drive 2 ==> Physical drive 2 (auto detection) + {3, 0}, // Logical drive 3 ==> Physical drive 3 (auto detection) + /* + {0, 2}, // Logical drive 2 ==> Physical drive 0, 2nd partition + {0, 3}, // Logical drive 3 ==> Physical drive 0, 3rd partition + */ +}; + +DWORD get_fattime(void) { + return ((2000 + 2016 - 1980) << 25) | ((12) << 21) | ((4) << 16) | ((00) << 11) | ((18) << 5) | (23 / 2); +} diff --git a/nrf5/gccollect.h b/nrf5/gccollect.h index be5419a56f..297a9d53ae 100644 --- a/nrf5/gccollect.h +++ b/nrf5/gccollect.h @@ -3,6 +3,7 @@ * * The MIT License (MIT) * + * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2016 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c new file mode 100644 index 0000000000..dc86a0cd52 --- /dev/null +++ b/nrf5/hal/hal_spi.c @@ -0,0 +1,122 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "mphalport.h" +#include "hal_spi.h" + +#ifdef HAL_SPI_MODULE_ENABLED + +static uint32_t m_ss_pin; + +static const uint32_t hal_spi_frequency_lookup[] = { + SPI_FREQUENCY_FREQUENCY_K125, // 125 kbps + SPI_FREQUENCY_FREQUENCY_K250, // 250 kbps + SPI_FREQUENCY_FREQUENCY_K500, // 500 kbps + SPI_FREQUENCY_FREQUENCY_M1, // 1 Mbps + SPI_FREQUENCY_FREQUENCY_M2, // 2 Mbps + SPI_FREQUENCY_FREQUENCY_M4, // 4 Mbps + SPI_FREQUENCY_FREQUENCY_M8 // 8 Mbps +}; + +void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) { + hal_gpio_pin_set(p_spi_init->enable_pin); + m_ss_pin = p_spi_init->enable_pin; + + hal_gpio_cfg_pin_output(p_spi_init->clk_pin); + hal_gpio_cfg_pin_output(p_spi_init->mosi_pin); + hal_gpio_cfg_pin_input(p_spi_init->miso_pin, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin_output(p_spi_init->enable_pin); + +#if NRF51 + p_instance->PSELSCK = p_spi_init->clk_pin; + p_instance->PSELMOSI = p_spi_init->mosi_pin; + p_instance->PSELMISO = p_spi_init->miso_pin; +#else + p_instance->PSEL.SCK = p_spi_init->clk_pin; + p_instance->PSEL.MOSI = p_spi_init->mosi_pin; + p_instance->PSEL.MISO = p_spi_init->miso_pin; +#endif + + p_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq]; + + uint32_t mode; + switch (p_spi_init->mode) { + case HAL_SPI_MODE_CPOL0_CPHA0: + mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); + break; + case HAL_SPI_MODE_CPOL0_CPHA1: + mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); + break; + case HAL_SPI_MODE_CPOL1_CPHA0: + mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos); + break; + case HAL_SPI_MODE_CPOL1_CPHA1: + mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos); + break; + default: + mode = 0; + break; + } + + if (p_spi_init->lsb_first) { + p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_LsbFirst << SPI_CONFIG_ORDER_Pos)); + } else { + p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos)); + } + + p_instance->EVENTS_READY = 0U; + p_instance->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos); +} + +void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, const uint8_t * tx_data, uint8_t * rx_data) { + + uint16_t number_of_txd_bytes = 0; + + p_instance->EVENTS_READY = 0; + + hal_gpio_pin_clear(m_ss_pin); + + while (number_of_txd_bytes < transfer_size) { + p_instance->TXD = (uint32_t)(tx_data[number_of_txd_bytes]); + + // wait for the transaction complete or timeout (about 10ms - 20 ms) + while (p_instance->EVENTS_READY == 0) { + ; + } + p_instance->EVENTS_READY = 0; + + rx_data[number_of_txd_bytes] = (uint8_t)p_instance->RXD; + number_of_txd_bytes++; + }; + + hal_gpio_pin_set(m_ss_pin); + +} + +#endif // HAL_SPI_MODULE_ENABLED diff --git a/nrf5/hal/hal_spi.h b/nrf5/hal/hal_spi.h new file mode 100644 index 0000000000..9c30c0ed4f --- /dev/null +++ b/nrf5/hal/hal_spi.h @@ -0,0 +1,105 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_SPI_H__ +#define HAL_SPI_H__ + +#include "nrf.h" + +#if NRF51 + +#define SPI0 ((NRF_SPI_Type *) NRF_SPI0) +#define SPI0_IRQ_NUM SPI0_TWI0_IRQn +#define SPI1 ((NRF_SPI_Type *) NRF_SPI1) +#define SPI1_IRQ_NUM SPI1_TWI1_IRQn + +#elif NRF52 + +#define SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) +#define SPI0_IRQ_NUM SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#define SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) +#define SPI1_IRQ_NUM SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#define SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) +#define SPI2_IRQ_NUM SPIM2_SPIS2_SPI2_IRQn + +#else +#error "Device not supported." +#endif + +/** + * @brief SPI clock frequency type definition + */ +typedef enum { + HAL_FREQ_125_Kbps = 0, + HAL_FREQ_250_Kbps, + HAL_FREQ_500_Kbps, + HAL_FREQ_1_Mbps, + HAL_FREQ_2_Mbps, + HAL_FREQ_4_Mbps, + HAL_FREQ_8_Mbps +} hal_spi_clk_freq_t; + +/** + * @brief SPI mode type definition + */ +typedef enum { + HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge) + HAL_SPI_MODE_CPOL0_CPHA1, // CPOL = 0, CPHA = 1 (data on trailing edge) + HAL_SPI_MODE_CPOL1_CPHA0, // CPOL = 1, CPHA = 0 (data on leading edge) + HAL_SPI_MODE_CPOL1_CPHA1 // CPOL = 1, CPHA = 1 (data on trailing edge) +} hal_spi_mode_t; + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct { + uint8_t mosi_pin; + uint8_t miso_pin; + uint8_t clk_pin; + uint8_t enable_pin; + bool lsb_first; + hal_spi_mode_t mode; + uint32_t irq_priority; + hal_spi_clk_freq_t freq; +} hal_spi_init_t; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + NRF_SPI_Type *instance; /* SPI registers base address */ + hal_spi_init_t init; /* SPI initialization parameters */ +} SPI_HandleTypeDef; + +void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init); + +void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, + uint16_t transfer_size, + const uint8_t * tx_data, + uint8_t * rx_data); + +#endif // HAL_SPI_H__ diff --git a/nrf5/hal/hal_spie.c b/nrf5/hal/hal_spie.c new file mode 100644 index 0000000000..6af19afa91 --- /dev/null +++ b/nrf5/hal/hal_spie.c @@ -0,0 +1,135 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "mphalport.h" +#include "hal_spi.h" + +#ifdef HAL_SPIE_MODULE_ENABLED + +#if NRF52 + +#define SPIM0 ((NRF_SPI_Type *) NRF_SPIM0_BASE) +#define SPIM0_IRQ_NUM SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#define SPIM1 ((NRF_SPI_Type *) NRF_SPIM1_BASE) +#define SPIM1_IRQ_NUM SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#define SPIM2 ((NRF_SPI_Type *) NRF_SPIM2_BASE) +#define SPIM2_IRQ_NUM SPIM2_SPIS2_SPI2_IRQn + +#else +#error "Device not supported." +#endif + +static uint32_t m_ss_pin; + +static const uint32_t hal_spi_frequency_lookup[] = { + SPI_FREQUENCY_FREQUENCY_K125, // 125 kbps + SPI_FREQUENCY_FREQUENCY_K250, // 250 kbps + SPI_FREQUENCY_FREQUENCY_K500, // 500 kbps + SPI_FREQUENCY_FREQUENCY_M1, // 1 Mbps + SPI_FREQUENCY_FREQUENCY_M2, // 2 Mbps + SPI_FREQUENCY_FREQUENCY_M4, // 4 Mbps + SPI_FREQUENCY_FREQUENCY_M8 // 8 Mbps +}; + +void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) { + // cast to master type + NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance; + + hal_gpio_pin_set(p_spi_init->enable_pin); + m_ss_pin = p_spi_init->enable_pin; + + hal_gpio_cfg_pin_output(p_spi_init->clk_pin); + hal_gpio_cfg_pin_output(p_spi_init->mosi_pin); + hal_gpio_cfg_pin_input(p_spi_init->miso_pin, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin_output(p_spi_init->enable_pin); + +#if NRF51 + spim_instance->PSELSCK = p_spi_init->clk_pin; + spim_instance->PSELMOSI = p_spi_init->mosi_pin; + spim_instance->PSELMISO = p_spi_init->miso_pin; +#else + spim_instance->PSEL.SCK = p_spi_init->clk_pin; + spim_instance->PSEL.MOSI = p_spi_init->mosi_pin; + spim_instance->PSEL.MISO = p_spi_init->miso_pin; +#endif + + spim_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq]; + + uint32_t mode; + switch (p_spi_init->mode) { + case HAL_SPI_MODE_CPOL0_CPHA0: + mode = (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos); + break; + case HAL_SPI_MODE_CPOL0_CPHA1: + mode = (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos); + break; + case HAL_SPI_MODE_CPOL1_CPHA0: + mode = (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos); + break; + case HAL_SPI_MODE_CPOL1_CPHA1: + mode = (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos); + break; + default: + mode = 0; + break; + } + + if (p_spi_init->lsb_first) { + spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_LsbFirst << SPIM_CONFIG_ORDER_Pos)); + } else { + spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos)); + } + + spim_instance->EVENTS_END = 0; + spim_instance->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos); +} + +void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, const uint8_t * tx_data, uint8_t * rx_data) { + + // cast to master type + NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance; + + hal_gpio_pin_clear(m_ss_pin); + + spim_instance->TXD.PTR = (uint32_t)(tx_data); + spim_instance->TXD.MAXCNT = transfer_size; + spim_instance->RXD.PTR = (uint32_t)(rx_data); + spim_instance->RXD.MAXCNT = transfer_size; + + spim_instance->TASKS_START = 1; + + while((0 == spim_instance->EVENTS_END)); + + spim_instance->EVENTS_END = 0; + spim_instance->TASKS_STOP = 1; + + hal_gpio_pin_set(m_ss_pin); +} + +#endif // HAL_SPIE_MODULE_ENABLED diff --git a/nrf5/hal/hal_time.c b/nrf5/hal/hal_time.c new file mode 100644 index 0000000000..d98dd4de8c --- /dev/null +++ b/nrf5/hal/hal_time.c @@ -0,0 +1,116 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "hal_time.h" + +#ifdef HAL_TIME_MODULE_ENABLED + +void mp_hal_delay_us(mp_uint_t us) +{ + register uint32_t delay __ASM ("r0") = us; + __ASM volatile ( +#ifdef NRF51 + ".syntax unified\n" +#endif + "1:\n" + " SUBS %0, %0, #1\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" +#ifdef NRF52 + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" + " NOP\n" +#endif + " BNE 1b\n" +#ifdef NRF51 + ".syntax divided\n" +#endif + : "+r" (delay)); +} + +void mp_hal_delay_ms(mp_uint_t ms) +{ + for (mp_uint_t i = 0; i < ms; i++) + { + mp_hal_delay_us(999); + } +} + +#endif // HAL_TIME_MODULE_ENABLED diff --git a/nrf5/hal/hal_time.h b/nrf5/hal/hal_time.h new file mode 100644 index 0000000000..1cef8b9521 --- /dev/null +++ b/nrf5/hal/hal_time.h @@ -0,0 +1,32 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_TIME_H__ +#define HAL_TIME_H__ + +void mp_hal_delay_ms(mp_uint_t ms); + +#endif // HAL_TIME_H__ diff --git a/nrf5/hal/hal_uart.c b/nrf5/hal/hal_uart.c index 56a6d889fd..4c4a0d99f4 100644 --- a/nrf5/hal/hal_uart.c +++ b/nrf5/hal/hal_uart.c @@ -30,6 +30,8 @@ #include "mphalport.h" #include "hal_uart.h" +#ifdef HAL_UART_MODULE_ENABLED + #ifdef NRF51 #include "nrf51.h" #include "nrf51_bitfields.h" @@ -123,3 +125,5 @@ void nrf_uart_init(hal_uart_init_t const * p_uart_init) { UART_BASE->TASKS_STARTTX = 1; UART_BASE->TASKS_STARTRX = 1; } + +#endif // HAL_UART_MODULE_ENABLED diff --git a/nrf5/hal/hal_uarte.c b/nrf5/hal/hal_uarte.c index 9e2535b22f..1990988758 100644 --- a/nrf5/hal/hal_uarte.c +++ b/nrf5/hal/hal_uarte.c @@ -29,19 +29,28 @@ #include "mphalport.h" #include "hal_uart.h" + +#ifdef HAL_UARTE_MODULE_ENABLED + #include "nrf52.h" #include "nrf52_bitfields.h" +#if NRF52 + #define UARTE_BASE ((NRF_UARTE_Type *) NRF_UARTE0_BASE) #define UART_IRQ_NUM UARTE0_UART0_IRQn +#else +#error "Device not supported." +#endif + #define TX_BUF_SIZE 1 #define RX_BUF_SIZE 1 static uart_complete_cb dma_read_cb = NULL; static uart_complete_cb dma_write_cb = NULL; -uint32_t hal_uart_baudrate_lookup[] = { +static const uint32_t hal_uart_baudrate_lookup[] = { UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud. UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud. UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud. @@ -208,13 +217,18 @@ static void dma_write_complete(void) { } void UARTE0_UART0_IRQHandler(void) { - if ((UARTE_BASE->EVENTS_ENDRX) && - (UARTE_BASE->INTEN & UARTE_INTENSET_ENDRX_Msk)) { + if ((UARTE_BASE->EVENTS_ENDRX) + && (UARTE_BASE->INTEN & UARTE_INTENSET_ENDRX_Msk)) { + UARTE_BASE->EVENTS_ENDRX = 0; dma_read_complete(); - } else if ((UARTE_BASE->EVENTS_ENDTX) && - (UARTE_BASE->INTEN & UARTE_INTENSET_ENDTX_Msk)) { + + } else if ((UARTE_BASE->EVENTS_ENDTX) + && (UARTE_BASE->INTEN & UARTE_INTENSET_ENDTX_Msk)) { + UARTE_BASE->EVENTS_ENDTX = 0; dma_write_complete(); } } + +#endif // HAL_UARTE_MODULE_ENABLED diff --git a/nrf5/hal/nrf51_hal.h b/nrf5/hal/nrf51_hal.h new file mode 100644 index 0000000000..f6975aaa8e --- /dev/null +++ b/nrf5/hal/nrf51_hal.h @@ -0,0 +1,31 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +// include config from board +#include "nrf51_hal_conf.h" diff --git a/nrf5/hal/nrf52_hal.h b/nrf5/hal/nrf52_hal.h new file mode 100644 index 0000000000..3ebd45cf97 --- /dev/null +++ b/nrf5/hal/nrf52_hal.h @@ -0,0 +1,31 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +// include config from board +#include "nrf52_hal_conf.h" diff --git a/nrf5/help.c b/nrf5/help.c index c5b47a47c0..04b0b00d34 100644 --- a/nrf5/help.c +++ b/nrf5/help.c @@ -3,6 +3,7 @@ * * The MIT License (MIT) * + * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2016 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/nrf5/led.c b/nrf5/led.c index 38dbe1b97c..a47a9de656 100644 --- a/nrf5/led.c +++ b/nrf5/led.c @@ -3,6 +3,7 @@ * * The MIT License (MIT) * + * Copyright (c) 2013-2016 Damien P. George * Copyright (c) 2015 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/nrf5/led.h b/nrf5/led.h index 7bc0d7fa9d..29139a4d48 100644 --- a/nrf5/led.h +++ b/nrf5/led.h @@ -3,6 +3,7 @@ * * The MIT License (MIT) * + * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2015 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/nrf5/lexerfatfs.c b/nrf5/lexerfatfs.c new file mode 100644 index 0000000000..fd7f62dfdd --- /dev/null +++ b/nrf5/lexerfatfs.c @@ -0,0 +1,35 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/lexer.h" + +mp_lexer_t *fat_vfs_lexer_new_from_file(const char *filename); + +// TODO: Instead of such shims, probably better to let port #define +// mp_lexer_new_from_file to a function it wants to use. +mp_lexer_t *mp_lexer_new_from_file(const char *filename) { + return fat_vfs_lexer_new_from_file(filename); +} diff --git a/nrf5/main.c b/nrf5/main.c index db55581834..290926b76f 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -3,6 +3,7 @@ * * The MIT License (MIT) * + * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2015 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -23,6 +24,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ + #include #include #include @@ -38,9 +40,17 @@ #include "lib/utils/pyexec.h" #include "readline.h" #include "gccollect.h" +#include "modmachine.h" +#include "modnetwork.h" #include "led.h" #include "uart.h" #include "nrf.h" +#include "pin.h" +#include "spi.h" + +#if (BLUETOOTH_SD == 132) +#include "nrf52_ble.h" +#endif void do_str(const char *src, mp_parse_input_kind_t input_kind) { mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0); @@ -69,11 +79,17 @@ int main(int argc, char **argv) { // Stack limit should be less than real stack size, so we have a chance // to recover from limit hit. (Limit is measured in bytes.) - mp_stack_set_limit((char*)&_ram_end - (char*)&_heap_end - 1024); + mp_stack_set_limit((char*)&_ram_end - (char*)&_heap_end - 400); led_init(); + machine_init(); gc_init(&_heap_start, &_heap_end); + +#if (BLUETOOTH_SD == 132) + nrf52_ble_init(); +#endif + mp_init(); mp_obj_list_init(mp_sys_path, 0); mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script) @@ -81,6 +97,17 @@ int main(int argc, char **argv) { readline_init0(); + pin_init0(); +#if MICROPY_PY_MACHINE_SPI + spi_init0(); +#endif + + /* + extint_init0(); + timer_init0(); + */ + +#if (BLUETOOTH_SD != 132) uart_init0(); { mp_obj_t args[2] = { @@ -89,6 +116,44 @@ int main(int argc, char **argv) { }; MP_STATE_PORT(pyb_stdio_uart) = pyb_uart_type.make_new((mp_obj_t)&pyb_uart_type, MP_ARRAY_SIZE(args), 0, args); } +#endif + +#if MICROPY_HW_HAS_SDCARD + // if an SD card is present then mount it on /sd/ + if (sdcard_is_present()) { + // create vfs object + fs_user_mount_t *vfs = m_new_obj_maybe(fs_user_mount_t); + if (vfs == NULL) { + goto no_mem_for_sd; + } + vfs->str = "/sd"; + vfs->len = 3; + vfs->flags = FSUSER_FREE_OBJ; + sdcard_init_vfs(vfs); + + // put the sd device in slot 1 (it will be unused at this point) + MP_STATE_PORT(fs_user_mount)[1] = vfs; + + FRESULT res = f_mount(&vfs->fatfs, vfs->str, 1); + if (res != FR_OK) { + printf("PYB: can't mount SD card\n"); + MP_STATE_PORT(fs_user_mount)[1] = NULL; + m_del_obj(fs_user_mount_t, vfs); + } else { + // TODO these should go before the /flash entries in the path + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_sd)); + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_sd_slash_lib)); + + // use SD card as current directory + f_chdrive("/sd"); + } + no_mem_for_sd:; + } +#endif + +#if MICROPY_PY_NETWORK + mod_network_init(); +#endif #if MICROPY_HW_LED_TRICOLOR do_str("import pyb\r\n" \ @@ -133,19 +198,10 @@ void HardFault_Handler(void) #endif } -mp_lexer_t *mp_lexer_new_from_file(const char *filename) { - return NULL; -} - mp_import_stat_t mp_import_stat(const char *path) { return MP_IMPORT_STAT_NO_EXIST; } -mp_obj_t mp_builtin_open(uint n_args, const mp_obj_t *args, mp_map_t *kwargs) { - return mp_const_none; -} -MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open); - void nlr_jump_fail(void *val) { } diff --git a/nrf5/modmachine.c b/nrf5/modmachine.c new file mode 100644 index 0000000000..a1b28cdd2d --- /dev/null +++ b/nrf5/modmachine.c @@ -0,0 +1,185 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2015 Damien P. George + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include + +#include "modmachine.h" +#include "py/gc.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "extmod/machine_mem.h" +#include "extmod/machine_pulse.h" +#include "extmod/machine_i2c.h" +#include "lib/utils/pyexec.h" +#include "lib/fatfs/ff.h" +#include "lib/fatfs/diskio.h" +#include "gccollect.h" +#include "pin.h" +#include "spi.h" + +#define PYB_RESET_HARD (0) +#define PYB_RESET_WDT (1) +#define PYB_RESET_SOFT (2) +#define PYB_RESET_LOCKUP (3) +#define PYB_RESET_POWER_ON (16) +#define PYB_RESET_LPCOMP (17) +#define PYB_RESET_DIF (18) +#define PYB_RESET_NFC (19) + +STATIC uint32_t reset_cause; + +void machine_init(void) { + uint32_t state = NRF_POWER->RESETREAS; + if (state & POWER_RESETREAS_RESETPIN_Msk) { + reset_cause = PYB_RESET_HARD; + } else if (state & POWER_RESETREAS_DOG_Msk) { + reset_cause = PYB_RESET_WDT; + } else if (state & POWER_RESETREAS_SREQ_Msk) { + reset_cause = PYB_RESET_SOFT; + } else if (state & POWER_RESETREAS_LOCKUP_Msk) { + reset_cause = PYB_RESET_LOCKUP; + } else if (state & POWER_RESETREAS_OFF_Msk) { + reset_cause = PYB_RESET_POWER_ON; + } else if (state & POWER_RESETREAS_LPCOMP_Msk) { + reset_cause = PYB_RESET_LPCOMP; + } else if (state & POWER_RESETREAS_DIF_Msk) { + reset_cause = PYB_RESET_DIF; +#if NRF52 + } else if (state & POWER_RESETREAS_NFC_Msk) { + reset_cause = PYB_RESET_NFC; +#endif + } + + // clear reset reason + NRF_POWER->RESETREAS = (1 << reset_cause); +} + +// machine.info([dump_alloc_table]) +// Print out lots of information about the board. +STATIC mp_obj_t machine_info(mp_uint_t n_args, const mp_obj_t *args) { + // to print info about memory + { + printf("_etext=%p\n", &_etext); + printf("_sidata=%p\n", &_sidata); + printf("_sdata=%p\n", &_sdata); + printf("_edata=%p\n", &_edata); + printf("_sbss=%p\n", &_sbss); + printf("_ebss=%p\n", &_ebss); + printf("_estack=%p\n", &_estack); + printf("_ram_start=%p\n", &_ram_start); + printf("_heap_start=%p\n", &_heap_start); + printf("_heap_end=%p\n", &_heap_end); + printf("_ram_end=%p\n", &_ram_end); + } + + // qstr info + { + mp_uint_t n_pool, n_qstr, n_str_data_bytes, n_total_bytes; + qstr_pool_info(&n_pool, &n_qstr, &n_str_data_bytes, &n_total_bytes); + printf("qstr:\n n_pool=" UINT_FMT "\n n_qstr=" UINT_FMT "\n n_str_data_bytes=" UINT_FMT "\n n_total_bytes=" UINT_FMT "\n", n_pool, n_qstr, n_str_data_bytes, n_total_bytes); + } + + // GC info + { + gc_info_t info; + gc_info(&info); + printf("GC:\n"); + printf(" " UINT_FMT " total\n", info.total); + printf(" " UINT_FMT " : " UINT_FMT "\n", info.used, info.free); + printf(" 1=" UINT_FMT " 2=" UINT_FMT " m=" UINT_FMT "\n", info.num_1block, info.num_2block, info.max_block); + } + + if (n_args == 1) { + // arg given means dump gc allocation table + gc_dump_alloc_table(); + } + + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_info_obj, 0, 1, machine_info); + +// Resets the pyboard in a manner similar to pushing the external RESET button. +STATIC mp_obj_t machine_reset(void) { + NVIC_SystemReset(); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_reset_obj, machine_reset); + +STATIC mp_obj_t machine_soft_reset(void) { + pyexec_system_exit = PYEXEC_FORCED_EXIT; + nlr_raise(mp_obj_new_exception(&mp_type_SystemExit)); +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_soft_reset_obj, machine_soft_reset); + +STATIC mp_obj_t machine_sleep(void) { + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_sleep_obj, machine_sleep); + +STATIC mp_obj_t machine_deepsleep(void) { + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_deepsleep_obj, machine_deepsleep); + +STATIC mp_obj_t machine_reset_cause(void) { + return MP_OBJ_NEW_SMALL_INT(reset_cause); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(machine_reset_cause_obj, machine_reset_cause); + +STATIC const mp_map_elem_t machine_module_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_umachine) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_info), (mp_obj_t)&machine_info_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_reset), (mp_obj_t)&machine_reset_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_soft_reset), (mp_obj_t)&machine_soft_reset_obj }, +#if MICROPY_HW_ENABLE_RNG + { MP_OBJ_NEW_QSTR(MP_QSTR_rng), (mp_obj_t)&pyb_rng_get_obj }, +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_sleep), (mp_obj_t)&machine_sleep_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_deepsleep), (mp_obj_t)&machine_deepsleep_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_reset_cause), (mp_obj_t)&machine_reset_cause_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Pin), (mp_obj_t)&pin_type }, +#if MICROPY_PY_MACHINE_SPI + { MP_OBJ_NEW_QSTR(MP_QSTR_SPI), (mp_obj_t)&machine_hard_spi_type }, +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_HARD_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_HARD) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_WDT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_WDT) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SOFT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_SOFT) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_LOCKUP_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_LOCKUP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PWRON_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_POWER_ON) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_LPCOMP_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_LPCOMP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_DEBUG_IF_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_DIF) }, +#if NRF52 + { MP_OBJ_NEW_QSTR(MP_QSTR_NFC_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_NFC) }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(machine_module_globals, machine_module_globals_table); + +const mp_obj_module_t machine_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&machine_module_globals, +}; + diff --git a/nrf5/modmachine.h b/nrf5/modmachine.h new file mode 100644 index 0000000000..35852ffec3 --- /dev/null +++ b/nrf5/modmachine.h @@ -0,0 +1,42 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2015 Damien P. George + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __MICROPY_INCLUDED_NRF5_MODMACHINE_H__ +#define __MICROPY_INCLUDED_NRF5_MODMACHINE_H__ + +#include "py/mpstate.h" +#include "py/nlr.h" +#include "py/obj.h" + +void machine_init(void); + +MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_info_obj); +MP_DECLARE_CONST_FUN_OBJ_0(machine_reset_obj); +MP_DECLARE_CONST_FUN_OBJ_0(machine_sleep_obj); +MP_DECLARE_CONST_FUN_OBJ_0(machine_deepsleep_obj); + +#endif // __MICROPY_INCLUDED_NRF5_MODMACHINE_H__ diff --git a/nrf5/modnetwork.c b/nrf5/modnetwork.c new file mode 100644 index 0000000000..f47df0db4e --- /dev/null +++ b/nrf5/modnetwork.c @@ -0,0 +1,97 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include + +#include "py/nlr.h" +#include "py/objlist.h" +#include "py/runtime.h" +#include "modnetwork.h" + +#if MICROPY_PY_NETWORK + +/// \module network - network configuration +/// +/// This module provides network drivers and routing configuration. + +void mod_network_init(void) { + mp_obj_list_init(&MP_STATE_PORT(mod_network_nic_list), 0); +} + +void mod_network_register_nic(mp_obj_t nic) { + for (mp_uint_t i = 0; i < MP_STATE_PORT(mod_network_nic_list).len; i++) { + if (MP_STATE_PORT(mod_network_nic_list).items[i] == nic) { + // nic already registered + return; + } + } + // nic not registered so add to list + mp_obj_list_append(&MP_STATE_PORT(mod_network_nic_list), nic); +} + +mp_obj_t mod_network_find_nic(const uint8_t *ip) { + // find a NIC that is suited to given IP address + for (mp_uint_t i = 0; i < MP_STATE_PORT(mod_network_nic_list).len; i++) { + mp_obj_t nic = MP_STATE_PORT(mod_network_nic_list).items[i]; + // TODO check IP suitability here + //mod_network_nic_type_t *nic_type = (mod_network_nic_type_t*)mp_obj_get_type(nic); + return nic; + } + + nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "no available NIC")); +} + +STATIC mp_obj_t network_route(void) { + return &MP_STATE_PORT(mod_network_nic_list); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(network_route_obj, network_route); + +STATIC const mp_map_elem_t mp_module_network_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_network) }, + + #if MICROPY_PY_WIZNET5K + { MP_OBJ_NEW_QSTR(MP_QSTR_WIZNET5K), (mp_obj_t)&mod_network_nic_type_wiznet5k }, + #endif + #if MICROPY_PY_CC3K + { MP_OBJ_NEW_QSTR(MP_QSTR_CC3K), (mp_obj_t)&mod_network_nic_type_cc3k }, + #endif + #if MICROPY_PY_BLE_6LOWPAN + { MP_OBJ_NEW_QSTR(MP_QSTR_ble_6lowpan), (mp_obj_t)&mod_network_nic_type_ble_6lowpan }, + #endif + + { MP_OBJ_NEW_QSTR(MP_QSTR_route), (mp_obj_t)&network_route_obj }, +}; + +STATIC MP_DEFINE_CONST_DICT(mp_module_network_globals, mp_module_network_globals_table); + +const mp_obj_module_t mp_module_network = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&mp_module_network_globals, +}; + +#endif // MICROPY_PY_NETWORK diff --git a/nrf5/modnetwork.h b/nrf5/modnetwork.h new file mode 100644 index 0000000000..73f8b628fc --- /dev/null +++ b/nrf5/modnetwork.h @@ -0,0 +1,81 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define MOD_NETWORK_IPADDR_BUF_SIZE (16) + +#define MOD_NETWORK_AF_INET (2) +#define MOD_NETWORK_AF_INET6 (10) + +#define MOD_NETWORK_SOCK_STREAM (1) +#define MOD_NETWORK_SOCK_DGRAM (2) +#define MOD_NETWORK_SOCK_RAW (3) + +struct _mod_network_socket_obj_t; + +typedef struct _mod_network_nic_type_t { + mp_obj_type_t base; + + // API for non-socket operations + int (*gethostbyname)(mp_obj_t nic, const char *name, mp_uint_t len, uint8_t *ip_out); + + // API for socket operations; return -1 on error + int (*socket)(struct _mod_network_socket_obj_t *socket, int *_errno); + void (*close)(struct _mod_network_socket_obj_t *socket); + int (*bind)(struct _mod_network_socket_obj_t *socket, byte *ip, mp_uint_t port, int *_errno); + int (*listen)(struct _mod_network_socket_obj_t *socket, mp_int_t backlog, int *_errno); + int (*accept)(struct _mod_network_socket_obj_t *socket, struct _mod_network_socket_obj_t *socket2, byte *ip, mp_uint_t *port, int *_errno); + int (*connect)(struct _mod_network_socket_obj_t *socket, byte *ip, mp_uint_t port, int *_errno); + mp_uint_t (*send)(struct _mod_network_socket_obj_t *socket, const byte *buf, mp_uint_t len, int *_errno); + mp_uint_t (*recv)(struct _mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, int *_errno); + mp_uint_t (*sendto)(struct _mod_network_socket_obj_t *socket, const byte *buf, mp_uint_t len, byte *ip, mp_uint_t port, int *_errno); + mp_uint_t (*recvfrom)(struct _mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, byte *ip, mp_uint_t *port, int *_errno); + int (*setsockopt)(struct _mod_network_socket_obj_t *socket, mp_uint_t level, mp_uint_t opt, const void *optval, mp_uint_t optlen, int *_errno); + int (*settimeout)(struct _mod_network_socket_obj_t *socket, mp_uint_t timeout_ms, int *_errno); + int (*ioctl)(struct _mod_network_socket_obj_t *socket, mp_uint_t request, mp_uint_t arg, int *_errno); +} mod_network_nic_type_t; + +typedef struct _mod_network_socket_obj_t { + mp_obj_base_t base; + mp_obj_t nic; + mod_network_nic_type_t *nic_type; + union { + struct { + uint8_t domain; + uint8_t type; + int8_t fileno; + } u_param; + mp_uint_t u_state; + }; + struct udp_pcb * p_socket; +} mod_network_socket_obj_t; + +extern const mod_network_nic_type_t mod_network_nic_type_wiznet5k; +extern const mod_network_nic_type_t mod_network_nic_type_cc3k; +extern const mod_network_nic_type_t mod_network_nic_type_ble_6lowpan; + +void mod_network_init(void); +void mod_network_register_nic(mp_obj_t nic); +mp_obj_t mod_network_find_nic(const uint8_t *ip); diff --git a/nrf5/modpyb.c b/nrf5/modpyb.c index d7b2e24b2d..b436c2468c 100644 --- a/nrf5/modpyb.c +++ b/nrf5/modpyb.c @@ -30,12 +30,15 @@ #include "py/obj.h" #include "uart.h" #include "led.h" +#include "nrf.h" // TODO: figure out where to put this import +#include "pin.h" STATIC const mp_map_elem_t pyb_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_pyb) }, { MP_OBJ_NEW_QSTR(MP_QSTR_LED), (mp_obj_t)&pyb_led_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_repl_info), (mp_obj_t)&pyb_set_repl_info_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&pyb_uart_type } + { MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&pyb_uart_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Pin), (mp_obj_t)&pin_type }, /* { MP_OBJ_NEW_QSTR(MP_QSTR_main), (mp_obj_t)&pyb_main_obj }*/ }; diff --git a/nrf5/modules/mountsd.py b/nrf5/modules/mountsd.py new file mode 100644 index 0000000000..2b4ac26362 --- /dev/null +++ b/nrf5/modules/mountsd.py @@ -0,0 +1,9 @@ +import os +from machine import SPI +from pyb import Pin +from sdcard import SDCard + +def mount_sd(): + sd = SDCard(SPI(0), Pin("A22")) + os.mount(sd, '/') + diff --git a/nrf5/modules/sdcard.py b/nrf5/modules/sdcard.py new file mode 100644 index 0000000000..4fdb3bd045 --- /dev/null +++ b/nrf5/modules/sdcard.py @@ -0,0 +1,278 @@ +""" +Micro Python driver for SD cards using SPI bus. + +Requires an SPI bus and a CS pin. Provides readblocks and writeblocks +methods so the device can be mounted as a filesystem. + +Example usage on pyboard: + + import pyb, sdcard, os + sd = sdcard.SDCard(pyb.SPI(1), pyb.Pin.board.X5) + pyb.mount(sd, '/sd2') + os.listdir('/') + +Example usage on ESP8266: + + import machine, sdcard, os + sd = sdcard.SDCard(machine.SPI(0), machine.Pin(15)) + os.umount() + os.VfsFat(sd, "") + os.listdir() + +Example usage on NRF52832: + + import machine, pyb, os + sd = sdcard.SDCard(machine.SPI(0), machine.PIN("A22")) + os.mount(sd, "") + os.listdir() + +""" + +import time + + +_CMD_TIMEOUT = const(100) + +_R1_IDLE_STATE = const(1 << 0) +#R1_ERASE_RESET = const(1 << 1) +_R1_ILLEGAL_COMMAND = const(1 << 2) +#R1_COM_CRC_ERROR = const(1 << 3) +#R1_ERASE_SEQUENCE_ERROR = const(1 << 4) +#R1_ADDRESS_ERROR = const(1 << 5) +#R1_PARAMETER_ERROR = const(1 << 6) +_TOKEN_CMD25 = const(0xfc) +_TOKEN_STOP_TRAN = const(0xfd) +_TOKEN_DATA = const(0xfe) + + +class SDCard: + def __init__(self, spi, cs): + self.spi = spi + self.cs = cs + + self.cmdbuf = bytearray(6) + self.dummybuf = bytearray(512) + for i in range(512): + self.dummybuf[i] = 0xff + self.dummybuf_memoryview = memoryview(self.dummybuf) + + # initialise the card + self.init_card() + + def init_spi(self, baudrate): + try: + master = self.spi.MASTER + except AttributeError: + # on ESP8266 + self.spi.init(baudrate=baudrate, phase=0, polarity=0) + else: + # on pyboard + self.spi.init(master, baudrate=baudrate, phase=0, polarity=0) + + def init_card(self): + # init CS pin + #self.cs.init(self.cs.OUT, value=1) + + # init SPI bus; use low data rate for initialisation + self.init_spi(100000) + + # clock card at least 100 cycles with cs high + for i in range(16): + self.spi.write(b'\xff') + + # CMD0: init card; should return _R1_IDLE_STATE (allow 5 attempts) + for _ in range(5): + if self.cmd(0, 0, 0x95) == _R1_IDLE_STATE: + break + else: + raise OSError("no SD card") + + # CMD8: determine card version + r = self.cmd(8, 0x01aa, 0x87, 4) + if r == _R1_IDLE_STATE: + self.init_card_v2() + elif r == (_R1_IDLE_STATE | _R1_ILLEGAL_COMMAND): + self.init_card_v1() + else: + raise OSError("couldn't determine SD card version") + + # get the number of sectors + # CMD9: response R2 (R1 byte + 16-byte block read) + if self.cmd(9, 0, 0, 0, False) != 0: + raise OSError("no response from SD card") + csd = bytearray(16) + self.readinto(csd) + if csd[0] & 0xc0 != 0x40: + raise OSError("SD card CSD format not supported") + self.sectors = ((csd[8] << 8 | csd[9]) + 1) * 2014 + #print('sectors', self.sectors) + + # CMD16: set block length to 512 bytes + if self.cmd(16, 512, 0) != 0: + raise OSError("can't set 512 block size") + + # set to high data rate now that it's initialised + self.init_spi(1320000) + + def init_card_v1(self): + for i in range(_CMD_TIMEOUT): + self.cmd(55, 0, 0) + if self.cmd(41, 0, 0) == 0: + self.cdv = 512 + #print("[SDCard] v1 card") + return + raise OSError("timeout waiting for v1 card") + + def init_card_v2(self): + for i in range(_CMD_TIMEOUT): + time.sleep_ms(50) + self.cmd(58, 0, 0, 4) + self.cmd(55, 0, 0) + if self.cmd(41, 0x40000000, 0) == 0: + self.cmd(58, 0, 0, 4) + self.cdv = 1 + #print("[SDCard] v2 card") + return + raise OSError("timeout waiting for v2 card") + + def cmd(self, cmd, arg, crc, final=0, release=True): + self.cs.low() + + # create and send the command + buf = self.cmdbuf + buf[0] = 0x40 | cmd + buf[1] = arg >> 24 + buf[2] = arg >> 16 + buf[3] = arg >> 8 + buf[4] = arg + buf[5] = crc + self.spi.write(buf) + + # wait for the repsonse (response[7] == 0) + for i in range(_CMD_TIMEOUT): + response = self.spi.read(1, 0xff)[0] + if not (response & 0x80): + # this could be a big-endian integer that we are getting here + for j in range(final): + self.spi.write(b'\xff') + if release: + self.cs.high() + self.spi.write(b'\xff') + return response + + # timeout + self.cs.high() + self.spi.write(b'\xff') + return -1 + + def cmd_nodata(self, cmd): + self.spi.write(cmd) + self.spi.read(1, 0xff) # ignore stuff byte + for _ in range(_CMD_TIMEOUT): + if self.spi.read(1, 0xff)[0] == 0xff: + self.cs.high() + self.spi.write(b'\xff') + return 0 # OK + self.cs.high() + self.spi.write(b'\xff') + return 1 # timeout + + def readinto(self, buf): + self.cs.low() + + # read until start byte (0xff) + while self.spi.read(1, 0xff)[0] != 0xfe: + pass + + # read data + mv = self.dummybuf_memoryview[:len(buf)] + self.spi.write_readinto(mv, buf) + + # read checksum + self.spi.write(b'\xff') + self.spi.write(b'\xff') + + self.cs.high() + self.spi.write(b'\xff') + + def write(self, token, buf): + self.cs.low() + + # send: start of block, data, checksum + self.spi.read(1, token) + self.spi.write(buf) + self.spi.write(b'\xff') + self.spi.write(b'\xff') + + # check the response + if (self.spi.read(1, 0xff)[0] & 0x1f) != 0x05: + self.cs.high() + self.spi.write(b'\xff') + return + + # wait for write to finish + while self.spi.read(1, 0xff)[0] == 0: + pass + + self.cs.high() + self.spi.write(b'\xff') + + def write_token(self, token): + self.cs.low() + self.spi.read(1, token) + self.spi.write(b'\xff') + # wait for write to finish + while self.spi.read(1, 0xff)[0] == 0x00: + pass + + self.cs.high() + self.spi.write(b'\xff') + + def count(self): + return self.sectors + + def readblocks(self, block_num, buf): + nblocks, err = divmod(len(buf), 512) + assert nblocks and not err, 'Buffer length is invalid' + if nblocks == 1: + # CMD17: set read address for single block + if self.cmd(17, block_num * self.cdv, 0) != 0: + return 1 + # receive the data + self.readinto(buf) + else: + # CMD18: set read address for multiple blocks + if self.cmd(18, block_num * self.cdv, 0) != 0: + return 1 + offset = 0 + mv = memoryview(buf) + while nblocks: + self.readinto(mv[offset : offset + 512]) + offset += 512 + nblocks -= 1 + return self.cmd_nodata(b'\x0c') # cmd 12 + return 0 + + def writeblocks(self, block_num, buf): + nblocks, err = divmod(len(buf), 512) + assert nblocks and not err, 'Buffer length is invalid' + if nblocks == 1: + # CMD24: set write address for single block + if self.cmd(24, block_num * self.cdv, 0) != 0: + return 1 + + # send the data + self.write(_TOKEN_DATA, buf) + else: + # CMD25: set write address for first block + if self.cmd(25, block_num * self.cdv, 0) != 0: + return 1 + # send the data + offset = 0 + mv = memoryview(buf) + while nblocks: + self.write(_TOKEN_CMD25, mv[offset : offset + 512]) + offset += 512 + nblocks -= 1 + self.write_token(_TOKEN_STOP_TRAN) + return 0 diff --git a/nrf5/moduos.c b/nrf5/moduos.c new file mode 100644 index 0000000000..e3bf4c1ae1 --- /dev/null +++ b/nrf5/moduos.c @@ -0,0 +1,411 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/mpstate.h" +#include "py/runtime.h" +#include "py/objtuple.h" +#include "py/objstr.h" +#include "genhdr/mpversion.h" +#include "lib/fatfs/ff.h" +#include "lib/fatfs/diskio.h" +#include "lib/timeutils/timeutils.h" +//#include "rng.h" +#include "uart.h" +#include "extmod/vfs_fat_file.h" +//#include "sdcard.h" +#include "extmod/fsusermount.h" +//#include "portmodules.h" + +/// \module os - basic "operating system" services +/// +/// The `os` module contains functions for filesystem access and `urandom`. +/// +/// The filesystem has `/` as the root directory, and the available physical +/// drives are accessible from here. They are currently: +/// +/// /flash -- the internal flash filesystem +/// /sd -- the SD card (if it exists) +/// +/// On boot up, the current directory is `/flash` if no SD card is inserted, +/// otherwise it is `/sd`. + +STATIC const qstr os_uname_info_fields[] = { + MP_QSTR_sysname, MP_QSTR_nodename, + MP_QSTR_release, MP_QSTR_version, MP_QSTR_machine +}; +STATIC const MP_DEFINE_STR_OBJ(os_uname_info_sysname_obj, "pyboard"); +STATIC const MP_DEFINE_STR_OBJ(os_uname_info_nodename_obj, "pyboard"); +STATIC const MP_DEFINE_STR_OBJ(os_uname_info_release_obj, MICROPY_VERSION_STRING); +STATIC const MP_DEFINE_STR_OBJ(os_uname_info_version_obj, MICROPY_GIT_TAG " on " MICROPY_BUILD_DATE); +STATIC const MP_DEFINE_STR_OBJ(os_uname_info_machine_obj, MICROPY_HW_BOARD_NAME " with " MICROPY_HW_MCU_NAME); +STATIC MP_DEFINE_ATTRTUPLE( + os_uname_info_obj, + os_uname_info_fields, + 5, + (mp_obj_t)&os_uname_info_sysname_obj, + (mp_obj_t)&os_uname_info_nodename_obj, + (mp_obj_t)&os_uname_info_release_obj, + (mp_obj_t)&os_uname_info_version_obj, + (mp_obj_t)&os_uname_info_machine_obj +); + +STATIC mp_obj_t os_uname(void) { + return (mp_obj_t)&os_uname_info_obj; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(os_uname_obj, os_uname); + +/// \function chdir(path) +/// Change current directory. +STATIC mp_obj_t os_chdir(mp_obj_t path_in) { + const char *path; + path = mp_obj_str_get_str(path_in); + + FRESULT res = f_chdrive(path); + + if (res == FR_OK) { + res = f_chdir(path); + } + + if (res != FR_OK) { + // TODO should be mp_type_FileNotFoundError + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "No such file or directory: '%s'", path)); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_chdir_obj, os_chdir); + +/// \function getcwd() +/// Get the current directory. +STATIC mp_obj_t os_getcwd(void) { + char buf[MICROPY_ALLOC_PATH_MAX + 1]; + FRESULT res = f_getcwd(buf, sizeof buf); + + if (res != FR_OK) { + mp_raise_OSError(fresult_to_errno_table[res]); + } + + return mp_obj_new_str(buf, strlen(buf), false); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(os_getcwd_obj, os_getcwd); + +/// \function listdir([dir]) +/// With no argument, list the current directory. Otherwise list the given directory. +STATIC mp_obj_t os_listdir(mp_uint_t n_args, const mp_obj_t *args) { + bool is_str_type = true; + const char *path; + if (n_args == 1) { + if (mp_obj_get_type(args[0]) == &mp_type_bytes) { + is_str_type = false; + } + path = mp_obj_str_get_str(args[0]); + } else { + path = ""; + } + + // "hack" to list root directory + if (path[0] == '/' && path[1] == '\0') { + mp_obj_t dir_list = mp_obj_new_list(0, NULL); + for (size_t i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(fs_user_mount)); ++i) { + fs_user_mount_t *vfs = MP_STATE_PORT(fs_user_mount)[i]; + if (vfs != NULL) { + mp_obj_list_append(dir_list, mp_obj_new_str(vfs->str + 1, vfs->len - 1, false)); + } + } + return dir_list; + } + + return fat_vfs_listdir(path, is_str_type); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(os_listdir_obj, 0, 1, os_listdir); + +/// \function mkdir(path) +/// Create a new directory. +STATIC mp_obj_t os_mkdir(mp_obj_t path_o) { + const char *path = mp_obj_str_get_str(path_o); + FRESULT res = f_mkdir(path); + switch (res) { + case FR_OK: + return mp_const_none; + case FR_EXIST: + // TODO should be FileExistsError + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "File exists: '%s'", path)); + default: + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error creating directory '%s'", path)); + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_mkdir_obj, os_mkdir); + +/// \function remove(path) +/// Remove a file. +STATIC mp_obj_t os_remove(mp_obj_t path_o) { + const char *path = mp_obj_str_get_str(path_o); + // TODO check that path is actually a file before trying to unlink it + FRESULT res = f_unlink(path); + switch (res) { + case FR_OK: + return mp_const_none; + default: + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error removing file '%s'", path)); + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_remove_obj, os_remove); + +/// \function rename(old_path, new_path) +/// Rename a file +STATIC mp_obj_t os_rename(mp_obj_t path_in, mp_obj_t path_out) { + const char *old_path = mp_obj_str_get_str(path_in); + const char *new_path = mp_obj_str_get_str(path_out); + FRESULT res = f_rename(old_path, new_path); + switch (res) { + case FR_OK: + return mp_const_none; + default: + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error renaming file '%s' to '%s'", old_path, new_path)); + } + +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(os_rename_obj, os_rename); + +/// \function rmdir(path) +/// Remove a directory. +STATIC mp_obj_t os_rmdir(mp_obj_t path_o) { + const char *path = mp_obj_str_get_str(path_o); + // TODO check that path is actually a directory before trying to unlink it + FRESULT res = f_unlink(path); + switch (res) { + case FR_OK: + return mp_const_none; + default: + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error removing directory '%s'", path)); + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_rmdir_obj, os_rmdir); + +// Checks for path equality, ignoring trailing slashes: +// path_equal(/, /) -> true +// path_equal(/flash//, /flash) -> true +// second argument must be in canonical form (meaning no trailing slash, unless it's just /) +STATIC bool path_equal(const char *path, const char *path_canonical) { + for (; *path_canonical != '\0' && *path == *path_canonical; ++path, ++path_canonical) { + } + if (*path_canonical != '\0') { + return false; + } + for (; *path == '/'; ++path) { + } + return *path == '\0'; +} + +/// \function stat(path) +/// Get the status of a file or directory. +STATIC mp_obj_t os_stat(mp_obj_t path_in) { + const char *path = mp_obj_str_get_str(path_in); + + FILINFO fno; +#if _USE_LFN + fno.lfname = NULL; + fno.lfsize = 0; +#endif + + FRESULT res; + if (path_equal(path, "/")) { + // stat root directory + fno.fsize = 0; + fno.fdate = 0; + fno.ftime = 0; + fno.fattrib = AM_DIR; + } else { + res = FR_NO_PATH; + for (size_t i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(fs_user_mount)); ++i) { + fs_user_mount_t *vfs = MP_STATE_PORT(fs_user_mount)[i]; + if (vfs != NULL && path_equal(path, vfs->str)) { + // stat mounted device directory + fno.fsize = 0; + fno.fdate = 0; + fno.ftime = 0; + fno.fattrib = AM_DIR; + res = FR_OK; + } + } + if (res == FR_NO_PATH) { + // stat normal file + res = f_stat(path, &fno); + } + if (res != FR_OK) { + mp_raise_OSError(fresult_to_errno_table[res]); + } + } + + mp_obj_tuple_t *t = mp_obj_new_tuple(10, NULL); + mp_int_t mode = 0; + if (fno.fattrib & AM_DIR) { + mode |= 0x4000; // stat.S_IFDIR + } else { + mode |= 0x8000; // stat.S_IFREG + } + mp_int_t seconds = timeutils_seconds_since_2000( + 1980 + ((fno.fdate >> 9) & 0x7f), + (fno.fdate >> 5) & 0x0f, + fno.fdate & 0x1f, + (fno.ftime >> 11) & 0x1f, + (fno.ftime >> 5) & 0x3f, + 2 * (fno.ftime & 0x1f) + ); + t->items[0] = MP_OBJ_NEW_SMALL_INT(mode); // st_mode + t->items[1] = MP_OBJ_NEW_SMALL_INT(0); // st_ino + t->items[2] = MP_OBJ_NEW_SMALL_INT(0); // st_dev + t->items[3] = MP_OBJ_NEW_SMALL_INT(0); // st_nlink + t->items[4] = MP_OBJ_NEW_SMALL_INT(0); // st_uid + t->items[5] = MP_OBJ_NEW_SMALL_INT(0); // st_gid + t->items[6] = MP_OBJ_NEW_SMALL_INT(fno.fsize); // st_size + t->items[7] = MP_OBJ_NEW_SMALL_INT(seconds); // st_atime + t->items[8] = MP_OBJ_NEW_SMALL_INT(seconds); // st_mtime + t->items[9] = MP_OBJ_NEW_SMALL_INT(seconds); // st_ctime + + return t; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_stat_obj, os_stat); + +STATIC mp_obj_t os_statvfs(mp_obj_t path_in) { + const char *path = mp_obj_str_get_str(path_in); + + DWORD nclst; + FATFS *fatfs; + FRESULT res = f_getfree(path, &nclst, &fatfs); + if (res != FR_OK) { + goto error; + } + + mp_obj_tuple_t *t = mp_obj_new_tuple(10, NULL); + + t->items[0] = MP_OBJ_NEW_SMALL_INT(fatfs->csize * 512); // f_bsize - block size + t->items[1] = t->items[0]; // f_frsize - fragment size + t->items[2] = MP_OBJ_NEW_SMALL_INT((fatfs->n_fatent - 2) * fatfs->csize); // f_blocks - total number of blocks + t->items[3] = MP_OBJ_NEW_SMALL_INT(nclst); // f_bfree - number of free blocks + t->items[4] = t->items[3]; // f_bavail - free blocks avail to unpriviledged users + t->items[5] = MP_OBJ_NEW_SMALL_INT(0); // f_files - # inodes + t->items[6] = MP_OBJ_NEW_SMALL_INT(0); // f_ffree - # free inodes + t->items[7] = MP_OBJ_NEW_SMALL_INT(0); // f_favail - # free inodes avail to unpriviledges users + t->items[8] = MP_OBJ_NEW_SMALL_INT(0); // f_flags + t->items[9] = MP_OBJ_NEW_SMALL_INT(_MAX_LFN); // f_namemax + + return t; + +error: + mp_raise_OSError(fresult_to_errno_table[res]); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_statvfs_obj, os_statvfs); + +/// \function sync() +/// Sync all filesystems. +STATIC mp_obj_t os_sync(void) { + disk_ioctl(0, CTRL_SYNC, NULL); + disk_ioctl(1, CTRL_SYNC, NULL); + disk_ioctl(2, CTRL_SYNC, NULL); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(mod_os_sync_obj, os_sync); + +#if MICROPY_HW_ENABLE_RNG +/// \function urandom(n) +/// Return a bytes object with n random bytes, generated by the hardware +/// random number generator. +STATIC mp_obj_t os_urandom(mp_obj_t num) { + mp_int_t n = mp_obj_get_int(num); + vstr_t vstr; + vstr_init_len(&vstr, n); + for (int i = 0; i < n; i++) { + vstr.buf[i] = rng_get(); + } + return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_urandom_obj, os_urandom); +#endif + +// Get or set the UART object that the REPL is repeated on. +// TODO should accept any object with read/write methods. +STATIC mp_obj_t os_dupterm(mp_uint_t n_args, const mp_obj_t *args) { + if (n_args == 0) { + if (MP_STATE_PORT(pyb_stdio_uart) == NULL) { + return mp_const_none; + } else { + return MP_STATE_PORT(pyb_stdio_uart); + } + } else { + if (args[0] == mp_const_none) { + MP_STATE_PORT(pyb_stdio_uart) = NULL; + } else if (mp_obj_get_type(args[0]) == &pyb_uart_type) { + MP_STATE_PORT(pyb_stdio_uart) = args[0]; + } else { + nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "need a UART object")); + } + return mp_const_none; + } +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mod_os_dupterm_obj, 0, 1, os_dupterm); + +STATIC const mp_map_elem_t os_module_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_uos) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_uname), (mp_obj_t)&os_uname_obj }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_chdir), (mp_obj_t)&os_chdir_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getcwd), (mp_obj_t)&os_getcwd_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_listdir), (mp_obj_t)&os_listdir_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_mkdir), (mp_obj_t)&os_mkdir_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_remove), (mp_obj_t)&os_remove_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_rename),(mp_obj_t)&os_rename_obj}, + { MP_OBJ_NEW_QSTR(MP_QSTR_rmdir), (mp_obj_t)&os_rmdir_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_stat), (mp_obj_t)&os_stat_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_statvfs), (mp_obj_t)&os_statvfs_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_unlink), (mp_obj_t)&os_remove_obj }, // unlink aliases to remove + + { MP_OBJ_NEW_QSTR(MP_QSTR_sync), (mp_obj_t)&mod_os_sync_obj }, + + /// \constant sep - separation character used in paths + { MP_OBJ_NEW_QSTR(MP_QSTR_sep), MP_OBJ_NEW_QSTR(MP_QSTR__slash_) }, + +#if MICROPY_HW_ENABLE_RNG + { MP_OBJ_NEW_QSTR(MP_QSTR_urandom), (mp_obj_t)&os_urandom_obj }, +#endif + + // these are MicroPython extensions + { MP_OBJ_NEW_QSTR(MP_QSTR_dupterm), (mp_obj_t)&mod_os_dupterm_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_mount), (mp_obj_t)&fsuser_mount_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_umount), (mp_obj_t)&fsuser_umount_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_mkfs), (mp_obj_t)&fsuser_mkfs_obj }, +}; + +STATIC MP_DEFINE_CONST_DICT(os_module_globals, os_module_globals_table); + +const mp_obj_module_t mp_module_uos = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&os_module_globals, +}; diff --git a/nrf5/modusocket.c b/nrf5/modusocket.c new file mode 100644 index 0000000000..4c49788793 --- /dev/null +++ b/nrf5/modusocket.c @@ -0,0 +1,480 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/nlr.h" +#include "py/objtuple.h" +#include "py/objlist.h" +#include "py/runtime.h" +#include "py/mperrno.h" +#include "netutils.h" +#include "modnetwork.h" + +#if MICROPY_PY_USOCKET + +/******************************************************************************/ +// socket class + +STATIC const mp_obj_type_t socket_type; + +// constructor socket(family=AF_INET, type=SOCK_STREAM, proto=0, fileno=None) +STATIC mp_obj_t socket_make_new(const mp_obj_type_t *type, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 0, 4, false); + + // create socket object (not bound to any NIC yet) + mod_network_socket_obj_t *s = m_new_obj_with_finaliser(mod_network_socket_obj_t); + s->base.type = (mp_obj_t)&socket_type; + s->nic = MP_OBJ_NULL; + s->nic_type = NULL; + s->u_param.domain = MOD_NETWORK_AF_INET; + s->u_param.type = MOD_NETWORK_SOCK_STREAM; + s->u_param.fileno = -1; + if (n_args >= 1) { + s->u_param.domain = mp_obj_get_int(args[0]); + if (n_args >= 2) { + s->u_param.type = mp_obj_get_int(args[1]); + if (n_args >= 4) { + s->u_param.fileno = mp_obj_get_int(args[3]); + } + } + } + + return s; +} + +STATIC void socket_select_nic(mod_network_socket_obj_t *self, const byte *ip) { + if (self->nic == MP_OBJ_NULL) { + // select NIC based on IP + self->nic = mod_network_find_nic(ip); + self->nic_type = (mod_network_nic_type_t*)mp_obj_get_type(self->nic); + + // call the NIC to open the socket + int _errno; + if (self->nic_type->socket(self, &_errno) != 0) { + mp_raise_OSError(_errno); + } + } +} +// method socket.close() +STATIC mp_obj_t socket_close(mp_obj_t self_in) { + mod_network_socket_obj_t *self = self_in; + if (self->nic != MP_OBJ_NULL) { + self->nic_type->close(self); + self->nic = MP_OBJ_NULL; + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(socket_close_obj, socket_close); + +#include + +// method socket.bind(address) +STATIC mp_obj_t socket_bind(mp_obj_t self_in, mp_obj_t addr_in) { + mod_network_socket_obj_t *self = self_in; + + // get address + uint8_t ip[MOD_NETWORK_IPADDR_BUF_SIZE]; + + mp_uint_t port; + if (self->u_param.domain == MOD_NETWORK_AF_INET) { + port = netutils_parse_inet_addr(addr_in, ip, NETUTILS_BIG); + } else { + port = netutils_parse_inet6_addr(addr_in, ip, NETUTILS_BIG); + } + + // check if we need to select a NIC + socket_select_nic(self, ip); + + // call the NIC to bind the socket + int _errno; + if (self->nic_type->bind(self, ip, port, &_errno) != 0) { + mp_raise_OSError(_errno); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_bind_obj, socket_bind); + +// method socket.listen(backlog) +STATIC mp_obj_t socket_listen(mp_obj_t self_in, mp_obj_t backlog) { + mod_network_socket_obj_t *self = self_in; + + if (self->nic == MP_OBJ_NULL) { + // not connected + // TODO I think we can listen even if not bound... + mp_raise_OSError(MP_ENOTCONN); + } + + int _errno; + if (self->nic_type->listen(self, mp_obj_get_int(backlog), &_errno) != 0) { + mp_raise_OSError(_errno); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_listen_obj, socket_listen); + +// method socket.accept() +STATIC mp_obj_t socket_accept(mp_obj_t self_in) { + mod_network_socket_obj_t *self = self_in; + + // create new socket object + // starts with empty NIC so that finaliser doesn't run close() method if accept() fails + mod_network_socket_obj_t *socket2 = m_new_obj_with_finaliser(mod_network_socket_obj_t); + socket2->base.type = (mp_obj_t)&socket_type; + socket2->nic = MP_OBJ_NULL; + socket2->nic_type = NULL; + + // accept incoming connection + uint8_t ip[MOD_NETWORK_IPADDR_BUF_SIZE]; + mp_uint_t port; + int _errno; + if (self->nic_type->accept(self, socket2, ip, &port, &_errno) != 0) { + mp_raise_OSError(_errno); + } + + // new socket has valid state, so set the NIC to the same as parent + socket2->nic = self->nic; + socket2->nic_type = self->nic_type; + + // make the return value + mp_obj_tuple_t *client = mp_obj_new_tuple(2, NULL); + client->items[0] = socket2; + + if (self->u_param.domain == MOD_NETWORK_AF_INET) { + client->items[1] = netutils_format_inet_addr(ip, port, NETUTILS_BIG); + } else { + client->items[1] = netutils_format_inet6_addr(ip, port, NETUTILS_BIG); + } + + return client; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(socket_accept_obj, socket_accept); + +// method socket.connect(address) +STATIC mp_obj_t socket_connect(mp_obj_t self_in, mp_obj_t addr_in) { + mod_network_socket_obj_t *self = self_in; + + // get address + uint8_t ip[MOD_NETWORK_IPADDR_BUF_SIZE]; + + mp_uint_t port; + if (self->u_param.domain == MOD_NETWORK_AF_INET) { + port = netutils_parse_inet_addr(addr_in, ip, NETUTILS_BIG); + } else { + port = netutils_parse_inet6_addr(addr_in, ip, NETUTILS_BIG); + } + // check if we need to select a NIC + socket_select_nic(self, ip); + + // call the NIC to connect the socket + int _errno; + if (self->nic_type->connect(self, ip, port, &_errno) != 0) { + mp_raise_OSError(_errno); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_connect_obj, socket_connect); + +// method socket.send(bytes) +STATIC mp_obj_t socket_send(mp_obj_t self_in, mp_obj_t buf_in) { + mod_network_socket_obj_t *self = self_in; + if (self->nic == MP_OBJ_NULL) { + // not connected + mp_raise_OSError(MP_EPIPE); + } + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(buf_in, &bufinfo, MP_BUFFER_READ); + int _errno; + mp_uint_t ret = self->nic_type->send(self, bufinfo.buf, bufinfo.len, &_errno); + if (ret == -1) { + mp_raise_OSError(_errno); + } + return mp_obj_new_int_from_uint(ret); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_send_obj, socket_send); + +// method socket.recv(bufsize) +STATIC mp_obj_t socket_recv(mp_obj_t self_in, mp_obj_t len_in) { + mod_network_socket_obj_t *self = self_in; + if (self->nic == MP_OBJ_NULL) { + // not connected + mp_raise_OSError(MP_ENOTCONN); + } + mp_int_t len = mp_obj_get_int(len_in); + vstr_t vstr; + vstr_init_len(&vstr, len); + int _errno; + mp_uint_t ret = self->nic_type->recv(self, (byte*)vstr.buf, len, &_errno); + if (ret == -1) { + mp_raise_OSError(_errno); + } + if (ret == 0) { + return mp_const_empty_bytes; + } + vstr.len = ret; + return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_recv_obj, socket_recv); + +// method socket.sendto(bytes, address) +STATIC mp_obj_t socket_sendto(mp_obj_t self_in, mp_obj_t data_in, mp_obj_t addr_in) { + mod_network_socket_obj_t *self = self_in; + + // get the data + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(data_in, &bufinfo, MP_BUFFER_READ); + + // get address + uint8_t ip[MOD_NETWORK_IPADDR_BUF_SIZE]; + mp_uint_t port; + if (self->u_param.domain == MOD_NETWORK_AF_INET) { + port = netutils_parse_inet_addr(addr_in, ip, NETUTILS_BIG); + } else { + port = netutils_parse_inet6_addr(addr_in, ip, NETUTILS_BIG); + } + + // check if we need to select a NIC + socket_select_nic(self, ip); + + // call the NIC to sendto + int _errno; + mp_int_t ret = self->nic_type->sendto(self, bufinfo.buf, bufinfo.len, ip, port, &_errno); + if (ret == -1) { + mp_raise_OSError(_errno); + } + + return mp_obj_new_int(ret); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_3(socket_sendto_obj, socket_sendto); + +// method socket.recvfrom(bufsize) +STATIC mp_obj_t socket_recvfrom(mp_obj_t self_in, mp_obj_t len_in) { + mod_network_socket_obj_t *self = self_in; + if (self->nic == MP_OBJ_NULL) { + // not connected + mp_raise_OSError(MP_ENOTCONN); + } + vstr_t vstr; + vstr_init_len(&vstr, mp_obj_get_int(len_in)); + byte ip[4]; + mp_uint_t port; + int _errno; + mp_int_t ret = self->nic_type->recvfrom(self, (byte*)vstr.buf, vstr.len, ip, &port, &_errno); + if (ret == -1) { + mp_raise_OSError(_errno); + } + mp_obj_t tuple[2]; + if (ret == 0) { + tuple[0] = mp_const_empty_bytes; + } else { + vstr.len = ret; + tuple[0] = mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr); + } + + if (self->u_param.domain == MOD_NETWORK_AF_INET) { + tuple[1] = netutils_format_inet_addr(ip, port, NETUTILS_BIG); + } else { + tuple[1] = netutils_format_inet6_addr(ip, port, NETUTILS_BIG); + } + return mp_obj_new_tuple(2, tuple); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_recvfrom_obj, socket_recvfrom); + +// method socket.setsockopt(level, optname, value) +STATIC mp_obj_t socket_setsockopt(mp_uint_t n_args, const mp_obj_t *args) { + mod_network_socket_obj_t *self = args[0]; + + mp_int_t level = mp_obj_get_int(args[1]); + mp_int_t opt = mp_obj_get_int(args[2]); + + const void *optval; + mp_uint_t optlen; + mp_int_t val; + if (mp_obj_is_integer(args[3])) { + val = mp_obj_get_int_truncated(args[3]); + optval = &val; + optlen = sizeof(val); + } else { + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(args[3], &bufinfo, MP_BUFFER_READ); + optval = bufinfo.buf; + optlen = bufinfo.len; + } + + int _errno; + if (self->nic_type->setsockopt(self, level, opt, optval, optlen, &_errno) != 0) { + mp_raise_OSError(_errno); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(socket_setsockopt_obj, 4, 4, socket_setsockopt); + +// method socket.settimeout(value) +// timeout=0 means non-blocking +// timeout=None means blocking +// otherwise, timeout is in seconds +STATIC mp_obj_t socket_settimeout(mp_obj_t self_in, mp_obj_t timeout_in) { + mod_network_socket_obj_t *self = self_in; + if (self->nic == MP_OBJ_NULL) { + // not connected + mp_raise_OSError(MP_ENOTCONN); + } + mp_uint_t timeout; + if (timeout_in == mp_const_none) { + timeout = -1; + } else { + #if MICROPY_PY_BUILTINS_FLOAT + timeout = 1000 * mp_obj_get_float(timeout_in); + #else + timeout = 1000 * mp_obj_get_int(timeout_in); + #endif + } + int _errno; + if (self->nic_type->settimeout(self, timeout, &_errno) != 0) { + mp_raise_OSError(_errno); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_settimeout_obj, socket_settimeout); + +// method socket.setblocking(flag) +STATIC mp_obj_t socket_setblocking(mp_obj_t self_in, mp_obj_t blocking) { + if (mp_obj_is_true(blocking)) { + return socket_settimeout(self_in, mp_const_none); + } else { + return socket_settimeout(self_in, MP_OBJ_NEW_SMALL_INT(0)); + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_setblocking_obj, socket_setblocking); + +STATIC const mp_map_elem_t socket_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)&socket_close_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_close), (mp_obj_t)&socket_close_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_bind), (mp_obj_t)&socket_bind_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_listen), (mp_obj_t)&socket_listen_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_accept), (mp_obj_t)&socket_accept_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)&socket_connect_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_send), (mp_obj_t)&socket_send_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_recv), (mp_obj_t)&socket_recv_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_sendto), (mp_obj_t)&socket_sendto_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_recvfrom), (mp_obj_t)&socket_recvfrom_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setsockopt), (mp_obj_t)&socket_setsockopt_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_settimeout), (mp_obj_t)&socket_settimeout_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setblocking), (mp_obj_t)&socket_setblocking_obj }, +}; + +STATIC MP_DEFINE_CONST_DICT(socket_locals_dict, socket_locals_dict_table); + +mp_uint_t socket_ioctl(mp_obj_t self_in, mp_uint_t request, mp_uint_t arg, int *errcode) { + mod_network_socket_obj_t *self = self_in; + return self->nic_type->ioctl(self, request, arg, errcode); +} + +STATIC const mp_stream_p_t socket_stream_p = { + .ioctl = socket_ioctl, + .is_text = false, +}; + +STATIC const mp_obj_type_t socket_type = { + { &mp_type_type }, + .name = MP_QSTR_socket, + .make_new = socket_make_new, + .protocol = &socket_stream_p, + .locals_dict = (mp_obj_t)&socket_locals_dict, +}; + +/******************************************************************************/ +// usocket module + +// function usocket.getaddrinfo(host, port) +STATIC mp_obj_t mod_usocket_getaddrinfo(mp_obj_t host_in, mp_obj_t port_in) { + mp_uint_t hlen; + const char *host = mp_obj_str_get_data(host_in, &hlen); + mp_int_t port = mp_obj_get_int(port_in); + + // find a NIC that can do a name lookup + for (mp_uint_t i = 0; i < MP_STATE_PORT(mod_network_nic_list).len; i++) { + mp_obj_t nic = MP_STATE_PORT(mod_network_nic_list).items[i]; + mod_network_nic_type_t *nic_type = (mod_network_nic_type_t*)mp_obj_get_type(nic); + if (nic_type->gethostbyname != NULL) { + uint8_t out_ip[MOD_NETWORK_IPADDR_BUF_SIZE]; + int ret = nic_type->gethostbyname(nic, host, hlen, out_ip); + if (ret != 0) { + // TODO CPython raises: socket.gaierror: [Errno -2] Name or service not known + mp_raise_OSError(ret); + } + mp_obj_tuple_t *tuple = mp_obj_new_tuple(5, NULL); + tuple->items[0] = MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_AF_INET); + tuple->items[1] = MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_SOCK_STREAM); + tuple->items[2] = MP_OBJ_NEW_SMALL_INT(0); + tuple->items[3] = MP_OBJ_NEW_QSTR(MP_QSTR_); + tuple->items[4] = netutils_format_inet_addr(out_ip, port, NETUTILS_BIG); + return mp_obj_new_list(1, (mp_obj_t*)&tuple); + } + } + + nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "no available NIC")); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(mod_usocket_getaddrinfo_obj, mod_usocket_getaddrinfo); + +STATIC const mp_map_elem_t mp_module_usocket_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_usocket) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_socket), (mp_obj_t)&socket_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getaddrinfo), (mp_obj_t)&mod_usocket_getaddrinfo_obj }, + + // class constants + { MP_OBJ_NEW_QSTR(MP_QSTR_AF_INET), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_AF_INET) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AF_INET6), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_AF_INET6) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_SOCK_STREAM), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_SOCK_STREAM) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SOCK_DGRAM), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_SOCK_DGRAM) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SOCK_RAW), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_SOCK_RAW) }, + + /* + { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_IP), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_IP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_ICMP), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_ICMP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_IPV4), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_IPV4) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_TCP), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_TCP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_UDP), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_UDP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_IPV6), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_IPV6) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_RAW), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_RAW) }, + */ +}; + +STATIC MP_DEFINE_CONST_DICT(mp_module_usocket_globals, mp_module_usocket_globals_table); + +const mp_obj_module_t mp_module_usocket = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&mp_module_usocket_globals, +}; + +#endif // MICROPY_PY_USOCKET diff --git a/nrf5/modutime.c b/nrf5/modutime.c new file mode 100644 index 0000000000..a0e4f904c4 --- /dev/null +++ b/nrf5/modutime.c @@ -0,0 +1,52 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include NRF5_HAL_H + +#include "py/nlr.h" +#include "py/smallint.h" +#include "py/obj.h" +#include "extmod/utime_mphal.h" + +/// \module time - time related functions +/// +/// The `time` module provides functions for getting the current time and date, +/// and for sleeping. + +STATIC const mp_rom_map_elem_t time_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_utime) }, + + { MP_ROM_QSTR(MP_QSTR_sleep_ms), MP_ROM_PTR(&mp_utime_sleep_ms_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(time_module_globals, time_module_globals_table); + +const mp_obj_module_t mp_module_utime = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&time_module_globals, +}; diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 9a8865dce0..b43dc9940e 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -27,7 +27,7 @@ #ifndef NRF5_MPCONFIGPORT_H__ #define NRF5_MPCONFIGPORT_H__ -#include +#include // options to control how Micro Python is built // options to control how Micro Python is built @@ -45,20 +45,20 @@ #define MICROPY_REPL_EMACS_KEYS (0) #define MICROPY_REPL_AUTO_INDENT (0) #define MICROPY_ENABLE_SOURCE_LINE (0) -#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_NONE) +#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ) #define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_NONE) #define MICROPY_OPT_COMPUTED_GOTO (0) #define MICROPY_OPT_CACHE_MAP_LOOKUP_IN_BYTECODE (0) #define MICROPY_OPT_MPZ_BITWISE (0) // fatfs configuration used in ffconf.h -#define MICROPY_FATFS_ENABLE_LFN (0) +#define MICROPY_FATFS_ENABLE_LFN (1) #define MICROPY_FATFS_LFN_CODE_PAGE (437) /* 1=SFN/ANSI 437=LFN/U.S.(OEM) */ -#define MICROPY_FATFS_USE_LABEL (0) -#define MICROPY_FATFS_RPATH (0) -#define MICROPY_FATFS_VOLUMES (0) -#define MICROPY_FATFS_MULTI_PARTITION (0) -#define MICROPY_FSUSERMOUNT (0) +#define MICROPY_FATFS_USE_LABEL (1) +#define MICROPY_FATFS_RPATH (2) +#define MICROPY_FATFS_VOLUMES (4) +#define MICROPY_FATFS_MULTI_PARTITION (1) +#define MICROPY_FSUSERMOUNT (1) #define MICROPY_STREAMS_NON_BLOCK (1) #define MICROPY_MODULE_WEAK_LINKS (1) @@ -69,8 +69,8 @@ #define MICROPY_PY_BUILTINS_STR_CENTER (0) #define MICROPY_PY_BUILTINS_STR_PARTITION (0) #define MICROPY_PY_BUILTINS_STR_SPLITLINES (0) -#define MICROPY_PY_BUILTINS_MEMORYVIEW (0) -#define MICROPY_PY_BUILTINS_FROZENSET (0) +#define MICROPY_PY_BUILTINS_MEMORYVIEW (1) +#define MICROPY_PY_BUILTINS_FROZENSET (1) #define MICROPY_PY_BUILTINS_EXECFILE (0) #define MICROPY_PY_BUILTINS_COMPILE (1) #define MICROPY_PY_ALL_SPECIAL_METHODS (0) @@ -96,25 +96,34 @@ #define MICROPY_PY_URE (0) #define MICROPY_PY_UHEAPQ (0) #define MICROPY_PY_UHASHLIB (0) -#define MICROPY_PY_UTIME_MP_HAL (0) -#define MICROPY_PY_MACHINE (0) +#define MICROPY_PY_UTIME_MP_HAL (1) +#define MICROPY_PY_MACHINE (1) #define MICROPY_PY_MACHINE_PULSE (0) #define MICROPY_PY_MACHINE_I2C (0) -#define MICROPY_PY_MACHINE_SPI (0) + +#ifndef MICROPY_PY_MACHINE_SPI +#define MICROPY_PY_MACHINE_SPI (1) +#endif + #define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) #define MICROPY_PY_FRAMEBUF (0) #ifndef MICROPY_PY_USOCKET -#define MICROPY_PY_USOCKET (0) +#define MICROPY_PY_USOCKET (1) #endif #ifndef MICROPY_PY_NETWORK -#define MICROPY_PY_NETWORK (0) +#define MICROPY_PY_NETWORK (1) #endif #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) #define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0) +// if sdk is in use, import configuration +#if BLUETOOTH_SD +#include "nrf5_sdk_conf.h" +#endif + // type definitions for the specific machine #define BYTES_PER_WORD (4) @@ -131,33 +140,68 @@ typedef int mp_int_t; // must be pointer size typedef unsigned int mp_uint_t; // must be pointer size typedef long mp_off_t; -// board specific definitions -#include "mpconfigboard.h" - // extra built in modules to add to the list of known ones extern const struct _mp_obj_module_t pyb_module; +extern const struct _mp_obj_module_t machine_module; +extern const struct _mp_obj_module_t mp_module_utime; +extern const struct _mp_obj_module_t mp_module_uos; +extern const struct _mp_obj_module_t mp_module_usocket; +extern const struct _mp_obj_module_t mp_module_network; + +#if MICROPY_PY_USOCKET +#define SOCKET_BUILTIN_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_usocket), (mp_obj_t)&mp_module_usocket }, +#define SOCKET_BUILTIN_MODULE_WEAK_LINKS { MP_OBJ_NEW_QSTR(MP_QSTR_socket), (mp_obj_t)&mp_module_usocket }, +#else +#define SOCKET_BUILTIN_MODULE +#define SOCKET_BUILTIN_MODULE_WEAK_LINKS +#endif + +#if MICROPY_PY_NETWORK +#define NETWORK_BUILTIN_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_network), (mp_obj_t)&mp_module_network }, +#else +#define NETWORK_BUILTIN_MODULE +#endif + #if BLUETOOTH_SD extern const struct _mp_obj_module_t ble_module; #define MICROPY_PORT_BUILTIN_MODULES \ { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_ble), (mp_obj_t)&ble_module }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&mp_module_utime }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ + SOCKET_BUILTIN_MODULE \ + NETWORK_BUILTIN_MODULE \ + #else extern const struct _mp_obj_module_t ble_module; #define MICROPY_PORT_BUILTIN_MODULES \ { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ + #endif // BLUETOOTH_SD +#define MICROPY_PORT_BUILTIN_MODULE_WEAK_LINKS \ + { MP_OBJ_NEW_QSTR(MP_QSTR_os), (mp_obj_t)&mp_module_uos }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&mp_module_utime }, \ + SOCKET_BUILTIN_MODULE_WEAK_LINKS \ + // extra built in names to add to the global namespace #define MICROPY_PORT_BUILTINS \ { MP_OBJ_NEW_QSTR(MP_QSTR_help), (mp_obj_t)&mp_builtin_help_obj }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_open), (mp_obj_t)&mp_builtin_open_obj }, \ // extra constants #define MICROPY_PORT_CONSTANTS \ { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_ble), (mp_obj_t)&ble_module }, \ + { MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \ #define MP_STATE_PORT MP_STATE_VM @@ -174,12 +218,15 @@ extern const struct _mp_obj_module_t ble_module; \ /* pointers to all UART objects (if they have been created) */ \ struct _pyb_uart_obj_t *pyb_uart_obj_all[1]; \ + \ + /* list of registered NICs */ \ + mp_obj_list_t mod_network_nic_list; \ #define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len) // We need to provide a declaration/definition of alloca() #include -#include "mpconfigboard.h" +#define MICROPY_PIN_DEFS_PORT_H "pin_defs_nrf5.h" #endif diff --git a/nrf5/mphalport.c b/nrf5/mphalport.c index 54283adde7..2de06d2314 100644 --- a/nrf5/mphalport.c +++ b/nrf5/mphalport.c @@ -23,6 +23,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ + #include #include @@ -47,6 +48,7 @@ void mp_hal_set_interrupt_char(int c) { } +#if (BLUETOOTH_SD != 132) int mp_hal_stdin_rx_chr(void) { for (;;) { if (MP_STATE_PORT(pyb_stdio_uart) != NULL && uart_rx_any(MP_STATE_PORT(pyb_stdio_uart))) { @@ -56,16 +58,19 @@ int mp_hal_stdin_rx_chr(void) { return 0; } +#endif void mp_hal_stdout_tx_str(const char *str) { mp_hal_stdout_tx_strn(str, strlen(str)); } +#if (BLUETOOTH_SD != 132) void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) { if (MP_STATE_PORT(pyb_stdio_uart) != NULL) { uart_tx_strn(MP_STATE_PORT(pyb_stdio_uart), str, len); } } +#endif void mp_hal_stdout_tx_strn_cooked(const char *str, mp_uint_t len) { if (MP_STATE_PORT(pyb_stdio_uart) != NULL) { diff --git a/nrf5/mphalport.h b/nrf5/mphalport.h index 47fb617c47..5d80d5142b 100644 --- a/nrf5/mphalport.h +++ b/nrf5/mphalport.h @@ -27,10 +27,9 @@ #ifndef __NRF52_HAL #define __NRF52_HAL -#include - #include "py/mpconfig.h" -#include "nrf.h" +#include NRF5_HAL_H +#include "pin.h" typedef enum { @@ -47,6 +46,27 @@ typedef enum #define GPIO_BASE ((NRF_GPIO_Type *)NRF_P0_BASE) #endif +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternat_function_selection */ +} GPIO_InitTypeDef; + typedef enum { HAL_GPIO_PULL_DISABLED = (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos), HAL_GPIO_PULL_DOWN = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos), @@ -106,5 +126,16 @@ void mp_hal_set_interrupt_char(int c); // -1 to disable int mp_hal_stdin_rx_chr(void); void mp_hal_stdout_tx_str(const char *str); +#define mp_hal_pin_obj_t const pin_obj_t* +#define mp_hal_pin_high(p) (((NRF_GPIO_Type *)((p)->gpio))->OUTSET = (p)->pin_mask) +#define mp_hal_pin_low(p) (((NRF_GPIO_Type *)((p)->gpio))->OUTCLR = (p)->pin_mask) +#define mp_hal_pin_read(p) (((NRF_GPIO_Type *)((p)->gpio))->OUT >> ((p)->pin) & 1) +#define mp_hal_pin_write(p, v) do { if (v) { mp_hal_pin_high(p); } else { mp_hal_pin_low(p); } } while (0) + +// TODO: empty implementation for now. Used by machine_spi.c:69 +#define mp_hal_delay_us_fast(p) +#define mp_hal_ticks_us() (0) +#define mp_hal_ticks_cpu() (0) + #endif diff --git a/nrf5/nrf51_af.csv b/nrf5/nrf51_af.csv new file mode 100644 index 0000000000..b54aaa1e31 --- /dev/null +++ b/nrf5/nrf51_af.csv @@ -0,0 +1,32 @@ +PA0,PA0 +PA1,PA1 +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA5,PA5 +PA6,PA6 +PA7,PA7 +PA8,PA8 +PA9,PA9 +PA10,PA10 +PA11,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 \ No newline at end of file diff --git a/nrf5/nrf52_af.csv b/nrf5/nrf52_af.csv new file mode 100644 index 0000000000..b54aaa1e31 --- /dev/null +++ b/nrf5/nrf52_af.csv @@ -0,0 +1,32 @@ +PA0,PA0 +PA1,PA1 +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA5,PA5 +PA6,PA6 +PA7,PA7 +PA8,PA8 +PA9,PA9 +PA10,PA10 +PA11,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 \ No newline at end of file diff --git a/nrf5/pin.c b/nrf5/pin.c new file mode 100644 index 0000000000..5172ec27d1 --- /dev/null +++ b/nrf5/pin.c @@ -0,0 +1,611 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +#include +#include +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "pin.h" + +/// \moduleref pyb +/// \class Pin - control I/O pins +/// +/// A pin is the basic object to control I/O pins. It has methods to set +/// the mode of the pin (input, output, etc) and methods to get and set the +/// digital logic level. For analog control of a pin, see the ADC class. +/// +/// Usage Model: +/// +/// All Board Pins are predefined as pyb.Pin.board.Name +/// +/// x1_pin = pyb.Pin.board.X1 +/// +/// g = pyb.Pin(pyb.Pin.board.X1, pyb.Pin.IN) +/// +/// CPU pins which correspond to the board pins are available +/// as `pyb.cpu.Name`. For the CPU pins, the names are the port letter +/// followed by the pin number. On the PYBv1.0, `pyb.Pin.board.X1` and +/// `pyb.Pin.cpu.B6` are the same pin. +/// +/// You can also use strings: +/// +/// g = pyb.Pin('X1', pyb.Pin.OUT_PP) +/// +/// Users can add their own names: +/// +/// MyMapperDict = { 'LeftMotorDir' : pyb.Pin.cpu.C12 } +/// pyb.Pin.dict(MyMapperDict) +/// g = pyb.Pin("LeftMotorDir", pyb.Pin.OUT_OD) +/// +/// and can query mappings +/// +/// pin = pyb.Pin("LeftMotorDir") +/// +/// Users can also add their own mapping function: +/// +/// def MyMapper(pin_name): +/// if pin_name == "LeftMotorDir": +/// return pyb.Pin.cpu.A0 +/// +/// pyb.Pin.mapper(MyMapper) +/// +/// So, if you were to call: `pyb.Pin("LeftMotorDir", pyb.Pin.OUT_PP)` +/// then `"LeftMotorDir"` is passed directly to the mapper function. +/// +/// To summarise, the following order determines how things get mapped into +/// an ordinal pin number: +/// +/// 1. Directly specify a pin object +/// 2. User supplied mapping function +/// 3. User supplied mapping (object must be usable as a dictionary key) +/// 4. Supply a string which matches a board pin +/// 5. Supply a string which matches a CPU port/pin +/// +/// You can set `pyb.Pin.debug(True)` to get some debug information about +/// how a particular object gets mapped to a pin. + +// Pin class variables +STATIC bool pin_class_debug; + +void pin_init0(void) { + MP_STATE_PORT(pin_class_mapper) = mp_const_none; + MP_STATE_PORT(pin_class_map_dict) = mp_const_none; + pin_class_debug = false; +} + +// C API used to convert a user-supplied pin name into an ordinal pin number. +const pin_obj_t *pin_find(mp_obj_t user_obj) { + const pin_obj_t *pin_obj; + + // If a pin was provided, then use it + if (MP_OBJ_IS_TYPE(user_obj, &pin_type)) { + pin_obj = user_obj; + if (pin_class_debug) { + printf("Pin map passed pin "); + mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); + printf("\n"); + } + return pin_obj; + } + + if (MP_STATE_PORT(pin_class_mapper) != mp_const_none) { + pin_obj = mp_call_function_1(MP_STATE_PORT(pin_class_mapper), user_obj); + if (pin_obj != mp_const_none) { + if (!MP_OBJ_IS_TYPE(pin_obj, &pin_type)) { + nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "Pin.mapper didn't return a Pin object")); + } + if (pin_class_debug) { + printf("Pin.mapper maps "); + mp_obj_print(user_obj, PRINT_REPR); + printf(" to "); + mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); + printf("\n"); + } + return pin_obj; + } + // The pin mapping function returned mp_const_none, fall through to + // other lookup methods. + } + + if (MP_STATE_PORT(pin_class_map_dict) != mp_const_none) { + mp_map_t *pin_map_map = mp_obj_dict_get_map(MP_STATE_PORT(pin_class_map_dict)); + mp_map_elem_t *elem = mp_map_lookup(pin_map_map, user_obj, MP_MAP_LOOKUP); + if (elem != NULL && elem->value != NULL) { + pin_obj = elem->value; + if (pin_class_debug) { + printf("Pin.map_dict maps "); + mp_obj_print(user_obj, PRINT_REPR); + printf(" to "); + mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); + printf("\n"); + } + return pin_obj; + } + } + + // See if the pin name matches a board pin + pin_obj = pin_find_named_pin(&pin_board_pins_locals_dict, user_obj); + if (pin_obj) { + if (pin_class_debug) { + printf("Pin.board maps "); + mp_obj_print(user_obj, PRINT_REPR); + printf(" to "); + mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); + printf("\n"); + } + return pin_obj; + } + + // See if the pin name matches a cpu pin + pin_obj = pin_find_named_pin(&pin_cpu_pins_locals_dict, user_obj); + if (pin_obj) { + if (pin_class_debug) { + printf("Pin.cpu maps "); + mp_obj_print(user_obj, PRINT_REPR); + printf(" to "); + mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); + printf("\n"); + } + return pin_obj; + } + + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "pin '%s' not a valid pin identifier", mp_obj_str_get_str(user_obj))); +} + +/// \method __str__() +/// Return a string describing the pin object. +STATIC void pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + pin_obj_t *self = self_in; + + // pin name + mp_printf(print, "Pin(Pin.cpu.%q, mode=Pin.", self->name); + mp_printf(print, "gpio=0x%x,", self->gpio); + mp_printf(print, "pin_mask=0x%x,", self->pin_mask); +/* + uint32_t mode = pin_get_mode(self); + + if (mode == GPIO_MODE_ANALOG) { + // analog + mp_print_str(print, "ANALOG)"); + + } else { + // IO mode + bool af = false; + qstr mode_qst; + if (mode == GPIO_MODE_INPUT) { + mode_qst = MP_QSTR_IN; + } else if (mode == GPIO_MODE_OUTPUT_PP) { + mode_qst = MP_QSTR_OUT; + } else if (mode == GPIO_MODE_OUTPUT_OD) { + mode_qst = MP_QSTR_OPEN_DRAIN; + } else { + af = true; + if (mode == GPIO_MODE_AF_PP) { + mode_qst = MP_QSTR_ALT; + } else { + mode_qst = MP_QSTR_ALT_OPEN_DRAIN; + } + } + mp_print_str(print, qstr_str(mode_qst)); + + // pull mode + qstr pull_qst = MP_QSTR_NULL; + uint32_t pull = pin_get_pull(self); + if (pull == GPIO_PULLUP) { + pull_qst = MP_QSTR_PULL_UP; + } else if (pull == GPIO_PULLDOWN) { + pull_qst = MP_QSTR_PULL_DOWN; + } + if (pull_qst != MP_QSTR_NULL) { + mp_printf(print, ", pull=Pin.%q", pull_qst); + } + + // AF mode + if (af) { + mp_uint_t af_idx = pin_get_af(self); + const pin_af_obj_t *af_obj = pin_find_af_by_index(self, af_idx); + if (af_obj == NULL) { + mp_printf(print, ", af=%d)", af_idx); + } else { + mp_printf(print, ", af=Pin.%q)", af_obj->name); + } + } else { +*/ + mp_print_str(print, ")"); + /* } + }*/ + +} + +STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *pin, mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args); + +/// \classmethod \constructor(id, ...) +/// Create a new Pin object associated with the id. If additional arguments are given, +/// they are used to initialise the pin. See `init`. +STATIC mp_obj_t pin_make_new(const mp_obj_type_t *type, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true); + + // Run an argument through the mapper and return the result. + const pin_obj_t *pin = pin_find(args[0]); + + if (n_args > 1 || n_kw > 0) { + // pin mode given, so configure this GPIO + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + pin_obj_init_helper(pin, n_args - 1, args + 1, &kw_args); + } + + return (mp_obj_t)pin; +} + +// fast method for getting/setting pin value +STATIC mp_obj_t pin_call(mp_obj_t self_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 0, 1, false); + pin_obj_t *self = self_in; + if (n_args == 0) { + // get pin + return MP_OBJ_NEW_SMALL_INT(mp_hal_pin_read(self)); + } else { + // set pin + mp_hal_pin_write(self, mp_obj_is_true(args[0])); + return mp_const_none; + } +} + +/// \classmethod mapper([fun]) +/// Get or set the pin mapper function. +STATIC mp_obj_t pin_mapper(mp_uint_t n_args, const mp_obj_t *args) { + if (n_args > 1) { + MP_STATE_PORT(pin_class_mapper) = args[1]; + return mp_const_none; + } + return MP_STATE_PORT(pin_class_mapper); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_mapper_fun_obj, 1, 2, pin_mapper); +STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_mapper_obj, (mp_obj_t)&pin_mapper_fun_obj); + +/// \classmethod dict([dict]) +/// Get or set the pin mapper dictionary. +STATIC mp_obj_t pin_map_dict(mp_uint_t n_args, const mp_obj_t *args) { + if (n_args > 1) { + MP_STATE_PORT(pin_class_map_dict) = args[1]; + return mp_const_none; + } + return MP_STATE_PORT(pin_class_map_dict); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_map_dict_fun_obj, 1, 2, pin_map_dict); +STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_map_dict_obj, (mp_obj_t)&pin_map_dict_fun_obj); + +/// \classmethod af_list() +/// Returns an array of alternate functions available for this pin. +STATIC mp_obj_t pin_af_list(mp_obj_t self_in) { + pin_obj_t *self = self_in; + mp_obj_t result = mp_obj_new_list(0, NULL); + + const pin_af_obj_t *af = self->af; + for (mp_uint_t i = 0; i < self->num_af; i++, af++) { + mp_obj_list_append(result, (mp_obj_t)af); + } + return result; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_list_obj, pin_af_list); + +/// \classmethod debug([state]) +/// Get or set the debugging state (`True` or `False` for on or off). +STATIC mp_obj_t pin_debug(mp_uint_t n_args, const mp_obj_t *args) { + if (n_args > 1) { + pin_class_debug = mp_obj_is_true(args[1]); + return mp_const_none; + } + return mp_obj_new_bool(pin_class_debug); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_debug_fun_obj, 1, 2, pin_debug); +STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_debug_obj, (mp_obj_t)&pin_debug_fun_obj); + +// init(mode, pull=None, af=-1, *, value, alt) +STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT }, + { MP_QSTR_pull, MP_ARG_OBJ, {.u_obj = mp_const_none}}, + { MP_QSTR_af, MP_ARG_INT, {.u_int = -1}}, // legacy + { MP_QSTR_value, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL}}, + { MP_QSTR_alt, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1}}, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); +/* + // get io mode + uint mode = args[0].u_int; + if (!IS_GPIO_MODE(mode)) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "invalid pin mode: %d", mode)); + } +*/ + // get pull mode + uint pull = HAL_GPIO_PULL_DISABLED; + if (args[1].u_obj != mp_const_none) { + pull = mp_obj_get_int(args[1].u_obj); + } + + (void)pull; + + // if given, set the pin value before initialising to prevent glitches + if (args[3].u_obj != MP_OBJ_NULL) { + mp_hal_pin_write(self, mp_obj_is_true(args[3].u_obj)); + } + + hal_gpio_cfg_pin_output(self->pin_mask); + + return mp_const_none; +} + +STATIC mp_obj_t pin_obj_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) { + return pin_obj_init_helper(args[0], n_args - 1, args + 1, kw_args); +} +MP_DEFINE_CONST_FUN_OBJ_KW(pin_init_obj, 1, pin_obj_init); + +/// \method value([value]) +/// Get or set the digital logic level of the pin: +/// +/// - With no argument, return 0 or 1 depending on the logic level of the pin. +/// - With `value` given, set the logic level of the pin. `value` can be +/// anything that converts to a boolean. If it converts to `True`, the pin +/// is set high, otherwise it is set low. +STATIC mp_obj_t pin_value(mp_uint_t n_args, const mp_obj_t *args) { + return pin_call(args[0], n_args - 1, 0, args + 1); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_value_obj, 1, 2, pin_value); + +/// \method low() +/// Set the pin to a low logic level. +STATIC mp_obj_t pin_low(mp_obj_t self_in) { + pin_obj_t *self = self_in; + mp_hal_pin_low(self); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_low_obj, pin_low); + +/// \method high() +/// Set the pin to a high logic level. +STATIC mp_obj_t pin_high(mp_obj_t self_in) { + pin_obj_t *self = self_in; + mp_hal_pin_high(self); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_high_obj, pin_high); + +/// \method name() +/// Get the pin name. +STATIC mp_obj_t pin_name(mp_obj_t self_in) { + pin_obj_t *self = self_in; + return MP_OBJ_NEW_QSTR(self->name); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_name_obj, pin_name); + +/// \method names() +/// Returns the cpu and board names for this pin. +STATIC mp_obj_t pin_names(mp_obj_t self_in) { + pin_obj_t *self = self_in; + mp_obj_t result = mp_obj_new_list(0, NULL); + mp_obj_list_append(result, MP_OBJ_NEW_QSTR(self->name)); + + mp_map_t *map = mp_obj_dict_get_map((mp_obj_t)&pin_board_pins_locals_dict); + mp_map_elem_t *elem = map->table; + + for (mp_uint_t i = 0; i < map->used; i++, elem++) { + if (elem->value == self) { + mp_obj_list_append(result, elem->key); + } + } + return result; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_names_obj, pin_names); + +/// \method port() +/// Get the pin port. +STATIC mp_obj_t pin_port(mp_obj_t self_in) { + pin_obj_t *self = self_in; + return MP_OBJ_NEW_SMALL_INT(self->port); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_port_obj, pin_port); + +/// \method pin() +/// Get the pin number. +STATIC mp_obj_t pin_pin(mp_obj_t self_in) { + pin_obj_t *self = self_in; + return MP_OBJ_NEW_SMALL_INT(self->pin); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_pin_obj, pin_pin); + +/// \method gpio() +/// Returns the base address of the GPIO block associated with this pin. +STATIC mp_obj_t pin_gpio(mp_obj_t self_in) { + pin_obj_t *self = self_in; + return MP_OBJ_NEW_SMALL_INT((mp_int_t)self->gpio); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_gpio_obj, pin_gpio); + +/// \method mode() +/// Returns the currently configured mode of the pin. The integer returned +/// will match one of the allowed constants for the mode argument to the init +/// function. +STATIC mp_obj_t pin_mode(mp_obj_t self_in) { + return mp_const_none; // TODO: MP_OBJ_NEW_SMALL_INT(pin_get_mode(self_in)); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_mode_obj, pin_mode); + +/// \method pull() +/// Returns the currently configured pull of the pin. The integer returned +/// will match one of the allowed constants for the pull argument to the init +/// function. +STATIC mp_obj_t pin_pull(mp_obj_t self_in) { + return mp_const_none; // TODO: MP_OBJ_NEW_SMALL_INT(pin_get_pull(self_in)); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_pull_obj, pin_pull); + +/// \method af() +/// Returns the currently configured alternate-function of the pin. The +/// integer returned will match one of the allowed constants for the af +/// argument to the init function. +STATIC mp_obj_t pin_af(mp_obj_t self_in) { + return mp_const_none; // TODO: MP_OBJ_NEW_SMALL_INT(pin_get_af(self_in)); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_obj, pin_af); + +STATIC const mp_map_elem_t pin_locals_dict_table[] = { + // instance methods + { MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&pin_init_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_value), (mp_obj_t)&pin_value_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_low), (mp_obj_t)&pin_low_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_high), (mp_obj_t)&pin_high_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_name), (mp_obj_t)&pin_name_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_names), (mp_obj_t)&pin_names_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_af_list), (mp_obj_t)&pin_af_list_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_port), (mp_obj_t)&pin_port_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_pin), (mp_obj_t)&pin_pin_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_gpio), (mp_obj_t)&pin_gpio_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_mode), (mp_obj_t)&pin_mode_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_pull), (mp_obj_t)&pin_pull_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_af), (mp_obj_t)&pin_af_obj }, + + // class methods + { MP_OBJ_NEW_QSTR(MP_QSTR_mapper), (mp_obj_t)&pin_mapper_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_dict), (mp_obj_t)&pin_map_dict_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_debug), (mp_obj_t)&pin_debug_obj }, +/* + // class attributes + { MP_OBJ_NEW_QSTR(MP_QSTR_board), (mp_obj_t)&pin_board_pins_obj_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_cpu), (mp_obj_t)&pin_cpu_pins_obj_type }, + + // class constants + { MP_OBJ_NEW_QSTR(MP_QSTR_IN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_INPUT) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_OUT), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ALT), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_PP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ALT_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_OD) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ANALOG), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_ANALOG) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_UP), MP_OBJ_NEW_SMALL_INT(GPIO_PULLUP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DOWN), MP_OBJ_NEW_SMALL_INT(GPIO_PULLDOWN) }, + + // legacy class constants + { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_PP), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_OD), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AF_PP), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_PP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AF_OD), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_OD) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_NONE), MP_OBJ_NEW_SMALL_INT(GPIO_NOPULL) }, +*/ +#include "genhdr/pins_af_const.h" +}; + +STATIC MP_DEFINE_CONST_DICT(pin_locals_dict, pin_locals_dict_table); + +const mp_obj_type_t pin_type = { + { &mp_type_type }, + .name = MP_QSTR_Pin, + .print = pin_print, + .make_new = pin_make_new, + .call = pin_call, + .locals_dict = (mp_obj_t)&pin_locals_dict, +}; + +/// \moduleref pyb +/// \class PinAF - Pin Alternate Functions +/// +/// A Pin represents a physical pin on the microcprocessor. Each pin +/// can have a variety of functions (GPIO, I2C SDA, etc). Each PinAF +/// object represents a particular function for a pin. +/// +/// Usage Model: +/// +/// x3 = pyb.Pin.board.X3 +/// x3_af = x3.af_list() +/// +/// x3_af will now contain an array of PinAF objects which are availble on +/// pin X3. +/// +/// For the pyboard, x3_af would contain: +/// [Pin.AF1_TIM2, Pin.AF2_TIM5, Pin.AF3_TIM9, Pin.AF7_USART2] +/// +/// Normally, each peripheral would configure the af automatically, but sometimes +/// the same function is available on multiple pins, and having more control +/// is desired. +/// +/// To configure X3 to expose TIM2_CH3, you could use: +/// pin = pyb.Pin(pyb.Pin.board.X3, mode=pyb.Pin.AF_PP, af=pyb.Pin.AF1_TIM2) +/// or: +/// pin = pyb.Pin(pyb.Pin.board.X3, mode=pyb.Pin.AF_PP, af=1) + +/// \method __str__() +/// Return a string describing the alternate function. +STATIC void pin_af_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + pin_af_obj_t *self = self_in; + mp_printf(print, "Pin.%q", self->name); +} + +/// \method index() +/// Return the alternate function index. +STATIC mp_obj_t pin_af_index(mp_obj_t self_in) { + pin_af_obj_t *af = self_in; + return MP_OBJ_NEW_SMALL_INT(af->idx); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_index_obj, pin_af_index); + +/// \method name() +/// Return the name of the alternate function. +STATIC mp_obj_t pin_af_name(mp_obj_t self_in) { + pin_af_obj_t *af = self_in; + return MP_OBJ_NEW_QSTR(af->name); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_name_obj, pin_af_name); + +/// \method reg() +/// Return the base register associated with the peripheral assigned to this +/// alternate function. +STATIC mp_obj_t pin_af_reg(mp_obj_t self_in) { + pin_af_obj_t *af = self_in; + return MP_OBJ_NEW_SMALL_INT((mp_uint_t)af->reg); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_reg_obj, pin_af_reg); + +STATIC const mp_map_elem_t pin_af_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_index), (mp_obj_t)&pin_af_index_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_name), (mp_obj_t)&pin_af_name_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_reg), (mp_obj_t)&pin_af_reg_obj }, +}; +STATIC MP_DEFINE_CONST_DICT(pin_af_locals_dict, pin_af_locals_dict_table); + +const mp_obj_type_t pin_af_type = { + { &mp_type_type }, + .name = MP_QSTR_PinAF, + .print = pin_af_obj_print, + .locals_dict = (mp_obj_t)&pin_af_locals_dict, +}; diff --git a/nrf5/pin.h b/nrf5/pin.h new file mode 100644 index 0000000000..d2b6e863c9 --- /dev/null +++ b/nrf5/pin.h @@ -0,0 +1,101 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __MICROPY_INCLUDED_NRF5_PIN_H__ +#define __MICROPY_INCLUDED_NRF5_PIN_H__ + +// This file requires pin_defs_xxx.h (which has port specific enums and +// defines, so we include it here. It should never be included directly + +#include MICROPY_PIN_DEFS_PORT_H +#include "py/obj.h" + +typedef struct { + mp_obj_base_t base; + qstr name; + uint8_t idx; + uint8_t fn; + uint8_t unit; + uint8_t type; + + union { + void *reg; + + PIN_DEFS_PORT_AF_UNION + }; +} pin_af_obj_t; + +typedef struct { + mp_obj_base_t base; + qstr name; + uint32_t port : 4; + uint32_t pin : 5; // Some ARM processors use 32 bits/PORT + uint32_t num_af : 4; + uint32_t adc_channel : 5; // Some ARM processors use 32 bits/PORT + uint32_t adc_num : 3; // 1 bit per ADC + uint32_t pin_mask; + pin_gpio_t *gpio; + const pin_af_obj_t *af; +} pin_obj_t; + +extern const mp_obj_type_t pin_type; +extern const mp_obj_type_t pin_af_type; + +typedef struct { + const char *name; + const pin_obj_t *pin; +} pin_named_pin_t; + +extern const pin_named_pin_t pin_board_pins[]; +extern const pin_named_pin_t pin_cpu_pins[]; + +//extern pin_map_obj_t pin_map_obj; + +typedef struct { + mp_obj_base_t base; + qstr name; + const pin_named_pin_t *named_pins; +} pin_named_pins_obj_t; + +extern const mp_obj_type_t pin_board_pins_obj_type; +extern const mp_obj_type_t pin_cpu_pins_obj_type; + +extern const mp_obj_dict_t pin_cpu_pins_locals_dict; +extern const mp_obj_dict_t pin_board_pins_locals_dict; + +MP_DECLARE_CONST_FUN_OBJ_KW(pin_init_obj); + +void pin_init0(void); +uint32_t pin_get_mode(const pin_obj_t *pin); +uint32_t pin_get_pull(const pin_obj_t *pin); +uint32_t pin_get_af(const pin_obj_t *pin); +const pin_obj_t *pin_find(mp_obj_t user_obj); +const pin_obj_t *pin_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name); +const pin_af_obj_t *pin_find_af(const pin_obj_t *pin, uint8_t fn, uint8_t unit); +const pin_af_obj_t *pin_find_af_by_index(const pin_obj_t *pin, mp_uint_t af_idx); +const pin_af_obj_t *pin_find_af_by_name(const pin_obj_t *pin, const char *name); + +#endif // __MICROPY_INCLUDED_NRF5_PIN_H__ diff --git a/nrf5/pin_defs_nrf5.h b/nrf5/pin_defs_nrf5.h new file mode 100644 index 0000000000..739b674d63 --- /dev/null +++ b/nrf5/pin_defs_nrf5.h @@ -0,0 +1,58 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file contains pin definitions that are specific to the nrf5 port. +// This file should only ever be #included by pin.h and not directly. + +enum { + PORT_A, +}; + +enum { + AF_FN_UART, + AF_FN_SPI, +}; + +enum { + AF_PIN_TYPE_UART_TX = 0, + AF_PIN_TYPE_UART_RX, + AF_PIN_TYPE_UART_CTS, + AF_PIN_TYPE_UART_RTS, + + AF_PIN_TYPE_SPI_MOSI = 0, + AF_PIN_TYPE_SPI_MISO, + AF_PIN_TYPE_SPI_SCK, + AF_PIN_TYPE_SPI_NSS, +}; + +#define PIN_DEFS_PORT_AF_UNION \ + NRF_UART_Type *UART; +// NRF_SPI_Type *SPIM; +// NRF_SPIS_Type *SPIS; + + +typedef NRF_GPIO_Type pin_gpio_t; diff --git a/nrf5/pin_named_pins.c b/nrf5/pin_named_pins.c new file mode 100644 index 0000000000..9e5f9593b4 --- /dev/null +++ b/nrf5/pin_named_pins.c @@ -0,0 +1,92 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/runtime.h" +#include "py/mphal.h" +#include "pin.h" + +STATIC void pin_named_pins_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + pin_named_pins_obj_t *self = self_in; + mp_printf(print, "", self->name); +} + +const mp_obj_type_t pin_cpu_pins_obj_type = { + { &mp_type_type }, + .name = MP_QSTR_cpu, + .print = pin_named_pins_obj_print, + .locals_dict = (mp_obj_t)&pin_cpu_pins_locals_dict, +}; + +const mp_obj_type_t pin_board_pins_obj_type = { + { &mp_type_type }, + .name = MP_QSTR_board, + .print = pin_named_pins_obj_print, + .locals_dict = (mp_obj_t)&pin_board_pins_locals_dict, +}; + +const pin_obj_t *pin_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name) { + mp_map_t *named_map = mp_obj_dict_get_map((mp_obj_t)named_pins); + mp_map_elem_t *named_elem = mp_map_lookup(named_map, name, MP_MAP_LOOKUP); + if (named_elem != NULL && named_elem->value != NULL) { + return named_elem->value; + } + return NULL; +} + +const pin_af_obj_t *pin_find_af(const pin_obj_t *pin, uint8_t fn, uint8_t unit) { + const pin_af_obj_t *af = pin->af; + for (mp_uint_t i = 0; i < pin->num_af; i++, af++) { + if (af->fn == fn && af->unit == unit) { + return af; + } + } + return NULL; +} + +const pin_af_obj_t *pin_find_af_by_index(const pin_obj_t *pin, mp_uint_t af_idx) { + const pin_af_obj_t *af = pin->af; + for (mp_uint_t i = 0; i < pin->num_af; i++, af++) { + if (af->idx == af_idx) { + return af; + } + } + return NULL; +} + +/* unused +const pin_af_obj_t *pin_find_af_by_name(const pin_obj_t *pin, const char *name) { + const pin_af_obj_t *af = pin->af; + for (mp_uint_t i = 0; i < pin->num_af; i++, af++) { + if (strcmp(name, qstr_str(af->name)) == 0) { + return af; + } + } + return NULL; +} +*/ diff --git a/nrf5/sdk/help_sd.h b/nrf5/sdk/help_sd.h index ff6c1ad044..f6d5ef6565 100644 --- a/nrf5/sdk/help_sd.h +++ b/nrf5/sdk/help_sd.h @@ -27,6 +27,10 @@ #ifndef HELP_SD_H__ #define HELP_SD_H__ +#include "nrf5_sdk_conf.h" + +#if MICROPY_PY_BLE + #define HELP_TEXT_SD \ "If compiled with SD= the additional commands are\n" \ "available:\n" \ @@ -35,4 +39,8 @@ " ble.advertise() -- Start advertising Eddystone beacon\n" \ "\n" +#else +#define HELP_TEXT_SD +#endif // MICROPY_PY_BLE + #endif diff --git a/nrf5/sdk/iot_0.9.0/build.mk b/nrf5/sdk/iot_0.9.0/build.mk new file mode 100644 index 0000000000..763aa5a424 --- /dev/null +++ b/nrf5/sdk/iot_0.9.0/build.mk @@ -0,0 +1,118 @@ +# this file's folder +SDK_DIR := $(SDK_ROOT) + +# -D in CFLAGS +DEFINES += __HEAP_SIZE=0 +DEFINES += BLE_STACK_SUPPORT_REQD +DEFINES += CONFIG_GPIO_AS_PINRESET +DEFINES += NRF52 +DEFINES += NRF52_PAN_12 +DEFINES += NRF52_PAN_15 +DEFINES += NRF52_PAN_20 +DEFINES += NRF52_PAN_30 +DEFINES += NRF52_PAN_31 +DEFINES += NRF52_PAN_36 +DEFINES += NRF52_PAN_51 +DEFINES += NRF52_PAN_53 +DEFINES += NRF52_PAN_54 +DEFINES += NRF52_PAN_55 +DEFINES += NRF52_PAN_58 +DEFINES += NRF52_PAN_62 +DEFINES += NRF52_PAN_63 +DEFINES += NRF52_PAN_64 +DEFINES += s1xx +DEFINES += SOFTDEVICE_PRESENT +DEFINES += SWI_DISABLE0 +DEFINES += NRF_SD_BLE_API_VERSION=3 +DEFINES += PEER_MANAGER_ENABLED=1 +DEFINES += FDS_ENABLED=1 +DEFINES += LWIP_DEBUG=0 + +# nordic SDK C sources (relative path) +SDK_SRC_C += \ + components/ble/common/ble_advdata.c \ + components/ble/common/ble_conn_params.c \ + components/ble/common/ble_srv_common.c \ + components/libraries/fifo/app_fifo.c \ + components/libraries/timer/app_timer.c \ + components/libraries/util/app_util_platform.c \ + components/softdevice/common/softdevice_handler/softdevice_handler.c \ + components/drivers_nrf/clock/nrf_drv_clock.c \ + components/libraries/util/app_error.c \ + components/drivers_nrf/common/nrf_drv_common.c \ + components/libraries/mem_manager/mem_manager.c \ + components/libraries/trace/app_trace.c \ + components/iot/context_manager/iot_context_manager.c \ + components/iot/iot_timer/iot_timer.c \ + external/lwip/src/core/def.c \ + external/lwip/src/core/dhcp.c \ + external/lwip/src/core/ipv6/dhcp6.c \ + external/lwip/src/core/dns.c \ + external/lwip/src/core/ipv4/icmp.c \ + external/lwip/src/core/ipv6/icmp6.c \ + external/lwip/src/core/ipv6/inet6.c \ + external/lwip/src/core/inet_chksum.c \ + external/lwip/src/core/init.c \ + external/lwip/src/core/ipv4/ip4.c \ + external/lwip/src/core/ipv4/ip4_addr.c \ + external/lwip/src/core/ipv6/ip6.c \ + external/lwip/src/core/ipv6/ip6_addr.c \ + external/lwip/src/core/memp.c \ + external/lwip/src/core/ipv6/mld6.c \ + external/lwip/src/core/ipv6/nd6.c \ + external/lwip/src/core/netif.c \ + external/lwip/src/port/nrf_platform_port.c \ + external/lwip/src/core/pbuf.c \ + external/lwip/src/core/raw.c \ + external/lwip/src/core/sys.c \ + external/lwip/src/core/tcp.c \ + external/lwip/src/core/tcp_in.c \ + external/lwip/src/core/tcp_out.c \ + external/lwip/src/core/timers.c \ + external/lwip/src/core/udp.c \ + +# include source folders (sort removes duplicates) +SDK_INC_DIRS += $(sort $(dir $(SDK_SRC_C))) +# nrf_drv_config.h +SDK_INC_DIRS += components/drivers_nrf/config +# app_util.h +SDK_INC_DIRS += components/libraries/util +# nrf_log.h +SDK_INC_DIRS += components/libraries/log/ +# nrf_log_internal.h +SDK_INC_DIRS += components/libraries/log/src +# nrf_clock.h +SDK_INC_DIRS += components/drivers_nrf/hal +# nrf_drv_common.h +SDK_INC_DIRS += components/drivers_nrf/common +# nrf_delay.h +SDK_INC_DIRS += components/drivers_nrf/delay +# ble_6lowpan.h +SDK_INC_DIRS += components/iot/ble_6lowpan +# ble_ipsp.h +SDK_INC_DIRS += components/iot/ble_ipsp +# iot_defines.h +SDK_INC_DIRS += components/iot/common +# SDK lwip includes +SDK_INC_DIRS += external/lwip/src/port/arch +SDK_INC_DIRS += external/lwip/src/include +SDK_INC_DIRS += external/lwip/src/include/netif +SDK_INC_DIRS += external/lwip/src/port +SDK_INC_DIRS += external/lwip/src/include/lwip + +LIBS += $(SDK_ROOT)/components/iot/ble_6lowpan/lib/ble_6lowpan.a + +CFLAGS += $(patsubst %,-D%,${DEFINES}) + +# include full path +INC += $(patsubst %,-I${SDK_DIR}/%, ${SDK_INC_DIRS}) + +# additional SDK source files +SRC_C += $(addprefix ${SDK_ROOT}/, $(SDK_SRC_C)) + +# Wrappers +SRC_C += \ + $(SDK_MODULES_PATH)sdkhelp.c \ + $(SDK_MODULES_PATH)modnwble6lowpan.c \ + + diff --git a/nrf5/sdk/iot_0.9.0/modnwble6lowpan.c b/nrf5/sdk/iot_0.9.0/modnwble6lowpan.c new file mode 100644 index 0000000000..80f1b81e0a --- /dev/null +++ b/nrf5/sdk/iot_0.9.0/modnwble6lowpan.c @@ -0,0 +1,217 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "nrf5_sdk_conf.h" + +#if MICROPY_PY_BLE_6LOWPAN + +#include "lwip/ip6_addr.h" +#include "lwip/udp.h" + +#ifdef MAX +#undef MAX +#endif + +#ifdef MIN +#undef MIN +#endif + +#include +#include +#include + +#include "py/nlr.h" +#include "py/objlist.h" +#include "py/runtime.h" +#include "py/mperrno.h" +#include "py/mphal.h" +#include "netutils.h" +#include "modnetwork.h" +#include "pin.h" +#include "genhdr/pins.h" +#include "lwip/ip6_addr.h" +#include "lwip/udp.h" + +/// \moduleref network + +typedef struct _ble_6lowpan_obj_t { + mp_obj_base_t base; +} ble_6lowpan_obj_t; + +STATIC ble_6lowpan_obj_t ble_6lowpan_obj; + + + +STATIC int ble_6lowpan_gethostbyname(mp_obj_t nic, const char *name, mp_uint_t len, uint8_t *out_ip) { + return MP_ENOENT; +} + +STATIC int ble_6lowpan_socket_socket(mod_network_socket_obj_t *socket, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +STATIC void ble_6lowpan_socket_close(mod_network_socket_obj_t *socket) { +} + +STATIC int ble_6lowpan_socket_bind(mod_network_socket_obj_t *socket, byte *ip, mp_uint_t port, int *_errno) { + err_t err; + socket->p_socket = udp_new_ip6(); + if (socket->p_socket) { + + + err = udp_bind_ip6(socket->p_socket, ip, port); + if (err != ERR_OK) { + *_errno = err; + udp_remove(socket->p_socket); + } + } + + return 0; +} + +STATIC int ble_6lowpan_socket_listen(mod_network_socket_obj_t *socket, mp_int_t backlog, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +STATIC int ble_6lowpan_socket_accept(mod_network_socket_obj_t *socket, mod_network_socket_obj_t *socket2, byte *ip, mp_uint_t *port, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +STATIC int ble_6lowpan_socket_connect(mod_network_socket_obj_t *socket, byte *ip, mp_uint_t port, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +STATIC mp_uint_t ble_6lowpan_socket_send(mod_network_socket_obj_t *socket, const byte *buf, mp_uint_t len, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +STATIC mp_uint_t ble_6lowpan_socket_recv(mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +#include "netutils/netutils.h" + +STATIC mp_uint_t ble_6lowpan_socket_sendto(mod_network_socket_obj_t *socket, const byte *buf, mp_uint_t len, byte *ip, mp_uint_t port, int *_errno) { + + struct pbuf * lwip_buffer = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM); + memcpy(lwip_buffer->payload, buf, len); + + printf("Sendto\n"); + + err_t err = udp_sendto_ip6(socket->p_socket, + lwip_buffer, + ip, + port); + + printf("dest: %02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x\n", + ip[0], ip[1], ip[2], ip[3], + ip[4], ip[5], ip[6], ip[7], + ip[8], ip[9], ip[10], ip[11], + ip[12], ip[13], ip[14], ip[15]); + + printf("port: %x\n", port); + printf("len: %d\n", len); + + if (err != ERR_OK) { + *_errno = err; + } + + return 0; +} + +STATIC mp_uint_t ble_6lowpan_socket_recvfrom(mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, byte *ip, mp_uint_t *port, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +STATIC int ble_6lowpan_socket_setsockopt(mod_network_socket_obj_t *socket, mp_uint_t level, mp_uint_t opt, const void *optval, mp_uint_t optlen, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +STATIC int ble_6lowpan_socket_settimeout(mod_network_socket_obj_t *socket, mp_uint_t timeout_ms, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +STATIC int ble_6lowpan_socket_ioctl(mod_network_socket_obj_t *socket, mp_uint_t request, mp_uint_t arg, int *_errno) { + *_errno = MP_EINVAL; + return -1; +} + +#include "sdkhelp.h" + +/******************************************************************************/ +// Micro Python bindings + +/// \classmethod \constructor +/// Create and return a BLE 6LoWPAN object. +STATIC mp_obj_t ble_6lowpan_make_new(const mp_obj_type_t *type, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) { + // check arguments + //mp_arg_check_num(n_args, n_kw, 0, 0, false); + + // init the BLE 6lowpan object + ble_6lowpan_obj.base.type = (mp_obj_type_t*)&mod_network_nic_type_ble_6lowpan; + + // blocking call to wait for connection with peer. + transport_init(); + + // regiser NIC with network module + mod_network_register_nic(&ble_6lowpan_obj); + + // return BLE 6LoWPAN object + return &ble_6lowpan_obj; +} + +const mod_network_nic_type_t mod_network_nic_type_ble_6lowpan = { + .base = { + { &mp_type_type }, + .name = MP_QSTR_BLE6LOWPAN, + .make_new = ble_6lowpan_make_new, + }, + .gethostbyname = ble_6lowpan_gethostbyname, + .socket = ble_6lowpan_socket_socket, + .close = ble_6lowpan_socket_close, + .bind = ble_6lowpan_socket_bind, + .listen = ble_6lowpan_socket_listen, + .accept = ble_6lowpan_socket_accept, + .connect = ble_6lowpan_socket_connect, + .send = ble_6lowpan_socket_send, + .recv = ble_6lowpan_socket_recv, + .sendto = ble_6lowpan_socket_sendto, + .recvfrom = ble_6lowpan_socket_recvfrom, + .setsockopt = ble_6lowpan_socket_setsockopt, + .settimeout = ble_6lowpan_socket_settimeout, + .ioctl = ble_6lowpan_socket_ioctl, +}; + +#endif diff --git a/nrf5/sdk/iot_0.9.0/sdk.mk b/nrf5/sdk/iot_0.9.0/sdk.mk new file mode 100644 index 0000000000..81be3000cc --- /dev/null +++ b/nrf5/sdk/iot_0.9.0/sdk.mk @@ -0,0 +1,12 @@ + +INC += -I./$(SDK_MODULES_PATH) + +include $(SDK_MODULES_PATH)build.mk + +INC += -I$(SDK_ROOT)components/softdevice/s1xx_iot/headers +INC += -I$(SDK_ROOT)components/softdevice/s1xx_iot/headers/nrf52 +CFLAGS += -DBLUETOOTH_SD=100 +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 + +# softdevice .hex file +SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s1xx_iot/hex/s1xx*softdevice.hex)) diff --git a/nrf5/sdk/iot_0.9.0/sdk_config.h b/nrf5/sdk/iot_0.9.0/sdk_config.h new file mode 100644 index 0000000000..fa851f540f --- /dev/null +++ b/nrf5/sdk/iot_0.9.0/sdk_config.h @@ -0,0 +1,46 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SDK_CONFIG_H__ +#define SDK_CONFIG_H__ + +#define MEMORY_MANAGER_SMALL_BLOCK_COUNT (8) +#define MEMORY_MANAGER_SMALL_BLOCK_SIZE (128) +#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT (4) +#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE (256) +#define MEMORY_MANAGER_LARGE_BLOCK_COUNT (3) +#define MEMORY_MANAGER_LARGE_BLOCK_SIZE (1024) +#define MEM_MANAGER_ENABLE_LOGS (0) +#define MEM_MANAGER_DISABLE_API_PARAM_CHECK (0) +#define IOT_CONTEXT_MANAGER_ENABLE_LOGS (0) +#define IOT_CONTEXT_MANAGER_DISABLE_API_PARAM_CHECK (0) +#define IOT_CONTEXT_MANAGER_MAX_CONTEXTS (16) +#define IOT_CONTEXT_MANAGER_MAX_TABLES (1) +#define NRF_LWIP_DRIVER_ENABLE_LOGS (0) +#define IOT_TIMER_RESOLUTION_IN_MS (100) +#define IOT_TIMER_DISABLE_API_PARAM_CHECK (0) + +#endif // SDK_CONFIG_H__ diff --git a/nrf5/sdk/iot_0.9.0/sdkhelp.c b/nrf5/sdk/iot_0.9.0/sdkhelp.c new file mode 100644 index 0000000000..f3b1bf7991 --- /dev/null +++ b/nrf5/sdk/iot_0.9.0/sdkhelp.c @@ -0,0 +1,256 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "softdevice_handler.h" +#include "app_trace.h" +#include "app_timer_appsh.h" +#include "ble_advdata.h" +#include "ble_srv_common.h" +#include "ble_ipsp.h" +#include "ble_6lowpan.h" +#include "mem_manager.h" +#include "app_trace.h" +#include "lwip/init.h" +#include "lwip/inet6.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/netif.h" +#include "lwip/timers.h" +#include "nrf_platform_port.h" +#include "app_util_platform.h" +#include "ble_gap.h" +#include "sdkhelp.h" +#include "mpconfigport.h" +#include "app_timer_appsh.h" +#include "iot_timer.h" + +#include "iot_defines.h" + +eui64_t eui64_local_iid; + +bool m_interface_up = false; + +void nrf_driver_interface_up(void) +{ + // sys_check_timeouts(); + m_interface_up = true; +} + +void nrf_driver_interface_down(void) +{ + m_interface_up = false; +} + +#define DEVICE_NAME "MPY_IPv6" +#define APP_ADV_TIMEOUT (0) // disable timeout +#define APP_ADV_ADV_INTERVAL MSEC_TO_UNITS(333, UNIT_0_625_MS) +#define IOT_TIMER_RESOLUTION_IN_MS 100 +#define LWIP_SYS_TICK_MS 100 +#define APP_TIMER_PRESCALER 31 // Value of the RTC1 PRESCALER register. */ +#define APP_TIMER_MAX_TIMERS 1 +#define APP_TIMER_OP_QUEUE_SIZE 5 + +APP_TIMER_DEF(m_iot_timer_tick_src_id); + +static ble_gap_adv_params_t m_adv_params; +static ble_gap_addr_t m_local_ble_addr; + +static void app_lwip_time_tick(iot_timer_time_in_ms_t wall_clock_value) +{ + sys_check_timeouts(); +} + +static void iot_timer_init(void) +{ + uint32_t err_code; + + static const iot_timer_client_t list_of_clients[] = + { + {app_lwip_time_tick, LWIP_SYS_TICK_MS} + }; + + // The list of IoT Timer clients is declared as a constant. + static const iot_timer_clients_list_t iot_timer_clients = + { + (sizeof(list_of_clients) / sizeof(iot_timer_client_t)), + &(list_of_clients[0]), + }; + + // Passing the list of clients to the IoT Timer module. + err_code = iot_timer_client_list_set(&iot_timer_clients); + APP_ERROR_CHECK(err_code); + + // Starting the app timer instance that is the tick source for the IoT Timer. + err_code = app_timer_start(m_iot_timer_tick_src_id, \ + APP_TIMER_TICKS(IOT_TIMER_RESOLUTION_IN_MS, APP_TIMER_PRESCALER), \ + NULL); + APP_ERROR_CHECK(err_code); +} + +static void iot_timer_tick_callback(void * p_context) +{ + UNUSED_VARIABLE(p_context); + uint32_t err_code = iot_timer_update(); + APP_ERROR_CHECK(err_code); +} + +static void timers_init(void) +{ + uint32_t err_code; + + // Initialize timer module, making it use the scheduler + APP_TIMER_APPSH_INIT(APP_TIMER_PRESCALER, APP_TIMER_OP_QUEUE_SIZE, false); + + // Create a sys timer. + err_code = app_timer_create(&m_iot_timer_tick_src_id, + APP_TIMER_MODE_REPEATED, + iot_timer_tick_callback); + APP_ERROR_CHECK(err_code); +} + +static void on_ble_evt(ble_evt_t * p_ble_evt) +{ + switch (p_ble_evt->header.evt_id) + { + case BLE_GAP_EVT_CONNECTED: + break; + case BLE_GAP_EVT_DISCONNECTED: + sd_ble_gap_adv_start(&m_adv_params); + break; + default: + break; + } +} + +static void ble_evt_dispatch(ble_evt_t * p_ble_evt) +{ + ble_ipsp_evt_handler(p_ble_evt); + on_ble_evt(p_ble_evt); +} + +void transport_init(void) { + + // if interface is already up, return + if (m_interface_up) { + return; + } + + uint32_t err_code; + + timers_init(); + + // Initialize the SoftDevice handler module. + SOFTDEVICE_HANDLER_INIT(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, false); + printf("Softdevice init done\n"); + + // Enable BLE stack. + ble_enable_params_t ble_enable_params; + memset(&ble_enable_params, 0x00, sizeof(ble_enable_params)); + ble_enable_params.gatts_enable_params.attr_tab_size = BLE_GATTS_ATTR_TAB_SIZE_DEFAULT; + ble_enable_params.gatts_enable_params.service_changed = false; + err_code = sd_ble_enable(&ble_enable_params); + printf("Softdevice enable:" UINT_FMT "\n", (uint16_t)err_code); + + // Register with the SoftDevice handler module for BLE events. + err_code = softdevice_ble_evt_handler_set(ble_evt_dispatch); + printf("Softdevice evt handler set:" UINT_FMT "\n", (uint16_t)err_code); + APP_ERROR_CHECK(err_code); + + ble_advdata_t advdata; + uint8_t flags = BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED; + ble_gap_conn_sec_mode_t sec_mode; + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); + + err_code = sd_ble_gap_device_name_set(&sec_mode, + (const uint8_t *)DEVICE_NAME, + strlen(DEVICE_NAME)); + printf("Device name set:" UINT_FMT "\n", (uint16_t)err_code); + APP_ERROR_CHECK(err_code); + + err_code = sd_ble_gap_address_get(&m_local_ble_addr); + APP_ERROR_CHECK(err_code); + printf("GAP address get:" UINT_FMT "\n", (uint16_t)err_code); + + m_local_ble_addr.addr[5] = 0x00; + m_local_ble_addr.addr_type = BLE_GAP_ADDR_TYPE_PUBLIC; + + err_code = sd_ble_gap_address_set(BLE_GAP_ADDR_CYCLE_MODE_NONE, &m_local_ble_addr); + APP_ERROR_CHECK(err_code); + printf("GAP address set:" UINT_FMT "\n", (uint16_t)err_code); + IPV6_EUI64_CREATE_FROM_EUI48(eui64_local_iid.identifier, + m_local_ble_addr.addr, + m_local_ble_addr.addr_type); + + ble_uuid_t adv_uuids[] = + { + {BLE_UUID_IPSP_SERVICE, BLE_UUID_TYPE_BLE} + }; + + // build and set advertising data + memset(&advdata, 0, sizeof(advdata)); + + advdata.name_type = BLE_ADVDATA_FULL_NAME; + advdata.flags = flags; + advdata.uuids_complete.uuid_cnt = sizeof(adv_uuids) / sizeof(adv_uuids[0]); + advdata.uuids_complete.p_uuids = adv_uuids; + + err_code = ble_advdata_set(&advdata, NULL); + APP_ERROR_CHECK(err_code); + printf("Adv data set:" UINT_FMT "\n", (uint16_t)err_code); + // initialize advertising parameters (used when starting advertising) + memset(&m_adv_params, 0, sizeof(m_adv_params)); + + m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND; + m_adv_params.p_peer_addr = NULL; // undirected advertisement + m_adv_params.fp = BLE_GAP_ADV_FP_ANY; + m_adv_params.interval = APP_ADV_ADV_INTERVAL; + m_adv_params.timeout = APP_ADV_TIMEOUT; + + // initialize memory manager + err_code = nrf_mem_init(); + APP_ERROR_CHECK(err_code); + printf("mem init:" UINT_FMT "\n", (uint16_t)err_code); + // initialize lwip stack driver + err_code = nrf_driver_init(); + APP_ERROR_CHECK(err_code); + printf("driver init:" UINT_FMT "\n", (uint16_t)err_code); + // initialize lwip stack + lwip_init(); + printf("lwip init:" UINT_FMT "\n", (uint16_t)err_code); + + iot_timer_init(); + + printf("Starting adv:" UINT_FMT "\n", (uint16_t)err_code); + err_code = sd_ble_gap_adv_start(&m_adv_params); + + while (!m_interface_up) { + ; + } +} + diff --git a/nrf5/sdk/iot_0.9.0/sdkhelp.h b/nrf5/sdk/iot_0.9.0/sdkhelp.h new file mode 100644 index 0000000000..c3e8a122fb --- /dev/null +++ b/nrf5/sdk/iot_0.9.0/sdkhelp.h @@ -0,0 +1,27 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +void transport_init(void); diff --git a/nrf5/sdk/modble.c b/nrf5/sdk/modble.c index 80a113e077..07655b0f83 100644 --- a/nrf5/sdk/modble.c +++ b/nrf5/sdk/modble.c @@ -28,6 +28,8 @@ #include #include "py/runtime.h" +#if MICROPY_PY_BLE + #include "led.h" #include "mpconfigboard.h" #include "softdevice.h" @@ -36,7 +38,7 @@ /// Enable BLE softdevice. mp_obj_t ble_obj_enable(void) { printf("SoftDevice enabled\n"); - uint32_t err_code = softdevice_enable(); + uint32_t err_code = sd_enable(); if (err_code < 0) { // TODO: raise exception. } @@ -46,14 +48,14 @@ mp_obj_t ble_obj_enable(void) { /// \method disable() /// Disable BLE softdevice. mp_obj_t ble_obj_disable(void) { - softdevice_disable(); + sd_disable(); return mp_const_none; } /// \method enabled() /// Get state of whether the softdevice is enabled or not. mp_obj_t ble_obj_enabled(void) { - uint8_t is_enabled = softdevice_enabled(); + uint8_t is_enabled = sd_enabled(); mp_int_t enabled = is_enabled; return MP_OBJ_NEW_SMALL_INT(enabled); } @@ -61,14 +63,14 @@ mp_obj_t ble_obj_enabled(void) { /// \method address_print() /// Print device address. mp_obj_t ble_obj_address_print(void) { - softdevice_address_get(); + sd_address_get(); return mp_const_none; } /// \method advertise() /// Bluetooth Low Energy advertise. mp_obj_t ble_obj_advertise(void) { - softdevice_advertise(); + sd_advertise(); return mp_const_none; } @@ -94,3 +96,5 @@ const mp_obj_module_t ble_module = { .base = { &mp_type_module }, .globals = (mp_obj_dict_t*)&ble_module_globals, }; + +#endif // MICROPY_PY_BLE diff --git a/nrf5/sdk/nrf5_sdk_conf.h b/nrf5/sdk/nrf5_sdk_conf.h new file mode 100644 index 0000000000..ab256be1f3 --- /dev/null +++ b/nrf5/sdk/nrf5_sdk_conf.h @@ -0,0 +1,40 @@ +#ifndef NRF_SDK_CONF_H__ +#define NRF_SDK_CONF_H__ + +// SD specific configurations. + +#if (BLUETOOTH_SD == 100) + +#define MICROPY_PY_BLE (1) +#define MICROPY_PY_BLE_6LOWPAN (1) +#define MICROPY_PY_USOCKET (1) +#define MICROPY_PY_NETWORK (1) + +#elif (BLUETOOTH_SD == 110) + +#define MICROPY_PY_BLE (1) + +#elif (BLUETOOTH_SD == 132) + +#define MICROPY_PY_BLE (1) +#define MICROPY_PY_BLE_NUS (1) + +#else +#error "SD not supported" +#endif + +// Default defines. + +#ifndef MICROPY_PY_BLE_6LOWPAN +#define MICROPY_PY_BLE_6LOWPAN (0) +#endif + +#ifndef MICROPY_PY_BLE +#define MICROPY_PY_BLE (0) +#endif + +#ifndef MICROPY_PY_BLE_NUS +#define MICROPY_PY_BLE_NUS (0) +#endif + +#endif diff --git a/nrf5/sdk/sdk_10.0.0/sdk.mk b/nrf5/sdk/sdk_10.0.0/sdk.mk new file mode 100644 index 0000000000..a5097eabc9 --- /dev/null +++ b/nrf5/sdk/sdk_10.0.0/sdk.mk @@ -0,0 +1,17 @@ + +INC += -I./$(SDK_MODULES_PATH) + +# Nothing to build from SDK. +# include $(SDK_MODULES_PATH)build.mk + +INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 + +# softdevice .hex file +ifeq ($(SD), s110) +CFLAGS += -DBLUETOOTH_SD=110 +SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s110/hex/s110_nrf51_8.0.0_softdevice.hex)) +else ifeq ($(SD), s120) +CFLAGS += -DBLUETOOTH_SD=120 +SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s120/hex/s120_nrf51_2.1.0_softdevice.hex)) +endif \ No newline at end of file diff --git a/nrf5/sdk/sdk_12.1.0/build.mk b/nrf5/sdk/sdk_12.1.0/build.mk new file mode 100644 index 0000000000..e14ec76448 --- /dev/null +++ b/nrf5/sdk/sdk_12.1.0/build.mk @@ -0,0 +1,103 @@ +# this file's folder +SDK_DIR := $(SDK_ROOT) + +# -D in CFLAGS +DEFINES += __HEAP_SIZE=0 +DEFINES += BLE_STACK_SUPPORT_REQD +DEFINES += CONFIG_GPIO_AS_PINRESET +DEFINES += NRF52 +DEFINES += NRF52_PAN_12 +DEFINES += NRF52_PAN_15 +DEFINES += NRF52_PAN_20 +DEFINES += NRF52_PAN_30 +DEFINES += NRF52_PAN_31 +DEFINES += NRF52_PAN_36 +DEFINES += NRF52_PAN_51 +DEFINES += NRF52_PAN_53 +DEFINES += NRF52_PAN_54 +DEFINES += NRF52_PAN_55 +DEFINES += NRF52_PAN_58 +DEFINES += NRF52_PAN_62 +DEFINES += NRF52_PAN_63 +DEFINES += NRF52_PAN_64 +DEFINES += S132 +DEFINES += SOFTDEVICE_PRESENT +DEFINES += SWI_DISABLE0 +DEFINES += NRF_SD_BLE_API_VERSION=3 +DEFINES += PEER_MANAGER_ENABLED=1 +DEFINES += FDS_ENABLED=1 + +# nordic SDK C sources (relative path) +SDK_SRC_C += \ + components/ble/ble_advertising/ble_advertising.c \ + components/ble/ble_services/ble_nus/ble_nus.c \ + components/ble/common/ble_advdata.c \ + components/ble/common/ble_conn_params.c \ + components/ble/common/ble_conn_state.c \ + components/ble/common/ble_srv_common.c \ + components/ble/peer_manager/gatt_cache_manager.c \ + components/ble/peer_manager/gatts_cache_manager.c \ + components/ble/peer_manager/id_manager.c \ + components/ble/peer_manager/peer_data.c \ + components/ble/peer_manager/peer_data_storage.c \ + components/ble/peer_manager/peer_database.c \ + components/ble/peer_manager/peer_id.c \ + components/ble/peer_manager/peer_manager.c \ + components/ble/peer_manager/pm_buffer.c \ + components/ble/peer_manager/pm_mutex.c \ + components/ble/peer_manager/security_dispatcher.c \ + components/ble/peer_manager/security_manager.c \ + components/libraries/fds/fds.c \ + components/libraries/fifo/app_fifo.c \ + components/libraries/fstorage/fstorage.c \ + components/libraries/timer/app_timer.c \ + components/libraries/util/app_util_platform.c \ + components/libraries/util/sdk_mapped_flags.c \ + components/softdevice/common/softdevice_handler/softdevice_handler.c \ + components/drivers_nrf/clock/nrf_drv_clock.c \ + components/libraries/util/app_error.c \ + components/libraries/util/app_error_weak.c \ + components/drivers_nrf/common/nrf_drv_common.c + +# include source folders (sort removes duplicates) +SDK_INC_DIRS += $(sort $(dir $(SDK_SRC_C))) +#SDK_INC_DIRS += $(sort $(${SDK_ROOT} ${SDK_SRC_C})) +# ble.h +SDK_INC_DIRS += components/softdevice/s132/headers +# nrf52.h compiler_abstraction.h +SDK_INC_DIRS += components/device +# core_cm4.h +SDK_INC_DIRS += components/toolchain/CMSIS/Include +# section_vars.h +SDK_INC_DIRS += components/libraries/experimental_section_vars +# fstorage_config.h +SDK_INC_DIRS += components/libraries/fstorage/config +# nrf_drv_config.h +SDK_INC_DIRS += components/drivers_nrf/config +# app_util.h +SDK_INC_DIRS += components/libraries/util +# fds_config.h +SDK_INC_DIRS += components/libraries/fds/config +# nrf_log.h +SDK_INC_DIRS += components/libraries/log/ +# nrf_log_internal.h +SDK_INC_DIRS += components/libraries/log/src +# nrf_clock.h +SDK_INC_DIRS += components/drivers_nrf/hal +# nrf_drv_common.h +SDK_INC_DIRS += components/drivers_nrf/common +# nrf_delay.h +SDK_INC_DIRS += components/drivers_nrf/delay + +CFLAGS += $(patsubst %,-D%,${DEFINES}) + +# include full path +INC += $(patsubst %,-I${SDK_DIR}/%, ${SDK_INC_DIRS}) + +# additional SDK source files +SRC_C += $(addprefix ${SDK_ROOT}/, $(SDK_SRC_C)) + +# Wrappers +SRC_C += \ + $(SDK_MODULES_PATH)nrf52_ble.c \ + diff --git a/nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld b/nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld new file mode 100644 index 0000000000..094a8c45ca --- /dev/null +++ b/nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld @@ -0,0 +1,40 @@ +/* + GNU linker script for NRF52 w/ s132 3.0.0 SoftDevice +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x0001f000, LENGTH = 0x001000 /* sector 0, 4 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 /* 396 KiB */ + RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 57.89 KiB, give 8KiB headroom for softdevice */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 8K; +_minimum_heap_size = 8K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x200069c0; /* tunable */ + +__data_start__ = ORIGIN(RAM); + +SECTIONS +{ + .fs_data : + { + PROVIDE(__start_fs_data = .); + KEEP(*(.fs_data)) + PROVIDE(__stop_fs_data = .); + } > RAM +} INSERT AFTER .data; + + +INCLUDE "boards/common.ld" diff --git a/nrf5/sdk/sdk_12.1.0/nrf52_app_error.c b/nrf5/sdk/sdk_12.1.0/nrf52_app_error.c new file mode 100644 index 0000000000..5775a3e3a3 --- /dev/null +++ b/nrf5/sdk/sdk_12.1.0/nrf52_app_error.c @@ -0,0 +1,19 @@ +#include +#include "app_error.h" + + +void +#ifdef DEBUG +app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) +#else +app_error_handler_bare(ret_code_t error_code) +#endif +{ +#ifdef DEBUG + for (;;) { + /* FOREVER */ + } +#else + NVIC_SystemReset(); +#endif +} diff --git a/nrf5/sdk/sdk_12.1.0/nrf52_ble.c b/nrf5/sdk/sdk_12.1.0/nrf52_ble.c new file mode 100644 index 0000000000..abaec5eac4 --- /dev/null +++ b/nrf5/sdk/sdk_12.1.0/nrf52_ble.c @@ -0,0 +1,487 @@ +#include "nrf52_ble.h" +#include "nrf52_board.h" + +#include "sdk_config.h" +#include "app_error.h" +#include "app_fifo.h" +#include "app_timer.h" +#include "ble_advertising.h" +#include "ble_conn_params.h" +#include "ble_conn_state.h" +#include "ble_hci.h" +#include "ble_nus.h" +#include "ble_srv_common.h" +#include "fds.h" +#include "fstorage.h" +#include "peer_manager.h" +#include "softdevice_handler.h" + +#define CENTRAL_LINK_COUNT 0 /**< Number of central links used by the application. When changing this number remember to adjust the RAM settings*/ +#define PERIPHERAL_LINK_COUNT 1 /**< Number of peripheral links used by the application. When changing this number remember to adjust the RAM settings*/ + +#define DEVICE_NAME "micropython" + +#define MIN_CONN_INTERVAL MSEC_TO_UNITS(20, UNIT_1_25_MS) /**< Minimum acceptable connection interval (0.02 seconds). */ +#define MAX_CONN_INTERVAL MSEC_TO_UNITS(200, UNIT_1_25_MS) /**< Maximum acceptable connection interval (0.2 second). */ +#define SLAVE_LATENCY 0 /**< Slave latency. */ +#define CONN_SUP_TIMEOUT MSEC_TO_UNITS(3000, UNIT_10_MS) /**< Connection supervisory timeout (3 seconds). */ + +#define APP_ADV_INTERVAL MSEC_TO_UNITS(25, UNIT_0_625_MS) +#define APP_ADV_TIMEOUT_IN_SECONDS 180 + +#define APP_TIMER_PRESCALER 0 /**< Value of the RTC1 PRESCALER register. */ +#define APP_TIMER_OP_QUEUE_SIZE 4 /**< Size of timer operation queues. */ + +#define FIRST_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(5000, APP_TIMER_PRESCALER) /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (5 seconds). */ +#define NEXT_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(30000, APP_TIMER_PRESCALER) /**< Time between each call to sd_ble_gap_conn_param_update after the first call (30 seconds). */ +#define MAX_CONN_PARAMS_UPDATE_COUNT 3 + +#define SEC_PARAM_BOND 1 /**< Perform bonding. */ +#define SEC_PARAM_MITM 0 /**< Man In The Middle protection not required. */ +#define SEC_PARAM_LESC 0 /**< LE Secure Connections not enabled. */ +#define SEC_PARAM_KEYPRESS 0 /**< Keypress notifications not enabled. */ +#define SEC_PARAM_IO_CAPABILITIES BLE_GAP_IO_CAPS_NONE /**< No I/O capabilities. */ +#define SEC_PARAM_OOB 0 /**< Out Of Band data not available. */ +#define SEC_PARAM_MIN_KEY_SIZE 7 /**< Minimum encryption key size. */ +#define SEC_PARAM_MAX_KEY_SIZE 16 /**< Maximum encryption key size. */ + +#define NUS_RX_FIFO_BUFFER_SIZE 64 + +static ble_uuid_t m_adv_uuids[] = {{BLE_UUID_NUS_SERVICE, 0}}; /**< Universally unique service identifiers. */ + +static ble_nus_t m_nus; +static app_fifo_t m_nus_rx_fifo; +static uint8_t m_nus_rx_fifo_buffer[NUS_RX_FIFO_BUFFER_SIZE]; + + +static void +ble_evt_dispatch(ble_evt_t * p_ble_evt) +{ + ble_conn_state_on_ble_evt(p_ble_evt); + pm_on_ble_evt(p_ble_evt); + ble_conn_params_on_ble_evt(p_ble_evt); + ble_advertising_on_ble_evt(p_ble_evt); + ble_nus_on_ble_evt(&m_nus, p_ble_evt); +} + +static void +sys_evt_dispatch(uint32_t sys_evt) +{ + fs_sys_event_handler(sys_evt); + ble_advertising_on_sys_evt(sys_evt); +} + +static void +ble_stack_init(void) +{ + nrf_clock_lf_cfg_t clock_lf_cfg = NRF_CLOCK_LFCLKSRC; + + // Initialize the SoftDevice handler module. + SOFTDEVICE_HANDLER_INIT(&clock_lf_cfg, NULL); + + ble_enable_params_t ble_enable_params; + uint32_t err_code = softdevice_enable_get_default_config(CENTRAL_LINK_COUNT, + PERIPHERAL_LINK_COUNT, + &ble_enable_params); + APP_ERROR_CHECK(err_code); + + //Check the ram settings against the used number of links + CHECK_RAM_START_ADDR(CENTRAL_LINK_COUNT, PERIPHERAL_LINK_COUNT); + + // Enable BLE stack. + err_code = softdevice_enable(&ble_enable_params); + APP_ERROR_CHECK(err_code); + + // Register with the SoftDevice handler module for BLE events. + err_code = softdevice_ble_evt_handler_set(ble_evt_dispatch); + APP_ERROR_CHECK(err_code); + + // Register with the SoftDevice handler module for BLE events. + err_code = softdevice_sys_evt_handler_set(sys_evt_dispatch); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for the GAP initialization. + * + * @details This function sets up all the necessary GAP (Generic Access Profile) parameters of the + * device including the device name, appearance, and the preferred connection parameters. + */ +static void +gap_params_init(void) +{ + uint32_t err_code; + ble_gap_conn_params_t gap_conn_params; + ble_gap_conn_sec_mode_t sec_mode; + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); + + err_code = sd_ble_gap_device_name_set(&sec_mode, + (const uint8_t *)DEVICE_NAME, + strlen(DEVICE_NAME)); + APP_ERROR_CHECK(err_code); + + err_code = sd_ble_gap_appearance_set(BLE_APPEARANCE_UNKNOWN); + APP_ERROR_CHECK(err_code); + + memset(&gap_conn_params, 0, sizeof(gap_conn_params)); + + gap_conn_params.min_conn_interval = MIN_CONN_INTERVAL; + gap_conn_params.max_conn_interval = MAX_CONN_INTERVAL; + gap_conn_params.slave_latency = SLAVE_LATENCY; + gap_conn_params.conn_sup_timeout = CONN_SUP_TIMEOUT; + + err_code = sd_ble_gap_ppcp_set(&gap_conn_params); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for handling advertising events. + * + * @details This function will be called for advertising events which are passed to the application. + * + * @param[in] ble_adv_evt Advertising event. + */ +static void +on_adv_evt(ble_adv_evt_t ble_adv_evt) +{ + switch (ble_adv_evt) + { + case BLE_ADV_EVT_FAST: + break; + case BLE_ADV_EVT_IDLE: + break; + default: + break; + } +} + +/**@brief Function for initializing the Advertising functionality. + */ +static void +advertising_init(void) +{ + uint32_t err_code; + ble_advdata_t advdata; + + // Build advertising data struct to pass into @ref ble_advertising_init. + memset(&advdata, 0, sizeof(advdata)); + + advdata.name_type = BLE_ADVDATA_FULL_NAME; + advdata.include_appearance = true; + advdata.flags = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE; + advdata.uuids_complete.uuid_cnt = sizeof(m_adv_uuids) / sizeof(m_adv_uuids[0]); + advdata.uuids_complete.p_uuids = m_adv_uuids; + + ble_adv_modes_config_t options = {0}; + options.ble_adv_fast_enabled = true; + options.ble_adv_fast_interval = APP_ADV_INTERVAL; + options.ble_adv_fast_timeout = APP_ADV_TIMEOUT_IN_SECONDS; + + err_code = ble_advertising_init(&advdata, NULL, &options, on_adv_evt, NULL); + APP_ERROR_CHECK(err_code); +} + +static void +nus_data_handler(ble_nus_t * p_nus, uint8_t * p_data, uint16_t length) +{ + for (uint32_t i = 0; i < length; i++) { + // XXX + app_fifo_put(&m_nus_rx_fifo, p_data[i]); + } +} + +static void +services_init(void) +{ + uint32_t err_code; + ble_nus_init_t nus_init = {0}; + nus_init.data_handler = nus_data_handler; + err_code = ble_nus_init(&m_nus, &nus_init); + APP_ERROR_CHECK(err_code); + + m_adv_uuids[0].type = m_nus.uuid_type; + + err_code = app_fifo_init(&m_nus_rx_fifo, m_nus_rx_fifo_buffer, NUS_RX_FIFO_BUFFER_SIZE); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for handling a Connection Parameters error. + * + * @param[in] nrf_error Error code containing information about what went wrong. + */ +static void conn_params_error_handler(uint32_t nrf_error) +{ + APP_ERROR_HANDLER(nrf_error); +} + +/**@brief Function for initializing the Connection Parameters module. + */ +static void +conn_params_init(void) +{ + uint32_t err_code; + ble_conn_params_init_t cp_init; + + memset(&cp_init, 0, sizeof(cp_init)); + + cp_init.p_conn_params = NULL; + cp_init.first_conn_params_update_delay = FIRST_CONN_PARAMS_UPDATE_DELAY; + cp_init.next_conn_params_update_delay = NEXT_CONN_PARAMS_UPDATE_DELAY; + cp_init.max_conn_params_update_count = MAX_CONN_PARAMS_UPDATE_COUNT; + cp_init.start_on_notify_cccd_handle = BLE_GATT_HANDLE_INVALID; + cp_init.disconnect_on_fail = true; + cp_init.evt_handler = NULL; + cp_init.error_handler = conn_params_error_handler; + + err_code = ble_conn_params_init(&cp_init); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for starting advertising. + */ +static void +advertising_start(void) +{ + uint32_t err_code = ble_advertising_start(BLE_ADV_MODE_FAST); + APP_ERROR_CHECK(err_code); +} + +/**@brief Function for handling Peer Manager events. + * + * @param[in] p_evt Peer Manager event. + */ +static void +pm_evt_handler(pm_evt_t const * p_evt) +{ + ret_code_t err_code; + + switch(p_evt->evt_id) + { + case PM_EVT_BONDED_PEER_CONNECTED: + err_code = pm_peer_rank_highest(p_evt->peer_id); + if (err_code != NRF_ERROR_BUSY) + { + APP_ERROR_CHECK(err_code); + } + break;//PM_EVT_BONDED_PEER_CONNECTED + + case PM_EVT_CONN_SEC_START: + break;//PM_EVT_CONN_SEC_START + + case PM_EVT_CONN_SEC_SUCCEEDED: + { + /* + NRF_LOG_PRINTF_DEBUG("Link secured. Role: %d. conn_handle: %d, Procedure: %d\r\n", + ble_conn_state_role(p_evt->conn_handle), + p_evt->conn_handle, + p_evt->params.conn_sec_succeeded.procedure); + */ + err_code = pm_peer_rank_highest(p_evt->peer_id); + if (err_code != NRF_ERROR_BUSY) + { + APP_ERROR_CHECK(err_code); + } + } + break;//PM_EVT_CONN_SEC_SUCCEEDED + + case PM_EVT_CONN_SEC_FAILED: + { + /** In some cases, when securing fails, it can be restarted directly. Sometimes it can + * be restarted, but only after changing some Security Parameters. Sometimes, it cannot + * be restarted until the link is disconnected and reconnected. Sometimes it is + * impossible, to secure the link, or the peer device does not support it. How to + * handle this error is highly application dependent. */ + switch (p_evt->params.conn_sec_failed.error) + { + case PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING: + // Rebond if one party has lost its keys. + err_code = pm_conn_secure(p_evt->conn_handle, true); + if (err_code != NRF_ERROR_INVALID_STATE) + { + APP_ERROR_CHECK(err_code); + } + break;//PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING + + default: + break; + } + } + break;//PM_EVT_CONN_SEC_FAILED + + case PM_EVT_CONN_SEC_CONFIG_REQ: + { + // Reject pairing request from an already bonded peer. + pm_conn_sec_config_t conn_sec_config = {.allow_repairing = false}; + pm_conn_sec_config_reply(p_evt->conn_handle, &conn_sec_config); + } + break;//PM_EVT_CONN_SEC_CONFIG_REQ + + case PM_EVT_STORAGE_FULL: + { + // Run garbage collection on the flash. + err_code = fds_gc(); + if (err_code == FDS_ERR_BUSY || err_code == FDS_ERR_NO_SPACE_IN_QUEUES) + { + // Retry. + } + else + { + APP_ERROR_CHECK(err_code); + } + } + break;//PM_EVT_STORAGE_FULL + + case PM_EVT_ERROR_UNEXPECTED: + // Assert. + APP_ERROR_CHECK(p_evt->params.error_unexpected.error); + break;//PM_EVT_ERROR_UNEXPECTED + + case PM_EVT_PEER_DATA_UPDATE_SUCCEEDED: + break;//PM_EVT_PEER_DATA_UPDATE_SUCCEEDED + + case PM_EVT_PEER_DATA_UPDATE_FAILED: + // Assert. + APP_ERROR_CHECK_BOOL(false); + break;//PM_EVT_PEER_DATA_UPDATE_FAILED + + case PM_EVT_PEER_DELETE_SUCCEEDED: + break;//PM_EVT_PEER_DELETE_SUCCEEDED + + case PM_EVT_PEER_DELETE_FAILED: + // Assert. + APP_ERROR_CHECK(p_evt->params.peer_delete_failed.error); + break;//PM_EVT_PEER_DELETE_FAILED + + case PM_EVT_PEERS_DELETE_SUCCEEDED: + advertising_start(); + break;//PM_EVT_PEERS_DELETE_SUCCEEDED + + case PM_EVT_PEERS_DELETE_FAILED: + // Assert. + APP_ERROR_CHECK(p_evt->params.peers_delete_failed_evt.error); + break;//PM_EVT_PEERS_DELETE_FAILED + + case PM_EVT_LOCAL_DB_CACHE_APPLIED: + break;//PM_EVT_LOCAL_DB_CACHE_APPLIED + + case PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED: + // The local database has likely changed, send service changed indications. + pm_local_database_has_changed(); + break;//PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED + + case PM_EVT_SERVICE_CHANGED_IND_SENT: + break;//PM_EVT_SERVICE_CHANGED_IND_SENT + + case PM_EVT_SERVICE_CHANGED_IND_CONFIRMED: + break;//PM_EVT_SERVICE_CHANGED_IND_CONFIRMED + + default: + // No implementation needed. + break; + } +} + +static void +peer_manager_init(bool erase_bonds) +{ + ble_gap_sec_params_t sec_param; + ret_code_t err_code; + + err_code = pm_init(); + APP_ERROR_CHECK(err_code); + + if (erase_bonds) + { + err_code = pm_peers_delete(); + APP_ERROR_CHECK(err_code); + } + + memset(&sec_param, 0, sizeof(ble_gap_sec_params_t)); + + // Security parameters to be used for all security procedures. + sec_param.bond = SEC_PARAM_BOND; + sec_param.mitm = SEC_PARAM_MITM; + sec_param.lesc = SEC_PARAM_LESC; + sec_param.keypress = SEC_PARAM_KEYPRESS; + sec_param.io_caps = SEC_PARAM_IO_CAPABILITIES; + sec_param.oob = SEC_PARAM_OOB; + sec_param.min_key_size = SEC_PARAM_MIN_KEY_SIZE; + sec_param.max_key_size = SEC_PARAM_MAX_KEY_SIZE; + sec_param.kdist_own.enc = 1; + sec_param.kdist_own.id = 1; + sec_param.kdist_peer.enc = 1; + sec_param.kdist_peer.id = 1; + + err_code = pm_sec_params_set(&sec_param); + APP_ERROR_CHECK(err_code); + + err_code = pm_register(pm_evt_handler); + APP_ERROR_CHECK(err_code); +} + +static void +timers_init() +{ + APP_TIMER_INIT(APP_TIMER_PRESCALER, APP_TIMER_OP_QUEUE_SIZE, false); +} + +void +nrf52_ble_init(void) +{ + fds_init(); + fs_init(); + timers_init(); + ble_stack_init(); + ble_conn_state_init(); + peer_manager_init(false); + gap_params_init(); + services_init(); + advertising_init(); + conn_params_init(); + + (void)ble_advertising_start(BLE_ADV_MODE_FAST); + + +} + +static void +power_manage() +{ + uint32_t err_code = sd_app_evt_wait(); + APP_ERROR_CHECK(err_code); +} + +// ########################### MP IO functions ########################### + +void +mp_hal_stdout_tx_strn(const char *str, size_t len) +{ + uint32_t err_code; + uint8_t *buf = (uint8_t *)str; + size_t send_len; + + while (len > 0) { + if (len >= BLE_NUS_MAX_DATA_LEN) + send_len = BLE_NUS_MAX_DATA_LEN; + else + send_len = len; + err_code = ble_nus_string_send(&m_nus, buf, send_len); + if (err_code == NRF_SUCCESS) { + len -= send_len; + buf += send_len; + } else if (err_code != NRF_ERROR_INVALID_STATE) { + APP_ERROR_CHECK(err_code); + } + } +} + +int +mp_hal_stdin_rx_chr() +{ + uint8_t byte; + for (;;) { + if (app_fifo_get(&m_nus_rx_fifo, &byte) == NRF_SUCCESS) { + return byte; + } + power_manage(); + } +} diff --git a/nrf5/sdk/sdk_12.1.0/nrf52_ble.h b/nrf5/sdk/sdk_12.1.0/nrf52_ble.h new file mode 100644 index 0000000000..26f9d86400 --- /dev/null +++ b/nrf5/sdk/sdk_12.1.0/nrf52_ble.h @@ -0,0 +1,4 @@ +#pragma once + + +void nrf52_ble_init(void); diff --git a/nrf5/sdk/sdk_12.1.0/nrf52_board.h b/nrf5/sdk/sdk_12.1.0/nrf52_board.h new file mode 100644 index 0000000000..8d20b72844 --- /dev/null +++ b/nrf5/sdk/sdk_12.1.0/nrf52_board.h @@ -0,0 +1,9 @@ +#pragma once + +#include "nrf_sdm.h" + +// Low frequency clock source to be used by the SoftDevice +#define NRF_CLOCK_LFCLKSRC {.source = NRF_CLOCK_LF_SRC_XTAL, \ + .rc_ctiv = 0, \ + .rc_temp_ctiv = 0, \ + .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM} diff --git a/nrf5/sdk/sdk_12.1.0/sdk.mk b/nrf5/sdk/sdk_12.1.0/sdk.mk new file mode 100644 index 0000000000..2c744f013d --- /dev/null +++ b/nrf5/sdk/sdk_12.1.0/sdk.mk @@ -0,0 +1,19 @@ + +INC += -I./$(SDK_MODULES_PATH) + +include $(SDK_MODULES_PATH)build.mk + +INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers +INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers/$(MCU_VARIANT) +CFLAGS += -DBLUETOOTH_SD_DEBUG=1 + +# softdevice .hex file +ifeq ($(SD), s130) +CFLAGS += -DBLUETOOTH_SD=130 +SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s130/hex/s130_nrf51_2.0.1_softdevice.hex)) +else ifeq ($(SD), s132) +CFLAGS += -DBLUETOOTH_SD=132 +SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s132/hex/s132_nrf52_3.0.0_softdevice.hex)) +# Update to local linker file, special linking has to be done +LD_FILE := $(SDK_MODULES_PATH)nrf52832_aa_s132.ld +endif diff --git a/nrf5/sdk/sdk_12.1.0/sdk_config.h b/nrf5/sdk/sdk_12.1.0/sdk_config.h new file mode 100644 index 0000000000..fa78d17e3e --- /dev/null +++ b/nrf5/sdk/sdk_12.1.0/sdk_config.h @@ -0,0 +1,2299 @@ + + +#ifndef SDK_CONFIG_H +#define SDK_CONFIG_H +// <<< Use Configuration Wizard in Context Menu >>>\n +#ifdef USE_APP_CONFIG +#include "app_config.h" +#endif +// nRF_BLE + +//========================================================== +// BLE_ADVERTISING_ENABLED - ble_advertising - Advertising module + + +#ifndef BLE_ADVERTISING_ENABLED +#define BLE_ADVERTISING_ENABLED 1 +#endif + +// BLE_DTM_ENABLED - ble_dtm - Module for testing RF/PHY using DTM commands + + +#ifndef BLE_DTM_ENABLED +#define BLE_DTM_ENABLED 0 +#endif + +// BLE_RACP_ENABLED - ble_racp - Record Access Control Point library + + +#ifndef BLE_RACP_ENABLED +#define BLE_RACP_ENABLED 0 +#endif + +// NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write) + + +#ifndef NRF_BLE_QWR_ENABLED +#define NRF_BLE_QWR_ENABLED 0 +#endif + +// PEER_MANAGER_ENABLED - peer_manager - Peer Manager + + +#ifndef PEER_MANAGER_ENABLED +#define PEER_MANAGER_ENABLED 1 +#endif + +// +//========================================================== + +// nRF_BLE_Services + +//========================================================== +// BLE_ANCS_C_ENABLED - ble_ancs_c - Apple Notification Service Client + + +#ifndef BLE_ANCS_C_ENABLED +#define BLE_ANCS_C_ENABLED 0 +#endif + +// BLE_ANS_C_ENABLED - ble_ans_c - Alert Notification Service Client + + +#ifndef BLE_ANS_C_ENABLED +#define BLE_ANS_C_ENABLED 0 +#endif + +// BLE_BAS_C_ENABLED - ble_bas_c - Battery Service Client + + +#ifndef BLE_BAS_C_ENABLED +#define BLE_BAS_C_ENABLED 0 +#endif + +// BLE_BAS_ENABLED - ble_bas - Battery Service + + +#ifndef BLE_BAS_ENABLED +#define BLE_BAS_ENABLED 0 +#endif + +// BLE_CSCS_ENABLED - ble_cscs - Cycling Speed and Cadence Service + + +#ifndef BLE_CSCS_ENABLED +#define BLE_CSCS_ENABLED 0 +#endif + +// BLE_CTS_C_ENABLED - ble_cts_c - Current Time Service Client + + +#ifndef BLE_CTS_C_ENABLED +#define BLE_CTS_C_ENABLED 0 +#endif + +// BLE_DIS_ENABLED - ble_dis - Device Information Service + + +#ifndef BLE_DIS_ENABLED +#define BLE_DIS_ENABLED 0 +#endif + +// BLE_GLS_ENABLED - ble_gls - Glucose Service + + +#ifndef BLE_GLS_ENABLED +#define BLE_GLS_ENABLED 0 +#endif + +// BLE_HIDS_ENABLED - ble_hids - Human Interface Device Service + + +#ifndef BLE_HIDS_ENABLED +#define BLE_HIDS_ENABLED 0 +#endif + +// BLE_HRS_C_ENABLED - ble_hrs_c - Heart Rate Service Client + + +#ifndef BLE_HRS_C_ENABLED +#define BLE_HRS_C_ENABLED 0 +#endif + +// BLE_HRS_ENABLED - ble_hrs - Heart Rate Service + + +#ifndef BLE_HRS_ENABLED +#define BLE_HRS_ENABLED 0 +#endif + +// BLE_HTS_ENABLED - ble_hts - Health Thermometer Service + + +#ifndef BLE_HTS_ENABLED +#define BLE_HTS_ENABLED 0 +#endif + +// BLE_IAS_C_ENABLED - ble_ias_c - Immediate Alert Service Client + + +#ifndef BLE_IAS_C_ENABLED +#define BLE_IAS_C_ENABLED 0 +#endif + +// BLE_IAS_ENABLED - ble_ias - Immediate Alert Service + + +#ifndef BLE_IAS_ENABLED +#define BLE_IAS_ENABLED 0 +#endif + +// BLE_LBS_C_ENABLED - ble_lbs_c - Nordic LED Button Service Client + + +#ifndef BLE_LBS_C_ENABLED +#define BLE_LBS_C_ENABLED 0 +#endif + +// BLE_LBS_ENABLED - ble_lbs - LED Button Service + + +#ifndef BLE_LBS_ENABLED +#define BLE_LBS_ENABLED 0 +#endif + +// BLE_LLS_ENABLED - ble_lls - Link Loss Service + + +#ifndef BLE_LLS_ENABLED +#define BLE_LLS_ENABLED 0 +#endif + +// BLE_NUS_C_ENABLED - ble_nus_c - Nordic UART Central Service + + +#ifndef BLE_NUS_C_ENABLED +#define BLE_NUS_C_ENABLED 0 +#endif + +// BLE_NUS_ENABLED - ble_nus - Nordic UART Service + + +#ifndef BLE_NUS_ENABLED +#define BLE_NUS_ENABLED 1 +#endif + +// BLE_RSCS_C_ENABLED - ble_rscs_c - Running Speed and Cadence Client + + +#ifndef BLE_RSCS_C_ENABLED +#define BLE_RSCS_C_ENABLED 0 +#endif + +// BLE_RSCS_ENABLED - ble_rscs - Running Speed and Cadence Service + + +#ifndef BLE_RSCS_ENABLED +#define BLE_RSCS_ENABLED 0 +#endif + +// BLE_TPS_ENABLED - ble_tps - TX Power Service + + +#ifndef BLE_TPS_ENABLED +#define BLE_TPS_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Drivers + +//========================================================== +// ADC_ENABLED - nrf_drv_adc - Driver for ADC peripheral (nRF51) +//========================================================== +#ifndef ADC_ENABLED +#define ADC_ENABLED 0 +#endif +#if ADC_ENABLED +// ADC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef ADC_CONFIG_IRQ_PRIORITY +#define ADC_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //ADC_ENABLED +// + +// CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver +//========================================================== +#ifndef CLOCK_ENABLED +#define CLOCK_ENABLED 1 +#endif +#if CLOCK_ENABLED +// CLOCK_CONFIG_XTAL_FREQ - HF XTAL Frequency + +// <0=> Default (64 MHz) + +#ifndef CLOCK_CONFIG_XTAL_FREQ +#define CLOCK_CONFIG_XTAL_FREQ 0 +#endif + +// CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth + +#ifndef CLOCK_CONFIG_LF_SRC +#define CLOCK_CONFIG_LF_SRC 1 +#endif + +// CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef CLOCK_CONFIG_IRQ_PRIORITY +#define CLOCK_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //CLOCK_ENABLED +// + +// COMP_ENABLED - nrf_drv_comp - COMP peripheral driver +//========================================================== +#ifndef COMP_ENABLED +#define COMP_ENABLED 0 +#endif +#if COMP_ENABLED +// COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef COMP_CONFIG_REF +#define COMP_CONFIG_REF 1 +#endif + +// COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef COMP_CONFIG_MAIN_MODE +#define COMP_CONFIG_MAIN_MODE 0 +#endif + +// COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef COMP_CONFIG_SPEED_MODE +#define COMP_CONFIG_SPEED_MODE 2 +#endif + +// COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef COMP_CONFIG_HYST +#define COMP_CONFIG_HYST 0 +#endif + +// COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef COMP_CONFIG_ISOURCE +#define COMP_CONFIG_ISOURCE 0 +#endif + +// COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef COMP_CONFIG_INPUT +#define COMP_CONFIG_INPUT 0 +#endif + +// COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef COMP_CONFIG_IRQ_PRIORITY +#define COMP_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //COMP_ENABLED +// + +// EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver + + +#ifndef EGU_ENABLED +#define EGU_ENABLED 0 +#endif + +// GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver +//========================================================== +#ifndef GPIOTE_ENABLED +#define GPIOTE_ENABLED 1 +#endif +#if GPIOTE_ENABLED +// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4 +#endif + +// GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef GPIOTE_CONFIG_IRQ_PRIORITY +#define GPIOTE_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //GPIOTE_ENABLED +// + +// I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver +//========================================================== +#ifndef I2S_ENABLED +#define I2S_ENABLED 0 +#endif +#if I2S_ENABLED +// I2S_CONFIG_SCK_PIN - SCK pin <0-31> + + +#ifndef I2S_CONFIG_SCK_PIN +#define I2S_CONFIG_SCK_PIN 31 +#endif + +// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> + + +#ifndef I2S_CONFIG_LRCK_PIN +#define I2S_CONFIG_LRCK_PIN 30 +#endif + +// I2S_CONFIG_MCK_PIN - MCK pin +#ifndef I2S_CONFIG_MCK_PIN +#define I2S_CONFIG_MCK_PIN 255 +#endif + +// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> + + +#ifndef I2S_CONFIG_SDOUT_PIN +#define I2S_CONFIG_SDOUT_PIN 29 +#endif + +// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> + + +#ifndef I2S_CONFIG_SDIN_PIN +#define I2S_CONFIG_SDIN_PIN 28 +#endif + +// I2S_CONFIG_MASTER - Mode + +// <0=> Master +// <1=> Slave + +#ifndef I2S_CONFIG_MASTER +#define I2S_CONFIG_MASTER 0 +#endif + +// I2S_CONFIG_FORMAT - Format + +// <0=> I2S +// <1=> Aligned + +#ifndef I2S_CONFIG_FORMAT +#define I2S_CONFIG_FORMAT 0 +#endif + +// I2S_CONFIG_ALIGN - Alignment + +// <0=> Left +// <1=> Right + +#ifndef I2S_CONFIG_ALIGN +#define I2S_CONFIG_ALIGN 0 +#endif + +// I2S_CONFIG_SWIDTH - Sample width (bits) + +// <0=> 8 +// <1=> 16 +// <2=> 24 + +#ifndef I2S_CONFIG_SWIDTH +#define I2S_CONFIG_SWIDTH 1 +#endif + +// I2S_CONFIG_CHANNELS - Channels + +// <0=> Stereo +// <1=> Left +// <2=> Right + +#ifndef I2S_CONFIG_CHANNELS +#define I2S_CONFIG_CHANNELS 1 +#endif + +// I2S_CONFIG_MCK_SETUP - MCK behavior + +// <0=> Disabled +// <2147483648=> 32MHz/2 +// <1342177280=> 32MHz/3 +// <1073741824=> 32MHz/4 +// <805306368=> 32MHz/5 +// <671088640=> 32MHz/6 +// <536870912=> 32MHz/8 +// <402653184=> 32MHz/10 +// <369098752=> 32MHz/11 +// <285212672=> 32MHz/15 +// <268435456=> 32MHz/16 +// <201326592=> 32MHz/21 +// <184549376=> 32MHz/23 +// <142606336=> 32MHz/30 +// <138412032=> 32MHz/31 +// <134217728=> 32MHz/32 +// <100663296=> 32MHz/42 +// <68157440=> 32MHz/63 +// <34340864=> 32MHz/125 + +#ifndef I2S_CONFIG_MCK_SETUP +#define I2S_CONFIG_MCK_SETUP 536870912 +#endif + +// I2S_CONFIG_RATIO - MCK/LRCK ratio + +// <0=> 32x +// <1=> 48x +// <2=> 64x +// <3=> 96x +// <4=> 128x +// <5=> 192x +// <6=> 256x +// <7=> 384x +// <8=> 512x + +#ifndef I2S_CONFIG_RATIO +#define I2S_CONFIG_RATIO 2000 +#endif + +// I2S_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef I2S_CONFIG_IRQ_PRIORITY +#define I2S_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //I2S_ENABLED +// + +// LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver +//========================================================== +#ifndef LPCOMP_ENABLED +#define LPCOMP_ENABLED 0 +#endif +#if LPCOMP_ENABLED +// LPCOMP_CONFIG_REFERENCE - Reference voltage + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 + +#ifndef LPCOMP_CONFIG_REFERENCE +#define LPCOMP_CONFIG_REFERENCE 3 +#endif + +// LPCOMP_CONFIG_DETECTION - Detection + +// <0=> Crossing +// <1=> Up +// <2=> Down + +#ifndef LPCOMP_CONFIG_DETECTION +#define LPCOMP_CONFIG_DETECTION 2 +#endif + +// LPCOMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef LPCOMP_CONFIG_INPUT +#define LPCOMP_CONFIG_INPUT 0 +#endif + +// LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef LPCOMP_CONFIG_IRQ_PRIORITY +#define LPCOMP_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //LPCOMP_ENABLED +// + +// PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver +//========================================================== +#ifndef PDM_ENABLED +#define PDM_ENABLED 0 +#endif +#if PDM_ENABLED +// PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef PDM_CONFIG_MODE +#define PDM_CONFIG_MODE 1 +#endif + +// PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef PDM_CONFIG_EDGE +#define PDM_CONFIG_EDGE 0 +#endif + +// PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef PDM_CONFIG_CLOCK_FREQ +#define PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef PDM_CONFIG_IRQ_PRIORITY +#define PDM_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //PDM_ENABLED +// + +// PERIPHERAL_RESOURCE_SHARING_ENABLED - nrf_drv_common - Peripheral drivers common module + + +#ifndef PERIPHERAL_RESOURCE_SHARING_ENABLED +#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0 +#endif + +// PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver + + +#ifndef PPI_ENABLED +#define PPI_ENABLED 0 +#endif + +// PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver +//========================================================== +#ifndef PWM_ENABLED +#define PWM_ENABLED 0 +#endif +#if PWM_ENABLED +// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN +#define PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN +#define PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN +#define PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN +#define PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 MHz + +#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK +#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE +#define PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE +#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE +#define PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef PWM_DEFAULT_CONFIG_STEP_MODE +#define PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// PWM0_ENABLED - Enable PWM0 instance + + +#ifndef PWM0_ENABLED +#define PWM0_ENABLED 0 +#endif + +// PWM1_ENABLED - Enable PWM1 instance + + +#ifndef PWM1_ENABLED +#define PWM1_ENABLED 0 +#endif + +// PWM2_ENABLED - Enable PWM2 instance + + +#ifndef PWM2_ENABLED +#define PWM2_ENABLED 0 +#endif + +#endif //PWM_ENABLED +// + +// QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver +//========================================================== +#ifndef QDEC_ENABLED +#define QDEC_ENABLED 0 +#endif +#if QDEC_ENABLED +// QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef QDEC_CONFIG_REPORTPER +#define QDEC_CONFIG_REPORTPER 0 +#endif + +// QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef QDEC_CONFIG_SAMPLEPER +#define QDEC_CONFIG_SAMPLEPER 7 +#endif + +// QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_A +#define QDEC_CONFIG_PIO_A 31 +#endif + +// QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_B +#define QDEC_CONFIG_PIO_B 31 +#endif + +// QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_LED +#define QDEC_CONFIG_PIO_LED 31 +#endif + +// QDEC_CONFIG_LEDPRE - LED pre +#ifndef QDEC_CONFIG_LEDPRE +#define QDEC_CONFIG_LEDPRE 511 +#endif + +// QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef QDEC_CONFIG_LEDPOL +#define QDEC_CONFIG_LEDPOL 1 +#endif + +// QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef QDEC_CONFIG_DBFEN +#define QDEC_CONFIG_DBFEN 0 +#endif + +// QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef QDEC_CONFIG_SAMPLE_INTEN +#define QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef QDEC_CONFIG_IRQ_PRIORITY +#define QDEC_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //QDEC_ENABLED +// + +// RNG_ENABLED - nrf_drv_rng - RNG peripheral driver +//========================================================== +#ifndef RNG_ENABLED +#define RNG_ENABLED 0 +#endif +#if RNG_ENABLED +// RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef RNG_CONFIG_ERROR_CORRECTION +#define RNG_CONFIG_ERROR_CORRECTION 0 +#endif + +// RNG_CONFIG_POOL_SIZE - Pool size +#ifndef RNG_CONFIG_POOL_SIZE +#define RNG_CONFIG_POOL_SIZE 8 +#endif + +// RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef RNG_CONFIG_IRQ_PRIORITY +#define RNG_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //RNG_ENABLED +// + +// RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver +//========================================================== +#ifndef RTC_ENABLED +#define RTC_ENABLED 0 +#endif +#if RTC_ENABLED +// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef RTC_DEFAULT_CONFIG_FREQUENCY +#define RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef RTC_DEFAULT_CONFIG_RELIABLE +#define RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// RTC0_ENABLED - Enable RTC0 instance + + +#ifndef RTC0_ENABLED +#define RTC0_ENABLED 0 +#endif + +// RTC1_ENABLED - Enable RTC1 instance + + +#ifndef RTC1_ENABLED +#define RTC1_ENABLED 0 +#endif + +// RTC2_ENABLED - Enable RTC2 instance + + +#ifndef RTC2_ENABLED +#define RTC2_ENABLED 0 +#endif + +// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRF_MAXIMUM_LATENCY_US +#define NRF_MAXIMUM_LATENCY_US 2000 +#endif + +#endif //RTC_ENABLED +// + +// SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver +//========================================================== +#ifndef SAADC_ENABLED +#define SAADC_ENABLED 0 +#endif +#if SAADC_ENABLED +// SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef SAADC_CONFIG_RESOLUTION +#define SAADC_CONFIG_RESOLUTION 1 +#endif + +// SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef SAADC_CONFIG_OVERSAMPLE +#define SAADC_CONFIG_OVERSAMPLE 0 +#endif + +// SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef SAADC_CONFIG_LP_MODE +#define SAADC_CONFIG_LP_MODE 0 +#endif + +// SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SAADC_CONFIG_IRQ_PRIORITY +#define SAADC_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //SAADC_ENABLED +// + +// SPIS_ENABLED - nrf_drv_spis - SPI Slave driver +//========================================================== +#ifndef SPIS_ENABLED +#define SPIS_ENABLED 0 +#endif +#if SPIS_ENABLED +// SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// SPIS_DEFAULT_MODE - Mode + +// <0=> MODE_0 +// <1=> MODE_1 +// <2=> MODE_2 +// <3=> MODE_3 + +#ifndef SPIS_DEFAULT_MODE +#define SPIS_DEFAULT_MODE 0 +#endif + +// SPIS_DEFAULT_BIT_ORDER - SPIS default bit order + +// <0=> MSB first +// <1=> LSB first + +#ifndef SPIS_DEFAULT_BIT_ORDER +#define SPIS_DEFAULT_BIT_ORDER 0 +#endif + +// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef SPIS_DEFAULT_DEF +#define SPIS_DEFAULT_DEF 255 +#endif + +// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef SPIS_DEFAULT_ORC +#define SPIS_DEFAULT_ORC 255 +#endif + +// SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef SPIS0_ENABLED +#define SPIS0_ENABLED 0 +#endif + +// SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef SPIS1_ENABLED +#define SPIS1_ENABLED 0 +#endif + +// SPIS2_ENABLED - Enable SPIS2 instance + + +#ifndef SPIS2_ENABLED +#define SPIS2_ENABLED 0 +#endif + +#endif //SPIS_ENABLED +// + +// SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver +//========================================================== +#ifndef SPI_ENABLED +#define SPI_ENABLED 0 +#endif +#if SPI_ENABLED +// SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPI_CONFIG_LOG_ENABLED +#define SPI_CONFIG_LOG_ENABLED 0 +#endif +#if SPI_CONFIG_LOG_ENABLED +// SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPI_CONFIG_LOG_LEVEL +#define SPI_CONFIG_LOG_LEVEL 3 +#endif + +// SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_INFO_COLOR +#define SPI_CONFIG_INFO_COLOR 0 +#endif + +// SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_DEBUG_COLOR +#define SPI_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //SPI_CONFIG_LOG_ENABLED +// + +// SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// SPI0_ENABLED - Enable SPI0 instance +//========================================================== +#ifndef SPI0_ENABLED +#define SPI0_ENABLED 0 +#endif +#if SPI0_ENABLED +// SPI0_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI0_USE_EASY_DMA +#define SPI0_USE_EASY_DMA 1 +#endif + +#endif //SPI0_ENABLED +// + +// SPI1_ENABLED - Enable SPI1 instance +//========================================================== +#ifndef SPI1_ENABLED +#define SPI1_ENABLED 0 +#endif +#if SPI1_ENABLED +// SPI1_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI1_USE_EASY_DMA +#define SPI1_USE_EASY_DMA 1 +#endif + +#endif //SPI1_ENABLED +// + +// SPI2_ENABLED - Enable SPI2 instance +//========================================================== +#ifndef SPI2_ENABLED +#define SPI2_ENABLED 0 +#endif +#if SPI2_ENABLED +// SPI2_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI2_USE_EASY_DMA +#define SPI2_USE_EASY_DMA 1 +#endif + +#endif //SPI2_ENABLED +// + +#endif //SPI_ENABLED +// + +// TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver +//========================================================== +#ifndef TIMER_ENABLED +#define TIMER_ENABLED 0 +#endif +#if TIMER_ENABLED +// TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY +#define TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef TIMER_DEFAULT_CONFIG_MODE +#define TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef TIMER0_ENABLED +#define TIMER0_ENABLED 0 +#endif + +// TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef TIMER1_ENABLED +#define TIMER1_ENABLED 0 +#endif + +// TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef TIMER2_ENABLED +#define TIMER2_ENABLED 0 +#endif + +// TIMER3_ENABLED - Enable TIMER3 instance + + +#ifndef TIMER3_ENABLED +#define TIMER3_ENABLED 0 +#endif + +// TIMER4_ENABLED - Enable TIMER4 instance + + +#ifndef TIMER4_ENABLED +#define TIMER4_ENABLED 0 +#endif + +#endif //TIMER_ENABLED +// + +// TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver +//========================================================== +#ifndef TWIS_ENABLED +#define TWIS_ENABLED 0 +#endif +#if TWIS_ENABLED +// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef TWIS_DEFAULT_CONFIG_ADDR0 +#define TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef TWIS_DEFAULT_CONFIG_ADDR1 +#define TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL +#define TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL +#define TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef TWIS0_ENABLED +#define TWIS0_ENABLED 0 +#endif + +// TWIS1_ENABLED - Enable TWIS1 instance + + +#ifndef TWIS1_ENABLED +#define TWIS1_ENABLED 0 +#endif + +// TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef TWIS_NO_SYNC_MODE +#define TWIS_NO_SYNC_MODE 0 +#endif + +#endif //TWIS_ENABLED +// + +// TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver +//========================================================== +#ifndef TWI_ENABLED +#define TWI_ENABLED 0 +#endif +#if TWI_ENABLED +// TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef TWI_DEFAULT_CONFIG_FREQUENCY +#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// TWI_DEFAULT_CONFIG_CLR_BUS_INIT - Enables bus clearing procedure during init + + +#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT +#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 +#endif + +// TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// TWI0_ENABLED - Enable TWI0 instance +//========================================================== +#ifndef TWI0_ENABLED +#define TWI0_ENABLED 0 +#endif +#if TWI0_ENABLED +// TWI0_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI0_USE_EASY_DMA +#define TWI0_USE_EASY_DMA 0 +#endif + +#endif //TWI0_ENABLED +// + +// TWI1_ENABLED - Enable TWI1 instance +//========================================================== +#ifndef TWI1_ENABLED +#define TWI1_ENABLED 0 +#endif +#if TWI1_ENABLED +// TWI1_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI1_USE_EASY_DMA +#define TWI1_USE_EASY_DMA 0 +#endif + +#endif //TWI1_ENABLED +// + +#endif //TWI_ENABLED +// + +// UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver +//========================================================== +#ifndef UART_ENABLED +#define UART_ENABLED 1 +#endif +#if UART_ENABLED +// UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef UART_DEFAULT_CONFIG_HWFC +#define UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef UART_DEFAULT_CONFIG_PARITY +#define UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 57600 baud + +#ifndef UART_DEFAULT_CONFIG_BAUDRATE +#define UART_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA + + +#ifndef UART0_CONFIG_USE_EASY_DMA +#define UART0_CONFIG_USE_EASY_DMA 1 +#endif + +// UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA + + +#ifndef UART_EASY_DMA_SUPPORT +#define UART_EASY_DMA_SUPPORT 1 +#endif + +// UART_LEGACY_SUPPORT - Driver supporting Legacy mode + + +#ifndef UART_LEGACY_SUPPORT +#define UART_LEGACY_SUPPORT 1 +#endif + +#endif //UART_ENABLED +// + +// WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver +//========================================================== +#ifndef WDT_ENABLED +#define WDT_ENABLED 0 +#endif +#if WDT_ENABLED +// WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef WDT_CONFIG_BEHAVIOUR +#define WDT_CONFIG_BEHAVIOUR 1 +#endif + +// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef WDT_CONFIG_RELOAD_VALUE +#define WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef WDT_CONFIG_IRQ_PRIORITY +#define WDT_CONFIG_IRQ_PRIORITY 6 +#endif + +#endif //WDT_ENABLED +// + +// +//========================================================== + +// nRF_Libraries + +//========================================================== +// APP_FIFO_ENABLED - app_fifo - Software FIFO implementation + + +#ifndef APP_FIFO_ENABLED +#define APP_FIFO_ENABLED 1 +#endif + +// APP_MAILBOX_ENABLED - app_mailbox - Thread safe mailbox + + +#ifndef APP_MAILBOX_ENABLED +#define APP_MAILBOX_ENABLED 0 +#endif + +// APP_PWM_ENABLED - app_pwm - PWM functionality + + +#ifndef APP_PWM_ENABLED +#define APP_PWM_ENABLED 0 +#endif + +// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler +//========================================================== +#ifndef APP_SCHEDULER_ENABLED +#define APP_SCHEDULER_ENABLED 0 +#endif +#if APP_SCHEDULER_ENABLED +// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature + + +#ifndef APP_SCHEDULER_WITH_PAUSE +#define APP_SCHEDULER_WITH_PAUSE 0 +#endif + +// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling + + +#ifndef APP_SCHEDULER_WITH_PROFILER +#define APP_SCHEDULER_WITH_PROFILER 0 +#endif + +#endif //APP_SCHEDULER_ENABLED +// + +// APP_TIMER_ENABLED - app_timer - Application timer functionality +//========================================================== +#ifndef APP_TIMER_ENABLED +#define APP_TIMER_ENABLED 1 +#endif +#if APP_TIMER_ENABLED +// APP_TIMER_WITH_PROFILER - Enable app_timer profiling + + +#ifndef APP_TIMER_WITH_PROFILER +#define APP_TIMER_WITH_PROFILER 0 +#endif + +// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on + + +// If option is enabled RTC is kept running even if there is no active timers. +// This option can be used when app_timer is used for timestamping. + +#ifndef APP_TIMER_KEEPS_RTC_ACTIVE +#define APP_TIMER_KEEPS_RTC_ACTIVE 0 +#endif + +#endif //APP_TIMER_ENABLED +// + +// APP_TWI_ENABLED - app_twi - TWI transaction manager + + +#ifndef APP_TWI_ENABLED +#define APP_TWI_ENABLED 0 +#endif + +// APP_UART_ENABLED - app_uart - UART driver +//========================================================== +#ifndef APP_UART_ENABLED +#define APP_UART_ENABLED 1 +#endif +#if APP_UART_ENABLED +// APP_UART_DRIVER_INSTANCE - UART instance used + +// <0=> 0 + +#ifndef APP_UART_DRIVER_INSTANCE +#define APP_UART_DRIVER_INSTANCE 0 +#endif + +#endif //APP_UART_ENABLED +// + +// BUTTON_ENABLED - app_button - buttons handling module + + +#ifndef BUTTON_ENABLED +#define BUTTON_ENABLED 1 +#endif + +// CRC16_ENABLED - crc16 - CRC16 calculation routines + + +#ifndef CRC16_ENABLED +#define CRC16_ENABLED 0 +#endif + +// CRC32_ENABLED - crc32 - CRC32 calculation routines + + +#ifndef CRC32_ENABLED +#define CRC32_ENABLED 0 +#endif + +// ECC_ENABLED - ecc - Elliptic Curve Cryptography Library + + +#ifndef ECC_ENABLED +#define ECC_ENABLED 0 +#endif + +// FDS_ENABLED - fds - Flash data storage module +//========================================================== +#ifndef FDS_ENABLED +#define FDS_ENABLED 1 +#endif +#if FDS_ENABLED +// FDS_OP_QUEUE_SIZE - Size of the internal queue. +#ifndef FDS_OP_QUEUE_SIZE +#define FDS_OP_QUEUE_SIZE 4 +#endif + +// FDS_CHUNK_QUEUE_SIZE - Determines how many @ref fds_record_chunk_t structures can be buffered at any time. +#ifndef FDS_CHUNK_QUEUE_SIZE +#define FDS_CHUNK_QUEUE_SIZE 8 +#endif + +// FDS_MAX_USERS - Maximum number of callbacks that can be registered. +#ifndef FDS_MAX_USERS +#define FDS_MAX_USERS 8 +#endif + +// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. +// One of the virtual pages is reserved by the system for garbage collection. +// Therefore, the minimum is two virtual pages: one page to store data and +// one page to be used by the system for garbage collection. The total amount +// of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES +// @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes. + +#ifndef FDS_VIRTUAL_PAGES +#define FDS_VIRTUAL_PAGES 3 +#endif + +// FDS_VIRTUAL_PAGE_SIZE - The size of a virtual page of flash memory, expressed in number of 4-byte words. + + +// By default, a virtual page is the same size as a physical page. +// The size of a virtual page must be a multiple of the size of a physical page. +// <1024=> 1024 +// <2048=> 2048 + +#ifndef FDS_VIRTUAL_PAGE_SIZE +#define FDS_VIRTUAL_PAGE_SIZE 1024 +#endif + +#endif //FDS_ENABLED +// + +// FSTORAGE_ENABLED - fstorage - Flash storage module +//========================================================== +#ifndef FSTORAGE_ENABLED +#define FSTORAGE_ENABLED 1 +#endif +#if FSTORAGE_ENABLED +// FS_QUEUE_SIZE - Configures the size of the internal queue. +// Increase this if there are many users, or if it is likely that many +// operation will be queued at once without waiting for the previous operations +// to complete. In general, increase the queue size if you frequently receive +// @ref FS_ERR_QUEUE_FULL errors when calling @ref fs_store or @ref fs_erase. + +#ifndef FS_QUEUE_SIZE +#define FS_QUEUE_SIZE 4 +#endif + +// FS_OP_MAX_RETRIES - Number attempts to execute an operation if the SoftDevice fails. +// Increase this value if events return the @ref FS_ERR_OPERATION_TIMEOUT +// error often. The SoftDevice may fail to schedule flash access due to high BLE activity. + +#ifndef FS_OP_MAX_RETRIES +#define FS_OP_MAX_RETRIES 3 +#endif + +// FS_MAX_WRITE_SIZE_WORDS - Maximum number of words to be written to flash in a single operation. +// Tweaking this value can increase the chances of the SoftDevice being +// able to fit flash operations in between radio activity. This value is bound by the +// maximum number of words which the SoftDevice can write to flash in a single call to +// @ref sd_flash_write, which is 256 words for nRF51 ICs and 1024 words for nRF52 ICs. + +#ifndef FS_MAX_WRITE_SIZE_WORDS +#define FS_MAX_WRITE_SIZE_WORDS 1024 +#endif + +#endif //FSTORAGE_ENABLED +// + +// HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release + + +#ifndef HARDFAULT_HANDLER_ENABLED +#define HARDFAULT_HANDLER_ENABLED 0 +#endif + +// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI +//========================================================== +#ifndef HCI_MEM_POOL_ENABLED +#define HCI_MEM_POOL_ENABLED 0 +#endif +#if HCI_MEM_POOL_ENABLED +// HCI_TX_BUF_SIZE - TX buffer size in bytes. +#ifndef HCI_TX_BUF_SIZE +#define HCI_TX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_SIZE - RX buffer size in bytes. +#ifndef HCI_RX_BUF_SIZE +#define HCI_RX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. +#ifndef HCI_RX_BUF_QUEUE_SIZE +#define HCI_RX_BUF_QUEUE_SIZE 4 +#endif + +#endif //HCI_MEM_POOL_ENABLED +// + +// HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI +//========================================================== +#ifndef HCI_SLIP_ENABLED +#define HCI_SLIP_ENABLED 0 +#endif +#if HCI_SLIP_ENABLED +// HCI_UART_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 57600 baud + +#ifndef HCI_UART_BAUDRATE +#define HCI_UART_BAUDRATE 30801920 +#endif + +// HCI_UART_FLOW_CONTROL - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef HCI_UART_FLOW_CONTROL +#define HCI_UART_FLOW_CONTROL 0 +#endif + +// HCI_UART_RX_PIN - UART RX pin +#ifndef HCI_UART_RX_PIN +#define HCI_UART_RX_PIN 8 +#endif + +// HCI_UART_TX_PIN - UART TX pin +#ifndef HCI_UART_TX_PIN +#define HCI_UART_TX_PIN 6 +#endif + +// HCI_UART_RTS_PIN - UART RTS pin +#ifndef HCI_UART_RTS_PIN +#define HCI_UART_RTS_PIN 5 +#endif + +// HCI_UART_CTS_PIN - UART CTS pin +#ifndef HCI_UART_CTS_PIN +#define HCI_UART_CTS_PIN 7 +#endif + +#endif //HCI_SLIP_ENABLED +// + +// HCI_TRANSPORT_ENABLED - hci_transport - HCI transport +//========================================================== +#ifndef HCI_TRANSPORT_ENABLED +#define HCI_TRANSPORT_ENABLED 0 +#endif +#if HCI_TRANSPORT_ENABLED +// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. +#ifndef HCI_MAX_PACKET_SIZE_IN_BITS +#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 +#endif + +#endif //HCI_TRANSPORT_ENABLED +// + +// LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module + + +#ifndef LED_SOFTBLINK_ENABLED +#define LED_SOFTBLINK_ENABLED 0 +#endif + +// LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module + + +#ifndef LOW_POWER_PWM_ENABLED +#define LOW_POWER_PWM_ENABLED 0 +#endif + +// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator +//========================================================== +#ifndef MEM_MANAGER_ENABLED +#define MEM_MANAGER_ENABLED 0 +#endif +#if MEM_MANAGER_ENABLED +// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> + + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT +#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 +#endif + +// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. +// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE +#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> + + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT +#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. +// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE +#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> + + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT +#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. +// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE +#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 +#endif + +// MEM_MANAGER_ENABLE_LOGS - Enable debug trace in the module. + + +#ifndef MEM_MANAGER_ENABLE_LOGS +#define MEM_MANAGER_ENABLE_LOGS 0 +#endif + +// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. + + +#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK +#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 +#endif + +#endif //MEM_MANAGER_ENABLED +// + +// NRF_CSENSE_ENABLED - nrf_csense - nrf_csense module +//========================================================== +#ifndef NRF_CSENSE_ENABLED +#define NRF_CSENSE_ENABLED 0 +#endif +#if NRF_CSENSE_ENABLED +// NRF_CSENSE_PAD_HYSTERESIS - Minimal value of change to decide that pad was touched. +#ifndef NRF_CSENSE_PAD_HYSTERESIS +#define NRF_CSENSE_PAD_HYSTERESIS 15 +#endif + +// NRF_CSENSE_PAD_DEVIATION - Minimal value measured on pad to take its value while calculating step. +#ifndef NRF_CSENSE_PAD_DEVIATION +#define NRF_CSENSE_PAD_DEVIATION 70 +#endif + +// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on pad to take its value into account. +#ifndef NRF_CSENSE_MIN_PAD_VALUE +#define NRF_CSENSE_MIN_PAD_VALUE 20 +#endif + +// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. +#ifndef NRF_CSENSE_MAX_PADS_NUMBER +#define NRF_CSENSE_MAX_PADS_NUMBER 20 +#endif + +// NRF_CSENSE_MAX_VALUE - Maximum normalized value got from measurement. +#ifndef NRF_CSENSE_MAX_VALUE +#define NRF_CSENSE_MAX_VALUE 1000 +#endif + +// NRF_CSENSE_OUTPUT_PIN - Output pin used by lower module. +// This is only used when running on NRF51. + +#ifndef NRF_CSENSE_OUTPUT_PIN +#define NRF_CSENSE_OUTPUT_PIN 30 +#endif + +#endif //NRF_CSENSE_ENABLED +// + +// NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor module +//========================================================== +#ifndef NRF_DRV_CSENSE_ENABLED +#define NRF_DRV_CSENSE_ENABLED 0 +#endif +#if NRF_DRV_CSENSE_ENABLED +// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (except nRF51) +#ifndef TIMER0_FOR_CSENSE +#define TIMER0_FOR_CSENSE 1 +#endif + +// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (except nRF51) +#ifndef TIMER1_FOR_CSENSE +#define TIMER1_FOR_CSENSE 2 +#endif + +// MEASUREMENT_PERIOD - Single measurement period. +// Time of single measurement can be calculated as T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). I_SOURCE, VUP and VDOWN are values used to initialize COMP and C is capacitance of used pad. + +#ifndef MEASUREMENT_PERIOD +#define MEASUREMENT_PERIOD 20 +#endif + +#endif //NRF_DRV_CSENSE_ENABLED +// + +// RETARGET_ENABLED - retarget - Retargeting stdio functions + + +#ifndef RETARGET_ENABLED +#define RETARGET_ENABLED 1 +#endif + +// SLIP_ENABLED - slip - SLIP encoding decoding + + +#ifndef SLIP_ENABLED +#define SLIP_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Log + +//========================================================== +// NRF_LOG_ENABLED - nrf_log - Logging +//========================================================== +#ifndef NRF_LOG_ENABLED +#define NRF_LOG_ENABLED 0 +#endif +#if NRF_LOG_ENABLED +// NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string +//========================================================== +#ifndef NRF_LOG_USES_COLORS +#define NRF_LOG_USES_COLORS 0 +#endif +#if NRF_LOG_USES_COLORS +// NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_COLOR_DEFAULT +#define NRF_LOG_COLOR_DEFAULT 0 +#endif + +// NRF_LOG_ERROR_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_ERROR_COLOR +#define NRF_LOG_ERROR_COLOR 0 +#endif + +// NRF_LOG_WARNING_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_WARNING_COLOR +#define NRF_LOG_WARNING_COLOR 0 +#endif + +#endif //NRF_LOG_USES_COLORS +// + +// NRF_LOG_DEFAULT_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_LOG_DEFAULT_LEVEL +#define NRF_LOG_DEFAULT_LEVEL 3 +#endif + +// NRF_LOG_DEFERRED - Enable deffered logger. + +// Log data is buffered and can be processed in idle. +//========================================================== +#ifndef NRF_LOG_DEFERRED +#define NRF_LOG_DEFERRED 1 +#endif +#if NRF_LOG_DEFERRED +// NRF_LOG_DEFERRED_BUFSIZE - Size of the buffer for logs in words. +// Must be power of 2 + +#ifndef NRF_LOG_DEFERRED_BUFSIZE +#define NRF_LOG_DEFERRED_BUFSIZE 256 +#endif + +#endif //NRF_LOG_DEFERRED +// + +// NRF_LOG_USES_TIMESTAMP - Enable timestamping + + +// Function for getting the timestamp is provided by the user + +#ifndef NRF_LOG_USES_TIMESTAMP +#define NRF_LOG_USES_TIMESTAMP 0 +#endif + +#endif //NRF_LOG_ENABLED +// + +// +//========================================================== + +// <<< end of configuration section >>> +#endif //SDK_CONFIG_H + diff --git a/nrf5/sdk/sdk_common.mk b/nrf5/sdk/sdk_common.mk new file mode 100644 index 0000000000..cc75446b35 --- /dev/null +++ b/nrf5/sdk/sdk_common.mk @@ -0,0 +1,27 @@ + +SDK_MODULES ?= + +ifeq ($(SD), s1xx) + SDK_MODULES = iot_0.9.0 +else ifeq ($(SD), s110) + SDK_MODULES = sdk_10.0.0 +else ifeq ($(SD), s120) + SDK_MODULES = sdk_10.0.0 + $(error No supported BLE wrapper) +else ifeq ($(SD), s130) + SDK_MODULES = sdk_10.0.0 +else ifeq ($(SD), s132) + SDK_MODULES = sdk_12.1.0 +else + $(error No SDK configured for this SD) +endif + +SDK_MODULES_PATH = sdk/$(SDK_MODULES)/ + +include $(SDK_MODULES_PATH)sdk.mk + +INC += -I./sdk + +SRC_C += \ + sdk/modble.c \ + sdk/softdevice.c diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 965bac4c6d..e59ddd66d1 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -52,7 +52,7 @@ void softdevice_assert_handler(uint32_t id, uint32_t pc, uint32_t info) { printf("ERROR: SoftDevice assert!!!"); } #endif -uint32_t softdevice_enable(void) { +uint32_t sd_enable(void) { #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) memset(&nrf_nvic_state, 0, sizeof(nrf_nvic_state_t)); #endif @@ -108,11 +108,11 @@ uint32_t softdevice_enable(void) { return err_code; } -void softdevice_disable(void) { +void sd_disable(void) { sd_softdevice_disable(); } -uint8_t softdevice_enabled(void) { +uint8_t sd_enabled(void) { uint8_t is_enabled; uint32_t err_code = sd_softdevice_is_enabled(&is_enabled); @@ -123,7 +123,7 @@ uint8_t softdevice_enabled(void) { return is_enabled; } -void softdevice_address_get(void) { +void sd_address_get(void) { ble_gap_addr_t local_ble_addr; #if (BLUETOOTH_SD != 132) uint32_t err_code = sd_ble_gap_address_get(&local_ble_addr); @@ -157,7 +157,7 @@ void softdevice_address_get(void) { #define APP_CFG_NON_CONN_ADV_TIMEOUT 0 // Disable timeout. #define NON_CONNECTABLE_ADV_INTERVAL MSEC_TO_UNITS(100, UNIT_0_625_MS) -void softdevice_advertise(void) { +void sd_advertise(void) { ble_uuid_t adv_uuids[] = {{.uuid = EDDYSTONE_UUID, .type = BLE_UUID_TYPE_BLE}}; uint8_t encoded_size; uint8_t uuid_encoded[2]; diff --git a/nrf5/sdk/softdevice.h b/nrf5/sdk/softdevice.h index decc7e296f..78cb60a127 100644 --- a/nrf5/sdk/softdevice.h +++ b/nrf5/sdk/softdevice.h @@ -26,13 +26,13 @@ #include -uint32_t softdevice_enable(void); +uint32_t sd_enable(void); -void softdevice_disable(void); +void sd_disable(void); -uint8_t softdevice_enabled(void); +uint8_t sd_enabled(void); -void softdevice_address_get(void); +void sd_address_get(void); -void softdevice_advertise(void); +void sd_advertise(void); diff --git a/nrf5/spi.c b/nrf5/spi.c new file mode 100644 index 0000000000..60e1113f93 --- /dev/null +++ b/nrf5/spi.c @@ -0,0 +1,326 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "extmod/machine_spi.h" +#include "pin.h" +#include "genhdr/pins.h" +#include "spi.h" +#include "hal_spi.h" + +#if MICROPY_PY_MACHINE_SPI + +/// \moduleref pyb +/// \class SPI - a master-driven serial protocol +/// +/// SPI is a serial protocol that is driven by a master. At the physical level +/// there are 3 lines: SCK, MOSI, MISO. +/// +/// See usage model of I2C; SPI is very similar. Main difference is +/// parameters to init the SPI bus: +/// +/// from pyb import SPI +/// spi = SPI(1, SPI.MASTER, baudrate=600000, polarity=1, phase=0, crc=0x7) +/// +/// Only required parameter is mode, SPI.MASTER or SPI.SLAVE. Polarity can be +/// 0 or 1, and is the level the idle clock line sits at. Phase can be 0 or 1 +/// to sample data on the first or second clock edge respectively. Crc can be +/// None for no CRC, or a polynomial specifier. +/// +/// Additional method for SPI: +/// +/// data = spi.send_recv(b'1234') # send 4 bytes and receive 4 bytes +/// buf = bytearray(4) +/// spi.send_recv(b'1234', buf) # send 4 bytes and receive 4 into buf +/// spi.send_recv(buf, buf) # send/recv 4 bytes from/to buf + +typedef struct _pyb_spi_obj_t { + mp_obj_base_t base; + SPI_HandleTypeDef *spi; +} pyb_spi_obj_t; + +#if defined(MICROPY_HW_SPI0_SCK) +SPI_HandleTypeDef SPIHandle0 = {.instance = NULL}; +#endif + +STATIC const pyb_spi_obj_t machine_spi_obj[] = { + #if defined(MICROPY_HW_SPI0_SCK) + {{&machine_hard_spi_type}, &SPIHandle0}, + #else + {{&machine_hard_spi_type}, NULL}, + #endif +}; + +void spi_init0(void) { + // reset the SPI handles + #if defined(MICROPY_HW_SPI0_SCK) + memset(&SPIHandle0, 0, sizeof(SPI_HandleTypeDef)); + SPIHandle0.instance = SPI0; + #endif +} + +STATIC int spi_find(mp_obj_t id) { + if (MP_OBJ_IS_STR(id)) { + // given a string id + const char *port = mp_obj_str_get_str(id); + if (0) { + #ifdef MICROPY_HW_SPI0_NAME + } else if (strcmp(port, MICROPY_HW_SPI0_NAME) == 0) { + return 1; + #endif + } + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "SPI(%s) does not exist", port)); + } else { + // given an integer id + int spi_id = mp_obj_get_int(id); + if (spi_id >= 0 && spi_id <= MP_ARRAY_SIZE(machine_spi_obj) + && machine_spi_obj[spi_id].spi != NULL) { + return spi_id; + } + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "SPI(%d) does not exist", spi_id)); + } +} + +void spi_init(SPI_HandleTypeDef *spi, bool enable_nss_pin) { +} + +void spi_deinit(SPI_HandleTypeDef *spi) { +} + +STATIC void spi_transfer(const pyb_spi_obj_t * self, size_t len, const uint8_t * src, uint8_t * dest, uint32_t timeout) { + hal_spi_master_tx_rx(self->spi->instance, len, src, dest); +} + +STATIC void spi_print(const mp_print_t *print, SPI_HandleTypeDef *spi, bool legacy) { + uint spi_num = 0; // default to SPI1 + mp_printf(print, "SPI(%u)", spi_num); +} + +/******************************************************************************/ +/* MicroPython bindings for machine API */ + +// for make_new +enum { + ARG_NEW_id, + ARG_NEW_baudrate, + ARG_NEW_polarity, + ARG_NEW_phase, + ARG_NEW_bits, + ARG_NEW_firstbit, + ARG_NEW_sck, + ARG_NEW_mosi, + ARG_NEW_miso +}; + +// for init +enum { + ARG_INIT_baudrate, + ARG_INIT_polarity, + ARG_INIT_phase, + ARG_INIT_bits, + ARG_INIT_firstbit +}; + +STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args); +STATIC void machine_hard_spi_init(mp_obj_t self, mp_arg_val_t *args); +STATIC void machine_hard_spi_deinit(mp_obj_t self); + +/* common code for both soft and hard implementations *************************/ + +STATIC mp_obj_t machine_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + { MP_QSTR_baudrate, MP_ARG_INT, {.u_int = 500000} }, + { MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} }, + { MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0 /* SPI_FIRSTBIT_MSB */} }, + { MP_QSTR_sck, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_mosi, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_miso, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { + // TODO: implement soft SPI + // return machine_soft_spi_make_new(args); + return mp_const_none; + } else { + // hardware peripheral id given + return machine_hard_spi_make_new(args); + } +} + +STATIC mp_obj_t machine_spi_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_baudrate, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + }; + + // parse args + mp_obj_t self = pos_args[0]; + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // dispatch to specific implementation + if (mp_obj_get_type(self) == &machine_hard_spi_type) { + machine_hard_spi_init(self, args); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_spi_init_obj, 1, machine_spi_init); + +STATIC mp_obj_t machine_spi_deinit(mp_obj_t self) { + // dispatch to specific implementation + if (mp_obj_get_type(self) == &machine_hard_spi_type) { + machine_hard_spi_deinit(self); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_spi_deinit_obj, machine_spi_deinit); + +STATIC const mp_rom_map_elem_t machine_spi_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_spi_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_spi_deinit_obj) }, + + { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_machine_spi_read_obj) }, + { MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&mp_machine_spi_readinto_obj) }, + { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&mp_machine_spi_write_obj) }, + { MP_ROM_QSTR(MP_QSTR_write_readinto), MP_ROM_PTR(&mp_machine_spi_write_readinto_obj) }, + + { MP_ROM_QSTR(MP_QSTR_MSB), MP_ROM_INT(0) }, // SPI_FIRSTBIT_MSB + { MP_ROM_QSTR(MP_QSTR_LSB), MP_ROM_INT(1) }, // SPI_FIRSTBIT_LSB +}; + +STATIC MP_DEFINE_CONST_DICT(machine_spi_locals_dict, machine_spi_locals_dict_table); + +/* code for hard implementation ***********************************************/ + +typedef struct _machine_hard_spi_obj_t { + mp_obj_base_t base; + const pyb_spi_obj_t *pyb; +} machine_hard_spi_obj_t; + +STATIC const machine_hard_spi_obj_t machine_hard_spi_obj[] = { + {{&machine_hard_spi_type}, &machine_spi_obj[0]}, +}; + +STATIC void machine_hard_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_hard_spi_obj_t *self = self_in; + spi_print(print, self->pyb->spi, false); +} + +STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) { + // get static peripheral object + int spi_id = spi_find(args[ARG_NEW_id].u_obj); + const machine_hard_spi_obj_t *self = &machine_hard_spi_obj[spi_id]; + + hal_spi_init_t spi_init_conf; + + // here we would check the sck/mosi/miso pins and configure them + if (args[ARG_NEW_sck].u_obj != MP_OBJ_NULL + && args[ARG_NEW_mosi].u_obj != MP_OBJ_NULL + && args[ARG_NEW_miso].u_obj != MP_OBJ_NULL) { + + spi_init_conf.clk_pin = mp_obj_get_int(args[ARG_NEW_sck].u_obj); + spi_init_conf.mosi_pin = mp_obj_get_int(args[ARG_NEW_mosi].u_obj); + spi_init_conf.miso_pin = mp_obj_get_int(args[ARG_NEW_miso].u_obj); + spi_init_conf.enable_pin = MICROPY_HW_SPI0_NSS; + } else { + spi_init_conf.clk_pin = MICROPY_HW_SPI0_SCK; + spi_init_conf.mosi_pin = MICROPY_HW_SPI0_MOSI; + spi_init_conf.miso_pin = MICROPY_HW_SPI0_MISO; + spi_init_conf.enable_pin = MICROPY_HW_SPI0_NSS; + } + + int baudrate = args[ARG_NEW_baudrate].u_int; + + if (baudrate <= 125000) { + spi_init_conf.freq = HAL_FREQ_125_Kbps; + } else if (baudrate <= 250000) { + spi_init_conf.freq = HAL_FREQ_250_Kbps; + } else if (baudrate <= 500000) { + spi_init_conf.freq = HAL_FREQ_500_Kbps; + } else if (baudrate <= 1000000) { + spi_init_conf.freq = HAL_FREQ_1_Mbps; + } else if (baudrate <= 2000000) { + spi_init_conf.freq = HAL_FREQ_2_Mbps; + } else if (baudrate <= 4000000) { + spi_init_conf.freq = HAL_FREQ_4_Mbps; + } else { + spi_init_conf.freq = HAL_FREQ_8_Mbps; + } + + spi_init_conf.irq_priority = 4; + spi_init_conf.mode = HAL_SPI_MODE_CPOL0_CPHA0; + spi_init_conf.lsb_first = false; + hal_spi_master_init(self->pyb->spi->instance, &spi_init_conf); + + return MP_OBJ_FROM_PTR(self); +} + +STATIC void machine_hard_spi_init(mp_obj_t self_in, mp_arg_val_t *args) { +} + +STATIC void machine_hard_spi_deinit(mp_obj_t self_in) { + machine_hard_spi_obj_t *self = self_in; + spi_deinit(self->pyb->spi); +} + +STATIC void machine_hard_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8_t *src, uint8_t *dest) { + machine_hard_spi_obj_t *self = (machine_hard_spi_obj_t*)self_in; + spi_transfer(self->pyb, len, src, dest, 100); +} + +STATIC const mp_machine_spi_p_t machine_hard_spi_p = { + .transfer = machine_hard_spi_transfer, +}; + +const mp_obj_type_t machine_hard_spi_type = { + { &mp_type_type }, + .name = MP_QSTR_SPI, + .print = machine_hard_spi_print, + .make_new = machine_spi_make_new, + .protocol = &machine_hard_spi_p, + .locals_dict = (mp_obj_t)&machine_spi_locals_dict, +}; + +#endif // MICROPY_PY_MACHINE_SPI diff --git a/nrf5/spi.h b/nrf5/spi.h new file mode 100644 index 0000000000..dc8489d1e0 --- /dev/null +++ b/nrf5/spi.h @@ -0,0 +1,32 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hal_spi.h" + +extern const mp_obj_type_t machine_hard_spi_type; + +void spi_init0(void); diff --git a/nrf5/uart.c b/nrf5/uart.c index 76fb4e8a47..1d6ca6fb01 100644 --- a/nrf5/uart.c +++ b/nrf5/uart.c @@ -3,6 +3,7 @@ * * The MIT License (MIT) * + * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2015 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -23,6 +24,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ + #include #include #include diff --git a/nrf5/uart.h b/nrf5/uart.h index 6243bfe969..26b79c949f 100644 --- a/nrf5/uart.h +++ b/nrf5/uart.h @@ -3,6 +3,7 @@ * * The MIT License (MIT) * + * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2015 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy From 4344d41b36488a8a86b5e45c0edaec1ad1fd910a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 13 Dec 2016 20:32:54 +0100 Subject: [PATCH 012/809] lib/netutils: Adding some basic parsing and formating of ipv6 address strings. Only working with full length ipv6 strings. Short forms not supported at the moment (for example FE80::1, needs to be expressed as FE80:0000:0000:0000:0000:0000:0000:0001). --- lib/netutils/netutils.c | 85 +++++++++++++++++++++++++++++++++++++++++ lib/netutils/netutils.h | 15 ++++++++ 2 files changed, 100 insertions(+) diff --git a/lib/netutils/netutils.c b/lib/netutils/netutils.c index ac4ebfa2b7..b896cf0c8f 100644 --- a/lib/netutils/netutils.c +++ b/lib/netutils/netutils.c @@ -5,6 +5,7 @@ * * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2015 Daniel Campora + * Copyright (c) 2016 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,6 +29,7 @@ #include #include #include +#include #include "py/obj.h" #include "py/nlr.h" @@ -93,3 +95,86 @@ mp_uint_t netutils_parse_inet_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_e netutils_parse_ipv4_addr(addr_items[0], out_ip, endian); return mp_obj_get_int(addr_items[1]); } + + +// Takes an array with a raw IPv6 address and returns something like '2001:db8::abcd:ef01:2345'. +mp_obj_t netutils_format_ipv6_addr(uint8_t *ip, netutils_endian_t endian) { + char ip_str[40]; + mp_uint_t ip_len; + if (endian == NETUTILS_LITTLE) { + ip_len = snprintf(ip_str, 40, "%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x", + ip[15], ip[14], ip[13], ip[12], + ip[11], ip[10], ip[9], ip[8], + ip[7], ip[6], ip[5], ip[4], + ip[3], ip[2], ip[1], ip[0]); + } else { + ip_len = snprintf(ip_str, 40, "%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x", + ip[0], ip[1], ip[2], ip[3], + ip[4], ip[5], ip[6], ip[7], + ip[8], ip[9], ip[10], ip[11], + ip[12], ip[13], ip[14], ip[15]); + } + return mp_obj_new_str(ip_str, ip_len, false); +} + +// Takes an array with a raw IP address, and a port, and returns a net-address +// tuple such as ('2001:db8::abcd:ef01:2345', 8080). +mp_obj_t netutils_format_inet6_addr(uint8_t *ip, mp_uint_t port, netutils_endian_t endian) { + mp_obj_t tuple[2] = { + tuple[0] = netutils_format_ipv6_addr(ip, endian), + tuple[1] = mp_obj_new_int(port), + }; + return mp_obj_new_tuple(2, tuple); +} + +void netutils_parse_ipv6_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian) { + mp_uint_t addr_len; + const char *addr_str = mp_obj_str_get_data(addr_in, &addr_len); + if (addr_len == 0) { + // special case of no address given + memset(out_ip, 0, NETUTILS_IPV6ADDR_BUFSIZE); + return; + } + + const char *s = addr_str; + const char *s_top = addr_str + addr_len; + + for (uint8_t i = 0; i <= NETUTILS_IPV6ADDR_BUFSIZE; i += 2) { + uint16_t val = 0; + for (; s < s_top && *s != ':'; s++) { + if ((*s >= 'a' && *s <= 'f')) { + val = val * 16 + (*s - 'a' + 10); + } else if (*s >= 'A' && *s <= 'F') { + val = val * 16 + (*s - 'A' + 10); + } else { + val = val * 16 + (*s - '0'); + } + } + +// if (endian == NETUTILS_LITTLE) { +// // not supported +// } else + { + out_ip[i] = (val >> 8); + out_ip[i + 1] = (val & 0xFF); + } + + if (s == s_top) { + return; + } else if (s < s_top && *s == ':') { + s++; + } else { + nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "invalid arguments")); + } + } +} + +// Takes an address of the form ('2001:db8::abcd:ef01:2345', 8080), returns the port and +// puts IP in out_ip (which must take at least IPADDR_BUF_SIZE bytes). +mp_uint_t netutils_parse_inet6_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian) { + mp_obj_t *addr_items; + mp_obj_get_array_fixed_n(addr_in, 2, &addr_items); + netutils_parse_ipv6_addr(addr_items[0], out_ip, endian); + return mp_obj_get_int(addr_items[1]); + +} diff --git a/lib/netutils/netutils.h b/lib/netutils/netutils.h index 45e0216402..78ffffc551 100644 --- a/lib/netutils/netutils.h +++ b/lib/netutils/netutils.h @@ -5,6 +5,7 @@ * * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2015 Daniel Campora + * Copyrigth (c) 2016 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,6 +29,7 @@ #define __MICROPY_INCLUDED_LIB_NETUTILS_H__ #define NETUTILS_IPV4ADDR_BUFSIZE 4 +#define NETUTILS_IPV6ADDR_BUFSIZE 16 typedef enum _netutils_endian_t { NETUTILS_LITTLE, @@ -47,4 +49,17 @@ void netutils_parse_ipv4_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian // puts IP in out_ip (which must take at least IPADDR_BUF_SIZE bytes). mp_uint_t netutils_parse_inet_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian); +// Takes an array with a raw IPv6 address and returns something like '2001:db8::abcd:ef01:2345'. +mp_obj_t netutils_format_ipv6_addr(uint8_t *ip, netutils_endian_t endian); + +// Takes an array with a raw IP address, and a port, and returns a net-address +// tuple such as ('2001:db8::abcd:ef01:2345', 8080). +mp_obj_t netutils_format_inet6_addr(uint8_t *ip, mp_uint_t port, netutils_endian_t endian); + +void netutils_parse_ipv6_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian); + +// Takes an address of the form ('2001:db8::abcd:ef01:2345', 8080), returns the port and +// puts IP in out_ip (which must take at least IPADDR_BUF_SIZE bytes). +mp_uint_t netutils_parse_inet6_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian); + #endif // __MICROPY_INCLUDED_LIB_NETUTILS_H__ From 1a1f9b0c9db567e0699ca121c24066a21e270315 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 13 Dec 2016 21:31:39 +0100 Subject: [PATCH 013/809] nrf5: updating flash size comment in nrf52832 linker script. --- nrf5/boards/nrf52832_aa.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/nrf52832_aa.ld b/nrf5/boards/nrf52832_aa.ld index cfdbe073cf..6edcc1cce3 100644 --- a/nrf5/boards/nrf52832_aa.ld +++ b/nrf5/boards/nrf52832_aa.ld @@ -5,7 +5,7 @@ /* Specify the memory areas */ MEMORY { - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 256 KiB */ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */ FLASH_ISR (rx) : ORIGIN = 0x00000000, LENGTH = 0x001000 /* sector 0, 4 KiB */ FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x07F000 /* 508 KiB */ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x010000 /* 64 KiB */ From faa460ae883d685f238a08de888a49360707cd3d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 13 Dec 2016 21:32:40 +0100 Subject: [PATCH 014/809] nrf5: Adding new linker script for nrf52840. --- nrf5/boards/nrf52840_aa.ld | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 nrf5/boards/nrf52840_aa.ld diff --git a/nrf5/boards/nrf52840_aa.ld b/nrf5/boards/nrf52840_aa.ld new file mode 100644 index 0000000000..64d58bff6c --- /dev/null +++ b/nrf5/boards/nrf52840_aa.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for NRF52 blank w/ no SoftDevice +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 /* entire flash, 1 MiB */ + FLASH_ISR (rx) : ORIGIN = 0x00000000, LENGTH = 0x001000 /* sector 0, 4 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x0FF000 /* 1020 KiB */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x040000 /* 256 KiB */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20005000; /* tunable */ + +INCLUDE "boards/common.ld" From bc1aa84caccc1c46327703cfd73b55563b8bdd58 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 13 Dec 2016 21:35:15 +0100 Subject: [PATCH 015/809] nrf5: Updating comment in linker script for nrf52832 and nrf52840 to distinguish between the two nrf52 variants. --- nrf5/boards/nrf52832_aa.ld | 2 +- nrf5/boards/nrf52840_aa.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/nrf52832_aa.ld b/nrf5/boards/nrf52832_aa.ld index 6edcc1cce3..6da7790f7b 100644 --- a/nrf5/boards/nrf52832_aa.ld +++ b/nrf5/boards/nrf52832_aa.ld @@ -1,5 +1,5 @@ /* - GNU linker script for NRF52 blank w/ no SoftDevice + GNU linker script for NRF52832 blank w/ no SoftDevice */ /* Specify the memory areas */ diff --git a/nrf5/boards/nrf52840_aa.ld b/nrf5/boards/nrf52840_aa.ld index 64d58bff6c..1f31e21cb6 100644 --- a/nrf5/boards/nrf52840_aa.ld +++ b/nrf5/boards/nrf52840_aa.ld @@ -1,5 +1,5 @@ /* - GNU linker script for NRF52 blank w/ no SoftDevice + GNU linker script for NRF52840 blank w/ no SoftDevice */ /* Specify the memory areas */ From 90730787f3ba7b238223cce69d1b874077816ad6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 13 Dec 2016 21:38:39 +0100 Subject: [PATCH 016/809] nrf5: Adding initial board files for pca10056. The files are not complete (only 32 pins are added for now). UART REPL, leds, and Pins (up to 31) are functional. --- nrf5/boards/pca10056/mpconfigboard.h | 62 +++++++++++++++++++++++++++ nrf5/boards/pca10056/mpconfigboard.mk | 4 ++ nrf5/boards/pca10056/nrf52_hal_conf.h | 10 +++++ nrf5/boards/pca10056/pins.csv | 30 +++++++++++++ 4 files changed, 106 insertions(+) create mode 100644 nrf5/boards/pca10056/mpconfigboard.h create mode 100644 nrf5/boards/pca10056/mpconfigboard.mk create mode 100644 nrf5/boards/pca10056/nrf52_hal_conf.h create mode 100644 nrf5/boards/pca10056/pins.csv diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h new file mode 100644 index 0000000000..35d02ad232 --- /dev/null +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -0,0 +1,62 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define PCA10056 + +#define MICROPY_HW_BOARD_NAME "PCA10056" +#define MICROPY_HW_MCU_NAME "NRF52840" +#define MICROPY_PY_SYS_PLATFORM "nrf52840-PDK" + +#define MICROPY_PY_MACHINE_SPI (0) + +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_PULLUP (1) + +#define MICROPY_HW_LED1 (13) // LED1 +#define MICROPY_HW_LED2 (14) // LED2 +#define MICROPY_HW_LED3 (15) // LED3 +#define MICROPY_HW_LED4 (16) // LED4 + +// UART config +#define MICROPY_HW_UART1_RX (8) +#define MICROPY_HW_UART1_TX (6) +#define MICROPY_HW_UART1_CTS (7) +#define MICROPY_HW_UART1_RTS (5) +#define MICROPY_HW_UART1_HWFC (1) + +#define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10056/mpconfigboard.mk b/nrf5/boards/pca10056/mpconfigboard.mk new file mode 100644 index 0000000000..2e273dabc7 --- /dev/null +++ b/nrf5/boards/pca10056/mpconfigboard.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m4 +MCU_VARIANT = nrf52 +LD_FILE = boards/nrf52840_aa.ld + diff --git a/nrf5/boards/pca10056/nrf52_hal_conf.h b/nrf5/boards/pca10056/nrf52_hal_conf.h new file mode 100644 index 0000000000..c5f52b8b58 --- /dev/null +++ b/nrf5/boards/pca10056/nrf52_hal_conf.h @@ -0,0 +1,10 @@ +#ifndef NRF52_HAL_CONF_H__ +#define NRF52_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +// #define HAL_UARTE_MODULE_ENABLED +// #define HAL_SPI_MODULE_ENABLED +// #define HAL_SPIE_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED + +#endif // NRF52_HAL_CONF_H__ diff --git a/nrf5/boards/pca10056/pins.csv b/nrf5/boards/pca10056/pins.csv new file mode 100644 index 0000000000..c177133983 --- /dev/null +++ b/nrf5/boards/pca10056/pins.csv @@ -0,0 +1,30 @@ +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA5,PA5 +PA6,PA6 +PA7,PA7 +PA8,PA8 +PA9,PA9 +PA10,PA10 +PA11,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 \ No newline at end of file From 82f7fe88b0992ab517b5f48657b465be8529316b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 16 Dec 2016 19:17:42 +0100 Subject: [PATCH 017/809] nrf5/hal: Starting implementation of PWM hal to be used by PWM python module later. --- nrf5/hal/hal_pwm.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++ nrf5/hal/hal_pwm.h | 61 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 127 insertions(+) create mode 100644 nrf5/hal/hal_pwm.c create mode 100644 nrf5/hal/hal_pwm.h diff --git a/nrf5/hal/hal_pwm.c b/nrf5/hal/hal_pwm.c new file mode 100644 index 0000000000..a1c6ad4aed --- /dev/null +++ b/nrf5/hal/hal_pwm.c @@ -0,0 +1,66 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "mphalport.h" +#include "hal_pwm.h" + +#ifdef HAL_PWM_MODULE_ENABLED + +#define PWM_COUNTER_TOP 16000 // 16MHz divided by 16000-> 1ms + +volatile uint16_t g_pwm_seq[4]; + +void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init) { + + uint16_t duty_cycle = ((PWM_COUNTER_TOP*50)/100); + + g_pwm_seq[0] = duty_cycle; + g_pwm_seq[1] = duty_cycle; + g_pwm_seq[2] = 0; + g_pwm_seq[3] = 0; + + p_instance->PSEL.OUT[0] = (p_pwm_init->pwm_pin << PWM_PSEL_OUT_PIN_Pos) + | (PWM_PSEL_OUT_CONNECT_Connected << PWM_PSEL_OUT_CONNECT_Pos); + + p_instance->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos); + p_instance->MODE = (PWM_MODE_UPDOWN_Up << PWM_MODE_UPDOWN_Pos); + p_instance->PRESCALER = (PWM_PRESCALER_PRESCALER_DIV_1 << PWM_PRESCALER_PRESCALER_Pos); + p_instance->COUNTERTOP = (PWM_COUNTER_TOP << PWM_COUNTERTOP_COUNTERTOP_Pos); //1 msec + p_instance->LOOP = (PWM_LOOP_CNT_Disabled << PWM_LOOP_CNT_Pos); + p_instance->DECODER = (PWM_DECODER_LOAD_Individual << PWM_DECODER_LOAD_Pos) + | (PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos); + p_instance->SEQ[0].PTR = ((uint32_t)(g_pwm_seq) << PWM_SEQ_PTR_PTR_Pos); + p_instance->SEQ[0].CNT = ((sizeof(g_pwm_seq) / sizeof(uint16_t)) << PWM_SEQ_CNT_CNT_Pos); + + p_instance->SEQ[0].REFRESH = 0; + p_instance->SEQ[0].ENDDELAY = 0; + p_instance->TASKS_SEQSTART[0] = 1; +} + +#endif // HAL_PWM_MODULE_ENABLED diff --git a/nrf5/hal/hal_pwm.h b/nrf5/hal/hal_pwm.h new file mode 100644 index 0000000000..f60fb707d8 --- /dev/null +++ b/nrf5/hal/hal_pwm.h @@ -0,0 +1,61 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_PWM_H__ +#define HAL_PWM_H__ + +#include + +#include "nrf.h" + +#if NRF51 + +// TODO: create software PWM. + +#elif NRF52 + +#define PWM0 ((NRF_PWM_Type *)NRF_PWM0_BASE) +#define PWM0_IRQ_NUM PWM1_IRQn +#define PWM1 ((NRF_PWM_Type *)NRF_PWM1_BASE) +#define PWM1_IRQ_NUM PWM1_IRQn +#define PWM2 ((NRF_PWM_Type *)NRF_PWM2_BASE) +#define PWM2_IRQ_NUM PWM2_IRQn + +#if 0 // TODO: nrf52840 +#define PWM3 ((NRF_PWM_Type *)NRF_PWM3_BASE) +#define PWM3_IRQ_NUM PWM3_IRQn +#endif + +#else +#error "Device not supported." +#endif + + +typedef struct { + uint8_t pwm_pin; +} hal_pwm_init_t; + +#endif // HAL_PWM_H__ From 930112753a43a07e6f771b680d559458f0913042 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 16 Dec 2016 19:48:28 +0100 Subject: [PATCH 018/809] nrf5: Adding pwm work in progress machine PWM module. --- nrf5/pwm.c | 230 +++++++++++++++++++++++++++++++++++++++++++++++++++++ nrf5/pwm.h | 29 +++++++ 2 files changed, 259 insertions(+) create mode 100644 nrf5/pwm.c create mode 100644 nrf5/pwm.h diff --git a/nrf5/pwm.c b/nrf5/pwm.c new file mode 100644 index 0000000000..446333b07d --- /dev/null +++ b/nrf5/pwm.c @@ -0,0 +1,230 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "pin.h" +#include "genhdr/pins.h" +#include "pwm.h" +#include "hal_pwm.h" + +#if MICROPY_PY_MACHINE_PWM + +typedef struct _pyb_pwm_obj_t { + mp_obj_base_t base; + PWM_HandleTypeDef *pwm; +} pyb_pwm_obj_t; + +#if MICROPY_HW_PWM0 +PWM_HandleTypeDef PWMHandle0 = {.instance = NULL}; +#endif + +STATIC const pyb_pwm_obj_t machine_pwm_obj[] = { + #if MICROPY_HW_PWM0 + {{&machine_hard_pwm_type}, &PWMHandle0}, + #else + {{&machine_hard_pwm_type}, NULL}, + #endif +}; + +void pwm_init0(void) { + // reset the PWM handles + #if MICROPY_HW_PWM0 + memset(&PWMHandle0, 0, sizeof(PWM_HandleTypeDef)); + PWMHandle0.instance = PWM0; + #endif +} + +STATIC int pwm_find(mp_obj_t id) { + if (MP_OBJ_IS_STR(id)) { + // given a string id + const char *port = mp_obj_str_get_str(id); + if (0) { + #ifdef MICROPY_HW_PWM0_NAME + } else if (strcmp(port, MICROPY_HW_PWM0_NAME) == 0) { + return 1; + #endif + } + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "PWM(%s) does not exist", port)); + } else { + // given an integer id + int pwm_id = mp_obj_get_int(id); + if (pwm_id >= 0 && pwm_id <= MP_ARRAY_SIZE(machine_pwm_obj) + && machine_pwm_obj[pwm_id].pwm != NULL) { + return pwm_id; + } + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "PWM(%d) does not exist", pwm_id)); + } +} + +void pwm_init(PWM_HandleTypeDef *pwm) { +} + +void pwm_deinit(PWM_HandleTypeDef *pwm) { +} + +STATIC void pwm_print(const mp_print_t *print, PWM_HandleTypeDef *pwm, bool legacy) { + uint pwm_num = 0; // default to PWM0 + mp_printf(print, "PWM(%u)", pwm_num); +} + +/******************************************************************************/ +/* MicroPython bindings for machine API */ + +// for make_new +enum { + ARG_NEW_id, + ARG_NEW_pin +}; + +// for init +enum { + ARG_INIT_pin +}; + +STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args); +STATIC void machine_hard_pwm_init(mp_obj_t self, mp_arg_val_t *args); +STATIC void machine_hard_pwm_deinit(mp_obj_t self); + +/* common code for both soft and hard implementations *************************/ + +STATIC mp_obj_t machine_pwm_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + { MP_QSTR_pin, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} } + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { + // TODO: implement soft PWM + // return machine_soft_pwm_make_new(args); + return mp_const_none; + } else { + // hardware peripheral id given + return machine_hard_pwm_make_new(args); + } +} + +STATIC mp_obj_t machine_pwm_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_pin, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} } + }; + + // parse args + mp_obj_t self = pos_args[0]; + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // dispatch to specific implementation + if (mp_obj_get_type(self) == &machine_hard_pwm_type) { + machine_hard_pwm_init(self, args); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_pwm_init_obj, 1, machine_pwm_init); + +STATIC mp_obj_t machine_pwm_deinit(mp_obj_t self) { + // dispatch to specific implementation + if (mp_obj_get_type(self) == &machine_hard_pwm_type) { + machine_hard_pwm_deinit(self); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pwm_deinit_obj, machine_pwm_deinit); + +STATIC const mp_rom_map_elem_t machine_pwm_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_pwm_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_pwm_deinit_obj) }, + + { MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&mp_machine_pwm_start_obj) }, + { MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&mp_machine_pwm_stop_obj) }, + { MP_ROM_QSTR(MP_QSTR_update), MP_ROM_PTR(&mp_machine_pwm_update_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(machine_pwm_locals_dict, machine_pwm_locals_dict_table); + +/* code for hard implementation ***********************************************/ + +typedef struct _machine_hard_pwm_obj_t { + mp_obj_base_t base; + const pyb_pwm_obj_t *pyb; +} machine_hard_pwm_obj_t; + +STATIC const machine_hard_pwm_obj_t machine_hard_pwm_obj[] = { + {{&machine_hard_pwm_type}, &machine_pwm_obj[0]}, +}; + +STATIC void machine_hard_pwm_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_hard_pwm_obj_t *self = self_in; + pwm_print(print, self->pyb->pwm, false); +} + +STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args) { + // get static peripheral object + int pwm_id = pwm_find(args[ARG_NEW_id].u_obj); + const machine_hard_pwm_obj_t *self = &machine_hard_pwm_obj[pwm_id]; + + hal_pwm_init_t pwm_init_conf; + + // here we would check the sck/mosi/miso pins and configure them + if (args[ARG_NEW_pin].u_obj != MP_OBJ_NULL) { + pwm_init_conf.pwm_pin = mp_obj_get_int(args[ARG_NEW_pin].u_obj); + } else { + // TODO: raise exception. + } + + hal_pwm_init(self->pyb->pwm->instance, &pwm_init_conf); + + return MP_OBJ_FROM_PTR(self); +} + +STATIC void machine_hard_pwm_init(mp_obj_t self_in, mp_arg_val_t *args) { +} + +STATIC void machine_hard_pwm_deinit(mp_obj_t self_in) { + machine_hard_pwm_obj_t *self = self_in; + pwm_deinit(self->pyb->pwm); +} + +const mp_obj_type_t machine_hard_pwm_type = { + { &mp_type_type }, + .name = MP_QSTR_PWM, + .print = machine_hard_pwm_print, + .make_new = machine_pwm_make_new, + .locals_dict = (mp_obj_t)&machine_pwm_locals_dict, +}; + +#endif // MICROPY_PY_MACHINE_PWM diff --git a/nrf5/pwm.h b/nrf5/pwm.h new file mode 100644 index 0000000000..b6575a9e3f --- /dev/null +++ b/nrf5/pwm.h @@ -0,0 +1,29 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hal_pwm.h" + +extern const mp_obj_type_t machine_hard_pwm_type; From 36a232182a74a0f2ff94738c60e9c777d5be0416 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 16 Dec 2016 19:49:58 +0100 Subject: [PATCH 019/809] nrf5/boards: Adding config flag for HAL_PWM in pca10040 and pca10056. --- nrf5/boards/pca10040/nrf52_hal_conf.h | 1 + nrf5/boards/pca10056/nrf52_hal_conf.h | 1 + 2 files changed, 2 insertions(+) diff --git a/nrf5/boards/pca10040/nrf52_hal_conf.h b/nrf5/boards/pca10040/nrf52_hal_conf.h index b879b974aa..e98a61e044 100644 --- a/nrf5/boards/pca10040/nrf52_hal_conf.h +++ b/nrf5/boards/pca10040/nrf52_hal_conf.h @@ -6,5 +6,6 @@ #define HAL_SPI_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED +// #define HAL_PWM_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ diff --git a/nrf5/boards/pca10056/nrf52_hal_conf.h b/nrf5/boards/pca10056/nrf52_hal_conf.h index c5f52b8b58..313954735a 100644 --- a/nrf5/boards/pca10056/nrf52_hal_conf.h +++ b/nrf5/boards/pca10056/nrf52_hal_conf.h @@ -6,5 +6,6 @@ // #define HAL_SPI_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED +// #define HAL_PWM_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ From eaece2734bb3258cc83bae3db4d4737aa6494371 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 16 Dec 2016 19:50:35 +0100 Subject: [PATCH 020/809] nrf5: Updating makefile to compile in pwm.c and hal_pwm.c --- nrf5/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 1685573f60..fa5b262acc 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -114,6 +114,7 @@ SRC_HAL = $(addprefix hal/,\ hal_spi.c \ hal_spie.c \ hal_time.c \ + hal_pwm.c \ ) SRC_C += \ @@ -123,6 +124,7 @@ SRC_C += \ mphalport.c \ uart.c \ spi.c \ + pwm.c \ help.c \ gccollect.c \ pin_named_pins.c \ From a081bf2f9166340d4e6555b5802acf7ca46722a0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 17 Dec 2016 00:39:24 +0100 Subject: [PATCH 021/809] nrf5/pwm: Removing include of hal_pwm.h as pwm.c might not use a hal, but sw implementation. --- nrf5/pwm.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/pwm.h b/nrf5/pwm.h index b6575a9e3f..c77f6fede1 100644 --- a/nrf5/pwm.h +++ b/nrf5/pwm.h @@ -24,6 +24,4 @@ * THE SOFTWARE. */ -#include "hal_pwm.h" - extern const mp_obj_type_t machine_hard_pwm_type; From 7bfe001d22b499d0b70764afeb778b80e96d989b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 17 Dec 2016 01:03:39 +0100 Subject: [PATCH 022/809] nrf5/pwm: Updating PWM dict table to have freq and duty function. Also added creation of default objects based on PWM name set in board config. Adding ifdef surrounding the import of hal_pwm.h as this module might be used by software implmentation of PWM later. --- nrf5/pwm.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/nrf5/pwm.c b/nrf5/pwm.c index 446333b07d..60326c9f43 100644 --- a/nrf5/pwm.c +++ b/nrf5/pwm.c @@ -30,24 +30,29 @@ #include "py/nlr.h" #include "py/runtime.h" #include "py/mphal.h" + +#if MICROPY_PY_MACHINE_PWM + #include "pin.h" #include "genhdr/pins.h" #include "pwm.h" -#include "hal_pwm.h" -#if MICROPY_PY_MACHINE_PWM +#if NRF52 +// Use PWM hardware. +#include "hal_pwm.h" +#endif typedef struct _pyb_pwm_obj_t { mp_obj_base_t base; PWM_HandleTypeDef *pwm; } pyb_pwm_obj_t; -#if MICROPY_HW_PWM0 +#ifdef MICROPY_HW_PWM0_NAME PWM_HandleTypeDef PWMHandle0 = {.instance = NULL}; #endif STATIC const pyb_pwm_obj_t machine_pwm_obj[] = { - #if MICROPY_HW_PWM0 + #ifdef MICROPY_HW_PWM0_NAME {{&machine_hard_pwm_type}, &PWMHandle0}, #else {{&machine_hard_pwm_type}, NULL}, @@ -56,7 +61,7 @@ STATIC const pyb_pwm_obj_t machine_pwm_obj[] = { void pwm_init0(void) { // reset the PWM handles - #if MICROPY_HW_PWM0 + #ifdef MICROPY_HW_PWM0_NAME memset(&PWMHandle0, 0, sizeof(PWM_HandleTypeDef)); PWMHandle0.instance = PWM0; #endif @@ -165,13 +170,22 @@ STATIC mp_obj_t machine_pwm_deinit(mp_obj_t self) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pwm_deinit_obj, machine_pwm_deinit); +STATIC mp_obj_t machine_pwm_freq(size_t n_args, const mp_obj_t *args) { + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_pwm_freq_obj, 1, 2, machine_pwm_freq); + +STATIC mp_obj_t machine_pwm_duty(size_t n_args, const mp_obj_t *args) { + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_pwm_duty_obj, 1, 2, machine_pwm_duty); + STATIC const mp_rom_map_elem_t machine_pwm_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_pwm_init_obj) }, { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_pwm_deinit_obj) }, - { MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&mp_machine_pwm_start_obj) }, - { MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&mp_machine_pwm_stop_obj) }, - { MP_ROM_QSTR(MP_QSTR_update), MP_ROM_PTR(&mp_machine_pwm_update_obj) }, + { MP_ROM_QSTR(MP_QSTR_freq), MP_ROM_PTR(&mp_machine_pwm_freq_obj) }, + { MP_ROM_QSTR(MP_QSTR_duty), MP_ROM_PTR(&mp_machine_pwm_duty_obj) }, }; STATIC MP_DEFINE_CONST_DICT(machine_pwm_locals_dict, machine_pwm_locals_dict_table); From abd945fde1d8627244e946762f4fb36f2b9a25f0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 17 Dec 2016 01:05:43 +0100 Subject: [PATCH 023/809] nrf5/hal: Updating PWM header file with init function prototype. Also added PWM_HandleTypeDef structure that can be used in the pwm python module. --- nrf5/hal/hal_pwm.h | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/nrf5/hal/hal_pwm.h b/nrf5/hal/hal_pwm.h index f60fb707d8..739a0b6829 100644 --- a/nrf5/hal/hal_pwm.h +++ b/nrf5/hal/hal_pwm.h @@ -31,11 +31,9 @@ #include "nrf.h" -#if NRF51 +// TODO: nrf51 series need Soft PWM. Not part of HAL. -// TODO: create software PWM. - -#elif NRF52 +#if NRF52 #define PWM0 ((NRF_PWM_Type *)NRF_PWM0_BASE) #define PWM0_IRQ_NUM PWM1_IRQn @@ -58,4 +56,17 @@ typedef struct { uint8_t pwm_pin; } hal_pwm_init_t; +/** + * @brief PWM handle Structure definition + */ +typedef struct __PWM_HandleTypeDef +{ + NRF_PWM_Type *instance; /* PWM registers base address */ + hal_pwm_init_t init; /* PWM initialization parameters */ +} PWM_HandleTypeDef; + + +void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init); + + #endif // HAL_PWM_H__ From 3bf2ca05f1205bc1d2f9af56c8654226ec236cd0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 17 Dec 2016 01:14:50 +0100 Subject: [PATCH 024/809] nrf5/pwm: Adding pwm to modmachine.c --- nrf5/modmachine.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/modmachine.c b/nrf5/modmachine.c index a1b28cdd2d..5bcf241d1f 100644 --- a/nrf5/modmachine.c +++ b/nrf5/modmachine.c @@ -39,6 +39,7 @@ #include "gccollect.h" #include "pin.h" #include "spi.h" +#include "pwm.h" #define PYB_RESET_HARD (0) #define PYB_RESET_WDT (1) @@ -164,6 +165,10 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { #if MICROPY_PY_MACHINE_SPI { MP_OBJ_NEW_QSTR(MP_QSTR_SPI), (mp_obj_t)&machine_hard_spi_type }, #endif + +#if MICROPY_PY_MACHINE_PWM + { MP_OBJ_NEW_QSTR(MP_QSTR_PWM), (mp_obj_t)&machine_hard_pwm_type }, +#endif { MP_OBJ_NEW_QSTR(MP_QSTR_HARD_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_HARD) }, { MP_OBJ_NEW_QSTR(MP_QSTR_WDT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_WDT) }, { MP_OBJ_NEW_QSTR(MP_QSTR_SOFT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_SOFT) }, From 18f528eceb2866560423450954f847e40fe16054 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 17 Dec 2016 01:16:38 +0100 Subject: [PATCH 025/809] nrf5: Only enable hal_pwm.c if nrf52 target as nrf51 must have a sw implementation. --- nrf5/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index fa5b262acc..439c8d32bc 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -114,8 +114,13 @@ SRC_HAL = $(addprefix hal/,\ hal_spi.c \ hal_spie.c \ hal_time.c \ + ) + +ifeq ($(MCU_VARIANT), nrf52) +SRC_HAL += $(addprefix hal/,\ hal_pwm.c \ ) +endif SRC_C += \ main.c \ From 275bf468317a5da62efaefc1519f9584f3883dfb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 17 Dec 2016 01:19:44 +0100 Subject: [PATCH 026/809] nrf51: Disable MICROPY_PY_MACHINE_PWM for now in all nrf51 target boards as sw impl. is not yet included in the repo. --- nrf5/boards/pca10000/mpconfigboard.h | 1 + nrf5/boards/pca10001/mpconfigboard.h | 2 ++ nrf5/boards/pca10028/mpconfigboard.h | 2 ++ nrf5/boards/pca10031/mpconfigboard.h | 2 ++ 4 files changed, 7 insertions(+) diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf5/boards/pca10000/mpconfigboard.h index 2e2326da20..f149238edd 100644 --- a/nrf5/boards/pca10000/mpconfigboard.h +++ b/nrf5/boards/pca10000/mpconfigboard.h @@ -31,6 +31,7 @@ #define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" #define MICROPY_PY_MACHINE_SPI (0) +#define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) diff --git a/nrf5/boards/pca10001/mpconfigboard.h b/nrf5/boards/pca10001/mpconfigboard.h index 4e723efcb7..1438a3fff3 100644 --- a/nrf5/boards/pca10001/mpconfigboard.h +++ b/nrf5/boards/pca10001/mpconfigboard.h @@ -30,6 +30,8 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" +#define MICROPY_PY_MACHINE_PWM (0) + #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index b854e685e3..4b0170aac3 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -30,6 +30,8 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" +#define MICROPY_PY_MACHINE_PWM (0) + #define MICROPY_PY_USOCKET (0) #define MICROPY_PY_NETWORK (0) diff --git a/nrf5/boards/pca10031/mpconfigboard.h b/nrf5/boards/pca10031/mpconfigboard.h index 743375ea0e..2c645a0ff0 100644 --- a/nrf5/boards/pca10031/mpconfigboard.h +++ b/nrf5/boards/pca10031/mpconfigboard.h @@ -30,6 +30,8 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" +#define MICROPY_PY_MACHINE_PWM (0) + #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) From dd9812e1e9b8696cde8d84c13faa72c5876f79f8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 17 Dec 2016 01:21:32 +0100 Subject: [PATCH 027/809] nrf52: Enable PWM HAL for both pca10040 (nrf52832) and pca10056 (nrf52840). --- nrf5/boards/pca10040/nrf52_hal_conf.h | 2 +- nrf5/boards/pca10056/nrf52_hal_conf.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/pca10040/nrf52_hal_conf.h b/nrf5/boards/pca10040/nrf52_hal_conf.h index e98a61e044..1ea1005c3c 100644 --- a/nrf5/boards/pca10040/nrf52_hal_conf.h +++ b/nrf5/boards/pca10040/nrf52_hal_conf.h @@ -6,6 +6,6 @@ #define HAL_SPI_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED -// #define HAL_PWM_MODULE_ENABLED +#define HAL_PWM_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ diff --git a/nrf5/boards/pca10056/nrf52_hal_conf.h b/nrf5/boards/pca10056/nrf52_hal_conf.h index 313954735a..3cfe4c0321 100644 --- a/nrf5/boards/pca10056/nrf52_hal_conf.h +++ b/nrf5/boards/pca10056/nrf52_hal_conf.h @@ -6,6 +6,6 @@ // #define HAL_SPI_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED -// #define HAL_PWM_MODULE_ENABLED +#define HAL_PWM_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ From b350dc5198347e058339cb53a2aeaaedb0c96491 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 17 Dec 2016 01:27:58 +0100 Subject: [PATCH 028/809] nrf52: Set names to be used on PWM0-2 in board config. For nrf52840, the PWM3 is excluded as repo does not have latest headers to reflect this yet. Bump up to be done soon. --- nrf5/boards/pca10040/mpconfigboard.h | 3 +++ nrf5/boards/pca10056/mpconfigboard.h | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 8dd0d43d0c..0b78f700a3 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -64,5 +64,8 @@ #define MICROPY_HW_SPI0_MISO (24) // A24 (Arduino D12) #define MICROPY_HW_SPI0_NSS (22) // A22 (Arduino D10) +#define MICROPY_HW_PWM0_NAME "PWM0" +#define MICROPY_HW_PWM1_NAME "PWM1" +#define MICROPY_HW_PWM2_NAME "PWM2" #define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index 35d02ad232..feee311ddf 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -59,4 +59,11 @@ #define MICROPY_HW_UART1_RTS (5) #define MICROPY_HW_UART1_HWFC (1) +#define MICROPY_HW_PWM0_NAME "PWM0" +#define MICROPY_HW_PWM1_NAME "PWM1" +#define MICROPY_HW_PWM2_NAME "PWM2" +#if 0 +#define MICROPY_HW_PWM3_NAME "PWM3" +#endif + #define HELP_TEXT_BOARD_LED "1,2,3,4" From b4dc9254ac908b3721dd7e855633918c51c95cac Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 17 Dec 2016 01:29:12 +0100 Subject: [PATCH 029/809] nrf5: Updating mpconfigport.h to set a default for PWM machine module to be enabled by default, if not disabled in a board config. Refactoring order in the file. --- nrf5/mpconfigport.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index b43dc9940e..e76205050b 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -101,12 +101,17 @@ #define MICROPY_PY_MACHINE_PULSE (0) #define MICROPY_PY_MACHINE_I2C (0) +#define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) +#define MICROPY_PY_FRAMEBUF (0) + + #ifndef MICROPY_PY_MACHINE_SPI #define MICROPY_PY_MACHINE_SPI (1) #endif -#define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) -#define MICROPY_PY_FRAMEBUF (0) +#ifndef MICROPY_PY_MACHINE_PWM +#define MICROPY_PY_MACHINE_PWM (1) +#endif #ifndef MICROPY_PY_USOCKET #define MICROPY_PY_USOCKET (1) From faa1b778445e9aecf96a44d7c59ab7bd8c3a648b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 19 Dec 2016 17:09:46 +0100 Subject: [PATCH 030/809] nrf5/pwm: Adding api to initialize pwm instances. --- nrf5/pwm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/pwm.h b/nrf5/pwm.h index c77f6fede1..c79668520d 100644 --- a/nrf5/pwm.h +++ b/nrf5/pwm.h @@ -24,4 +24,6 @@ * THE SOFTWARE. */ +void pwm_init0(void); + extern const mp_obj_type_t machine_hard_pwm_type; From db1faf85f7c8531ce03c2d41fa8520f4ed4ec01a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 19 Dec 2016 17:10:48 +0100 Subject: [PATCH 031/809] nrf5/pwm: Initializing pwm instances in main.c if enabled by MICROPY_PY_MACHINE_PWM. --- nrf5/main.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/nrf5/main.c b/nrf5/main.c index 290926b76f..1c0c71625d 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -47,6 +47,7 @@ #include "nrf.h" #include "pin.h" #include "spi.h" +#include "pwm.h" #if (BLUETOOTH_SD == 132) #include "nrf52_ble.h" @@ -98,10 +99,15 @@ int main(int argc, char **argv) { readline_init0(); pin_init0(); + #if MICROPY_PY_MACHINE_SPI spi_init0(); #endif +#if MICROPY_PY_MACHINE_PWM + pwm_init0(); +#endif + /* extint_init0(); timer_init0(); From 099922610313e811f6e50a366995990ff4e5a3c1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 20 Dec 2016 23:15:26 +0100 Subject: [PATCH 032/809] nrf5/pwm: Updating pwm module with freq function which re-initilises the PWM instance such that new frequency will be applied. --- nrf5/hal/hal_pwm.c | 50 +++++++++++++++++++++++-- nrf5/hal/hal_pwm.h | 21 +++++++++++ nrf5/pwm.c | 93 ++++++++++++++++++++++++++++++++++++++++------ 3 files changed, 149 insertions(+), 15 deletions(-) diff --git a/nrf5/hal/hal_pwm.c b/nrf5/hal/hal_pwm.c index a1c6ad4aed..cf678c0ff2 100644 --- a/nrf5/hal/hal_pwm.c +++ b/nrf5/hal/hal_pwm.c @@ -35,10 +35,22 @@ #define PWM_COUNTER_TOP 16000 // 16MHz divided by 16000-> 1ms volatile uint16_t g_pwm_seq[4]; +volatile uint16_t g_pwm_period; + +static const uint32_t hal_pwm_frequency_lookup[] = { + PWM_PRESCALER_PRESCALER_DIV_1, // 16MHz + PWM_PRESCALER_PRESCALER_DIV_2, // 8MHz + PWM_PRESCALER_PRESCALER_DIV_4, // 4MHz + PWM_PRESCALER_PRESCALER_DIV_8, // 2MHz + PWM_PRESCALER_PRESCALER_DIV_16, // 1MHz + PWM_PRESCALER_PRESCALER_DIV_32, // 500kHz + PWM_PRESCALER_PRESCALER_DIV_64, // 250kHz + PWM_PRESCALER_PRESCALER_DIV_128 // 125kHz +}; void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init) { - - uint16_t duty_cycle = ((PWM_COUNTER_TOP*50)/100); + g_pwm_period = p_pwm_init->period; + uint16_t duty_cycle = ((g_pwm_period * p_pwm_init->duty)/100); g_pwm_seq[0] = duty_cycle; g_pwm_seq[1] = duty_cycle; @@ -50,8 +62,8 @@ void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init) p_instance->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos); p_instance->MODE = (PWM_MODE_UPDOWN_Up << PWM_MODE_UPDOWN_Pos); - p_instance->PRESCALER = (PWM_PRESCALER_PRESCALER_DIV_1 << PWM_PRESCALER_PRESCALER_Pos); - p_instance->COUNTERTOP = (PWM_COUNTER_TOP << PWM_COUNTERTOP_COUNTERTOP_Pos); //1 msec + p_instance->PRESCALER = (hal_pwm_frequency_lookup[p_pwm_init->freq] << PWM_PRESCALER_PRESCALER_Pos); + p_instance->COUNTERTOP = (p_pwm_init->period << PWM_COUNTERTOP_COUNTERTOP_Pos); p_instance->LOOP = (PWM_LOOP_CNT_Disabled << PWM_LOOP_CNT_Pos); p_instance->DECODER = (PWM_DECODER_LOAD_Individual << PWM_DECODER_LOAD_Pos) | (PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos); @@ -63,4 +75,34 @@ void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init) p_instance->TASKS_SEQSTART[0] = 1; } +void hal_pwm_start(NRF_PWM_Type * p_instance) { + // p_instance->TASKS_SEQSTART[0] = 1; +} + +void hal_pwm_stop(NRF_PWM_Type * p_instance) { + // p_instance->TASKS_STOP = 1; +} + +void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq) { +#if 0 + p_instance->PRESCALER = (hal_pwm_frequency_lookup[freq] << PWM_PRESCALER_PRESCALER_Pos); +#endif +} + +void hal_pwm_period_set(NRF_PWM_Type * p_instance, uint16_t period) { +#if 0 + g_pwm_period = period; + p_instance->COUNTERTOP = (g_pwm_period << PWM_COUNTERTOP_COUNTERTOP_Pos); +#endif +} + +void hal_pwm_duty_set(NRF_PWM_Type * p_instance, uint8_t duty) { +#if 0 + uint16_t duty_cycle = ((g_pwm_period * duty)/100); + + g_pwm_seq[0] = duty_cycle; + g_pwm_seq[1] = duty_cycle; +#endif +} + #endif // HAL_PWM_MODULE_ENABLED diff --git a/nrf5/hal/hal_pwm.h b/nrf5/hal/hal_pwm.h index 739a0b6829..eb69731149 100644 --- a/nrf5/hal/hal_pwm.h +++ b/nrf5/hal/hal_pwm.h @@ -51,9 +51,25 @@ #error "Device not supported." #endif +/** + * @brief PWM frequency type definition + */ +typedef enum { + HAL_PWM_FREQ_16Mhz = 0, + HAL_PWM_FREQ_8Mhz, + HAL_PWM_FREQ_4Mhz, + HAL_PWM_FREQ_2Mhz, + HAL_PWM_FREQ_1Mhz, + HAL_PWM_FREQ_500khz, + HAL_PWM_FREQ_250khz, + HAL_PWM_FREQ_125khz +} hal_pwm_freq_t; typedef struct { uint8_t pwm_pin; + hal_pwm_freq_t freq; + uint8_t duty; + uint16_t period; } hal_pwm_init_t; /** @@ -68,5 +84,10 @@ typedef struct __PWM_HandleTypeDef void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init); +void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq); + +void hal_pwm_period_set(NRF_PWM_Type * p_instance, uint16_t period); + +void hal_pwm_duty_set(NRF_PWM_Type * p_instance, uint8_t duty); #endif // HAL_PWM_H__ diff --git a/nrf5/pwm.c b/nrf5/pwm.c index 60326c9f43..32d4586718 100644 --- a/nrf5/pwm.c +++ b/nrf5/pwm.c @@ -108,7 +108,10 @@ STATIC void pwm_print(const mp_print_t *print, PWM_HandleTypeDef *pwm, bool lega // for make_new enum { ARG_NEW_id, - ARG_NEW_pin + ARG_NEW_pin, + ARG_NEW_freq, + ARG_NEW_period, + ARG_NEW_duty, }; // for init @@ -116,16 +119,25 @@ enum { ARG_INIT_pin }; +// for freq +enum { + ARG_FREQ_freq +}; + STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args); STATIC void machine_hard_pwm_init(mp_obj_t self, mp_arg_val_t *args); STATIC void machine_hard_pwm_deinit(mp_obj_t self); +STATIC mp_obj_t machine_hard_pwm_freq(mp_obj_t self, mp_arg_val_t *args); /* common code for both soft and hard implementations *************************/ STATIC mp_obj_t machine_pwm_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, - { MP_QSTR_pin, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} } + { MP_QSTR_pin, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_period, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_duty, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, }; // parse args @@ -170,10 +182,29 @@ STATIC mp_obj_t machine_pwm_deinit(mp_obj_t self) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pwm_deinit_obj, machine_pwm_deinit); -STATIC mp_obj_t machine_pwm_freq(size_t n_args, const mp_obj_t *args) { - return mp_const_none; +STATIC mp_obj_t machine_pwm_freq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_freq, MP_ARG_INT, {.u_int = -1} }, + }; + + mp_obj_t self = pos_args[0]; + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (mp_obj_get_type(self) == &machine_hard_pwm_type) { + machine_hard_pwm_freq(self, args); + } else { + // soft pwm + } + + return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_pwm_freq_obj, 1, 2, machine_pwm_freq); +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(mp_machine_pwm_freq_obj, 1, machine_pwm_freq); + +STATIC mp_obj_t machine_pwm_period(size_t n_args, const mp_obj_t *args) { + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_pwm_period_obj, 1, 2, machine_pwm_period); STATIC mp_obj_t machine_pwm_duty(size_t n_args, const mp_obj_t *args) { return mp_const_none; @@ -185,7 +216,16 @@ STATIC const mp_rom_map_elem_t machine_pwm_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_pwm_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_freq), MP_ROM_PTR(&mp_machine_pwm_freq_obj) }, + { MP_ROM_QSTR(MP_QSTR_period), MP_ROM_PTR(&mp_machine_pwm_period_obj) }, { MP_ROM_QSTR(MP_QSTR_duty), MP_ROM_PTR(&mp_machine_pwm_duty_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_16MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_16Mhz) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_8MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_8Mhz) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_4MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_4Mhz) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_2MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_2Mhz) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_1MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_1Mhz) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_500KHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_500khz) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_250KHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_250khz) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_125KHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_125khz) }, }; STATIC MP_DEFINE_CONST_DICT(machine_pwm_locals_dict, machine_pwm_locals_dict_table); @@ -211,16 +251,33 @@ STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args) { int pwm_id = pwm_find(args[ARG_NEW_id].u_obj); const machine_hard_pwm_obj_t *self = &machine_hard_pwm_obj[pwm_id]; - hal_pwm_init_t pwm_init_conf; - - // here we would check the sck/mosi/miso pins and configure them + // check if PWM pin is set if (args[ARG_NEW_pin].u_obj != MP_OBJ_NULL) { - pwm_init_conf.pwm_pin = mp_obj_get_int(args[ARG_NEW_pin].u_obj); + self->pyb->pwm->init.pwm_pin = mp_obj_get_int(args[ARG_NEW_pin].u_obj); } else { // TODO: raise exception. } - - hal_pwm_init(self->pyb->pwm->instance, &pwm_init_conf); + + if (args[ARG_NEW_freq].u_obj != MP_OBJ_NULL) { + self->pyb->pwm->init.freq = mp_obj_get_int(args[ARG_NEW_freq].u_obj); + } else { + self->pyb->pwm->init.freq = 50; // 50 Hz by default. + } + + if (args[ARG_NEW_period].u_obj != MP_OBJ_NULL) { + self->pyb->pwm->init.period = mp_obj_get_int(args[ARG_NEW_period].u_obj); + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "PWM period has to be within 16000 frequence cycles", self->pyb->pwm->init.period)); + } + + if (args[ARG_NEW_duty].u_obj != MP_OBJ_NULL) { + self->pyb->pwm->init.duty = mp_obj_get_int(args[ARG_NEW_duty].u_obj); + } else { + self->pyb->pwm->init.duty = 50; // 50% by default. + } + + hal_pwm_init(self->pyb->pwm->instance, &self->pyb->pwm->init); return MP_OBJ_FROM_PTR(self); } @@ -233,6 +290,20 @@ STATIC void machine_hard_pwm_deinit(mp_obj_t self_in) { pwm_deinit(self->pyb->pwm); } +STATIC mp_obj_t machine_hard_pwm_freq(mp_obj_t self_in, mp_arg_val_t *args) { + machine_hard_pwm_obj_t *self = self_in; + + if (args[ARG_FREQ_freq].u_int != -1) { + self->pyb->pwm->init.freq = args[ARG_FREQ_freq].u_int; + hal_pwm_init(self->pyb->pwm->instance, &self->pyb->pwm->init); + } else { + return MP_OBJ_NEW_SMALL_INT(self->pyb->pwm->init.freq); + } + + return mp_const_none; +} + + const mp_obj_type_t machine_hard_pwm_type = { { &mp_type_type }, .name = MP_QSTR_PWM, From 2db3f0deb717fbd6b81222eb015c8dc077858809 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 20 Dec 2016 23:21:17 +0100 Subject: [PATCH 033/809] nrf5/modules: Adding a python test file with function to dim a specific led (17). --- nrf5/modules/test.py | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 nrf5/modules/test.py diff --git a/nrf5/modules/test.py b/nrf5/modules/test.py new file mode 100644 index 0000000000..db1af5af88 --- /dev/null +++ b/nrf5/modules/test.py @@ -0,0 +1,10 @@ +import time +from machine import PWM + +def pulse(): + for i in range(0, 101): + p = PWM(0, pin=17, freq=50, duty=i, period=16000) + time.sleep_ms(10) + for i in range(0, 101): + p = PWM(0, pin=17, freq=50, duty=100-i, period=16000) + time.sleep_ms(10) From 3191a31ce890e764821ea8a04316700c0dd93e62 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 24 Dec 2016 00:30:35 +0100 Subject: [PATCH 034/809] nrf5/modules: updating test python file with correct PWM frequency type. --- nrf5/modules/test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/test.py b/nrf5/modules/test.py index db1af5af88..87af84edf6 100644 --- a/nrf5/modules/test.py +++ b/nrf5/modules/test.py @@ -3,8 +3,8 @@ from machine import PWM def pulse(): for i in range(0, 101): - p = PWM(0, pin=17, freq=50, duty=i, period=16000) + p = PWM(0, pin=17, freq=PWM.FREQ_16MHZ, duty=i, period=16000) time.sleep_ms(10) for i in range(0, 101): - p = PWM(0, pin=17, freq=50, duty=100-i, period=16000) + p = PWM(0, pin=17, freq=PWM.FREQ_16MHZ, duty=100-i, period=16000) time.sleep_ms(10) From d75912388617d38096e26250b23c476da8aff0cc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 24 Dec 2016 01:15:37 +0100 Subject: [PATCH 035/809] nrf5/pwm: Switching from hardcoded pin number to Pin object type as input to the new() function. Also changing the parameter from kw to arg. --- nrf5/pwm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nrf5/pwm.c b/nrf5/pwm.c index 32d4586718..7d77a00237 100644 --- a/nrf5/pwm.c +++ b/nrf5/pwm.c @@ -134,7 +134,7 @@ STATIC mp_obj_t machine_hard_pwm_freq(mp_obj_t self, mp_arg_val_t *args); STATIC mp_obj_t machine_pwm_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, - { MP_QSTR_pin, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_period, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_duty, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, @@ -253,7 +253,8 @@ STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args) { // check if PWM pin is set if (args[ARG_NEW_pin].u_obj != MP_OBJ_NULL) { - self->pyb->pwm->init.pwm_pin = mp_obj_get_int(args[ARG_NEW_pin].u_obj); + pin_obj_t *pin_obj = args[ARG_NEW_pin].u_obj; + self->pyb->pwm->init.pwm_pin = pin_obj->pin; } else { // TODO: raise exception. } From c1c78404b65c3462e69f2b68a4459da83e0ddaf5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 24 Dec 2016 01:16:23 +0100 Subject: [PATCH 036/809] nrf5/modules: Updating pulse example to work with Pin object instead of hard coded pin number. --- nrf5/modules/test.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/test.py b/nrf5/modules/test.py index 87af84edf6..cabc279ae7 100644 --- a/nrf5/modules/test.py +++ b/nrf5/modules/test.py @@ -1,10 +1,10 @@ import time -from machine import PWM +from machine import PWM, Pin def pulse(): for i in range(0, 101): - p = PWM(0, pin=17, freq=PWM.FREQ_16MHZ, duty=i, period=16000) + p = PWM(0, Pin("A17"), freq=PWM.FREQ_16MHZ, duty=i, period=16000) time.sleep_ms(10) for i in range(0, 101): - p = PWM(0, pin=17, freq=PWM.FREQ_16MHZ, duty=100-i, period=16000) + p = PWM(0, Pin("A17"), freq=PWM.FREQ_16MHZ, duty=100-i, period=16000) time.sleep_ms(10) From 1264122e76b8f356067bf83ac02e88f8983f6142 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 25 Dec 2016 18:09:33 +0100 Subject: [PATCH 037/809] nrf5/hal: Adding skeleton files for rtc and timer driver. --- nrf5/hal/hal_rtc.c | 33 +++++++++++++++++++++++++ nrf5/hal/hal_rtc.h | 52 +++++++++++++++++++++++++++++++++++++++ nrf5/hal/hal_timer.c | 32 ++++++++++++++++++++++++ nrf5/hal/hal_timer.h | 58 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 175 insertions(+) create mode 100644 nrf5/hal/hal_rtc.c create mode 100644 nrf5/hal/hal_rtc.h create mode 100644 nrf5/hal/hal_timer.c create mode 100644 nrf5/hal/hal_timer.h diff --git a/nrf5/hal/hal_rtc.c b/nrf5/hal/hal_rtc.c new file mode 100644 index 0000000000..626f7c2c10 --- /dev/null +++ b/nrf5/hal/hal_rtc.c @@ -0,0 +1,33 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "hal_rtc.h" + +#ifdef HAL_RTC_MODULE_ENABLED + +#endif // HAL_RTC_MODULE_ENABLED + diff --git a/nrf5/hal/hal_rtc.h b/nrf5/hal/hal_rtc.h new file mode 100644 index 0000000000..5c21f9bf29 --- /dev/null +++ b/nrf5/hal/hal_rtc.h @@ -0,0 +1,52 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_RTC_H__ +#define HAL_RTC_H__ + +#include "nrf.h" + +#if NRF51 + +#define RTC0 ((NRF_RTC_Type *) NRF_RTC0) +#define RTC0_IRQ_NUM RTC0_IRQn +#define RTC1 ((NRF_RTC_Type *) NRF_RTC1) +#define RTC1_IRQ_NUM RTC1_IRQn + +#elif NRF52 + +#define RTC0 ((NRF_RTC_Type *) NRF_RTC0) +#define RTC0_IRQ_NUM RTC0_IRQn +#define RTC1 ((NRF_RTC_Type *) NRF_RTC1) +#define RTC1_IRQ_NUM RTC1_IRQn +#define RTC2 ((NRF_RTC_Type *) NRF_RTC2) +#define RTC2_IRQ_NUM RTC2_IRQn + +#else +#error "Device not supported." +#endif + +#endif // HAL_RTC_H__ diff --git a/nrf5/hal/hal_timer.c b/nrf5/hal/hal_timer.c new file mode 100644 index 0000000000..900be82123 --- /dev/null +++ b/nrf5/hal/hal_timer.c @@ -0,0 +1,32 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "hal_timer.h" + +#ifdef HAL_TIMER_MODULE_ENABLED + +#endif // HAL_TIMER_MODULE_ENABLED diff --git a/nrf5/hal/hal_timer.h b/nrf5/hal/hal_timer.h new file mode 100644 index 0000000000..b3d7149223 --- /dev/null +++ b/nrf5/hal/hal_timer.h @@ -0,0 +1,58 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_TIMER_H__ +#define HAL_TIMER_H__ + +#include "nrf.h" + +#if NRF51 + +#define TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0) +#define TIMER0_IRQ_NUM TIMER0_IRQn +#define TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1) +#define TIMER1_IRQ_NUM TIMER1_IRQn +#define TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2) +#define TIMER2_IRQ_NUM TIMER2_IRQn + +#elif NRF52 + +#define TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0) +#define TIMER0_IRQ_NUM TIMER0_IRQn +#define TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1) +#define TIMER1_IRQ_NUM TIMER1_IRQn +#define TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2) +#define TIMER2_IRQ_NUM TIMER2_IRQn +#define TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3) +#define TIMER3_IRQ_NUM TIMER3_IRQn +#define TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4) +#define TIMER4_IRQ_NUM TIMER4_IRQn + +#else +#error "Device not supported." +#endif + +#endif // HAL_TIMER_H__ From 1e79ccf305cebcebb58ca86b15992c62c9f3282b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 25 Dec 2016 18:12:51 +0100 Subject: [PATCH 038/809] nrf5: Adding rtc and timer hal to Makefile. --- nrf5/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 439c8d32bc..67c70d02b8 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -114,6 +114,8 @@ SRC_HAL = $(addprefix hal/,\ hal_spi.c \ hal_spie.c \ hal_time.c \ + hal_rtc.c \ + hal_timer.c \ ) ifeq ($(MCU_VARIANT), nrf52) From 5c327f2f2f7f783bdacb496d23f879f5f8867c6f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 25 Dec 2016 18:15:32 +0100 Subject: [PATCH 039/809] nrf/boards: Adding RTC and TIMER hal to be linked in when implemented. Enable one board for nrf51 and one for nrf52 for ease of debugging when implementing the hal. --- nrf5/boards/pca10028/nrf51_hal_conf.h | 2 ++ nrf5/boards/pca10040/nrf52_hal_conf.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/nrf5/boards/pca10028/nrf51_hal_conf.h b/nrf5/boards/pca10028/nrf51_hal_conf.h index 67cbc983ba..4bd11e1dd5 100644 --- a/nrf5/boards/pca10028/nrf51_hal_conf.h +++ b/nrf5/boards/pca10028/nrf51_hal_conf.h @@ -4,5 +4,7 @@ #define HAL_UART_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10040/nrf52_hal_conf.h b/nrf5/boards/pca10040/nrf52_hal_conf.h index 1ea1005c3c..f19e49744b 100644 --- a/nrf5/boards/pca10040/nrf52_hal_conf.h +++ b/nrf5/boards/pca10040/nrf52_hal_conf.h @@ -7,5 +7,7 @@ // #define HAL_SPIE_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED #define HAL_PWM_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ From 8cce98576504cb2dd8bbfb92d3ce375224222fb9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 14:03:50 +0100 Subject: [PATCH 040/809] nrf5/timer: Adding skeleton for machine timer module for nrf51/52. --- nrf5/timer.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++ nrf5/timer.h | 36 ++++++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 nrf5/timer.c create mode 100644 nrf5/timer.h diff --git a/nrf5/timer.c b/nrf5/timer.c new file mode 100644 index 0000000000..de9fb62fb8 --- /dev/null +++ b/nrf5/timer.c @@ -0,0 +1,86 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "timer.h" +#include "hal_timer.h" + +#if MICROPY_PY_MACHINE_TIMER + +typedef struct _machine_timer_obj_t { + mp_obj_base_t base; + Timer_HandleTypeDef *timer; +} machine_timer_obj_t; + +Timer_HandleTypeDef TimerHandle0 = {.instance = NULL}; +Timer_HandleTypeDef TimerHandle1 = {.instance = NULL}; +Timer_HandleTypeDef TimerHandle2 = {.instance = NULL}; + +STATIC const machine_timer_obj_t machine_timer_obj[] = { + {{&machine_timer_type}, &TimerHandle0}, + {{&machine_timer_type}, &TimerHandle1}, + {{&machine_timer_type}, &TimerHandle2}, +}; + +void timer_init0(void) { + // reset the Timer handles + memset(&TimerHandle0, 0, sizeof(Timer_HandleTypeDef)); + TimerHandle0.instance = TIMER0; + memset(&TimerHandle1, 0, sizeof(Timer_HandleTypeDef)); + TimerHandle0.instance = TIMER1; + memset(&TimerHandle2, 0, sizeof(Timer_HandleTypeDef)); + TimerHandle0.instance = TIMER2; +} + +#if 0 +STATIC int timer_find(mp_obj_t id) { + // given an integer id + int timer_id = mp_obj_get_int(id); + if (timer_id >= 0 && timer_id <= MP_ARRAY_SIZE(machine_timer_obj) + && machine_timer_obj[timer_id].timer != NULL) { + return timer_id; + } + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Timer(%d) does not exist", timer_id)); +} +#endif + +const mp_obj_type_t machine_timer_type = { + { &mp_type_type }, + .name = MP_QSTR_Timer, +#if 0 + .print = machine_timer_print, + .make_new = machine_timer_make_new, + .locals_dict = (mp_obj_t)&machine_timer_locals_dict +#endif +}; + +#endif // MICROPY_PY_MACHINE_TIMER diff --git a/nrf5/timer.h b/nrf5/timer.h new file mode 100644 index 0000000000..7419b1fd85 --- /dev/null +++ b/nrf5/timer.h @@ -0,0 +1,36 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef TIMER_H__ +#define TIMER_H__ + +#include "hal_timer.h" + +extern const mp_obj_type_t machine_timer_type; + +void timer_init0(void); + +#endif // TIMER_H__ From 9b084fc376ab6568b10b7c543853e85df4a2a233 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:08:22 +0100 Subject: [PATCH 041/809] nrf5/hal: Adding structures and init function prototype to hal_timer.h. --- nrf5/hal/hal_timer.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/nrf5/hal/hal_timer.h b/nrf5/hal/hal_timer.h index b3d7149223..18905c9096 100644 --- a/nrf5/hal/hal_timer.h +++ b/nrf5/hal/hal_timer.h @@ -55,4 +55,22 @@ #error "Device not supported." #endif +/** + * @brief Timer Configuration Structure definition + */ +typedef struct { +} hal_timer_init_t; + +/** + * @brief Timer handle Structure definition + */ +typedef struct __Timer_HandleTypeDef +{ + NRF_TIMER_Type *instance; /* Timer registers base address */ + hal_timer_init_t init; /* Timer initialization parameters */ + uint8_t id; /* Timer instance id */ +} Timer_HandleTypeDef; + +void hal_timer_init(NRF_TIMER_Type * p_instance, hal_timer_init_t const * p_timer_init); + #endif // HAL_TIMER_H__ From 53fdcf91d7fae1d89d6a532bd470eccc400fae5a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:08:59 +0100 Subject: [PATCH 042/809] nrf5/hal: Adding empty init function in hal_timer.c --- nrf5/hal/hal_timer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nrf5/hal/hal_timer.c b/nrf5/hal/hal_timer.c index 900be82123..fbf3520fe7 100644 --- a/nrf5/hal/hal_timer.c +++ b/nrf5/hal/hal_timer.c @@ -29,4 +29,7 @@ #ifdef HAL_TIMER_MODULE_ENABLED +void hal_timer_init(NRF_TIMER_Type * p_instance, hal_timer_init_t const * p_timer_init) { +} + #endif // HAL_TIMER_MODULE_ENABLED From 9c828c7630c0a08729bab784afd639b12bac27eb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:13:09 +0100 Subject: [PATCH 043/809] nrf5/timer: Adding initializaton of id field for Timer_HandleTypeDef's. Adding simple print function. Adding make_new function. Enabling the functions in machine_timer_type. --- nrf5/timer.c | 49 ++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/nrf5/timer.c b/nrf5/timer.c index de9fb62fb8..b973800963 100644 --- a/nrf5/timer.c +++ b/nrf5/timer.c @@ -40,9 +40,9 @@ typedef struct _machine_timer_obj_t { Timer_HandleTypeDef *timer; } machine_timer_obj_t; -Timer_HandleTypeDef TimerHandle0 = {.instance = NULL}; -Timer_HandleTypeDef TimerHandle1 = {.instance = NULL}; -Timer_HandleTypeDef TimerHandle2 = {.instance = NULL}; +Timer_HandleTypeDef TimerHandle0 = {.instance = NULL, .id = 0}; +Timer_HandleTypeDef TimerHandle1 = {.instance = NULL, .id = 1}; +Timer_HandleTypeDef TimerHandle2 = {.instance = NULL, .id = 2}; STATIC const machine_timer_obj_t machine_timer_obj[] = { {{&machine_timer_type}, &TimerHandle0}, @@ -60,7 +60,6 @@ void timer_init0(void) { TimerHandle0.instance = TIMER2; } -#if 0 STATIC int timer_find(mp_obj_t id) { // given an integer id int timer_id = mp_obj_get_int(id); @@ -71,14 +70,50 @@ STATIC int timer_find(mp_obj_t id) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Timer(%d) does not exist", timer_id)); } -#endif + +STATIC void timer_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + machine_timer_obj_t *self = o; + mp_printf(print, "Timer(%u)", self->timer->id); +} + +/******************************************************************************/ +/* MicroPython bindings for machine API */ + +// for make_new +enum { + ARG_NEW_id, +}; + +STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { + // index -1 does not exist + return mp_const_none; + // TODO: raise exception + } + + // get static peripheral object + int timer_id = timer_find(args[ARG_NEW_id].u_obj); + const machine_timer_obj_t *self = &machine_timer_obj[timer_id]; + + hal_timer_init(self->timer->instance, &self->timer->init); + + return MP_OBJ_FROM_PTR(self); +} const mp_obj_type_t machine_timer_type = { { &mp_type_type }, .name = MP_QSTR_Timer, -#if 0 - .print = machine_timer_print, + .print = timer_print, .make_new = machine_timer_make_new, +#if 0 .locals_dict = (mp_obj_t)&machine_timer_locals_dict #endif }; From e4365fcac4560b5776222a8b197c232a932a09f2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:15:26 +0100 Subject: [PATCH 044/809] nrf5: Adding initialization of timer module if enabled by MICROPY_PY_MACHINE_TIMER. --- nrf5/main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/main.c b/nrf5/main.c index 1c0c71625d..eba42a4510 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -48,6 +48,7 @@ #include "pin.h" #include "spi.h" #include "pwm.h" +#include "timer.h" #if (BLUETOOTH_SD == 132) #include "nrf52_ble.h" @@ -108,6 +109,10 @@ int main(int argc, char **argv) { pwm_init0(); #endif +#if MICROPY_PY_MACHINE_TIMER + timer_init0(); +#endif + /* extint_init0(); timer_init0(); From 8e7f9d7c389f5a85165e48b60758a8611ece897a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:18:16 +0100 Subject: [PATCH 045/809] nrf5/boards: Enable MICROPY_PY_MACHINE_TIMER in pca10028 (nrf51) and pca10040 (nrf52) targets. --- nrf5/boards/pca10028/mpconfigboard.h | 1 + nrf5/boards/pca10040/mpconfigboard.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 4b0170aac3..3320afd2cb 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -31,6 +31,7 @@ #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" #define MICROPY_PY_MACHINE_PWM (0) +#define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_USOCKET (0) #define MICROPY_PY_NETWORK (0) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 0b78f700a3..910fb699c2 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -30,6 +30,8 @@ #define MICROPY_HW_MCU_NAME "NRF52832" #define MICROPY_PY_SYS_PLATFORM "nrf52-DK" +#define MICROPY_PY_MACHINE_TIMER (1) + #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) From a3cc6abba67615737bccebe360f79513a64d6b15 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:19:48 +0100 Subject: [PATCH 046/809] nrf5: Setting MICROPY_PY_MACHINE_TIMER to disabled by default (during development) in mpconfigport.h. This can be overriden by board config. --- nrf5/mpconfigport.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index e76205050b..f3dcc42ca1 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -113,6 +113,10 @@ #define MICROPY_PY_MACHINE_PWM (1) #endif +#ifndef MICROPY_PY_MACHINE_TIMER +#define MICROPY_PY_MACHINE_TIMER (0) +#endif + #ifndef MICROPY_PY_USOCKET #define MICROPY_PY_USOCKET (1) #endif From d79588ddf474f0b63d9442f3fd8f8da434dfcd24 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:20:36 +0100 Subject: [PATCH 047/809] nrf5: Adding timer.c which implements the machine timer module to be included in build. --- nrf5/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 67c70d02b8..2a1ddbc4a0 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -144,6 +144,7 @@ SRC_C += \ lexerfatfs.c \ modusocket.c \ modnetwork.c \ + timer.c \ #ifeq ($(SD), ) From bab030d793b9363888cfe5ae605e0dd2c30c006d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:46:23 +0100 Subject: [PATCH 048/809] nrf5/rtc: Adding skeleton for machine rtc module for nrf51/52. --- nrf5/rtc.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++++++ nrf5/rtc.h | 36 +++++++++++++++++ 2 files changed, 153 insertions(+) create mode 100644 nrf5/rtc.c create mode 100644 nrf5/rtc.h diff --git a/nrf5/rtc.c b/nrf5/rtc.c new file mode 100644 index 0000000000..3aae1e36fe --- /dev/null +++ b/nrf5/rtc.c @@ -0,0 +1,117 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "rtc.h" +#include "hal_rtc.h" + +#if MICROPY_PY_MACHINE_RTC + +typedef struct _machine_rtc_obj_t { + mp_obj_base_t base; + RTC_HandleTypeDef *rtc; +} machine_rtc_obj_t; + +RTC_HandleTypeDef RTCHandle0 = {.instance = NULL, .id = 0}; +RTC_HandleTypeDef RTCHandle1 = {.instance = NULL, .id = 1}; + +STATIC const machine_rtc_obj_t machine_rtc_obj[] = { + {{&machine_rtc_type}, &RTCHandle0}, + {{&machine_rtc_type}, &RTCHandle1}, +}; + +void rtc_init0(void) { + // reset the RTC handles + memset(&RTCHandle0, 0, sizeof(RTC_HandleTypeDef)); + RTCHandle0.instance = RTC0; + memset(&RTCHandle1, 0, sizeof(RTC_HandleTypeDef)); + RTCHandle0.instance = RTC1; +} + +STATIC int rtc_find(mp_obj_t id) { + // given an integer id + int rtc_id = mp_obj_get_int(id); + if (rtc_id >= 0 && rtc_id <= MP_ARRAY_SIZE(machine_rtc_obj) + && machine_rtc_obj[rtc_id].rtc != NULL) { + return rtc_id; + } + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "RTC(%d) does not exist", rtc_id)); +} + +STATIC void rtc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + machine_rtc_obj_t *self = o; + mp_printf(print, "RTC(%u)", self->rtc->id); +} + +/******************************************************************************/ +/* MicroPython bindings for machine API */ + +// for make_new +enum { + ARG_NEW_id, +}; + +STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { + // index -1 does not exist + return mp_const_none; + // TODO: raise exception + } + + // get static peripheral object + int rtc_id = rtc_find(args[ARG_NEW_id].u_obj); + const machine_rtc_obj_t *self = &machine_rtc_obj[rtc_id]; + + hal_rtc_init(self->rtc->instance, &self->rtc->init); + + return MP_OBJ_FROM_PTR(self); +} + +const mp_obj_type_t machine_rtc_type = { + { &mp_type_type }, + .name = MP_QSTR_RTC, + .print = rtc_print, + .make_new = machine_rtc_make_new, +#if 0 + .locals_dict = (mp_obj_t)&machine_rtc_locals_dict +#endif +}; + +#endif // MICROPY_PY_MACHINE_RTC diff --git a/nrf5/rtc.h b/nrf5/rtc.h new file mode 100644 index 0000000000..3aa22e262f --- /dev/null +++ b/nrf5/rtc.h @@ -0,0 +1,36 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RTC_H__ +#define RTC_H__ + +#include "hal_rtc.h" + +extern const mp_obj_type_t machine_rtc_type; + +void rtc_init0(void); + +#endif // RTC_H__ From d78d7177338861d4539d6646bf0c9378305af6f7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:47:56 +0100 Subject: [PATCH 049/809] nrf5: Setting MICROPY_PY_MACHINE_RTC to disabled by default (during development) in mpconfigport.h. This can be overriden by board config. --- nrf5/mpconfigport.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index f3dcc42ca1..88c220f3be 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -117,6 +117,10 @@ #define MICROPY_PY_MACHINE_TIMER (0) #endif +#ifndef MICROPY_PY_MACHINE_RTC +#define MICROPY_PY_MACHINE_RTC (0) +#endif + #ifndef MICROPY_PY_USOCKET #define MICROPY_PY_USOCKET (1) #endif From 22c62fb53f266156d4ae3915100b43ad523a5295 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:48:56 +0100 Subject: [PATCH 050/809] nrf5/hal: Adding structures and init function prototype to hal_rtc.h. --- nrf5/hal/hal_rtc.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/nrf5/hal/hal_rtc.h b/nrf5/hal/hal_rtc.h index 5c21f9bf29..4c4e9d1194 100644 --- a/nrf5/hal/hal_rtc.h +++ b/nrf5/hal/hal_rtc.h @@ -49,4 +49,22 @@ #error "Device not supported." #endif +/** + * @brief RTC Configuration Structure definition + */ +typedef struct { +} hal_rtc_init_t; + +/** + * @brief RTC handle Structure definition + */ +typedef struct __RTC_HandleTypeDef +{ + NRF_RTC_Type *instance; /* RTC registers base address */ + hal_rtc_init_t init; /* RTC initialization parameters */ + uint8_t id; /* RTC instance id */ +} RTC_HandleTypeDef; + +void hal_rtc_init(NRF_RTC_Type * p_instance, hal_rtc_init_t const * p_rtc_init); + #endif // HAL_RTC_H__ From c2d2958205bad9430d44ba5faefd976244290eb6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:49:27 +0100 Subject: [PATCH 051/809] nrf5/hal: Adding empty init function in hal_rtc.c --- nrf5/hal/hal_rtc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nrf5/hal/hal_rtc.c b/nrf5/hal/hal_rtc.c index 626f7c2c10..9f3bef48cd 100644 --- a/nrf5/hal/hal_rtc.c +++ b/nrf5/hal/hal_rtc.c @@ -29,5 +29,8 @@ #ifdef HAL_RTC_MODULE_ENABLED +void hal_rtc_init(NRF_RTC_Type * p_instance, hal_rtc_init_t const * p_rtc_init) { +} + #endif // HAL_RTC_MODULE_ENABLED From 46ddf2ed703b8e3ffd7e50f42fbff569759e2135 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:50:59 +0100 Subject: [PATCH 052/809] nrf5/boards: Enable MICROPY_PY_MACHINE_RTC in pca10028 (nrf51) and pca10040 (nrf52) targets. --- nrf5/boards/pca10028/mpconfigboard.h | 1 + nrf5/boards/pca10040/mpconfigboard.h | 1 + 2 files changed, 2 insertions(+) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 3320afd2cb..a40e30c906 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -32,6 +32,7 @@ #define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_USOCKET (0) #define MICROPY_PY_NETWORK (0) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 910fb699c2..9ca7150f7f 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -31,6 +31,7 @@ #define MICROPY_PY_SYS_PLATFORM "nrf52-DK" #define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) From 4fee95c4682cf2f85aa8ca0a6ee22abc1f361332 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 26 Dec 2016 16:53:24 +0100 Subject: [PATCH 053/809] nrf5: Adding rtc.c which implements the machine rtc module to be included in build. --- nrf5/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 2a1ddbc4a0..42b402f258 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -145,6 +145,7 @@ SRC_C += \ modusocket.c \ modnetwork.c \ timer.c \ + rtc.c \ #ifeq ($(SD), ) From d6300a2e82099968672778a2cda2108afc7200c7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 27 Dec 2016 15:40:20 +0100 Subject: [PATCH 054/809] nrf5/pin: Merging input and output pin configuration to one comon function. Adding implementation in Pin class to be able to configure mode and pull. Updating drivers which uses gpio pin configuration to use new function parameters. --- nrf5/hal/hal_spi.c | 8 ++++---- nrf5/hal/hal_spie.c | 8 ++++---- nrf5/hal/hal_uart.c | 8 ++++---- nrf5/hal/hal_uarte.c | 8 ++++---- nrf5/led.c | 2 +- nrf5/mphalport.h | 20 ++++++++------------ nrf5/pin.c | 34 +++++++++++++++++----------------- nrf5/pin.h | 1 + 8 files changed, 43 insertions(+), 46 deletions(-) diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c index dc86a0cd52..39acea2437 100644 --- a/nrf5/hal/hal_spi.c +++ b/nrf5/hal/hal_spi.c @@ -48,10 +48,10 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi hal_gpio_pin_set(p_spi_init->enable_pin); m_ss_pin = p_spi_init->enable_pin; - hal_gpio_cfg_pin_output(p_spi_init->clk_pin); - hal_gpio_cfg_pin_output(p_spi_init->mosi_pin); - hal_gpio_cfg_pin_input(p_spi_init->miso_pin, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin_output(p_spi_init->enable_pin); + hal_gpio_cfg_pin(p_spi_init->clk_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->mosi_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->miso_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->enable_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); #if NRF51 p_instance->PSELSCK = p_spi_init->clk_pin; diff --git a/nrf5/hal/hal_spie.c b/nrf5/hal/hal_spie.c index 6af19afa91..dd1a8865ef 100644 --- a/nrf5/hal/hal_spie.c +++ b/nrf5/hal/hal_spie.c @@ -64,10 +64,10 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi hal_gpio_pin_set(p_spi_init->enable_pin); m_ss_pin = p_spi_init->enable_pin; - hal_gpio_cfg_pin_output(p_spi_init->clk_pin); - hal_gpio_cfg_pin_output(p_spi_init->mosi_pin); - hal_gpio_cfg_pin_input(p_spi_init->miso_pin, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin_output(p_spi_init->enable_pin); + hal_gpio_cfg_pin(p_spi_init->clk_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->mosi_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->miso_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->enable_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); #if NRF51 spim_instance->PSELSCK = p_spi_init->clk_pin; diff --git a/nrf5/hal/hal_uart.c b/nrf5/hal/hal_uart.c index 4c4a0d99f4..392acebe69 100644 --- a/nrf5/hal/hal_uart.c +++ b/nrf5/hal/hal_uart.c @@ -103,15 +103,15 @@ void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_comple } void nrf_uart_init(hal_uart_init_t const * p_uart_init) { - hal_gpio_cfg_pin_output(p_uart_init->tx_pin); - hal_gpio_cfg_pin_input(p_uart_init->rx_pin, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->tx_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->rx_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); UART_BASE->PSELTXD = p_uart_init->tx_pin; UART_BASE->PSELRXD = p_uart_init->rx_pin; if (p_uart_init->flow_control) { - hal_gpio_cfg_pin_output(p_uart_init->rts_pin); - hal_gpio_cfg_pin_input(p_uart_init->cts_pin, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->rts_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->cts_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); UART_BASE->PSELCTS = p_uart_init->cts_pin; UART_BASE->PSELRTS = p_uart_init->rts_pin; diff --git a/nrf5/hal/hal_uarte.c b/nrf5/hal/hal_uarte.c index 1990988758..ff3bd978a3 100644 --- a/nrf5/hal/hal_uarte.c +++ b/nrf5/hal/hal_uarte.c @@ -84,9 +84,9 @@ void nrf_sendchar(int ch) { } void nrf_uart_init(hal_uart_init_t const * p_uart_init) { - hal_gpio_cfg_pin_output(p_uart_init->tx_pin); + hal_gpio_cfg_pin(p_uart_init->tx_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_pin_set(p_uart_init->tx_pin); - hal_gpio_cfg_pin_input(p_uart_init->rx_pin, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->rx_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); UARTE_BASE->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]); @@ -104,8 +104,8 @@ void nrf_uart_init(hal_uart_init_t const * p_uart_init) { UARTE_BASE->PSEL.TXD = p_uart_init->tx_pin; if (hwfc) { - hal_gpio_cfg_pin_input(p_uart_init->cts_pin, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin_output(p_uart_init->rts_pin); + hal_gpio_cfg_pin(p_uart_init->cts_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->rts_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_pin_set(p_uart_init->rts_pin); UARTE_BASE->PSEL.RTS = p_uart_init->rts_pin; diff --git a/nrf5/led.c b/nrf5/led.c index a47a9de656..8cd0d69861 100644 --- a/nrf5/led.c +++ b/nrf5/led.c @@ -63,7 +63,7 @@ STATIC const pyb_led_obj_t pyb_led_obj[] = { void led_init(void) { for (uint8_t i = 0; i < NUM_LEDS; i++) { LED_OFF(pyb_led_obj[i].hw_pin); - hal_gpio_cfg_pin_output(pyb_led_obj[i].hw_pin); + hal_gpio_cfg_pin(pyb_led_obj[i].hw_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); } } diff --git a/nrf5/mphalport.h b/nrf5/mphalport.h index 5d80d5142b..23e39a0997 100644 --- a/nrf5/mphalport.h +++ b/nrf5/mphalport.h @@ -73,23 +73,19 @@ typedef enum { HAL_GPIO_PULL_UP = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) } hal_gpio_pull_t; -static inline void hal_gpio_cfg_pin_output(uint32_t pin_number) { +typedef enum { + HAL_GPIO_MODE_OUTPUT = (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos), + HAL_GPIO_MODE_INPUT = (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos), +} hal_gpio_mode_t; + +static inline void hal_gpio_cfg_pin(uint32_t pin_number, hal_gpio_mode_t mode, hal_gpio_pull_t pull) { GPIO_BASE->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | pull | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + | mode; } -static inline void hal_gpio_cfg_pin_input(uint32_t pin_number, hal_gpio_pull_t pull) { - GPIO_BASE->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | pull - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); -} - - static inline void hal_gpio_out_set(uint32_t pin_mask) { GPIO_BASE->OUTSET = pin_mask; } diff --git a/nrf5/pin.c b/nrf5/pin.c index 5172ec27d1..1debbaa0d3 100644 --- a/nrf5/pin.c +++ b/nrf5/pin.c @@ -215,7 +215,6 @@ STATIC void pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t } } mp_print_str(print, qstr_str(mode_qst)); - // pull mode qstr pull_qst = MP_QSTR_NULL; uint32_t pull = pin_get_pull(self); @@ -227,7 +226,6 @@ STATIC void pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t if (pull_qst != MP_QSTR_NULL) { mp_printf(print, ", pull=Pin.%q", pull_qst); } - // AF mode if (af) { mp_uint_t af_idx = pin_get_af(self); @@ -343,27 +341,25 @@ STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, con // parse args mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); -/* - // get io mode - uint mode = args[0].u_int; - if (!IS_GPIO_MODE(mode)) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "invalid pin mode: %d", mode)); - } -*/ + // get pull mode uint pull = HAL_GPIO_PULL_DISABLED; if (args[1].u_obj != mp_const_none) { pull = mp_obj_get_int(args[1].u_obj); } - (void)pull; - // if given, set the pin value before initialising to prevent glitches if (args[3].u_obj != MP_OBJ_NULL) { mp_hal_pin_write(self, mp_obj_is_true(args[3].u_obj)); } - hal_gpio_cfg_pin_output(self->pin_mask); + // get io mode + uint mode = args[0].u_int; + if (mode == HAL_GPIO_MODE_OUTPUT || mode == HAL_GPIO_MODE_INPUT) { + hal_gpio_cfg_pin(self->pin, mode, pull); + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "invalid pin mode: %d", mode)); + } return mp_const_none; } @@ -501,21 +497,25 @@ STATIC const mp_map_elem_t pin_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_mapper), (mp_obj_t)&pin_mapper_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_dict), (mp_obj_t)&pin_map_dict_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_debug), (mp_obj_t)&pin_debug_obj }, -/* + // class attributes { MP_OBJ_NEW_QSTR(MP_QSTR_board), (mp_obj_t)&pin_board_pins_obj_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_cpu), (mp_obj_t)&pin_cpu_pins_obj_type }, // class constants - { MP_OBJ_NEW_QSTR(MP_QSTR_IN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_INPUT) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_OUT), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_IN), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_MODE_INPUT) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_OUT), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_MODE_OUTPUT) }, +/* { MP_OBJ_NEW_QSTR(MP_QSTR_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ALT), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_PP) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ALT_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_OD) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ANALOG), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_ANALOG) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_UP), MP_OBJ_NEW_SMALL_INT(GPIO_PULLUP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DOWN), MP_OBJ_NEW_SMALL_INT(GPIO_PULLDOWN) }, +*/ + { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DISABLED), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_DISABLED) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_UP), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_UP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DOWN), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_DOWN) }, +/* // legacy class constants { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_PP), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) }, { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_OD), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) }, diff --git a/nrf5/pin.h b/nrf5/pin.h index d2b6e863c9..2556faf743 100644 --- a/nrf5/pin.h +++ b/nrf5/pin.h @@ -59,6 +59,7 @@ typedef struct { uint32_t pin_mask; pin_gpio_t *gpio; const pin_af_obj_t *af; + uint32_t pull; } pin_obj_t; extern const mp_obj_type_t pin_type; From 9197739cf44ef557ad1a0c8b5be3afbe9357b096 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 27 Dec 2016 15:42:35 +0100 Subject: [PATCH 055/809] nrf5/modules: Updating mountsd, SD card test script with new params. --- nrf5/modules/mountsd.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/mountsd.py b/nrf5/modules/mountsd.py index 2b4ac26362..e449a692dc 100644 --- a/nrf5/modules/mountsd.py +++ b/nrf5/modules/mountsd.py @@ -1,9 +1,8 @@ import os -from machine import SPI -from pyb import Pin +from machine import SPI, Pin from sdcard import SDCard def mount_sd(): - sd = SDCard(SPI(0), Pin("A22")) + sd = SDCard(SPI(0), Pin("A22", mode=Pin.OUT)) os.mount(sd, '/') From db994e2ec0cd97558fb993bd6563660fff81bedf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 27 Dec 2016 15:44:39 +0100 Subject: [PATCH 056/809] nrf5/modules: Updating documentation on sdcard.py copy to use new params in the example description --- nrf5/modules/sdcard.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/sdcard.py b/nrf5/modules/sdcard.py index 4fdb3bd045..953c486a46 100644 --- a/nrf5/modules/sdcard.py +++ b/nrf5/modules/sdcard.py @@ -21,8 +21,8 @@ Example usage on ESP8266: Example usage on NRF52832: - import machine, pyb, os - sd = sdcard.SDCard(machine.SPI(0), machine.PIN("A22")) + import os, machine, sdcard + sd = sdcard.SDCard(machine.SPI(0), machine.PIN("A22", mode=machine.Pin.OUT)) os.mount(sd, "") os.listdir() From cceea0a5049d630cf2881640938a8f363c5bd2d9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 27 Dec 2016 15:47:55 +0100 Subject: [PATCH 057/809] nrf5/modules: Adding new python script to initialize and clear the display on Seeedstudio 2.8 TFT Touch Shield v2. --- nrf5/modules/seeedstudio_tft_shield_v2.py | 150 ++++++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 nrf5/modules/seeedstudio_tft_shield_v2.py diff --git a/nrf5/modules/seeedstudio_tft_shield_v2.py b/nrf5/modules/seeedstudio_tft_shield_v2.py new file mode 100644 index 0000000000..7d8038c0cd --- /dev/null +++ b/nrf5/modules/seeedstudio_tft_shield_v2.py @@ -0,0 +1,150 @@ +# MicroPython Seeedstudio TFT Shield V2 driver, SPI interfaces, Analog GPIO +# Contains SD-card reader, LCD and Touch sensor + +import time +from machine import SPI, Pin + +class ILI9341: + def __init__(self, width, height): + self.width = width + self.height = height + self.spi = SPI(0) + # chip select + self.cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) + # command + self.dc = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) + + # initialize all pins high + self.cs.high() + self.dc.high() + + self.spi.init(baudrate=1000000, phase=0, polarity=0) + + self.init_display() + + + def init_display(self): + time.sleep_ms(500) + + self.write_cmd(0x01) + + time.sleep_ms(200) + + self.write_cmd(0xCF) + self.write_data(bytearray([0x00, 0x8B, 0x30])) + + self.write_cmd(0xED) + self.write_data(bytearray([0x67, 0x03, 0x12, 0x81])) + + self.write_cmd(0xE8) + self.write_data(bytearray([0x85, 0x10, 0x7A])) + + self.write_cmd(0xCB) + self.write_data(bytearray([0x39, 0x2C, 0x00, 0x34, 0x02])) + + self.write_cmd(0xF7) + self.write_data(bytearray([0x20])) + + self.write_cmd(0xEA) + self.write_data(bytearray([0x00, 0x00])) + + # Power control + self.write_cmd(0xC0) + # VRH[5:0] + self.write_data(bytearray([0x1B])) + + # Power control + self.write_cmd(0xC1) + # SAP[2:0];BT[3:0] + self.write_data(bytearray([0x10])) + + # VCM control + self.write_cmd(0xC5) + self.write_data(bytearray([0x3F, 0x3C])) + + # VCM control2 + self.write_cmd(0xC7) + self.write_data(bytearray([0xB7])) + + # Memory Access Control + self.write_cmd(0x36) + self.write_data(bytearray([0x08])) + + self.write_cmd(0x3A) + self.write_data(bytearray([0x55])) + + self.write_cmd(0xB1) + self.write_data(bytearray([0x00, 0x1B])) + + # Display Function Control + self.write_cmd(0xB6) + self.write_data(bytearray([0x0A, 0xA2])) + + # 3Gamma Function Disable + self.write_cmd(0xF2) + self.write_data(bytearray([0x00])) + + # Gamma curve selected + self.write_cmd(0x26) + self.write_data(bytearray([0x01])) + + # Set Gamma + self.write_cmd(0xE0) + self.write_data(bytearray([0x0F, 0x2A, 0x28, 0x08, 0x0E, 0x08, 0x54, 0XA9, 0x43, 0x0A, 0x0F, 0x00, 0x00, 0x00, 0x00])) + + # Set Gamma + self.write_cmd(0XE1) + self.write_data(bytearray([0x00, 0x15, 0x17, 0x07, 0x11, 0x06, 0x2B, 0x56, 0x3C, 0x05, 0x10, 0x0F, 0x3F, 0x3F, 0x0F])) + + # Exit Sleep + self.write_cmd(0x11) + time.sleep_ms(120) + + # Display on + self.write_cmd(0x29) + time.sleep_ms(500) + self.fill(0) + + def fill(self, col): + + # set col + self.write_cmd(0x2A) + self.write_data(bytearray([0x00, 0x00])); + self.write_data(bytearray([0x00, 0xef])); + + # set page + self.write_cmd(0x2B) + self.write_data(bytearray([0x00, 0x00])); + self.write_data(bytearray([0x01, 0x3f])); + + self.write_cmd(0x2c); + + self.dc.high() + self.cs.low() + for i in range(0, self.width): + for j in range(0, self.height): + a = bytearray([col, col]) + self.spi.write(a) + self.cs.high() + + def pixel(self, x, y, col): + pass + + def scroll(self, dx, dy): + pass + + def text(self, string, x, y, col=1): + pass + + def write_cmd(self, cmd): + self.dc.low() + self.cs.low() + self.spi.write(bytearray([cmd])) + self.cs.high() + + def write_data(self, buf): + self.dc.high() + self.cs.low() + self.spi.write(buf) + self.cs.high() + From d2969048ff4a57d5ce519d868b9262d6f569c116 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 27 Dec 2016 16:05:49 +0100 Subject: [PATCH 058/809] nrf5/modules: Adding a function to get access to the SD card flash drive on the seeedstudio tft shield. --- nrf5/modules/seeedstudio_tft_shield_v2.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/nrf5/modules/seeedstudio_tft_shield_v2.py b/nrf5/modules/seeedstudio_tft_shield_v2.py index 7d8038c0cd..e0daf1ca03 100644 --- a/nrf5/modules/seeedstudio_tft_shield_v2.py +++ b/nrf5/modules/seeedstudio_tft_shield_v2.py @@ -3,6 +3,12 @@ import time from machine import SPI, Pin +import os +from sdcard import SDCard + +def mount_tf(self, mount_point="/"): + sd = SDCard(SPI(0), Pin("A15", mode=Pin.OUT)) + os.mount(sd, mount_point) class ILI9341: def __init__(self, width, height): From 5f4cf7b908905126c4a38e261ee0e230fa448e25 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 08:49:20 +0100 Subject: [PATCH 059/809] nrf5/boards: Bouncing up heap to 32k on pca10040 to allow for application to allocate 9600bytes+ framebuffer when using LCD screen (240x320). --- nrf5/boards/nrf52832_aa.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/nrf52832_aa.ld b/nrf5/boards/nrf52832_aa.ld index 6da7790f7b..afd7d359f8 100644 --- a/nrf5/boards/nrf52832_aa.ld +++ b/nrf5/boards/nrf52832_aa.ld @@ -13,7 +13,7 @@ MEMORY /* produce a link error if there is not this amount of RAM for these sections */ _minimum_stack_size = 2K; -_minimum_heap_size = 16K; +_minimum_heap_size = 32K; /* top end of the stack */ @@ -22,6 +22,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20005000; /* tunable */ +_heap_end = 0x20008000; /* tunable */ INCLUDE "boards/common.ld" From cfbe91a70947b3c120294f860b2b87cc69bb9e8c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 08:52:32 +0100 Subject: [PATCH 060/809] nrf5/modules: Updating seeedstudio tft lcd driver to render using already existing framebuffer implementation. --- nrf5/modules/seeedstudio_tft_shield_v2.py | 76 ++++++++++++++++------- 1 file changed, 52 insertions(+), 24 deletions(-) diff --git a/nrf5/modules/seeedstudio_tft_shield_v2.py b/nrf5/modules/seeedstudio_tft_shield_v2.py index e0daf1ca03..81d17cbce8 100644 --- a/nrf5/modules/seeedstudio_tft_shield_v2.py +++ b/nrf5/modules/seeedstudio_tft_shield_v2.py @@ -1,9 +1,28 @@ -# MicroPython Seeedstudio TFT Shield V2 driver, SPI interfaces, Analog GPIO -# Contains SD-card reader, LCD and Touch sensor +""" +MicroPython Seeedstudio TFT Shield V2 driver, SPI interfaces, Analog GPIO +Contains SD-card reader, LCD and Touch sensor -import time -from machine import SPI, Pin +Example usage of LCD: + + from seeedstudio_tft_shield_v2 import ILI9341 + + lcd = ILI9341(240, 320) + lcd.text("Hello World!, 32, 32) + lcd.show() + +Example usage of SD card reader: + + import os + from seeedstudio_tft_shield_v2 import mount_tf + + tf = mount_tf() + os.listdir() +""" import os +import time +import framebuf + +from machine import SPI, Pin from sdcard import SDCard def mount_tf(self, mount_point="/"): @@ -14,6 +33,10 @@ class ILI9341: def __init__(self, width, height): self.width = width self.height = height + self.pages = self.height // 8 + self.buffer = bytearray(self.pages * self.width) + self.framebuf = framebuf.FrameBuffer1(self.buffer, self.width, self.height) + self.spi = SPI(0) # chip select self.cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) @@ -24,7 +47,7 @@ class ILI9341: self.cs.high() self.dc.high() - self.spi.init(baudrate=1000000, phase=0, polarity=0) + self.spi.init(baudrate=8000000, phase=0, polarity=0) self.init_display() @@ -110,37 +133,42 @@ class ILI9341: self.write_cmd(0x29) time.sleep_ms(500) self.fill(0) - - def fill(self, col): - + + def show(self): # set col self.write_cmd(0x2A) - self.write_data(bytearray([0x00, 0x00])); - self.write_data(bytearray([0x00, 0xef])); + self.write_data(bytearray([0x00, 0x00])) + self.write_data(bytearray([0x00, 0xef])) # set page self.write_cmd(0x2B) - self.write_data(bytearray([0x00, 0x00])); - self.write_data(bytearray([0x01, 0x3f])); - + self.write_data(bytearray([0x00, 0x00])) + self.write_data(bytearray([0x01, 0x3f])) + self.write_cmd(0x2c); - - self.dc.high() - self.cs.low() - for i in range(0, self.width): - for j in range(0, self.height): - a = bytearray([col, col]) - self.spi.write(a) - self.cs.high() + + num_of_pixels = self.height * self.width + + for row in range(0, self.pages): + for pixel_pos in range(0, 8): + for col in range(0, self.width): + compressed_pixel = self.buffer[row * 240 + col] + if ((compressed_pixel >> pixel_pos) & 0x1) == 0: + self.write_data(bytearray([0x00, 0x00])) + else: + self.write_data(bytearray([0xFF, 0xFF])) + + def fill(self, col): + self.framebuf.fill(col) def pixel(self, x, y, col): - pass + self.framebuf.pixel(x, y, col) def scroll(self, dx, dy): - pass + self.framebuf.scroll(dx, dy) def text(self, string, x, y, col=1): - pass + self.framebuf.text(string, x, y, col) def write_cmd(self, cmd): self.dc.low() From 02203389c2fd19d35d7069d04b368df91b9a3414 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 08:53:38 +0100 Subject: [PATCH 061/809] nrf5/modules: Updating pulse test to set output direction on the LED pin used in the test. --- nrf5/modules/test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/test.py b/nrf5/modules/test.py index cabc279ae7..df0f520f4e 100644 --- a/nrf5/modules/test.py +++ b/nrf5/modules/test.py @@ -3,8 +3,8 @@ from machine import PWM, Pin def pulse(): for i in range(0, 101): - p = PWM(0, Pin("A17"), freq=PWM.FREQ_16MHZ, duty=i, period=16000) + p = PWM(0, Pin("A17", mode=Pin.OUT), freq=PWM.FREQ_16MHZ, duty=i, period=16000) time.sleep_ms(10) for i in range(0, 101): - p = PWM(0, Pin("A17"), freq=PWM.FREQ_16MHZ, duty=100-i, period=16000) + p = PWM(0, Pin("A17", mode=Pin.OUT), freq=PWM.FREQ_16MHZ, duty=100-i, period=16000) time.sleep_ms(10) From 88e45f85c3b8b0bfffe25fc3b92b541a353c85ea Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 13:03:47 +0100 Subject: [PATCH 062/809] nrf5/lcd: Adding work in progress monochrome lcd framebuffer driver which only updates modified (dirty) display lines. --- nrf5/lcd_mono_fb.c | 335 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 335 insertions(+) create mode 100644 nrf5/lcd_mono_fb.c diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c new file mode 100644 index 0000000000..db71ed059b --- /dev/null +++ b/nrf5/lcd_mono_fb.c @@ -0,0 +1,335 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/nlr.h" +#include "py/obj.h" +#include "py/runtime.h" + +#include "lcd_mono_fb.h" +#include "font.h" + +#define LCD_BLACK 0 +#define LCD_WHITE 1 + +typedef struct { + mp_obj_base_t base; + fb_byte_t * fb_bytes; + fb_byte_t * fb_dirty; + uint16_t height; + uint16_t width; + mp_obj_t line_update_cb; +} mp_obj_framebuf_t; + +static uint8_t m_bg_color; +static uint8_t m_fg_color; +static uint8_t m_font_size; + +STATIC void lcd_enable_pixel(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y) +{ + uint16_t column = (x / 8); + uint16_t line = y; + uint8_t bit_pos = x % 8; + + m_framebuffer->fb_bytes[line* (m_framebuffer->width / 8) + column].byte |= (1 << bit_pos); + m_framebuffer->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); +} + +STATIC void lcd_disable_pixel(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y) +{ + uint16_t column = (x / 8); + uint16_t line = y; + uint8_t bit_pos = x % 8; + + m_framebuffer->fb_bytes[line * (m_framebuffer->width / 8) + column].byte &= ~(1 << bit_pos); + m_framebuffer->fb_dirty[y/8].byte |= (uint8_t)(0x1 << y % 8); +} + +STATIC void lcd_init(mp_obj_framebuf_t * m_framebuffer) +{ + m_fg_color = LCD_BLACK; + m_bg_color = LCD_WHITE; + + memset(m_framebuffer->fb_bytes, 0x00, m_framebuffer->width * m_framebuffer->height / 8); + memset(m_framebuffer->fb_dirty, 0x00, m_framebuffer->height / 8); +} + +STATIC void lcd_fg_color_set(mp_obj_framebuf_t * m_framebuffer, uint16_t color) +{ + m_fg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; +} + +#if 0 +STATIC uint16_t lcd_fg_color_get(mp_obj_framebuf_t * m_framebuffer) +{ + return m_fg_color; +} +#endif + +STATIC void lcd_bg_color_set(mp_obj_framebuf_t * m_framebuffer, uint16_t color) +{ + m_bg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; +} + +#if 0 +STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * m_framebuffer) +{ + return m_bg_color; +} +#endif + +STATIC void lcd_clear_screen(mp_obj_framebuf_t * m_framebuffer) +{ + if (m_bg_color == LCD_BLACK) { + memset(m_framebuffer->fb_bytes, 0x00, m_framebuffer->width * m_framebuffer->height / 8); + } else { + memset(m_framebuffer->fb_bytes, 0xFF, m_framebuffer->width * m_framebuffer->height / 8); + } + memset(m_framebuffer->fb_dirty, 0xFF, m_framebuffer->height / 8); +} + +STATIC void lcd_print_char(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y, char ch) +{ + + //int column = (x / 8); + uint16_t line = y; + for (uint8_t i = 0; i < 8; i++) + { + uint16_t current_line = line + (i * m_font_size); + for (uint8_t x_pos = 0; x_pos < 8; x_pos++) + { + if (((uint8_t)font_8x8[ch - 32][i] >> x_pos) & 0x01) + { + for (uint8_t s_w = 0; s_w < m_font_size; s_w++) + { + for (uint8_t s_h = 0; s_h < m_font_size; s_h++) + { + if (m_fg_color < LCD_WHITE) + { + lcd_disable_pixel(m_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + } + else + { + lcd_enable_pixel(m_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + } + } + } + } + else + { + for (uint8_t s_w = 0; s_w < m_font_size; s_w++) + { + for (uint8_t s_h = 0; s_h < m_font_size; s_h++) + { + if (m_bg_color < LCD_WHITE) + { + lcd_disable_pixel(m_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + } + else + { + lcd_enable_pixel(m_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + } + } + } + } + } + } +} + +#if 0 +STATIC void lcd_font_size_set(mp_obj_framebuf_t * m_framebuffer, uint8_t size) +{ + m_font_size = size; +} + +STATIC uint8_t lcd_font_size_get(mp_obj_framebuf_t * m_framebuffer) +{ + return m_font_size; +} +#endif + +STATIC void lcd_print_string(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y, const char * p_str) +{ + uint16_t str_len = strlen(p_str); + for (uint16_t i = 0; i < str_len; i++) + { + lcd_print_char(m_framebuffer, x + (i * 8 * m_font_size), y, p_str[i]); + } +} + +STATIC void lcd_pixel_draw(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y) +{ + +} + +#include "py/objarray.h" + +STATIC void lcd_update(mp_obj_framebuf_t * m_framebuffer) +{ + for (uint16_t i = 0; i < m_framebuffer->height / 8; i++) + { + if (m_framebuffer->fb_dirty[i].byte != 0) + { + for (uint16_t b = 0; b < 8; b++) + { + if (((m_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) + { + uint16_t line_num = (i * 8) + b; + mp_obj_t args[3]; + args[0] = m_framebuffer; + args[1] = MP_OBJ_NEW_SMALL_INT(line_num); + args[2] = mp_obj_new_bytearray_by_ref(m_framebuffer->width / 8, (uint8_t *)&m_framebuffer->fb_bytes[line_num * m_framebuffer->width / 8]); + + mp_obj_array_t *o = MP_OBJ_TO_PTR(args[2]); + (void)o; + mp_call_function_n_kw(m_framebuffer->line_update_cb, 3, 0, args); + } + } + m_framebuffer->fb_dirty[i].byte = 0x00; + } + } +} + +STATIC mp_obj_t lcd_mono_fb_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 3, 4, false); + + mp_obj_framebuf_t *o = m_new_obj(mp_obj_framebuf_t); + o->base.type = type; + + + o->line_update_cb = args[0]; + + o->width = mp_obj_get_int(args[1]); + o->height = mp_obj_get_int(args[2]); + + o->fb_bytes = m_new(fb_byte_t, (o->width / 8) * o->height); + o->fb_dirty = m_new(fb_byte_t, o->height / 8); + + m_font_size = 1; + + lcd_init(o); + + return MP_OBJ_FROM_PTR(o); +} + +STATIC mp_obj_t lcd_mono_fb_fill(mp_obj_t self_in, mp_obj_t col_in) { + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + mp_int_t col = mp_obj_get_int(col_in); + + + lcd_bg_color_set(self, col); + lcd_fg_color_set(self, !col); + + lcd_clear_screen(self); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_mono_fb_fill_obj, lcd_mono_fb_fill); + +STATIC mp_obj_t lcd_mono_fb_pixel(size_t n_args, const mp_obj_t *args) { + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t x = mp_obj_get_int(args[1]); + mp_int_t y = mp_obj_get_int(args[2]); + + lcd_pixel_draw(self, x, y); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_mono_fb_pixel_obj, 3, 4, lcd_mono_fb_pixel); + +STATIC mp_obj_t lcd_mono_fb_scroll(mp_obj_t self_in, mp_obj_t xstep_in, mp_obj_t ystep_in) { +#if 0 + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + mp_int_t xstep = mp_obj_get_int(xstep_in); + mp_int_t ystep = mp_obj_get_int(ystep_in); +#endif + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_3(lcd_mono_fb_scroll_obj, lcd_mono_fb_scroll); + +STATIC mp_obj_t lcd_mono_fb_text(size_t n_args, const mp_obj_t *args) { + // extract arguments + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(args[0]); + const char *str = mp_obj_str_get_str(args[1]); + mp_int_t x0 = mp_obj_get_int(args[2]); + mp_int_t y0 = mp_obj_get_int(args[3]); + + lcd_print_string(self, x0, y0, str); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_mono_fb_text_obj, 4, 5, lcd_mono_fb_text); + + +STATIC mp_obj_t lcd_mono_fb_show(mp_obj_t self_in) { + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + + lcd_update(self); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_show_obj, lcd_mono_fb_show); + +STATIC mp_obj_t lcd_mono_fb_del(mp_obj_t self_in) { + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + + m_free(self->fb_bytes); + m_free(self->fb_dirty); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_del_obj, lcd_mono_fb_del); + +STATIC const mp_rom_map_elem_t lcd_mono_fb_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR___del__), MP_ROM_PTR(&lcd_mono_fb_del_obj) }, + { MP_ROM_QSTR(MP_QSTR_fill), MP_ROM_PTR(&lcd_mono_fb_fill_obj) }, + { MP_ROM_QSTR(MP_QSTR_pixel), MP_ROM_PTR(&lcd_mono_fb_pixel_obj) }, + { MP_ROM_QSTR(MP_QSTR_scroll), MP_ROM_PTR(&lcd_mono_fb_scroll_obj) }, + { MP_ROM_QSTR(MP_QSTR_text), MP_ROM_PTR(&lcd_mono_fb_text_obj) }, + { MP_ROM_QSTR(MP_QSTR_show), MP_ROM_PTR(&lcd_mono_fb_show_obj) }, +}; +STATIC MP_DEFINE_CONST_DICT(lcd_mono_fb_locals_dict, lcd_mono_fb_locals_dict_table); + +STATIC const mp_obj_type_t mp_type_lcd_mono_fb = { + { &mp_type_type }, + .name = MP_QSTR_MonoFB, + .make_new = lcd_mono_fb_make_new, + .locals_dict = (mp_obj_t)&lcd_mono_fb_locals_dict, +}; + +STATIC const mp_rom_map_elem_t lcd_mono_fb_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_lcd_mono_fb) }, + { MP_ROM_QSTR(MP_QSTR_MonoFB), MP_ROM_PTR(&mp_type_lcd_mono_fb) }, +}; + +STATIC MP_DEFINE_CONST_DICT(lcd_mono_fb_module_globals, lcd_mono_fb_module_globals_table); + +const mp_obj_module_t mp_module_lcd_mono_fb = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&lcd_mono_fb_module_globals, +}; From d14a72795cf44a57ef73a7fbd778f8892201ce5a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 14:25:30 +0100 Subject: [PATCH 063/809] nrf5/lcd: Cleaning up a bit in lcd framebuffer. --- nrf5/lcd_mono_fb.c | 51 ++++++++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 22 deletions(-) diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index db71ed059b..1056e2a08b 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -43,6 +43,8 @@ typedef struct { fb_byte_t * fb_dirty; uint16_t height; uint16_t width; + mp_uint_t bytes_stride; + mp_uint_t dirty_stride; mp_obj_t line_update_cb; } mp_obj_framebuf_t; @@ -56,7 +58,7 @@ STATIC void lcd_enable_pixel(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint uint16_t line = y; uint8_t bit_pos = x % 8; - m_framebuffer->fb_bytes[line* (m_framebuffer->width / 8) + column].byte |= (1 << bit_pos); + m_framebuffer->fb_bytes[line * (m_framebuffer->bytes_stride) + column].byte |= (1 << bit_pos); m_framebuffer->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); } @@ -66,7 +68,7 @@ STATIC void lcd_disable_pixel(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uin uint16_t line = y; uint8_t bit_pos = x % 8; - m_framebuffer->fb_bytes[line * (m_framebuffer->width / 8) + column].byte &= ~(1 << bit_pos); + m_framebuffer->fb_bytes[line * (m_framebuffer->bytes_stride) + column].byte &= ~(1 << bit_pos); m_framebuffer->fb_dirty[y/8].byte |= (uint8_t)(0x1 << y % 8); } @@ -75,8 +77,8 @@ STATIC void lcd_init(mp_obj_framebuf_t * m_framebuffer) m_fg_color = LCD_BLACK; m_bg_color = LCD_WHITE; - memset(m_framebuffer->fb_bytes, 0x00, m_framebuffer->width * m_framebuffer->height / 8); - memset(m_framebuffer->fb_dirty, 0x00, m_framebuffer->height / 8); + memset(m_framebuffer->fb_bytes, 0x00, m_framebuffer->bytes_stride * m_framebuffer->height); + memset(m_framebuffer->fb_dirty, 0x00, m_framebuffer->dirty_stride); } STATIC void lcd_fg_color_set(mp_obj_framebuf_t * m_framebuffer, uint16_t color) @@ -106,11 +108,11 @@ STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * m_framebuffer) STATIC void lcd_clear_screen(mp_obj_framebuf_t * m_framebuffer) { if (m_bg_color == LCD_BLACK) { - memset(m_framebuffer->fb_bytes, 0x00, m_framebuffer->width * m_framebuffer->height / 8); + memset(m_framebuffer->fb_bytes, 0x00, m_framebuffer->bytes_stride * m_framebuffer->height); } else { - memset(m_framebuffer->fb_bytes, 0xFF, m_framebuffer->width * m_framebuffer->height / 8); + memset(m_framebuffer->fb_bytes, 0xFF, m_framebuffer->bytes_stride * m_framebuffer->height); } - memset(m_framebuffer->fb_dirty, 0xFF, m_framebuffer->height / 8); + memset(m_framebuffer->fb_dirty, 0xFF, m_framebuffer->dirty_stride); } STATIC void lcd_print_char(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y, char ch) @@ -182,16 +184,20 @@ STATIC void lcd_print_string(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint } } -STATIC void lcd_pixel_draw(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y) +STATIC void lcd_pixel_draw(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y, uint16_t color) { - + if (color < LCD_WHITE) + { + lcd_disable_pixel(m_framebuffer, x, y); + } + else + { + lcd_enable_pixel(m_framebuffer, x, y); + } } -#include "py/objarray.h" - -STATIC void lcd_update(mp_obj_framebuf_t * m_framebuffer) -{ - for (uint16_t i = 0; i < m_framebuffer->height / 8; i++) +STATIC void lcd_update(mp_obj_framebuf_t * m_framebuffer) { + for (uint16_t i = 0; i < m_framebuffer->dirty_stride; i++) { if (m_framebuffer->fb_dirty[i].byte != 0) { @@ -203,10 +209,8 @@ STATIC void lcd_update(mp_obj_framebuf_t * m_framebuffer) mp_obj_t args[3]; args[0] = m_framebuffer; args[1] = MP_OBJ_NEW_SMALL_INT(line_num); - args[2] = mp_obj_new_bytearray_by_ref(m_framebuffer->width / 8, (uint8_t *)&m_framebuffer->fb_bytes[line_num * m_framebuffer->width / 8]); - - mp_obj_array_t *o = MP_OBJ_TO_PTR(args[2]); - (void)o; + args[2] = mp_obj_new_bytearray_by_ref(m_framebuffer->bytes_stride, + &m_framebuffer->fb_bytes[line_num * m_framebuffer->bytes_stride]); mp_call_function_n_kw(m_framebuffer->line_update_cb, 3, 0, args); } } @@ -221,14 +225,16 @@ STATIC mp_obj_t lcd_mono_fb_make_new(const mp_obj_type_t *type, size_t n_args, s mp_obj_framebuf_t *o = m_new_obj(mp_obj_framebuf_t); o->base.type = type; - o->line_update_cb = args[0]; o->width = mp_obj_get_int(args[1]); o->height = mp_obj_get_int(args[2]); - o->fb_bytes = m_new(fb_byte_t, (o->width / 8) * o->height); - o->fb_dirty = m_new(fb_byte_t, o->height / 8); + o->bytes_stride = o->width / 8; + o->dirty_stride = o->height / 8; + + o->fb_bytes = m_new(fb_byte_t, (o->bytes_stride) * o->height); + o->fb_dirty = m_new(fb_byte_t, o->dirty_stride); m_font_size = 1; @@ -255,8 +261,9 @@ STATIC mp_obj_t lcd_mono_fb_pixel(size_t n_args, const mp_obj_t *args) { mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(args[0]); mp_int_t x = mp_obj_get_int(args[1]); mp_int_t y = mp_obj_get_int(args[2]); + mp_int_t color = mp_obj_get_int(args[3]); - lcd_pixel_draw(self, x, y); + lcd_pixel_draw(self, x, y, color); return mp_const_none; } From 85c9db4bcd732244083bc0b12d90abb38d72be75 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 14:26:26 +0100 Subject: [PATCH 064/809] nrf5/lcd: Renaming variable name from m_ to p_ --- nrf5/lcd_mono_fb.c | 76 +++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index 1056e2a08b..7e3f4d73e8 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -52,70 +52,70 @@ static uint8_t m_bg_color; static uint8_t m_fg_color; static uint8_t m_font_size; -STATIC void lcd_enable_pixel(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y) +STATIC void lcd_enable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { uint16_t column = (x / 8); uint16_t line = y; uint8_t bit_pos = x % 8; - m_framebuffer->fb_bytes[line * (m_framebuffer->bytes_stride) + column].byte |= (1 << bit_pos); - m_framebuffer->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); + p_framebuffer->fb_bytes[line * (p_framebuffer->bytes_stride) + column].byte |= (1 << bit_pos); + p_framebuffer->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); } -STATIC void lcd_disable_pixel(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y) +STATIC void lcd_disable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { uint16_t column = (x / 8); uint16_t line = y; uint8_t bit_pos = x % 8; - m_framebuffer->fb_bytes[line * (m_framebuffer->bytes_stride) + column].byte &= ~(1 << bit_pos); - m_framebuffer->fb_dirty[y/8].byte |= (uint8_t)(0x1 << y % 8); + p_framebuffer->fb_bytes[line * (p_framebuffer->bytes_stride) + column].byte &= ~(1 << bit_pos); + p_framebuffer->fb_dirty[y/8].byte |= (uint8_t)(0x1 << y % 8); } -STATIC void lcd_init(mp_obj_framebuf_t * m_framebuffer) +STATIC void lcd_init(mp_obj_framebuf_t * p_framebuffer) { m_fg_color = LCD_BLACK; m_bg_color = LCD_WHITE; - memset(m_framebuffer->fb_bytes, 0x00, m_framebuffer->bytes_stride * m_framebuffer->height); - memset(m_framebuffer->fb_dirty, 0x00, m_framebuffer->dirty_stride); + memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); + memset(p_framebuffer->fb_dirty, 0x00, p_framebuffer->dirty_stride); } -STATIC void lcd_fg_color_set(mp_obj_framebuf_t * m_framebuffer, uint16_t color) +STATIC void lcd_fg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { m_fg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; } #if 0 -STATIC uint16_t lcd_fg_color_get(mp_obj_framebuf_t * m_framebuffer) +STATIC uint16_t lcd_fg_color_get(mp_obj_framebuf_t * p_framebuffer) { return m_fg_color; } #endif -STATIC void lcd_bg_color_set(mp_obj_framebuf_t * m_framebuffer, uint16_t color) +STATIC void lcd_bg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { m_bg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; } #if 0 -STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * m_framebuffer) +STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * p_framebuffer) { return m_bg_color; } #endif -STATIC void lcd_clear_screen(mp_obj_framebuf_t * m_framebuffer) +STATIC void lcd_clear_screen(mp_obj_framebuf_t * p_framebuffer) { if (m_bg_color == LCD_BLACK) { - memset(m_framebuffer->fb_bytes, 0x00, m_framebuffer->bytes_stride * m_framebuffer->height); + memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); } else { - memset(m_framebuffer->fb_bytes, 0xFF, m_framebuffer->bytes_stride * m_framebuffer->height); + memset(p_framebuffer->fb_bytes, 0xFF, p_framebuffer->bytes_stride * p_framebuffer->height); } - memset(m_framebuffer->fb_dirty, 0xFF, m_framebuffer->dirty_stride); + memset(p_framebuffer->fb_dirty, 0xFF, p_framebuffer->dirty_stride); } -STATIC void lcd_print_char(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y, char ch) +STATIC void lcd_print_char(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, char ch) { //int column = (x / 8); @@ -133,11 +133,11 @@ STATIC void lcd_print_char(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16 { if (m_fg_color < LCD_WHITE) { - lcd_disable_pixel(m_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + lcd_disable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); } else { - lcd_enable_pixel(m_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + lcd_enable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); } } } @@ -150,11 +150,11 @@ STATIC void lcd_print_char(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16 { if (m_bg_color < LCD_WHITE) { - lcd_disable_pixel(m_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + lcd_disable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); } else { - lcd_enable_pixel(m_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + lcd_enable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); } } } @@ -164,57 +164,57 @@ STATIC void lcd_print_char(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16 } #if 0 -STATIC void lcd_font_size_set(mp_obj_framebuf_t * m_framebuffer, uint8_t size) +STATIC void lcd_font_size_set(mp_obj_framebuf_t * p_framebuffer, uint8_t size) { m_font_size = size; } -STATIC uint8_t lcd_font_size_get(mp_obj_framebuf_t * m_framebuffer) +STATIC uint8_t lcd_font_size_get(mp_obj_framebuf_t * p_framebuffer) { return m_font_size; } #endif -STATIC void lcd_print_string(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y, const char * p_str) +STATIC void lcd_print_string(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, const char * p_str) { uint16_t str_len = strlen(p_str); for (uint16_t i = 0; i < str_len; i++) { - lcd_print_char(m_framebuffer, x + (i * 8 * m_font_size), y, p_str[i]); + lcd_print_char(p_framebuffer, x + (i * 8 * m_font_size), y, p_str[i]); } } -STATIC void lcd_pixel_draw(mp_obj_framebuf_t * m_framebuffer, uint16_t x, uint16_t y, uint16_t color) +STATIC void lcd_pixel_draw(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, uint16_t color) { if (color < LCD_WHITE) { - lcd_disable_pixel(m_framebuffer, x, y); + lcd_disable_pixel(p_framebuffer, x, y); } else { - lcd_enable_pixel(m_framebuffer, x, y); + lcd_enable_pixel(p_framebuffer, x, y); } } -STATIC void lcd_update(mp_obj_framebuf_t * m_framebuffer) { - for (uint16_t i = 0; i < m_framebuffer->dirty_stride; i++) +STATIC void lcd_update(mp_obj_framebuf_t * p_framebuffer) { + for (uint16_t i = 0; i < p_framebuffer->dirty_stride; i++) { - if (m_framebuffer->fb_dirty[i].byte != 0) + if (p_framebuffer->fb_dirty[i].byte != 0) { for (uint16_t b = 0; b < 8; b++) { - if (((m_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) + if (((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) { uint16_t line_num = (i * 8) + b; mp_obj_t args[3]; - args[0] = m_framebuffer; + args[0] = p_framebuffer; args[1] = MP_OBJ_NEW_SMALL_INT(line_num); - args[2] = mp_obj_new_bytearray_by_ref(m_framebuffer->bytes_stride, - &m_framebuffer->fb_bytes[line_num * m_framebuffer->bytes_stride]); - mp_call_function_n_kw(m_framebuffer->line_update_cb, 3, 0, args); + args[2] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, + &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); + mp_call_function_n_kw(p_framebuffer->line_update_cb, 3, 0, args); } } - m_framebuffer->fb_dirty[i].byte = 0x00; + p_framebuffer->fb_dirty[i].byte = 0x00; } } } From 6179abd6f711b63ecef2829fd833e6f3798d5572 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 14:30:24 +0100 Subject: [PATCH 065/809] nrf5/lcd: Updating brackets in framebuffer module. --- nrf5/lcd_mono_fb.c | 113 ++++++++++++++++----------------------------- 1 file changed, 41 insertions(+), 72 deletions(-) diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index 7e3f4d73e8..726a929fec 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -52,8 +52,7 @@ static uint8_t m_bg_color; static uint8_t m_fg_color; static uint8_t m_font_size; -STATIC void lcd_enable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) -{ +STATIC void lcd_enable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { uint16_t column = (x / 8); uint16_t line = y; uint8_t bit_pos = x % 8; @@ -62,8 +61,7 @@ STATIC void lcd_enable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint p_framebuffer->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); } -STATIC void lcd_disable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) -{ +STATIC void lcd_disable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { uint16_t column = (x / 8); uint16_t line = y; uint8_t bit_pos = x % 8; @@ -72,8 +70,7 @@ STATIC void lcd_disable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uin p_framebuffer->fb_dirty[y/8].byte |= (uint8_t)(0x1 << y % 8); } -STATIC void lcd_init(mp_obj_framebuf_t * p_framebuffer) -{ +STATIC void lcd_init(mp_obj_framebuf_t * p_framebuffer) { m_fg_color = LCD_BLACK; m_bg_color = LCD_WHITE; @@ -81,32 +78,27 @@ STATIC void lcd_init(mp_obj_framebuf_t * p_framebuffer) memset(p_framebuffer->fb_dirty, 0x00, p_framebuffer->dirty_stride); } -STATIC void lcd_fg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) -{ +STATIC void lcd_fg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { m_fg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; } #if 0 -STATIC uint16_t lcd_fg_color_get(mp_obj_framebuf_t * p_framebuffer) -{ +STATIC uint16_t lcd_fg_color_get(mp_obj_framebuf_t * p_framebuffer) { return m_fg_color; } #endif -STATIC void lcd_bg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) -{ +STATIC void lcd_bg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { m_bg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; } #if 0 -STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * p_framebuffer) -{ +STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * p_framebuffer) { return m_bg_color; } #endif -STATIC void lcd_clear_screen(mp_obj_framebuf_t * p_framebuffer) -{ +STATIC void lcd_clear_screen(mp_obj_framebuf_t * p_framebuffer) { if (m_bg_color == LCD_BLACK) { memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); } else { @@ -115,45 +107,33 @@ STATIC void lcd_clear_screen(mp_obj_framebuf_t * p_framebuffer) memset(p_framebuffer->fb_dirty, 0xFF, p_framebuffer->dirty_stride); } -STATIC void lcd_print_char(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, char ch) -{ - - //int column = (x / 8); +STATIC void lcd_print_char(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, char ch) { uint16_t line = y; - for (uint8_t i = 0; i < 8; i++) - { + for (uint8_t i = 0; i < 8; i++) { + uint16_t current_line = line + (i * m_font_size); - for (uint8_t x_pos = 0; x_pos < 8; x_pos++) - { - if (((uint8_t)font_8x8[ch - 32][i] >> x_pos) & 0x01) - { - for (uint8_t s_w = 0; s_w < m_font_size; s_w++) - { - for (uint8_t s_h = 0; s_h < m_font_size; s_h++) - { - if (m_fg_color < LCD_WHITE) - { - lcd_disable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); - } - else - { - lcd_enable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + + for (uint8_t x_pos = 0; x_pos < 8; x_pos++) { + if (((uint8_t)font_8x8[ch - 32][i] >> x_pos) & 0x01) { + for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { + for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { + if (m_fg_color < LCD_WHITE) { + lcd_disable_pixel(p_framebuffer, + x + (x_pos * m_font_size) + s_w, + current_line + s_h); + } else { + lcd_enable_pixel(p_framebuffer, + x + (x_pos * m_font_size) + s_w, + current_line + s_h); } } } - } - else - { - for (uint8_t s_w = 0; s_w < m_font_size; s_w++) - { - for (uint8_t s_h = 0; s_h < m_font_size; s_h++) - { - if (m_bg_color < LCD_WHITE) - { + } else { + for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { + for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { + if (m_bg_color < LCD_WHITE) { lcd_disable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); - } - else - { + } else { lcd_enable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); } } @@ -164,47 +144,35 @@ STATIC void lcd_print_char(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16 } #if 0 -STATIC void lcd_font_size_set(mp_obj_framebuf_t * p_framebuffer, uint8_t size) -{ +STATIC void lcd_font_size_set(mp_obj_framebuf_t * p_framebuffer, uint8_t size) { m_font_size = size; } -STATIC uint8_t lcd_font_size_get(mp_obj_framebuf_t * p_framebuffer) -{ +STATIC uint8_t lcd_font_size_get(mp_obj_framebuf_t * p_framebuffer) { return m_font_size; } #endif -STATIC void lcd_print_string(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, const char * p_str) -{ +STATIC void lcd_print_string(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, const char * p_str) { uint16_t str_len = strlen(p_str); - for (uint16_t i = 0; i < str_len; i++) - { + for (uint16_t i = 0; i < str_len; i++) { lcd_print_char(p_framebuffer, x + (i * 8 * m_font_size), y, p_str[i]); } } -STATIC void lcd_pixel_draw(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, uint16_t color) -{ - if (color < LCD_WHITE) - { +STATIC void lcd_pixel_draw(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, uint16_t color) { + if (color < LCD_WHITE) { lcd_disable_pixel(p_framebuffer, x, y); - } - else - { + } else { lcd_enable_pixel(p_framebuffer, x, y); } } STATIC void lcd_update(mp_obj_framebuf_t * p_framebuffer) { - for (uint16_t i = 0; i < p_framebuffer->dirty_stride; i++) - { - if (p_framebuffer->fb_dirty[i].byte != 0) - { - for (uint16_t b = 0; b < 8; b++) - { - if (((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) - { + for (uint16_t i = 0; i < p_framebuffer->dirty_stride; i++) { + if (p_framebuffer->fb_dirty[i].byte != 0) { + for (uint16_t b = 0; b < 8; b++) { + if (((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) { uint16_t line_num = (i * 8) + b; mp_obj_t args[3]; args[0] = p_framebuffer; @@ -214,6 +182,7 @@ STATIC void lcd_update(mp_obj_framebuf_t * p_framebuffer) { mp_call_function_n_kw(p_framebuffer->line_update_cb, 3, 0, args); } } + p_framebuffer->fb_dirty[i].byte = 0x00; } } From 06263713780124780a4c12c29cb15c1abf377fe7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 14:31:56 +0100 Subject: [PATCH 066/809] nrf5/lcd: Adding header file for lcd_mono_fb. --- nrf5/lcd_mono_fb.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 nrf5/lcd_mono_fb.h diff --git a/nrf5/lcd_mono_fb.h b/nrf5/lcd_mono_fb.h new file mode 100644 index 0000000000..17e9af1556 --- /dev/null +++ b/nrf5/lcd_mono_fb.h @@ -0,0 +1,54 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LCD_MONO_FB_H__ +#define LCD_MONO_FB_H__ + +extern const mp_obj_module_t mp_module_lcd_mono_fb; + +#include + +typedef struct +{ + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; + +} bits_t; + +typedef struct { + union { + uint8_t byte; + bits_t bits; + }; +} fb_byte_t; + +#endif From af116d1d80e318dffff885190b67ae10b7f445ff Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 14:39:41 +0100 Subject: [PATCH 067/809] nrf5/modules: Adding new driver for seeedstudio tft shield v2, using new framebuffer module which handles faster update on single lines, callback driven write on each line which is touched in the framebuffer. --- nrf5/modules/seeed.py | 191 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 nrf5/modules/seeed.py diff --git a/nrf5/modules/seeed.py b/nrf5/modules/seeed.py new file mode 100644 index 0000000000..9e199c7084 --- /dev/null +++ b/nrf5/modules/seeed.py @@ -0,0 +1,191 @@ +""" +MicroPython Seeedstudio TFT Shield V2 driver, SPI interfaces, Analog GPIO +Contains SD-card reader, LCD and Touch sensor + +Example usage of LCD: + + from seeed import ILI9341 + + lcd = ILI9341(320, 240, False) # Horizontal view + lcd.text("Hello World!, 32, 32) + lcd.show() + +Example usage of SD card reader: + + import os + from seeedstudio_tft_shield_v2 import mount_tf + + tf = mount_tf() + os.listdir() +""" +import os +import time +import lcd_mono_fb + +from machine import SPI, Pin +from sdcard import SDCard + +def mount_tf(self, mount_point="/"): + sd = SDCard(SPI(0), Pin("A15", mode=Pin.OUT)) + os.mount(sd, mount_point) + +class ILI9341: + def __init__(self, width=240, height=320, vertical=True): + self.width = width + self.height = height + self.vertical = vertical + self.framebuf = lcd_mono_fb.MonoFB(self.line_update, self.width, self.height) + + self.spi = SPI(0) + # chip select + self.cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) + # command + self.dc = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) + + # initialize all pins high + self.cs.high() + self.dc.high() + + self.spi.init(baudrate=8000000, phase=0, polarity=0) + + self.init_display() + + def line_update(self, o, line, bytes): + if self.vertical: + # set col + self.write_cmd(0x2A) + self.write_data(bytearray([0x00, 0x00, 0x00, 0xEF])) + + # set page + self.write_cmd(0x2B) + self.write_data(bytearray([line >> 8, line & 0xFF, line >> 8, line & 0xFF])) + else: + # set col + self.write_cmd(0x2A) + self.write_data(bytearray([0x00, 0x00, 0x01, 0x3F])) + + # set page + self.write_cmd(0x2B) + self.write_data(bytearray([line >> 8, line & 0xFF, line >> 8, line & 0xFF])) + + self.write_cmd(0x2c); + + for compressed_pixel in bytes: + for pixel_pos in range(0, 8): + if ((compressed_pixel >> pixel_pos) & 0x1) == 0: + self.write_data(bytearray([0x00, 0x00])) + else: + self.write_data(bytearray([0xFF, 0xFF])) + + def init_display(self): + time.sleep_ms(500) + + self.write_cmd(0x01) + + time.sleep_ms(200) + + self.write_cmd(0xCF) + self.write_data(bytearray([0x00, 0x8B, 0x30])) + + self.write_cmd(0xED) + self.write_data(bytearray([0x67, 0x03, 0x12, 0x81])) + + self.write_cmd(0xE8) + self.write_data(bytearray([0x85, 0x10, 0x7A])) + + self.write_cmd(0xCB) + self.write_data(bytearray([0x39, 0x2C, 0x00, 0x34, 0x02])) + + self.write_cmd(0xF7) + self.write_data(bytearray([0x20])) + + self.write_cmd(0xEA) + self.write_data(bytearray([0x00, 0x00])) + + # Power control + self.write_cmd(0xC0) + # VRH[5:0] + self.write_data(bytearray([0x1B])) + + # Power control + self.write_cmd(0xC1) + # SAP[2:0];BT[3:0] + self.write_data(bytearray([0x10])) + + # VCM control + self.write_cmd(0xC5) + self.write_data(bytearray([0x3F, 0x3C])) + + # VCM control2 + self.write_cmd(0xC7) + self.write_data(bytearray([0xB7])) + + # Memory Access Control + self.write_cmd(0x36) + if self.vertical: + self.write_data(bytearray([0x08])) + else: + self.write_data(bytearray([0x08 | (0x4 | 0x1) << 5])) + + self.write_cmd(0x3A) + self.write_data(bytearray([0x55])) + + self.write_cmd(0xB1) + self.write_data(bytearray([0x00, 0x1B])) + + # Display Function Control + self.write_cmd(0xB6) + self.write_data(bytearray([0x0A, 0xA2])) + + # 3Gamma Function Disable + self.write_cmd(0xF2) + self.write_data(bytearray([0x00])) + + # Gamma curve selected + self.write_cmd(0x26) + self.write_data(bytearray([0x01])) + + # Set Gamma + self.write_cmd(0xE0) + self.write_data(bytearray([0x0F, 0x2A, 0x28, 0x08, 0x0E, 0x08, 0x54, 0XA9, 0x43, 0x0A, 0x0F, 0x00, 0x00, 0x00, 0x00])) + + # Set Gamma + self.write_cmd(0XE1) + self.write_data(bytearray([0x00, 0x15, 0x17, 0x07, 0x11, 0x06, 0x2B, 0x56, 0x3C, 0x05, 0x10, 0x0F, 0x3F, 0x3F, 0x0F])) + + # Exit Sleep + self.write_cmd(0x11) + time.sleep_ms(120) + + # Display on + self.write_cmd(0x29) + time.sleep_ms(500) + self.fill(0) + + def show(self): + self.framebuf.show() + + def fill(self, col): + self.framebuf.fill(col) + + def pixel(self, x, y, col): + self.framebuf.pixel(x, y, col) + + def scroll(self, dx, dy): + self.framebuf.scroll(dx, dy) + + def text(self, string, x, y, col=1): + self.framebuf.text(string, x, y, col) + + def write_cmd(self, cmd): + self.dc.low() + self.cs.low() + self.spi.write(bytearray([cmd])) + self.cs.high() + + def write_data(self, buf): + self.dc.high() + self.cs.low() + self.spi.write(buf) + self.cs.high() + From c8ff22ced0edd48e4c5392bed7ee79c36c23f529 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 15:35:24 +0100 Subject: [PATCH 068/809] nrf5/lcd: Changing framebuffer to use petme128 8x8 font. This is vertical font. Code modified to flip and mirror the font when rendering a character. Adding copy of the font from stmhal. --- nrf5/font_petme128_8x8.h | 124 +++++++++++++++++++++++++++++++++++++++ nrf5/lcd_mono_fb.c | 26 ++++---- 2 files changed, 139 insertions(+), 11 deletions(-) create mode 100644 nrf5/font_petme128_8x8.h diff --git a/nrf5/font_petme128_8x8.h b/nrf5/font_petme128_8x8.h new file mode 100644 index 0000000000..7f928edda4 --- /dev/null +++ b/nrf5/font_petme128_8x8.h @@ -0,0 +1,124 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +static const uint8_t font_petme128_8x8[] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // 32= + 0x00,0x00,0x00,0x4f,0x4f,0x00,0x00,0x00, // 33=! + 0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00, // 34=" + 0x14,0x7f,0x7f,0x14,0x14,0x7f,0x7f,0x14, // 35=# + 0x00,0x24,0x2e,0x6b,0x6b,0x3a,0x12,0x00, // 36=$ + 0x00,0x63,0x33,0x18,0x0c,0x66,0x63,0x00, // 37=% + 0x00,0x32,0x7f,0x4d,0x4d,0x77,0x72,0x50, // 38=& + 0x00,0x00,0x00,0x04,0x06,0x03,0x01,0x00, // 39=' + 0x00,0x00,0x1c,0x3e,0x63,0x41,0x00,0x00, // 40=( + 0x00,0x00,0x41,0x63,0x3e,0x1c,0x00,0x00, // 41=) + 0x08,0x2a,0x3e,0x1c,0x1c,0x3e,0x2a,0x08, // 42=* + 0x00,0x08,0x08,0x3e,0x3e,0x08,0x08,0x00, // 43=+ + 0x00,0x00,0x80,0xe0,0x60,0x00,0x00,0x00, // 44=, + 0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x00, // 45=- + 0x00,0x00,0x00,0x60,0x60,0x00,0x00,0x00, // 46=. + 0x00,0x40,0x60,0x30,0x18,0x0c,0x06,0x02, // 47=/ + 0x00,0x3e,0x7f,0x49,0x45,0x7f,0x3e,0x00, // 48=0 + 0x00,0x40,0x44,0x7f,0x7f,0x40,0x40,0x00, // 49=1 + 0x00,0x62,0x73,0x51,0x49,0x4f,0x46,0x00, // 50=2 + 0x00,0x22,0x63,0x49,0x49,0x7f,0x36,0x00, // 51=3 + 0x00,0x18,0x18,0x14,0x16,0x7f,0x7f,0x10, // 52=4 + 0x00,0x27,0x67,0x45,0x45,0x7d,0x39,0x00, // 53=5 + 0x00,0x3e,0x7f,0x49,0x49,0x7b,0x32,0x00, // 54=6 + 0x00,0x03,0x03,0x79,0x7d,0x07,0x03,0x00, // 55=7 + 0x00,0x36,0x7f,0x49,0x49,0x7f,0x36,0x00, // 56=8 + 0x00,0x26,0x6f,0x49,0x49,0x7f,0x3e,0x00, // 57=9 + 0x00,0x00,0x00,0x24,0x24,0x00,0x00,0x00, // 58=: + 0x00,0x00,0x80,0xe4,0x64,0x00,0x00,0x00, // 59=; + 0x00,0x08,0x1c,0x36,0x63,0x41,0x41,0x00, // 60=< + 0x00,0x14,0x14,0x14,0x14,0x14,0x14,0x00, // 61== + 0x00,0x41,0x41,0x63,0x36,0x1c,0x08,0x00, // 62=> + 0x00,0x02,0x03,0x51,0x59,0x0f,0x06,0x00, // 63=? + 0x00,0x3e,0x7f,0x41,0x4d,0x4f,0x2e,0x00, // 64=@ + 0x00,0x7c,0x7e,0x0b,0x0b,0x7e,0x7c,0x00, // 65=A + 0x00,0x7f,0x7f,0x49,0x49,0x7f,0x36,0x00, // 66=B + 0x00,0x3e,0x7f,0x41,0x41,0x63,0x22,0x00, // 67=C + 0x00,0x7f,0x7f,0x41,0x63,0x3e,0x1c,0x00, // 68=D + 0x00,0x7f,0x7f,0x49,0x49,0x41,0x41,0x00, // 69=E + 0x00,0x7f,0x7f,0x09,0x09,0x01,0x01,0x00, // 70=F + 0x00,0x3e,0x7f,0x41,0x49,0x7b,0x3a,0x00, // 71=G + 0x00,0x7f,0x7f,0x08,0x08,0x7f,0x7f,0x00, // 72=H + 0x00,0x00,0x41,0x7f,0x7f,0x41,0x00,0x00, // 73=I + 0x00,0x20,0x60,0x41,0x7f,0x3f,0x01,0x00, // 74=J + 0x00,0x7f,0x7f,0x1c,0x36,0x63,0x41,0x00, // 75=K + 0x00,0x7f,0x7f,0x40,0x40,0x40,0x40,0x00, // 76=L + 0x00,0x7f,0x7f,0x06,0x0c,0x06,0x7f,0x7f, // 77=M + 0x00,0x7f,0x7f,0x0e,0x1c,0x7f,0x7f,0x00, // 78=N + 0x00,0x3e,0x7f,0x41,0x41,0x7f,0x3e,0x00, // 79=O + 0x00,0x7f,0x7f,0x09,0x09,0x0f,0x06,0x00, // 80=P + 0x00,0x1e,0x3f,0x21,0x61,0x7f,0x5e,0x00, // 81=Q + 0x00,0x7f,0x7f,0x19,0x39,0x6f,0x46,0x00, // 82=R + 0x00,0x26,0x6f,0x49,0x49,0x7b,0x32,0x00, // 83=S + 0x00,0x01,0x01,0x7f,0x7f,0x01,0x01,0x00, // 84=T + 0x00,0x3f,0x7f,0x40,0x40,0x7f,0x3f,0x00, // 85=U + 0x00,0x1f,0x3f,0x60,0x60,0x3f,0x1f,0x00, // 86=V + 0x00,0x7f,0x7f,0x30,0x18,0x30,0x7f,0x7f, // 87=W + 0x00,0x63,0x77,0x1c,0x1c,0x77,0x63,0x00, // 88=X + 0x00,0x07,0x0f,0x78,0x78,0x0f,0x07,0x00, // 89=Y + 0x00,0x61,0x71,0x59,0x4d,0x47,0x43,0x00, // 90=Z + 0x00,0x00,0x7f,0x7f,0x41,0x41,0x00,0x00, // 91=[ + 0x00,0x02,0x06,0x0c,0x18,0x30,0x60,0x40, // 92='\' + 0x00,0x00,0x41,0x41,0x7f,0x7f,0x00,0x00, // 93=] + 0x00,0x08,0x0c,0x06,0x06,0x0c,0x08,0x00, // 94=^ + 0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0, // 95=_ + 0x00,0x00,0x01,0x03,0x06,0x04,0x00,0x00, // 96=` + 0x00,0x20,0x74,0x54,0x54,0x7c,0x78,0x00, // 97=a + 0x00,0x7f,0x7f,0x44,0x44,0x7c,0x38,0x00, // 98=b + 0x00,0x38,0x7c,0x44,0x44,0x6c,0x28,0x00, // 99=c + 0x00,0x38,0x7c,0x44,0x44,0x7f,0x7f,0x00, // 100=d + 0x00,0x38,0x7c,0x54,0x54,0x5c,0x58,0x00, // 101=e + 0x00,0x08,0x7e,0x7f,0x09,0x03,0x02,0x00, // 102=f + 0x00,0x98,0xbc,0xa4,0xa4,0xfc,0x7c,0x00, // 103=g + 0x00,0x7f,0x7f,0x04,0x04,0x7c,0x78,0x00, // 104=h + 0x00,0x00,0x00,0x7d,0x7d,0x00,0x00,0x00, // 105=i + 0x00,0x40,0xc0,0x80,0x80,0xfd,0x7d,0x00, // 106=j + 0x00,0x7f,0x7f,0x30,0x38,0x6c,0x44,0x00, // 107=k + 0x00,0x00,0x41,0x7f,0x7f,0x40,0x00,0x00, // 108=l + 0x00,0x7c,0x7c,0x18,0x30,0x18,0x7c,0x7c, // 109=m + 0x00,0x7c,0x7c,0x04,0x04,0x7c,0x78,0x00, // 110=n + 0x00,0x38,0x7c,0x44,0x44,0x7c,0x38,0x00, // 111=o + 0x00,0xfc,0xfc,0x24,0x24,0x3c,0x18,0x00, // 112=p + 0x00,0x18,0x3c,0x24,0x24,0xfc,0xfc,0x00, // 113=q + 0x00,0x7c,0x7c,0x04,0x04,0x0c,0x08,0x00, // 114=r + 0x00,0x48,0x5c,0x54,0x54,0x74,0x20,0x00, // 115=s + 0x04,0x04,0x3f,0x7f,0x44,0x64,0x20,0x00, // 116=t + 0x00,0x3c,0x7c,0x40,0x40,0x7c,0x3c,0x00, // 117=u + 0x00,0x1c,0x3c,0x60,0x60,0x3c,0x1c,0x00, // 118=v + 0x00,0x1c,0x7c,0x30,0x18,0x30,0x7c,0x1c, // 119=w + 0x00,0x44,0x6c,0x38,0x38,0x6c,0x44,0x00, // 120=x + 0x00,0x9c,0xbc,0xa0,0xa0,0xfc,0x7c,0x00, // 121=y + 0x00,0x44,0x64,0x74,0x5c,0x4c,0x44,0x00, // 122=z + 0x00,0x08,0x08,0x3e,0x77,0x41,0x41,0x00, // 123={ + 0x00,0x00,0x00,0xff,0xff,0x00,0x00,0x00, // 124=| + 0x00,0x41,0x41,0x77,0x3e,0x08,0x08,0x00, // 125=} + 0x00,0x02,0x03,0x01,0x03,0x02,0x03,0x01, // 126=~ + 0xaa,0x55,0xaa,0x55,0xaa,0x55,0xaa,0x55, // 127 +}; diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index 726a929fec..11029dbe41 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -32,7 +32,7 @@ #include "py/runtime.h" #include "lcd_mono_fb.h" -#include "font.h" +#include "font_petme128_8x8.h" #define LCD_BLACK 0 #define LCD_WHITE 1 @@ -108,23 +108,23 @@ STATIC void lcd_clear_screen(mp_obj_framebuf_t * p_framebuffer) { } STATIC void lcd_print_char(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, char ch) { - uint16_t line = y; + uint16_t col = x; for (uint8_t i = 0; i < 8; i++) { - uint16_t current_line = line + (i * m_font_size); + uint16_t current_col = col + (i * m_font_size); - for (uint8_t x_pos = 0; x_pos < 8; x_pos++) { - if (((uint8_t)font_8x8[ch - 32][i] >> x_pos) & 0x01) { + for (uint8_t y_pos = 0; y_pos < 8; y_pos++) { + if ((((uint8_t)font_petme128_8x8[((ch - 32) * 8) + i]) >> y_pos) & 0x01) { for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { if (m_fg_color < LCD_WHITE) { lcd_disable_pixel(p_framebuffer, - x + (x_pos * m_font_size) + s_w, - current_line + s_h); + current_col + s_w, + y + (y_pos * m_font_size) + s_h); } else { lcd_enable_pixel(p_framebuffer, - x + (x_pos * m_font_size) + s_w, - current_line + s_h); + current_col + s_w, + y + (y_pos * m_font_size) + s_h); } } } @@ -132,9 +132,13 @@ STATIC void lcd_print_char(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16 for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { if (m_bg_color < LCD_WHITE) { - lcd_disable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + lcd_disable_pixel(p_framebuffer, + current_col + s_w, + y + (y_pos * m_font_size) + s_h); } else { - lcd_enable_pixel(p_framebuffer, x + (x_pos * m_font_size) + s_w, current_line + s_h); + lcd_enable_pixel(p_framebuffer, + current_col + s_w, + y + (y_pos * m_font_size) + s_h); } } } From 82746d4549438c2528c4991fb3894b3236c2d609 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 15:54:47 +0100 Subject: [PATCH 069/809] nrf5/lcd: Correcting indention (tabs with space) in framebuffer module source and header. --- nrf5/lcd_mono_fb.c | 199 ++++++++++++++++++++++----------------------- nrf5/lcd_mono_fb.h | 28 +++---- 2 files changed, 112 insertions(+), 115 deletions(-) diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index 11029dbe41..b369eb9e2f 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -38,14 +38,14 @@ #define LCD_WHITE 1 typedef struct { - mp_obj_base_t base; - fb_byte_t * fb_bytes; - fb_byte_t * fb_dirty; - uint16_t height; - uint16_t width; - mp_uint_t bytes_stride; - mp_uint_t dirty_stride; - mp_obj_t line_update_cb; + mp_obj_base_t base; + fb_byte_t * fb_bytes; + fb_byte_t * fb_dirty; + uint16_t height; + uint16_t width; + mp_uint_t bytes_stride; + mp_uint_t dirty_stride; + mp_obj_t line_update_cb; } mp_obj_framebuf_t; static uint8_t m_bg_color; @@ -53,17 +53,17 @@ static uint8_t m_fg_color; static uint8_t m_font_size; STATIC void lcd_enable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { - uint16_t column = (x / 8); - uint16_t line = y; - uint8_t bit_pos = x % 8; + uint16_t column = (x / 8); + uint16_t line = y; + uint8_t bit_pos = x % 8; - p_framebuffer->fb_bytes[line * (p_framebuffer->bytes_stride) + column].byte |= (1 << bit_pos); - p_framebuffer->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); + p_framebuffer->fb_bytes[line * (p_framebuffer->bytes_stride) + column].byte |= (1 << bit_pos); + p_framebuffer->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); } STATIC void lcd_disable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { - uint16_t column = (x / 8); - uint16_t line = y; + uint16_t column = (x / 8); + uint16_t line = y; uint8_t bit_pos = x % 8; p_framebuffer->fb_bytes[line * (p_framebuffer->bytes_stride) + column].byte &= ~(1 << bit_pos); @@ -71,125 +71,125 @@ STATIC void lcd_disable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uin } STATIC void lcd_init(mp_obj_framebuf_t * p_framebuffer) { - m_fg_color = LCD_BLACK; - m_bg_color = LCD_WHITE; + m_fg_color = LCD_BLACK; + m_bg_color = LCD_WHITE; - memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); - memset(p_framebuffer->fb_dirty, 0x00, p_framebuffer->dirty_stride); + memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); + memset(p_framebuffer->fb_dirty, 0x00, p_framebuffer->dirty_stride); } STATIC void lcd_fg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { - m_fg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; + m_fg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; } #if 0 STATIC uint16_t lcd_fg_color_get(mp_obj_framebuf_t * p_framebuffer) { - return m_fg_color; + return m_fg_color; } #endif STATIC void lcd_bg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { - m_bg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; + m_bg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; } #if 0 STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * p_framebuffer) { - return m_bg_color; + return m_bg_color; } #endif STATIC void lcd_clear_screen(mp_obj_framebuf_t * p_framebuffer) { - if (m_bg_color == LCD_BLACK) { - memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); - } else { - memset(p_framebuffer->fb_bytes, 0xFF, p_framebuffer->bytes_stride * p_framebuffer->height); - } - memset(p_framebuffer->fb_dirty, 0xFF, p_framebuffer->dirty_stride); + if (m_bg_color == LCD_BLACK) { + memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); + } else { + memset(p_framebuffer->fb_bytes, 0xFF, p_framebuffer->bytes_stride * p_framebuffer->height); + } + memset(p_framebuffer->fb_dirty, 0xFF, p_framebuffer->dirty_stride); } STATIC void lcd_print_char(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, char ch) { - uint16_t col = x; - for (uint8_t i = 0; i < 8; i++) { + uint16_t col = x; + for (uint8_t i = 0; i < 8; i++) { - uint16_t current_col = col + (i * m_font_size); + uint16_t current_col = col + (i * m_font_size); - for (uint8_t y_pos = 0; y_pos < 8; y_pos++) { - if ((((uint8_t)font_petme128_8x8[((ch - 32) * 8) + i]) >> y_pos) & 0x01) { - for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { - for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { - if (m_fg_color < LCD_WHITE) { - lcd_disable_pixel(p_framebuffer, - current_col + s_w, - y + (y_pos * m_font_size) + s_h); - } else { - lcd_enable_pixel(p_framebuffer, - current_col + s_w, - y + (y_pos * m_font_size) + s_h); - } - } - } - } else { - for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { - for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { - if (m_bg_color < LCD_WHITE) { - lcd_disable_pixel(p_framebuffer, - current_col + s_w, - y + (y_pos * m_font_size) + s_h); - } else { - lcd_enable_pixel(p_framebuffer, - current_col + s_w, - y + (y_pos * m_font_size) + s_h); - } - } - } - } - } - } + for (uint8_t y_pos = 0; y_pos < 8; y_pos++) { + if ((((uint8_t)font_petme128_8x8[((ch - 32) * 8) + i]) >> y_pos) & 0x01) { + for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { + for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { + if (m_fg_color < LCD_WHITE) { + lcd_disable_pixel(p_framebuffer, + current_col + s_w, + y + (y_pos * m_font_size) + s_h); + } else { + lcd_enable_pixel(p_framebuffer, + current_col + s_w, + y + (y_pos * m_font_size) + s_h); + } + } + } + } else { + for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { + for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { + if (m_bg_color < LCD_WHITE) { + lcd_disable_pixel(p_framebuffer, + current_col + s_w, + y + (y_pos * m_font_size) + s_h); + } else { + lcd_enable_pixel(p_framebuffer, + current_col + s_w, + y + (y_pos * m_font_size) + s_h); + } + } + } + } + } + } } #if 0 STATIC void lcd_font_size_set(mp_obj_framebuf_t * p_framebuffer, uint8_t size) { - m_font_size = size; + m_font_size = size; } STATIC uint8_t lcd_font_size_get(mp_obj_framebuf_t * p_framebuffer) { - return m_font_size; + return m_font_size; } #endif STATIC void lcd_print_string(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, const char * p_str) { - uint16_t str_len = strlen(p_str); - for (uint16_t i = 0; i < str_len; i++) { - lcd_print_char(p_framebuffer, x + (i * 8 * m_font_size), y, p_str[i]); - } + uint16_t str_len = strlen(p_str); + for (uint16_t i = 0; i < str_len; i++) { + lcd_print_char(p_framebuffer, x + (i * 8 * m_font_size), y, p_str[i]); + } } STATIC void lcd_pixel_draw(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, uint16_t color) { - if (color < LCD_WHITE) { - lcd_disable_pixel(p_framebuffer, x, y); - } else { - lcd_enable_pixel(p_framebuffer, x, y); - } + if (color < LCD_WHITE) { + lcd_disable_pixel(p_framebuffer, x, y); + } else { + lcd_enable_pixel(p_framebuffer, x, y); + } } STATIC void lcd_update(mp_obj_framebuf_t * p_framebuffer) { - for (uint16_t i = 0; i < p_framebuffer->dirty_stride; i++) { - if (p_framebuffer->fb_dirty[i].byte != 0) { - for (uint16_t b = 0; b < 8; b++) { - if (((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) { - uint16_t line_num = (i * 8) + b; - mp_obj_t args[3]; - args[0] = p_framebuffer; - args[1] = MP_OBJ_NEW_SMALL_INT(line_num); - args[2] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, - &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); - mp_call_function_n_kw(p_framebuffer->line_update_cb, 3, 0, args); - } - } + for (uint16_t i = 0; i < p_framebuffer->dirty_stride; i++) { + if (p_framebuffer->fb_dirty[i].byte != 0) { + for (uint16_t b = 0; b < 8; b++) { + if (((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) { + uint16_t line_num = (i * 8) + b; + mp_obj_t args[3]; + args[0] = p_framebuffer; + args[1] = MP_OBJ_NEW_SMALL_INT(line_num); + args[2] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, + &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); + mp_call_function_n_kw(p_framebuffer->line_update_cb, 3, 0, args); + } + } - p_framebuffer->fb_dirty[i].byte = 0x00; - } - } + p_framebuffer->fb_dirty[i].byte = 0x00; + } + } } STATIC mp_obj_t lcd_mono_fb_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { @@ -217,10 +217,9 @@ STATIC mp_obj_t lcd_mono_fb_make_new(const mp_obj_type_t *type, size_t n_args, s } STATIC mp_obj_t lcd_mono_fb_fill(mp_obj_t self_in, mp_obj_t col_in) { - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); mp_int_t col = mp_obj_get_int(col_in); - lcd_bg_color_set(self, col); lcd_fg_color_set(self, !col); @@ -231,7 +230,7 @@ STATIC mp_obj_t lcd_mono_fb_fill(mp_obj_t self_in, mp_obj_t col_in) { STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_mono_fb_fill_obj, lcd_mono_fb_fill); STATIC mp_obj_t lcd_mono_fb_pixel(size_t n_args, const mp_obj_t *args) { - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(args[0]); + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(args[0]); mp_int_t x = mp_obj_get_int(args[1]); mp_int_t y = mp_obj_get_int(args[2]); mp_int_t color = mp_obj_get_int(args[3]); @@ -244,7 +243,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_mono_fb_pixel_obj, 3, 4, lcd_mono STATIC mp_obj_t lcd_mono_fb_scroll(mp_obj_t self_in, mp_obj_t xstep_in, mp_obj_t ystep_in) { #if 0 - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); mp_int_t xstep = mp_obj_get_int(xstep_in); mp_int_t ystep = mp_obj_get_int(ystep_in); #endif @@ -254,7 +253,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_3(lcd_mono_fb_scroll_obj, lcd_mono_fb_scroll); STATIC mp_obj_t lcd_mono_fb_text(size_t n_args, const mp_obj_t *args) { // extract arguments - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(args[0]); + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(args[0]); const char *str = mp_obj_str_get_str(args[1]); mp_int_t x0 = mp_obj_get_int(args[2]); mp_int_t y0 = mp_obj_get_int(args[3]); @@ -267,16 +266,16 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_mono_fb_text_obj, 4, 5, lcd_mono_ STATIC mp_obj_t lcd_mono_fb_show(mp_obj_t self_in) { - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); - lcd_update(self); + lcd_update(self); return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_show_obj, lcd_mono_fb_show); STATIC mp_obj_t lcd_mono_fb_del(mp_obj_t self_in) { - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); m_free(self->fb_bytes); m_free(self->fb_dirty); @@ -291,7 +290,7 @@ STATIC const mp_rom_map_elem_t lcd_mono_fb_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_pixel), MP_ROM_PTR(&lcd_mono_fb_pixel_obj) }, { MP_ROM_QSTR(MP_QSTR_scroll), MP_ROM_PTR(&lcd_mono_fb_scroll_obj) }, { MP_ROM_QSTR(MP_QSTR_text), MP_ROM_PTR(&lcd_mono_fb_text_obj) }, - { MP_ROM_QSTR(MP_QSTR_show), MP_ROM_PTR(&lcd_mono_fb_show_obj) }, + { MP_ROM_QSTR(MP_QSTR_show), MP_ROM_PTR(&lcd_mono_fb_show_obj) }, }; STATIC MP_DEFINE_CONST_DICT(lcd_mono_fb_locals_dict, lcd_mono_fb_locals_dict_table); diff --git a/nrf5/lcd_mono_fb.h b/nrf5/lcd_mono_fb.h index 17e9af1556..82a6d637c7 100644 --- a/nrf5/lcd_mono_fb.h +++ b/nrf5/lcd_mono_fb.h @@ -31,24 +31,22 @@ extern const mp_obj_module_t mp_module_lcd_mono_fb; #include -typedef struct -{ - uint8_t bit0 : 1; - uint8_t bit1 : 1; - uint8_t bit2 : 1; - uint8_t bit3 : 1; - uint8_t bit4 : 1; - uint8_t bit5 : 1; - uint8_t bit6 : 1; - uint8_t bit7 : 1; - +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; } bits_t; typedef struct { - union { - uint8_t byte; - bits_t bits; - }; + union { + uint8_t byte; + bits_t bits; + }; } fb_byte_t; #endif From 342ffadc59f9757283a22802ec32f71a00c7c168 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 16:11:59 +0100 Subject: [PATCH 070/809] nrf5: Adding handling of CTRL+D to reset chip in main.c. Call to NVIC System Reset is issued. --- nrf5/main.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/nrf5/main.c b/nrf5/main.c index eba42a4510..6621809bce 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -180,14 +180,21 @@ int main(int argc, char **argv) { // Main script is finished, so now go into REPL mode. // The REPL mode can change, or it can request a soft reset. + int ret_code = 0; + for (;;) { - if (pyexec_friendly_repl() != 0) { + ret_code = pyexec_friendly_repl(); + if (ret_code != 0) { break; } } mp_deinit(); + if (ret_code == PYEXEC_FORCED_EXIT) { + NVIC_SystemReset(); + } + return 0; } From 387725ce601dd2117edcb88986a379015070e2db Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 16:12:54 +0100 Subject: [PATCH 071/809] nrf5: Adding help text for CTRL-D (soft reset) and and CTRL-E (paste mode) in help.c --- nrf5/help.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/help.c b/nrf5/help.c index 04b0b00d34..a3a12bd19c 100644 --- a/nrf5/help.c +++ b/nrf5/help.c @@ -45,6 +45,10 @@ STATIC const char help_text[] = #if BLUETOOTH_SD HELP_TEXT_SD #endif +"Control commands:\n" +" CTRL-D -- on a blank line, do a soft reset of the board\n" +" CTRL-E -- on a blank line, enter paste mode\n" +"\n" "For further help on a specific object, type help(obj)\n" ; From a7832a203f202750aa0389cf801675e323608950 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 16:48:47 +0100 Subject: [PATCH 072/809] nrf52/sdk: Correcting path to iot softdevice if SDK is enabled. --- nrf5/sdk/iot_0.9.0/sdk.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/sdk/iot_0.9.0/sdk.mk b/nrf5/sdk/iot_0.9.0/sdk.mk index 81be3000cc..26544f2fc7 100644 --- a/nrf5/sdk/iot_0.9.0/sdk.mk +++ b/nrf5/sdk/iot_0.9.0/sdk.mk @@ -9,4 +9,4 @@ CFLAGS += -DBLUETOOTH_SD=100 CFLAGS += -DBLUETOOTH_SD_DEBUG=1 # softdevice .hex file -SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s1xx_iot/hex/s1xx*softdevice.hex)) +SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s1xx_iot/s1xx*softdevice.hex)) From 64d28272333b9951097237c0b9b66cb736f1dd79 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 17:03:15 +0100 Subject: [PATCH 073/809] nrf5/lcd: Adding lcd_mono_fb.c to source list in the makefile. Adding define in implementation to de-select the file from being included. Adding module to PORT BUILTIN in mpconfigport.h --- nrf5/Makefile | 1 + nrf5/lcd_mono_fb.c | 4 ++++ nrf5/mpconfigport.h | 11 ++++++++++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 42b402f258..c5dc610d9b 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -146,6 +146,7 @@ SRC_C += \ modnetwork.c \ timer.c \ rtc.c \ + lcd_mono_fb.c \ #ifeq ($(SD), ) diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index b369eb9e2f..31b9aeb0d1 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -34,6 +34,8 @@ #include "lcd_mono_fb.h" #include "font_petme128_8x8.h" +#if MICROPY_PY_LCD_MONO_FB + #define LCD_BLACK 0 #define LCD_WHITE 1 @@ -312,3 +314,5 @@ const mp_obj_module_t mp_module_lcd_mono_fb = { .base = { &mp_type_module }, .globals = (mp_obj_dict_t*)&lcd_mono_fb_module_globals, }; + +#endif // MICROPY_PY_LCD_MONO_FB diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 88c220f3be..0af3531a43 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -129,6 +129,8 @@ #define MICROPY_PY_NETWORK (1) #endif +#define MICROPY_PY_LCD_MONO_FB (0) + #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) #define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0) @@ -160,6 +162,7 @@ extern const struct _mp_obj_module_t mp_module_utime; extern const struct _mp_obj_module_t mp_module_uos; extern const struct _mp_obj_module_t mp_module_usocket; extern const struct _mp_obj_module_t mp_module_network; +extern const struct _mp_obj_module_t mp_module_lcd_mono_fb; #if MICROPY_PY_USOCKET #define SOCKET_BUILTIN_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_usocket), (mp_obj_t)&mp_module_usocket }, @@ -175,6 +178,11 @@ extern const struct _mp_obj_module_t mp_module_network; #define NETWORK_BUILTIN_MODULE #endif +#if MICROPY_PY_LCD_MONO_FB +#define LCD_MONO_FB_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_lcd_mono_fb), (mp_obj_t)&mp_module_lcd_mono_fb }, +#else +#define LCD_MONO_FB_MODULE +#endif #if BLUETOOTH_SD extern const struct _mp_obj_module_t ble_module; @@ -187,6 +195,7 @@ extern const struct _mp_obj_module_t ble_module; { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ SOCKET_BUILTIN_MODULE \ NETWORK_BUILTIN_MODULE \ + LCD_MONO_FB_MODULE \ #else @@ -196,7 +205,7 @@ extern const struct _mp_obj_module_t ble_module; { MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ - + LCD_MONO_FB_MODULE \ #endif // BLUETOOTH_SD From 520105aaa7ecf7453e1ddceb1f97724ae15513dc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 29 Dec 2016 17:08:16 +0100 Subject: [PATCH 074/809] nrf52/boards: Tuning linker script for nrf52832 when using iot softdevice. Need more heap for LCD framebuffer. --- nrf5/boards/nrf52832_aa_s1xx.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/boards/nrf52832_aa_s1xx.ld b/nrf5/boards/nrf52832_aa_s1xx.ld index c2188afd47..2e2dc7cce6 100644 --- a/nrf5/boards/nrf52832_aa_s1xx.ld +++ b/nrf5/boards/nrf52832_aa_s1xx.ld @@ -12,8 +12,8 @@ MEMORY } /* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 16K; -_minimum_heap_size = 20K; +_minimum_stack_size = 8K; +_minimum_heap_size = 28K; /* top end of the stack */ @@ -22,6 +22,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20008800; /* tunable */ +_heap_end = 0x2000a800; /* tunable */ INCLUDE "boards/common.ld" From 38607ee4453f49d941a12b6b4ac2acd3816261c7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 31 Dec 2016 14:02:05 +0100 Subject: [PATCH 075/809] nrf5/modules: Adding licence text on seeedstudio tft shield python modules. --- nrf5/modules/seeed.py | 24 +++++++++++++++++++++++ nrf5/modules/seeedstudio_tft_shield_v2.py | 24 +++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/nrf5/modules/seeed.py b/nrf5/modules/seeed.py index 9e199c7084..7c73087ef9 100644 --- a/nrf5/modules/seeed.py +++ b/nrf5/modules/seeed.py @@ -1,3 +1,27 @@ +# This file is part of the Micro Python project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2016 Glenn Ruben Bakke +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + """ MicroPython Seeedstudio TFT Shield V2 driver, SPI interfaces, Analog GPIO Contains SD-card reader, LCD and Touch sensor diff --git a/nrf5/modules/seeedstudio_tft_shield_v2.py b/nrf5/modules/seeedstudio_tft_shield_v2.py index 81d17cbce8..95f66ed742 100644 --- a/nrf5/modules/seeedstudio_tft_shield_v2.py +++ b/nrf5/modules/seeedstudio_tft_shield_v2.py @@ -1,3 +1,27 @@ +# This file is part of the Micro Python project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2016 Glenn Ruben Bakke +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + """ MicroPython Seeedstudio TFT Shield V2 driver, SPI interfaces, Analog GPIO Contains SD-card reader, LCD and Touch sensor From c5d77f0e7ee14c051aa4504d61506e4f4ff4b151 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 31 Dec 2016 17:05:32 +0100 Subject: [PATCH 076/809] nrf5/hal: Moving enablement of PWM task from init to a start function. Also activating code in stop function to stop the PWM. --- nrf5/hal/hal_pwm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/nrf5/hal/hal_pwm.c b/nrf5/hal/hal_pwm.c index cf678c0ff2..6363b6a32c 100644 --- a/nrf5/hal/hal_pwm.c +++ b/nrf5/hal/hal_pwm.c @@ -72,15 +72,14 @@ void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init) p_instance->SEQ[0].REFRESH = 0; p_instance->SEQ[0].ENDDELAY = 0; - p_instance->TASKS_SEQSTART[0] = 1; } void hal_pwm_start(NRF_PWM_Type * p_instance) { - // p_instance->TASKS_SEQSTART[0] = 1; + p_instance->TASKS_SEQSTART[0] = 1; } void hal_pwm_stop(NRF_PWM_Type * p_instance) { - // p_instance->TASKS_STOP = 1; + p_instance->TASKS_STOP = 1; } void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq) { From 5e322ea0783cf3698f1c06d6534db7ba18c2e661 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 31 Dec 2016 17:06:07 +0100 Subject: [PATCH 077/809] nrf5/hal: Exposing two new PWM hal functions start() and stop(). --- nrf5/hal/hal_pwm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/hal/hal_pwm.h b/nrf5/hal/hal_pwm.h index eb69731149..6837ad4a54 100644 --- a/nrf5/hal/hal_pwm.h +++ b/nrf5/hal/hal_pwm.h @@ -90,4 +90,8 @@ void hal_pwm_period_set(NRF_PWM_Type * p_instance, uint16_t period); void hal_pwm_duty_set(NRF_PWM_Type * p_instance, uint8_t duty); +void hal_pwm_start(NRF_PWM_Type * p_instance); + +void hal_pwm_stop(NRF_PWM_Type * p_instance); + #endif // HAL_PWM_H__ From 3d120ac1036605a34a7b890ddfa1e499a83b214a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 31 Dec 2016 17:07:30 +0100 Subject: [PATCH 078/809] nrf5/pwm: Implementing start and stop call to hal on init and deinit as hal_init does not longer start the PWM automatically. --- nrf5/pwm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/nrf5/pwm.c b/nrf5/pwm.c index 7d77a00237..b38f3d612f 100644 --- a/nrf5/pwm.c +++ b/nrf5/pwm.c @@ -92,9 +92,13 @@ STATIC int pwm_find(mp_obj_t id) { } void pwm_init(PWM_HandleTypeDef *pwm) { + // start pwm + hal_pwm_start(pwm->instance); } void pwm_deinit(PWM_HandleTypeDef *pwm) { + // stop pwm + hal_pwm_stop(pwm->instance); } STATIC void pwm_print(const mp_print_t *print, PWM_HandleTypeDef *pwm, bool legacy) { @@ -284,6 +288,8 @@ STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args) { } STATIC void machine_hard_pwm_init(mp_obj_t self_in, mp_arg_val_t *args) { + machine_hard_pwm_obj_t *self = self_in; + pwm_init(self->pyb->pwm); } STATIC void machine_hard_pwm_deinit(mp_obj_t self_in) { From 1bc50dbeb5db0298dac904a6f1ef5b6bb6bc2b66 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 31 Dec 2016 17:20:54 +0100 Subject: [PATCH 079/809] nrf5/hal: Fixing some issues in PWM stop function. Doing a proper stop and disable the peripheral. --- nrf5/hal/hal_pwm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_pwm.c b/nrf5/hal/hal_pwm.c index 6363b6a32c..d1c947f796 100644 --- a/nrf5/hal/hal_pwm.c +++ b/nrf5/hal/hal_pwm.c @@ -79,7 +79,8 @@ void hal_pwm_start(NRF_PWM_Type * p_instance) { } void hal_pwm_stop(NRF_PWM_Type * p_instance) { - p_instance->TASKS_STOP = 1; + p_instance->TASKS_SEQSTART[0] = 0; + p_instance->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos); } void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq) { From bcb0c9d8cbc926f3f39916d839326d6fbf35ea76 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 31 Dec 2016 17:21:38 +0100 Subject: [PATCH 080/809] nrf5/modules: Updating PWM test python script to cope with new api. --- nrf5/modules/test.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/modules/test.py b/nrf5/modules/test.py index df0f520f4e..2ea1e7be7e 100644 --- a/nrf5/modules/test.py +++ b/nrf5/modules/test.py @@ -4,7 +4,12 @@ from machine import PWM, Pin def pulse(): for i in range(0, 101): p = PWM(0, Pin("A17", mode=Pin.OUT), freq=PWM.FREQ_16MHZ, duty=i, period=16000) + p.init() time.sleep_ms(10) + p.deinit() + for i in range(0, 101): p = PWM(0, Pin("A17", mode=Pin.OUT), freq=PWM.FREQ_16MHZ, duty=100-i, period=16000) + p.init() time.sleep_ms(10) + p.deinit() From 04751defa0276db209d22d6007e83802ce6bf72e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 2 Jan 2017 12:51:56 +0100 Subject: [PATCH 081/809] nrf5/spi: Removing automatic chip select (NSS) in hal_spi.c. Also removing configuration of this pin as it is confusing to pass it if not used. User of SPI has to set the NSS/CS itself. --- nrf5/hal/hal_spi.c | 11 ----------- nrf5/hal/hal_spi.h | 1 - nrf5/spi.c | 2 -- 3 files changed, 14 deletions(-) diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c index 39acea2437..652df524eb 100644 --- a/nrf5/hal/hal_spi.c +++ b/nrf5/hal/hal_spi.c @@ -32,8 +32,6 @@ #ifdef HAL_SPI_MODULE_ENABLED -static uint32_t m_ss_pin; - static const uint32_t hal_spi_frequency_lookup[] = { SPI_FREQUENCY_FREQUENCY_K125, // 125 kbps SPI_FREQUENCY_FREQUENCY_K250, // 250 kbps @@ -45,13 +43,9 @@ static const uint32_t hal_spi_frequency_lookup[] = { }; void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) { - hal_gpio_pin_set(p_spi_init->enable_pin); - m_ss_pin = p_spi_init->enable_pin; - hal_gpio_cfg_pin(p_spi_init->clk_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_spi_init->mosi_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_spi_init->miso_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_spi_init->enable_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); #if NRF51 p_instance->PSELSCK = p_spi_init->clk_pin; @@ -100,8 +94,6 @@ void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, con p_instance->EVENTS_READY = 0; - hal_gpio_pin_clear(m_ss_pin); - while (number_of_txd_bytes < transfer_size) { p_instance->TXD = (uint32_t)(tx_data[number_of_txd_bytes]); @@ -114,9 +106,6 @@ void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, con rx_data[number_of_txd_bytes] = (uint8_t)p_instance->RXD; number_of_txd_bytes++; }; - - hal_gpio_pin_set(m_ss_pin); - } #endif // HAL_SPI_MODULE_ENABLED diff --git a/nrf5/hal/hal_spi.h b/nrf5/hal/hal_spi.h index 9c30c0ed4f..cdcbd9248c 100644 --- a/nrf5/hal/hal_spi.h +++ b/nrf5/hal/hal_spi.h @@ -79,7 +79,6 @@ typedef struct { uint8_t mosi_pin; uint8_t miso_pin; uint8_t clk_pin; - uint8_t enable_pin; bool lsb_first; hal_spi_mode_t mode; uint32_t irq_priority; diff --git a/nrf5/spi.c b/nrf5/spi.c index 60e1113f93..3006b626b5 100644 --- a/nrf5/spi.c +++ b/nrf5/spi.c @@ -263,12 +263,10 @@ STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) { spi_init_conf.clk_pin = mp_obj_get_int(args[ARG_NEW_sck].u_obj); spi_init_conf.mosi_pin = mp_obj_get_int(args[ARG_NEW_mosi].u_obj); spi_init_conf.miso_pin = mp_obj_get_int(args[ARG_NEW_miso].u_obj); - spi_init_conf.enable_pin = MICROPY_HW_SPI0_NSS; } else { spi_init_conf.clk_pin = MICROPY_HW_SPI0_SCK; spi_init_conf.mosi_pin = MICROPY_HW_SPI0_MOSI; spi_init_conf.miso_pin = MICROPY_HW_SPI0_MISO; - spi_init_conf.enable_pin = MICROPY_HW_SPI0_NSS; } int baudrate = args[ARG_NEW_baudrate].u_int; From 994b1689e3787b89ee6db226b8a4bc9285992444 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 16:54:33 +0100 Subject: [PATCH 082/809] nrf5/uart: Making compile time exclusion of RTS/CTS if not defined to use flow control by board configuration. --- nrf5/uart.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nrf5/uart.c b/nrf5/uart.c index 1d6ca6fb01..cb05c2359f 100644 --- a/nrf5/uart.c +++ b/nrf5/uart.c @@ -204,8 +204,11 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, con hal_uart_init_t uart_init = { .rx_pin = MICROPY_HW_UART1_RX, .tx_pin = MICROPY_HW_UART1_TX, +#if MICROPY_HW_UART1_HWFC .rts_pin = MICROPY_HW_UART1_RTS, .cts_pin = MICROPY_HW_UART1_CTS, +#endif + #if MICROPY_HW_UART1_HWFC .flow_control = true, #else From 4b6a12a251e19b675ce20ff54cec47e6bd587512 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 16:57:05 +0100 Subject: [PATCH 083/809] nrf5/boards: Updating pca10028 board config to not define RTS/CTS pins when HWFC is set to 0. --- nrf5/boards/pca10028/mpconfigboard.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index a40e30c906..401fb61b79 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -60,8 +60,6 @@ // UART config #define MICROPY_HW_UART1_RX (11) #define MICROPY_HW_UART1_TX (9) -#define MICROPY_HW_UART1_CTS (10) -#define MICROPY_HW_UART1_RTS (8) #define MICROPY_HW_UART1_HWFC (0) // SPI0 config From 31569dc9527d864461437b89821ed9dc6cb4e7d9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 17:00:06 +0100 Subject: [PATCH 084/809] nrf5: Makefile option to set FLASHER when doing flash target. If defined in board .mk file, this will be used, else nrfjprog will be used by default (segger). This opens up for using pyocd flashtool and still run 'make flash'. --- nrf5/Makefile | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index c5dc610d9b..2b961b4b31 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -175,6 +175,10 @@ $(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os all: $(BUILD)/firmware.elf binary hex +FLASHER ?= + +ifeq ($(FLASHER),) + flash: $(BUILD)/firmware.elf nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT) nrfjprog --pinreset -f $(MCU_VARIANT) @@ -185,6 +189,13 @@ sd: nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT) nrfjprog --pinreset -f $(MCU_VARIANT) +else ifeq ($(FLASHER), pyocd) + +flash: $(BUILD)/firmware.elf + pyocd-flashtool -t $(MCU_VARIANT) $(BUILD)/firmware.hex + +endif + $(BUILD)/firmware.elf: $(OBJ) $(ECHO) "LINK $@" $(Q)$(CC) $(LDFLAGS) -o $@ $(OBJ) $(LIBS) From 11fc46ca6f418b7a3a18d424d69835ffc78fe8a6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 17:02:49 +0100 Subject: [PATCH 085/809] nrf5/boards: Adding initial microbit build files and board configurations. --- nrf5/boards/microbit/mpconfigboard.h | 72 ++++++++++++++++++++++ nrf5/boards/microbit/mpconfigboard.mk | 5 ++ nrf5/boards/microbit/mpconfigboard_s110.mk | 4 ++ nrf5/boards/microbit/nrf51_hal_conf.h | 10 +++ nrf5/boards/microbit/pins.csv | 32 ++++++++++ 5 files changed, 123 insertions(+) create mode 100644 nrf5/boards/microbit/mpconfigboard.h create mode 100644 nrf5/boards/microbit/mpconfigboard.mk create mode 100644 nrf5/boards/microbit/mpconfigboard_s110.mk create mode 100644 nrf5/boards/microbit/nrf51_hal_conf.h create mode 100644 nrf5/boards/microbit/pins.csv diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h new file mode 100644 index 0000000000..83d7c25f54 --- /dev/null +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -0,0 +1,72 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define PCA10028 + +#define MICROPY_HW_BOARD_NAME "micro:bit" +#define MICROPY_HW_MCU_NAME "NRF51822" +#define MICROPY_PY_SYS_PLATFORM "nrf51" + +#define MICROPY_PY_MACHINE_PWM (0) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) + +#define MICROPY_PY_USOCKET (0) +#define MICROPY_PY_NETWORK (0) + +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_PULLUP (1) + +#define MICROPY_HW_LED1 (21) // LED1 +#define MICROPY_HW_LED2 (22) // LED2 +#define MICROPY_HW_LED3 (23) // LED3 +#define MICROPY_HW_LED4 (24) // LED4 + +// UART config +#define MICROPY_HW_UART1_RX (25) +#define MICROPY_HW_UART1_TX (24) +#define MICROPY_HW_UART1_HWFC (0) + +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (1) // A3 +#define MICROPY_HW_SPI0_MOSI (2) // A2 +#define MICROPY_HW_SPI0_MISO (3) // A1 +#define MICROPY_HW_SPI0_NSS (4) // A4 + +#define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/microbit/mpconfigboard.mk b/nrf5/boards/microbit/mpconfigboard.mk new file mode 100644 index 0000000000..c8a0f0caea --- /dev/null +++ b/nrf5/boards/microbit/mpconfigboard.mk @@ -0,0 +1,5 @@ +MCU_SERIES = m0 +MCU_VARIANT = nrf51 +LD_FILE = boards/nrf51822_aa.ld +FLASHER = pyocd + diff --git a/nrf5/boards/microbit/mpconfigboard_s110.mk b/nrf5/boards/microbit/mpconfigboard_s110.mk new file mode 100644 index 0000000000..54766bd429 --- /dev/null +++ b/nrf5/boards/microbit/mpconfigboard_s110.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m0 +MCU_VARIANT = nrf51 +LD_FILE = boards/nrf51822_ac_s110.ld + diff --git a/nrf5/boards/microbit/nrf51_hal_conf.h b/nrf5/boards/microbit/nrf51_hal_conf.h new file mode 100644 index 0000000000..4bd11e1dd5 --- /dev/null +++ b/nrf5/boards/microbit/nrf51_hal_conf.h @@ -0,0 +1,10 @@ +#ifndef NRF51_HAL_CONF_H__ +#define NRF51_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED + +#endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/microbit/pins.csv b/nrf5/boards/microbit/pins.csv new file mode 100644 index 0000000000..2b16969869 --- /dev/null +++ b/nrf5/boards/microbit/pins.csv @@ -0,0 +1,32 @@ +PA0,PA0 +PA1,PA1 +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA5,PA5 +PA6,PA6 +PA7,PA7 +UART_RTS,PA8 +UART_TX,PA9 +UART_CTS,PA10 +UART_RX,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 \ No newline at end of file From 70198b07a57dffc9168ea98d1e5d55f1d19b444c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 21:12:39 +0100 Subject: [PATCH 086/809] nrf5/lcd: Updating framebuffer with double buffer for epaper displays. Moving statics into instance struct. Adding new function to refresh using old buffer, such that epaper can get a cleaner image after update. --- nrf5/lcd_mono_fb.c | 120 +++++++++++++++++++++++++++++++-------------- 1 file changed, 84 insertions(+), 36 deletions(-) diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index 31b9aeb0d1..ac6c437f75 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -26,6 +26,7 @@ #include #include +#include #include "py/nlr.h" #include "py/obj.h" @@ -42,18 +43,18 @@ typedef struct { mp_obj_base_t base; fb_byte_t * fb_bytes; + fb_byte_t * fb_old; fb_byte_t * fb_dirty; - uint16_t height; - uint16_t width; + uint16_t height; + uint16_t width; mp_uint_t bytes_stride; mp_uint_t dirty_stride; - mp_obj_t line_update_cb; + mp_obj_t line_update_cb; + mp_uint_t bg_color; + mp_uint_t fg_color; + mp_uint_t font_size; } mp_obj_framebuf_t; -static uint8_t m_bg_color; -static uint8_t m_fg_color; -static uint8_t m_font_size; - STATIC void lcd_enable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { uint16_t column = (x / 8); uint16_t line = y; @@ -73,35 +74,35 @@ STATIC void lcd_disable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uin } STATIC void lcd_init(mp_obj_framebuf_t * p_framebuffer) { - m_fg_color = LCD_BLACK; - m_bg_color = LCD_WHITE; + p_framebuffer->fg_color = LCD_BLACK; + p_framebuffer->bg_color = LCD_WHITE; memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); memset(p_framebuffer->fb_dirty, 0x00, p_framebuffer->dirty_stride); } STATIC void lcd_fg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { - m_fg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; + p_framebuffer->fg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; } #if 0 STATIC uint16_t lcd_fg_color_get(mp_obj_framebuf_t * p_framebuffer) { - return m_fg_color; + return p_framebuffer->fg_color; } #endif STATIC void lcd_bg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { - m_bg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; + p_framebuffer->bg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; } #if 0 STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * p_framebuffer) { - return m_bg_color; + return p_framebuffer->bg_color; } #endif STATIC void lcd_clear_screen(mp_obj_framebuf_t * p_framebuffer) { - if (m_bg_color == LCD_BLACK) { + if (p_framebuffer->bg_color == LCD_BLACK) { memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); } else { memset(p_framebuffer->fb_bytes, 0xFF, p_framebuffer->bytes_stride * p_framebuffer->height); @@ -113,34 +114,34 @@ STATIC void lcd_print_char(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16 uint16_t col = x; for (uint8_t i = 0; i < 8; i++) { - uint16_t current_col = col + (i * m_font_size); + uint16_t current_col = col + (i * p_framebuffer->font_size); for (uint8_t y_pos = 0; y_pos < 8; y_pos++) { if ((((uint8_t)font_petme128_8x8[((ch - 32) * 8) + i]) >> y_pos) & 0x01) { - for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { - for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { - if (m_fg_color < LCD_WHITE) { + for (uint8_t s_w = 0; s_w < p_framebuffer->font_size; s_w++) { + for (uint8_t s_h = 0; s_h < p_framebuffer->font_size; s_h++) { + if (p_framebuffer->fg_color < LCD_WHITE) { lcd_disable_pixel(p_framebuffer, current_col + s_w, - y + (y_pos * m_font_size) + s_h); + y + (y_pos * p_framebuffer->font_size) + s_h); } else { lcd_enable_pixel(p_framebuffer, current_col + s_w, - y + (y_pos * m_font_size) + s_h); + y + (y_pos * p_framebuffer->font_size) + s_h); } } } } else { - for (uint8_t s_w = 0; s_w < m_font_size; s_w++) { - for (uint8_t s_h = 0; s_h < m_font_size; s_h++) { - if (m_bg_color < LCD_WHITE) { + for (uint8_t s_w = 0; s_w < p_framebuffer->font_size; s_w++) { + for (uint8_t s_h = 0; s_h < p_framebuffer->font_size; s_h++) { + if (p_framebuffer->bg_color < LCD_WHITE) { lcd_disable_pixel(p_framebuffer, current_col + s_w, - y + (y_pos * m_font_size) + s_h); + y + (y_pos * p_framebuffer->font_size) + s_h); } else { lcd_enable_pixel(p_framebuffer, current_col + s_w, - y + (y_pos * m_font_size) + s_h); + y + (y_pos * p_framebuffer->font_size) + s_h); } } } @@ -162,7 +163,7 @@ STATIC uint8_t lcd_font_size_get(mp_obj_framebuf_t * p_framebuffer) { STATIC void lcd_print_string(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, const char * p_str) { uint16_t str_len = strlen(p_str); for (uint16_t i = 0; i < str_len; i++) { - lcd_print_char(p_framebuffer, x + (i * 8 * m_font_size), y, p_str[i]); + lcd_print_char(p_framebuffer, x + (i * 8 * p_framebuffer->font_size), y, p_str[i]); } } @@ -174,22 +175,44 @@ STATIC void lcd_pixel_draw(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16 } } -STATIC void lcd_update(mp_obj_framebuf_t * p_framebuffer) { +STATIC void lcd_update(mp_obj_framebuf_t * p_framebuffer, bool refresh) { for (uint16_t i = 0; i < p_framebuffer->dirty_stride; i++) { - if (p_framebuffer->fb_dirty[i].byte != 0) { + if (p_framebuffer->fb_dirty[i].byte != 0 || refresh) { for (uint16_t b = 0; b < 8; b++) { - if (((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) { + if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) || refresh) { uint16_t line_num = (i * 8) + b; - mp_obj_t args[3]; + mp_obj_t args[4]; + mp_uint_t num_of_args = 3; args[0] = p_framebuffer; args[1] = MP_OBJ_NEW_SMALL_INT(line_num); - args[2] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, - &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); - mp_call_function_n_kw(p_framebuffer->line_update_cb, 3, 0, args); + + if (refresh == false) { + args[2] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, + &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); + } else { + args[2] = mp_const_none; + } + + if (p_framebuffer->fb_old != NULL) { + args[3] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, + &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); + num_of_args = 4; + } + + mp_call_function_n_kw(p_framebuffer->line_update_cb, num_of_args, 0, args); + + // update old buffer + if (p_framebuffer->fb_old != NULL) { + memcpy(&p_framebuffer->fb_old[line_num * p_framebuffer->bytes_stride], + &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride], + p_framebuffer->dirty_stride); + } } } - p_framebuffer->fb_dirty[i].byte = 0x00; + if (refresh == false) { + p_framebuffer->fb_dirty[i].byte = 0x00; + } } } } @@ -211,7 +234,16 @@ STATIC mp_obj_t lcd_mono_fb_make_new(const mp_obj_type_t *type, size_t n_args, s o->fb_bytes = m_new(fb_byte_t, (o->bytes_stride) * o->height); o->fb_dirty = m_new(fb_byte_t, o->dirty_stride); - m_font_size = 1; + // default to not use double buffer + o->fb_old = NULL; + + o->font_size = 1; + + if (n_args >= 4) { + if (mp_obj_is_true(args[3])) { + o->fb_old = m_new(fb_byte_t, (o->bytes_stride) * o->height); + } + } lcd_init(o); @@ -270,18 +302,33 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_mono_fb_text_obj, 4, 5, lcd_mono_ STATIC mp_obj_t lcd_mono_fb_show(mp_obj_t self_in) { mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); - lcd_update(self); + lcd_update(self, false); return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_show_obj, lcd_mono_fb_show); +STATIC mp_obj_t lcd_mono_fb_refresh(mp_obj_t self_in) { + mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + + lcd_update(self, true); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_refresh_obj, lcd_mono_fb_refresh); + + STATIC mp_obj_t lcd_mono_fb_del(mp_obj_t self_in) { mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); m_free(self->fb_bytes); m_free(self->fb_dirty); + if (self->fb_old != NULL) { + // free double buffer if used + m_free(self->fb_old); + } + return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_del_obj, lcd_mono_fb_del); @@ -293,6 +340,7 @@ STATIC const mp_rom_map_elem_t lcd_mono_fb_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_scroll), MP_ROM_PTR(&lcd_mono_fb_scroll_obj) }, { MP_ROM_QSTR(MP_QSTR_text), MP_ROM_PTR(&lcd_mono_fb_text_obj) }, { MP_ROM_QSTR(MP_QSTR_show), MP_ROM_PTR(&lcd_mono_fb_show_obj) }, + { MP_ROM_QSTR(MP_QSTR_refresh), MP_ROM_PTR(&lcd_mono_fb_refresh_obj) }, }; STATIC MP_DEFINE_CONST_DICT(lcd_mono_fb_locals_dict, lcd_mono_fb_locals_dict_table); From 7b6bdc4c2b0b260a05c4f2dfcf67fe19eccd51a8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 21:15:53 +0100 Subject: [PATCH 087/809] nrf5: Adding sleep_us to modutime.c and exposing mp_hal_delay_us in hal/hal_time.h --- nrf5/hal/hal_time.h | 2 ++ nrf5/modutime.c | 1 + 2 files changed, 3 insertions(+) diff --git a/nrf5/hal/hal_time.h b/nrf5/hal/hal_time.h index 1cef8b9521..79b643acc7 100644 --- a/nrf5/hal/hal_time.h +++ b/nrf5/hal/hal_time.h @@ -29,4 +29,6 @@ void mp_hal_delay_ms(mp_uint_t ms); +void mp_hal_delay_us(mp_uint_t us); + #endif // HAL_TIME_H__ diff --git a/nrf5/modutime.c b/nrf5/modutime.c index a0e4f904c4..bb3f6a401a 100644 --- a/nrf5/modutime.c +++ b/nrf5/modutime.c @@ -42,6 +42,7 @@ STATIC const mp_rom_map_elem_t time_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_utime) }, { MP_ROM_QSTR(MP_QSTR_sleep_ms), MP_ROM_PTR(&mp_utime_sleep_ms_obj) }, + { MP_ROM_QSTR(MP_QSTR_sleep_us), MP_ROM_PTR(&mp_utime_sleep_us_obj) }, }; STATIC MP_DEFINE_CONST_DICT(time_module_globals, time_module_globals_table); From c34127e754d4cf71e04e09cc0290b6ef28f4ded5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 21:17:37 +0100 Subject: [PATCH 088/809] nrf5/hal: Fixing bug in mp_hal_pin_read in mphalport.h which tried to read an OUT register. Corrected to read the IN register. --- nrf5/mphalport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/mphalport.h b/nrf5/mphalport.h index 23e39a0997..ce8f991e5c 100644 --- a/nrf5/mphalport.h +++ b/nrf5/mphalport.h @@ -125,7 +125,7 @@ void mp_hal_stdout_tx_str(const char *str); #define mp_hal_pin_obj_t const pin_obj_t* #define mp_hal_pin_high(p) (((NRF_GPIO_Type *)((p)->gpio))->OUTSET = (p)->pin_mask) #define mp_hal_pin_low(p) (((NRF_GPIO_Type *)((p)->gpio))->OUTCLR = (p)->pin_mask) -#define mp_hal_pin_read(p) (((NRF_GPIO_Type *)((p)->gpio))->OUT >> ((p)->pin) & 1) +#define mp_hal_pin_read(p) (((NRF_GPIO_Type *)((p)->gpio))->IN >> ((p)->pin) & 1) #define mp_hal_pin_write(p, v) do { if (v) { mp_hal_pin_high(p); } else { mp_hal_pin_low(p); } } while (0) // TODO: empty implementation for now. Used by machine_spi.c:69 From ef234503ef10afa0dfda99692cefe9dd0fe5c11a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 21:25:06 +0100 Subject: [PATCH 089/809] nrf5/modules: Adding python epaper display driver. Currently colors have been reversed. --- nrf5/modules/epaper.py | 451 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 451 insertions(+) create mode 100644 nrf5/modules/epaper.py diff --git a/nrf5/modules/epaper.py b/nrf5/modules/epaper.py new file mode 100644 index 0000000000..13c0d754a9 --- /dev/null +++ b/nrf5/modules/epaper.py @@ -0,0 +1,451 @@ +# This file is part of the Micro Python project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2017 Glenn Ruben Bakke +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +""" +E-paper SLD00200. + +Pin layout on pca10040 (nrf52): + +EPAPER_PANEL_ON 13 (Arduino D2) +EPAPER_BORDER 14 (Arduino D3) +EPAPER_PWM 16 (Arduino D5) +EPAPER_RESET 17 (Arduino D6) +EPAPER_BUSY 18 (Arduino D7) +EPAPER_DISCHARGE 19 (Arduino D8) +EPAPER_TEMP_SENSOR 03 (Arduino A0) +EPAPER_CS 22 (Arduino D10) +EPAPER_DIN 23 (Arduino D11) +EPAPER_DOUT 24 (Arduino D12) +EPAPER_CLK 25 (Arduino D13) + +Example usage on pca10040: + + from epaper import Epaper + + epd = Epaper() + epd.fill(0) + epd.text("Hello World!", 50, 50) + epd.show() + + epd.refresh() + epd.refresh() +""" + +import os +import time +import lcd_mono_fb + +from machine import SPI, Pin, PWM + +EPD_STATE_COMP = const(0x1) +EPD_STATE_WHITE = const(0x2) +EPD_STATE_INV = const(0x3) +EPD_STATE_NORM = const(0x4) + +class Epaper: + def __init__(self, width=264, height=176, vertical=False): + + self.width = width + self.height = height + self.vertical = vertical + self.framebuf = lcd_mono_fb.MonoFB(self.line_update, self.width, self.height, True) + + self.reset = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) + self.panel_on = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) + self.discharge = Pin("A19", mode=Pin.OUT, pull=Pin.PULL_UP) + self.border = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) + self.busy = Pin("A18", mode=Pin.IN, pull=Pin.PULL_DISABLED) + self.cs = Pin("A22", mode=Pin.OUT, pull=Pin.PULL_UP) + + self.reset.low() + self.panel_on.low() + self.discharge.low() + self.border.low() + + self.pwm = PWM(0, Pin("A16", mode=Pin.OUT), freq=PWM.FREQ_250KHZ, duty=50, period=2) + + # Min baudrate 4M, max 12M + self.spi = SPI(0, baudrate=80000000) + # self.spi.init(baudrate=8000000, phase=0, polarity=0) + + def line_update(self, o, line, new_bytes, old_bytes): + if new_bytes: + self._update_line(line, old_bytes, EPD_STATE_COMP) + self._update_line(line, old_bytes, EPD_STATE_WHITE) + self._update_line(line, new_bytes, EPD_STATE_INV) + self._update_line(line, new_bytes, EPD_STATE_NORM) + else: + self._update_line(line, old_bytes, EPD_STATE_NORM) + + def clear(self): + line_count = self.height; + for i in range(0, line_count): + self._update_line(i, None, EPD_STATE_COMP, 0xFF) + + time.sleep_ms(500) + + for i in range(0, line_count): + self._update_line(i, None, EPD_STATE_WHITE, 0xAA) + + time.sleep_ms(500) + + for i in range(0, line_count): + self._update_line(i, None, EPD_STATE_INV, 0xFF) + + time.sleep_ms(500) + + for i in range(0, line_count): + self._update_line(i, None, EPD_STATE_NORM, 0xAA) + + time.sleep_ms(500) + + def init_display(self): + + self.pwm.init() # start the pwm + + print("sleep") + time.sleep_ms(5) + print("wakeup") + self.panel_on.high() + time.sleep_ms(10) + + self.reset.high() + self.border.high() + self.cs.high() + + time.sleep_ms(5) + + self.reset.low() + + time.sleep_ms(5) + + self.reset.high() + + time.sleep_ms(5) + print("Wait for busy") + self.wait_for_busy_release() + + time.sleep_us(10) + # channel select + self.write_data(bytearray([0x70, 0x01])) + time.sleep_us(10) + + # CS + self.write_data(bytearray([0x72, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xfe, 0x00, 0x00])) + + # DC/DC frequency + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x06])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0xff])) + + # high power mode osc + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x07])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x9d])) + + # disable ADC + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x08])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x00])) + + # Vcom level + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x09])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0xd0, 0x00])) + + # gate and source voltage levels + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x04])) + + # GS + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x00])) + + time.sleep_ms(5) + + # driver latch on + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x03])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x01])) + + # driver latch off + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x03])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x00])) + + time.sleep_ms(5) + + # charge pump positive voltage on + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x05])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x01])) + + # final delay before PWM off + time.sleep_us(30) + + # stop PWM + self.pwm.deinit() + + # charge pump negative voltage on + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x05])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x03])) + + time.sleep_us(30) + + # Vcom driver on + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x05])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x0f])) + + time.sleep_ms(30); + + # output enable to disable + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x02])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x24])) + + def wait_for_busy_release(self): + # wait for COG to become ready + while (self.busy.value() == 1): + pass + + def _update_line(self, line, data, state, fixed=None): + time.sleep_us(10) + + self.write_data(bytearray([0x70, 0x04])) + time.sleep_us(10) + + # gate source + self.write_data(bytearray([0x72, 0x00])) + time.sleep_us(10) + + self.write_data(bytearray([0x70, 0x0a])) + time.sleep_us(10) + + self.cs.low() + + self.write_data_wait(bytearray([0x72])) + + bytes_per_line = self.width // 8; + + # even pixels + if data: + for i in range(bytes_per_line - 1, -1, -1): + + pixels = data[i] & 0xaa; + + if state == EPD_STATE_COMP: + # B -> W, W -> B (current image) + pixels = 0xaa | ((pixels ^ 0xaa) >> 1) + + elif state == EPD_STATE_WHITE: + # B -> N, W -> W (current image) + pixels = 0x55 + ((pixels ^ 0xaa) >> 1) + + elif state == EPD_STATE_INV: + # B -> N, W -> B (new image) + pixels = 0x55 | (pixels ^ 0xaa) + + elif state == EPD_STATE_NORM: + # B -> B, W -> W (new image) + pixels = 0xaa | (pixels >> 1) + + self.write_data_wait(bytearray([pixels])); + else: + self.write_data_wait(bytearray([fixed] * bytes_per_line)); + + bytes_per_scan = 176 // 4; + # scan line + for i in range(0, bytes_per_scan): + if (line // 4 == i): + self.write_data_wait(bytearray([0xc0 >> (2 * (line & 0x03))])) + else: + self.write_data_wait(bytearray([0x00])) + + # odd pixels + if data: + for i in range (0, bytes_per_line): + pixels = data[i] & 0x55 + + if state == EPD_STATE_COMP: + pixels = 0xaa | (pixels ^ 0x55) + + elif state == EPD_STATE_WHITE: + pixels = 0x55 + (pixels ^ 0x55) + + elif state == EPD_STATE_INV: + pixels = 0x55 | ((pixels ^ 0x55) << 1) + + elif state == EPD_STATE_NORM: + pixels = 0xaa | pixels + + p1 = (pixels >> 6) & 0x03; + p2 = (pixels >> 4) & 0x03; + p3 = (pixels >> 2) & 0x03; + p4 = (pixels >> 0) & 0x03; + + pixels = (p1 << 0) | (p2 << 2) | (p3 << 4) | (p4 << 6); + + self.write_data_wait(bytearray([pixels])) + else: + self.write_data_wait(bytearray([fixed] * bytes_per_line)) + + # Complete line + self.write_data_wait(bytearray([0x00])) + + self.cs.high() + + time.sleep_us(10) + + + self.write_data(bytearray([0x70, 0x02])) + time.sleep_us(10) + + self.write_data(bytearray([0x72, 0x2f])) + + def deinit_display(self): + # all display sizes + self._update_line(0x7fff, None, EPD_STATE_NORM, 0x55) + time.sleep_ms(25) + self.border.low() + time.sleep_ms(250) + self.border.high() + + # latch reset turn on + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x03])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x01])) + + # output enable off + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x02])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x05])) + + # Vcom power off + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x05])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x0e])) + + # power off negative charge pump + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x05])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x02])) + + # discharge + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x04])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x0c])) + time.sleep_us(120) + + # all charge pumps off + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x05])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x00])) + + # turn of osc + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x07])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x0d])) + + # discharge internal - 1 + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x04])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x50])) + time.sleep_us(40) + + # discharge internal - 2 + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x04])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0xA0])) + time.sleep_us(40) + + # discharge internal - 3 + time.sleep_us(10) + self.write_data(bytearray([0x70, 0x04])) + time.sleep_us(10) + self.write_data(bytearray([0x72, 0x00])) + + # turn of power and all signals + time.sleep_ms(10) + self.reset.low() + self.panel_on.low() + self.border.low() + + # discharge pulse + self.discharge.high() + time.sleep_us(250) + self.discharge.low() + + self.cs.high() + + def show(self): + self.init_display() + self.framebuf.show() + self.deinit_display() + + def refresh(self): + self.init_display() + self.framebuf.refresh() + self.deinit_display() + + def fill(self, col): + self.framebuf.fill(col) + + def pixel(self, x, y, col): + self.framebuf.pixel(x, y, col) + + def scroll(self, dx, dy): + self.framebuf.scroll(dx, dy) + + def text(self, string, x, y, col=1): + self.framebuf.text(string, x, y, col) + + def write_data_wait(self, buf): + self.spi.write(buf) + self.wait_for_busy_release() + + def write_data(self, buf): + self.cs.low() + self.spi.write(buf) + self.cs.high() From 5265d70329e26215315aabcff1832faf6cf862f4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 21:32:17 +0100 Subject: [PATCH 090/809] nrf5/modules: Updating to correct name of display in epaper driver. --- nrf5/modules/epaper.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/epaper.py b/nrf5/modules/epaper.py index 13c0d754a9..ff08b1303e 100644 --- a/nrf5/modules/epaper.py +++ b/nrf5/modules/epaper.py @@ -23,7 +23,7 @@ # THE SOFTWARE. """ -E-paper SLD00200. +E-paper EM027AS011. Pin layout on pca10040 (nrf52): From bae425ca05d861f5ae078530b3c02be978d0e60d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 3 Jan 2017 22:16:00 +0100 Subject: [PATCH 091/809] nrf5/drivers: Adding template for c-implementation of lcd, epaper and oled drivers as a display module. --- .../display/epaper/moddisplay_epaper.c | 41 +++++++++++++++++ .../display/epaper/moddisplay_epaper.h | 32 +++++++++++++ nrf5/drivers/display/lcd/moddisplay_lcd.c | 43 +++++++++++++++++ nrf5/drivers/display/lcd/moddisplay_lcd.h | 32 +++++++++++++ nrf5/drivers/display/moddisplay.c | 46 +++++++++++++++++++ nrf5/drivers/display/moddisplay.h | 32 +++++++++++++ nrf5/drivers/display/oled/moddisplay_oled.c | 42 +++++++++++++++++ nrf5/drivers/display/oled/moddisplay_oled.h | 32 +++++++++++++ 8 files changed, 300 insertions(+) create mode 100644 nrf5/drivers/display/epaper/moddisplay_epaper.c create mode 100644 nrf5/drivers/display/epaper/moddisplay_epaper.h create mode 100644 nrf5/drivers/display/lcd/moddisplay_lcd.c create mode 100644 nrf5/drivers/display/lcd/moddisplay_lcd.h create mode 100644 nrf5/drivers/display/moddisplay.c create mode 100644 nrf5/drivers/display/moddisplay.h create mode 100644 nrf5/drivers/display/oled/moddisplay_oled.c create mode 100644 nrf5/drivers/display/oled/moddisplay_oled.h diff --git a/nrf5/drivers/display/epaper/moddisplay_epaper.c b/nrf5/drivers/display/epaper/moddisplay_epaper.c new file mode 100644 index 0000000000..7a08e19a1f --- /dev/null +++ b/nrf5/drivers/display/epaper/moddisplay_epaper.c @@ -0,0 +1,41 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" + +STATIC const mp_map_elem_t epaper_module_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_epaper) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_sld00200p), (mp_obj_t)&epaper_sld00200p_type }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(epaper_module_globals, epaper_module_globals_table); + +const mp_obj_module_t display_epaper_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&epaper_module_globals, +}; diff --git a/nrf5/drivers/display/epaper/moddisplay_epaper.h b/nrf5/drivers/display/epaper/moddisplay_epaper.h new file mode 100644 index 0000000000..5a90a001fa --- /dev/null +++ b/nrf5/drivers/display/epaper/moddisplay_epaper.h @@ -0,0 +1,32 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MODDISPLAY_EPAPER_H__ +#define MODDISPLAY_EPAPER_H__ + +extern const mp_obj_module_t display_epaper_module; + +#endif // MODDISPLAY_EPAPER_H__ diff --git a/nrf5/drivers/display/lcd/moddisplay_lcd.c b/nrf5/drivers/display/lcd/moddisplay_lcd.c new file mode 100644 index 0000000000..a456c326d4 --- /dev/null +++ b/nrf5/drivers/display/lcd/moddisplay_lcd.c @@ -0,0 +1,43 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" + +STATIC const mp_map_elem_t lcd_module_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_lcd) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_sld10261p), (mp_obj_t)&lcd_sld10261p_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ssd1289), (mp_obj_t)&lcd_ssd1289_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ls027b7dh01), (mp_obj_t)&lcd_ls027b7dh01_type }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(lcd_module_globals, lcd_module_globals_table); + +const mp_obj_module_t display_lcd_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&lcd_module_globals, +}; diff --git a/nrf5/drivers/display/lcd/moddisplay_lcd.h b/nrf5/drivers/display/lcd/moddisplay_lcd.h new file mode 100644 index 0000000000..8646316f53 --- /dev/null +++ b/nrf5/drivers/display/lcd/moddisplay_lcd.h @@ -0,0 +1,32 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MODDISPLAY_LCD_H__ +#define MODDISPLAY_LCD_H__ + +extern const mp_obj_module_t display_lcd_module; + +#endif // MODDISPLAY_LCD_H__ diff --git a/nrf5/drivers/display/moddisplay.c b/nrf5/drivers/display/moddisplay.c new file mode 100644 index 0000000000..d4a12126dd --- /dev/null +++ b/nrf5/drivers/display/moddisplay.c @@ -0,0 +1,46 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" + +#include "epaper/moddisplay_epaper.h" +#include "lcd/moddisplay_lcd.h" +#include "oled/moddisplay_oled.h" + +STATIC const mp_map_elem_t display_module_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_display) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_epaper), (mp_obj_t)&display_epaper_module }, + { MP_OBJ_NEW_QSTR(MP_QSTR_lcd), (mp_obj_t)&display_lcd_module}, + { MP_OBJ_NEW_QSTR(MP_QSTR_oled), (mp_obj_t)&display_oled_module }, +}; + + +STATIC MP_DEFINE_CONST_DICT(display_module_globals, display_module_globals_table); + +const mp_obj_module_t display_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&display_module_globals, +}; diff --git a/nrf5/drivers/display/moddisplay.h b/nrf5/drivers/display/moddisplay.h new file mode 100644 index 0000000000..f32833a65d --- /dev/null +++ b/nrf5/drivers/display/moddisplay.h @@ -0,0 +1,32 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MODDISPLAY_H__ +#define MODDISPLAY_H__ + +extern const mp_obj_module_t display_module; + +#endif // MODDISPLAY_H__ diff --git a/nrf5/drivers/display/oled/moddisplay_oled.c b/nrf5/drivers/display/oled/moddisplay_oled.c new file mode 100644 index 0000000000..e0b4237241 --- /dev/null +++ b/nrf5/drivers/display/oled/moddisplay_oled.c @@ -0,0 +1,42 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" + +STATIC const mp_map_elem_t oled_module_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_oled) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_ssd1305), (mp_obj_t)&oled_ssd1305_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ssd1306), (mp_obj_t)&oled_ssd1306_type }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(oled_module_globals, oled_module_globals_table); + +const mp_obj_module_t display_oled_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&oled_module_globals, +}; diff --git a/nrf5/drivers/display/oled/moddisplay_oled.h b/nrf5/drivers/display/oled/moddisplay_oled.h new file mode 100644 index 0000000000..9a37e4b715 --- /dev/null +++ b/nrf5/drivers/display/oled/moddisplay_oled.h @@ -0,0 +1,32 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MODDISPLAY_OLED_H__ +#define MODDISPLAY_OLED_H__ + +extern const mp_obj_module_t display_oled_module; + +#endif // MODDISPLAY_OLED_H__ From f97eded57e36abb7174a592f5bd7358b421d1b3c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 17:13:19 +0100 Subject: [PATCH 092/809] nrf5/drivers: Adding driver files to makefile. Implicitly adding display module. --- nrf5/Makefile | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 2b961b4b31..e834caf25d 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -60,7 +60,7 @@ INC += -I./device INC += -I./device/$(MCU_VARIANT) INC += -I./hal INC += -I./hal/$(MCU_VARIANT) -INC += -I./drivers +INC += -I./drivers/display INC += -I../lib/mp-readline NRF_DEFINES = -D$(MCU_VARIANT_UPPER) @@ -148,6 +148,15 @@ SRC_C += \ rtc.c \ lcd_mono_fb.c \ +DRIVERS_SRC_C += $(addprefix drivers/,\ + display/moddisplay.c \ + display/epaper/moddisplay_epaper.c \ + display/lcd/moddisplay_lcd.c \ + display/oled/moddisplay_oled.c \ + display/epaper/epaper_sld00200p.c \ + display/epaper/epaper_sld00200p_driver.c \ + ) + #ifeq ($(SD), ) SRC_C += \ @@ -164,6 +173,7 @@ FROZEN_MPY_MPY_FILES := $(addprefix $(BUILD)/,$(FROZEN_MPY_PY_FILES:.py=.mpy)) OBJ += $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_HAL:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(DRIVERS_SRC_C:.c=.o)) OBJ += $(BUILD)/pins_gen.o OBJ += $(BUILD)/$(BUILD)/frozen_mpy.o @@ -202,7 +212,7 @@ $(BUILD)/firmware.elf: $(OBJ) $(Q)$(SIZE) $@ # List of sources for qstr extraction -SRC_QSTR += $(SRC_C) $(SRC_MOD) $(SRC_LIB) +SRC_QSTR += $(SRC_C) $(SRC_MOD) $(SRC_LIB) $(DRIVERS_SRC_C) # Append any auto-generated sources that are needed by sources listed in # SRC_QSTR From bace74fba4b8427fddc30a85e36883e5efa8c242 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 17:14:44 +0100 Subject: [PATCH 093/809] nrf5: Adding display module to port builtins. --- nrf5/mpconfigport.h | 77 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 0af3531a43..569ab430f4 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -129,7 +129,73 @@ #define MICROPY_PY_NETWORK (1) #endif -#define MICROPY_PY_LCD_MONO_FB (0) + + +#ifndef MICROPY_PY_DISPLAY + +#define MICROPY_PY_DISPLAY (0) +#define MICROPY_PY_DISPLAY_EPAPER (0) +#define MICROPY_PY_DISPLAY_EPAPER_SLD0020P (0) +#define MICROPY_PY_DISPLAY_LCD (0) +#define MICROPY_PY_DISPLAY_LCD_SLD10261P (0) +#define MICROPY_PY_DISPLAY_OLED (0) +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) +#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) + +#elif MICROPY_PY_DISPLAY + +// Default to include Monochrome Framebuffer +// if display module is selected. +#ifndef MICROPY_PY_LCD_MONO_FB +#define MICROPY_PY_LCD_MONO_FB (1) +#endif + +#ifndef MICROPY_PY_DISPLAY_EPAPER_SLD0020P +#define MICROPY_PY_DISPLAY_EPAPER_SLD0020P (0) +#else +#if MICROPY_PY_DISPLAY_EPAPER_SLD0020P +#define MICROPY_PY_DISPLAY_EPAPER (1) +#endif +#endif // MICROPY_PY_DISPLAY_EPAPER_SLD0020P + +#ifndef MICROPY_PY_DISPLAY_LCD_SLD10261P +#define MICROPY_PY_DISPLAY_LCD_SLD10261P (0) +#else +#if MICROPY_PY_DISPLAY_LCD_SLD10261P +#define MICROPY_PY_DISPLAY_LCD (1) +#endif +#endif // MICROPY_PY_DISPLAY_LCD_SLD10261P + +#ifndef MICROPY_PY_DISPLAY_OLED_SSD1305 +#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) +#else +#if MICROPY_PY_DISPLAY_OLED_SSD1305 +#define MICROPY_PY_DISPLAY_OLED (1) +#endif +#endif // MICROPY_PY_DISPLAY_OLED_SSD1305 + +#ifndef MICROPY_PY_DISPLAY_OLED_SSD1306 +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) +#else +#if MICROPY_PY_DISPLAY_OLED_SSD1306 +#define MICROPY_PY_DISPLAY_OLED (1) +#endif + +#endif // MICROPY_PY_DISPLAY_OLED_SSD1306 + +#endif // MICROPY_PY_DISPLAY + +#ifndef MICROPY_PY_DISPLAY_EPAPER +#define MICROPY_PY_DISPLAY_EPAPER (0) +#endif + +#ifndef MICROPY_PY_DISPLAY_LCD +#define MICROPY_PY_DISPLAY_LCD (0) +#endif + +#ifndef MICROPY_PY_DISPLAY_OLED +#define MICROPY_PY_DISPLAY_OLED (0) +#endif #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) #define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0) @@ -163,6 +229,7 @@ extern const struct _mp_obj_module_t mp_module_uos; extern const struct _mp_obj_module_t mp_module_usocket; extern const struct _mp_obj_module_t mp_module_network; extern const struct _mp_obj_module_t mp_module_lcd_mono_fb; +extern const struct _mp_obj_module_t mp_module_display; #if MICROPY_PY_USOCKET #define SOCKET_BUILTIN_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_usocket), (mp_obj_t)&mp_module_usocket }, @@ -184,6 +251,12 @@ extern const struct _mp_obj_module_t mp_module_lcd_mono_fb; #define LCD_MONO_FB_MODULE #endif +#if MICROPY_PY_DISPLAY +#define DISPLAY_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_display), (mp_obj_t)&mp_module_display }, +#else +#define DISPLAY_MODULE +#endif + #if BLUETOOTH_SD extern const struct _mp_obj_module_t ble_module; #define MICROPY_PORT_BUILTIN_MODULES \ @@ -196,6 +269,7 @@ extern const struct _mp_obj_module_t ble_module; SOCKET_BUILTIN_MODULE \ NETWORK_BUILTIN_MODULE \ LCD_MONO_FB_MODULE \ + DISPLAY_MODULE \ #else @@ -206,6 +280,7 @@ extern const struct _mp_obj_module_t ble_module; { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ LCD_MONO_FB_MODULE \ + DISPLAY_MODULE \ #endif // BLUETOOTH_SD From 6b492cd8c455577e8e5cd36b273378b5209bde3b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 17:18:47 +0100 Subject: [PATCH 094/809] nrf5/drivers: Adding ifdef sourrounding the implementation of module. Configurable with mpconfigport.h. --- nrf5/drivers/display/epaper/moddisplay_epaper.c | 3 +++ nrf5/drivers/display/lcd/moddisplay_lcd.c | 4 ++++ nrf5/drivers/display/oled/moddisplay_oled.c | 4 ++++ 3 files changed, 11 insertions(+) diff --git a/nrf5/drivers/display/epaper/moddisplay_epaper.c b/nrf5/drivers/display/epaper/moddisplay_epaper.c index 7a08e19a1f..3b2aafa2f0 100644 --- a/nrf5/drivers/display/epaper/moddisplay_epaper.c +++ b/nrf5/drivers/display/epaper/moddisplay_epaper.c @@ -26,6 +26,7 @@ #include "py/obj.h" +#if MICROPY_PY_DISPLAY_EPAPER STATIC const mp_map_elem_t epaper_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_epaper) }, #if 0 @@ -39,3 +40,5 @@ const mp_obj_module_t display_epaper_module = { .base = { &mp_type_module }, .globals = (mp_obj_dict_t*)&epaper_module_globals, }; + +#endif // MICROPY_PY_DISPLAY_EPAPER diff --git a/nrf5/drivers/display/lcd/moddisplay_lcd.c b/nrf5/drivers/display/lcd/moddisplay_lcd.c index a456c326d4..7b871521ec 100644 --- a/nrf5/drivers/display/lcd/moddisplay_lcd.c +++ b/nrf5/drivers/display/lcd/moddisplay_lcd.c @@ -26,6 +26,8 @@ #include "py/obj.h" +#if MICROPY_PY_DISPLAY_LCD + STATIC const mp_map_elem_t lcd_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_lcd) }, #if 0 @@ -41,3 +43,5 @@ const mp_obj_module_t display_lcd_module = { .base = { &mp_type_module }, .globals = (mp_obj_dict_t*)&lcd_module_globals, }; + +#endif // MICROPY_PY_DISPLAY_LCD diff --git a/nrf5/drivers/display/oled/moddisplay_oled.c b/nrf5/drivers/display/oled/moddisplay_oled.c index e0b4237241..bb39d46f6f 100644 --- a/nrf5/drivers/display/oled/moddisplay_oled.c +++ b/nrf5/drivers/display/oled/moddisplay_oled.c @@ -26,6 +26,8 @@ #include "py/obj.h" +#if MICROPY_PY_DISPLAY_OLED + STATIC const mp_map_elem_t oled_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_oled) }, #if 0 @@ -40,3 +42,5 @@ const mp_obj_module_t display_oled_module = { .base = { &mp_type_module }, .globals = (mp_obj_dict_t*)&oled_module_globals, }; + +#endif // MICROPY_PY_DISPLAY_OLED From 2b92438d94816b175c97e404319a5e3a0f494d20 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 17:20:00 +0100 Subject: [PATCH 095/809] nrf5/drivers: Renaming display module to mp_module prefix as it is going to be inbuilt. ifdef'ing all submodules based on type of display configured through mpconfigport.h --- nrf5/drivers/display/moddisplay.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/nrf5/drivers/display/moddisplay.c b/nrf5/drivers/display/moddisplay.c index d4a12126dd..f53e121794 100644 --- a/nrf5/drivers/display/moddisplay.c +++ b/nrf5/drivers/display/moddisplay.c @@ -26,21 +26,31 @@ #include "py/obj.h" +#if MICROPY_PY_DISPLAY + #include "epaper/moddisplay_epaper.h" #include "lcd/moddisplay_lcd.h" #include "oled/moddisplay_oled.h" -STATIC const mp_map_elem_t display_module_globals_table[] = { +STATIC const mp_map_elem_t mp_module_display_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_display) }, +#if MICROPY_PY_DISPLAY_EPAPER { MP_OBJ_NEW_QSTR(MP_QSTR_epaper), (mp_obj_t)&display_epaper_module }, +#endif +#if MICROPY_PY_DISPLAY_LCD { MP_OBJ_NEW_QSTR(MP_QSTR_lcd), (mp_obj_t)&display_lcd_module}, +#endif +#if MICROPY_PY_DISPLAY_OLED { MP_OBJ_NEW_QSTR(MP_QSTR_oled), (mp_obj_t)&display_oled_module }, +#endif }; -STATIC MP_DEFINE_CONST_DICT(display_module_globals, display_module_globals_table); +STATIC MP_DEFINE_CONST_DICT(mp_module_display_globals, mp_module_display_globals_table); -const mp_obj_module_t display_module = { +const mp_obj_module_t mp_module_display = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&display_module_globals, + .globals = (mp_obj_dict_t*)&mp_module_display_globals, }; + +#endif // MICROPY_PY_DISPLAY From 87f250deecde311933ad386341d0be91925c6635 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 17:20:51 +0100 Subject: [PATCH 096/809] nrf5/drivers: Removing external decleration of display module in header. --- nrf5/drivers/display/moddisplay.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/drivers/display/moddisplay.h b/nrf5/drivers/display/moddisplay.h index f32833a65d..353097710e 100644 --- a/nrf5/drivers/display/moddisplay.h +++ b/nrf5/drivers/display/moddisplay.h @@ -27,6 +27,4 @@ #ifndef MODDISPLAY_H__ #define MODDISPLAY_H__ -extern const mp_obj_module_t display_module; - #endif // MODDISPLAY_H__ From 25947a1b00f5cf5e177b670de0815805450808ea Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 17:22:58 +0100 Subject: [PATCH 097/809] nrf5/boards: Enable display module to be built in. Also adding one epaper display and one tft lcd to test display module when porting the corresponding drivers to micropython. --- nrf5/boards/pca10040/mpconfigboard.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 9ca7150f7f..d1b2fbc9f6 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -33,6 +33,10 @@ #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_DISPLAY (1) +#define MICROPY_PY_DISPLAY_EPAPER_SLD0020P (1) +#define MICROPY_PY_DISPLAY_LCD_SLD10261P (1) + #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) From 5875013670f6eccc769305618f60f611a745294c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 17:27:02 +0100 Subject: [PATCH 098/809] nrf5/modules: Moving python scripts to examples folder to free up some flash space on constrained targets as modules folder is used as frozen files folder. --- nrf5/{modules => examples}/epaper.py | 0 nrf5/{modules => examples}/mountsd.py | 0 nrf5/{modules => examples}/sdcard.py | 0 nrf5/{modules => examples}/seeed.py | 0 nrf5/{modules => examples}/seeedstudio_tft_shield_v2.py | 0 5 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/{modules => examples}/epaper.py (100%) rename nrf5/{modules => examples}/mountsd.py (100%) rename nrf5/{modules => examples}/sdcard.py (100%) rename nrf5/{modules => examples}/seeed.py (100%) rename nrf5/{modules => examples}/seeedstudio_tft_shield_v2.py (100%) diff --git a/nrf5/modules/epaper.py b/nrf5/examples/epaper.py similarity index 100% rename from nrf5/modules/epaper.py rename to nrf5/examples/epaper.py diff --git a/nrf5/modules/mountsd.py b/nrf5/examples/mountsd.py similarity index 100% rename from nrf5/modules/mountsd.py rename to nrf5/examples/mountsd.py diff --git a/nrf5/modules/sdcard.py b/nrf5/examples/sdcard.py similarity index 100% rename from nrf5/modules/sdcard.py rename to nrf5/examples/sdcard.py diff --git a/nrf5/modules/seeed.py b/nrf5/examples/seeed.py similarity index 100% rename from nrf5/modules/seeed.py rename to nrf5/examples/seeed.py diff --git a/nrf5/modules/seeedstudio_tft_shield_v2.py b/nrf5/examples/seeedstudio_tft_shield_v2.py similarity index 100% rename from nrf5/modules/seeedstudio_tft_shield_v2.py rename to nrf5/examples/seeedstudio_tft_shield_v2.py From 6300c6045a575a8a2f6886d79021ec021947aeea Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 19:56:53 +0100 Subject: [PATCH 099/809] nrf5/drivers: Adding missing file for epaper module / driver. --- .../display/epaper/epaper_sld00200p_driver.c | 33 ++++++++ .../display/epaper/epaper_sld00200p_driver.h | 38 +++++++++ .../display/epaper/epaper_sld00200p_obj.c | 81 +++++++++++++++++++ .../display/epaper/epaper_sld00200p_obj.h | 35 ++++++++ 4 files changed, 187 insertions(+) create mode 100644 nrf5/drivers/display/epaper/epaper_sld00200p_driver.c create mode 100644 nrf5/drivers/display/epaper/epaper_sld00200p_driver.h create mode 100644 nrf5/drivers/display/epaper/epaper_sld00200p_obj.c create mode 100644 nrf5/drivers/display/epaper/epaper_sld00200p_obj.h diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_driver.c b/nrf5/drivers/display/epaper/epaper_sld00200p_driver.c new file mode 100644 index 0000000000..7442e8a3e3 --- /dev/null +++ b/nrf5/drivers/display/epaper/epaper_sld00200p_driver.c @@ -0,0 +1,33 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P + + + +#endif diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_driver.h b/nrf5/drivers/display/epaper/epaper_sld00200p_driver.h new file mode 100644 index 0000000000..2b641381f0 --- /dev/null +++ b/nrf5/drivers/display/epaper/epaper_sld00200p_driver.h @@ -0,0 +1,38 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef EPAPER_SLD00200P_DRIVER_H__ +#define EPAPER_SLD00200P_DRIVER_H__ + +typedef enum +{ + EPD_COMP, + EPD_WHITE, + EPD_INV, + EPD_NORM +} epd_stage_t; + +#endif // EPAPER_SLD00200P_DRIVER_H__ diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c new file mode 100644 index 0000000000..cfe461b6ce --- /dev/null +++ b/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c @@ -0,0 +1,81 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/runtime.h" + +#include "hal_spi.h" +#include "hal_pwm.h" + +#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P + +typedef struct _epaper_sld00200p_obj_t { + mp_obj_base_t base; + SPI_HandleTypeDef *spi; + PWM_HandleTypeDef *pwm; +} epaper_sld00200p_obj_t; + +STATIC void epaper_sld00200_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { +} + +// for make_new +enum { + ARG_NEW_SPI, + ARG_NEW_CS, + ARG_NEW_PWM, + ARG_NEW_PANEL_ON, + ARG_NEW_BORDER, + ARG_NEW_RESET, + ARG_NEW_BUSY, + ARG_NEW_DISCHARGE, + ARG_NEW_TEMP_SENSOR, +}; + +STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + epaper_sld00200p_obj_t *s = m_new_obj_with_finaliser(epaper_sld00200p_obj_t); + return MP_OBJ_FROM_PTR(s); +} + +const mp_obj_type_t epaper_sld00200p_type = { + { &mp_type_type }, + .name = MP_QSTR_sld00200p, + .print = epaper_sld00200_print, + .make_new = epaper_sld00200p_make_new, +#if 0 + .locals_dict = (mp_obj_t)&epaper_sld00200p_locals_dict +#endif +}; + +#endif // MICROPY_PY_DISPLAY_EPAPER_SLD00200P + diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_obj.h b/nrf5/drivers/display/epaper/epaper_sld00200p_obj.h new file mode 100644 index 0000000000..f6a3fa8ed9 --- /dev/null +++ b/nrf5/drivers/display/epaper/epaper_sld00200p_obj.h @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef EPAPER_SLD00200P_H__ +#define EPAPER_SLD00200P_H__ + +#include + +extern const mp_obj_type_t epaper_sld00200p_type; + +#endif // EPAPER_SLD00200P_H__ + From d2f5f1fe602ea1faeec773631df1e5e4c6b6af20 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 19:57:58 +0100 Subject: [PATCH 100/809] nrf5/drivers: Enable EPAPER_SLD00200P in epaper module globals table. --- nrf5/drivers/display/epaper/moddisplay_epaper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/nrf5/drivers/display/epaper/moddisplay_epaper.c b/nrf5/drivers/display/epaper/moddisplay_epaper.c index 3b2aafa2f0..fb481429ad 100644 --- a/nrf5/drivers/display/epaper/moddisplay_epaper.c +++ b/nrf5/drivers/display/epaper/moddisplay_epaper.c @@ -24,12 +24,14 @@ * THE SOFTWARE. */ +#include "epaper_sld00200p_obj.h" #include "py/obj.h" + #if MICROPY_PY_DISPLAY_EPAPER STATIC const mp_map_elem_t epaper_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_epaper) }, -#if 0 +#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P { MP_OBJ_NEW_QSTR(MP_QSTR_sld00200p), (mp_obj_t)&epaper_sld00200p_type }, #endif }; From 643bf1946663ff8585b67012da86ca94c0d1ad22 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 19:59:12 +0100 Subject: [PATCH 101/809] nrf5: Correcting define name for epaper sld00200p, missing 0. --- nrf5/boards/pca10040/mpconfigboard.h | 6 ++--- nrf5/mpconfigport.h | 38 ++++++++++++++-------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index d1b2fbc9f6..45d440c948 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -33,9 +33,9 @@ #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) -#define MICROPY_PY_DISPLAY (1) -#define MICROPY_PY_DISPLAY_EPAPER_SLD0020P (1) -#define MICROPY_PY_DISPLAY_LCD_SLD10261P (1) +#define MICROPY_PY_DISPLAY (1) +#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) +#define MICROPY_PY_DISPLAY_LCD_SLD10261P (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 569ab430f4..ec34c79525 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -133,52 +133,52 @@ #ifndef MICROPY_PY_DISPLAY -#define MICROPY_PY_DISPLAY (0) -#define MICROPY_PY_DISPLAY_EPAPER (0) -#define MICROPY_PY_DISPLAY_EPAPER_SLD0020P (0) -#define MICROPY_PY_DISPLAY_LCD (0) -#define MICROPY_PY_DISPLAY_LCD_SLD10261P (0) -#define MICROPY_PY_DISPLAY_OLED (0) -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) -#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) +#define MICROPY_PY_DISPLAY (0) +#define MICROPY_PY_DISPLAY_EPAPER (0) +#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) +#define MICROPY_PY_DISPLAY_LCD (0) +#define MICROPY_PY_DISPLAY_LCD_SLD10261P (0) +#define MICROPY_PY_DISPLAY_OLED (0) +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) +#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #elif MICROPY_PY_DISPLAY // Default to include Monochrome Framebuffer // if display module is selected. #ifndef MICROPY_PY_LCD_MONO_FB -#define MICROPY_PY_LCD_MONO_FB (1) +#define MICROPY_PY_LCD_MONO_FB (1) #endif -#ifndef MICROPY_PY_DISPLAY_EPAPER_SLD0020P -#define MICROPY_PY_DISPLAY_EPAPER_SLD0020P (0) +#ifndef MICROPY_PY_DISPLAY_EPAPER_SLD00200P +#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) #else -#if MICROPY_PY_DISPLAY_EPAPER_SLD0020P -#define MICROPY_PY_DISPLAY_EPAPER (1) +#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P +#define MICROPY_PY_DISPLAY_EPAPER (1) #endif #endif // MICROPY_PY_DISPLAY_EPAPER_SLD0020P #ifndef MICROPY_PY_DISPLAY_LCD_SLD10261P -#define MICROPY_PY_DISPLAY_LCD_SLD10261P (0) +#define MICROPY_PY_DISPLAY_LCD_SLD10261P (0) #else #if MICROPY_PY_DISPLAY_LCD_SLD10261P -#define MICROPY_PY_DISPLAY_LCD (1) +#define MICROPY_PY_DISPLAY_LCD (1) #endif #endif // MICROPY_PY_DISPLAY_LCD_SLD10261P #ifndef MICROPY_PY_DISPLAY_OLED_SSD1305 -#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) +#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #else #if MICROPY_PY_DISPLAY_OLED_SSD1305 -#define MICROPY_PY_DISPLAY_OLED (1) +#define MICROPY_PY_DISPLAY_OLED (1) #endif #endif // MICROPY_PY_DISPLAY_OLED_SSD1305 #ifndef MICROPY_PY_DISPLAY_OLED_SSD1306 -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #else #if MICROPY_PY_DISPLAY_OLED_SSD1306 -#define MICROPY_PY_DISPLAY_OLED (1) +#define MICROPY_PY_DISPLAY_OLED (1) #endif #endif // MICROPY_PY_DISPLAY_OLED_SSD1306 From cc3364db7f66f5e2982c0dc386e4a6716d0b6a0d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 20:00:10 +0100 Subject: [PATCH 102/809] nrf5: Adding suffix to _obj on epaper_sld00200p module. --- nrf5/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index e834caf25d..cb730e9e77 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -153,7 +153,7 @@ DRIVERS_SRC_C += $(addprefix drivers/,\ display/epaper/moddisplay_epaper.c \ display/lcd/moddisplay_lcd.c \ display/oled/moddisplay_oled.c \ - display/epaper/epaper_sld00200p.c \ + display/epaper/epaper_sld00200p_obj.c \ display/epaper/epaper_sld00200p_driver.c \ ) From 31a54e063aae2b89a8b9f757d61c7f48b68ac13f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 20:05:01 +0100 Subject: [PATCH 103/809] nrf5/drivers: Adding requirement for nrf52 target on the epaper sld00200p for now. There is no ported PWM module for nrf51 target yet. Hence, soft PWM for nrf51 needs to be added. --- nrf5/drivers/display/epaper/epaper_sld00200p_obj.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c index cfe461b6ce..8470850108 100644 --- a/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c +++ b/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c @@ -27,11 +27,12 @@ #include "py/obj.h" #include "py/runtime.h" +// For now PWM is only enabled for nrf52 targets. +#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P && NRF52 + #include "hal_spi.h" #include "hal_pwm.h" -#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P - typedef struct _epaper_sld00200p_obj_t { mp_obj_base_t base; SPI_HandleTypeDef *spi; From 6a077806c6fd82da0a35486cae0c2706763c67e6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 20:11:41 +0100 Subject: [PATCH 104/809] nrf5: Enable MICROPY_FINALISER and REPL_AUTO_INDENT. --- nrf5/mpconfigport.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index ec34c79525..daa5a64aee 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -39,11 +39,11 @@ #define MICROPY_COMP_MODULE_CONST (0) #define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0) #define MICROPY_ENABLE_GC (1) -#define MICROPY_ENABLE_FINALISER (0) +#define MICROPY_ENABLE_FINALISER (1) #define MICROPY_STACK_CHECK (0) #define MICROPY_HELPER_REPL (1) #define MICROPY_REPL_EMACS_KEYS (0) -#define MICROPY_REPL_AUTO_INDENT (0) +#define MICROPY_REPL_AUTO_INDENT (1) #define MICROPY_ENABLE_SOURCE_LINE (0) #define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ) #define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_NONE) From 4c0bb63e2bb1df8059d4afea7debb08acb7d8030 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 21:06:51 +0100 Subject: [PATCH 105/809] nrf5: Moving color defines in lcd_mono_fb from .c to .h so that it can be reused by other modules. --- nrf5/lcd_mono_fb.c | 3 --- nrf5/lcd_mono_fb.h | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index ac6c437f75..e0ff01df1f 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -37,9 +37,6 @@ #if MICROPY_PY_LCD_MONO_FB -#define LCD_BLACK 0 -#define LCD_WHITE 1 - typedef struct { mp_obj_base_t base; fb_byte_t * fb_bytes; diff --git a/nrf5/lcd_mono_fb.h b/nrf5/lcd_mono_fb.h index 82a6d637c7..9771fd6142 100644 --- a/nrf5/lcd_mono_fb.h +++ b/nrf5/lcd_mono_fb.h @@ -31,6 +31,9 @@ extern const mp_obj_module_t mp_module_lcd_mono_fb; #include +#define LCD_BLACK 0 +#define LCD_WHITE 1 + typedef struct { uint8_t bit0 : 1; uint8_t bit1 : 1; From 6cddad02a8b6b7dc377b686194883014e5e3adc2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Jan 2017 21:10:06 +0100 Subject: [PATCH 106/809] nrf5/drivers: Creating python object implementation (locals) to be used for epaper sld00200p. --- .../display/epaper/epaper_sld00200p_obj.c | 135 +++++++++++++++++- 1 file changed, 131 insertions(+), 4 deletions(-) diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c index 8470850108..07cb2bd696 100644 --- a/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c +++ b/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c @@ -30,8 +30,12 @@ // For now PWM is only enabled for nrf52 targets. #if MICROPY_PY_DISPLAY_EPAPER_SLD00200P && NRF52 +/// \moduleref epaper +/// \class sld00200p - SLD00200P E-paper shield. + #include "hal_spi.h" #include "hal_pwm.h" +#include "lcd_mono_fb.h" typedef struct _epaper_sld00200p_obj_t { mp_obj_base_t base; @@ -39,6 +43,8 @@ typedef struct _epaper_sld00200p_obj_t { PWM_HandleTypeDef *pwm; } epaper_sld00200p_obj_t; +/// \method __str__() +/// Return a string describing the SLD00200P object. STATIC void epaper_sld00200_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { } @@ -68,15 +74,136 @@ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_ar return MP_OBJ_FROM_PTR(s); } +// text + +/// \method fill(color) +/// Fill framebuffer with the color defined as argument. +STATIC mp_obj_t epaper_sld00200p_fill(mp_obj_t self_in, mp_obj_t color) { + epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(self_in); + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(epaper_sld00200p_fill_obj, epaper_sld00200p_fill); + +/// \method show([num_of_refresh]) +/// Display content in framebuffer. +/// +/// - With no argument, no refresh is done. +/// - With `num_of_refresh` given, the lines touched by previous update +/// will be refreshed the given number of times. If no lines have been +/// touched, no update will be performed. To force a refresh, call the +/// refresh() method explicitly. +STATIC mp_obj_t epaper_sld00200p_show(size_t n_args, const mp_obj_t *args) { + epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t num_of_refresh = 0; + + if (n_args > 1) { + num_of_refresh = mp_obj_get_int(args[1]); + } + + (void)num_of_refresh; + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_show_obj, 1, 2, epaper_sld00200p_show); + +/// \method refresh([num_of_refresh]) +/// Refresh content in framebuffer. +/// +/// - With no argument, 1 refresh will be done. +/// - With `num_of_refresh` given, The whole framebuffer will be considered +/// dirty and will be refreshed the given number of times. +STATIC mp_obj_t epaper_sld00200p_refresh(mp_obj_t self_in) { + epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(epaper_sld00200p_refresh_obj, epaper_sld00200p_refresh); + +/// \method pixel(x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color of the pixel in framebuffer will be returend. +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t epaper_sld00200p_pixel(size_t n_args, const mp_obj_t *args) { + epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t x = mp_obj_get_int(args[1]); + mp_int_t y = mp_obj_get_int(args[2]); + mp_int_t color; + if (n_args >= 3) { + color = mp_obj_get_int(args[3]); + } + (void)self; + (void)x; + (void)y; + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_pixel_obj, 3, 4, epaper_sld00200p_pixel); + +/// \method pixel(text, x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color will be the opposite of background (fill color). +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t epaper_sld00200p_text(size_t n_args, const mp_obj_t *args) { + epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); + const char *str = mp_obj_str_get_str(args[1]); + mp_int_t x = mp_obj_get_int(args[2]); + mp_int_t y = mp_obj_get_int(args[3]); + mp_int_t color; + if (n_args >= 4) { + color = mp_obj_get_int(args[3]); + } + (void)self; + (void)str; + (void)x; + (void)y; + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_text_obj, 4, 5, epaper_sld00200p_text); + + +STATIC mp_obj_t epaper_sld00200p_del(mp_obj_t self_in) { + epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(epaper_sld00200p_del_obj, epaper_sld00200p_del); + +STATIC const mp_rom_map_elem_t epaper_sld00200p_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR___del__), MP_ROM_PTR(&epaper_sld00200p_del_obj) }, + { MP_ROM_QSTR(MP_QSTR_fill), MP_ROM_PTR(&epaper_sld00200p_fill_obj) }, + { MP_ROM_QSTR(MP_QSTR_show), MP_ROM_PTR(&epaper_sld00200p_show_obj) }, + { MP_ROM_QSTR(MP_QSTR_refresh), MP_ROM_PTR(&epaper_sld00200p_refresh_obj) }, + { MP_ROM_QSTR(MP_QSTR_text), MP_ROM_PTR(&epaper_sld00200p_text_obj) }, + { MP_ROM_QSTR(MP_QSTR_pixel), MP_ROM_PTR(&epaper_sld00200p_pixel_obj) }, +#if 0 + { MP_ROM_QSTR(MP_QSTR_bitmap), MP_ROM_PTR(&epaper_sld00200p_bitmap_obj) }, +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_BLACK) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_WHITE) }, + +}; + +STATIC MP_DEFINE_CONST_DICT(epaper_sld00200p_locals_dict, epaper_sld00200p_locals_dict_table); + + const mp_obj_type_t epaper_sld00200p_type = { { &mp_type_type }, - .name = MP_QSTR_sld00200p, + .name = MP_QSTR_SLD00200P, .print = epaper_sld00200_print, .make_new = epaper_sld00200p_make_new, -#if 0 .locals_dict = (mp_obj_t)&epaper_sld00200p_locals_dict -#endif }; #endif // MICROPY_PY_DISPLAY_EPAPER_SLD00200P - From aaadec99e06f109b335843d90ac724a8750a824d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 00:49:21 +0100 Subject: [PATCH 107/809] nrf5/drivers: Removing one level of module hierarchy in display drivers. Removed epaper, lcd and oled modules, making import of classes happen directly from display module. --- .../display/epaper/moddisplay_epaper.c | 46 ------------------ .../display/epaper/moddisplay_epaper.h | 32 ------------- .../{epaper => }/epaper_sld00200p_driver.c | 2 +- .../{epaper => }/epaper_sld00200p_driver.h | 0 .../{epaper => }/epaper_sld00200p_obj.c | 0 .../{epaper => }/epaper_sld00200p_obj.h | 0 nrf5/drivers/display/lcd/moddisplay_lcd.c | 47 ------------------- nrf5/drivers/display/lcd/moddisplay_lcd.h | 32 ------------- nrf5/drivers/display/moddisplay.c | 19 ++++---- nrf5/drivers/display/oled/moddisplay_oled.c | 46 ------------------ nrf5/drivers/display/oled/moddisplay_oled.h | 32 ------------- 11 files changed, 10 insertions(+), 246 deletions(-) delete mode 100644 nrf5/drivers/display/epaper/moddisplay_epaper.c delete mode 100644 nrf5/drivers/display/epaper/moddisplay_epaper.h rename nrf5/drivers/display/{epaper => }/epaper_sld00200p_driver.c (96%) rename nrf5/drivers/display/{epaper => }/epaper_sld00200p_driver.h (100%) rename nrf5/drivers/display/{epaper => }/epaper_sld00200p_obj.c (100%) rename nrf5/drivers/display/{epaper => }/epaper_sld00200p_obj.h (100%) delete mode 100644 nrf5/drivers/display/lcd/moddisplay_lcd.c delete mode 100644 nrf5/drivers/display/lcd/moddisplay_lcd.h delete mode 100644 nrf5/drivers/display/oled/moddisplay_oled.c delete mode 100644 nrf5/drivers/display/oled/moddisplay_oled.h diff --git a/nrf5/drivers/display/epaper/moddisplay_epaper.c b/nrf5/drivers/display/epaper/moddisplay_epaper.c deleted file mode 100644 index fb481429ad..0000000000 --- a/nrf5/drivers/display/epaper/moddisplay_epaper.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "epaper_sld00200p_obj.h" -#include "py/obj.h" - - -#if MICROPY_PY_DISPLAY_EPAPER -STATIC const mp_map_elem_t epaper_module_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_epaper) }, -#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P - { MP_OBJ_NEW_QSTR(MP_QSTR_sld00200p), (mp_obj_t)&epaper_sld00200p_type }, -#endif -}; - -STATIC MP_DEFINE_CONST_DICT(epaper_module_globals, epaper_module_globals_table); - -const mp_obj_module_t display_epaper_module = { - .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&epaper_module_globals, -}; - -#endif // MICROPY_PY_DISPLAY_EPAPER diff --git a/nrf5/drivers/display/epaper/moddisplay_epaper.h b/nrf5/drivers/display/epaper/moddisplay_epaper.h deleted file mode 100644 index 5a90a001fa..0000000000 --- a/nrf5/drivers/display/epaper/moddisplay_epaper.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef MODDISPLAY_EPAPER_H__ -#define MODDISPLAY_EPAPER_H__ - -extern const mp_obj_module_t display_epaper_module; - -#endif // MODDISPLAY_EPAPER_H__ diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_driver.c b/nrf5/drivers/display/epaper_sld00200p_driver.c similarity index 96% rename from nrf5/drivers/display/epaper/epaper_sld00200p_driver.c rename to nrf5/drivers/display/epaper_sld00200p_driver.c index 7442e8a3e3..3deef46ecd 100644 --- a/nrf5/drivers/display/epaper/epaper_sld00200p_driver.c +++ b/nrf5/drivers/display/epaper_sld00200p_driver.c @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -#include +#include "epaper_sld00200p_driver.h" #if MICROPY_PY_DISPLAY_EPAPER_SLD00200P diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_driver.h b/nrf5/drivers/display/epaper_sld00200p_driver.h similarity index 100% rename from nrf5/drivers/display/epaper/epaper_sld00200p_driver.h rename to nrf5/drivers/display/epaper_sld00200p_driver.h diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper_sld00200p_obj.c similarity index 100% rename from nrf5/drivers/display/epaper/epaper_sld00200p_obj.c rename to nrf5/drivers/display/epaper_sld00200p_obj.c diff --git a/nrf5/drivers/display/epaper/epaper_sld00200p_obj.h b/nrf5/drivers/display/epaper_sld00200p_obj.h similarity index 100% rename from nrf5/drivers/display/epaper/epaper_sld00200p_obj.h rename to nrf5/drivers/display/epaper_sld00200p_obj.h diff --git a/nrf5/drivers/display/lcd/moddisplay_lcd.c b/nrf5/drivers/display/lcd/moddisplay_lcd.c deleted file mode 100644 index 7b871521ec..0000000000 --- a/nrf5/drivers/display/lcd/moddisplay_lcd.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" - -#if MICROPY_PY_DISPLAY_LCD - -STATIC const mp_map_elem_t lcd_module_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_lcd) }, -#if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_sld10261p), (mp_obj_t)&lcd_sld10261p_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ssd1289), (mp_obj_t)&lcd_ssd1289_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ls027b7dh01), (mp_obj_t)&lcd_ls027b7dh01_type }, -#endif -}; - -STATIC MP_DEFINE_CONST_DICT(lcd_module_globals, lcd_module_globals_table); - -const mp_obj_module_t display_lcd_module = { - .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&lcd_module_globals, -}; - -#endif // MICROPY_PY_DISPLAY_LCD diff --git a/nrf5/drivers/display/lcd/moddisplay_lcd.h b/nrf5/drivers/display/lcd/moddisplay_lcd.h deleted file mode 100644 index 8646316f53..0000000000 --- a/nrf5/drivers/display/lcd/moddisplay_lcd.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef MODDISPLAY_LCD_H__ -#define MODDISPLAY_LCD_H__ - -extern const mp_obj_module_t display_lcd_module; - -#endif // MODDISPLAY_LCD_H__ diff --git a/nrf5/drivers/display/moddisplay.c b/nrf5/drivers/display/moddisplay.c index f53e121794..2de89bb967 100644 --- a/nrf5/drivers/display/moddisplay.c +++ b/nrf5/drivers/display/moddisplay.c @@ -28,20 +28,19 @@ #if MICROPY_PY_DISPLAY -#include "epaper/moddisplay_epaper.h" -#include "lcd/moddisplay_lcd.h" -#include "oled/moddisplay_oled.h" +#include "epaper_sld00200p_obj.h" STATIC const mp_map_elem_t mp_module_display_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_display) }, -#if MICROPY_PY_DISPLAY_EPAPER - { MP_OBJ_NEW_QSTR(MP_QSTR_epaper), (mp_obj_t)&display_epaper_module }, +#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P + { MP_OBJ_NEW_QSTR(MP_QSTR_SLD00200P), (mp_obj_t)&epaper_sld00200p_type }, #endif -#if MICROPY_PY_DISPLAY_LCD - { MP_OBJ_NEW_QSTR(MP_QSTR_lcd), (mp_obj_t)&display_lcd_module}, -#endif -#if MICROPY_PY_DISPLAY_OLED - { MP_OBJ_NEW_QSTR(MP_QSTR_oled), (mp_obj_t)&display_oled_module }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_SLD10261P), (mp_obj_t)&lcd_sld10261p_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1289), (mp_obj_t)&lcd_ssd1289_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_LS027b7DH01), (mp_obj_t)&lcd_ls027b7dh01_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1305), (mp_obj_t)&oled_ssd1305_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1306), (mp_obj_t)&oled_ssd1306_type }, #endif }; diff --git a/nrf5/drivers/display/oled/moddisplay_oled.c b/nrf5/drivers/display/oled/moddisplay_oled.c deleted file mode 100644 index bb39d46f6f..0000000000 --- a/nrf5/drivers/display/oled/moddisplay_oled.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" - -#if MICROPY_PY_DISPLAY_OLED - -STATIC const mp_map_elem_t oled_module_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_oled) }, -#if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_ssd1305), (mp_obj_t)&oled_ssd1305_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ssd1306), (mp_obj_t)&oled_ssd1306_type }, -#endif -}; - -STATIC MP_DEFINE_CONST_DICT(oled_module_globals, oled_module_globals_table); - -const mp_obj_module_t display_oled_module = { - .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&oled_module_globals, -}; - -#endif // MICROPY_PY_DISPLAY_OLED diff --git a/nrf5/drivers/display/oled/moddisplay_oled.h b/nrf5/drivers/display/oled/moddisplay_oled.h deleted file mode 100644 index 9a37e4b715..0000000000 --- a/nrf5/drivers/display/oled/moddisplay_oled.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef MODDISPLAY_OLED_H__ -#define MODDISPLAY_OLED_H__ - -extern const mp_obj_module_t display_oled_module; - -#endif // MODDISPLAY_OLED_H__ From b85b3b4e241390d56acecff10fedbcb428a08e5d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 10:35:39 +0100 Subject: [PATCH 108/809] nrf5: Removing epaper, lcd and oled modules from Makefile source list as the display modules has been moved to display root folder. --- nrf5/Makefile | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index cb730e9e77..88e35012a9 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -150,11 +150,8 @@ SRC_C += \ DRIVERS_SRC_C += $(addprefix drivers/,\ display/moddisplay.c \ - display/epaper/moddisplay_epaper.c \ - display/lcd/moddisplay_lcd.c \ - display/oled/moddisplay_oled.c \ - display/epaper/epaper_sld00200p_obj.c \ - display/epaper/epaper_sld00200p_driver.c \ + display/epaper_sld00200p_obj.c \ + display/epaper_sld00200p_driver.c \ ) #ifeq ($(SD), ) From f9ffcfdb7d239fd0af236db68a1e8e5b4e1f7953 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 19:50:20 +0100 Subject: [PATCH 109/809] nrf5/spi: Moving *_spi_obj_t out of implementation file to header. Setting hal init structure in the object structure instead of making a temp struct to configure hal. This would enable lookup of the spi settings later. --- nrf5/spi.c | 46 +++++++++++++++++----------------------------- nrf5/spi.h | 11 +++++++++++ 2 files changed, 28 insertions(+), 29 deletions(-) diff --git a/nrf5/spi.c b/nrf5/spi.c index 3006b626b5..1306a8f8ee 100644 --- a/nrf5/spi.c +++ b/nrf5/spi.c @@ -63,11 +63,6 @@ /// spi.send_recv(b'1234', buf) # send 4 bytes and receive 4 into buf /// spi.send_recv(buf, buf) # send/recv 4 bytes from/to buf -typedef struct _pyb_spi_obj_t { - mp_obj_base_t base; - SPI_HandleTypeDef *spi; -} pyb_spi_obj_t; - #if defined(MICROPY_HW_SPI0_SCK) SPI_HandleTypeDef SPIHandle0 = {.instance = NULL}; #endif @@ -234,11 +229,6 @@ STATIC MP_DEFINE_CONST_DICT(machine_spi_locals_dict, machine_spi_locals_dict_tab /* code for hard implementation ***********************************************/ -typedef struct _machine_hard_spi_obj_t { - mp_obj_base_t base; - const pyb_spi_obj_t *pyb; -} machine_hard_spi_obj_t; - STATIC const machine_hard_spi_obj_t machine_hard_spi_obj[] = { {{&machine_hard_spi_type}, &machine_spi_obj[0]}, }; @@ -253,44 +243,42 @@ STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) { int spi_id = spi_find(args[ARG_NEW_id].u_obj); const machine_hard_spi_obj_t *self = &machine_hard_spi_obj[spi_id]; - hal_spi_init_t spi_init_conf; - // here we would check the sck/mosi/miso pins and configure them if (args[ARG_NEW_sck].u_obj != MP_OBJ_NULL && args[ARG_NEW_mosi].u_obj != MP_OBJ_NULL && args[ARG_NEW_miso].u_obj != MP_OBJ_NULL) { - spi_init_conf.clk_pin = mp_obj_get_int(args[ARG_NEW_sck].u_obj); - spi_init_conf.mosi_pin = mp_obj_get_int(args[ARG_NEW_mosi].u_obj); - spi_init_conf.miso_pin = mp_obj_get_int(args[ARG_NEW_miso].u_obj); + self->pyb->spi->init.clk_pin = mp_obj_get_int(args[ARG_NEW_sck].u_obj); + self->pyb->spi->init.mosi_pin = mp_obj_get_int(args[ARG_NEW_mosi].u_obj); + self->pyb->spi->init.miso_pin = mp_obj_get_int(args[ARG_NEW_miso].u_obj); } else { - spi_init_conf.clk_pin = MICROPY_HW_SPI0_SCK; - spi_init_conf.mosi_pin = MICROPY_HW_SPI0_MOSI; - spi_init_conf.miso_pin = MICROPY_HW_SPI0_MISO; + self->pyb->spi->init.clk_pin = MICROPY_HW_SPI0_SCK; + self->pyb->spi->init.mosi_pin = MICROPY_HW_SPI0_MOSI; + self->pyb->spi->init.miso_pin = MICROPY_HW_SPI0_MISO; } int baudrate = args[ARG_NEW_baudrate].u_int; if (baudrate <= 125000) { - spi_init_conf.freq = HAL_FREQ_125_Kbps; + self->pyb->spi->init.freq = HAL_FREQ_125_Kbps; } else if (baudrate <= 250000) { - spi_init_conf.freq = HAL_FREQ_250_Kbps; + self->pyb->spi->init.freq = HAL_FREQ_250_Kbps; } else if (baudrate <= 500000) { - spi_init_conf.freq = HAL_FREQ_500_Kbps; + self->pyb->spi->init.freq = HAL_FREQ_500_Kbps; } else if (baudrate <= 1000000) { - spi_init_conf.freq = HAL_FREQ_1_Mbps; + self->pyb->spi->init.freq = HAL_FREQ_1_Mbps; } else if (baudrate <= 2000000) { - spi_init_conf.freq = HAL_FREQ_2_Mbps; + self->pyb->spi->init.freq = HAL_FREQ_2_Mbps; } else if (baudrate <= 4000000) { - spi_init_conf.freq = HAL_FREQ_4_Mbps; + self->pyb->spi->init.freq = HAL_FREQ_4_Mbps; } else { - spi_init_conf.freq = HAL_FREQ_8_Mbps; + self->pyb->spi->init.freq = HAL_FREQ_8_Mbps; } - spi_init_conf.irq_priority = 4; - spi_init_conf.mode = HAL_SPI_MODE_CPOL0_CPHA0; - spi_init_conf.lsb_first = false; - hal_spi_master_init(self->pyb->spi->instance, &spi_init_conf); + self->pyb->spi->init.irq_priority = 4; + self->pyb->spi->init.mode = HAL_SPI_MODE_CPOL0_CPHA0; + self->pyb->spi->init.lsb_first = false; + hal_spi_master_init(self->pyb->spi->instance, &self->pyb->spi->init); return MP_OBJ_FROM_PTR(self); } diff --git a/nrf5/spi.h b/nrf5/spi.h index dc8489d1e0..58d683c19c 100644 --- a/nrf5/spi.h +++ b/nrf5/spi.h @@ -24,9 +24,20 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ +#include "py/obj.h" #include "hal_spi.h" +typedef struct _pyb_spi_obj_t { + mp_obj_base_t base; + SPI_HandleTypeDef *spi; +} pyb_spi_obj_t; + +typedef struct _machine_hard_spi_obj_t { + mp_obj_base_t base; + const pyb_spi_obj_t *pyb; +} machine_hard_spi_obj_t; + extern const mp_obj_type_t machine_hard_spi_type; void spi_init0(void); From 4c24d3912261dd750a7297f515f52c37431605c7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 19:56:09 +0100 Subject: [PATCH 110/809] nrf5: Trimming down display configurations in mpconfigport.h --- nrf5/mpconfigport.h | 38 +++----------------------------------- 1 file changed, 3 insertions(+), 35 deletions(-) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index daa5a64aee..d37ed6b0be 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -134,11 +134,8 @@ #ifndef MICROPY_PY_DISPLAY #define MICROPY_PY_DISPLAY (0) -#define MICROPY_PY_DISPLAY_EPAPER (0) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) -#define MICROPY_PY_DISPLAY_LCD (0) -#define MICROPY_PY_DISPLAY_LCD_SLD10261P (0) -#define MICROPY_PY_DISPLAY_OLED (0) +#define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) @@ -152,51 +149,22 @@ #ifndef MICROPY_PY_DISPLAY_EPAPER_SLD00200P #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) -#else -#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P -#define MICROPY_PY_DISPLAY_EPAPER (1) #endif -#endif // MICROPY_PY_DISPLAY_EPAPER_SLD0020P -#ifndef MICROPY_PY_DISPLAY_LCD_SLD10261P -#define MICROPY_PY_DISPLAY_LCD_SLD10261P (0) -#else -#if MICROPY_PY_DISPLAY_LCD_SLD10261P -#define MICROPY_PY_DISPLAY_LCD (1) +#ifndef MICROPY_PY_DISPLAY_LCD_ILI9341 +#define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) #endif -#endif // MICROPY_PY_DISPLAY_LCD_SLD10261P #ifndef MICROPY_PY_DISPLAY_OLED_SSD1305 #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) -#else -#if MICROPY_PY_DISPLAY_OLED_SSD1305 -#define MICROPY_PY_DISPLAY_OLED (1) #endif -#endif // MICROPY_PY_DISPLAY_OLED_SSD1305 #ifndef MICROPY_PY_DISPLAY_OLED_SSD1306 #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) -#else -#if MICROPY_PY_DISPLAY_OLED_SSD1306 -#define MICROPY_PY_DISPLAY_OLED (1) #endif -#endif // MICROPY_PY_DISPLAY_OLED_SSD1306 - #endif // MICROPY_PY_DISPLAY -#ifndef MICROPY_PY_DISPLAY_EPAPER -#define MICROPY_PY_DISPLAY_EPAPER (0) -#endif - -#ifndef MICROPY_PY_DISPLAY_LCD -#define MICROPY_PY_DISPLAY_LCD (0) -#endif - -#ifndef MICROPY_PY_DISPLAY_OLED -#define MICROPY_PY_DISPLAY_OLED (0) -#endif - #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) #define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0) From e7c535b0cb207766f2af5012a8d599416f6f73c0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 19:58:12 +0100 Subject: [PATCH 111/809] nrf5: Moving out mp_obj_framebuf_t to the header file to get access to it from other modules. Exposing helper function to make new framebuffer object from c-code. --- nrf5/lcd_mono_fb.c | 43 ++++++++++++++++++++++++++++--------------- nrf5/lcd_mono_fb.h | 19 +++++++++++++++++++ 2 files changed, 47 insertions(+), 15 deletions(-) diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index e0ff01df1f..4e11b9a81f 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -37,21 +37,6 @@ #if MICROPY_PY_LCD_MONO_FB -typedef struct { - mp_obj_base_t base; - fb_byte_t * fb_bytes; - fb_byte_t * fb_old; - fb_byte_t * fb_dirty; - uint16_t height; - uint16_t width; - mp_uint_t bytes_stride; - mp_uint_t dirty_stride; - mp_obj_t line_update_cb; - mp_uint_t bg_color; - mp_uint_t fg_color; - mp_uint_t font_size; -} mp_obj_framebuf_t; - STATIC void lcd_enable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { uint16_t column = (x / 8); uint16_t line = y; @@ -214,6 +199,34 @@ STATIC void lcd_update(mp_obj_framebuf_t * p_framebuffer, bool refresh) { } } +mp_obj_t lcd_mono_fb_helper_make_new(mp_int_t width, mp_int_t height, mp_int_t vertical) { + + mp_obj_framebuf_t *o = m_new_obj(mp_obj_framebuf_t); + o->base.type = &mp_type_object; + + o->width = width; + o->height = height; + + o->bytes_stride = o->width / 8; + o->dirty_stride = o->height / 8; + + o->fb_bytes = m_new(fb_byte_t, (o->bytes_stride) * o->height); + o->fb_dirty = m_new(fb_byte_t, o->dirty_stride); + + // default to not use double buffer + o->fb_old = NULL; + + o->font_size = 1; + + if (vertical) { + o->fb_old = m_new(fb_byte_t, (o->bytes_stride) * o->height); + } + + lcd_init(o); + + return MP_OBJ_FROM_PTR(o); +} + STATIC mp_obj_t lcd_mono_fb_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { mp_arg_check_num(n_args, n_kw, 3, 4, false); diff --git a/nrf5/lcd_mono_fb.h b/nrf5/lcd_mono_fb.h index 9771fd6142..85f85a92db 100644 --- a/nrf5/lcd_mono_fb.h +++ b/nrf5/lcd_mono_fb.h @@ -52,4 +52,23 @@ typedef struct { }; } fb_byte_t; +typedef struct { + mp_obj_base_t base; + fb_byte_t * fb_bytes; + fb_byte_t * fb_old; + fb_byte_t * fb_dirty; + uint16_t height; + uint16_t width; + mp_uint_t bytes_stride; + mp_uint_t dirty_stride; + mp_obj_t line_update_cb; + mp_uint_t bg_color; + mp_uint_t fg_color; + mp_uint_t font_size; +} mp_obj_framebuf_t; + +// Functions for other drivers to use to create framebuffer instances using c. + +mp_obj_t lcd_mono_fb_helper_make_new(mp_int_t width, mp_int_t height, mp_int_t direction); + #endif From 56d187b942fd27f2e42f90a91a7d25c3d9252032 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 19:59:25 +0100 Subject: [PATCH 112/809] nrf5/boards: Changing tft lcd display name from SLD10261P to ILI9341 in pca10040 board configuration. --- nrf5/boards/pca10040/mpconfigboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 45d440c948..fc72d9d07d 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -35,7 +35,7 @@ #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) -#define MICROPY_PY_DISPLAY_LCD_SLD10261P (1) +#define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) From 28539221ce299dc85c428b35a8f51dead7a5b770 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 20:01:23 +0100 Subject: [PATCH 113/809] nrf5/drivers: Adding ILI9341 class to the display global dict. --- nrf5/drivers/display/moddisplay.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/display/moddisplay.c b/nrf5/drivers/display/moddisplay.c index 2de89bb967..ee9dcfec1c 100644 --- a/nrf5/drivers/display/moddisplay.c +++ b/nrf5/drivers/display/moddisplay.c @@ -29,14 +29,17 @@ #if MICROPY_PY_DISPLAY #include "epaper_sld00200p_obj.h" +#include "lcd_ili9341_obj.h" STATIC const mp_map_elem_t mp_module_display_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_display) }, #if MICROPY_PY_DISPLAY_EPAPER_SLD00200P - { MP_OBJ_NEW_QSTR(MP_QSTR_SLD00200P), (mp_obj_t)&epaper_sld00200p_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SLD00200P), (mp_obj_t)&epaper_sld00200p_type }, +#endif +#if MICROPY_PY_DISPLAY_LCD_ILI9341 + { MP_OBJ_NEW_QSTR(MP_QSTR_ILI9341), (mp_obj_t)&lcd_ili9341_type }, #endif #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_SLD10261P), (mp_obj_t)&lcd_sld10261p_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1289), (mp_obj_t)&lcd_ssd1289_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_LS027b7DH01), (mp_obj_t)&lcd_ls027b7dh01_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1305), (mp_obj_t)&oled_ssd1305_type }, From 5079cb0a25b566f5211a5e8c8d9c7c0c2268e581 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 20:13:51 +0100 Subject: [PATCH 114/809] nrf5/drivers: Adding lcd ili9341 object implementation to make a new instance. print implemented for debugging pins assigned to the display driver. No interaction yet with the hal driver. --- nrf5/drivers/display/lcd_ili9341_obj.c | 282 +++++++++++++++++++++++++ nrf5/drivers/display/lcd_ili9341_obj.h | 35 +++ 2 files changed, 317 insertions(+) create mode 100644 nrf5/drivers/display/lcd_ili9341_obj.c create mode 100644 nrf5/drivers/display/lcd_ili9341_obj.h diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/drivers/display/lcd_ili9341_obj.c new file mode 100644 index 0000000000..ca7d2b066b --- /dev/null +++ b/nrf5/drivers/display/lcd_ili9341_obj.c @@ -0,0 +1,282 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "py/obj.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "genhdr/pins.h" + +// For now PWM is only enabled for nrf52 targets. +#if MICROPY_PY_DISPLAY_LCD_ILI9341 + +/// \moduleref display +/// \class ILI9341 - ILI9341 TFT LCD display driver. + +#include "pin.h" +#include "spi.h" +#include "lcd_mono_fb.h" + +typedef struct _lcd_ili9341_obj_t { + mp_obj_base_t base; + machine_hard_spi_obj_t *spi; + pin_obj_t * pin_cs; + pin_obj_t * pin_dc; + mp_obj_framebuf_t * framebuffer; +} lcd_ili9341_obj_t; + +/// \method __str__() +/// Return a string describing the ILI9341 object. +STATIC void lcd_ili9341_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + lcd_ili9341_obj_t *self = o; + + mp_printf(print, "ILI9341(SPI(mosi=%u, miso=%u, clk=%u),\n", + self->spi->pyb->spi->init.mosi_pin, + self->spi->pyb->spi->init.miso_pin, + self->spi->pyb->spi->init.clk_pin); + + mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u),\n", + self->pin_cs->port, + self->pin_cs->pin, + self->pin_dc->port, + self->pin_dc->pin); + + mp_printf(print, " FB(width=%u, height=%u, dir=%u\n", + self->framebuffer->width, + self->framebuffer->height); +} + +// for make_new +enum { + ARG_NEW_WIDTH, + ARG_NEW_HEIGHT, + ARG_NEW_SPI, + ARG_NEW_CS, + ARG_NEW_DC, +}; + +/* +from machine import Pin, SPI +from display import ILI9341 +cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) +dc = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0) +d = ILI9341(320, 240, spi, cs, dc) +*/ +STATIC mp_obj_t lcd_ili9341_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_DC, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + lcd_ili9341_obj_t *s = m_new_obj_with_finaliser(lcd_ili9341_obj_t); + s->base.type = type; + + mp_int_t width; + mp_int_t height; + + if (args[ARG_NEW_WIDTH].u_int > 0) { + width = args[ARG_NEW_WIDTH].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display width not set")); + } + + if (args[ARG_NEW_HEIGHT].u_int > 0) { + height = args[ARG_NEW_HEIGHT].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display height not set")); + } + + if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { + s->spi = args[ARG_NEW_SPI].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display SPI not set")); + } + + if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { + s->pin_cs = args[ARG_NEW_CS].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display CS Pin not set")); + } + + if (args[ARG_NEW_DC].u_obj != MP_OBJ_NULL) { + s->pin_dc = args[ARG_NEW_DC].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display DC Pin not set")); + } + + // direction arg not yet configurable + mp_int_t vertical = true; + printf("Initializing framebuffer\n"); + s->framebuffer = lcd_mono_fb_helper_make_new(width, height, vertical); + printf("DONE: Initializing framebuffer\n"); + return MP_OBJ_FROM_PTR(s); +} + +// text + +/// \method fill(color) +/// Fill framebuffer with the color defined as argument. +STATIC mp_obj_t lcd_ili9341_fill(mp_obj_t self_in, mp_obj_t color) { + lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(self_in); + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_ili9341_fill_obj, lcd_ili9341_fill); + +/// \method show([num_of_refresh]) +/// Display content in framebuffer. +/// +/// - With no argument, no refresh is done. +/// - With `num_of_refresh` given, the lines touched by previous update +/// will be refreshed the given number of times. If no lines have been +/// touched, no update will be performed. To force a refresh, call the +/// refresh() method explicitly. +STATIC mp_obj_t lcd_ili9341_show(size_t n_args, const mp_obj_t *args) { + lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t num_of_refresh = 0; + + if (n_args > 1) { + num_of_refresh = mp_obj_get_int(args[1]); + } + + (void)num_of_refresh; + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ili9341_show_obj, 1, 2, lcd_ili9341_show); + +/// \method refresh([num_of_refresh]) +/// Refresh content in framebuffer. +/// +/// - With no argument, 1 refresh will be done. +/// - With `num_of_refresh` given, The whole framebuffer will be considered +/// dirty and will be refreshed the given number of times. +STATIC mp_obj_t lcd_ili9341_refresh(mp_obj_t self_in) { + lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ili9341_refresh_obj, lcd_ili9341_refresh); + +/// \method pixel(x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color of the pixel in framebuffer will be returend. +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t lcd_ili9341_pixel(size_t n_args, const mp_obj_t *args) { + lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t x = mp_obj_get_int(args[1]); + mp_int_t y = mp_obj_get_int(args[2]); + mp_int_t color; + if (n_args >= 3) { + color = mp_obj_get_int(args[3]); + } + (void)self; + (void)x; + (void)y; + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ili9341_pixel_obj, 3, 4, lcd_ili9341_pixel); + +/// \method pixel(text, x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color will be the opposite of background (fill color). +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t lcd_ili9341_text(size_t n_args, const mp_obj_t *args) { + lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(args[0]); + const char *str = mp_obj_str_get_str(args[1]); + mp_int_t x = mp_obj_get_int(args[2]); + mp_int_t y = mp_obj_get_int(args[3]); + mp_int_t color; + if (n_args >= 4) { + color = mp_obj_get_int(args[3]); + } + (void)self; + (void)str; + (void)x; + (void)y; + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ili9341_text_obj, 4, 5, lcd_ili9341_text); + +STATIC mp_obj_t lcd_ili9341_del(mp_obj_t self_in) { + lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ili9341_del_obj, lcd_ili9341_del); + +STATIC const mp_map_elem_t lcd_ili9341_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&lcd_ili9341_del_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&lcd_ili9341_fill_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&lcd_ili9341_show_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&lcd_ili9341_text_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&lcd_ili9341_pixel_obj) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&lcd_ili9341_bitmap_obj) }, +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_BLACK) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_WHITE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, +}; + +STATIC MP_DEFINE_CONST_DICT(lcd_ili9341_locals_dict, lcd_ili9341_locals_dict_table); + +const mp_obj_type_t lcd_ili9341_type = { + { &mp_type_type }, + .name = MP_QSTR_ILI9341, + .print = lcd_ili9341_print, + .make_new = lcd_ili9341_make_new, + .locals_dict = (mp_obj_t)&lcd_ili9341_locals_dict +}; + +#endif // MICROPY_PY_DISPLAY_LCD_ILI9341 diff --git a/nrf5/drivers/display/lcd_ili9341_obj.h b/nrf5/drivers/display/lcd_ili9341_obj.h new file mode 100644 index 0000000000..097b7eb698 --- /dev/null +++ b/nrf5/drivers/display/lcd_ili9341_obj.h @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LCD_ILI9341_H__ +#define LCD_ILI9341_H__ + +#include + +extern const mp_obj_type_t lcd_ili9341_type; + +#endif // LCD_ILI9341_H__ + From a62573ad41d24f2feb68a61e11ce4cae249c770f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 20:15:23 +0100 Subject: [PATCH 115/809] nrf5/drivers: Adding template files for upcomming ili9341 driver. --- nrf5/drivers/display/lcd_ili9341_driver.c | 33 +++++++++++++++++++++++ nrf5/drivers/display/lcd_ili9341_driver.h | 30 +++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 nrf5/drivers/display/lcd_ili9341_driver.c create mode 100644 nrf5/drivers/display/lcd_ili9341_driver.h diff --git a/nrf5/drivers/display/lcd_ili9341_driver.c b/nrf5/drivers/display/lcd_ili9341_driver.c new file mode 100644 index 0000000000..7bdc0a8405 --- /dev/null +++ b/nrf5/drivers/display/lcd_ili9341_driver.c @@ -0,0 +1,33 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "lcd_ili9341_driver.h" + +#if MICROPY_PY_DISPLAY_LCD_ILI9341 + + + +#endif diff --git a/nrf5/drivers/display/lcd_ili9341_driver.h b/nrf5/drivers/display/lcd_ili9341_driver.h new file mode 100644 index 0000000000..ce0cbcc316 --- /dev/null +++ b/nrf5/drivers/display/lcd_ili9341_driver.h @@ -0,0 +1,30 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LCD_ILI9341_DRIVER_H__ +#define LCD_ILI9341_DRIVER_H__ + +#endif // LCD_ILI9341_DRIVER_H__ From a8dc8cb23634566b69ebe3488cf58af2beec9467 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 20:16:24 +0100 Subject: [PATCH 116/809] nrf5: Adding ili9341 class and driver files in Makefile to be included in build. --- nrf5/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 88e35012a9..c8d852f6ad 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -152,6 +152,8 @@ DRIVERS_SRC_C += $(addprefix drivers/,\ display/moddisplay.c \ display/epaper_sld00200p_obj.c \ display/epaper_sld00200p_driver.c \ + display/lcd_ili9341_obj.c \ + display/lcd_ili9341_driver.c \ ) #ifeq ($(SD), ) From 042e3653cfd7a7b056284af99fee88df727d80dd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 21:56:17 +0100 Subject: [PATCH 117/809] nrf5/hal: Adding support for NULL pointer to be set if no rx buffer is of interest in SPI rx_tx function. --- nrf5/hal/hal_spi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c index 652df524eb..1ab7623943 100644 --- a/nrf5/hal/hal_spi.c +++ b/nrf5/hal/hal_spi.c @@ -101,9 +101,15 @@ void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, con while (p_instance->EVENTS_READY == 0) { ; } + p_instance->EVENTS_READY = 0; - rx_data[number_of_txd_bytes] = (uint8_t)p_instance->RXD; + uint8_t in_byte = (uint8_t)p_instance->RXD; + + if (rx_data != NULL) { + rx_data[number_of_txd_bytes] = in_byte; + } + number_of_txd_bytes++; }; } From 62c3f9c1e32d82430fb0e44ee197e0ceb4ccd745 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 5 Jan 2017 21:57:59 +0100 Subject: [PATCH 118/809] nrf5/drivers: Adding preliminary file for ili9341 lcd driver. --- nrf5/drivers/display/lcd_ili9341_driver.c | 195 ++++++++++++++++++++++ nrf5/drivers/display/lcd_ili9341_driver.h | 6 + nrf5/drivers/display/lcd_ili9341_obj.c | 5 + 3 files changed, 206 insertions(+) diff --git a/nrf5/drivers/display/lcd_ili9341_driver.c b/nrf5/drivers/display/lcd_ili9341_driver.c index 7bdc0a8405..bd232a34a2 100644 --- a/nrf5/drivers/display/lcd_ili9341_driver.c +++ b/nrf5/drivers/display/lcd_ili9341_driver.c @@ -24,10 +24,205 @@ * THE SOFTWARE. */ +#include "py/mphal.h" + #include "lcd_ili9341_driver.h" +#include "hal_spi.h" +#include "hal_time.h" #if MICROPY_PY_DISPLAY_LCD_ILI9341 +static pin_obj_t * mp_cs_pin; +static pin_obj_t * mp_dc_pin; +static NRF_SPI_Type * mp_instance; +static void raw_write(uint8_t value) +{ + hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); +} + +static void cmd_write(uint8_t value) +{ + mp_hal_pin_low(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); + + mp_hal_pin_low(mp_cs_pin); +} + +static void data_write(uint8_t value) +{ + mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); + + mp_hal_pin_low(mp_cs_pin); +} + +void driver_ili9341_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_obj_t * p_dc_pin) +{ + mp_instance = p_instance; + mp_cs_pin = p_cs_pin; + mp_dc_pin = p_dc_pin; + + // mp_hal_pin_high(enable_pin); + // mp_hal_pin_high(backlight_pin); + mp_hal_pin_high(mp_cs_pin); + mp_hal_pin_high(mp_dc_pin); + + // Read driver id + + mp_hal_delay_ms(500); + + cmd_write(0x01); + + mp_hal_delay_ms(200); + + cmd_write(0xCF); + data_write(0x00); + data_write(0x8B); + data_write(0X30); + + cmd_write(0xED); + data_write(0x67); + data_write(0x03); + data_write(0X12); + data_write(0X81); + + cmd_write(0xE8); + data_write(0x85); + data_write(0x10); + data_write(0x7A); + + cmd_write(0xCB); + data_write(0x39); + data_write(0x2C); + data_write(0x00); + data_write(0x34); + data_write(0x02); + + cmd_write(0xF7); + data_write(0x20); + + cmd_write(0xEA); + data_write(0x00); + data_write(0x00); + + cmd_write(0xC0); /* Power control */ + data_write(0x1B); /* VRH[5:0] */ + + cmd_write(0xC1); /* Power control */ + data_write(0x10); /* SAP[2:0];BT[3:0] */ + + cmd_write(0xC5); /* VCM control */ + data_write(0x3F); + data_write(0x3C); + + cmd_write(0xC7); /* VCM control2 */ + data_write(0XB7); + + cmd_write(0x36); /* Memory Access Control */ + data_write(0x08); + + cmd_write(0x3A); + data_write(0x55); + + cmd_write(0xB1); + data_write(0x00); + data_write(0x1B); + + cmd_write(0xB6); /* Display Function Control */ + data_write(0x0A); + data_write(0xA2); + + cmd_write(0xF2); /* 3Gamma Function Disable */ + data_write(0x00); + + cmd_write(0x26); /* Gamma curve selected */ + data_write(0x01); + + cmd_write(0xE0); /* Set Gamma */ + data_write(0x0F); + data_write(0x2A); + data_write(0x28); + data_write(0x08); + data_write(0x0E); + data_write(0x08); + data_write(0x54); + data_write(0XA9); + data_write(0x43); + data_write(0x0A); + data_write(0x0F); + data_write(0x00); + data_write(0x00); + data_write(0x00); + data_write(0x00); + + cmd_write(0XE1); /* Set Gamma */ + data_write(0x00); + data_write(0x15); + data_write(0x17); + data_write(0x07); + data_write(0x11); + data_write(0x06); + data_write(0x2B); + data_write(0x56); + data_write(0x3C); + data_write(0x05); + data_write(0x10); + data_write(0x0F); + data_write(0x3F); + data_write(0x3F); + data_write(0x0F); + + cmd_write(0x11); /* Exit Sleep */ + + mp_hal_delay_ms(120); + + cmd_write(0x29); /* Display on */ +} + +static void set_col(uint16_t start_col, uint16_t end_col) +{ + cmd_write(0x2A); /* Column Command address */ + data_write(start_col >> 8); + data_write(start_col & 0xFF ); + data_write(end_col >> 8); + data_write(end_col & 0xFF); +} + +static void set_page(uint16_t start_page, uint16_t end_page) +{ + cmd_write(0x2B); /* Column Command address */ + data_write(start_page >> 8); + data_write(start_page & 0xFF); + data_write(end_page >> 8); + data_write(end_page & 0xFF); +} + +void driver_ili9341_clear(uint16_t color) +{ + set_col(0, 239); + set_page(0, 319); + + cmd_write(0x2c); // start writing to the display ram + + mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + for(uint16_t i = 0; i < 38400; i++) + { + raw_write(color >> 10); + raw_write((color >> 6) & 0xFF ); + raw_write(color & 0xFF); + raw_write(0); + } + + mp_hal_pin_high(mp_cs_pin); + +} + #endif diff --git a/nrf5/drivers/display/lcd_ili9341_driver.h b/nrf5/drivers/display/lcd_ili9341_driver.h index ce0cbcc316..c81592daa6 100644 --- a/nrf5/drivers/display/lcd_ili9341_driver.h +++ b/nrf5/drivers/display/lcd_ili9341_driver.h @@ -27,4 +27,10 @@ #ifndef LCD_ILI9341_DRIVER_H__ #define LCD_ILI9341_DRIVER_H__ +#include "hal_spi.h" + +void driver_ili9341_init(NRF_SPI_Type * p_instance, pin_obj_t * cs_pin, pin_obj_t * dc_pin); + +void driver_ili9341_clear(uint16_t color); + #endif // LCD_ILI9341_DRIVER_H__ diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/drivers/display/lcd_ili9341_obj.c index ca7d2b066b..222442d17b 100644 --- a/nrf5/drivers/display/lcd_ili9341_obj.c +++ b/nrf5/drivers/display/lcd_ili9341_obj.c @@ -31,6 +31,7 @@ #include "py/mphal.h" #include "genhdr/pins.h" +#include "lcd_ili9341_driver.h" // For now PWM is only enabled for nrf52 targets. #if MICROPY_PY_DISPLAY_LCD_ILI9341 @@ -157,6 +158,8 @@ STATIC mp_obj_t lcd_ili9341_fill(mp_obj_t self_in, mp_obj_t color) { lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(self_in); (void)self; + driver_ili9341_clear(mp_obj_get_int(color)); + return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_ili9341_fill_obj, lcd_ili9341_fill); @@ -177,6 +180,8 @@ STATIC mp_obj_t lcd_ili9341_show(size_t n_args, const mp_obj_t *args) { num_of_refresh = mp_obj_get_int(args[1]); } + driver_ili9341_init(self->spi->pyb->spi->instance, self->pin_cs, self->pin_dc); + (void)num_of_refresh; (void)self; From 795df06283c1810d5c61596ee5944a2bdc3f0a21 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 6 Jan 2017 19:59:58 +0100 Subject: [PATCH 119/809] nrf5/hal: Adding include of stdbool.h in hal_spi.h as it is used by the header. --- nrf5/hal/hal_spi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/hal/hal_spi.h b/nrf5/hal/hal_spi.h index cdcbd9248c..ba85328ae6 100644 --- a/nrf5/hal/hal_spi.h +++ b/nrf5/hal/hal_spi.h @@ -27,6 +27,7 @@ #ifndef HAL_SPI_H__ #define HAL_SPI_H__ +#include #include "nrf.h" #if NRF51 From f92e581e13ae2501fc5fafb6270ec46243c30e5a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 6 Jan 2017 20:06:09 +0100 Subject: [PATCH 120/809] nrf5: Started to split up lcd_mono_fb such that it can be used as a c-library and python module with the same implementaton. --- nrf5/lcd_mono_fb.c | 66 ++++++++++++++++++++++++++-------------------- nrf5/lcd_mono_fb.h | 17 ++++++++++++ 2 files changed, 54 insertions(+), 29 deletions(-) diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c index 4e11b9a81f..2ce900e6e8 100644 --- a/nrf5/lcd_mono_fb.c +++ b/nrf5/lcd_mono_fb.c @@ -83,7 +83,11 @@ STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * p_framebuffer) { } #endif -STATIC void lcd_clear_screen(mp_obj_framebuf_t * p_framebuffer) { +void display_clear_screen(mp_obj_framebuf_t * p_framebuffer, uint8_t color) { + + lcd_bg_color_set(p_framebuffer, color); + lcd_fg_color_set(p_framebuffer, !color); + if (p_framebuffer->bg_color == LCD_BLACK) { memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); } else { @@ -142,7 +146,7 @@ STATIC uint8_t lcd_font_size_get(mp_obj_framebuf_t * p_framebuffer) { } #endif -STATIC void lcd_print_string(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, const char * p_str) { +void display_print_string(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, const char * p_str) { uint16_t str_len = strlen(p_str); for (uint16_t i = 0; i < str_len; i++) { lcd_print_char(p_framebuffer, x + (i * 8 * p_framebuffer->font_size), y, p_str[i]); @@ -157,31 +161,42 @@ STATIC void lcd_pixel_draw(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16 } } -STATIC void lcd_update(mp_obj_framebuf_t * p_framebuffer, bool refresh) { +void display_update(mp_obj_framebuf_t * p_framebuffer, bool refresh, lcd_update_line_callback_t c_callback) { for (uint16_t i = 0; i < p_framebuffer->dirty_stride; i++) { if (p_framebuffer->fb_dirty[i].byte != 0 || refresh) { for (uint16_t b = 0; b < 8; b++) { if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) || refresh) { uint16_t line_num = (i * 8) + b; - mp_obj_t args[4]; - mp_uint_t num_of_args = 3; - args[0] = p_framebuffer; - args[1] = MP_OBJ_NEW_SMALL_INT(line_num); - if (refresh == false) { - args[2] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, - &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); + if (c_callback != NULL) + { + if (p_framebuffer->fb_old == NULL) { + c_callback(p_framebuffer, + line_num, + &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride], + NULL); + } } else { - args[2] = mp_const_none; - } + mp_obj_t args[4]; + mp_uint_t num_of_args = 3; + args[0] = p_framebuffer; + args[1] = MP_OBJ_NEW_SMALL_INT(line_num); - if (p_framebuffer->fb_old != NULL) { - args[3] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, - &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); - num_of_args = 4; - } + if (refresh == false) { + args[2] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, + &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); + } else { + args[2] = mp_const_none; + } - mp_call_function_n_kw(p_framebuffer->line_update_cb, num_of_args, 0, args); + if (p_framebuffer->fb_old != NULL) { + args[3] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, + &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); + num_of_args = 4; + } + + mp_call_function_n_kw(p_framebuffer->line_update_cb, num_of_args, 0, args); + } // update old buffer if (p_framebuffer->fb_old != NULL) { @@ -218,10 +233,6 @@ mp_obj_t lcd_mono_fb_helper_make_new(mp_int_t width, mp_int_t height, mp_int_t v o->font_size = 1; - if (vertical) { - o->fb_old = m_new(fb_byte_t, (o->bytes_stride) * o->height); - } - lcd_init(o); return MP_OBJ_FROM_PTR(o); @@ -264,10 +275,7 @@ STATIC mp_obj_t lcd_mono_fb_fill(mp_obj_t self_in, mp_obj_t col_in) { mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); mp_int_t col = mp_obj_get_int(col_in); - lcd_bg_color_set(self, col); - lcd_fg_color_set(self, !col); - - lcd_clear_screen(self); + display_clear_screen(self, col); return mp_const_none; } @@ -302,7 +310,7 @@ STATIC mp_obj_t lcd_mono_fb_text(size_t n_args, const mp_obj_t *args) { mp_int_t x0 = mp_obj_get_int(args[2]); mp_int_t y0 = mp_obj_get_int(args[3]); - lcd_print_string(self, x0, y0, str); + display_print_string(self, x0, y0, str); return mp_const_none; } @@ -312,7 +320,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_mono_fb_text_obj, 4, 5, lcd_mono_ STATIC mp_obj_t lcd_mono_fb_show(mp_obj_t self_in) { mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); - lcd_update(self, false); + display_update(self, false, NULL); return mp_const_none; } @@ -321,7 +329,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_show_obj, lcd_mono_fb_show); STATIC mp_obj_t lcd_mono_fb_refresh(mp_obj_t self_in) { mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); - lcd_update(self, true); + display_update(self, true, NULL); return mp_const_none; } diff --git a/nrf5/lcd_mono_fb.h b/nrf5/lcd_mono_fb.h index 85f85a92db..8ab748a58e 100644 --- a/nrf5/lcd_mono_fb.h +++ b/nrf5/lcd_mono_fb.h @@ -67,8 +67,25 @@ typedef struct { mp_uint_t font_size; } mp_obj_framebuf_t; + +typedef void (*lcd_update_line_callback_t)(mp_obj_framebuf_t * p_framebuffer, + uint16_t line, + fb_byte_t * p_new, + fb_byte_t * p_old); + // Functions for other drivers to use to create framebuffer instances using c. mp_obj_t lcd_mono_fb_helper_make_new(mp_int_t width, mp_int_t height, mp_int_t direction); +void display_clear_screen(mp_obj_framebuf_t * p_framebuffer, uint8_t color); + +void display_update(mp_obj_framebuf_t * p_framebuffer, + bool refresh, + lcd_update_line_callback_t c_callback); + +void display_print_string(mp_obj_framebuf_t * p_framebuffer, + uint16_t x, + uint16_t y, + const char * p_str); + #endif From 67683722c8dbe7de71af67bcf2273d0d70efeaea Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 6 Jan 2017 20:18:00 +0100 Subject: [PATCH 121/809] nrf5/drivers: Updating a working version of ili9341 module and driver. About 10 times faster than python implementation to update a full screen. --- nrf5/drivers/display/lcd_ili9341_driver.c | 258 ++++++++++++---------- nrf5/drivers/display/lcd_ili9341_driver.h | 5 + nrf5/drivers/display/lcd_ili9341_obj.c | 53 ++--- 3 files changed, 175 insertions(+), 141 deletions(-) diff --git a/nrf5/drivers/display/lcd_ili9341_driver.c b/nrf5/drivers/display/lcd_ili9341_driver.c index bd232a34a2..5201b5d3a0 100644 --- a/nrf5/drivers/display/lcd_ili9341_driver.c +++ b/nrf5/drivers/display/lcd_ili9341_driver.c @@ -39,7 +39,7 @@ static NRF_SPI_Type * mp_instance; static void raw_write(uint8_t value) { - hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); + hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); } static void cmd_write(uint8_t value) @@ -64,165 +64,193 @@ static void data_write(uint8_t value) void driver_ili9341_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_obj_t * p_dc_pin) { - mp_instance = p_instance; - mp_cs_pin = p_cs_pin; - mp_dc_pin = p_dc_pin; + mp_instance = p_instance; + mp_cs_pin = p_cs_pin; + mp_dc_pin = p_dc_pin; +#if 0 + mp_hal_pin_high(enable_pin); + mp_hal_pin_high(backlight_pin); +#endif - // mp_hal_pin_high(enable_pin); - // mp_hal_pin_high(backlight_pin); - mp_hal_pin_high(mp_cs_pin); - mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_high(mp_cs_pin); + mp_hal_pin_high(mp_dc_pin); - // Read driver id + // Read driver id - mp_hal_delay_ms(500); + mp_hal_delay_ms(500); - cmd_write(0x01); + cmd_write(0x01); - mp_hal_delay_ms(200); + mp_hal_delay_ms(200); - cmd_write(0xCF); - data_write(0x00); - data_write(0x8B); - data_write(0X30); + cmd_write(0xCF); + data_write(0x00); + data_write(0x8B); + data_write(0X30); - cmd_write(0xED); - data_write(0x67); - data_write(0x03); - data_write(0X12); - data_write(0X81); + cmd_write(0xED); + data_write(0x67); + data_write(0x03); + data_write(0X12); + data_write(0X81); - cmd_write(0xE8); - data_write(0x85); - data_write(0x10); - data_write(0x7A); + cmd_write(0xE8); + data_write(0x85); + data_write(0x10); + data_write(0x7A); - cmd_write(0xCB); - data_write(0x39); - data_write(0x2C); - data_write(0x00); - data_write(0x34); - data_write(0x02); + cmd_write(0xCB); + data_write(0x39); + data_write(0x2C); + data_write(0x00); + data_write(0x34); + data_write(0x02); - cmd_write(0xF7); - data_write(0x20); + cmd_write(0xF7); + data_write(0x20); - cmd_write(0xEA); - data_write(0x00); - data_write(0x00); + cmd_write(0xEA); + data_write(0x00); + data_write(0x00); - cmd_write(0xC0); /* Power control */ - data_write(0x1B); /* VRH[5:0] */ + cmd_write(0xC0); /* Power control */ + data_write(0x1B); /* VRH[5:0] */ - cmd_write(0xC1); /* Power control */ - data_write(0x10); /* SAP[2:0];BT[3:0] */ + cmd_write(0xC1); /* Power control */ + data_write(0x10); /* SAP[2:0];BT[3:0] */ - cmd_write(0xC5); /* VCM control */ - data_write(0x3F); - data_write(0x3C); + cmd_write(0xC5); /* VCM control */ + data_write(0x3F); + data_write(0x3C); - cmd_write(0xC7); /* VCM control2 */ - data_write(0XB7); + cmd_write(0xC7); /* VCM control2 */ + data_write(0XB7); - cmd_write(0x36); /* Memory Access Control */ - data_write(0x08); + cmd_write(0x36); /* Memory Access Control */ + data_write(0x08); - cmd_write(0x3A); - data_write(0x55); + cmd_write(0x3A); + data_write(0x55); - cmd_write(0xB1); - data_write(0x00); - data_write(0x1B); + cmd_write(0xB1); + data_write(0x00); + data_write(0x1B); - cmd_write(0xB6); /* Display Function Control */ - data_write(0x0A); - data_write(0xA2); + cmd_write(0xB6); /* Display Function Control */ + data_write(0x0A); + data_write(0xA2); - cmd_write(0xF2); /* 3Gamma Function Disable */ - data_write(0x00); + cmd_write(0xF2); /* 3Gamma Function Disable */ + data_write(0x00); - cmd_write(0x26); /* Gamma curve selected */ - data_write(0x01); + cmd_write(0x26); /* Gamma curve selected */ + data_write(0x01); - cmd_write(0xE0); /* Set Gamma */ - data_write(0x0F); - data_write(0x2A); - data_write(0x28); - data_write(0x08); - data_write(0x0E); - data_write(0x08); - data_write(0x54); - data_write(0XA9); - data_write(0x43); - data_write(0x0A); - data_write(0x0F); - data_write(0x00); - data_write(0x00); - data_write(0x00); - data_write(0x00); + cmd_write(0xE0); /* Set Gamma */ + data_write(0x0F); + data_write(0x2A); + data_write(0x28); + data_write(0x08); + data_write(0x0E); + data_write(0x08); + data_write(0x54); + data_write(0XA9); + data_write(0x43); + data_write(0x0A); + data_write(0x0F); + data_write(0x00); + data_write(0x00); + data_write(0x00); + data_write(0x00); - cmd_write(0XE1); /* Set Gamma */ - data_write(0x00); - data_write(0x15); - data_write(0x17); - data_write(0x07); - data_write(0x11); - data_write(0x06); - data_write(0x2B); - data_write(0x56); - data_write(0x3C); - data_write(0x05); - data_write(0x10); - data_write(0x0F); - data_write(0x3F); - data_write(0x3F); - data_write(0x0F); + cmd_write(0XE1); /* Set Gamma */ + data_write(0x00); + data_write(0x15); + data_write(0x17); + data_write(0x07); + data_write(0x11); + data_write(0x06); + data_write(0x2B); + data_write(0x56); + data_write(0x3C); + data_write(0x05); + data_write(0x10); + data_write(0x0F); + data_write(0x3F); + data_write(0x3F); + data_write(0x0F); - cmd_write(0x11); /* Exit Sleep */ + cmd_write(0x11); /* Exit Sleep */ - mp_hal_delay_ms(120); + mp_hal_delay_ms(120); - cmd_write(0x29); /* Display on */ + cmd_write(0x29); /* Display on */ } static void set_col(uint16_t start_col, uint16_t end_col) { - cmd_write(0x2A); /* Column Command address */ - data_write(start_col >> 8); - data_write(start_col & 0xFF ); - data_write(end_col >> 8); - data_write(end_col & 0xFF); + cmd_write(0x2A); /* Column Command address */ + data_write(start_col >> 8); + data_write(start_col & 0xFF ); + data_write(end_col >> 8); + data_write(end_col & 0xFF); } static void set_page(uint16_t start_page, uint16_t end_page) { - cmd_write(0x2B); /* Column Command address */ - data_write(start_page >> 8); - data_write(start_page & 0xFF); - data_write(end_page >> 8); - data_write(end_page & 0xFF); + cmd_write(0x2B); /* Column Command address */ + data_write(start_page >> 8); + data_write(start_page & 0xFF); + data_write(end_page >> 8); + data_write(end_page & 0xFF); } void driver_ili9341_clear(uint16_t color) { - set_col(0, 239); - set_page(0, 319); + set_col(0, 239); + set_page(0, 319); - cmd_write(0x2c); // start writing to the display ram + cmd_write(0x2c); // start writing to the display ram mp_hal_pin_high(mp_dc_pin); mp_hal_pin_low(mp_cs_pin); - for(uint16_t i = 0; i < 38400; i++) - { - raw_write(color >> 10); - raw_write((color >> 6) & 0xFF ); - raw_write(color & 0xFF); - raw_write(0); - } + for(uint16_t i = 0; i < 38400; i++) + { + raw_write(color >> 8); + raw_write(color & 0xFF); + raw_write(color >> 8); + raw_write(color & 0xFF); + } - mp_hal_pin_high(mp_cs_pin); + mp_hal_pin_high(mp_cs_pin); +} +void driver_ili9341_update_line(uint16_t line, fb_byte_t * p_bytes, uint16_t len, bool compressed) { + set_col(0, 239); + set_page(line, line); + + cmd_write(0x2c); + + mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + if (compressed == true) { + for (uint16_t i = 0; i < len; i++) { + for (uint8_t pixel_pos = 0; pixel_pos < 8; pixel_pos++) { + uint8_t byte = (uint8_t)((uint8_t * )p_bytes)[i]; + if (((byte >> pixel_pos) & 0x1) == 0x0) { + data_write(0x00); + data_write(0x00); + } else { + data_write(0xFF); + data_write(0xFF); + } + } + } + } + + mp_hal_pin_high(mp_cs_pin); } #endif diff --git a/nrf5/drivers/display/lcd_ili9341_driver.h b/nrf5/drivers/display/lcd_ili9341_driver.h index c81592daa6..b420ae97ab 100644 --- a/nrf5/drivers/display/lcd_ili9341_driver.h +++ b/nrf5/drivers/display/lcd_ili9341_driver.h @@ -27,10 +27,15 @@ #ifndef LCD_ILI9341_DRIVER_H__ #define LCD_ILI9341_DRIVER_H__ +#include "py/mphal.h" + #include "hal_spi.h" +#include "lcd_mono_fb.h" void driver_ili9341_init(NRF_SPI_Type * p_instance, pin_obj_t * cs_pin, pin_obj_t * dc_pin); void driver_ili9341_clear(uint16_t color); +void driver_ili9341_update_line(uint16_t line, fb_byte_t * p_bytes, uint16_t len, bool compressed); + #endif // LCD_ILI9341_DRIVER_H__ diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/drivers/display/lcd_ili9341_obj.c index 222442d17b..0453d72096 100644 --- a/nrf5/drivers/display/lcd_ili9341_obj.c +++ b/nrf5/drivers/display/lcd_ili9341_obj.c @@ -50,6 +50,16 @@ typedef struct _lcd_ili9341_obj_t { mp_obj_framebuf_t * framebuffer; } lcd_ili9341_obj_t; +static void dirty_line_update_cb(mp_obj_framebuf_t * p_framebuffer, + uint16_t line, + fb_byte_t * p_new, + fb_byte_t * p_old) { + // the lcd does not have double buffer needs, skip it. + (void)p_old; + + driver_ili9341_update_line(line, p_new, p_framebuffer->bytes_stride, true); +} + /// \method __str__() /// Return a string describing the ILI9341 object. STATIC void lcd_ili9341_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { @@ -85,8 +95,10 @@ from machine import Pin, SPI from display import ILI9341 cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) dc = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0) -d = ILI9341(320, 240, spi, cs, dc) +spi = SPI(0, baudrate=8000000) +d = ILI9341(240, 320, spi, cs, dc) +d.text("Hello World!", 32, 32) +d.show() */ STATIC mp_obj_t lcd_ili9341_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { @@ -144,9 +156,14 @@ STATIC mp_obj_t lcd_ili9341_make_new(const mp_obj_type_t *type, size_t n_args, s // direction arg not yet configurable mp_int_t vertical = true; - printf("Initializing framebuffer\n"); s->framebuffer = lcd_mono_fb_helper_make_new(width, height, vertical); - printf("DONE: Initializing framebuffer\n"); + + driver_ili9341_init(s->spi->pyb->spi->instance, s->pin_cs, s->pin_dc); + // Default to white background + driver_ili9341_clear(0xFFFF); + + display_clear_screen(s->framebuffer, 0x1); + return MP_OBJ_FROM_PTR(s); } @@ -156,34 +173,19 @@ STATIC mp_obj_t lcd_ili9341_make_new(const mp_obj_type_t *type, size_t n_args, s /// Fill framebuffer with the color defined as argument. STATIC mp_obj_t lcd_ili9341_fill(mp_obj_t self_in, mp_obj_t color) { lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(self_in); - (void)self; - driver_ili9341_clear(mp_obj_get_int(color)); + display_clear_screen(self->framebuffer, (uint8_t)mp_obj_get_int(color)); return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_ili9341_fill_obj, lcd_ili9341_fill); -/// \method show([num_of_refresh]) +/// \method show() /// Display content in framebuffer. -/// -/// - With no argument, no refresh is done. -/// - With `num_of_refresh` given, the lines touched by previous update -/// will be refreshed the given number of times. If no lines have been -/// touched, no update will be performed. To force a refresh, call the -/// refresh() method explicitly. STATIC mp_obj_t lcd_ili9341_show(size_t n_args, const mp_obj_t *args) { lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(args[0]); - mp_int_t num_of_refresh = 0; - if (n_args > 1) { - num_of_refresh = mp_obj_get_int(args[1]); - } - - driver_ili9341_init(self->spi->pyb->spi->instance, self->pin_cs, self->pin_dc); - - (void)num_of_refresh; - (void)self; + display_update(self->framebuffer, false, dirty_line_update_cb); return mp_const_none; } @@ -240,10 +242,9 @@ STATIC mp_obj_t lcd_ili9341_text(size_t n_args, const mp_obj_t *args) { if (n_args >= 4) { color = mp_obj_get_int(args[3]); } - (void)self; - (void)str; - (void)x; - (void)y; + + display_print_string(self->framebuffer, x, y, str); + (void)color; return mp_const_none; From ad4149cc80be4b12c5dda00532c425131fbbd137 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 6 Jan 2017 23:40:23 +0100 Subject: [PATCH 122/809] nrf5/pwm: Moving out object types to header file so that it can be resused by other modules. --- nrf5/pwm.c | 10 ---------- nrf5/pwm.h | 12 ++++++++++++ 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/nrf5/pwm.c b/nrf5/pwm.c index b38f3d612f..2f646d2f11 100644 --- a/nrf5/pwm.c +++ b/nrf5/pwm.c @@ -42,11 +42,6 @@ #include "hal_pwm.h" #endif -typedef struct _pyb_pwm_obj_t { - mp_obj_base_t base; - PWM_HandleTypeDef *pwm; -} pyb_pwm_obj_t; - #ifdef MICROPY_HW_PWM0_NAME PWM_HandleTypeDef PWMHandle0 = {.instance = NULL}; #endif @@ -236,11 +231,6 @@ STATIC MP_DEFINE_CONST_DICT(machine_pwm_locals_dict, machine_pwm_locals_dict_tab /* code for hard implementation ***********************************************/ -typedef struct _machine_hard_pwm_obj_t { - mp_obj_base_t base; - const pyb_pwm_obj_t *pyb; -} machine_hard_pwm_obj_t; - STATIC const machine_hard_pwm_obj_t machine_hard_pwm_obj[] = { {{&machine_hard_pwm_type}, &machine_pwm_obj[0]}, }; diff --git a/nrf5/pwm.h b/nrf5/pwm.h index c79668520d..fe4e26c895 100644 --- a/nrf5/pwm.h +++ b/nrf5/pwm.h @@ -24,6 +24,18 @@ * THE SOFTWARE. */ +#include "hal_pwm.h" + +typedef struct _pyb_pwm_obj_t { + mp_obj_base_t base; + PWM_HandleTypeDef *pwm; +} pyb_pwm_obj_t; + +typedef struct _machine_hard_pwm_obj_t { + mp_obj_base_t base; + const pyb_pwm_obj_t *pyb; +} machine_hard_pwm_obj_t; + void pwm_init0(void); extern const mp_obj_type_t machine_hard_pwm_type; From a2e2f3c07ee7cf6d54f758841c9180c25e183387 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 6 Jan 2017 23:41:16 +0100 Subject: [PATCH 123/809] nrf5/drivers: Fixing parenthesis in ILI9341 __str__ print function. --- nrf5/drivers/display/lcd_ili9341_obj.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/drivers/display/lcd_ili9341_obj.c index 0453d72096..1987131efe 100644 --- a/nrf5/drivers/display/lcd_ili9341_obj.c +++ b/nrf5/drivers/display/lcd_ili9341_obj.c @@ -76,7 +76,7 @@ STATIC void lcd_ili9341_print(const mp_print_t *print, mp_obj_t o, mp_print_kind self->pin_dc->port, self->pin_dc->pin); - mp_printf(print, " FB(width=%u, height=%u, dir=%u\n", + mp_printf(print, " FB(width=%u, height=%u, dir=%u))\n", self->framebuffer->width, self->framebuffer->height); } From 9214381671cba7f70c1ab7b36e250019869d2cf2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 7 Jan 2017 00:07:17 +0100 Subject: [PATCH 124/809] nrf5/drivers: Backing up working epaper display (sld00200p shield) driver before refactoring. --- .../drivers/display/epaper_sld00200p_driver.c | 414 ++++++++++++++++++ .../drivers/display/epaper_sld00200p_driver.h | 23 + nrf5/drivers/display/epaper_sld00200p_obj.c | 251 ++++++++++- 3 files changed, 673 insertions(+), 15 deletions(-) diff --git a/nrf5/drivers/display/epaper_sld00200p_driver.c b/nrf5/drivers/display/epaper_sld00200p_driver.c index 3deef46ecd..b4efe726bf 100644 --- a/nrf5/drivers/display/epaper_sld00200p_driver.c +++ b/nrf5/drivers/display/epaper_sld00200p_driver.c @@ -28,6 +28,420 @@ #if MICROPY_PY_DISPLAY_EPAPER_SLD00200P +#include "py/mphal.h" +#include "epaper_sld00200p_driver.h" +#include "hal_spi.h" +#include "hal_time.h" + +#define BYTE_ARRAY(...) ((uint8_t[]){ __VA_ARGS__}) +#define DATA_WRITE(...) (data_write_buffer(BYTE_ARRAY(__VA_ARGS__), sizeof(BYTE_ARRAY(__VA_ARGS__)))) + +static NRF_SPI_Type * mp_spi_instance; +static NRF_PWM_Type * mp_pwm_instance; +static pin_obj_t * mp_pin_cs; +static pin_obj_t * mp_pin_panel_on; +static pin_obj_t * mp_pin_border; +static pin_obj_t * mp_pin_busy; +static pin_obj_t * mp_pin_reset; +static pin_obj_t * mp_pin_discharge; + +#if 0 +static pin_obj_t * mp_pin_temp_sensor; +#endif + +static void wait_for_busy_release(void) { + while (mp_hal_pin_read(mp_pin_busy) == 1) { + ; + } +} + +static void data_write_buffer(uint8_t * p_bytes, uint16_t num_of_bytes) { + mp_hal_pin_low(mp_pin_cs); + + hal_spi_master_tx_rx(mp_spi_instance, num_of_bytes, p_bytes, NULL); + + mp_hal_pin_high(mp_pin_cs); +} + +static void raw_write(uint8_t value) +{ + hal_spi_master_tx_rx(mp_spi_instance, 1, &value, NULL); +} + +void driver_sld00200p_init(NRF_SPI_Type * p_spi_instance, + NRF_PWM_Type * p_pwm_instance, + pin_obj_t * p_pin_cs, + pin_obj_t * p_pin_panel_on, + pin_obj_t * p_pin_border, + pin_obj_t * p_pin_busy, + pin_obj_t * p_pin_reset, + pin_obj_t * p_pin_discharge) { + + mp_spi_instance = p_spi_instance; + mp_pwm_instance = p_pwm_instance; + mp_pin_cs = p_pin_cs; + mp_pin_panel_on = p_pin_panel_on; + mp_pin_border = p_pin_border; + mp_pin_busy = p_pin_busy; + mp_pin_reset = p_pin_reset; + mp_pin_discharge = p_pin_discharge; + + driver_sld00200p_reinit(); +} + +void driver_sld00200p_reinit(void) { + mp_hal_pin_low(mp_pin_reset); + mp_hal_pin_low(mp_pin_panel_on); + mp_hal_pin_low(mp_pin_discharge); + mp_hal_pin_low(mp_pin_border); + + // start the pwm + hal_pwm_start(mp_pwm_instance); + + mp_hal_delay_ms(5); + + mp_hal_pin_high(mp_pin_panel_on); + + mp_hal_delay_ms(10); + + mp_hal_pin_high(mp_pin_reset); + mp_hal_pin_high(mp_pin_border); + mp_hal_pin_high(mp_pin_cs); + + // make reset square wave + mp_hal_delay_ms(5); + mp_hal_pin_low(mp_pin_reset); + mp_hal_delay_ms(5); + mp_hal_pin_high(mp_pin_reset); + mp_hal_delay_ms(5); + + wait_for_busy_release(); + + // channel select + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x01); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xfe, 0x00, 0x00); + + // DC/DC frequency + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x06); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xfe, 0x00, 0x00); + + // high power mode osc + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x07); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x9d); + + // disable ADC + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x08); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x00); + + // Vcom level + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x09); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0xd0, 0x00); + + // gate and source voltage levels + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x04); + + // GS + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x00); + + mp_hal_delay_ms(5); + + // driver latch on + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x03); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x01); + + // driver latch off + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x03); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x00); + + mp_hal_delay_ms(5); + + // charge pump positive voltage on + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x05); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x01); + + // final delay before PWM off + mp_hal_delay_us(30); + + // stop the pwm + hal_pwm_start(mp_pwm_instance); + + // charge pump negative voltage on + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x05); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x03); + + mp_hal_delay_us(30); + + // Vcom driver on + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x05); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x0f); + + mp_hal_delay_ms(30); + + // output enable to disable + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x02); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x24); +} + +void driver_sld00200p_deinit(void) { + epaper_sld00200p_line(0x7fffu, 0, 0x55, EPD_NORM); + mp_hal_delay_ms(25); + mp_hal_pin_low(mp_pin_border); + mp_hal_delay_ms(250); + mp_hal_pin_high(mp_pin_border); + + // latch reset turn on + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x03); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x01); + + // output enable off + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x02); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x05); + + // Vcom power off + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x05); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x0e); + + // power off negative charge pump + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x05); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x02); + + // discharge + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x04); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x0c); + mp_hal_delay_us(120); + + // all charge pumps off + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x05); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x00); + + // turn of osc + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x07); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x0d); + + // discharge internal - 1 + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x04); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x50); + mp_hal_delay_us(40); + + // discharge internal - 2 + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x04); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0xA0); + mp_hal_delay_us(40); + + // discharge internal - 3 + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x04); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x00); + + // turn of power and all signals + mp_hal_delay_ms(10); + mp_hal_pin_low(mp_pin_reset); + mp_hal_pin_low(mp_pin_panel_on); + mp_hal_pin_low(mp_pin_border); + + // discharge pulse + mp_hal_pin_high(mp_pin_discharge); + mp_hal_delay_us(250); + mp_hal_pin_low(mp_pin_discharge); + mp_hal_pin_high(mp_pin_cs); +} + +static void epaper_sld00200p_line(uint16_t line, const uint8_t * data, uint8_t fixed_value, epd_stage_t stage) +{ + mp_hal_delay_ms(10); + + DATA_WRITE(0x70, 0x04); + wait_for_busy_release(); + + // gate source + DATA_WRITE(0x72, 0x00); + wait_for_busy_release(); + + DATA_WRITE(0x70, 0x0a); + wait_for_busy_release(); + + mp_hal_pin_low(mp_pin_cs); + raw_write(0x72); + wait_for_busy_release(); + + uint16_t bytes_per_line = 264 / 8; + + // even pixels + for (uint16_t i = bytes_per_line; i > 0; --i) { + if (data != NULL) { + uint8_t pixels = data[i - 1] & 0xaa; + + switch (stage) { + case EPD_COMP: + // B -> W, W -> B (current image) + pixels = 0xaa | ((pixels ^ 0xaa) >> 1); + break; + + case EPD_WHITE: + // B -> N, W -> W (current image) + pixels = 0x55 + ((pixels ^ 0xaa) >> 1); + break; + + case EPD_INV: + // B -> N, W -> B (new image) + pixels = 0x55 | (pixels ^ 0xaa); + break; + + case EPD_NORM: + // B -> B, W -> W (new image) + pixels = 0xaa | (pixels >> 1); + break; + + default: + break; + } + + raw_write(pixels); + wait_for_busy_release(); + } else { + raw_write(fixed_value); + wait_for_busy_release(); + } + } + + uint16_t bytes_per_scan = 176 / 4; + // scan line + for (uint16_t i = 0; i < bytes_per_scan; i++) { + if (line / 4 == i) { + raw_write(0xc0 >> (2 * (line & 0x03))); + wait_for_busy_release(); + } else { + raw_write(0x00); + wait_for_busy_release(); + } + } + + // odd pixels + for (uint16_t i = 0; i < bytes_per_line; i++) { + if (data != NULL) { + uint8_t pixels; + pixels = data[i] & 0x55; + + switch (stage) { + case EPD_COMP: + pixels = 0xaa | (pixels ^ 0x55); + break; + + case EPD_WHITE: + pixels = 0x55 + (pixels ^ 0x55); + break; + + case EPD_INV: + pixels = 0x55 | ((pixels ^ 0x55) << 1); + break; + + case EPD_NORM: + pixels = 0xaa | pixels; + break; + + default: + break; + } + + uint8_t p1 = (pixels >> 6) & 0x03; + uint8_t p2 = (pixels >> 4) & 0x03; + uint8_t p3 = (pixels >> 2) & 0x03; + uint8_t p4 = (pixels >> 0) & 0x03; + pixels = (p1 << 0) | (p2 << 2) | (p3 << 4) | (p4 << 6); + + raw_write(pixels); + wait_for_busy_release(); + } else { + raw_write(fixed_value); + wait_for_busy_release(); + } + } + + // Complete line + raw_write(0x00); + wait_for_busy_release(); + + mp_hal_pin_high(mp_pin_cs); + wait_for_busy_release(); + + DATA_WRITE(0x70, 0x02); + wait_for_busy_release(); + + DATA_WRITE(0x72, 0x2f); +} + +void driver_sld00200p_clear(uint16_t color) { + uint16_t line_count = 176; + for (uint16_t i = 0; i < line_count; i++) { + epaper_sld00200p_line(i, NULL, 0xFF, EPD_COMP); + } + mp_hal_delay_ms(100); + + for (uint16_t i = 0; i < line_count; i++) { + epaper_sld00200p_line(i, NULL, 0xAA, EPD_WHITE); + } + mp_hal_delay_ms(100); + + for (uint16_t i = 0; i < line_count; i++) { + epaper_sld00200p_line(i, NULL, 0xFF, EPD_INV); + } + mp_hal_delay_ms(100); + + for (uint16_t i = 0; i < line_count; i++) { + epaper_sld00200p_line(i, NULL, 0xAA, EPD_NORM); + } + mp_hal_delay_ms(100); +} + +void driver_sld00200p_update_line(uint16_t line, fb_byte_t * p_bytes, fb_byte_t * p_old, uint16_t len, bool compressed) { + epaper_sld00200p_line(line, (uint8_t *)p_old, 0x00, EPD_COMP); + epaper_sld00200p_line(line, (uint8_t *)p_old, 0xAA, EPD_WHITE); + epaper_sld00200p_line(line, (uint8_t *)p_bytes, 0xAA, EPD_INV); + epaper_sld00200p_line(line, (uint8_t *)p_bytes, 0xFF, EPD_NORM); +} #endif diff --git a/nrf5/drivers/display/epaper_sld00200p_driver.h b/nrf5/drivers/display/epaper_sld00200p_driver.h index 2b641381f0..22fc2b56a9 100644 --- a/nrf5/drivers/display/epaper_sld00200p_driver.h +++ b/nrf5/drivers/display/epaper_sld00200p_driver.h @@ -27,6 +27,12 @@ #ifndef EPAPER_SLD00200P_DRIVER_H__ #define EPAPER_SLD00200P_DRIVER_H__ +#include "py/mphal.h" + +#include "hal_spi.h" +#include "hal_pwm.h" +#include "lcd_mono_fb.h" + typedef enum { EPD_COMP, @@ -35,4 +41,21 @@ typedef enum EPD_NORM } epd_stage_t; +void driver_sld00200p_init(NRF_SPI_Type * p_spi_instance, + NRF_PWM_Type * p_pwm_instance, + pin_obj_t * p_pin_cs, + pin_obj_t * p_pin_panel_on, + pin_obj_t * p_pin_border, + pin_obj_t * p_pin_busy, + pin_obj_t * p_pin_reset, + pin_obj_t * p_pin_discharge); + +void driver_sld00200p_reinit(void); + +void driver_sld00200p_deinit(void); + +void driver_sld00200p_clear(uint16_t color); + +void driver_sld00200p_update_line(uint16_t line, fb_byte_t * p_bytes, fb_byte_t * p_old, uint16_t len, bool compressed); + #endif // EPAPER_SLD00200P_DRIVER_H__ diff --git a/nrf5/drivers/display/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper_sld00200p_obj.c index 07cb2bd696..46ac21fe19 100644 --- a/nrf5/drivers/display/epaper_sld00200p_obj.c +++ b/nrf5/drivers/display/epaper_sld00200p_obj.c @@ -24,8 +24,14 @@ * THE SOFTWARE. */ +#include + #include "py/obj.h" #include "py/runtime.h" +#include "py/mphal.h" +#include "genhdr/pins.h" + +#include "epaper_sld00200p_driver.h" // For now PWM is only enabled for nrf52 targets. #if MICROPY_PY_DISPLAY_EPAPER_SLD00200P && NRF52 @@ -33,37 +39,118 @@ /// \moduleref epaper /// \class sld00200p - SLD00200P E-paper shield. +#include "pin.h" +#include "spi.h" +#include "pwm.h" #include "hal_spi.h" #include "hal_pwm.h" #include "lcd_mono_fb.h" typedef struct _epaper_sld00200p_obj_t { mp_obj_base_t base; - SPI_HandleTypeDef *spi; - PWM_HandleTypeDef *pwm; + machine_hard_spi_obj_t *spi; + machine_hard_pwm_obj_t *pwm; + pin_obj_t * pin_cs; + pin_obj_t * pin_panel_on; + pin_obj_t * pin_border; + pin_obj_t * pin_busy; + pin_obj_t * pin_reset; + pin_obj_t * pin_discharge; +#if 0 + pin_obj_t * pin_temp_sensor; +#endif + mp_obj_framebuf_t * framebuffer; } epaper_sld00200p_obj_t; +static void dirty_line_update_cb(mp_obj_framebuf_t * p_framebuffer, + uint16_t line, + fb_byte_t * p_new, + fb_byte_t * p_old) { + driver_sld00200p_update_line(line, p_new, p_old, p_framebuffer->bytes_stride, true); +} + /// \method __str__() /// Return a string describing the SLD00200P object. STATIC void epaper_sld00200_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + epaper_sld00200p_obj_t *self = o; + + mp_printf(print, "ILI9341(SPI(mosi=%u, miso=%u, clk=%u),\n", + self->spi->pyb->spi->init.mosi_pin, + self->spi->pyb->spi->init.miso_pin, + self->spi->pyb->spi->init.clk_pin); + mp_printf(print, " PWM(pwm_pin=%u),\n", + self->pwm->pyb->pwm->init.pwm_pin); + + mp_printf(print, " cs=(port=%u, pin=%u), panel_on=(port=%u, pin=%u),\n", + self->pin_cs->port, + self->pin_cs->pin, + self->pin_panel_on->port, + self->pin_panel_on->pin); + + mp_printf(print, " border=(port=%u, pin=%u), busy=(port=%u, pin=%u),\n", + self->pin_border->port, + self->pin_border->pin, + self->pin_busy->port, + self->pin_busy->pin); + + mp_printf(print, " reset=(port=%u, pin=%u), discharge=(port=%u, pin=%u),\n", + self->pin_reset->port, + self->pin_reset->pin, + self->pin_discharge->port, + self->pin_discharge->pin); + + mp_printf(print, " FB(width=%u, height=%u, dir=%u))\n", + self->framebuffer->width, + self->framebuffer->height); + } // for make_new enum { + ARG_NEW_WIDTH, + ARG_NEW_HEIGHT, ARG_NEW_SPI, - ARG_NEW_CS, ARG_NEW_PWM, + ARG_NEW_CS, ARG_NEW_PANEL_ON, ARG_NEW_BORDER, - ARG_NEW_RESET, ARG_NEW_BUSY, + ARG_NEW_RESET, ARG_NEW_DISCHARGE, ARG_NEW_TEMP_SENSOR, }; +/* +from machine import Pin, SPI, PWM +from display import SLD00200P +cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) +panel_on = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) +discharge = Pin("A19", mode=Pin.OUT, pull=Pin.PULL_UP) +border = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) +busy = Pin("A18", mode=Pin.IN, pull=Pin.PULL_DISABLED) +cs = Pin("A22", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +pwm = PWM(0, Pin("A16", mode=Pin.OUT), freq=PWM.FREQ_250KHZ, duty=50, period=2) +d = SLD00200P(264, 176, spi, pwm, cs, panel_on, border, busy, reset, discharge) +d.text("Hello World!", 32, 32) +d.show() +*/ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { - { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_PWM, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_PANEL_ON, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_BORDER, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_BUSY, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_DISCHARGE, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, +#if 0 + { ARG_NEW_TEMP_SENSOR, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, +#endif }; // parse args @@ -71,6 +158,113 @@ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_ar mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); epaper_sld00200p_obj_t *s = m_new_obj_with_finaliser(epaper_sld00200p_obj_t); + s->base.type = type; + + mp_int_t width; + mp_int_t height; + + if (args[ARG_NEW_WIDTH].u_int > 0) { + width = args[ARG_NEW_WIDTH].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display width not set")); + } + + if (args[ARG_NEW_HEIGHT].u_int > 0) { + height = args[ARG_NEW_HEIGHT].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display height not set")); + } + + if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { + s->spi = args[ARG_NEW_SPI].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display SPI not set")); + } + + if (args[ARG_NEW_PWM].u_obj != MP_OBJ_NULL) { + s->pwm = args[ARG_NEW_PWM].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display PWM not set")); + } + + if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { + s->pin_cs = args[ARG_NEW_CS].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display CS Pin not set")); + } + + if (args[ARG_NEW_PANEL_ON].u_obj != MP_OBJ_NULL) { + s->pin_panel_on = args[ARG_NEW_PANEL_ON].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Panel-on Pin not set")); + } + + if (args[ARG_NEW_BORDER].u_obj != MP_OBJ_NULL) { + s->pin_border = args[ARG_NEW_BORDER].u_obj; + printf("BORDER PIN %u\n", s->pin_border->pin); + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Border Pin not set")); + } + + if (args[ARG_NEW_BUSY].u_obj != MP_OBJ_NULL) { + s->pin_busy = args[ARG_NEW_BUSY].u_obj; + printf("BUSY PIN %u\n", s->pin_busy->pin); + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Busy Pin not set")); + } + + if (args[ARG_NEW_RESET].u_obj != MP_OBJ_NULL) { + s->pin_reset = args[ARG_NEW_RESET].u_obj; + printf("RESET PIN %u\n", s->pin_reset->pin); + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Reset Pin not set")); + } + + if (args[ARG_NEW_DISCHARGE].u_obj != MP_OBJ_NULL) { + s->pin_discharge = args[ARG_NEW_DISCHARGE].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Reset Pin not set")); + } + +#if 0 + if (args[ARG_NEW_TEMP_SENSOR].u_obj != MP_OBJ_NULL) { + s->pin_temp_sensor = args[ARG_NEW_TEMP_SENSOR].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Busy Pin not set)")); + } +#endif + + // direction arg not yet configurable + mp_int_t vertical = false; + s->framebuffer = lcd_mono_fb_helper_make_new(width, height, vertical); + + driver_sld00200p_init(s->spi->pyb->spi->instance, + s->pwm->pyb->pwm->instance, + s->pin_cs, + s->pin_panel_on, + s->pin_border, + s->pin_busy, + s->pin_reset, + s->pin_discharge); + + // Default to white background + driver_sld00200p_clear(0x00); + + display_clear_screen(s->framebuffer, 0x0); + + driver_sld00200p_deinit(); + return MP_OBJ_FROM_PTR(s); } @@ -96,14 +290,24 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(epaper_sld00200p_fill_obj, epaper_sld00200p_fil /// refresh() method explicitly. STATIC mp_obj_t epaper_sld00200p_show(size_t n_args, const mp_obj_t *args) { epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t num_of_refresh = 0; if (n_args > 1) { num_of_refresh = mp_obj_get_int(args[1]); } + driver_sld00200p_reinit(); - (void)num_of_refresh; - (void)self; + display_update(self->framebuffer, false, dirty_line_update_cb); + + if (num_of_refresh > 0) { + while (num_of_refresh > 0) { + display_update(self->framebuffer, true, dirty_line_update_cb); + num_of_refresh--; + } + } + + driver_sld00200p_deinit(); return mp_const_none; } @@ -115,14 +319,32 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_show_obj, 1, 2, epap /// - With no argument, 1 refresh will be done. /// - With `num_of_refresh` given, The whole framebuffer will be considered /// dirty and will be refreshed the given number of times. -STATIC mp_obj_t epaper_sld00200p_refresh(mp_obj_t self_in) { - epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(self_in); +STATIC mp_obj_t epaper_sld00200p_refresh(size_t n_args, const mp_obj_t *args) { + epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); - (void)self; + mp_int_t num_of_refresh = 0; + + if (n_args > 1) { + num_of_refresh = mp_obj_get_int(args[1]); + } + + driver_sld00200p_reinit(); + + if (num_of_refresh > 0) { + while (num_of_refresh > 0) { + display_update(self->framebuffer, true, dirty_line_update_cb); + num_of_refresh--; + } + } else { + // default to one refresh + display_update(self->framebuffer, true, dirty_line_update_cb); + } + + driver_sld00200p_deinit(); return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_1(epaper_sld00200p_refresh_obj, epaper_sld00200p_refresh); +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_refresh_obj, 1, 2, epaper_sld00200p_refresh); /// \method pixel(x, y, [color]) /// Write one pixel in framebuffer. @@ -160,12 +382,11 @@ STATIC mp_obj_t epaper_sld00200p_text(size_t n_args, const mp_obj_t *args) { if (n_args >= 4) { color = mp_obj_get_int(args[3]); } - (void)self; - (void)str; - (void)x; - (void)y; + (void)color; + display_print_string(self->framebuffer, x, y, str); + return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_text_obj, 4, 5, epaper_sld00200p_text); From 721065b307879e0b5e396e7f0fd5080733206134 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 13:30:21 +0100 Subject: [PATCH 125/809] nrf5/devices: Renaming system.c files for nrf51 and nrf52 to be more explicit on which version of chip they are referring to. --- nrf5/device/nrf51/{system_nrf51.c => system_nrf51822.c} | 0 nrf5/device/nrf52/{system_nrf52.c => system_nrf52832.c} | 0 nrf5/hal/hal_uart.h | 4 ++++ 3 files changed, 4 insertions(+) rename nrf5/device/nrf51/{system_nrf51.c => system_nrf51822.c} (100%) rename nrf5/device/nrf52/{system_nrf52.c => system_nrf52832.c} (100%) diff --git a/nrf5/device/nrf51/system_nrf51.c b/nrf5/device/nrf51/system_nrf51822.c similarity index 100% rename from nrf5/device/nrf51/system_nrf51.c rename to nrf5/device/nrf51/system_nrf51822.c diff --git a/nrf5/device/nrf52/system_nrf52.c b/nrf5/device/nrf52/system_nrf52832.c similarity index 100% rename from nrf5/device/nrf52/system_nrf52.c rename to nrf5/device/nrf52/system_nrf52832.c diff --git a/nrf5/hal/hal_uart.h b/nrf5/hal/hal_uart.h index ddcbdd5700..32e91ad6f4 100644 --- a/nrf5/hal/hal_uart.h +++ b/nrf5/hal/hal_uart.h @@ -113,6 +113,10 @@ typedef struct { uint8_t tx_pin; /**< TX pin number. */ uint8_t rts_pin; /**< RTS pin number, only used if flow control is enabled. */ uint8_t cts_pin; /**< CTS pin number, only used if flow control is enabled. */ + uint8_t rx_pin_port; /**< RX port number. */ + uint8_t tx_pin_port; /**< TX port number. */ + uint8_t rts_pin_port; /**< RTS port number, only used if flow control is enabled. */ + uint8_t cts_pin_port; /**< CTS port number, only used if flow control is enabled. */ bool flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ uint32_t baud_rate; /**< Baud rate configuration. */ From 4f04eed4c5863163fe87202f85ccaa60b6bccb13 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 15:15:36 +0100 Subject: [PATCH 126/809] nrf5/boards: Updating makefiles to use system.c files based on sub-variant of mcu. --- nrf5/Makefile | 4 ++-- nrf5/boards/microbit/mpconfigboard.mk | 4 ++-- nrf5/boards/pca10000/mpconfigboard.mk | 3 ++- nrf5/boards/pca10001/mpconfigboard.mk | 3 ++- nrf5/boards/pca10028/mpconfigboard.mk | 4 ++-- nrf5/boards/pca10031/mpconfigboard.mk | 3 ++- nrf5/boards/pca10040/mpconfigboard.mk | 4 +++- nrf5/boards/pca10056/mpconfigboard.mk | 4 +++- 8 files changed, 18 insertions(+), 11 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index c8d852f6ad..7aa0dd52a7 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -63,7 +63,7 @@ INC += -I./hal/$(MCU_VARIANT) INC += -I./drivers/display INC += -I../lib/mp-readline -NRF_DEFINES = -D$(MCU_VARIANT_UPPER) +NRF_DEFINES += -D$(MCU_VARIANT_UPPER) NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET CFLAGS_CORTEX_M = -mthumb -mabi=aapcs -fsingle-precision-constant -Wdouble-promotion @@ -159,7 +159,7 @@ DRIVERS_SRC_C += $(addprefix drivers/,\ #ifeq ($(SD), ) SRC_C += \ - device/$(MCU_VARIANT)/system_$(MCU_VARIANT).c \ + device/$(MCU_VARIANT)/system_$(MCU_SUB_VARIANT).c \ SRC_S = \ device/$(MCU_VARIANT)/startup_$(MCU_VARIANT).s \ diff --git a/nrf5/boards/microbit/mpconfigboard.mk b/nrf5/boards/microbit/mpconfigboard.mk index c8a0f0caea..f959edab50 100644 --- a/nrf5/boards/microbit/mpconfigboard.mk +++ b/nrf5/boards/microbit/mpconfigboard.mk @@ -1,5 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_aa.ld +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld FLASHER = pyocd - diff --git a/nrf5/boards/pca10000/mpconfigboard.mk b/nrf5/boards/pca10000/mpconfigboard.mk index d2a566aea8..523653ede0 100644 --- a/nrf5/boards/pca10000/mpconfigboard.mk +++ b/nrf5/boards/pca10000/mpconfigboard.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_aa.ld +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld diff --git a/nrf5/boards/pca10001/mpconfigboard.mk b/nrf5/boards/pca10001/mpconfigboard.mk index 40a74fd176..269fdc95af 100644 --- a/nrf5/boards/pca10001/mpconfigboard.mk +++ b/nrf5/boards/pca10001/mpconfigboard.mk @@ -1,3 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_aa.ld +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld diff --git a/nrf5/boards/pca10028/mpconfigboard.mk b/nrf5/boards/pca10028/mpconfigboard.mk index ac92424ec7..01b6bcf7e1 100644 --- a/nrf5/boards/pca10028/mpconfigboard.mk +++ b/nrf5/boards/pca10028/mpconfigboard.mk @@ -1,4 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_ac.ld - +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/$(MCU_SUB_VARIANT)_ac.ld diff --git a/nrf5/boards/pca10031/mpconfigboard.mk b/nrf5/boards/pca10031/mpconfigboard.mk index 72a21aa76f..01b6bcf7e1 100644 --- a/nrf5/boards/pca10031/mpconfigboard.mk +++ b/nrf5/boards/pca10031/mpconfigboard.mk @@ -1,3 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_ac.ld +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/$(MCU_SUB_VARIANT)_ac.ld diff --git a/nrf5/boards/pca10040/mpconfigboard.mk b/nrf5/boards/pca10040/mpconfigboard.mk index 3b6af95f75..62fce4c795 100644 --- a/nrf5/boards/pca10040/mpconfigboard.mk +++ b/nrf5/boards/pca10040/mpconfigboard.mk @@ -1,4 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 -LD_FILE = boards/nrf52832_aa.ld +MCU_SUB_VARIANT = nrf52832 +LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld +NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf5/boards/pca10056/mpconfigboard.mk b/nrf5/boards/pca10056/mpconfigboard.mk index 2e273dabc7..15a88ed091 100644 --- a/nrf5/boards/pca10056/mpconfigboard.mk +++ b/nrf5/boards/pca10056/mpconfigboard.mk @@ -1,4 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 -LD_FILE = boards/nrf52840_aa.ld +MCU_SUB_VARIANT = nrf52840 +LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld +NRF_DEFINES += -DNRF52840_XXAA From 19d354ed050c2470692ad2b23e6b0e8119a609ce Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 15:17:03 +0100 Subject: [PATCH 127/809] nrf5: Updating to use new nrfjprog in makefile. Needed for nrf52840 targets. Changed from pinreset to debug reset. --- nrf5/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 7aa0dd52a7..934bd648c9 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -190,13 +190,13 @@ ifeq ($(FLASHER),) flash: $(BUILD)/firmware.elf nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT) - nrfjprog --pinreset -f $(MCU_VARIANT) + nrfjprog --reset -f $(MCU_VARIANT) sd: nrfjprog --eraseall -f $(MCU_VARIANT) nrfjprog --program $(SOFTDEV_HEX) -f $(MCU_VARIANT) nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT) - nrfjprog --pinreset -f $(MCU_VARIANT) + nrfjprog --reset -f $(MCU_VARIANT) else ifeq ($(FLASHER), pyocd) From 307f95bd030df3922e4cb5c881195610b830bbfd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 15:32:26 +0100 Subject: [PATCH 128/809] nrf5/devices: Updating header files for nrf51 and nrf52. Adding headers for nrf52840. --- nrf5/device/nrf.h | 36 +- nrf5/device/nrf51/nrf51.h | 2 +- nrf5/device/nrf51/nrf51_bitfields.h | 3 +- nrf5/device/nrf52/nrf51_to_nrf52840.h | 567 + nrf5/device/nrf52/nrf52.h | 2 +- nrf5/device/nrf52/nrf52840.h | 2417 ++++ nrf5/device/nrf52/nrf52840_bitfields.h | 14633 +++++++++++++++++++++++ nrf5/device/nrf52/nrf52_bitfields.h | 14 +- nrf5/device/nrf52/nrf52_name_change.h | 5 - nrf5/device/nrf52/nrf52_to_nrf52840.h | 88 + nrf5/device/nrf52/system_nrf52840.c | 209 + nrf5/device/nrf52/system_nrf52840.h | 69 + 12 files changed, 18027 insertions(+), 18 deletions(-) create mode 100644 nrf5/device/nrf52/nrf51_to_nrf52840.h create mode 100644 nrf5/device/nrf52/nrf52840.h create mode 100644 nrf5/device/nrf52/nrf52840_bitfields.h create mode 100644 nrf5/device/nrf52/nrf52_to_nrf52840.h create mode 100644 nrf5/device/nrf52/system_nrf52840.c create mode 100644 nrf5/device/nrf52/system_nrf52840.h diff --git a/nrf5/device/nrf.h b/nrf5/device/nrf.h index 6c9676cc48..277e94148d 100644 --- a/nrf5/device/nrf.h +++ b/nrf5/device/nrf.h @@ -33,30 +33,48 @@ /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 9 -#define MDK_MICRO_VERSION 0 +#define MDK_MINOR_VERSION 11 +#define MDK_MICRO_VERSION 1 + +/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ +#if defined (NRF52) + #ifndef NRF52832_XXAA + #define NRF52832_XXAA + #endif +#endif + +/* Define NRF52_SERIES for common use in nRF52 series devices. */ +#if defined (NRF52832_XXAA) || defined (NRF52840_XXAA) + #define NRF52_SERIES +#endif + #if defined(_WIN32) - /* Do not include nrf51 specific files when building for PC host */ + /* Do not include nrf specific files when building for PC host */ #elif defined(__unix) - /* Do not include nrf51 specific files when building for PC host */ + /* Do not include nrf specific files when building for PC host */ #elif defined(__APPLE__) - /* Do not include nrf51 specific files when building for PC host */ + /* Do not include nrf specific files when building for PC host */ #else - /* Family selection for family includes. */ + /* Device selection for device includes. */ #if defined (NRF51) #include "nrf51.h" #include "nrf51_bitfields.h" #include "nrf51_deprecated.h" - #elif defined (NRF52) + #elif defined (NRF52840_XXAA) + #include "nrf52840.h" + #include "nrf52840_bitfields.h" + #include "nrf51_to_nrf52840.h" + #include "nrf52_to_nrf52840.h" + #elif defined (NRF52832_XXAA) #include "nrf52.h" #include "nrf52_bitfields.h" #include "nrf51_to_nrf52.h" #include "nrf52_name_change.h" #else - #error "Device family must be defined. See nrf.h." - #endif /* NRF51, NRF52 */ + #error "Device must be defined. See nrf.h." + #endif /* NRF51, NRF52832_XXAA, NRF52840_XXAA */ #include "compiler_abstraction.h" diff --git a/nrf5/device/nrf51/nrf51.h b/nrf5/device/nrf51/nrf51.h index e657fa75c0..ae60a5613d 100644 --- a/nrf5/device/nrf51/nrf51.h +++ b/nrf5/device/nrf51/nrf51.h @@ -6,7 +6,7 @@ * nrf51 from Nordic Semiconductor. * * @version V522 - * @date 30. September 2016 + * @date 18. November 2016 * * @note Generated with SVDConv V2.81d * from CMSIS SVD File 'nrf51.svd' Version 522, diff --git a/nrf5/device/nrf51/nrf51_bitfields.h b/nrf5/device/nrf51/nrf51_bitfields.h index 6505a0bb06..22c2c21e55 100644 --- a/nrf5/device/nrf51/nrf51_bitfields.h +++ b/nrf5/device/nrf51/nrf51_bitfields.h @@ -5692,7 +5692,7 @@ #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ -#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps). */ /* Register: TWI_ADDRESS */ /* Description: Address used in the two-wire transfer. */ @@ -5886,6 +5886,7 @@ #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ diff --git a/nrf5/device/nrf52/nrf51_to_nrf52840.h b/nrf5/device/nrf52/nrf51_to_nrf52840.h new file mode 100644 index 0000000000..2ee36e7558 --- /dev/null +++ b/nrf5/device/nrf52/nrf51_to_nrf52840.h @@ -0,0 +1,567 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF51_TO_NRF52840_H +#define NRF51_TO_NRF52840_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#define UART0_IRQHandler UARTE0_UART0_IRQHandler +#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define ADC_IRQHandler SAADC_IRQHandler +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#define SWI5_IRQHandler SWI5_EGU5_IRQHandler + +#define UART0_IRQn UARTE0_UART0_IRQn +#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#define ADC_IRQn SAADC_IRQn +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define SWI0_IRQn SWI0_EGU0_IRQn +#define SWI1_IRQn SWI1_EGU1_IRQn +#define SWI2_IRQn SWI2_EGU2_IRQn +#define SWI3_IRQn SWI3_EGU3_IRQn +#define SWI4_IRQn SWI4_EGU4_IRQn +#define SWI5_IRQn SWI5_EGU5_IRQn + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#define RBPCONF APPROTECT + +#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled + + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#define NRF_GPIO NRF_P0 +#define NRF_GPIO_BASE NRF_P0_BASE + + +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#define PSELLED PSEL.LED +#define PSELA PSEL.A +#define PSELB PSEL.B + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#define PSELSCK PSEL.SCK +#define PSELMISO PSEL.MISO +#define PSELMOSI PSEL.MOSI +#define PSELCSN PSEL.CSN + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#define RXDPTR RXD.PTR +#define MAXRX RXD.MAXCNT +#define AMOUNTRX RXD.AMOUNT + +#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#define TXDPTR TXD.PTR +#define MAXTX TXD.MAXCNT +#define AMOUNTTX TXD.AMOUNT + +#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk + + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#define PSELRTS PSEL.RTS +#define PSELTXD PSEL.TXD +#define PSELCTS PSEL.CTS +#define PSELRXD PSEL.RXD + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#define PSELSCL PSEL.SCL +#define PSELSDA PSEL.SDA + + + +/* From nrf51_deprecated.h */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* IRQ */ +/* COMP module was eliminated. Adapted to nrf52840 headers. */ +#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn + + +/* REFSEL register redefined enumerated values and added some more. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd + + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52840_H */ + diff --git a/nrf5/device/nrf52/nrf52.h b/nrf5/device/nrf52/nrf52.h index 760fd29ba6..8e0ff0c0b5 100644 --- a/nrf5/device/nrf52/nrf52.h +++ b/nrf5/device/nrf52/nrf52.h @@ -6,7 +6,7 @@ * nrf52 from Nordic Semiconductor. * * @version V1 - * @date 30. September 2016 + * @date 18. November 2016 * * @note Generated with SVDConv V2.81d * from CMSIS SVD File 'nrf52.svd' Version 1, diff --git a/nrf5/device/nrf52/nrf52840.h b/nrf5/device/nrf52/nrf52840.h new file mode 100644 index 0000000000..92a40f4c08 --- /dev/null +++ b/nrf5/device/nrf52/nrf52840.h @@ -0,0 +1,2417 @@ + +/****************************************************************************************************//** + * @file nrf52840.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * nrf52840 from Nordic Semiconductor. + * + * @version V1 + * @date 18. November 2016 + * + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nrf52840.svd' Version 1, + * + * @par Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + +/** @addtogroup nrf52840 + * @{ + */ + +#ifndef NRF52840_H +#define NRF52840_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- nrf52840 Specific Interrupt Numbers -------------------- */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38, /*!< 38 FPU */ + USBD_IRQn = 39, /*!< 39 USBD */ + UARTE1_IRQn = 40, /*!< 40 UARTE1 */ + QSPI_IRQn = 41, /*!< 41 QSPI */ + CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ + SPIM3_IRQn = 43, /*!< 43 SPIM3 */ + PWM3_IRQn = 45 /*!< 45 PWM3 */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_nrf52840.h" /*!< nrf52840 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + +typedef struct { + __I uint32_t PART; /*!< Part code */ + __I uint32_t VARIANT; /*!< Part variant (hardware version and production configuration). */ + __I uint32_t PACKAGE; /*!< Package option */ + __I uint32_t RAM; /*!< RAM variant */ + __I uint32_t FLASH; /*!< Flash variant */ + __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */ +} FICR_INFO_Type; + +typedef struct { + __I uint32_t A0; /*!< Slope definition A0. */ + __I uint32_t A1; /*!< Slope definition A1. */ + __I uint32_t A2; /*!< Slope definition A2. */ + __I uint32_t A3; /*!< Slope definition A3. */ + __I uint32_t A4; /*!< Slope definition A4. */ + __I uint32_t A5; /*!< Slope definition A5. */ + __I uint32_t B0; /*!< y-intercept B0. */ + __I uint32_t B1; /*!< y-intercept B1. */ + __I uint32_t B2; /*!< y-intercept B2. */ + __I uint32_t B3; /*!< y-intercept B3. */ + __I uint32_t B4; /*!< y-intercept B4. */ + __I uint32_t B5; /*!< y-intercept B5. */ + __I uint32_t T0; /*!< Segment end T0. */ + __I uint32_t T1; /*!< Segment end T1. */ + __I uint32_t T2; /*!< Segment end T2. */ + __I uint32_t T3; /*!< Segment end T3. */ + __I uint32_t T4; /*!< Segment end T4. */ +} FICR_TEMP_Type; + +typedef struct { + __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; + +typedef struct { + __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */ + __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */ + __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */ + __I uint32_t RESERVED0; +} POWER_RAM_Type; + +typedef struct { + __IO uint32_t RTS; /*!< Pin select for RTS signal */ + __IO uint32_t TXD; /*!< Pin select for TXD signal */ + __IO uint32_t CTS; /*!< Pin select for CTS signal */ + __IO uint32_t RXD; /*!< Pin select for RXD signal */ +} UARTE_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; + +typedef struct { + __IO uint32_t RTS; /*!< Pin select for RTS */ + __IO uint32_t TXD; /*!< Pin select for TXD */ + __IO uint32_t CTS; /*!< Pin select for CTS */ + __IO uint32_t RXD; /*!< Pin select for RXD */ +} UART_PSEL_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ + __IO uint32_t CSN; /*!< Pin select for CSN */ +} SPIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_TXD_Type; + +typedef struct { + __IO uint32_t RXDELAY; /*!< Sample delay for input serial data on MISO */ + __IO uint32_t CSNDUR; /*!< Minimum duration between edge of CSN and edge of SCK and minimum + duration CSN must stay high between transactions */ +} SPIM_IFTIMING_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t CSN; /*!< Pin select for CSN signal */ +} SPIS_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< RXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< TXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; + +typedef struct { + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_TXD_Type; + +typedef struct { + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIS_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< RXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< TXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ +} SPI_PSEL_Type; + +typedef struct { + __IO uint32_t SCL; /*!< Pin select for SCL */ + __IO uint32_t SDA; /*!< Pin select for SDA */ +} TWI_PSEL_Type; + +typedef struct { + __IO uint32_t RX; /*!< Result of last incoming frame */ +} NFCT_FRAMESTATUS_Type; + +typedef struct { + __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */ + __IO uint32_t AMOUNT; /*!< Size of outgoing frame */ +} NFCT_TXD_Type; + +typedef struct { + __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */ + __I uint32_t AMOUNT; /*!< Size of last incoming frame */ +} NFCT_RXD_Type; + +typedef struct { + __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */ + __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; + +typedef struct { + __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */ + __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */ + __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */ + __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring + a channel */ +} SAADC_CH_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */ + __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */ +} SAADC_RESULT_Type; + +typedef struct { + __IO uint32_t LED; /*!< Pin select for LED signal */ + __IO uint32_t A; /*!< Pin select for A signal */ + __IO uint32_t B; /*!< Pin select for B signal */ +} QDEC_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence + A */ + __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence + A */ + __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between + samples loaded to compare register (load every CNT+1 PWM periods) */ + __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */ + __I uint32_t RESERVED1[4]; +} PWM_SEQ_Type; + +typedef struct { + __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel + 0 */ +} PWM_PSEL_Type; + +typedef struct { + __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */ + __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */ + __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */ +} PDM_SAMPLE_Type; + +typedef struct { + __IO uint32_t ADDR; /*!< Description cluster[0]: Configure the word-aligned start address + of region 0 to protect */ + __IO uint32_t SIZE; /*!< Description cluster[0]: Size of region to protect counting from + address ACL[0].ADDR. Write '0' as no effect. */ + __IO uint32_t PERM; /*!< Description cluster[0]: Access permissions for region 0 as defined + by start address ACL[0].ADDR and size ACL[0].SIZE */ + __IO uint32_t UNUSED0; /*!< Unspecified */ +} ACL_ACL_Type; + +typedef struct { + __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */ + __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */ +} PPI_TASKS_CHG_Type; + +typedef struct { + __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */ + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_CH_Type; + +typedef struct { + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_FORK_Type; + +typedef struct { + __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */ +} MWU_EVENTS_REGION_Type; + +typedef struct { + __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0 + detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */ +} MWU_EVENTS_PREGION_Type; + +typedef struct { + __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, write access detected while corresponding subregion was enabled + for watching */ + __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, read access detected while corresponding subregion was enabled + for watching */ +} MWU_PERREGION_Type; + +typedef struct { + __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */ + __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */ + __I uint32_t RESERVED2[2]; +} MWU_REGION_Type; + +typedef struct { + __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */ + __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */ + __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */ + __I uint32_t RESERVED3; +} MWU_PREGION_Type; + +typedef struct { + __IO uint32_t MODE; /*!< I2S mode. */ + __IO uint32_t RXEN; /*!< Reception (RX) enable. */ + __IO uint32_t TXEN; /*!< Transmission (TX) enable. */ + __IO uint32_t MCKEN; /*!< Master clock generator enable. */ + __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */ + __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */ + __IO uint32_t SWIDTH; /*!< Sample width. */ + __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */ + __IO uint32_t FORMAT; /*!< Frame format. */ + __IO uint32_t CHANNELS; /*!< Enable channels. */ +} I2S_CONFIG_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Receive buffer RAM start address. */ +} I2S_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */ +} I2S_TXD_Type; + +typedef struct { + __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; + +typedef struct { + __IO uint32_t MCK; /*!< Pin select for MCK signal. */ + __IO uint32_t SCK; /*!< Pin select for SCK signal. */ + __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */ + __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */ + __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */ +} I2S_PSEL_Type; + +typedef struct { + __I uint32_t EPIN[8]; /*!< Description collection[0]: IN endpoint halted status. Can be + used as is as response to a GetStatus() request to endpoint. */ + __I uint32_t RESERVED4; + __I uint32_t EPOUT[8]; /*!< Description collection[0]: OUT endpoint halted status. Can be + used as is as response to a GetStatus() request to endpoint. */ +} USBD_HALTED_Type; + +typedef struct { + __IO uint32_t EPOUT[8]; /*!< Description collection[0]: Amount of bytes received last in + the data stage of this OUT endpoint */ + __IO uint32_t ISOOUT; /*!< Amount of bytes received last on this iso OUT data endpoint */ +} USBD_SIZE_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Description cluster[0]: Data pointer */ + __IO uint32_t MAXCNT; /*!< Description cluster[0]: Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Description cluster[0]: Number of bytes transferred in the last + transaction */ + __I uint32_t RESERVED5[2]; +} USBD_EPIN_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} USBD_ISOIN_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Description cluster[0]: Data pointer */ + __IO uint32_t MAXCNT; /*!< Description cluster[0]: Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Description cluster[0]: Number of bytes transferred in the last + transaction */ + __I uint32_t RESERVED6[2]; +} USBD_EPOUT_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} USBD_ISOOUT_Type; + +typedef struct { + __IO uint32_t SRC; /*!< Flash memory source address */ + __IO uint32_t DST; /*!< RAM destination address */ + __IO uint32_t CNT; /*!< Read transfer length */ +} QSPI_READ_Type; + +typedef struct { + __IO uint32_t DST; /*!< Flash destination address */ + __IO uint32_t SRC; /*!< RAM source address */ + __IO uint32_t CNT; /*!< Write transfer length */ +} QSPI_WRITE_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Start address of flash block to be erased */ + __IO uint32_t LEN; /*!< Size of block to be erased. */ +} QSPI_ERASE_Type; + +typedef struct { + __IO uint32_t SCK; /*!< Pin select for serial clock SCK */ + __IO uint32_t CSN; /*!< Pin select for chip select signal CSN. */ + __I uint32_t RESERVED7; + __IO uint32_t IO0; /*!< Pin select for serial data MOSI/IO0. */ + __IO uint32_t IO1; /*!< Pin select for serial data MISO/IO1. */ + __IO uint32_t IO2; /*!< Pin select for serial data IO2. */ + __IO uint32_t IO3; /*!< Pin select for serial data IO3. */ +} QSPI_PSEL_Type; + + +/* ================================================================================ */ +/* ================ FICR ================ */ +/* ================================================================================ */ + + +/** + * @brief Factory Information Configuration Registers (FICR) + */ + +typedef struct { /*!< FICR Structure */ + __I uint32_t RESERVED0[4]; + __I uint32_t CODEPAGESIZE; /*!< Code memory page size */ + __I uint32_t CODESIZE; /*!< Code memory size */ + __I uint32_t RESERVED1[18]; + __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */ + __I uint32_t RESERVED2[6]; + __I uint32_t ER[4]; /*!< Description collection[0]: Encryption root, word 0 */ + __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */ + __I uint32_t DEVICEADDRTYPE; /*!< Device address type */ + __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */ + __I uint32_t RESERVED3[21]; + FICR_INFO_Type INFO; /*!< Device info */ + __I uint32_t RESERVED4[185]; + FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */ + __I uint32_t RESERVED5[2]; + FICR_NFC_Type NFC; /*!< Unspecified */ +} NRF_FICR_Type; + + +/* ================================================================================ */ +/* ================ UICR ================ */ +/* ================================================================================ */ + + +/** + * @brief User Information Configuration Registers (UICR) + */ + +typedef struct { /*!< UICR Structure */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t UNUSED1; /*!< Unspecified */ + __IO uint32_t UNUSED2; /*!< Unspecified */ + __I uint32_t RESERVED0; + __IO uint32_t UNUSED3; /*!< Unspecified */ + __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */ + __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */ + __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */ + __I uint32_t RESERVED1[64]; + __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function */ + __IO uint32_t APPROTECT; /*!< Access port protection */ + __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna + or GPIO */ + __I uint32_t RESERVED2[60]; + __IO uint32_t EXTSUPPLY; /*!< Enable external circuitry to be supplied from VDD pin. Applicable + in 'High voltage mode' only. */ + __IO uint32_t REGOUT0; /*!< GPIO reference voltage / external output supply voltage in 'High + voltage mode'. */ +} NRF_UICR_Type; + + +/* ================================================================================ */ +/* ================ POWER ================ */ +/* ================================================================================ */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< POWER Structure */ + __I uint32_t RESERVED0[30]; + __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */ + __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */ + __I uint32_t RESERVED1[34]; + __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */ + __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */ + __IO uint32_t EVENTS_USBDETECTED; /*!< Voltage supply detected on VBUS */ + __IO uint32_t EVENTS_USBREMOVED; /*!< Voltage supply removed from VBUS */ + __IO uint32_t EVENTS_USBPWRRDY; /*!< USB 3.3 V supply ready */ + __I uint32_t RESERVED3[119]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[61]; + __IO uint32_t RESETREAS; /*!< Reset reason */ + __I uint32_t RESERVED5[9]; + __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */ + __I uint32_t RESERVED6[3]; + __I uint32_t USBREGSTATUS; /*!< USB supply status */ + __I uint32_t RESERVED7[49]; + __O uint32_t SYSTEMOFF; /*!< System OFF register */ + __I uint32_t RESERVED8[3]; + __IO uint32_t POFCON; /*!< Power failure comparator configuration */ + __I uint32_t RESERVED9[2]; + __IO uint32_t GPREGRET; /*!< General purpose retention register */ + __IO uint32_t GPREGRET2; /*!< General purpose retention register */ + __I uint32_t RESERVED10[21]; + __IO uint32_t DCDCEN; /*!< Enable DC/DC converter for REG1 stage. */ + __I uint32_t RESERVED11; + __IO uint32_t DCDCEN0; /*!< Enable DC/DC converter for REG0 stage. */ + __I uint32_t RESERVED12[47]; + __I uint32_t MAINREGSTATUS; /*!< Main supply status */ + __I uint32_t RESERVED13[175]; + POWER_RAM_Type RAM[9]; /*!< Unspecified */ +} NRF_POWER_Type; + + +/* ================================================================================ */ +/* ================ CLOCK ================ */ +/* ================================================================================ */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< CLOCK Structure */ + __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */ + __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */ + __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */ + __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */ + __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC or LFULP oscillator */ + __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ + __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ + __I uint32_t RESERVED0[57]; + __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */ + __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ + __I uint32_t RESERVED1; + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ + __I uint32_t RESERVED2[124]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ + __I uint32_t HFCLKSTAT; /*!< HFCLK status */ + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ + __I uint32_t LFCLKSTAT; /*!< LFCLK status */ + __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + __I uint32_t RESERVED5[62]; + __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ + __I uint32_t RESERVED6[7]; + __IO uint32_t CTIV; /*!< Calibration timer interval */ + __I uint32_t RESERVED7[8]; + __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */ +} NRF_CLOCK_Type; + + +/* ================================================================================ */ +/* ================ RADIO ================ */ +/* ================================================================================ */ + + +/** + * @brief 2.4 GHz Radio (RADIO) + */ + +typedef struct { /*!< RADIO Structure */ + __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */ + __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */ + __O uint32_t TASKS_START; /*!< Start RADIO */ + __O uint32_t TASKS_STOP; /*!< Stop RADIO */ + __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */ + __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal + strength. */ + __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */ + __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */ + __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */ + __O uint32_t TASKS_EDSTART; /*!< Start the Energy Detect measurement used in IEEE 802.15.4 mode */ + __O uint32_t TASKS_EDSTOP; /*!< Stop the Energy Detect measurement */ + __O uint32_t TASKS_CCASTART; /*!< Start the Clear Channel Assessment used in IEEE 802.15.4 mode */ + __O uint32_t TASKS_CCASTOP; /*!< Stop the Clear Channel Assessment */ + __I uint32_t RESERVED0[51]; + __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */ + __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */ + __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */ + __IO uint32_t EVENTS_END; /*!< Packet sent or received */ + __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */ + __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */ + __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */ + __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */ + __I uint32_t RESERVED2; + __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */ + __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */ + __IO uint32_t EVENTS_FRAMESTART; /*!< IEEE 802.15.4 length field received */ + __IO uint32_t EVENTS_EDEND; /*!< Sampling of Energy Detection complete. A new ED sample is ready + for readout from the RADIO.EDSAMPLE register */ + __IO uint32_t EVENTS_EDSTOPPED; /*!< The sampling of Energy Detection has stopped */ + __IO uint32_t EVENTS_CCAIDLE; /*!< Wireless medium in idle - clear to send */ + __IO uint32_t EVENTS_CCABUSY; /*!< Wireless medium busy - do not send */ + __IO uint32_t EVENTS_CCASTOPPED; /*!< The CCA has stopped */ + __IO uint32_t EVENTS_RATEBOOST; /*!< Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit + to Ble_LR500Kbit. */ + __IO uint32_t EVENTS_TXREADY; /*!< RADIO has ramped up and is ready to be started TX path */ + __IO uint32_t EVENTS_RXREADY; /*!< RADIO has ramped up and is ready to be started RX path */ + __IO uint32_t EVENTS_MHRMATCH; /*!< MAC Header match found. */ + __I uint32_t RESERVED3[40]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED4[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[61]; + __I uint32_t CRCSTATUS; /*!< CRC status */ + __I uint32_t RESERVED6; + __I uint32_t RXMATCH; /*!< Received address */ + __I uint32_t RXCRC; /*!< CRC field of previously received packet */ + __I uint32_t DAI; /*!< Device address match index */ + __I uint32_t RESERVED7[60]; + __IO uint32_t PACKETPTR; /*!< Packet pointer */ + __IO uint32_t FREQUENCY; /*!< Frequency */ + __IO uint32_t TXPOWER; /*!< Output power */ + __IO uint32_t MODE; /*!< Data rate and modulation */ + __IO uint32_t PCNF0; /*!< Packet configuration register 0 */ + __IO uint32_t PCNF1; /*!< Packet configuration register 1 */ + __IO uint32_t BASE0; /*!< Base address 0 */ + __IO uint32_t BASE1; /*!< Base address 1 */ + __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */ + __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */ + __IO uint32_t TXADDRESS; /*!< Transmit address select */ + __IO uint32_t RXADDRESSES; /*!< Receive address select */ + __IO uint32_t CRCCNF; /*!< CRC configuration */ + __IO uint32_t CRCPOLY; /*!< CRC polynomial */ + __IO uint32_t CRCINIT; /*!< CRC initial value */ + __I uint32_t RESERVED8; + __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */ + __I uint32_t RSSISAMPLE; /*!< RSSI sample */ + __I uint32_t RESERVED9; + __I uint32_t STATE; /*!< Current radio state */ + __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */ + __I uint32_t RESERVED10[2]; + __IO uint32_t BCC; /*!< Bit counter compare */ + __I uint32_t RESERVED11[39]; + __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */ + __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */ + __IO uint32_t DACNF; /*!< Device address match configuration */ + __IO uint32_t MHRMATCHCONF; /*!< Search Pattern Configuration */ + __IO uint32_t MHRMATCHMAS; /*!< Pattern mask */ + __I uint32_t RESERVED12; + __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */ + __I uint32_t RESERVED13[3]; + __IO uint32_t SFD; /*!< IEEE 802.15.4 Start of Frame Delimiter */ + __IO uint32_t EDCNT; /*!< IEEE 802.15.4 Energy Detect Loop Count */ + __IO uint32_t EDSAMPLE; /*!< IEEE 802.15.4 Energy Detect Level */ + __IO uint32_t CCACTRL; /*!< IEEE 802.15.4 Clear Channel Assessment Control */ + __I uint32_t RESERVED14[611]; + __IO uint32_t POWER; /*!< Peripheral power control */ +} NRF_RADIO_Type; + + +/* ================================================================================ */ +/* ================ UARTE ================ */ +/* ================================================================================ */ + + +/** + * @brief UART with EasyDMA 0 (UARTE) + */ + +typedef struct { /*!< UARTE Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[7]; + __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */ + __I uint32_t RESERVED1[52]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD (but potentially not yet transferred to + Data RAM) */ + __I uint32_t RESERVED2; + __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ + __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */ + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */ + __I uint32_t RESERVED6; + __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */ + __I uint32_t RESERVED7[41]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[93]; + __IO uint32_t ERRORSRC; /*!< Error source Note : this register is read / write one to clear. */ + __I uint32_t RESERVED10[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED11; + UARTE_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[3]; + __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED13[3]; + UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED14; + UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED15[7]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; + + +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART) + */ + +typedef struct { /*!< UART Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ + __I uint32_t RESERVED1[56]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ + __I uint32_t RESERVED2[4]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ + __I uint32_t RESERVED3; + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5[46]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED6[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED7[93]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED8[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED9; + UART_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RXD; /*!< RXD register */ + __O uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED10; + __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED11[17]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UART_Type; + + +/* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM) + */ + +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */ + __I uint32_t RESERVED6[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started */ + __I uint32_t RESERVED7[44]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[61]; + __IO uint32_t STALLSTAT; /*!< Stall status for EasyDMA RAM accesses. The fields in this register + is set to STALL by hardware whenever a stall occurres and can + be cleared (set to NOSTALL) by the CPU. */ + __I uint32_t RESERVED10[63]; + __IO uint32_t ENABLE; /*!< Enable SPIM */ + __I uint32_t RESERVED11; + SPIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[3]; + __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED13[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED14[2]; + SPIM_IFTIMING_Type IFTIMING; /*!< Unspecified */ + __I uint32_t RESERVED15[22]; + __IO uint32_t ORC; /*!< Byte transmitted after TXD.MAXCNT bytes have been transmitted + in the case when RXD.MAXCNT is greater than TXD.MAXCNT */ +} NRF_SPIM_Type; + + +/* ================================================================================ */ +/* ================ SPIS ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI Slave 0 (SPIS) + */ + +typedef struct { /*!< SPIS Structure */ + __I uint32_t RESERVED0[9]; + __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */ + __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */ + __I uint32_t RESERVED1[54]; + __IO uint32_t EVENTS_END; /*!< Granted transaction completed */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED3[5]; + __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */ + __I uint32_t RESERVED4[53]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED5[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED6[61]; + __I uint32_t SEMSTAT; /*!< Semaphore status register */ + __I uint32_t RESERVED7[15]; + __IO uint32_t STATUS; /*!< Status from last transaction */ + __I uint32_t RESERVED8[47]; + __IO uint32_t ENABLE; /*!< Enable SPI slave */ + __I uint32_t RESERVED9; + SPIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED10[7]; + SPIS_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED11; + SPIS_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED12; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED13; + __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored + transaction. */ + __I uint32_t RESERVED14[24]; + __IO uint32_t ORC; /*!< Over-read character */ +} NRF_SPIS_Type; + + +/* ================================================================================ */ +/* ================ TWIM ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM) + */ + +typedef struct { /*!< TWIM Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is + not suspended. */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[8]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been + issued, TWI traffic is now suspended. */ + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[2]; + __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */ + __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */ + __I uint32_t RESERVED7[39]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED10[14]; + __IO uint32_t ENABLE; /*!< Enable TWIM */ + __I uint32_t RESERVED11; + TWIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[5]; + __IO uint32_t FREQUENCY; /*!< TWI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED13[3]; + TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[13]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWIM_Type; + + +/* ================================================================================ */ +/* ================ TWIS ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS) + */ + +typedef struct { /*!< TWIS Structure */ + __I uint32_t RESERVED0[5]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED2[3]; + __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */ + __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */ + __I uint32_t RESERVED3[51]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[9]; + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_WRITE; /*!< Write command received */ + __IO uint32_t EVENTS_READ; /*!< Read command received */ + __I uint32_t RESERVED7[37]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[113]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t MATCH; /*!< Status register indicating which address had a match */ + __I uint32_t RESERVED10[10]; + __IO uint32_t ENABLE; /*!< Enable TWIS */ + __I uint32_t RESERVED11; + TWIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[9]; + TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED13; + TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[14]; + __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */ + __I uint32_t RESERVED15; + __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */ + __I uint32_t RESERVED16[10]; + __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read + of the transmit buffer. */ +} NRF_TWIS_Type; + + +/* ================================================================================ */ +/* ================ SPI ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI) + */ + +typedef struct { /*!< SPI Structure */ + __I uint32_t RESERVED0[66]; + __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ + __I uint32_t RESERVED1[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable SPI */ + __I uint32_t RESERVED3; + SPI_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED4; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED5; + __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CONFIG; /*!< Configuration register */ +} NRF_SPI_Type; + + +/* ================================================================================ */ +/* ================ TWI ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI) + */ + +typedef struct { /*!< TWI Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ + __I uint32_t RESERVED4[4]; + __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or + received */ + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ + __I uint32_t RESERVED8[45]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED9[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED10[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED11[14]; + __IO uint32_t ENABLE; /*!< Enable TWI */ + __I uint32_t RESERVED12; + TWI_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED14; + __IO uint32_t FREQUENCY; /*!< TWI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED15[24]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWI_Type; + + +/* ================================================================================ */ +/* ================ NFCT ================ */ +/* ================================================================================ */ + + +/** + * @brief NFC-A compatible radio (NFCT) + */ + +typedef struct { /*!< NFCT Structure */ + __O uint32_t TASKS_ACTIVATE; /*!< Activate NFCT peripheral for incoming and outgoing frames, change + state to activated */ + __O uint32_t TASKS_DISABLE; /*!< Disable NFCT peripheral */ + __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */ + __O uint32_t TASKS_STARTTX; /*!< Start transmission of an outgoing frame, change state to transmit */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */ + __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */ + __I uint32_t RESERVED2[53]; + __IO uint32_t EVENTS_READY; /*!< The NFCT peripheral is ready to receive and send frames */ + __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */ + __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */ + __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */ + __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */ + __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */ + __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data has been checked (CRC, parity) and transferred + to RAM, and EasyDMA has ended accessing the RX buffer */ + __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details + on the source of the error. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains + details on the source of the error. */ + __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ + __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended + accessing the TX buffer */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */ + __I uint32_t RESERVED5[3]; + __IO uint32_t EVENTS_COLLISION; /*!< NFC auto collision resolution error reported. */ + __IO uint32_t EVENTS_SELECTED; /*!< NFC auto collision resolution successfully completed */ + __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */ + __I uint32_t RESERVED6[43]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED7[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED8[62]; + __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */ + __I uint32_t RESERVED9; + NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */ + __I uint32_t NFCTAGSTATE; /*!< NfcTag state register */ + __I uint32_t RESERVED10[10]; + __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */ + __I uint32_t RESERVED11[49]; + __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */ + __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */ + __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */ + __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */ + __IO uint32_t MAXLEN; /*!< Size of the RAM buffer allocated to TXD and RXD data storage + each */ + NFCT_TXD_Type TXD; /*!< Unspecified */ + NFCT_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED12[26]; + __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */ + __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */ + __IO uint32_t AUTOCOLRESCONFIG; /*!< Controls the auto collision resolution function. This setting + must be done before the NFCT peripheral is enabled. */ + __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */ + __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; + + +/* ================================================================================ */ +/* ================ GPIOTE ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< GPIOTE Structure */ + __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it high. */ + __I uint32_t RESERVED1[4]; + __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it low. */ + __I uint32_t RESERVED2[32]; + __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified + in CONFIG[0].PSEL */ + __I uint32_t RESERVED3[23]; + __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism + enabled */ + __I uint32_t RESERVED4[97]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[129]; + __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n] + and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; + + +/* ================================================================================ */ +/* ================ SAADC ================ */ +/* ================================================================================ */ + + +/** + * @brief Analog to Digital Converter (SAADC) + */ + +typedef struct { /*!< SAADC Structure */ + __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */ + __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */ + __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */ + __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */ + __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */ + __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode, + multiple conversions might be needed for a result to be transferred + to RAM. */ + __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */ + __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */ + __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */ + SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED1[106]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t STATUS; /*!< Status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t ENABLE; /*!< Enable or disable ADC */ + __I uint32_t RESERVED4[3]; + SAADC_CH_Type CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED5[24]; + __IO uint32_t RESOLUTION; /*!< Resolution configuration */ + __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined + with SCAN. The RESOLUTION is applied before averaging, thus + for high OVERSAMPLE a higher RESOLUTION should be used. */ + __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */ + __I uint32_t RESERVED6[12]; + SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */ +} NRF_SAADC_Type; + + +/* ================================================================================ */ +/* ================ TIMER ================ */ +/* ================================================================================ */ + + +/** + * @brief Timer/Counter 0 (TIMER) + */ + +typedef struct { /*!< TIMER Structure */ + __O uint32_t TASKS_START; /*!< Start Timer */ + __O uint32_t TASKS_STOP; /*!< Stop Timer */ + __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */ + __O uint32_t TASKS_CLEAR; /*!< Clear time */ + __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */ + __I uint32_t RESERVED0[11]; + __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */ + __I uint32_t RESERVED1[58]; + __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[42]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[61]; + __I uint32_t STATUS; /*!< Timer status */ + __I uint32_t RESERVED5[64]; + __IO uint32_t MODE; /*!< Timer mode selection */ + __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */ + __I uint32_t RESERVED6; + __IO uint32_t PRESCALER; /*!< Timer prescaler register */ + __I uint32_t RESERVED7[11]; + __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */ +} NRF_TIMER_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief Real time counter 0 (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __O uint32_t TASKS_START; /*!< Start RTC COUNTER */ + __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */ + __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */ + __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */ + __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */ + __I uint32_t RESERVED1[14]; + __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[109]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[13]; + __IO uint32_t EVTEN; /*!< Enable or disable event routing */ + __IO uint32_t EVTENSET; /*!< Enable event routing */ + __IO uint32_t EVTENCLR; /*!< Disable event routing */ + __I uint32_t RESERVED4[110]; + __I uint32_t COUNTER; /*!< Current COUNTER value */ + __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must + be written when RTC is stopped */ + __I uint32_t RESERVED5[13]; + __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */ +} NRF_RTC_Type; + + +/* ================================================================================ */ +/* ================ TEMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< TEMP Structure */ + __O uint32_t TASKS_START; /*!< Start temperature measurement */ + __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[127]; + __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */ + __I uint32_t RESERVED3[5]; + __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */ + __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */ + __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */ + __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */ + __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */ + __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */ + __I uint32_t RESERVED4[2]; + __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */ + __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */ + __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */ + __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */ + __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */ + __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */ + __I uint32_t RESERVED5[2]; + __IO uint32_t T0; /*!< End point of 1st piece wise linear function */ + __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */ + __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */ + __IO uint32_t T3; /*!< End point of 4th piece wise linear function */ + __IO uint32_t T4; /*!< End point of 5th piece wise linear function */ +} NRF_TEMP_Type; + + +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< RNG Structure */ + __O uint32_t TASKS_START; /*!< Task starting the random number generator */ + __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to + the VALUE register */ + __I uint32_t RESERVED1[63]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[126]; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t VALUE; /*!< Output random number */ +} NRF_RNG_Type; + + +/* ================================================================================ */ +/* ================ ECB ================ */ +/* ================================================================================ */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< ECB Structure */ + __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */ + __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */ + __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to + an error */ + __I uint32_t RESERVED1[127]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[126]; + __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */ +} NRF_ECB_Type; + + +/* ================================================================================ */ +/* ================ CCM ================ */ +/* ================================================================================ */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< CCM Structure */ + __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by + itself when completed. */ + __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself + when completed. */ + __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */ + __O uint32_t TASKS_RATEOVERRIDE; /*!< Override DATARATE setting in MODE register with the contents + of the RATEOVERRIDE register for any ongoing encryption/decryption */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */ + __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */ + __IO uint32_t EVENTS_ERROR; /*!< Deprecated register - CCM error event */ + __I uint32_t RESERVED1[61]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t MICSTATUS; /*!< MIC check result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable */ + __IO uint32_t MODE; /*!< Operation mode */ + __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */ + __IO uint32_t INPTR; /*!< Input pointer */ + __IO uint32_t OUTPTR; /*!< Output pointer */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ + __IO uint32_t MAXPACKETSIZE; /*!< Length of key-stream generated when MODE.LENGTH = Extended. */ + __IO uint32_t RATEOVERRIDE; /*!< Data rate override setting. */ +} NRF_CCM_Type; + + +/* ================================================================================ */ +/* ================ AAR ================ */ +/* ================================================================================ */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< AAR Structure */ + __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK + data structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ + __I uint32_t RESERVED1[61]; + __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ + __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ + __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t STATUS; /*!< Resolution status */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable AAR */ + __IO uint32_t NIRK; /*!< Number of IRKs */ + __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ + __I uint32_t RESERVED5; + __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ +} NRF_AAR_Type; + + +/* ================================================================================ */ +/* ================ WDT ================ */ +/* ================================================================================ */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< WDT Structure */ + __O uint32_t TASKS_START; /*!< Start the watchdog */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t RUNSTATUS; /*!< Run status */ + __I uint32_t REQSTATUS; /*!< Request status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t CRV; /*!< Counter reload value */ + __IO uint32_t RREN; /*!< Enable register for reload request registers */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED4[60]; + __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */ +} NRF_WDT_Type; + + +/* ================================================================================ */ +/* ================ QDEC ================ */ +/* ================================================================================ */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< QDEC Structure */ + __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */ + __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */ + __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */ + __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */ + __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */ + __I uint32_t RESERVED0[59]; + __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to + the SAMPLE register */ + __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */ + __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */ + __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */ + __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */ + __I uint32_t RESERVED1[59]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */ + __IO uint32_t LEDPOL; /*!< LED output pin polarity */ + __IO uint32_t SAMPLEPER; /*!< Sample period */ + __I int32_t SAMPLE; /*!< Motion sample value */ + __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events + can be generated */ + __I int32_t ACC; /*!< Register accumulating the valid transitions */ + __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC + task */ + QDEC_PSEL_Type PSEL; /*!< Unspecified */ + __IO uint32_t DBFEN; /*!< Enable input debounce filters */ + __I uint32_t RESERVED4[5]; + __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */ + __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */ + __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL + task */ +} NRF_QDEC_Type; + + +/* ================================================================================ */ +/* ================ COMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< COMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< COMP enable */ + __IO uint32_t PSEL; /*!< Pin select */ + __IO uint32_t REFSEL; /*!< Reference source select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[8]; + __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */ + __IO uint32_t MODE; /*!< Mode configuration */ + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ + __IO uint32_t ISOURCE; /*!< Current source select on analog input */ +} NRF_COMP_Type; + + +/* ================================================================================ */ +/* ================ LPCOMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Low Power Comparator (LPCOMP) + */ + +typedef struct { /*!< LPCOMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable LPCOMP */ + __IO uint32_t PSEL; /*!< Input pin select */ + __IO uint32_t REFSEL; /*!< Reference select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[4]; + __IO uint32_t ANADETECT; /*!< Analog detect configuration */ + __I uint32_t RESERVED6[5]; + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ +} NRF_LPCOMP_Type; + + +/* ================================================================================ */ +/* ================ SWI ================ */ +/* ================================================================================ */ + + +/** + * @brief Software interrupt 0 (SWI) + */ + +typedef struct { /*!< SWI Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_SWI_Type; + + +/* ================================================================================ */ +/* ================ EGU ================ */ +/* ================================================================================ */ + + +/** + * @brief Event Generator Unit 0 (EGU) + */ + +typedef struct { /*!< EGU Structure */ + __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding + TRIGGERED[0] event */ + __I uint32_t RESERVED0[48]; + __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering + the corresponding TRIGGER[0] task */ + __I uint32_t RESERVED1[112]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ +} NRF_EGU_Type; + + +/* ================================================================================ */ +/* ================ PWM ================ */ +/* ================================================================================ */ + + +/** + * @brief Pulse Width Modulation Unit 0 (PWM) + */ + +typedef struct { /*!< PWM Structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current + PWM period, and stops sequence playback */ + __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all + enabled channels from sequence 0, and starts playing that sequence + at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes + PWM generation to start it was not running. */ + __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels + if DECODER.MODE=NextStep. Does not cause PWM generation to start + it was not running. */ + __I uint32_t RESERVED1[60]; + __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer + generated */ + __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence + 0 */ + __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence + 0, when last value from RAM has been applied to wave counter */ + __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */ + __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times + defined in LOOP.CNT */ + __I uint32_t RESERVED2[56]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[125]; + __IO uint32_t ENABLE; /*!< PWM module enable register */ + __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */ + __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */ + __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */ + __IO uint32_t DECODER; /*!< Configuration of the decoder */ + __IO uint32_t LOOP; /*!< Amount of playback of a loop */ + __I uint32_t RESERVED5[2]; + PWM_SEQ_Type SEQ[2]; /*!< Unspecified */ + PWM_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_PWM_Type; + + +/* ================================================================================ */ +/* ================ PDM ================ */ +/* ================================================================================ */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< PDM Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */ + __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */ + __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */ + __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT + (or the last sample after a STOP task has been received) to + Data RAM */ + __I uint32_t RESERVED1[125]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< PDM module enable register */ + __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */ + __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */ + __I uint32_t RESERVED3[3]; + __IO uint32_t GAINL; /*!< Left output gain adjustment */ + __IO uint32_t GAINR; /*!< Right output gain adjustment */ + __IO uint32_t RATIO; /*!< Selects the ratio between PDM_CLK and output sample rate. Change + PDMCLKCTRL accordingly. */ + __I uint32_t RESERVED4[7]; + PDM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED5[6]; + PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */ +} NRF_PDM_Type; + + +/* ================================================================================ */ +/* ================ NVMC ================ */ +/* ================================================================================ */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< NVMC Structure */ + __I uint32_t RESERVED0[256]; + __I uint32_t READY; /*!< Ready flag */ + __I uint32_t RESERVED1[64]; + __IO uint32_t CONFIG; /*!< Configuration register */ + + union { + __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */ + }; + __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */ + __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */ + __I uint32_t RESERVED2[10]; + __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */ + __I uint32_t RESERVED3; + __IO uint32_t IHIT; /*!< I-Code cache hit counter. */ + __IO uint32_t IMISS; /*!< I-Code cache miss counter. */ +} NRF_NVMC_Type; + + +/* ================================================================================ */ +/* ================ ACL ================ */ +/* ================================================================================ */ + + +/** + * @brief Access control lists (ACL) + */ + +typedef struct { /*!< ACL Structure */ + __I uint32_t RESERVED0[449]; + __IO uint32_t DISABLEINDEBUG; /*!< Disable all ACL protection mechanisms for regions while in debug + mode */ + __I uint32_t RESERVED1[62]; + ACL_ACL_Type ACL[8]; /*!< Unspecified */ +} NRF_ACL_Type; + + +/* ================================================================================ */ +/* ================ PPI ================ */ +/* ================================================================================ */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< PPI Structure */ + PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */ + __I uint32_t RESERVED0[308]; + __IO uint32_t CHEN; /*!< Channel enable register */ + __IO uint32_t CHENSET; /*!< Channel enable set register */ + __IO uint32_t CHENCLR; /*!< Channel enable clear register */ + __I uint32_t RESERVED1; + PPI_CH_Type CH[20]; /*!< PPI Channel */ + __I uint32_t RESERVED2[148]; + __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */ + __I uint32_t RESERVED3[62]; + PPI_FORK_Type FORK[32]; /*!< Fork */ +} NRF_PPI_Type; + + +/* ================================================================================ */ +/* ================ MWU ================ */ +/* ================================================================================ */ + + +/** + * @brief Memory Watch Unit (MWU) + */ + +typedef struct { /*!< MWU Structure */ + __I uint32_t RESERVED0[64]; + MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED1[16]; + MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED2[100]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[5]; + __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */ + __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */ + __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */ + __I uint32_t RESERVED4[53]; + MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED5[64]; + __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */ + __IO uint32_t REGIONENSET; /*!< Enable regions watch */ + __IO uint32_t REGIONENCLR; /*!< Disable regions watch */ + __I uint32_t RESERVED6[57]; + MWU_REGION_Type REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED7[32]; + MWU_PREGION_Type PREGION[2]; /*!< Unspecified */ +} NRF_MWU_Type; + + +/* ================================================================================ */ +/* ================ I2S ================ */ +/* ================================================================================ */ + + +/** + * @brief Inter-IC Sound (I2S) + */ + +typedef struct { /*!< I2S Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when + this is enabled. */ + __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this + task will cause the {event:STOPPED} event to be generated. */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __I uint32_t RESERVED2[122]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable I2S module. */ + I2S_CONFIG_Type CONFIG; /*!< Unspecified */ + __I uint32_t RESERVED4[3]; + I2S_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED5; + I2S_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED6[3]; + I2S_RXTXD_Type RXTXD; /*!< Unspecified */ + __I uint32_t RESERVED7[3]; + I2S_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_I2S_Type; + + +/* ================================================================================ */ +/* ================ FPU ================ */ +/* ================================================================================ */ + + +/** + * @brief FPU (FPU) + */ + +typedef struct { /*!< FPU Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_FPU_Type; + + +/* ================================================================================ */ +/* ================ USBD ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Serial Bus device (USBD) + */ + +typedef struct { /*!< USBD Structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTEPIN[8]; /*!< Description collection[0]: Captures the EPIN[0].PTR, EPIN[0].MAXCNT + and EPIN[0].CONFIG registers values, and enables endpoint IN + 0 to respond to traffic from host */ + __O uint32_t TASKS_STARTISOIN; /*!< Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers + values, and enables sending data on iso endpoint */ + __O uint32_t TASKS_STARTEPOUT[8]; /*!< Description collection[0]: Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT + and EPOUT[0].CONFIG registers values, and enables endpoint 0 + to respond to traffic from host */ + __O uint32_t TASKS_STARTISOOUT; /*!< Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers + values, and enables receiving of data on iso endpoint */ + __O uint32_t TASKS_EP0RCVOUT; /*!< Allows OUT data stage on control endpoint 0 */ + __O uint32_t TASKS_EP0STATUS; /*!< Allows status stage on control endpoint 0 */ + __O uint32_t TASKS_EP0STALL; /*!< STALLs data and status stage on control endpoint 0 */ + __O uint32_t TASKS_DPDMDRIVE; /*!< Forces D+ and D-lines to the state defined in the DPDMVALUE + register */ + __O uint32_t TASKS_DPDMNODRIVE; /*!< Stops forcing D+ and D- lines to any state (USB engine takes + control) */ + __I uint32_t RESERVED1[40]; + __IO uint32_t EVENTS_USBRESET; /*!< Signals that a USB reset condition has been detected on the + USB lines */ + __IO uint32_t EVENTS_STARTED; /*!< Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG, + or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers + have been captured on all endpoints reported in the EPSTATUS + register */ + __IO uint32_t EVENTS_ENDEPIN[8]; /*!< Description collection[0]: The whole EPIN[0] buffer has been + consumed. The RAM buffer can be accessed safely by software. */ + __IO uint32_t EVENTS_EP0DATADONE; /*!< An acknowledged data transfer has taken place on the control + endpoint */ + __IO uint32_t EVENTS_ENDISOIN; /*!< The whole ISOIN buffer has been consumed. The RAM buffer can + be accessed safely by software. */ + __IO uint32_t EVENTS_ENDEPOUT[8]; /*!< Description collection[0]: The whole EPOUT[0] buffer has been + consumed. The RAM buffer can be accessed safely by software. */ + __IO uint32_t EVENTS_ENDISOOUT; /*!< The whole ISOOUT buffer has been consumed. The RAM buffer can + be accessed safely by software. */ + __IO uint32_t EVENTS_SOF; /*!< Signals that a SOF (start of frame) condition has been detected + on the USB lines */ + __IO uint32_t EVENTS_USBEVENT; /*!< An event or an error not covered by specific events has occurred, + check EVENTCAUSE register to find the cause */ + __IO uint32_t EVENTS_EP0SETUP; /*!< A valid SETUP token has been received (and acknowledged) on + the control endpoint */ + __IO uint32_t EVENTS_EPDATA; /*!< A data transfer has occurred on a data endpoint, indicated by + the EPDATASTATUS register */ + __IO uint32_t EVENTS_ACCESSFAULT; /*!< Access to an unavailable USB register has been attempted (software + or EasyDMA). This event can get fired even when USBD is not + ENABLEd. */ + __I uint32_t RESERVED2[38]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[61]; + __IO uint32_t EVENTCAUSE; /*!< Details on event that caused the USBEVENT event */ + __I uint32_t BUSSTATE; /*!< Provides the logic state of the D+ and D- lines */ + __I uint32_t RESERVED5[6]; + USBD_HALTED_Type HALTED; /*!< Unspecified */ + __I uint32_t RESERVED6; + __IO uint32_t EPSTATUS; /*!< Provides information on which endpoint's EasyDMA registers have + been captured */ + __IO uint32_t EPDATASTATUS; /*!< Provides information on which endpoint(s) an acknowledged data + transfer has occurred (EPDATA event) */ + __I uint32_t USBADDR; /*!< Device USB address */ + __I uint32_t RESERVED7[3]; + __I uint32_t BMREQUESTTYPE; /*!< SETUP data, byte 0, bmRequestType */ + __I uint32_t BREQUEST; /*!< SETUP data, byte 1, bRequest */ + __I uint32_t WVALUEL; /*!< SETUP data, byte 2, LSB of wValue */ + __I uint32_t WVALUEH; /*!< SETUP data, byte 3, MSB of wValue */ + __I uint32_t WINDEXL; /*!< SETUP data, byte 4, LSB of wIndex */ + __I uint32_t WINDEXH; /*!< SETUP data, byte 5, MSB of wIndex */ + __I uint32_t WLENGTHL; /*!< SETUP data, byte 6, LSB of wLength */ + __I uint32_t WLENGTHH; /*!< SETUP data, byte 7, MSB of wLength */ + USBD_SIZE_Type SIZE; /*!< Unspecified */ + __I uint32_t RESERVED8[15]; + __IO uint32_t ENABLE; /*!< Enable USB */ + __IO uint32_t USBPULLUP; /*!< Control of the USB pull-up */ + __IO uint32_t DPDMVALUE; /*!< State at which the DPDMDRIVE task will force D+ and D-. The + DPDMNODRIVE task reverts the control of the lines to MAC IP + (no forcing). */ + __IO uint32_t DTOGGLE; /*!< Data toggle control and status. */ + __IO uint32_t EPINEN; /*!< Endpoint IN enable */ + __IO uint32_t EPOUTEN; /*!< Endpoint OUT enable */ + __O uint32_t EPSTALL; /*!< STALL endpoints */ + __IO uint32_t ISOSPLIT; /*!< Controls the split of ISO buffers */ + __I uint32_t FRAMECNTR; /*!< Returns the current value of the start of frame counter */ + __I uint32_t RESERVED9[3]; + __IO uint32_t ISOINCONFIG; /*!< Controls the response of the ISO IN endpoint to an IN token + when no data is ready to be sent */ + __I uint32_t RESERVED10[51]; + USBD_EPIN_Type EPIN[8]; /*!< Unspecified */ + USBD_ISOIN_Type ISOIN; /*!< Unspecified */ + __I uint32_t RESERVED11[21]; + USBD_EPOUT_Type EPOUT[8]; /*!< Unspecified */ + USBD_ISOOUT_Type ISOOUT; /*!< Unspecified */ +} NRF_USBD_Type; + + +/* ================================================================================ */ +/* ================ QSPI ================ */ +/* ================================================================================ */ + + +/** + * @brief External flash interface (QSPI) + */ + +typedef struct { /*!< QSPI Structure */ + __O uint32_t TASKS_ACTIVATE; /*!< Activate QSPI interface */ + __O uint32_t TASKS_READSTART; /*!< Start transfer from external flash memory to internal RAM */ + __O uint32_t TASKS_WRITESTART; /*!< Start transfer from internal RAM to external flash memory */ + __O uint32_t TASKS_ERASESTART; /*!< Start external flash memory erase operation */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_READY; /*!< QSPI peripheral is ready. This event will be generated as a + response to any QSPI task. */ + __I uint32_t RESERVED1[127]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable QSPI peripheral and acquire the pins selected in PSELn + registers */ + QSPI_READ_Type READ; /*!< Unspecified */ + QSPI_WRITE_Type WRITE; /*!< Unspecified */ + QSPI_ERASE_Type ERASE; /*!< Unspecified */ + QSPI_PSEL_Type PSEL; /*!< Unspecified */ + __IO uint32_t XIPOFFSET; /*!< Address offset into the external memory for Execute in Place + operation. */ + __IO uint32_t IFCONFIG0; /*!< Interface configuration. */ + __I uint32_t RESERVED3[46]; + __IO uint32_t IFCONFIG1; /*!< Interface configuration. */ + __I uint32_t STATUS; /*!< Status register. */ + __I uint32_t RESERVED4[3]; + __IO uint32_t DPMDUR; /*!< Set the duration required to enter/exit deep power-down mode + (DPM). */ + __I uint32_t RESERVED5[3]; + __IO uint32_t ADDRCONF; /*!< Extended address configuration. */ + __I uint32_t RESERVED6[3]; + __IO uint32_t CINSTRCONF; /*!< Custom instruction configuration register. */ + __IO uint32_t CINSTRDAT0; /*!< Custom instruction data register 0. */ + __IO uint32_t CINSTRDAT1; /*!< Custom instruction data register 1. */ + __IO uint32_t IFTIMING; /*!< SPI interface timing. */ +} NRF_QSPI_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO Port 1 (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __I uint32_t RESERVED0[321]; + __IO uint32_t OUT; /*!< Write GPIO port */ + __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */ + __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */ + __I uint32_t IN; /*!< Read GPIO port */ + __IO uint32_t DIR; /*!< Direction of GPIO pins */ + __IO uint32_t DIRSET; /*!< DIR set register */ + __IO uint32_t DIRCLR; /*!< DIR clear register */ + __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria + set in the PIN_CNF[n].SENSE registers */ + __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */ + __I uint32_t RESERVED1[118]; + __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */ +} NRF_GPIO_Type; + + +/* ================================================================================ */ +/* ================ CRYPTOCELL ================ */ +/* ================================================================================ */ + + +/** + * @brief ARM CryptoCell register interface (CRYPTOCELL) + */ + +typedef struct { /*!< CRYPTOCELL Structure */ + __I uint32_t RESERVED0[320]; + __IO uint32_t ENABLE; /*!< Control power and clock for ARM CryptoCell subsystem */ +} NRF_CRYPTOCELL_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_ACL_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_USBD_BASE 0x40027000UL +#define NRF_UARTE1_BASE 0x40028000UL +#define NRF_QSPI_BASE 0x40029000UL +#define NRF_SPIM3_BASE 0x4002B000UL +#define NRF_PWM3_BASE 0x4002D000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_P1_BASE 0x50000300UL +#define NRF_CRYPTOCELL_BASE 0x5002A000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) +#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) +#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) +#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE) +#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) +#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) +#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) +#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) +#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) +#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE) +#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) +#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) +#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) +#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) +#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) +#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) +#define NRF_ACL ((NRF_ACL_Type *) NRF_ACL_BASE) +#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE) +#define NRF_USBD ((NRF_USBD_Type *) NRF_USBD_BASE) +#define NRF_UARTE1 ((NRF_UARTE_Type *) NRF_UARTE1_BASE) +#define NRF_QSPI ((NRF_QSPI_Type *) NRF_QSPI_BASE) +#define NRF_SPIM3 ((NRF_SPIM_Type *) NRF_SPIM3_BASE) +#define NRF_PWM3 ((NRF_PWM_Type *) NRF_PWM3_BASE) +#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE) +#define NRF_P1 ((NRF_GPIO_Type *) NRF_P1_BASE) +#define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type *) NRF_CRYPTOCELL_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group nrf52840 */ +/** @} */ /* End of group Nordic Semiconductor */ + +#ifdef __cplusplus +} +#endif + + +#endif /* nrf52840_H */ + diff --git a/nrf5/device/nrf52/nrf52840_bitfields.h b/nrf5/device/nrf52/nrf52840_bitfields.h new file mode 100644 index 0000000000..17f63b4ec2 --- /dev/null +++ b/nrf5/device/nrf52/nrf52840_bitfields.h @@ -0,0 +1,14633 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __NRF52840_BITS_H +#define __NRF52840_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for END event */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for END event */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: ACL */ +/* Description: Access control lists */ + +/* Register: ACL_DISABLEINDEBUG */ +/* Description: Disable all ACL protection mechanisms for regions while in debug mode */ + +/* Bit 0 : Disable the protection mechanism for regions while in debug mode. */ +#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << ACL_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< ACL is enabled in debug mode */ +#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< ACL is disabled in debug mode */ + +/* Register: ACL_ACL_ADDR */ +/* Description: Description cluster[0]: Configure the word-aligned start address of region 0 to protect */ + +/* Bits 31..0 : Valid word-aligned start address of region 0 to protect. Address must point to a flash page boundary. */ +#define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ +#define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + +/* Register: ACL_ACL_SIZE */ +/* Description: Description cluster[0]: Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect. */ + +/* Bits 31..0 : Size of flash region 0 in bytes. Must be a multiple of the flash page size. */ +#define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: ACL_ACL_PERM */ +/* Description: Description cluster[0]: Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE */ + +/* Bit 2 : Configure read permissions for region 0. Write '0' has no effect. */ +#define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ +#define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region 0 */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region 0 */ + +/* Bit 1 : Configure write and erase permissions for region 0. Write '0' has no effect. */ +#define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ +#define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region 0 */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region 0 */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for ERROR event */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for ERROR event */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packets up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packets up to MAXPACKETSIZE bytes will be generated. */ + +/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ + +/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + +/* Register: CCM_MAXPACKETSIZE */ +/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ + +/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet to be encrypted/decrypted. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ + +/* Register: CCM_RATEOVERRIDE */ +/* Description: Data rate override setting. */ + +/* Bits 1..0 : Data rate override setting. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for CTTO event */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DONE event */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for CTTO event */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DONE event */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ +#define CLOCK_LFCLKSTAT_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ +#define CLOCK_LFCLKSRCCOPY_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ +#define CLOCK_LFCLKSRC_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_TRACECONFIG */ +/* Description: Clocking options for the Trace Port debug interface */ + +/* Bits 17..16 : Pin multiplexing of trace signals. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */ + +/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for CROSS event */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for UP event */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for DOWN event */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation mode */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power mode */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + +/* Register: COMP_ISOURCE */ +/* Description: Current source select on analog input */ + +/* Bits 1..0 : Comparator hysteresis */ +#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */ +#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */ + + +/* Peripheral: CRYPTOCELL */ +/* Description: ARM CryptoCell register interface */ + +/* Register: CRYPTOCELL_ENABLE */ +/* Description: Control power and clock for ARM CryptoCell subsystem */ + +/* Bit 0 : Enable or disable the CryptoCell subsystem */ +#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CryptoCell subsystem disabled */ +#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CryptoCell subsystem enabled */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event Generator Unit 0 */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory Information Configuration Registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection[0]: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection[0]: Encryption root, word 0 */ + +/* Bits 31..0 : Encryption root, word 0 */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection[0]: Identity Root, word 0 */ + +/* Bits 31..0 : Identity Root, word 0 */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection[0]: Device address 0 */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part variant (hardware version and production configuration). */ + +/* Bits 31..0 : Part variant (hardware version and production configuration). Encoded as ASCII. */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ +#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ +#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_ABBA (0x41424241UL) /*!< ABBA */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ +#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */ +#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: y-intercept B0. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: y-intercept B1. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: y-intercept B2. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: y-intercept B3. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: y-intercept B4. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: y-intercept B5. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_NFC_TAGHEADER0 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 3 */ +#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ +#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ + +/* Bits 23..16 : Unique identifier byte 2 */ +#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ +#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ + +/* Bits 15..8 : Unique identifier byte 1 */ +#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ +#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ + +/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ +#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ +#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ + +/* Register: FICR_NFC_TAGHEADER1 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 7 */ +#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ +#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ + +/* Bits 23..16 : Unique identifier byte 6 */ +#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ +#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ + +/* Bits 15..8 : Unique identifier byte 5 */ +#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ +#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ + +/* Bits 7..0 : Unique identifier byte 4 */ +#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ +#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ + +/* Register: FICR_NFC_TAGHEADER2 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 11 */ +#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ +#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ + +/* Bits 23..16 : Unique identifier byte 10 */ +#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ +#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ + +/* Bits 15..8 : Unique identifier byte 9 */ +#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ +#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ + +/* Bits 7..0 : Unique identifier byte 8 */ +#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ +#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ + +/* Register: FICR_NFC_TAGHEADER3 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 15 */ +#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ +#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ + +/* Bits 23..16 : Unique identifier byte 14 */ +#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ +#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ + +/* Bits 15..8 : Unique identifier byte 13 */ +#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ +#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ + +/* Bits 7..0 : Unique identifier byte 12 */ +#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ +#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to Enable interrupt for PORT event */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to Disable interrupt for PORT event */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bits 14..13 : Port number */ +#define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */ +#define GPIOTE_CONFIG_PORT_Msk (0x3UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: I2S */ +/* Description: Inter-IC Sound */ + +/* Register: I2S_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ +#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for STOPPED event */ +#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ +#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */ +#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */ +#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */ +#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ + +/* Register: I2S_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */ +#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */ +#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */ +#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Register: I2S_ENABLE */ +/* Description: Enable I2S module. */ + +/* Bit 0 : Enable I2S module. */ +#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_CONFIG_MODE */ +/* Description: I2S mode. */ + +/* Bit 0 : I2S mode. */ +#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ +#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ + +/* Register: I2S_CONFIG_RXEN */ +/* Description: Reception (RX) enable. */ + +/* Bit 0 : Reception (RX) enable. */ +#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ +#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: I2S_CONFIG_TXEN */ +/* Description: Transmission (TX) enable. */ + +/* Bit 0 : Transmission (TX) enable. */ +#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ +#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ + +/* Register: I2S_CONFIG_MCKEN */ +/* Description: Master clock generator enable. */ + +/* Bit 0 : Master clock generator enable. */ +#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ +#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ + +/* Register: I2S_CONFIG_MCKFREQ */ +/* Description: Master clock generator frequency. */ + +/* Bits 31..0 : Master clock generator frequency. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ + +/* Register: I2S_CONFIG_RATIO */ +/* Description: MCK / LRCK ratio. */ + +/* Bits 3..0 : MCK / LRCK ratio. */ +#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ +#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ +#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ +#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ +#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ +#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ +#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ +#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ +#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ + +/* Register: I2S_CONFIG_SWIDTH */ +/* Description: Sample width. */ + +/* Bits 1..0 : Sample width. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ + +/* Register: I2S_CONFIG_ALIGN */ +/* Description: Alignment of sample within a frame. */ + +/* Bit 0 : Alignment of sample within a frame. */ +#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ + +/* Register: I2S_CONFIG_FORMAT */ +/* Description: Frame format. */ + +/* Bit 0 : Frame format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ + +/* Register: I2S_CONFIG_CHANNELS */ +/* Description: Enable channels. */ + +/* Bits 1..0 : Enable channels. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ + +/* Register: I2S_RXD_PTR */ +/* Description: Receive buffer RAM start address. */ + +/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ +#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_TXD_PTR */ +/* Description: Transmit buffer RAM start address. */ + +/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ +#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_RXTXD_MAXCNT */ +/* Description: Size of RXD and TXD buffers. */ + +/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: I2S_PSEL_MCK */ +/* Description: Pin select for MCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 9..8 : Port number */ +#define I2S_PSEL_MCK_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_MCK_PORT_Msk (0x3UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SCK */ +/* Description: Pin select for SCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 9..8 : Port number */ +#define I2S_PSEL_SCK_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SCK_PORT_Msk (0x3UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_LRCK */ +/* Description: Pin select for LRCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 9..8 : Port number */ +#define I2S_PSEL_LRCK_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_LRCK_PORT_Msk (0x3UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDIN */ +/* Description: Pin select for SDIN signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 9..8 : Port number */ +#define I2S_PSEL_SDIN_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SDIN_PORT_Msk (0x3UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDOUT */ +/* Description: Pin select for SDOUT signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 9..8 : Port number */ +#define I2S_PSEL_SDOUT_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SDOUT_PORT_Msk (0x3UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low Power Comparator */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: LPCOMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable LPCOMP */ + +/* Bits 1..0 : Enable or disable LPCOMP */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select */ + +/* Bits 2..0 : Analog pin select */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select */ + +/* Bits 3..0 : Reference select */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */ +#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration */ + +/* Bits 1..0 : Analog detect configuration */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */ + +/* Register: LPCOMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis enable */ +#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */ + + +/* Peripheral: MWU */ +/* Description: Memory Watch Unit */ + +/* Register: MWU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ +#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ +#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ +#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ +#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ +#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ +#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ +#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ +#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ +#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ +#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ +#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ +#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */ +#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */ +#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */ +#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */ +#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */ +#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */ +#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */ +#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */ +#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */ +#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */ +#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */ +#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */ +#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */ +#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */ +#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */ +#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */ +#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */ +#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */ +#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */ +#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */ +#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */ +#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */ +#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */ +#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */ +#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_NMIEN */ +/* Description: Enable or disable non-maskable interrupt */ + +/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_NMIENSET */ +/* Description: Enable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_NMIENCLR */ +/* Description: Disable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_PERREGION_SUBSTATWA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Register: MWU_PERREGION_SUBSTATRA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Register: MWU_REGIONEN */ +/* Description: Enable/disable regions watch */ + +/* Bit 27 : Enable/disable read access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable/disable write access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable/disable read access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable/disable write access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable/disable read access watch in region[3] */ +#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable/disable write access watch in region[3] */ +#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable/disable read access watch in region[2] */ +#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable/disable write access watch in region[2] */ +#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable/disable read access watch in region[1] */ +#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable/disable write access watch in region[1] */ +#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable/disable read access watch in region[0] */ +#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable/disable write access watch in region[0] */ +#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENSET */ +/* Description: Enable regions watch */ + +/* Bit 27 : Enable read access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable write access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable read access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable write access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable read access watch in region[3] */ +#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable write access watch in region[3] */ +#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable read access watch in region[2] */ +#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable write access watch in region[2] */ +#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable read access watch in region[1] */ +#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable write access watch in region[1] */ +#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable read access watch in region[0] */ +#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable write access watch in region[0] */ +#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENCLR */ +/* Description: Disable regions watch */ + +/* Bit 27 : Disable read access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 26 : Disable write access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 25 : Disable read access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 24 : Disable write access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 7 : Disable read access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 6 : Disable write access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 5 : Disable read access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 4 : Disable write access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 3 : Disable read access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 2 : Disable write access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 1 : Disable read access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 0 : Disable write access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Register: MWU_REGION_START */ +/* Description: Description cluster[0]: Start address for region 0 */ + +/* Bits 31..0 : Start address for region */ +#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_REGION_END */ +/* Description: Description cluster[0]: End address of region 0 */ + +/* Bits 31..0 : End address of region. */ +#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_START */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_PREGION_END */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_SUBS */ +/* Description: Description cluster[0]: Subregions of region 0 */ + +/* Bit 31 : Include or exclude subregion 31 in region */ +#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude subregion 30 in region */ +#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude subregion 29 in region */ +#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude subregion 28 in region */ +#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude subregion 27 in region */ +#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude subregion 26 in region */ +#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude subregion 25 in region */ +#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude subregion 24 in region */ +#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude subregion 23 in region */ +#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude subregion 22 in region */ +#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude subregion 21 in region */ +#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude subregion 20 in region */ +#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude subregion 19 in region */ +#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude subregion 18 in region */ +#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude subregion 17 in region */ +#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude subregion 16 in region */ +#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude subregion 15 in region */ +#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude subregion 14 in region */ +#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude subregion 13 in region */ +#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude subregion 12 in region */ +#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude subregion 11 in region */ +#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude subregion 10 in region */ +#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude subregion 9 in region */ +#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude subregion 8 in region */ +#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude subregion 7 in region */ +#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude subregion 6 in region */ +#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude subregion 5 in region */ +#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude subregion 4 in region */ +#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude subregion 3 in region */ +#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude subregion 2 in region */ +#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude subregion 1 in region */ +#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude subregion 0 in region */ +#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */ + + +/* Peripheral: NFCT */ +/* Description: NFC-A compatible radio */ + +/* Register: NFCT_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 5 : Shortcut between TXFRAMEEND event and ENABLERXDATA task */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: NFCT_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 20 : Enable or disable interrupt for STARTED event */ +#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for SELECTED event */ +#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for COLLISION event */ +#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for ENDTX event */ +#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for ENDRX event */ +#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for RXERROR event */ +#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for ERROR event */ +#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ +#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ +#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ +#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ +#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ +#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ +#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: NFCT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 20 : Write '1' to Enable interrupt for STARTED event */ +#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */ +#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */ +#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */ +#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */ +#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */ +#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for ERROR event */ +#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */ +#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */ +#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */ +#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */ +#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */ +#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */ +#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: NFCT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 20 : Write '1' to Disable interrupt for STARTED event */ +#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */ +#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */ +#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */ +#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */ +#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */ +#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for ERROR event */ +#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */ +#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */ +#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */ +#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */ +#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */ +#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */ +#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: NFCT_ERRORSTATUS */ +/* Description: NFC Error Status register */ + +/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */ + +/* Register: NFCT_FRAMESTATUS_RX */ +/* Description: Result of last incoming frame */ + +/* Bit 3 : Overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */ + +/* Bit 2 : Parity status of received frame */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */ + +/* Bit 0 : No valid end of frame (EoF) detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ + +/* Register: NFCT_NFCTAGSTATE */ +/* Description: NfcTag state register */ + +/* Bits 2..0 : NfcTag state */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL) /*!< Idle */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL) /*!< Receive */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */ + +/* Register: NFCT_FIELDPRESENT */ +/* Description: Indicates the presence or not of a valid field */ + +/* Bit 1 : Indicates if the low level has locked to the field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */ + +/* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */ + +/* Register: NFCT_FRAMEDELAYMIN */ +/* Description: Minimum frame delay */ + +/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ + +/* Register: NFCT_FRAMEDELAYMAX */ +/* Description: Maximum frame delay */ + +/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ + +/* Register: NFCT_FRAMEDELAYMODE */ +/* Description: Configuration register for the Frame Delay Timer */ + +/* Bits 1..0 : Configuration register for the Frame Delay Timer */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */ + +/* Register: NFCT_PACKETPTR */ +/* Description: Packet pointer for TXD and RXD data storage in Data RAM */ + +/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */ +#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: NFCT_MAXLEN */ +/* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */ + +/* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */ +#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: NFCT_TXD_FRAMECONFIG */ +/* Description: Configuration of outgoing frames */ + +/* Bit 4 : CRC mode for outgoing frames */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */ + +/* Bit 2 : Adding SoF or not in TX frames */ +#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol not added */ +#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol added */ + +/* Bit 1 : Discarding unused bits at start or end of a frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits are discarded at end of frame (EoF) */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits are discarded at start of frame (SoF) */ + +/* Bit 0 : Indicates if parity is added to the frame */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added to TX frames */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added to TX frames */ + +/* Register: NFCT_TXD_AMOUNT */ +/* Description: Size of outgoing frame */ + +/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ + +/* Register: NFCT_RXD_FRAMECONFIG */ +/* Description: Configuration of incoming frames */ + +/* Bit 4 : CRC mode for incoming frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */ + +/* Bit 2 : SoF expected or not in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol is expected in RX frames */ + +/* Bit 0 : Indicates if parity expected in RX frame */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */ + +/* Register: NFCT_RXD_AMOUNT */ +/* Description: Size of last incoming frame */ + +/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ + +/* Register: NFCT_NFCID1_LAST */ +/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */ + +/* Bits 31..24 : NFCID1 byte W */ +#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */ +#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */ + +/* Bits 23..16 : NFCID1 byte X */ +#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */ +#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */ + +/* Bits 15..8 : NFCID1 byte Y */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */ + +/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */ + +/* Register: NFCT_NFCID1_2ND_LAST */ +/* Description: Second last NFCID1 part (7 or 10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte T */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */ + +/* Bits 15..8 : NFCID1 byte U */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */ + +/* Bits 7..0 : NFCID1 byte V */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */ + +/* Register: NFCT_NFCID1_3RD_LAST */ +/* Description: Third last NFCID1 part (10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte Q */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */ + +/* Bits 15..8 : NFCID1 byte R */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */ + +/* Bits 7..0 : NFCID1 byte S */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ + +/* Register: NFCT_AUTOCOLRESCONFIG */ +/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. */ + +/* Bit 0 : Enables/disables auto collision resolution */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */ + +/* Register: NFCT_SENSRES */ +/* Description: NFC-A SENS_RES auto-response settings */ + +/* Bits 15..12 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ +#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ + +/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ +#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ + +/* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */ +#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */ + +/* Bit 5 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ +#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ + +/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */ + +/* Register: NFCT_SELRES */ +/* Description: NFC-A SEL_RES auto-response settings */ + +/* Bit 7 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ +#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ + +/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ +#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + +/* Bits 4..3 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ +#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ + +/* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */ +#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ + +/* Bits 1..0 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ +#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in Code area */ + +/* Bits 31..0 : Register for starting erase of a page in Code area */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing User Information Configuration Registers */ + +/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ICACHECNF */ +/* Description: I-Code cache configuration register. */ + +/* Bit 8 : Cache profiling enable */ +#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ + +/* Bit 0 : Cache enable */ +#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ +#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ + +/* Register: NVMC_IHIT */ +/* Description: I-Code cache hit counter. */ + +/* Bits 31..0 : Number of cache hits */ +#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ +#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ + +/* Register: NVMC_IMISS */ +/* Description: I-Code cache miss counter. */ + +/* Bits 31..0 : Number of cache misses */ +#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ +#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port 1 */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection[0]: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for END event */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for END event */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for END event */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */ +#define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_RATIO */ +/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ + +/* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */ +#define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */ +#define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define PDM_PSEL_CLK_PORT_Msk (0x3UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define PDM_PSEL_DIN_PORT_Msk (0x3UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 9 : Write '1' to Enable interrupt for USBPWRRDY event */ +#define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ +#define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ +#define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for USBREMOVED event */ +#define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ +#define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ +#define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for USBDETECTED event */ +#define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ +#define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ +#define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 9 : Write '1' to Disable interrupt for USBPWRRDY event */ +#define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ +#define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ +#define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for USBREMOVED event */ +#define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ +#define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ +#define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for USBDETECTED event */ +#define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ +#define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ +#define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 20 : Reset due to wake up from System OFF mode by Vbus rising into valid range */ +#define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */ +#define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */ +#define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */ + +/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */ +#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */ +#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ +#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Deprecated register - RAM status register */ + +/* Bit 3 : RAM block 3 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */ + +/* Bit 2 : RAM block 2 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */ + +/* Bit 1 : RAM block 1 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ + +/* Bit 0 : RAM block 0 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ + +/* Register: POWER_USBREGSTATUS */ +/* Description: USB supply status */ + +/* Bit 1 : USB supply output settling time elapsed */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */ +#define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */ + +/* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */ +#define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */ +#define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */ +#define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */ +#define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power failure comparator configuration */ + +/* Bits 11..8 : Power failure comparator threshold setting for voltage supply on VDDH */ +#define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */ +#define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */ +#define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */ +#define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */ +#define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */ +#define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */ +#define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */ +#define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */ +#define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */ +#define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */ +#define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */ +#define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */ +#define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */ +#define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */ +#define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */ +#define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */ +#define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */ + +/* Bits 4..1 : Power failure comparator threshold setting */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure comparator */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_DCDCEN */ +/* Description: Enable DC/DC converter for REG1 stage. */ + +/* Bit 0 : Enable DC/DC converter for REG1 stage. */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_DCDCEN0 */ +/* Description: Enable DC/DC converter for REG0 stage. */ + +/* Bit 0 : Enable DC/DC converter for REG0 stage. */ +#define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN0_DCDCEN_Msk (0x1UL << POWER_DCDCEN0_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN0_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN0_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_MAINREGSTATUS */ +/* Description: Main supply status */ + +/* Bit 0 : Main supply status */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster[0]: RAM0 power control register */ + +/* Bit 31 : Keep retention on RAM section S15 when RAM section is in OFF */ +#define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ +#define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ +#define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */ + +/* Bit 30 : Keep retention on RAM section S14 when RAM section is in OFF */ +#define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ +#define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ +#define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */ + +/* Bit 29 : Keep retention on RAM section S13 when RAM section is in OFF */ +#define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ +#define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ +#define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */ + +/* Bit 28 : Keep retention on RAM section S12 when RAM section is in OFF */ +#define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ +#define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ +#define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */ + +/* Bit 27 : Keep retention on RAM section S11 when RAM section is in OFF */ +#define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ +#define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ +#define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */ + +/* Bit 26 : Keep retention on RAM section S10 when RAM section is in OFF */ +#define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ +#define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ +#define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */ + +/* Bit 25 : Keep retention on RAM section S9 when RAM section is in OFF */ +#define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ +#define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ +#define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */ + +/* Bit 24 : Keep retention on RAM section S8 when RAM section is in OFF */ +#define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ +#define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ +#define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */ + +/* Bit 23 : Keep retention on RAM section S7 when RAM section is in OFF */ +#define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ +#define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ +#define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */ + +/* Bit 22 : Keep retention on RAM section S6 when RAM section is in OFF */ +#define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ +#define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ +#define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */ + +/* Bit 21 : Keep retention on RAM section S5 when RAM section is in OFF */ +#define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ +#define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ +#define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */ + +/* Bit 20 : Keep retention on RAM section S4 when RAM section is in OFF */ +#define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ +#define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ +#define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */ + +/* Bit 19 : Keep retention on RAM section S3 when RAM section is in OFF */ +#define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */ + +/* Bit 18 : Keep retention on RAM section S2 when RAM section is in OFF */ +#define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 15 : Keep RAM section S15 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ +#define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ +#define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */ + +/* Bit 14 : Keep RAM section S14 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ +#define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ +#define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */ + +/* Bit 13 : Keep RAM section S13 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ +#define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ +#define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */ + +/* Bit 12 : Keep RAM section S12 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ +#define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ +#define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */ + +/* Bit 11 : Keep RAM section S11 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ +#define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ +#define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */ + +/* Bit 10 : Keep RAM section S10 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ +#define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ +#define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */ + +/* Bit 9 : Keep RAM section S9 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ +#define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ +#define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */ + +/* Bit 8 : Keep RAM section S8 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ +#define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ +#define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */ + +/* Bit 7 : Keep RAM section S7 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ +#define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ +#define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */ + +/* Bit 6 : Keep RAM section S6 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ +#define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ +#define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */ + +/* Bit 5 : Keep RAM section S5 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ +#define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ +#define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */ + +/* Bit 4 : Keep RAM section S4 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ +#define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ +#define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */ + +/* Bit 3 : Keep RAM section S3 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */ + +/* Bit 2 : Keep RAM section S2 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster[0]: RAM0 power control set register */ + +/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ +#define POWER_RAM_POWERSET_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ +#define POWER_RAM_POWERSET_S15RETENTION_On (1UL) /*!< On */ + +/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ +#define POWER_RAM_POWERSET_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ +#define POWER_RAM_POWERSET_S14RETENTION_On (1UL) /*!< On */ + +/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ +#define POWER_RAM_POWERSET_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ +#define POWER_RAM_POWERSET_S13RETENTION_On (1UL) /*!< On */ + +/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ +#define POWER_RAM_POWERSET_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ +#define POWER_RAM_POWERSET_S12RETENTION_On (1UL) /*!< On */ + +/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ +#define POWER_RAM_POWERSET_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ +#define POWER_RAM_POWERSET_S11RETENTION_On (1UL) /*!< On */ + +/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ +#define POWER_RAM_POWERSET_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ +#define POWER_RAM_POWERSET_S10RETENTION_On (1UL) /*!< On */ + +/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ +#define POWER_RAM_POWERSET_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ +#define POWER_RAM_POWERSET_S9RETENTION_On (1UL) /*!< On */ + +/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ +#define POWER_RAM_POWERSET_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ +#define POWER_RAM_POWERSET_S8RETENTION_On (1UL) /*!< On */ + +/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ +#define POWER_RAM_POWERSET_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ +#define POWER_RAM_POWERSET_S7RETENTION_On (1UL) /*!< On */ + +/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ +#define POWER_RAM_POWERSET_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ +#define POWER_RAM_POWERSET_S6RETENTION_On (1UL) /*!< On */ + +/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ +#define POWER_RAM_POWERSET_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ +#define POWER_RAM_POWERSET_S5RETENTION_On (1UL) /*!< On */ + +/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ +#define POWER_RAM_POWERSET_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ +#define POWER_RAM_POWERSET_S4RETENTION_On (1UL) /*!< On */ + +/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define POWER_RAM_POWERSET_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define POWER_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */ + +/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define POWER_RAM_POWERSET_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define POWER_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ +#define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ +#define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */ + +/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ +#define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ +#define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */ + +/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ +#define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ +#define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */ + +/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ +#define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ +#define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */ + +/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ +#define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ +#define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */ + +/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ +#define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ +#define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */ + +/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ +#define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ +#define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */ + +/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ +#define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ +#define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */ + +/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ +#define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ +#define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */ + +/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ +#define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ +#define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */ + +/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ +#define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ +#define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */ + +/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ +#define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ +#define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */ + +/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */ + +/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster[0]: RAM0 power control clear register */ + +/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ +#define POWER_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ +#define POWER_RAM_POWERCLR_S15RETENTION_Off (1UL) /*!< Off */ + +/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ +#define POWER_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ +#define POWER_RAM_POWERCLR_S14RETENTION_Off (1UL) /*!< Off */ + +/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ +#define POWER_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ +#define POWER_RAM_POWERCLR_S13RETENTION_Off (1UL) /*!< Off */ + +/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ +#define POWER_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ +#define POWER_RAM_POWERCLR_S12RETENTION_Off (1UL) /*!< Off */ + +/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ +#define POWER_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ +#define POWER_RAM_POWERCLR_S11RETENTION_Off (1UL) /*!< Off */ + +/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ +#define POWER_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ +#define POWER_RAM_POWERCLR_S10RETENTION_Off (1UL) /*!< Off */ + +/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ +#define POWER_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ +#define POWER_RAM_POWERCLR_S9RETENTION_Off (1UL) /*!< Off */ + +/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ +#define POWER_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ +#define POWER_RAM_POWERCLR_S8RETENTION_Off (1UL) /*!< Off */ + +/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ +#define POWER_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ +#define POWER_RAM_POWERCLR_S7RETENTION_Off (1UL) /*!< Off */ + +/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ +#define POWER_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ +#define POWER_RAM_POWERCLR_S6RETENTION_Off (1UL) /*!< Off */ + +/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ +#define POWER_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ +#define POWER_RAM_POWERCLR_S5RETENTION_Off (1UL) /*!< Off */ + +/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ +#define POWER_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ +#define POWER_RAM_POWERCLR_S4RETENTION_Off (1UL) /*!< Off */ + +/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define POWER_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define POWER_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */ + +/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define POWER_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define POWER_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ +#define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ +#define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */ + +/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ +#define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ +#define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */ + +/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ +#define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ +#define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */ + +/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ +#define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ +#define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */ + +/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ +#define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ +#define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */ + +/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ +#define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ +#define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */ + +/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ +#define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ +#define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */ + +/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ +#define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ +#define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */ + +/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ +#define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ +#define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */ + +/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ +#define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ +#define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */ + +/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ +#define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ +#define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */ + +/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ +#define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ +#define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */ + +/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */ + +/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster[0]: Channel 0 event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection[0]: Channel group 0 */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: PWM */ +/* Description: Pulse Width Modulation Unit 0 */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up or up and down as wave counter mode */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Pre-scaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Amount of playback of a loop */ + +/* Bits 15..0 : Amount of playback of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */ + +/* Bits 31..0 : Beginning address in Data RAM of sequence A */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */ + +/* Bits 14..0 : Amount of values (duty cycles) in sequence A */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ + +/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster[0]: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection[0]: Output pin select for PWM channel 0 */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 9..8 : Port number */ +#define PWM_PSEL_OUT_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define PWM_PSEL_OUT_PORT_Msk (0x3UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QDEC_PSEL_LED_PORT_Msk (0x3UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QDEC_PSEL_A_PORT_Msk (0x3UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QDEC_PSEL_B_PORT_Msk (0x3UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: QSPI */ +/* Description: External flash interface */ + +/* Register: QSPI_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define QSPI_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: QSPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define QSPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define QSPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: QSPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define QSPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define QSPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: QSPI_ENABLE */ +/* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */ + +/* Bit 0 : Enable or disable QSPI */ +#define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QSPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable QSPI */ +#define QSPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QSPI */ + +/* Register: QSPI_READ_SRC */ +/* Description: Flash memory source address */ + +/* Bits 31..0 : Word-aligned flash memory source address. */ +#define QSPI_READ_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + +/* Register: QSPI_READ_DST */ +/* Description: RAM destination address */ + +/* Bits 31..0 : Word-aligned RAM destination address. */ +#define QSPI_READ_DST_DST_Pos (0UL) /*!< Position of DST field. */ +#define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos) /*!< Bit mask of DST field. */ + +/* Register: QSPI_READ_CNT */ +/* Description: Read transfer length */ + +/* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +#define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: QSPI_WRITE_DST */ +/* Description: Flash destination address */ + +/* Bits 31..0 : Word-aligned flash destination address. */ +#define QSPI_WRITE_DST_DST_Pos (0UL) /*!< Position of DST field. */ +#define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos) /*!< Bit mask of DST field. */ + +/* Register: QSPI_WRITE_SRC */ +/* Description: RAM source address */ + +/* Bits 31..0 : Word-aligned RAM source address. */ +#define QSPI_WRITE_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + +/* Register: QSPI_WRITE_CNT */ +/* Description: Write transfer length */ + +/* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +#define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: QSPI_ERASE_PTR */ +/* Description: Start address of flash block to be erased */ + +/* Bits 31..0 : Word-aligned start address of block to be erased. */ +#define QSPI_ERASE_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: QSPI_ERASE_LEN */ +/* Description: Size of block to be erased. */ + +/* Bits 1..0 : LEN */ +#define QSPI_ERASE_LEN_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos) /*!< Bit mask of LEN field. */ +#define QSPI_ERASE_LEN_LEN_4KB (0UL) /*!< Erase 4 kB block (flash command 0x20) */ +#define QSPI_ERASE_LEN_LEN_64KB (1UL) /*!< Erase 64 kB block (flash command 0xD8) */ +#define QSPI_ERASE_LEN_LEN_All (2UL) /*!< Erase all (flash command 0xC7) */ + +/* Register: QSPI_PSEL_SCK */ +/* Description: Pin select for serial clock SCK */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_SCK_PORT_Msk (0x3UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_CSN */ +/* Description: Pin select for chip select signal CSN. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_CSN_PORT_Msk (0x3UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO0 */ +/* Description: Pin select for serial data MOSI/IO0. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO0_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO0_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO0_PORT_Msk (0x3UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO1 */ +/* Description: Pin select for serial data MISO/IO1. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO1_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO1_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO1_PORT_Msk (0x3UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO2 */ +/* Description: Pin select for serial data IO2. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO2_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO2_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO2_PORT_Msk (0x3UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO3 */ +/* Description: Pin select for serial data IO3. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO3_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO3_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO3_PORT_Msk (0x3UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_XIPOFFSET */ +/* Description: Address offset into the external memory for Execute in Place operation. */ + +/* Bits 31..0 : Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. */ +#define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL) /*!< Position of XIPOFFSET field. */ +#define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos) /*!< Bit mask of XIPOFFSET field. */ + +/* Register: QSPI_IFCONFIG0 */ +/* Description: Interface configuration. */ + +/* Bit 7 : Enable deep power-down mode (DPM) feature. */ +#define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */ +#define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */ +#define QSPI_IFCONFIG0_DPMENABLE_Disable (0UL) /*!< Disable DPM feature. */ +#define QSPI_IFCONFIG0_DPMENABLE_Enable (1UL) /*!< Enable DPM feature. */ + +/* Bit 6 : Addressing mode. */ +#define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL) /*!< Position of ADDRMODE field. */ +#define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos) /*!< Bit mask of ADDRMODE field. */ +#define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL) /*!< 24-bit addressing. */ +#define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL) /*!< 32-bit addressing. */ + +/* Bits 5..3 : Configure number of data lines and opcode used for writing. */ +#define QSPI_IFCONFIG0_WRITEOC_Pos (3UL) /*!< Position of WRITEOC field. */ +#define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos) /*!< Bit mask of WRITEOC field. */ +#define QSPI_IFCONFIG0_WRITEOC_PP (0UL) /*!< Single data line SPI. PP (opcode 0x02). */ +#define QSPI_IFCONFIG0_WRITEOC_PP2O (1UL) /*!< Dual data line SPI. PP2O (opcode 0xA2). */ +#define QSPI_IFCONFIG0_WRITEOC_PP4O (2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */ +#define QSPI_IFCONFIG0_WRITEOC_PP4IO (3UL) /*!< Quad data line SPI. PP4IO (opcode 0x38). */ + +/* Bits 2..0 : Configure number of data lines and opcode used for reading. */ +#define QSPI_IFCONFIG0_READOC_Pos (0UL) /*!< Position of READOC field. */ +#define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos) /*!< Bit mask of READOC field. */ +#define QSPI_IFCONFIG0_READOC_FASTREAD (0UL) /*!< Single data line SPI. FAST_READ (opcode 0x0B). */ +#define QSPI_IFCONFIG0_READOC_READ2O (1UL) /*!< Dual data line SPI. READ2O (opcode 0x3B). */ +#define QSPI_IFCONFIG0_READOC_READ2IO (2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */ +#define QSPI_IFCONFIG0_READOC_READ4O (3UL) /*!< Quad data line SPI. READ4O (opcode 0x6B). */ +#define QSPI_IFCONFIG0_READOC_READ4IO (4UL) /*!< Quad data line SPI. READ4IO (opcode 0xEB). */ + +/* Register: QSPI_IFCONFIG1 */ +/* Description: Interface configuration. */ + +/* Bits 31..28 : SCK frequency is given as 32 MHz / (SCKFREQ + 1). */ +#define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */ +#define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */ + +/* Bit 25 : Select SPI mode. */ +#define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */ +#define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */ +#define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock's rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */ +#define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock's falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */ + +/* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */ +#define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */ +#define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos) /*!< Bit mask of DPMEN field. */ +#define QSPI_IFCONFIG1_DPMEN_Exit (0UL) /*!< Exit DPM. */ +#define QSPI_IFCONFIG1_DPMEN_Enter (1UL) /*!< Enter DPM. */ + +/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). */ +#define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */ +#define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */ + +/* Register: QSPI_STATUS */ +/* Description: Status register. */ + +/* Bits 31..24 : Value of external flash devices Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */ +#define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */ +#define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */ + +/* Bit 3 : Ready status. */ +#define QSPI_STATUS_READY_Pos (3UL) /*!< Position of READY field. */ +#define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_STATUS_READY_BUSY (0UL) /*!< QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. */ +#define QSPI_STATUS_READY_READY (1UL) /*!< QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. */ + +/* Bit 2 : Deep power-down mode (DPM) status of external flash. */ +#define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */ +#define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos) /*!< Bit mask of DPM field. */ +#define QSPI_STATUS_DPM_Disabled (0UL) /*!< External flash is not in DPM. */ +#define QSPI_STATUS_DPM_Enabled (1UL) /*!< External flash is in DPM. */ + +/* Register: QSPI_DPMDUR */ +/* Description: Set the duration required to enter/exit deep power-down mode (DPM). */ + +/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. */ +#define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */ +#define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */ + +/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. */ +#define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */ +#define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */ + +/* Register: QSPI_ADDRCONF */ +/* Description: Extended address configuration. */ + +/* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */ +#define QSPI_ADDRCONF_WREN_Pos (27UL) /*!< Position of WREN field. */ +#define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos) /*!< Bit mask of WREN field. */ +#define QSPI_ADDRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */ +#define QSPI_ADDRCONF_WREN_Enable (1UL) /*!< Send WREN. */ + +/* Bit 26 : Wait for write complete before sending command. */ +#define QSPI_ADDRCONF_WIPWAIT_Pos (26UL) /*!< Position of WIPWAIT field. */ +#define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */ +#define QSPI_ADDRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */ +#define QSPI_ADDRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */ + +/* Bits 25..24 : Extended addressing mode. */ +#define QSPI_ADDRCONF_MODE_Pos (24UL) /*!< Position of MODE field. */ +#define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */ +#define QSPI_ADDRCONF_MODE_NoInstr (0UL) /*!< Do not send any instruction. */ +#define QSPI_ADDRCONF_MODE_Opcode (1UL) /*!< Send opcode. */ +#define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, byte0. */ +#define QSPI_ADDRCONF_MODE_All (3UL) /*!< Send opcode, byte0, byte1. */ + +/* Bits 23..16 : Byte 1 following byte 0. */ +#define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */ +#define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */ + +/* Bits 15..8 : Byte 0 following opcode. */ +#define QSPI_ADDRCONF_BYTE0_Pos (8UL) /*!< Position of BYTE0 field. */ +#define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */ + +/* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */ +#define QSPI_ADDRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */ +#define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */ + +/* Register: QSPI_CINSTRCONF */ +/* Description: Custom instruction configuration register. */ + +/* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */ +#define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */ +#define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */ +#define QSPI_CINSTRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */ +#define QSPI_CINSTRCONF_WREN_Enable (1UL) /*!< Send WREN. */ + +/* Bit 14 : Wait for write complete before sending command. */ +#define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL) /*!< Position of WIPWAIT field. */ +#define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */ +#define QSPI_CINSTRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */ +#define QSPI_CINSTRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */ + +/* Bit 13 : Level of the IO3 pin (if connected) during transmission of custom instruction. */ +#define QSPI_CINSTRCONF_LIO3_Pos (13UL) /*!< Position of LIO3 field. */ +#define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos) /*!< Bit mask of LIO3 field. */ + +/* Bit 12 : Level of the IO2 pin (if connected) during transmission of custom instruction. */ +#define QSPI_CINSTRCONF_LIO2_Pos (12UL) /*!< Position of LIO2 field. */ +#define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos) /*!< Bit mask of LIO2 field. */ + +/* Bits 11..8 : Length of custom instruction in number of bytes. */ +#define QSPI_CINSTRCONF_LENGTH_Pos (8UL) /*!< Position of LENGTH field. */ +#define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define QSPI_CINSTRCONF_LENGTH_1B (1UL) /*!< Send opcode only. */ +#define QSPI_CINSTRCONF_LENGTH_2B (2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */ +#define QSPI_CINSTRCONF_LENGTH_3B (3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */ +#define QSPI_CINSTRCONF_LENGTH_4B (4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */ +#define QSPI_CINSTRCONF_LENGTH_5B (5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */ +#define QSPI_CINSTRCONF_LENGTH_6B (6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */ +#define QSPI_CINSTRCONF_LENGTH_7B (7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */ +#define QSPI_CINSTRCONF_LENGTH_8B (8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */ +#define QSPI_CINSTRCONF_LENGTH_9B (9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */ + +/* Bits 7..0 : Opcode of Custom instruction. */ +#define QSPI_CINSTRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */ +#define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */ + +/* Register: QSPI_CINSTRDAT0 */ +/* Description: Custom instruction data register 0. */ + +/* Bits 31..24 : Data byte 3 */ +#define QSPI_CINSTRDAT0_BYTE3_Pos (24UL) /*!< Position of BYTE3 field. */ +#define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos) /*!< Bit mask of BYTE3 field. */ + +/* Bits 23..16 : Data byte 2 */ +#define QSPI_CINSTRDAT0_BYTE2_Pos (16UL) /*!< Position of BYTE2 field. */ +#define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos) /*!< Bit mask of BYTE2 field. */ + +/* Bits 15..8 : Data byte 1 */ +#define QSPI_CINSTRDAT0_BYTE1_Pos (8UL) /*!< Position of BYTE1 field. */ +#define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */ + +/* Bits 7..0 : Data byte 0 */ +#define QSPI_CINSTRDAT0_BYTE0_Pos (0UL) /*!< Position of BYTE0 field. */ +#define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */ + +/* Register: QSPI_CINSTRDAT1 */ +/* Description: Custom instruction data register 1. */ + +/* Bits 31..24 : Data byte 7 */ +#define QSPI_CINSTRDAT1_BYTE7_Pos (24UL) /*!< Position of BYTE7 field. */ +#define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos) /*!< Bit mask of BYTE7 field. */ + +/* Bits 23..16 : Data byte 6 */ +#define QSPI_CINSTRDAT1_BYTE6_Pos (16UL) /*!< Position of BYTE6 field. */ +#define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos) /*!< Bit mask of BYTE6 field. */ + +/* Bits 15..8 : Data byte 5 */ +#define QSPI_CINSTRDAT1_BYTE5_Pos (8UL) /*!< Position of BYTE5 field. */ +#define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos) /*!< Bit mask of BYTE5 field. */ + +/* Bits 7..0 : Data byte 4 */ +#define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */ +#define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */ + +/* Register: QSPI_IFTIMING */ +/* Description: SPI interface timing. */ + +/* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. */ +#define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */ +#define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz Radio */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 19 : Shortcut between RXREADY event and START task */ +#define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 18 : Shortcut between TXREADY event and START task */ +#define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 17 : Shortcut between CCAIDLE event and STOP task */ +#define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 16 : Shortcut between EDEND event and DISABLE task */ +#define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 15 : Shortcut between READY event and EDSTART task */ +#define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 14 : Shortcut between FRAMESTART event and BCSTART task */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between CCABUSY event and DISABLE task */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between CCAIDLE event and TXEN task */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between RXREADY event and CCASTART task */ +#define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between END event and START task */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between END event and DISABLE task */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and START task */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 23 : Write '1' to Enable interrupt for MHRMATCH event */ +#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ + +/* Bit 22 : Write '1' to Enable interrupt for RXREADY event */ +#define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ + +/* Bit 21 : Write '1' to Enable interrupt for TXREADY event */ +#define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for RATEBOOST event */ +#define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for CCASTOPPED event */ +#define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for CCABUSY event */ +#define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for CCAIDLE event */ +#define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for EDSTOPPED event */ +#define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to Enable interrupt for EDEND event */ +#define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for FRAMESTART event */ +#define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for END event */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 23 : Write '1' to Disable interrupt for MHRMATCH event */ +#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 22 : Write '1' to Disable interrupt for RXREADY event */ +#define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 21 : Write '1' to Disable interrupt for TXREADY event */ +#define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for RATEBOOST event */ +#define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for CCASTOPPED event */ +#define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for CCABUSY event */ +#define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for CCAIDLE event */ +#define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for EDSTOPPED event */ +#define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to Disable interrupt for EDEND event */ +#define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for FRAMESTART event */ +#define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for END event */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power. */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos9dBm (0x9UL) /*!< +9 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ +#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s (TX Only - RX supports both) */ +#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s (TX Only - RX supports both) */ +#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bits 30..29 : Length of TERM field in Long Range operation */ +#define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */ +#define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */ + +/* Bit 26 : Indicates if LENGTH field contains CRC or not */ +#define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */ +#define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */ + +/* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ +#define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ +#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BTLE Long Range */ + +/* Bits 23..22 : Length of Code Indicator - Long Range */ +#define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ +#define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ +#define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Inter Frame Spacing in us */ + +/* Bits 9..0 : Inter Frame Spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection[0]: Device address base segment 0 */ + +/* Bits 31..0 : Device address base segment 0 */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection[0]: Device address prefix 0 */ + +/* Bits 15..0 : Device address prefix 0 */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_SFD */ +/* Description: IEEE 802.15.4 Start of Frame Delimiter */ + +/* Bits 7..0 : IEEE 802.15.4 Start of Frame Delimiter */ +#define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ +#define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ + +/* Register: RADIO_EDCNT */ +/* Description: IEEE 802.15.4 Energy Detect Loop Count */ + +/* Bits 20..0 : IEEE 802.15.4 Energy Detect Loop Count */ +#define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ +#define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ + +/* Register: RADIO_EDSAMPLE */ +/* Description: IEEE 802.15.4 Energy Detect Level */ + +/* Bits 7..0 : IEEE 802.15.4 Energy Detect Level */ +#define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ +#define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ + +/* Register: RADIO_CCACTRL */ +/* Description: IEEE 802.15.4 Clear Channel Assessment Control */ + +/* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */ +#define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ +#define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ + +/* Bits 23..16 : CCA Correlator Busy Threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */ +#define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ +#define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ + +/* Bits 15..8 : CCA Energy Busy Threshold. Used in all the CCA modes except CarrierMode. */ +#define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ +#define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ + +/* Bits 2..0 : CCA Mode Of Operation */ +#define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy Above Threshold */ +#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier Seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy Above Threshold AND Carrier Seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy Above Threshold OR Carrier Seen */ +#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TICK event */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TICK event */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable event routing for OVRFLW event */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable event routing for TICK event */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable event routing for TICK event */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable event routing for TICK event */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection[0]: Compare register 0 */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Analog to Digital Converter */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for STOPPED event */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for DONE event */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for END event */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for DONE event */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for DONE event */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable ADC */ + +/* Bit 0 : Enable or disable ADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster[0]: Input positive pin selection for CH[0] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ +#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x11UL) /*!< VDDH/5 */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster[0]: Input negative pin selection for CH[0] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ +#define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x11UL) /*!< VDDH/5 */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster[0]: Input configuration for CH[0] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster[0]: High/low limits for event monitoring a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 14..0 : Maximum number of buffer words to transfer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of buffer words transferred since last START */ + +/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for READY event */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for READY event */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPI_PSEL_SCK_PORT_Msk (0x3UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPI_PSEL_MOSI_PORT_Msk (0x3UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPI_PSEL_MISO_PORT_Msk (0x3UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 17 : Shortcut between END event and START task */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for STARTED event */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for END event */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for STARTED event */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for END event */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_STALLSTAT */ +/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ + +/* Bit 1 : Stall status for EasyDMA RAM writes */ +#define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */ +#define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */ +#define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */ +#define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */ + +/* Bit 0 : Stall status for EasyDMA RAM reads */ +#define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */ +#define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */ +#define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */ +#define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_SCK_PORT_Msk (0x3UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_MOSI_PORT_Msk (0x3UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_MISO_PORT_Msk (0x3UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_CSN */ +/* Description: Pin select for CSN */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_CSN_PORT_Msk (0x3UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 15..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Number of bytes in transmit buffer */ + +/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_IFTIMING_RXDELAY */ +/* Description: Sample delay for input serial data on MISO */ + +/* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */ +#define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */ +#define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + +/* Register: SPIM_IFTIMING_CSNDUR */ +/* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */ + +/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */ +#define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */ +#define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */ + +/* Register: SPIM_ORC */ +/* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */ + +/* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 2 : Shortcut between END event and ACQUIRE task */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_SCK_PORT_Msk (0x3UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_MISO_PORT_Msk (0x3UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_MOSI_PORT_Msk (0x3UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_CSN_PORT_Msk (0x3UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 7..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 7..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_STATUS */ +/* Description: Timer status */ + +/* Bit 0 : Timer status */ +#define TIMER_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define TIMER_STATUS_STATUS_Msk (0x1UL << TIMER_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define TIMER_STATUS_STATUS_Stopped (0UL) /*!< Timer is stopped */ +#define TIMER_STATUS_STATUS_Started (1UL) /*!< Timer is started */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection[0]: Capture/Compare register 0 */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface 0 */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between BB event and STOP task */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between BB event and SUSPEND task */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for BB event */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for BB event */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSEL_SCL */ +/* Description: Pin select for SCL */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWI_PSEL_SCL_PORT_Msk (0x3UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_PSEL_SDA */ +/* Description: Pin select for SDA */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWI_PSEL_SDA_PORT_Msk (0x3UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 12 : Shortcut between LASTRX event and STOP task */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between LASTTX event and STOP task */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for LASTTX event */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for LASTRX event */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIM_PSEL_SCL_PORT_Msk (0x3UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIM_PSEL_SDA_PORT_Msk (0x3UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 14 : Shortcut between READ event and SUSPEND task */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for READ event */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for WRITE event */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to Enable interrupt for READ event */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for WRITE event */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to Disable interrupt for READ event */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for WRITE event */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIS_PSEL_SCL_PORT_Msk (0x3UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIS_PSEL_SDA_PORT_Msk (0x3UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection[0]: TWI slave address 0 */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between NCTS event and STOPRX task */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between CTS event and STARTRX task */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSEL_RTS */ +/* Description: Pin select for RTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_RTS_PORT_Msk (0x3UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_TXD */ +/* Description: Pin select for TXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_TXD_PORT_Msk (0x3UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_CTS */ +/* Description: Pin select for CTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_CTS_PORT_Msk (0x3UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_RXD */ +/* Description: Pin select for RXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_RXD_PORT_Msk (0x3UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA 0 */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for RXTO event */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for ENDTX event */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for ENDRX event */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for NCTS event */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for CTS event */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source Note : this register is read / write one to clear. */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_RTS_PORT_Msk (0x3UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_TXD_PORT_Msk (0x3UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_CTS_PORT_Msk (0x3UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number */ +#define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_RXD_PORT_Msk (0x3UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 9..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 9..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 4 : Stop bits */ +#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User Information Configuration Registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection[0]: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection[0]: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection[0]: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection[0]: Mapping of the nRESET function */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 6..5 : Port number onto which nRESET is exposed */ +#define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UICR_PSELRESET_PORT_Msk (0x3UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number of PORT onto which nRESET is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access port protection */ + +/* Bits 7..0 : Enable or disable Access Port protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + +/* Register: UICR_NFCPINS */ +/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ + +/* Bit 0 : Setting of pins dedicated to NFC functionality */ +#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ + +/* Register: UICR_EXTSUPPLY */ +/* Description: Enable external circuitry to be supplied from VDD pin. Applicable in 'High voltage mode' only. */ + +/* Bit 0 : Enable external circuitry to be supplied from VDD pin (output of REG0 stage). */ +#define UICR_EXTSUPPLY_EXTSUPPLY_Pos (0UL) /*!< Position of EXTSUPPLY field. */ +#define UICR_EXTSUPPLY_EXTSUPPLY_Msk (0x1UL << UICR_EXTSUPPLY_EXTSUPPLY_Pos) /*!< Bit mask of EXTSUPPLY field. */ +#define UICR_EXTSUPPLY_EXTSUPPLY_Disabled (0UL) /*!< No current can be drawn from the VDD pin. */ +#define UICR_EXTSUPPLY_EXTSUPPLY_Enabled (1UL) /*!< It is allowed to supply external circuitry from the VDD pin. */ + +/* Register: UICR_REGOUT0 */ +/* Description: GPIO reference voltage / external output supply voltage in 'High voltage mode'. */ + +/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */ +#define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ +#define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */ +#define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */ +#define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */ +#define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */ +#define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */ +#define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */ +#define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */ +#define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */ + + +/* Peripheral: USBD */ +/* Description: Universal Serial Bus device */ + +/* Register: USBD_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between ENDEPOUT[0] event and EP0STATUS task */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between EP0DATADONE event and EP0STATUS task */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between EP0DATADONE event and STARTEPOUT[0] task */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between EP0DATADONE event and STARTEPIN[0] task */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: USBD_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 25 : Enable or disable interrupt for ACCESSFAULT event */ +#define USBD_INTEN_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */ +#define USBD_INTEN_ACCESSFAULT_Msk (0x1UL << USBD_INTEN_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */ +#define USBD_INTEN_ACCESSFAULT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ACCESSFAULT_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for EPDATA event */ +#define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for EP0SETUP event */ +#define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */ + +/* Bit 22 : Enable or disable interrupt for USBEVENT event */ +#define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */ + +/* Bit 21 : Enable or disable interrupt for SOF event */ +#define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for ENDISOOUT event */ +#define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */ +#define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */ +#define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */ +#define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */ +#define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */ +#define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */ +#define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */ +#define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */ +#define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for ENDISOIN event */ +#define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for EP0DATADONE event */ +#define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */ +#define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */ +#define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */ +#define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */ +#define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */ +#define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */ +#define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */ +#define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */ +#define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STARTED event */ +#define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for USBRESET event */ +#define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */ + +/* Register: USBD_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 25 : Write '1' to Enable interrupt for ACCESSFAULT event */ +#define USBD_INTENSET_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */ +#define USBD_INTENSET_ACCESSFAULT_Msk (0x1UL << USBD_INTENSET_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */ +#define USBD_INTENSET_ACCESSFAULT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ACCESSFAULT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ACCESSFAULT_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable interrupt for EPDATA event */ +#define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to Enable interrupt for EP0SETUP event */ +#define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */ + +/* Bit 22 : Write '1' to Enable interrupt for USBEVENT event */ +#define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */ + +/* Bit 21 : Write '1' to Enable interrupt for SOF event */ +#define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for ENDISOOUT event */ +#define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for ENDEPOUT[7] event */ +#define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for ENDEPOUT[6] event */ +#define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for ENDEPOUT[5] event */ +#define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for ENDEPOUT[4] event */ +#define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to Enable interrupt for ENDEPOUT[3] event */ +#define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for ENDEPOUT[2] event */ +#define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for ENDEPOUT[1] event */ +#define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for ENDEPOUT[0] event */ +#define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for ENDISOIN event */ +#define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for EP0DATADONE event */ +#define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ENDEPIN[7] event */ +#define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDEPIN[6] event */ +#define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for ENDEPIN[5] event */ +#define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for ENDEPIN[4] event */ +#define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for ENDEPIN[3] event */ +#define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDEPIN[2] event */ +#define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for ENDEPIN[1] event */ +#define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for ENDEPIN[0] event */ +#define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STARTED event */ +#define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for USBRESET event */ +#define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */ + +/* Register: USBD_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 25 : Write '1' to Disable interrupt for ACCESSFAULT event */ +#define USBD_INTENCLR_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */ +#define USBD_INTENCLR_ACCESSFAULT_Msk (0x1UL << USBD_INTENCLR_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */ +#define USBD_INTENCLR_ACCESSFAULT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ACCESSFAULT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ACCESSFAULT_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable interrupt for EPDATA event */ +#define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to Disable interrupt for EP0SETUP event */ +#define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */ + +/* Bit 22 : Write '1' to Disable interrupt for USBEVENT event */ +#define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */ + +/* Bit 21 : Write '1' to Disable interrupt for SOF event */ +#define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for ENDISOOUT event */ +#define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for ENDEPOUT[7] event */ +#define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for ENDEPOUT[6] event */ +#define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for ENDEPOUT[5] event */ +#define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for ENDEPOUT[4] event */ +#define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to Disable interrupt for ENDEPOUT[3] event */ +#define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for ENDEPOUT[2] event */ +#define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for ENDEPOUT[1] event */ +#define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for ENDEPOUT[0] event */ +#define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for ENDISOIN event */ +#define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for EP0DATADONE event */ +#define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ENDEPIN[7] event */ +#define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDEPIN[6] event */ +#define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for ENDEPIN[5] event */ +#define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for ENDEPIN[4] event */ +#define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for ENDEPIN[3] event */ +#define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDEPIN[2] event */ +#define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for ENDEPIN[1] event */ +#define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for ENDEPIN[0] event */ +#define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STARTED event */ +#define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for USBRESET event */ +#define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */ + +/* Register: USBD_EVENTCAUSE */ +/* Description: Details on event that caused the USBEVENT event */ + +/* Bit 11 : Wrapper has re-initialized SFRs to the proper values. MAC is ready for normal operation. Write '1' to clear. */ +#define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */ +#define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */ +#define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */ +#define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */ + +/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. Write '1' to clear. */ +#define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */ +#define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */ +#define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */ +#define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */ + +/* Bit 8 : Signals that the USB lines have been seen idle long enough for the device to enter suspend. Write '1' to clear. */ +#define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */ +#define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */ +#define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */ +#define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */ + +/* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */ + +/* Register: USBD_BUSSTATE */ +/* Description: Provides the logic state of the D+ and D- lines */ + +/* Bit 1 : State of the D+ line */ +#define USBD_BUSSTATE_DP_Pos (1UL) /*!< Position of DP field. */ +#define USBD_BUSSTATE_DP_Msk (0x1UL << USBD_BUSSTATE_DP_Pos) /*!< Bit mask of DP field. */ +#define USBD_BUSSTATE_DP_Low (0UL) /*!< Low */ +#define USBD_BUSSTATE_DP_High (1UL) /*!< High */ + +/* Bit 0 : State of the D- line */ +#define USBD_BUSSTATE_DM_Pos (0UL) /*!< Position of DM field. */ +#define USBD_BUSSTATE_DM_Msk (0x1UL << USBD_BUSSTATE_DM_Pos) /*!< Bit mask of DM field. */ +#define USBD_BUSSTATE_DM_Low (0UL) /*!< Low */ +#define USBD_BUSSTATE_DM_High (1UL) /*!< High */ + +/* Register: USBD_HALTED_EPIN */ +/* Description: Description collection[0]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ + +/* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +#define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ +#define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */ +#define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */ +#define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ + +/* Register: USBD_HALTED_EPOUT */ +/* Description: Description collection[0]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ + +/* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +#define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ +#define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */ +#define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */ +#define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ + +/* Register: USBD_EPSTATUS */ +/* Description: Provides information on which endpoint's EasyDMA registers have been captured */ + +/* Bit 24 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */ +#define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */ +#define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 23 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ +#define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ +#define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 22 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ +#define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ +#define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 21 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ +#define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ +#define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 20 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ +#define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ +#define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 19 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ +#define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ +#define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 18 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ +#define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ +#define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 17 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ +#define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ +#define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 16 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */ +#define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */ +#define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 8 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */ +#define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */ +#define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 7 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ +#define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ +#define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 6 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ +#define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ +#define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 5 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ +#define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ +#define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 4 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ +#define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ +#define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 3 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ +#define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ +#define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 2 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ +#define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ +#define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 1 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ +#define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ +#define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 0 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */ +#define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */ +#define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Register: USBD_EPDATASTATUS */ +/* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */ + +/* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ +#define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ +#define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ +#define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ +#define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ +#define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ +#define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ +#define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ +#define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ +#define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ +#define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ +#define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ +#define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ +#define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ +#define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ +#define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ +#define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ +#define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ +#define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ +#define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ +#define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ +#define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ +#define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ +#define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ +#define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ +#define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ +#define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ +#define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ +#define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Register: USBD_USBADDR */ +/* Description: Device USB address */ + +/* Bits 6..0 : Device USB address */ +#define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ +#define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + +/* Register: USBD_BMREQUESTTYPE */ +/* Description: SETUP data, byte 0, bmRequestType */ + +/* Bit 7 : Data transfer direction */ +#define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */ +#define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */ +#define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */ +#define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */ + +/* Bits 6..5 : Data transfer type */ +#define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */ +#define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */ +#define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */ +#define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */ +#define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */ + +/* Bits 4..0 : Data transfer type */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */ + +/* Register: USBD_BREQUEST */ +/* Description: SETUP data, byte 1, bRequest */ + +/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provides for standard requests only, user must implement Class and Vendor values. */ +#define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */ +#define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */ +#define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */ +#define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */ +#define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */ +#define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */ +#define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */ +#define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */ +#define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */ +#define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */ + +/* Register: USBD_WVALUEL */ +/* Description: SETUP data, byte 2, LSB of wValue */ + +/* Bits 7..0 : SETUP data, byte 2, LSB of wValue */ +#define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */ +#define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */ + +/* Register: USBD_WVALUEH */ +/* Description: SETUP data, byte 3, MSB of wValue */ + +/* Bits 7..0 : SETUP data, byte 3, MSB of wValue */ +#define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */ +#define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */ + +/* Register: USBD_WINDEXL */ +/* Description: SETUP data, byte 4, LSB of wIndex */ + +/* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */ +#define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */ +#define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */ + +/* Register: USBD_WINDEXH */ +/* Description: SETUP data, byte 5, MSB of wIndex */ + +/* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */ +#define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */ +#define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */ + +/* Register: USBD_WLENGTHL */ +/* Description: SETUP data, byte 6, LSB of wLength */ + +/* Bits 7..0 : SETUP data, byte 6, LSB of wLength */ +#define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */ +#define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */ + +/* Register: USBD_WLENGTHH */ +/* Description: SETUP data, byte 7, MSB of wLength */ + +/* Bits 7..0 : SETUP data, byte 7, MSB of wLength */ +#define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */ +#define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */ + +/* Register: USBD_SIZE_EPOUT */ +/* Description: Description collection[0]: Amount of bytes received last in the data stage of this OUT endpoint */ + +/* Bits 6..0 : Amount of bytes received last in the data stage of this OUT endpoint */ +#define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: USBD_SIZE_ISOOUT */ +/* Description: Amount of bytes received last on this iso OUT data endpoint */ + +/* Bit 16 : Zero-length data packet received */ +#define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */ +#define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */ +#define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */ +#define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */ + +/* Bits 9..0 : Amount of bytes received last on this iso OUT data endpoint */ +#define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: USBD_ENABLE */ +/* Description: Enable USB */ + +/* Bit 0 : Enable USB */ +#define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */ +#define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */ + +/* Register: USBD_USBPULLUP */ +/* Description: Control of the USB pull-up */ + +/* Bit 0 : Control of the USB pull-up on the D+ line */ +#define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */ +#define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */ +#define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */ + +/* Register: USBD_DPDMVALUE */ +/* Description: State at which the DPDMDRIVE task will force D+ and D-. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */ + +/* Bits 4..0 : State at which the DPDMDRIVE task will force D+ and D- */ +#define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing pre-set in hardware (50 us or 5 ms, depending on bus state) */ +#define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */ +#define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */ + +/* Register: USBD_DTOGGLE */ +/* Description: Data toggle control and status. */ + +/* Bits 9..8 : Data toggle value */ +#define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */ +#define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */ +#define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */ +#define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */ +#define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */ + +/* Bit 7 : Selects IN or OUT endpoint */ +#define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */ +#define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */ +#define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */ +#define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */ + +/* Bits 2..0 : Select bulk endpoint number */ +#define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */ +#define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */ + +/* Register: USBD_EPINEN */ +/* Description: Endpoint IN enable */ + +/* Bit 8 : Enable iso IN endpoint */ +#define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */ +#define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */ +#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable iso IN endpoint 8 */ +#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable iso IN endpoint 8 */ + +/* Bit 7 : Enable IN endpoint 7 */ +#define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */ +#define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */ + +/* Bit 6 : Enable IN endpoint 6 */ +#define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */ +#define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */ + +/* Bit 5 : Enable IN endpoint 5 */ +#define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */ +#define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */ + +/* Bit 4 : Enable IN endpoint 4 */ +#define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */ +#define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */ + +/* Bit 3 : Enable IN endpoint 3 */ +#define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */ +#define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */ + +/* Bit 2 : Enable IN endpoint 2 */ +#define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */ +#define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */ + +/* Bit 1 : Enable IN endpoint 1 */ +#define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */ +#define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */ + +/* Bit 0 : Enable IN endpoint 0 */ +#define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */ +#define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */ + +/* Register: USBD_EPOUTEN */ +/* Description: Endpoint OUT enable */ + +/* Bit 8 : Enable iso OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */ +#define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */ +#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable iso OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable iso OUT endpoint 8 */ + +/* Bit 7 : Enable OUT endpoint 7 */ +#define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ +#define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */ +#define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */ + +/* Bit 6 : Enable OUT endpoint 6 */ +#define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */ +#define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */ +#define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */ + +/* Bit 5 : Enable OUT endpoint 5 */ +#define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */ +#define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */ +#define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */ + +/* Bit 4 : Enable OUT endpoint 4 */ +#define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */ +#define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */ +#define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */ + +/* Bit 3 : Enable OUT endpoint 3 */ +#define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */ +#define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */ +#define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */ + +/* Bit 2 : Enable OUT endpoint 2 */ +#define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */ +#define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */ +#define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */ + +/* Bit 1 : Enable OUT endpoint 1 */ +#define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */ +#define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */ +#define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */ + +/* Bit 0 : Enable OUT endpoint 0 */ +#define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */ +#define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */ +#define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */ + +/* Register: USBD_EPSTALL */ +/* Description: STALL endpoints */ + +/* Bit 8 : Stall selected endpoint */ +#define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */ +#define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */ +#define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */ +#define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */ + +/* Bit 7 : Selects IN or OUT endpoint */ +#define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */ +#define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */ +#define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */ +#define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */ + +/* Bits 2..0 : Select endpoint number */ +#define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */ +#define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */ + +/* Register: USBD_ISOSPLIT */ +/* Description: Controls the split of ISO buffers */ + +/* Bits 15..0 : Controls the split of ISO buffers */ +#define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ +#define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ + +/* Register: USBD_FRAMECNTR */ +/* Description: Returns the current value of the start of frame counter */ + +/* Bits 10..0 : Returns the current value of the start of frame counter */ +#define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */ +#define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */ + +/* Register: USBD_ISOINCONFIG */ +/* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ + +/* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ +#define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */ +#define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */ +#define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */ +#define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */ + +/* Register: USBD_EPIN_PTR */ +/* Description: Description cluster[0]: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_EPIN_MAXCNT */ +/* Description: Description cluster[0]: Maximum number of bytes to transfer */ + +/* Bits 6..0 : Maximum number of bytes to transfer */ +#define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_EPIN_AMOUNT */ +/* Description: Description cluster[0]: Number of bytes transferred in the last transaction */ + +/* Bits 6..0 : Number of bytes transferred in the last transaction */ +#define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_ISOIN_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_ISOIN_MAXCNT */ +/* Description: Maximum number of bytes to transfer */ + +/* Bits 9..0 : Maximum number of bytes to transfer */ +#define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_ISOIN_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_EPOUT_PTR */ +/* Description: Description cluster[0]: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_EPOUT_MAXCNT */ +/* Description: Description cluster[0]: Maximum number of bytes to transfer */ + +/* Bits 6..0 : Maximum number of bytes to transfer */ +#define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_EPOUT_AMOUNT */ +/* Description: Description cluster[0]: Number of bytes transferred in the last transaction */ + +/* Bits 6..0 : Number of bytes transferred in the last transaction */ +#define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_ISOOUT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_ISOOUT_MAXCNT */ +/* Description: Maximum number of bytes to transfer */ + +/* Bits 9..0 : Maximum number of bytes to transfer */ +#define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_ISOOUT_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection[0]: Reload request 0 */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/nrf5/device/nrf52/nrf52_bitfields.h b/nrf5/device/nrf52/nrf52_bitfields.h index d01120711c..b695bf8a19 100644 --- a/nrf5/device/nrf52/nrf52_bitfields.h +++ b/nrf5/device/nrf52/nrf52_bitfields.h @@ -1909,7 +1909,8 @@ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ -#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2001UL) /*!< CIxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -11093,18 +11094,21 @@ #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Bit 1 : NACK received after sending the address (write '1' to clear) */ #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Register: TWI_ENABLE */ /* Description: Enable TWI */ @@ -11363,6 +11367,12 @@ #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + /* Register: TWIM_ENABLE */ /* Description: Enable TWIM */ @@ -11961,6 +11971,7 @@ #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ @@ -12336,6 +12347,7 @@ #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ diff --git a/nrf5/device/nrf52/nrf52_name_change.h b/nrf5/device/nrf52/nrf52_name_change.h index c75d821faf..61f90adb0c 100644 --- a/nrf5/device/nrf52/nrf52_name_change.h +++ b/nrf5/device/nrf52/nrf52_name_change.h @@ -64,11 +64,6 @@ /* Corrected typo in RESULT register. */ #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below -/* FICR */ -/* Renamed name of the package. */ -#define FICR_INFO_PACKAGE_PACKAGE_CH FICR_INFO_PACKAGE_PACKAGE_CI - - /*lint --flb "Leave library region" */ #endif /* NRF52_NAME_CHANGE_H */ diff --git a/nrf5/device/nrf52/nrf52_to_nrf52840.h b/nrf5/device/nrf52/nrf52_to_nrf52840.h new file mode 100644 index 0000000000..3067dcc005 --- /dev/null +++ b/nrf5/device/nrf52/nrf52_to_nrf52840.h @@ -0,0 +1,88 @@ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF52_TO_NRF52840_H +#define NRF52_TO_NRF52840_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices. + * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf52_namechange.h file. */ + +/* Differences between latest nRF52 headers and nRF52840 headers. */ + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#define PSELRTS PSEL.RTS +#define PSELTXD PSEL.TXD +#define PSELCTS PSEL.CTS +#define PSELRXD PSEL.RXD + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#define PSELSCL PSEL.SCL +#define PSELSDA PSEL.SDA + + +/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52840_H */ + diff --git a/nrf5/device/nrf52/system_nrf52840.c b/nrf5/device/nrf52/system_nrf52840.c new file mode 100644 index 0000000000..4a94218cc3 --- /dev/null +++ b/nrf5/device/nrf52/system_nrf52840.c @@ -0,0 +1,209 @@ +/* Copyright (c) 2012 ARM LIMITED + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of ARM nor the names of its contributors may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +#include +#include "nrf.h" +#include "system_nrf52840.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK_64M (64000000UL) + +static bool errata_36(void); +static bool errata_98(void); +static bool errata_103(void); +static bool errata_115(void); +static bool errata_120(void); + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + + /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_98()){ + *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; + } + + /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_103()){ + NRF_CCM->MAXPACKETSIZE = 0xFBul; + } + + /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_115()){ + *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); + } + + /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_120()){ + *(volatile uint32_t *)0x40029640ul = 0x200ul; + } + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, + two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as + normal GPIOs. */ + #if defined (CONFIG_NFCT_PINS_AS_GPIOS) + if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[0] = 18; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[1] = 18; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product + Specification to see which one). */ + #if defined (ENABLE_SWO) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + SystemCoreClockUpdate(); +} + + +static bool errata_36(void) +{ + if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ + return true; + } + + return false; +} + + +static bool errata_98(void) +{ + if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ + return true; + } + + return false; +} + + +static bool errata_103(void) +{ + if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ + return true; + } + + return false; +} + + +static bool errata_115(void) +{ + if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ + return true; + } + + return false; +} + + +static bool errata_120(void) +{ + if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ + return true; + } + + return false; +} + +/*lint --flb "Leave library region" */ diff --git a/nrf5/device/nrf52/system_nrf52840.h b/nrf5/device/nrf52/system_nrf52840.h new file mode 100644 index 0000000000..9201e7926b --- /dev/null +++ b/nrf5/device/nrf52/system_nrf52840.h @@ -0,0 +1,69 @@ +/* Copyright (c) 2012 ARM LIMITED + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of ARM nor the names of its contributors may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef SYSTEM_NRF52_H +#define SYSTEM_NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52_H */ From 6973c13608ff127560a60c2feca2f6b4fbf7f94f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:04:52 +0100 Subject: [PATCH 129/809] nrf5/boards: Updating all board configs with gpio port configuration for uart/spi pins. Leds still not defined by gpio port. --- nrf5/boards/microbit/mpconfigboard.h | 14 +++++--------- nrf5/boards/pca10000/mpconfigboard.h | 4 ++-- nrf5/boards/pca10001/mpconfigboard.h | 5 +++++ nrf5/boards/pca10028/mpconfigboard.h | 6 +++++- nrf5/boards/pca10031/mpconfigboard.h | 9 +++++++-- nrf5/boards/pca10040/mpconfigboard.h | 18 +++++++++++++----- nrf5/boards/pca10056/mpconfigboard.h | 7 +++++++ 7 files changed, 44 insertions(+), 19 deletions(-) diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index 83d7c25f54..ed655896ea 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -30,9 +30,10 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51" +#define MICROPY_PY_MACHINE_SPI (0) #define MICROPY_PY_MACHINE_PWM (0) -#define MICROPY_PY_MACHINE_TIMER (1) -#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_TIMER (0) +#define MICROPY_PY_MACHINE_RTC (0) #define MICROPY_PY_USOCKET (0) #define MICROPY_PY_NETWORK (0) @@ -60,13 +61,8 @@ // UART config #define MICROPY_HW_UART1_RX (25) #define MICROPY_HW_UART1_TX (24) +#define MICROPY_HW_UART1_RX_PORT (0) +#define MICROPY_HW_UART1_TX_PORT (0) #define MICROPY_HW_UART1_HWFC (0) -// SPI0 config -#define MICROPY_HW_SPI0_NAME "SPI0" -#define MICROPY_HW_SPI0_SCK (1) // A3 -#define MICROPY_HW_SPI0_MOSI (2) // A2 -#define MICROPY_HW_SPI0_MISO (3) // A1 -#define MICROPY_HW_SPI0_NSS (4) // A4 - #define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf5/boards/pca10000/mpconfigboard.h index f149238edd..e38ae686c1 100644 --- a/nrf5/boards/pca10000/mpconfigboard.h +++ b/nrf5/boards/pca10000/mpconfigboard.h @@ -56,8 +56,8 @@ // UART config #define MICROPY_HW_UART1_RX (11) #define MICROPY_HW_UART1_TX (9) -#define MICROPY_HW_UART1_CTS (10) -#define MICROPY_HW_UART1_RTS (8) +#define MICROPY_HW_UART1_RX_PORT (0) +#define MICROPY_HW_UART1_TX_PORT (0) #define MICROPY_HW_UART1_HWFC (0) #define HELP_TEXT_BOARD_LED "1,2,3" diff --git a/nrf5/boards/pca10001/mpconfigboard.h b/nrf5/boards/pca10001/mpconfigboard.h index 1438a3fff3..b440b7f900 100644 --- a/nrf5/boards/pca10001/mpconfigboard.h +++ b/nrf5/boards/pca10001/mpconfigboard.h @@ -30,6 +30,7 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" +#define MICROPY_PY_MACHINE_SPI (0) #define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_HW_HAS_SWITCH (0) @@ -56,6 +57,10 @@ #define MICROPY_HW_UART1_TX (9) #define MICROPY_HW_UART1_CTS (10) #define MICROPY_HW_UART1_RTS (8) +#define MICROPY_HW_UART1_RX_PORT (0) +#define MICROPY_HW_UART1_TX_PORT (0) +#define MICROPY_HW_UART1_RTS_PORT (0) +#define MICROPY_HW_UART1_CTS_PORT (0) #define MICROPY_HW_UART1_HWFC (1) #define HELP_TEXT_BOARD_LED "1,2" diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 401fb61b79..b1faec748e 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -60,6 +60,8 @@ // UART config #define MICROPY_HW_UART1_RX (11) #define MICROPY_HW_UART1_TX (9) +#define MICROPY_HW_UART1_RX_PORT (0) +#define MICROPY_HW_UART1_TX_PORT (0) #define MICROPY_HW_UART1_HWFC (0) // SPI0 config @@ -67,6 +69,8 @@ #define MICROPY_HW_SPI0_SCK (1) // A3 #define MICROPY_HW_SPI0_MOSI (2) // A2 #define MICROPY_HW_SPI0_MISO (3) // A1 -#define MICROPY_HW_SPI0_NSS (4) // A4 +#define MICROPY_HW_SPI0_SCK_PORT (0) +#define MICROPY_HW_SPI0_MISO_PORT (0) +#define MICROPY_HW_SPI0_MOSI_PORT (0) #define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10031/mpconfigboard.h b/nrf5/boards/pca10031/mpconfigboard.h index 2c645a0ff0..2afee5fbfc 100644 --- a/nrf5/boards/pca10031/mpconfigboard.h +++ b/nrf5/boards/pca10031/mpconfigboard.h @@ -57,6 +57,10 @@ #define MICROPY_HW_UART1_TX (9) #define MICROPY_HW_UART1_CTS (10) #define MICROPY_HW_UART1_RTS (8) +#define MICROPY_HW_UART1_RX_PORT (0) +#define MICROPY_HW_UART1_TX_PORT (0) +#define MICROPY_HW_UART1_CTS_PORT (0) +#define MICROPY_HW_UART1_RTS_PORT (0) #define MICROPY_HW_UART1_HWFC (0) // SPI0 config @@ -64,7 +68,8 @@ #define MICROPY_HW_SPI0_SCK (15) // A15 #define MICROPY_HW_SPI0_MOSI (16) // A16 #define MICROPY_HW_SPI0_MISO (17) // A17 -#define MICROPY_HW_SPI0_NSS (18) // A18 - +#define MICROPY_HW_SPI0_SCK_PORT (0) +#define MICROPY_HW_SPI0_MISO_PORT (0) +#define MICROPY_HW_SPI0_MOSI_PORT (0) #define HELP_TEXT_BOARD_LED "1,2,3" diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index fc72d9d07d..40ed17a934 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -30,12 +30,14 @@ #define MICROPY_HW_MCU_NAME "NRF52832" #define MICROPY_PY_SYS_PLATFORM "nrf52-DK" -#define MICROPY_PY_MACHINE_TIMER (1) -#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_PWM (0) +#define MICROPY_PY_MACHINE_SPI (0) +#define MICROPY_PY_MACHINE_TIMER (0) +#define MICROPY_PY_MACHINE_RTC (0) -#define MICROPY_PY_DISPLAY (1) -#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) -#define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) +#define MICROPY_PY_DISPLAY (0) +#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) +#define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) @@ -62,6 +64,12 @@ #define MICROPY_HW_UART1_TX (6) #define MICROPY_HW_UART1_CTS (7) #define MICROPY_HW_UART1_RTS (5) + +#define MICROPY_HW_UART1_RX_PORT (0) +#define MICROPY_HW_UART1_TX_PORT (0) +#define MICROPY_HW_UART1_CTS_PORT (0) +#define MICROPY_HW_UART1_RTS_PORT (0) + #define MICROPY_HW_UART1_HWFC (1) // SPI0 config diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index feee311ddf..caf03462bd 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -30,6 +30,7 @@ #define MICROPY_HW_MCU_NAME "NRF52840" #define MICROPY_PY_SYS_PLATFORM "nrf52840-PDK" +#define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_SPI (0) #define MICROPY_HW_HAS_SWITCH (0) @@ -57,6 +58,12 @@ #define MICROPY_HW_UART1_TX (6) #define MICROPY_HW_UART1_CTS (7) #define MICROPY_HW_UART1_RTS (5) + +#define MICROPY_HW_UART1_RX_PORT (0) +#define MICROPY_HW_UART1_TX_PORT (0) +#define MICROPY_HW_UART1_CTS_PORT (0) +#define MICROPY_HW_UART1_RTS_PORT (0) + #define MICROPY_HW_UART1_HWFC (1) #define MICROPY_HW_PWM0_NAME "PWM0" From ef8e679d7781ebd0fde9006811f25cb79cc2c178 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:08:47 +0100 Subject: [PATCH 130/809] nrf5/pin: Adding PORT_B to Pin port enum to reflect gpio port 1 on nrf52840. --- nrf5/pin_defs_nrf5.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/pin_defs_nrf5.h b/nrf5/pin_defs_nrf5.h index 739b674d63..9922cd5e41 100644 --- a/nrf5/pin_defs_nrf5.h +++ b/nrf5/pin_defs_nrf5.h @@ -30,6 +30,7 @@ enum { PORT_A, + PORT_B, }; enum { From 942942780fe4f2813344e2b9931def653509f2f4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:10:47 +0100 Subject: [PATCH 131/809] nrf5/pin: Adding more pins to nrf52_af.csv file for nrf52840. Port '1' will be prefixed 'B'. --- nrf5/nrf52_af.csv | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/nrf5/nrf52_af.csv b/nrf5/nrf52_af.csv index b54aaa1e31..44a7d8144f 100644 --- a/nrf5/nrf52_af.csv +++ b/nrf5/nrf52_af.csv @@ -29,4 +29,20 @@ PA27,PA27 PA28,PA28 PA29,PA29 PA30,PA30 -PA31,PA31 \ No newline at end of file +PA31,PA31 +PB0,PB0 +PB1,PB1 +PB2,PB2 +PB3,PB3 +PB4,PB4 +PB5,PB5 +PB6,PB6 +PB7,PB7 +PB8,PB8 +PB9,PB9 +PB10,PB10 +PB11,PB11 +PB12,PB12 +PB13,PB13 +PB14,PB14 +PB15,PB15 \ No newline at end of file From 392e226b2cb6b364d651e4e498bfd518ae577c30 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:16:29 +0100 Subject: [PATCH 132/809] nrf5/boards: Adding more pins to nrf52840 / pca10056 target board. --- nrf5/boards/pca10056/pins.csv | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/nrf5/boards/pca10056/pins.csv b/nrf5/boards/pca10056/pins.csv index c177133983..da863e75ab 100644 --- a/nrf5/boards/pca10056/pins.csv +++ b/nrf5/boards/pca10056/pins.csv @@ -1,3 +1,5 @@ +PA0,PA0 +PA1,PA1 PA2,PA2 PA3,PA3 PA4,PA4 @@ -27,4 +29,20 @@ PA27,PA27 PA28,PA28 PA29,PA29 PA30,PA30 -PA31,PA31 \ No newline at end of file +PA31,PA31 +PB0,PB0 +PB1,PB1 +PB2,PB2 +PB3,PB3 +PB4,PB4 +PB5,PB5 +PB6,PB6 +PB7,PB7 +PB8,PB8 +PB9,PB9 +PB10,PB10 +PB11,PB11 +PB12,PB12 +PB13,PB13 +PB14,PB14 +PB15,PB15 From db9eef64a5f0b26d2bf0eb19b1cd256befcfae5c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:20:01 +0100 Subject: [PATCH 133/809] nrf5/hal: Making nrf51/2_hal.h go trough nrf.h to find bitfields and other mcu headers instead of explicit include. --- nrf5/hal/nrf51_hal.h | 3 +-- nrf5/hal/nrf52_hal.h | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/nrf5/hal/nrf51_hal.h b/nrf5/hal/nrf51_hal.h index f6975aaa8e..e4be297054 100644 --- a/nrf5/hal/nrf51_hal.h +++ b/nrf5/hal/nrf51_hal.h @@ -24,8 +24,7 @@ * THE SOFTWARE. */ -#include -#include +#include // include config from board #include "nrf51_hal_conf.h" diff --git a/nrf5/hal/nrf52_hal.h b/nrf5/hal/nrf52_hal.h index 3ebd45cf97..aab3a84512 100644 --- a/nrf5/hal/nrf52_hal.h +++ b/nrf5/hal/nrf52_hal.h @@ -24,8 +24,7 @@ * THE SOFTWARE. */ -#include -#include +#include // include config from board #include "nrf52_hal_conf.h" From c38987240819eb07432d89998add806bcb68f5ed Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:23:00 +0100 Subject: [PATCH 134/809] nrf5/drivers: Block nrf51 from compiling epaper_sld00200p for the moment. There is no soft-pwm present yet, and including pwm would just make compilation fail now. --- nrf5/drivers/display/epaper_sld00200p_driver.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/drivers/display/epaper_sld00200p_driver.h b/nrf5/drivers/display/epaper_sld00200p_driver.h index 22fc2b56a9..ff997340cf 100644 --- a/nrf5/drivers/display/epaper_sld00200p_driver.h +++ b/nrf5/drivers/display/epaper_sld00200p_driver.h @@ -27,6 +27,8 @@ #ifndef EPAPER_SLD00200P_DRIVER_H__ #define EPAPER_SLD00200P_DRIVER_H__ +#if NRF52 // TODO: For now only supported by NRF52 targets, as PWM soft-pwm is not present for nrf51 yet. + #include "py/mphal.h" #include "hal_spi.h" @@ -58,4 +60,6 @@ void driver_sld00200p_clear(uint16_t color); void driver_sld00200p_update_line(uint16_t line, fb_byte_t * p_bytes, fb_byte_t * p_old, uint16_t len, bool compressed); +#endif // NRF52 + #endif // EPAPER_SLD00200P_DRIVER_H__ From b75cefd3835137bd8ddf56c695014a32cf84d8c4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:25:10 +0100 Subject: [PATCH 135/809] nrf5: Exclude import of pwm.h in main.c if MICROPY_PY_MACHINE_PWM is not set, as nrf51 does not yet have this module yet. --- nrf5/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/main.c b/nrf5/main.c index 6621809bce..61202f09b0 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -47,7 +47,9 @@ #include "nrf.h" #include "pin.h" #include "spi.h" +#if MICROPY_PY_MACHINE_PWM #include "pwm.h" +#endif #include "timer.h" #if (BLUETOOTH_SD == 132) From 8e71bcea07fed499814763276578d1886f28af13 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:26:03 +0100 Subject: [PATCH 136/809] nrf5: Exclude import of pwm.h in modmachine.c if MICROPY_PY_MACHINE_PWM is not set, as nrf51 does not yet have this module yet. --- nrf5/modmachine.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/modmachine.c b/nrf5/modmachine.c index 5bcf241d1f..7f6a52fc20 100644 --- a/nrf5/modmachine.c +++ b/nrf5/modmachine.c @@ -39,7 +39,9 @@ #include "gccollect.h" #include "pin.h" #include "spi.h" +#if MICROPY_PY_MACHINE_PWM #include "pwm.h" +#endif #define PYB_RESET_HARD (0) #define PYB_RESET_WDT (1) From ec44f6427bce56ef92dff2ef208f41686c69be0e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:27:35 +0100 Subject: [PATCH 137/809] nrf5/boards: Disable SPI/Timer/RTC hal from microbit board. --- nrf5/boards/microbit/nrf51_hal_conf.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/boards/microbit/nrf51_hal_conf.h b/nrf5/boards/microbit/nrf51_hal_conf.h index 4bd11e1dd5..b24164aeb1 100644 --- a/nrf5/boards/microbit/nrf51_hal_conf.h +++ b/nrf5/boards/microbit/nrf51_hal_conf.h @@ -2,9 +2,9 @@ #define NRF51_HAL_CONF_H__ #define HAL_UART_MODULE_ENABLED -#define HAL_SPI_MODULE_ENABLED +// #define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED -#define HAL_TIMER_MODULE_ENABLED +// #define HAL_RTC_MODULE_ENABLED +// #define HAL_TIMER_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ From 014e6504992271d144324e1fe8600c18ba84ebe7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:28:18 +0100 Subject: [PATCH 138/809] nrf5/boards: Disable SPI hal from pca10001 board. --- nrf5/boards/pca10001/nrf51_hal_conf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/pca10001/nrf51_hal_conf.h b/nrf5/boards/pca10001/nrf51_hal_conf.h index 67cbc983ba..8ea72b4107 100644 --- a/nrf5/boards/pca10001/nrf51_hal_conf.h +++ b/nrf5/boards/pca10001/nrf51_hal_conf.h @@ -2,7 +2,7 @@ #define NRF51_HAL_CONF_H__ #define HAL_UART_MODULE_ENABLED -#define HAL_SPI_MODULE_ENABLED +// #define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ From 43a2355665a60a57814a29070152bccdcd9230ad Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:40:18 +0100 Subject: [PATCH 139/809] nrf5: Updating pin, spi and uart to use port configuration for gpio pins. Update pin generation script, macros for PIN generation. Updating macros for setting pin values adding new port parameter to select the correct GPIO peripheral port. --- nrf5/boards/make-pins.py | 4 +-- nrf5/boards/nrf51_prefix.c | 1 - nrf5/boards/nrf52_prefix.c | 1 - nrf5/hal/hal_spi.c | 13 +++++++--- nrf5/hal/hal_spi.h | 3 +++ nrf5/hal/hal_uart.c | 33 ++++++++++++++++-------- nrf5/mphalport.h | 52 +++++++++++++++++++++----------------- nrf5/pin.c | 5 ++-- nrf5/spi.c | 3 +++ nrf5/uart.c | 18 ++++++++----- 10 files changed, 84 insertions(+), 49 deletions(-) diff --git a/nrf5/boards/make-pins.py b/nrf5/boards/make-pins.py index 11f9ffb3fd..c9ff8ede12 100644 --- a/nrf5/boards/make-pins.py +++ b/nrf5/boards/make-pins.py @@ -17,8 +17,8 @@ def parse_port_pin(name_str): raise ValueError("Expecting pin name to be at least 4 charcters.") if name_str[0] != 'P': raise ValueError("Expecting pin name to start with P") - if name_str[1] not in ('A'): - raise ValueError("Expecting pin port to be in A") + if name_str[1] not in ('A', 'B'): + raise ValueError("Expecting pin port to be in A or B") port = ord(name_str[1]) - ord('A') pin_str = name_str[2:].split('/')[0] if not pin_str.isdigit(): diff --git a/nrf5/boards/nrf51_prefix.c b/nrf5/boards/nrf51_prefix.c index 402bde1a60..a2413fe6bd 100644 --- a/nrf5/boards/nrf51_prefix.c +++ b/nrf5/boards/nrf51_prefix.c @@ -25,7 +25,6 @@ .pin = (p_pin), \ .num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \ .pin_mask = (1 << p_pin), \ - .gpio = GPIO_BASE, \ .af = p_af, \ .adc_num = p_adc_num, \ .adc_channel = p_adc_channel, \ diff --git a/nrf5/boards/nrf52_prefix.c b/nrf5/boards/nrf52_prefix.c index 6bb07dd3a1..89e5df5b10 100644 --- a/nrf5/boards/nrf52_prefix.c +++ b/nrf5/boards/nrf52_prefix.c @@ -25,7 +25,6 @@ .pin = (p_pin), \ .num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \ .pin_mask = (1 << p_pin), \ - .gpio = GPIO_BASE, \ .af = p_af, \ .adc_num = p_adc_num, \ .adc_channel = p_adc_channel, \ diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c index 1ab7623943..3729a2c229 100644 --- a/nrf5/hal/hal_spi.c +++ b/nrf5/hal/hal_spi.c @@ -43,9 +43,9 @@ static const uint32_t hal_spi_frequency_lookup[] = { }; void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) { - hal_gpio_cfg_pin(p_spi_init->clk_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_spi_init->mosi_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_spi_init->miso_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->clk_pin_port, p_spi_init->clk_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->mosi_pin_port, p_spi_init->mosi_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->miso_pin_port, p_spi_init->miso_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); #if NRF51 p_instance->PSELSCK = p_spi_init->clk_pin; @@ -55,6 +55,13 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi p_instance->PSEL.SCK = p_spi_init->clk_pin; p_instance->PSEL.MOSI = p_spi_init->mosi_pin; p_instance->PSEL.MISO = p_spi_init->miso_pin; + +#if NRF52840_XXAA + p_instance->PSEL.SCK |= (p_spi_init->clk_pin_port << SPIE_PSEL_CLK_PORT_Pos); + p_instance->PSEL.MOSI |= (p_spi_init->mosi_pin_port << SPIE_PSEL_MOSI_PORT_Pos); + p_instance->PSEL.MISO |= (p_spi_init->miso_pin_port << SPIE_PSEL_MISO_PORT_Pos); +#endif + #endif p_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq]; diff --git a/nrf5/hal/hal_spi.h b/nrf5/hal/hal_spi.h index ba85328ae6..852ea8b444 100644 --- a/nrf5/hal/hal_spi.h +++ b/nrf5/hal/hal_spi.h @@ -80,6 +80,9 @@ typedef struct { uint8_t mosi_pin; uint8_t miso_pin; uint8_t clk_pin; + uint8_t mosi_pin_port; + uint8_t miso_pin_port; + uint8_t clk_pin_port; bool lsb_first; hal_spi_mode_t mode; uint32_t irq_priority; diff --git a/nrf5/hal/hal_uart.c b/nrf5/hal/hal_uart.c index 392acebe69..a9e3698e69 100644 --- a/nrf5/hal/hal_uart.c +++ b/nrf5/hal/hal_uart.c @@ -27,19 +27,16 @@ #include #include +#include "nrf.h" #include "mphalport.h" #include "hal_uart.h" #ifdef HAL_UART_MODULE_ENABLED #ifdef NRF51 -#include "nrf51.h" -#include "nrf51_bitfields.h" #define UART_BASE ((NRF_UART_Type *) NRF_UART0_BASE) #define UART_IRQ_NUM UART0_IRQn #else -#include "nrf52.h" -#include "nrf52_bitfields.h" #define UART_BASE ((NRF_UART_Type *) NRF_UART0_BASE) #define UART_IRQ_NUM UARTE0_UART0_IRQn #endif @@ -103,18 +100,34 @@ void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_comple } void nrf_uart_init(hal_uart_init_t const * p_uart_init) { - hal_gpio_cfg_pin(p_uart_init->tx_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_uart_init->rx_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->tx_pin_port, p_uart_init->tx_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->tx_pin_port, p_uart_init->rx_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + + hal_gpio_pin_clear(p_uart_init->tx_pin_port, p_uart_init->tx_pin); UART_BASE->PSELTXD = p_uart_init->tx_pin; +#if NRF52840_XXAA + UART_BASE->PSELTXD |= (p_uart_init->tx_pin_port << UARTE_PSEL_TXD_PORT_Pos); +#endif UART_BASE->PSELRXD = p_uart_init->rx_pin; - +#if NRF52840_XXAA + UART_BASE->PSELRXD |= (p_uart_init->rx_pin_port << UARTE_PSEL_RXD_PORT_Pos); +#endif if (p_uart_init->flow_control) { - hal_gpio_cfg_pin(p_uart_init->rts_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_uart_init->cts_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); - +#if MICROPY_HW_UART1_HWFC + hal_gpio_cfg_pin(p_uart_init->rts_pin_port, p_uart_init->rts_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->cts_pin_port, p_uart_init->cts_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + UART_BASE->PSELCTS = p_uart_init->cts_pin; +#if NRF52840_XXAA + UART_BASE->PSELCTS |= (p_uart_init->cts_pin_port << UARTE_PSEL_CTS_PORT_Pos); +#endif UART_BASE->PSELRTS = p_uart_init->rts_pin; +#if NRF52840_XXAA + UART_BASE->PSELRTS |= (p_uart_init->rts_pin_port << UARTE_PSEL_RTS_PORT_Pos); +#endif +#endif + UART_BASE->CONFIG = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos); } diff --git a/nrf5/mphalport.h b/nrf5/mphalport.h index ce8f991e5c..a68ed8ed94 100644 --- a/nrf5/mphalport.h +++ b/nrf5/mphalport.h @@ -40,11 +40,17 @@ typedef enum } HAL_StatusTypeDef; -#ifdef NRF51 -#define GPIO_BASE ((NRF_GPIO_Type *)NRF_GPIO_BASE) -#else -#define GPIO_BASE ((NRF_GPIO_Type *)NRF_P0_BASE) +#if NRF51 +#define POINTERS (const uint32_t[]){NRF_GPIO_BASE} +#elif NRF52 +#ifdef NRF52832_XXAA +#define POINTERS (const uint32_t[]){NRF_P0_BASE} +#elif NRF52840_XXAA +#define POINTERS (const uint32_t[]){NRF_P0_BASE, NRF_P1_BASE} #endif +#endif + +#define GPIO_BASE(x) ((NRF_GPIO_Type *)POINTERS[x]) /** * @brief GPIO Init structure definition @@ -78,33 +84,33 @@ typedef enum { HAL_GPIO_MODE_INPUT = (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos), } hal_gpio_mode_t; -static inline void hal_gpio_cfg_pin(uint32_t pin_number, hal_gpio_mode_t mode, hal_gpio_pull_t pull) { - GPIO_BASE->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | pull - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | mode; +static inline void hal_gpio_cfg_pin(uint8_t port, uint32_t pin_number, hal_gpio_mode_t mode, hal_gpio_pull_t pull) { + GPIO_BASE(port)->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | pull + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | mode; } -static inline void hal_gpio_out_set(uint32_t pin_mask) { - GPIO_BASE->OUTSET = pin_mask; +static inline void hal_gpio_out_set(uint8_t port, uint32_t pin_mask) { + GPIO_BASE(port)->OUTSET = pin_mask; } -static inline void hal_gpio_pin_set(uint32_t pin) { - GPIO_BASE->OUTSET = (1 << pin); +static inline void hal_gpio_pin_set(uint8_t port, uint32_t pin) { + GPIO_BASE(port)->OUTSET = (1 << pin); } -static inline void hal_gpio_pin_clear(uint32_t pin) { - GPIO_BASE->OUTCLR = (1 << pin); +static inline void hal_gpio_pin_clear(uint8_t port, uint32_t pin) { + GPIO_BASE(port)->OUTCLR = (1 << pin); } -static inline void hal_gpio_pin_toggle(uint32_t pin) { +static inline void hal_gpio_pin_toggle(uint8_t port, uint32_t pin) { uint32_t pin_mask = (1 << pin); - if (GPIO_BASE->OUT ^ pin_mask) { - GPIO_BASE->OUTSET = pin_mask; + if (GPIO_BASE(port)->OUT ^ pin_mask) { + GPIO_BASE(port)->OUTSET = pin_mask; } else { - GPIO_BASE->OUTCLR = pin_mask; + GPIO_BASE(port)->OUTCLR = pin_mask; } } @@ -123,9 +129,9 @@ int mp_hal_stdin_rx_chr(void); void mp_hal_stdout_tx_str(const char *str); #define mp_hal_pin_obj_t const pin_obj_t* -#define mp_hal_pin_high(p) (((NRF_GPIO_Type *)((p)->gpio))->OUTSET = (p)->pin_mask) -#define mp_hal_pin_low(p) (((NRF_GPIO_Type *)((p)->gpio))->OUTCLR = (p)->pin_mask) -#define mp_hal_pin_read(p) (((NRF_GPIO_Type *)((p)->gpio))->IN >> ((p)->pin) & 1) +#define mp_hal_pin_high(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTSET = (p)->pin_mask) +#define mp_hal_pin_low(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask) +#define mp_hal_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1) #define mp_hal_pin_write(p, v) do { if (v) { mp_hal_pin_high(p); } else { mp_hal_pin_low(p); } } while (0) // TODO: empty implementation for now. Used by machine_spi.c:69 diff --git a/nrf5/pin.c b/nrf5/pin.c index 1debbaa0d3..b1690c7b5f 100644 --- a/nrf5/pin.c +++ b/nrf5/pin.c @@ -187,7 +187,8 @@ STATIC void pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t // pin name mp_printf(print, "Pin(Pin.cpu.%q, mode=Pin.", self->name); - mp_printf(print, "gpio=0x%x,", self->gpio); + mp_printf(print, "port=0x%x, ", self->port); + mp_printf(print, "pin=0x%x, ", self->pin); mp_printf(print, "pin_mask=0x%x,", self->pin_mask); /* uint32_t mode = pin_get_mode(self); @@ -356,7 +357,7 @@ STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, con // get io mode uint mode = args[0].u_int; if (mode == HAL_GPIO_MODE_OUTPUT || mode == HAL_GPIO_MODE_INPUT) { - hal_gpio_cfg_pin(self->pin, mode, pull); + hal_gpio_cfg_pin(self->port, self->pin, mode, pull); } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "invalid pin mode: %d", mode)); } diff --git a/nrf5/spi.c b/nrf5/spi.c index 1306a8f8ee..d61fb5b1bf 100644 --- a/nrf5/spi.c +++ b/nrf5/spi.c @@ -255,6 +255,9 @@ STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) { self->pyb->spi->init.clk_pin = MICROPY_HW_SPI0_SCK; self->pyb->spi->init.mosi_pin = MICROPY_HW_SPI0_MOSI; self->pyb->spi->init.miso_pin = MICROPY_HW_SPI0_MISO; + self->pyb->spi->init.clk_pin_port = MICROPY_HW_SPI0_SCK_PORT; + self->pyb->spi->init.mosi_pin_port = MICROPY_HW_SPI0_MOSI_PORT; + self->pyb->spi->init.miso_pin_port = MICROPY_HW_SPI0_MISO_PORT; } int baudrate = args[ARG_NEW_baudrate].u_int; diff --git a/nrf5/uart.c b/nrf5/uart.c index cb05c2359f..4edaea3881 100644 --- a/nrf5/uart.c +++ b/nrf5/uart.c @@ -202,13 +202,6 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, con } hal_uart_init_t uart_init = { - .rx_pin = MICROPY_HW_UART1_RX, - .tx_pin = MICROPY_HW_UART1_TX, -#if MICROPY_HW_UART1_HWFC - .rts_pin = MICROPY_HW_UART1_RTS, - .cts_pin = MICROPY_HW_UART1_CTS, -#endif - #if MICROPY_HW_UART1_HWFC .flow_control = true, #else @@ -222,6 +215,17 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, con .irq_priority = 6 #endif }; + uart_init.rx_pin = MICROPY_HW_UART1_RX; + uart_init.tx_pin = MICROPY_HW_UART1_TX; + uart_init.rx_pin_port = MICROPY_HW_UART1_RX_PORT; + uart_init.tx_pin_port = MICROPY_HW_UART1_TX_PORT; + +#if MICROPY_HW_UART1_HWFC + uart_init.rts_pin = MICROPY_HW_UART1_RTS; + uart_init.cts_pin = MICROPY_HW_UART1_CTS; + uart_init.rts_pin_port = MICROPY_HW_UART1_RTS_PORT; + uart_init.cts_pin_port = MICROPY_HW_UART1_CTS_PORT; +#endif nrf_uart_init(&uart_init); From 3e1da27f2b534c8e1605e9d886e6dfe1ba49ace3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:41:11 +0100 Subject: [PATCH 140/809] nrf5/hal: Changing import of nrf52 includes in hal_uarte.c to not be explicit. Now only nrf.h is included. --- nrf5/hal/hal_uarte.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/nrf5/hal/hal_uarte.c b/nrf5/hal/hal_uarte.c index ff3bd978a3..496c40e9b1 100644 --- a/nrf5/hal/hal_uarte.c +++ b/nrf5/hal/hal_uarte.c @@ -32,8 +32,7 @@ #ifdef HAL_UARTE_MODULE_ENABLED -#include "nrf52.h" -#include "nrf52_bitfields.h" +#include "nrf.h" #if NRF52 From 604ae87192e98f4fff39da6af90ebd2e87bfc263 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 16:41:48 +0100 Subject: [PATCH 141/809] nrf5/led: Hardcoding GPIO port 0 for Led module for now. --- nrf5/led.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/nrf5/led.c b/nrf5/led.c index 8cd0d69861..0c9bd8928a 100644 --- a/nrf5/led.c +++ b/nrf5/led.c @@ -31,13 +31,14 @@ #include "led.h" #include "mpconfigboard.h" -#define LED_OFF(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_set(led) : hal_gpio_pin_clear(led); } -#define LED_ON(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_clear(led) : hal_gpio_pin_set(led); } +#define LED_OFF(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_set(0, led) : hal_gpio_pin_clear(0, led); } +#define LED_ON(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_clear(0, led) : hal_gpio_pin_set(0, led); } typedef struct _pyb_led_obj_t { mp_obj_base_t base; mp_uint_t led_id; mp_uint_t hw_pin; + uint8_t hw_pin_port; } pyb_led_obj_t; STATIC const pyb_led_obj_t pyb_led_obj[] = { @@ -63,7 +64,7 @@ STATIC const pyb_led_obj_t pyb_led_obj[] = { void led_init(void) { for (uint8_t i = 0; i < NUM_LEDS; i++) { LED_OFF(pyb_led_obj[i].hw_pin); - hal_gpio_cfg_pin(pyb_led_obj[i].hw_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(0, pyb_led_obj[i].hw_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); } } @@ -76,7 +77,7 @@ void led_state(pyb_led_obj_t * led_obj, int state) { } void led_toggle(pyb_led_obj_t * led_obj) { - hal_gpio_pin_toggle(led_obj->hw_pin); + hal_gpio_pin_toggle(0, led_obj->hw_pin); } From 0676c9774aa8f821add0aa1b7d6798dc5a1a9287 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 20:31:12 +0100 Subject: [PATCH 142/809] nrf5/hal: Correcting SPI psel port position define name to the one defined in nrf52840_bitfields.h --- nrf5/hal/hal_spi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c index 3729a2c229..72cb716e3e 100644 --- a/nrf5/hal/hal_spi.c +++ b/nrf5/hal/hal_spi.c @@ -57,9 +57,9 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi p_instance->PSEL.MISO = p_spi_init->miso_pin; #if NRF52840_XXAA - p_instance->PSEL.SCK |= (p_spi_init->clk_pin_port << SPIE_PSEL_CLK_PORT_Pos); - p_instance->PSEL.MOSI |= (p_spi_init->mosi_pin_port << SPIE_PSEL_MOSI_PORT_Pos); - p_instance->PSEL.MISO |= (p_spi_init->miso_pin_port << SPIE_PSEL_MISO_PORT_Pos); + p_instance->PSEL.SCK |= (p_spi_init->clk_pin_port << SPI_PSEL_SCK_PORT_Pos); + p_instance->PSEL.MOSI |= (p_spi_init->mosi_pin_port << SPI_PSEL_MOSI_PORT_Pos); + p_instance->PSEL.MISO |= (p_spi_init->miso_pin_port << SPI_PSEL_MISO_PORT_Pos); #endif #endif From bc22cc9ce8c6565013cbdad6e17e4e8027a425f3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 21:16:31 +0100 Subject: [PATCH 143/809] nrf5/boards: Enabling display drivers/spi/pwm to be compiled in on pca10040 target board. Updating SPI configuration with gpio port. --- nrf5/boards/pca10040/mpconfigboard.h | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 40ed17a934..16a821459f 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -30,14 +30,14 @@ #define MICROPY_HW_MCU_NAME "NRF52832" #define MICROPY_PY_SYS_PLATFORM "nrf52-DK" -#define MICROPY_PY_MACHINE_PWM (0) -#define MICROPY_PY_MACHINE_SPI (0) -#define MICROPY_PY_MACHINE_TIMER (0) -#define MICROPY_PY_MACHINE_RTC (0) +#define MICROPY_PY_MACHINE_PWM (1) +#define MICROPY_PY_MACHINE_SPI (1) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) -#define MICROPY_PY_DISPLAY (0) -#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) -#define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) +#define MICROPY_PY_DISPLAY (1) +#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) +#define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) @@ -77,7 +77,9 @@ #define MICROPY_HW_SPI0_SCK (25) // A25 (Arduino D13) #define MICROPY_HW_SPI0_MOSI (23) // A23 (Arduino D11) #define MICROPY_HW_SPI0_MISO (24) // A24 (Arduino D12) -#define MICROPY_HW_SPI0_NSS (22) // A22 (Arduino D10) +#define MICROPY_HW_SPI0_SCK_PORT (0) +#define MICROPY_HW_SPI0_MOSI_PORT (0) +#define MICROPY_HW_SPI0_MISO_PORT (0) #define MICROPY_HW_PWM0_NAME "PWM0" #define MICROPY_HW_PWM1_NAME "PWM1" From c8cc2aa6f9a0c3eb791e6d288a83c04a8684a6ac Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 21:18:18 +0100 Subject: [PATCH 144/809] nrf5/boards: Enabling ili9341 display drivers and to be compiled in on pca10056 target board. Updating SPI configuration with gpio port. --- nrf5/boards/pca10056/mpconfigboard.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index caf03462bd..4ffd372d81 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -31,7 +31,11 @@ #define MICROPY_PY_SYS_PLATFORM "nrf52840-PDK" #define MICROPY_PY_MACHINE_PWM (0) -#define MICROPY_PY_MACHINE_SPI (0) +#define MICROPY_PY_MACHINE_SPI (1) + +#define MICROPY_PY_DISPLAY (1) +#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) +#define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) @@ -66,6 +70,16 @@ #define MICROPY_HW_UART1_HWFC (1) +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (15) // B15 (Arduino D13) +#define MICROPY_HW_SPI0_MOSI (13) // B13 (Arduino D11) +#define MICROPY_HW_SPI0_MISO (14) // B14 (Arduino D12) +#define MICROPY_HW_SPI0_SCK_PORT (1) +#define MICROPY_HW_SPI0_MOSI_PORT (1) +#define MICROPY_HW_SPI0_MISO_PORT (1) + + #define MICROPY_HW_PWM0_NAME "PWM0" #define MICROPY_HW_PWM1_NAME "PWM1" #define MICROPY_HW_PWM2_NAME "PWM2" From 268d9885536ac2fbdff7bed6072719c982e57fb3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 21:19:23 +0100 Subject: [PATCH 145/809] nrf5/boards: Enabling spi in pca10056 hal config. --- nrf5/boards/pca10056/nrf52_hal_conf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/pca10056/nrf52_hal_conf.h b/nrf5/boards/pca10056/nrf52_hal_conf.h index 3cfe4c0321..1ea1005c3c 100644 --- a/nrf5/boards/pca10056/nrf52_hal_conf.h +++ b/nrf5/boards/pca10056/nrf52_hal_conf.h @@ -3,7 +3,7 @@ #define HAL_UART_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED -// #define HAL_SPI_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED #define HAL_PWM_MODULE_ENABLED From 130f407287e054012cd28ffe48be53a120225f1c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 21:20:12 +0100 Subject: [PATCH 146/809] nrf5/devices: Removing define which clutters ported modules from nrf.h. --- nrf5/device/nrf.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/nrf5/device/nrf.h b/nrf5/device/nrf.h index 277e94148d..b74af23e6e 100644 --- a/nrf5/device/nrf.h +++ b/nrf5/device/nrf.h @@ -36,13 +36,6 @@ #define MDK_MINOR_VERSION 11 #define MDK_MICRO_VERSION 1 -/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ -#if defined (NRF52) - #ifndef NRF52832_XXAA - #define NRF52832_XXAA - #endif -#endif - /* Define NRF52_SERIES for common use in nRF52 series devices. */ #if defined (NRF52832_XXAA) || defined (NRF52840_XXAA) #define NRF52_SERIES From b83052f8d1a934ca2433b9661bd900acf6a8cc99 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 21:20:59 +0100 Subject: [PATCH 147/809] nrf5/hal: Refining if-defs to set up GPIO base pointers in mphalport.h --- nrf5/mphalport.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/nrf5/mphalport.h b/nrf5/mphalport.h index a68ed8ed94..5c62754727 100644 --- a/nrf5/mphalport.h +++ b/nrf5/mphalport.h @@ -41,13 +41,17 @@ typedef enum #if NRF51 -#define POINTERS (const uint32_t[]){NRF_GPIO_BASE} -#elif NRF52 -#ifdef NRF52832_XXAA -#define POINTERS (const uint32_t[]){NRF_P0_BASE} -#elif NRF52840_XXAA -#define POINTERS (const uint32_t[]){NRF_P0_BASE, NRF_P1_BASE} + #define POINTERS (const uint32_t[]){NRF_GPIO_BASE} #endif + +#if NRF52 + #ifdef NRF52832_XXAA + #define POINTERS (const uint32_t[]){NRF_P0_BASE} + #endif + + #ifdef NRF52840_XXAA + #define POINTERS (const uint32_t[]){NRF_P0_BASE, NRF_P1_BASE} + #endif #endif #define GPIO_BASE(x) ((NRF_GPIO_Type *)POINTERS[x]) From 06e0f5d0813eb727839487dfc02aa919eb5133ec Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 21:23:33 +0100 Subject: [PATCH 148/809] nrf5/examples: Removing tabs from epaper python script usage comment, so that it is easier to copy paste. --- nrf5/examples/epaper.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/nrf5/examples/epaper.py b/nrf5/examples/epaper.py index ff08b1303e..743ae2e0cb 100644 --- a/nrf5/examples/epaper.py +++ b/nrf5/examples/epaper.py @@ -41,15 +41,15 @@ EPAPER_CLK 25 (Arduino D13) Example usage on pca10040: - from epaper import Epaper +from epaper import Epaper - epd = Epaper() - epd.fill(0) - epd.text("Hello World!", 50, 50) - epd.show() +epd = Epaper() +epd.fill(0) +epd.text("Hello World!", 50, 50) +epd.show() - epd.refresh() - epd.refresh() +epd.refresh() +epd.refresh() """ import os From 8a69f42f8433b68bbd6c184acba383f67ad4a401 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 21:25:42 +0100 Subject: [PATCH 149/809] nrf5/drivers: Adding an initial script as comment for ili9341 on nrf52840/pca10056 in the driver module comment. --- nrf5/drivers/display/lcd_ili9341_obj.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/drivers/display/lcd_ili9341_obj.c index 1987131efe..5e929b0a51 100644 --- a/nrf5/drivers/display/lcd_ili9341_obj.c +++ b/nrf5/drivers/display/lcd_ili9341_obj.c @@ -91,6 +91,8 @@ enum { }; /* +Example for nrf52832 / pca10040: + from machine import Pin, SPI from display import ILI9341 cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) @@ -99,6 +101,18 @@ spi = SPI(0, baudrate=8000000) d = ILI9341(240, 320, spi, cs, dc) d.text("Hello World!", 32, 32) d.show() + +Example for nrf52840 / pca10056: + +from machine import Pin, SPI +from display import ILI9341 +cs = Pin("B6", mode=Pin.OUT, pull=Pin.PULL_UP) +dc = Pin("B7", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +d = ILI9341(240, 320, spi, cs, dc) +d.text("Hello World!", 32, 32) +d.show() + */ STATIC mp_obj_t lcd_ili9341_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { From 859380afe8660d18d5507e9fd3f52436a9526b28 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 21:27:37 +0100 Subject: [PATCH 150/809] nrf5/drivers: Correcting object print function to also include port number of the SPI pins. Correcting usage script example in comment. --- nrf5/drivers/display/epaper_sld00200p_obj.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/nrf5/drivers/display/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper_sld00200p_obj.c index 46ac21fe19..ebd59a89b2 100644 --- a/nrf5/drivers/display/epaper_sld00200p_obj.c +++ b/nrf5/drivers/display/epaper_sld00200p_obj.c @@ -74,10 +74,14 @@ static void dirty_line_update_cb(mp_obj_framebuf_t * p_framebuffer, STATIC void epaper_sld00200_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { epaper_sld00200p_obj_t *self = o; - mp_printf(print, "ILI9341(SPI(mosi=%u, miso=%u, clk=%u),\n", + mp_printf(print, "SLD00200(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", + self->spi->pyb->spi->init.mosi_pin_port, self->spi->pyb->spi->init.mosi_pin, + self->spi->pyb->spi->init.miso_pin_port, self->spi->pyb->spi->init.miso_pin, - self->spi->pyb->spi->init.clk_pin); + self->spi->pyb->spi->init.clk_pin_port, + self->spi->pyb->spi->init.clk_pin + ); mp_printf(print, " PWM(pwm_pin=%u),\n", self->pwm->pyb->pwm->init.pwm_pin); @@ -123,7 +127,6 @@ enum { /* from machine import Pin, SPI, PWM from display import SLD00200P -cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) reset = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) panel_on = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) discharge = Pin("A19", mode=Pin.OUT, pull=Pin.PULL_UP) @@ -131,7 +134,7 @@ border = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) busy = Pin("A18", mode=Pin.IN, pull=Pin.PULL_DISABLED) cs = Pin("A22", mode=Pin.OUT, pull=Pin.PULL_UP) spi = SPI(0, baudrate=8000000) -pwm = PWM(0, Pin("A16", mode=Pin.OUT), freq=PWM.FREQ_250KHZ, duty=50, period=2) +pwm = PWM(0, Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP), freq=PWM.FREQ_250KHZ, duty=50, period=2) d = SLD00200P(264, 176, spi, pwm, cs, panel_on, border, busy, reset, discharge) d.text("Hello World!", 32, 32) d.show() From 9a8bf934c680bd1297d018c273a95f4e9c306d64 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 21:29:13 +0100 Subject: [PATCH 151/809] nrf5/drivers: bugfix of the sld00200p driver. Stopping the pwm instead of restarting it. Shuffle placement of static function. --- .../drivers/display/epaper_sld00200p_driver.c | 168 +++++++++--------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/nrf5/drivers/display/epaper_sld00200p_driver.c b/nrf5/drivers/display/epaper_sld00200p_driver.c index b4efe726bf..d13570d666 100644 --- a/nrf5/drivers/display/epaper_sld00200p_driver.c +++ b/nrf5/drivers/display/epaper_sld00200p_driver.c @@ -182,7 +182,7 @@ void driver_sld00200p_reinit(void) { mp_hal_delay_us(30); // stop the pwm - hal_pwm_start(mp_pwm_instance); + hal_pwm_stop(mp_pwm_instance); // charge pump negative voltage on mp_hal_delay_us(10); @@ -207,89 +207,6 @@ void driver_sld00200p_reinit(void) { DATA_WRITE(0x72, 0x24); } -void driver_sld00200p_deinit(void) { - epaper_sld00200p_line(0x7fffu, 0, 0x55, EPD_NORM); - mp_hal_delay_ms(25); - mp_hal_pin_low(mp_pin_border); - mp_hal_delay_ms(250); - mp_hal_pin_high(mp_pin_border); - - // latch reset turn on - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x03); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x01); - - // output enable off - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x02); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x05); - - // Vcom power off - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x05); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x0e); - - // power off negative charge pump - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x05); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x02); - - // discharge - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x04); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x0c); - mp_hal_delay_us(120); - - // all charge pumps off - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x05); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x00); - - // turn of osc - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x07); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x0d); - - // discharge internal - 1 - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x04); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x50); - mp_hal_delay_us(40); - - // discharge internal - 2 - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x04); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0xA0); - mp_hal_delay_us(40); - - // discharge internal - 3 - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x04); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x00); - - // turn of power and all signals - mp_hal_delay_ms(10); - mp_hal_pin_low(mp_pin_reset); - mp_hal_pin_low(mp_pin_panel_on); - mp_hal_pin_low(mp_pin_border); - - // discharge pulse - mp_hal_pin_high(mp_pin_discharge); - mp_hal_delay_us(250); - mp_hal_pin_low(mp_pin_discharge); - mp_hal_pin_high(mp_pin_cs); -} - static void epaper_sld00200p_line(uint16_t line, const uint8_t * data, uint8_t fixed_value, epd_stage_t stage) { mp_hal_delay_ms(10); @@ -414,6 +331,89 @@ static void epaper_sld00200p_line(uint16_t line, const uint8_t * data, uint8_t f DATA_WRITE(0x72, 0x2f); } +void driver_sld00200p_deinit(void) { + epaper_sld00200p_line(0x7fffu, 0, 0x55, EPD_NORM); + mp_hal_delay_ms(25); + mp_hal_pin_low(mp_pin_border); + mp_hal_delay_ms(250); + mp_hal_pin_high(mp_pin_border); + + // latch reset turn on + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x03); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x01); + + // output enable off + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x02); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x05); + + // Vcom power off + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x05); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x0e); + + // power off negative charge pump + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x05); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x02); + + // discharge + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x04); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x0c); + mp_hal_delay_us(120); + + // all charge pumps off + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x05); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x00); + + // turn of osc + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x07); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x0d); + + // discharge internal - 1 + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x04); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x50); + mp_hal_delay_us(40); + + // discharge internal - 2 + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x04); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0xA0); + mp_hal_delay_us(40); + + // discharge internal - 3 + mp_hal_delay_us(10); + DATA_WRITE(0x70, 0x04); + mp_hal_delay_us(10); + DATA_WRITE(0x72, 0x00); + + // turn of power and all signals + mp_hal_delay_ms(10); + mp_hal_pin_low(mp_pin_reset); + mp_hal_pin_low(mp_pin_panel_on); + mp_hal_pin_low(mp_pin_border); + + // discharge pulse + mp_hal_pin_high(mp_pin_discharge); + mp_hal_delay_us(250); + mp_hal_pin_low(mp_pin_discharge); + mp_hal_pin_high(mp_pin_cs); +} + void driver_sld00200p_clear(uint16_t color) { uint16_t line_count = 176; for (uint16_t i = 0; i < line_count; i++) { From 4ca61a9d0e3f0f789e3da7931805bf2e96cef224 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 22:34:48 +0100 Subject: [PATCH 152/809] nrf5/boards: Giving a bit more heap for nrf52840 linker script. --- nrf5/boards/nrf52840_aa.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/nrf52840_aa.ld b/nrf5/boards/nrf52840_aa.ld index 1f31e21cb6..96365f54eb 100644 --- a/nrf5/boards/nrf52840_aa.ld +++ b/nrf5/boards/nrf52840_aa.ld @@ -13,7 +13,7 @@ MEMORY /* produce a link error if there is not this amount of RAM for these sections */ _minimum_stack_size = 2K; -_minimum_heap_size = 16K; +_minimum_heap_size = 32K; /* top end of the stack */ @@ -22,6 +22,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20005000; /* tunable */ +_heap_end = 0x20008000; /* tunable */ INCLUDE "boards/common.ld" From 6b976c410c9fdd1810744d47b00c8041cf2536d5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 8 Jan 2017 22:35:46 +0100 Subject: [PATCH 153/809] nrf5/drivers: Extending print function for ili9341 object to also print out gpio port of the SPI pins. --- nrf5/drivers/display/lcd_ili9341_obj.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/drivers/display/lcd_ili9341_obj.c index 5e929b0a51..b90de7950b 100644 --- a/nrf5/drivers/display/lcd_ili9341_obj.c +++ b/nrf5/drivers/display/lcd_ili9341_obj.c @@ -65,10 +65,14 @@ static void dirty_line_update_cb(mp_obj_framebuf_t * p_framebuffer, STATIC void lcd_ili9341_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { lcd_ili9341_obj_t *self = o; - mp_printf(print, "ILI9341(SPI(mosi=%u, miso=%u, clk=%u),\n", + mp_printf(print, "ILI9341(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", + self->spi->pyb->spi->init.mosi_pin_port, self->spi->pyb->spi->init.mosi_pin, + self->spi->pyb->spi->init.miso_pin_port, self->spi->pyb->spi->init.miso_pin, - self->spi->pyb->spi->init.clk_pin); + self->spi->pyb->spi->init.clk_pin_port, + self->spi->pyb->spi->init.clk_pin + ); mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u),\n", self->pin_cs->port, From 2ac3b23c0ef9d266f86b2147bf56a0e5cd3d3cef Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 9 Jan 2017 17:51:16 +0100 Subject: [PATCH 154/809] nrf5/drivers: Updating ili9341 driver to set CS high after cmd or data write. --- nrf5/drivers/display/lcd_ili9341_driver.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/display/lcd_ili9341_driver.c b/nrf5/drivers/display/lcd_ili9341_driver.c index 5201b5d3a0..17af3f235a 100644 --- a/nrf5/drivers/display/lcd_ili9341_driver.c +++ b/nrf5/drivers/display/lcd_ili9341_driver.c @@ -49,7 +49,7 @@ static void cmd_write(uint8_t value) hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); - mp_hal_pin_low(mp_cs_pin); + mp_hal_pin_high(mp_cs_pin); } static void data_write(uint8_t value) @@ -59,7 +59,7 @@ static void data_write(uint8_t value) hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); - mp_hal_pin_low(mp_cs_pin); + mp_hal_pin_high(mp_cs_pin); } void driver_ili9341_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_obj_t * p_dc_pin) From 22c7cf73580059efa20df6cda27bac96e7507041 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 9 Jan 2017 17:52:42 +0100 Subject: [PATCH 155/809] nrf5/examples: Adding copy of ssd1306.py driver hardcoded with SPI and Pin assignments. --- nrf5/examples/ssd1306.py | 172 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 nrf5/examples/ssd1306.py diff --git a/nrf5/examples/ssd1306.py b/nrf5/examples/ssd1306.py new file mode 100644 index 0000000000..843ff377a0 --- /dev/null +++ b/nrf5/examples/ssd1306.py @@ -0,0 +1,172 @@ +# MicroPython SSD1306 OLED driver, I2C and SPI interfaces + +import time +import framebuf +from machine import SPI, Pin + +# register definitions +SET_CONTRAST = const(0x81) +SET_ENTIRE_ON = const(0xa4) +SET_NORM_INV = const(0xa6) +SET_DISP = const(0xae) +SET_MEM_ADDR = const(0x20) +SET_COL_ADDR = const(0x21) +SET_PAGE_ADDR = const(0x22) +SET_DISP_START_LINE = const(0x40) +SET_SEG_REMAP = const(0xa0) +SET_MUX_RATIO = const(0xa8) +SET_COM_OUT_DIR = const(0xc0) +SET_DISP_OFFSET = const(0xd3) +SET_COM_PIN_CFG = const(0xda) +SET_DISP_CLK_DIV = const(0xd5) +SET_PRECHARGE = const(0xd9) +SET_VCOM_DESEL = const(0xdb) +SET_CHARGE_PUMP = const(0x8d) + + +class SSD1306: + def __init__(self, width, height, external_vcc): + self.width = width + self.height = height + self.external_vcc = external_vcc + self.pages = self.height // 8 + self.buffer = bytearray(self.pages * self.width) + self.framebuf = framebuf.FrameBuffer1(self.buffer, self.width, self.height) + self.poweron() + self.init_display() + + def init_display(self): + for cmd in ( + SET_DISP | 0x00, # off + # address setting + SET_MEM_ADDR, 0x00, # horizontal + # resolution and layout + SET_DISP_START_LINE | 0x00, + SET_SEG_REMAP | 0x01, # column addr 127 mapped to SEG0 + SET_MUX_RATIO, self.height - 1, + SET_COM_OUT_DIR | 0x08, # scan from COM[N] to COM0 + SET_DISP_OFFSET, 0x00, + SET_COM_PIN_CFG, 0x02 if self.height == 32 else 0x12, + # timing and driving scheme + SET_DISP_CLK_DIV, 0x80, + SET_PRECHARGE, 0x22 if self.external_vcc else 0xf1, + SET_VCOM_DESEL, 0x30, # 0.83*Vcc + # display + SET_CONTRAST, 0xff, # maximum + SET_ENTIRE_ON, # output follows RAM contents + SET_NORM_INV, # not inverted + # charge pump + SET_CHARGE_PUMP, 0x10 if self.external_vcc else 0x14, + SET_DISP | 0x01): # on + self.write_cmd(cmd) + self.fill(0) + self.show() + + def poweroff(self): + self.write_cmd(SET_DISP | 0x00) + + def contrast(self, contrast): + self.write_cmd(SET_CONTRAST) + self.write_cmd(contrast) + + def invert(self, invert): + self.write_cmd(SET_NORM_INV | (invert & 1)) + + def show(self): + x0 = 0 + x1 = self.width - 1 + if self.width == 64: + # displays with width of 64 pixels are shifted by 32 + x0 += 32 + x1 += 32 + self.write_cmd(SET_COL_ADDR) + self.write_cmd(x0) + self.write_cmd(x1) + self.write_cmd(SET_PAGE_ADDR) + self.write_cmd(0) + self.write_cmd(self.pages - 1) + self.write_data(self.buffer) + + def fill(self, col): + self.framebuf.fill(col) + + def pixel(self, x, y, col): + self.framebuf.pixel(x, y, col) + + def scroll(self, dx, dy): + self.framebuf.scroll(dx, dy) + + def text(self, string, x, y, col=1): + self.framebuf.text(string, x, y, col) + + +class SSD1306_I2C(SSD1306): + def __init__(self, width, height, i2c, addr=0x3c, external_vcc=False): + self.i2c = i2c + self.addr = addr + self.temp = bytearray(2) + super().__init__(width, height, external_vcc) + + def write_cmd(self, cmd): + self.temp[0] = 0x80 # Co=1, D/C#=0 + self.temp[1] = cmd + self.i2c.writeto(self.addr, self.temp) + + def write_data(self, buf): + self.temp[0] = self.addr << 1 + self.temp[1] = 0x40 # Co=0, D/C#=1 + self.i2c.start() + self.i2c.write(self.temp) + self.i2c.write(buf) + self.i2c.stop() + + def poweron(self): + pass + +class SSD1306_SPI(SSD1306): + def __init__(self, width, height, external_vcc=False): + self.rate = 10 * 1024 * 1024 + self.spi = SPI(0, baudrate=4000000) + +# self.dc = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) +# self.dc.low() +# +# self.res = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) +# self.res.low() +# +# self.cs = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) +# self.cs.high() + + self.dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) + self.dc.low() + + self.res = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) + self.res.low() + + self.cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) + self.cs.high() + + super().__init__(width, height, external_vcc) + + def write_cmd(self, cmd): + self.spi.init(baudrate=self.rate, polarity=0, phase=0) + self.cs.high() + self.dc.low() + self.cs.low() + self.spi.write(bytearray([cmd])) + self.cs.high() + + def write_data(self, buf): + self.spi.init(baudrate=self.rate, polarity=0, phase=0) + self.cs.high() + self.dc.high() + self.cs.low() + self.spi.write(buf) + self.cs.high() + + def poweron(self): + self.res.high() + time.sleep_ms(1) + self.res.low() + time.sleep_ms(10) + self.res.high() From 1208970f6c6100106c545a192e0ef98a3d703a17 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 9 Jan 2017 19:33:01 +0100 Subject: [PATCH 156/809] nrf5/drivers: Adding some more delay on bootup to ensure display recovers after reset. --- nrf5/drivers/display/lcd_ili9341_driver.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/display/lcd_ili9341_driver.c b/nrf5/drivers/display/lcd_ili9341_driver.c index 17af3f235a..87e193185d 100644 --- a/nrf5/drivers/display/lcd_ili9341_driver.c +++ b/nrf5/drivers/display/lcd_ili9341_driver.c @@ -77,11 +77,11 @@ void driver_ili9341_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_ob // Read driver id - mp_hal_delay_ms(500); + mp_hal_delay_ms(1000); cmd_write(0x01); - mp_hal_delay_ms(200); + mp_hal_delay_ms(500); cmd_write(0xCF); data_write(0x00); From dd7007240ccb0c8733c436a610680e6b8b871405 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 9 Jan 2017 19:44:31 +0100 Subject: [PATCH 157/809] nrf5/boards: Enable PWM module and epaper display module in pca10056 board config. --- nrf5/boards/pca10056/mpconfigboard.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index 4ffd372d81..7142d23a5f 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -30,11 +30,11 @@ #define MICROPY_HW_MCU_NAME "NRF52840" #define MICROPY_PY_SYS_PLATFORM "nrf52840-PDK" -#define MICROPY_PY_MACHINE_PWM (0) +#define MICROPY_PY_MACHINE_PWM (1) #define MICROPY_PY_MACHINE_SPI (1) #define MICROPY_PY_DISPLAY (1) -#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) +#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) #define MICROPY_HW_HAS_SWITCH (0) From 1d2bf263733d175393f0a6b5fff5f3a6a2662f30 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 9 Jan 2017 19:45:37 +0100 Subject: [PATCH 158/809] nrf5/drivers: Adding epaper display example script in comment for pca10056 / nrf52840 in the display module. --- nrf5/drivers/display/epaper_sld00200p_obj.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/nrf5/drivers/display/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper_sld00200p_obj.c index ebd59a89b2..164a70b009 100644 --- a/nrf5/drivers/display/epaper_sld00200p_obj.c +++ b/nrf5/drivers/display/epaper_sld00200p_obj.c @@ -138,6 +138,23 @@ pwm = PWM(0, Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP), freq=PWM.FREQ_250KHZ, d d = SLD00200P(264, 176, spi, pwm, cs, panel_on, border, busy, reset, discharge) d.text("Hello World!", 32, 32) d.show() + +Example for nrf52840 / pca10056: + +from machine import Pin, SPI, PWM +from display import SLD00200P +reset = Pin("B7", mode=Pin.OUT, pull=Pin.PULL_UP) +panel_on = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) +discharge = Pin("B9", mode=Pin.OUT, pull=Pin.PULL_UP) +border = Pin("B4", mode=Pin.OUT, pull=Pin.PULL_UP) +busy = Pin("B8", mode=Pin.IN, pull=Pin.PULL_DISABLED) +cs = Pin("B12", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +pwm = PWM(0, Pin("B6", mode=Pin.OUT, pull=Pin.PULL_UP), freq=PWM.FREQ_250KHZ, duty=50, period=2) +d = SLD00200P(264, 176, spi, pwm, cs, panel_on, border, busy, reset, discharge) +d.text("Hello World!", 32, 32) +d.show() + */ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { From 073cfc0a2e29f2979de222aec14f334cb2bb7b92 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 10 Jan 2017 18:26:58 +0100 Subject: [PATCH 159/809] nrf5/drivers: Adding SSD1306 SPI display driver. Not complete, but can do fill screen operation atm. --- nrf5/Makefile | 2 + nrf5/drivers/display/moddisplay.c | 5 +- nrf5/drivers/display/oled_ssd1306_driver.c | 195 +++++++++++++ nrf5/drivers/display/oled_ssd1306_driver.h | 41 +++ nrf5/drivers/display/oled_ssd1306_obj.c | 323 +++++++++++++++++++++ nrf5/drivers/display/oled_ssd1306_obj.h | 35 +++ 6 files changed, 600 insertions(+), 1 deletion(-) create mode 100644 nrf5/drivers/display/oled_ssd1306_driver.c create mode 100644 nrf5/drivers/display/oled_ssd1306_driver.h create mode 100644 nrf5/drivers/display/oled_ssd1306_obj.c create mode 100644 nrf5/drivers/display/oled_ssd1306_obj.h diff --git a/nrf5/Makefile b/nrf5/Makefile index 934bd648c9..ea0a86354f 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -154,6 +154,8 @@ DRIVERS_SRC_C += $(addprefix drivers/,\ display/epaper_sld00200p_driver.c \ display/lcd_ili9341_obj.c \ display/lcd_ili9341_driver.c \ + display/oled_ssd1306_obj.c \ + display/oled_ssd1306_driver.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/drivers/display/moddisplay.c b/nrf5/drivers/display/moddisplay.c index ee9dcfec1c..8bd6035724 100644 --- a/nrf5/drivers/display/moddisplay.c +++ b/nrf5/drivers/display/moddisplay.c @@ -30,6 +30,7 @@ #include "epaper_sld00200p_obj.h" #include "lcd_ili9341_obj.h" +#include "oled_ssd1306_obj.h" STATIC const mp_map_elem_t mp_module_display_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_display) }, @@ -39,11 +40,13 @@ STATIC const mp_map_elem_t mp_module_display_globals_table[] = { #if MICROPY_PY_DISPLAY_LCD_ILI9341 { MP_OBJ_NEW_QSTR(MP_QSTR_ILI9341), (mp_obj_t)&lcd_ili9341_type }, #endif +#if MICROPY_PY_DISPLAY_OLED_SSD1306 + { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1306), (mp_obj_t)&oled_ssd1306_type }, +#endif #if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1289), (mp_obj_t)&lcd_ssd1289_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_LS027b7DH01), (mp_obj_t)&lcd_ls027b7dh01_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1305), (mp_obj_t)&oled_ssd1305_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1306), (mp_obj_t)&oled_ssd1306_type }, #endif }; diff --git a/nrf5/drivers/display/oled_ssd1306_driver.c b/nrf5/drivers/display/oled_ssd1306_driver.c new file mode 100644 index 0000000000..07b3224515 --- /dev/null +++ b/nrf5/drivers/display/oled_ssd1306_driver.c @@ -0,0 +1,195 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "py/mphal.h" + +#include "oled_ssd1306_driver.h" +#include "hal_spi.h" +#include "hal_time.h" + +#if MICROPY_PY_DISPLAY_OLED_SSD1306 + +static pin_obj_t * mp_cs_pin; +static pin_obj_t * mp_dc_pin; +static pin_obj_t * mp_reset_pin; +static NRF_SPI_Type * mp_instance; + + +static void raw_write(uint8_t value) +{ + hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); + +} + +static void cmd_write(uint8_t value) +{ + mp_hal_pin_low(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); + + mp_hal_pin_high(mp_cs_pin); +} + +#define SET_CONTRAST (0x81) +#define SET_ENTIRE_ON (0xa4) +#define SET_NORM_INV (0xa6) +#define SET_DISP (0xae) +#define SET_MEM_ADDR (0x20) +#define SET_COL_ADDR (0x21) +#define SET_PAGE_ADDR (0x22) +#define SET_DISP_START_LINE (0x40) +#define SET_SEG_REMAP (0xa0) +#define SET_MUX_RATIO (0xa8) +#define SET_COM_OUT_DIR (0xc0) +#define SET_DISP_OFFSET (0xd3) +#define SET_COM_PIN_CFG (0xda) +#define SET_DISP_CLK_DIV (0xd5) +#define SET_PRECHARGE (0xd9) +#define SET_VCOM_DESEL (0xdb) +#define SET_CHARGE_PUMP (0x8d) + +void driver_ssd1306_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_obj_t * p_dc_pin, pin_obj_t * p_reset_pin) +{ + mp_instance = p_instance; + mp_cs_pin = p_cs_pin; + mp_dc_pin = p_dc_pin; + mp_reset_pin = p_reset_pin; + + mp_hal_pin_high(mp_cs_pin); + mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_high(mp_reset_pin); + + // power on display + mp_hal_pin_high(mp_reset_pin); + mp_hal_delay_ms(1); + mp_hal_pin_low(mp_reset_pin); + mp_hal_delay_ms(10); + mp_hal_pin_high(mp_reset_pin); + + // Turn off + cmd_write(SET_DISP | 0x00); // off + + // address setting + cmd_write(SET_MEM_ADDR); + cmd_write(0x00); // horizontal + + // resolution and layout + cmd_write(SET_DISP_START_LINE | 0x00); + cmd_write(SET_SEG_REMAP | 0x01); // column addr 127 mapped to SEG0 + cmd_write(SET_MUX_RATIO); + + uint16_t height = 64; // TODO: configurable + cmd_write(height - 1); // height - 1 + cmd_write(SET_COM_OUT_DIR | 0x08); // scan from COM[N] to COM0 + cmd_write(SET_DISP_OFFSET); + cmd_write(0x00); + cmd_write(SET_COM_PIN_CFG); + if (height == 32) { + cmd_write(0x02); + } else { + cmd_write(0x12); + } + // timing and driving scheme + cmd_write(SET_DISP_CLK_DIV); + cmd_write(0x80); + cmd_write(SET_PRECHARGE); + bool external_vcc = false; + if (external_vcc == true) { + cmd_write(0x22); + } else { + cmd_write(0xf1); + } + cmd_write(SET_VCOM_DESEL); + cmd_write(0x30); // 0.83*Vcc + // display + cmd_write(SET_CONTRAST); + cmd_write(0xff); // maximum + cmd_write(SET_ENTIRE_ON); // output follows RAM contents + cmd_write(SET_NORM_INV); // not inverted + // charge pump + cmd_write(SET_CHARGE_PUMP); + if (external_vcc == true) { + cmd_write(0x10); + } else { + cmd_write(0x14); + } + // on + cmd_write(SET_DISP | 0x01); + +} + +static void set_col(uint16_t start_col, uint16_t end_col) +{ + cmd_write(SET_COL_ADDR); /* Column Command address */ + cmd_write(start_col & 0xFF ); + cmd_write(end_col & 0xFF); +} + +static void set_page(uint16_t start_page, uint16_t end_page) +{ + cmd_write(SET_PAGE_ADDR); /* Column Command address */ + cmd_write(start_page & 0xFF); + cmd_write(end_page & 0xFF); +} + +void driver_ssd1306_clear(uint16_t color) +{ + uint16_t width = 128; + uint16_t height = 64; + + uint16_t x0 = 0; + uint16_t x1 = width - 1; + uint16_t y0 = 0; + uint16_t y1 = height -1; + + if (width == 64) { + // displays with width of 64 pixels are shifted by 32 + x0 += 32; + x1 += 32; + } + + uint16_t num_of_pages = height / 8; + set_col(x0, x1); + set_page(y0, y1); + + mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + for (uint16_t i = 0; i < (width * num_of_pages); i++) { + raw_write(color); + } + + mp_hal_pin_high(mp_cs_pin); +} + +void driver_ssd1306_update_line(uint16_t line, fb_byte_t * p_bytes, uint16_t len, bool compressed) { + +} + +#endif diff --git a/nrf5/drivers/display/oled_ssd1306_driver.h b/nrf5/drivers/display/oled_ssd1306_driver.h new file mode 100644 index 0000000000..0312f87914 --- /dev/null +++ b/nrf5/drivers/display/oled_ssd1306_driver.h @@ -0,0 +1,41 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OLED_SSD1306_DRIVER_H__ +#define OLED_SSD1306_DRIVER_H__ + +#include "py/mphal.h" + +#include "hal_spi.h" +#include "lcd_mono_fb.h" + +void driver_ssd1306_init(NRF_SPI_Type * p_instance, pin_obj_t * cs_pin, pin_obj_t * dc_pin, pin_obj_t * reset_pin); + +void driver_ssd1306_clear(uint16_t color); + +void driver_ssd1306_update_line(uint16_t line, fb_byte_t * p_bytes, uint16_t len, bool compressed); + +#endif // OLED_SSD1306_DRIVER_H__ diff --git a/nrf5/drivers/display/oled_ssd1306_obj.c b/nrf5/drivers/display/oled_ssd1306_obj.c new file mode 100644 index 0000000000..1c6fc1597c --- /dev/null +++ b/nrf5/drivers/display/oled_ssd1306_obj.c @@ -0,0 +1,323 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "py/obj.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "genhdr/pins.h" + +#include "oled_ssd1306_driver.h" + +#if MICROPY_PY_DISPLAY_OLED_SSD1306 + +/// \moduleref display +/// \class SSD1306 - SSD1306 TFT LCD display driver. + +#include "pin.h" +#include "spi.h" +#include "lcd_mono_fb.h" + +typedef struct _oled_ssd1306_obj_t { + mp_obj_base_t base; + machine_hard_spi_obj_t *spi; + pin_obj_t * pin_cs; + pin_obj_t * pin_dc; + pin_obj_t * pin_reset; + mp_obj_framebuf_t * framebuffer; +} oled_ssd1306_obj_t; + +static void dirty_line_update_cb(mp_obj_framebuf_t * p_framebuffer, + uint16_t line, + fb_byte_t * p_new, + fb_byte_t * p_old) { + // the lcd does not have double buffer needs, skip it. + (void)p_old; + + driver_ssd1306_update_line(line, p_new, p_framebuffer->bytes_stride, true); +} + +/// \method __str__() +/// Return a string describing the SSD1306 object. +STATIC void oled_ssd1306_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + oled_ssd1306_obj_t *self = o; + + mp_printf(print, "SSD1306(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", + self->spi->pyb->spi->init.mosi_pin_port, + self->spi->pyb->spi->init.mosi_pin, + self->spi->pyb->spi->init.miso_pin_port, + self->spi->pyb->spi->init.miso_pin, + self->spi->pyb->spi->init.clk_pin_port, + self->spi->pyb->spi->init.clk_pin + ); + + mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u), reset=(port=%u, pin=%u),\n", + self->pin_cs->port, + self->pin_cs->pin, + self->pin_dc->port, + self->pin_dc->pin, + self->pin_reset->port, + self->pin_reset->pin); + + mp_printf(print, " FB(width=%u, height=%u, dir=%u))\n", + self->framebuffer->width, + self->framebuffer->height); +} + +// for make_new +enum { + ARG_NEW_WIDTH, + ARG_NEW_HEIGHT, + ARG_NEW_SPI, + ARG_NEW_CS, + ARG_NEW_DC, + ARG_NEW_RESET +}; + +/* + +Example for nrf52832 / pca10040: + +from machine import Pin, SPI +from display import SSD1306 +cs = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) +dc = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=4000000) +d = SSD1306(128, 64, spi, cs, dc, reset) +d.text("Hello World!", 32, 32) +d.show() + +Example for nrf52840 / pca10056: + +from machine import Pin, SPI +from display import SSD1306 +cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) +dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +d = SSD1306(128, 64, spi, cs, dc, reset) +d.text("Hello World!", 32, 32) +d.show() + +*/ +STATIC mp_obj_t oled_ssd1306_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_DC, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + oled_ssd1306_obj_t *s = m_new_obj_with_finaliser(oled_ssd1306_obj_t); + s->base.type = type; + + mp_int_t width; + mp_int_t height; + + if (args[ARG_NEW_WIDTH].u_int > 0) { + width = args[ARG_NEW_WIDTH].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display width not set")); + } + + if (args[ARG_NEW_HEIGHT].u_int > 0) { + height = args[ARG_NEW_HEIGHT].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display height not set")); + } + + if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { + s->spi = args[ARG_NEW_SPI].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display SPI not set")); + } + + if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { + s->pin_cs = args[ARG_NEW_CS].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display CS Pin not set")); + } + + if (args[ARG_NEW_DC].u_obj != MP_OBJ_NULL) { + s->pin_dc = args[ARG_NEW_DC].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display DC Pin not set")); + } + + if (args[ARG_NEW_RESET].u_obj != MP_OBJ_NULL) { + s->pin_reset = args[ARG_NEW_RESET].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Reset Pin not set")); + } + + // direction arg not yet configurable + mp_int_t vertical = true; + s->framebuffer = lcd_mono_fb_helper_make_new(width, height, vertical); + + driver_ssd1306_init(s->spi->pyb->spi->instance, s->pin_cs, s->pin_dc, s->pin_reset); + // Default to black background + driver_ssd1306_clear(0); + + // display_clear_screen(s->framebuffer, 0x0); + + return MP_OBJ_FROM_PTR(s); +} + +// text + +/// \method fill(color) +/// Fill framebuffer with the color defined as argument. +STATIC mp_obj_t oled_ssd1306_fill(mp_obj_t self_in, mp_obj_t color) { + oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(self_in); + + driver_ssd1306_clear((uint8_t)mp_obj_get_int(color)); + + display_clear_screen(self->framebuffer, (uint8_t)mp_obj_get_int(color)); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(oled_ssd1306_fill_obj, oled_ssd1306_fill); + +/// \method show() +/// Display content in framebuffer. +STATIC mp_obj_t oled_ssd1306_show(size_t n_args, const mp_obj_t *args) { + oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(args[0]); + + display_update(self->framebuffer, false, dirty_line_update_cb); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1306_show_obj, 1, 2, oled_ssd1306_show); + +/// \method refresh([num_of_refresh]) +/// Refresh content in framebuffer. +/// +/// - With no argument, 1 refresh will be done. +/// - With `num_of_refresh` given, The whole framebuffer will be considered +/// dirty and will be refreshed the given number of times. +STATIC mp_obj_t oled_ssd1306_refresh(mp_obj_t self_in) { + oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(oled_ssd1306_refresh_obj, oled_ssd1306_refresh); + +/// \method pixel(x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color of the pixel in framebuffer will be returend. +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t oled_ssd1306_pixel(size_t n_args, const mp_obj_t *args) { + oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t x = mp_obj_get_int(args[1]); + mp_int_t y = mp_obj_get_int(args[2]); + mp_int_t color; + if (n_args >= 3) { + color = mp_obj_get_int(args[3]); + } + (void)self; + (void)x; + (void)y; + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1306_pixel_obj, 3, 4, oled_ssd1306_pixel); + +/// \method pixel(text, x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color will be the opposite of background (fill color). +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t oled_ssd1306_text(size_t n_args, const mp_obj_t *args) { + oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(args[0]); + const char *str = mp_obj_str_get_str(args[1]); + mp_int_t x = mp_obj_get_int(args[2]); + mp_int_t y = mp_obj_get_int(args[3]); + mp_int_t color; + if (n_args >= 4) { + color = mp_obj_get_int(args[3]); + } + + display_print_string(self->framebuffer, x, y, str); + + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1306_text_obj, 4, 5, oled_ssd1306_text); + +STATIC mp_obj_t oled_ssd1306_del(mp_obj_t self_in) { + oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(oled_ssd1306_del_obj, oled_ssd1306_del); + +STATIC const mp_map_elem_t oled_ssd1306_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&oled_ssd1306_del_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&oled_ssd1306_fill_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&oled_ssd1306_show_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&oled_ssd1306_text_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&oled_ssd1306_pixel_obj) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&oled_ssd1306_bitmap_obj) }, +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_BLACK) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_WHITE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, +}; + +STATIC MP_DEFINE_CONST_DICT(oled_ssd1306_locals_dict, oled_ssd1306_locals_dict_table); + +const mp_obj_type_t oled_ssd1306_type = { + { &mp_type_type }, + .name = MP_QSTR_SSD1306, + .print = oled_ssd1306_print, + .make_new = oled_ssd1306_make_new, + .locals_dict = (mp_obj_t)&oled_ssd1306_locals_dict +}; + +#endif // MICROPY_PY_DISPLAY_OLED_SSD1306 diff --git a/nrf5/drivers/display/oled_ssd1306_obj.h b/nrf5/drivers/display/oled_ssd1306_obj.h new file mode 100644 index 0000000000..37a00b1a88 --- /dev/null +++ b/nrf5/drivers/display/oled_ssd1306_obj.h @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OLED_SSD1306_H__ +#define OLED_SSD1306_H__ + +#include + +extern const mp_obj_type_t oled_ssd1306_type; + +#endif // OLED_SSD1306_H__ + From 28e1e506f6e3b07196bda4762fe880281239c289 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 10 Jan 2017 18:28:11 +0100 Subject: [PATCH 160/809] nrf5/boards: Enable SSD1306 spi driver for pca10040 (nrf52832) and pca10056 (nrf52840) boards. --- nrf5/boards/pca10040/mpconfigboard.h | 1 + nrf5/boards/pca10056/mpconfigboard.h | 1 + 2 files changed, 2 insertions(+) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 16a821459f..52d67cb44f 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -38,6 +38,7 @@ #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index 7142d23a5f..810618b276 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -36,6 +36,7 @@ #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) From ea7416216cbeb0c75d99833db27b9f282d8a7184 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 10 Jan 2017 18:31:44 +0100 Subject: [PATCH 161/809] nrf5/drivers: Correcting tabbing in oled ssd1306 c-module. --- nrf5/drivers/display/oled_ssd1306_obj.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/display/oled_ssd1306_obj.c b/nrf5/drivers/display/oled_ssd1306_obj.c index 1c6fc1597c..655189cb74 100644 --- a/nrf5/drivers/display/oled_ssd1306_obj.c +++ b/nrf5/drivers/display/oled_ssd1306_obj.c @@ -95,7 +95,7 @@ enum { ARG_NEW_SPI, ARG_NEW_CS, ARG_NEW_DC, - ARG_NEW_RESET + ARG_NEW_RESET }; /* @@ -132,7 +132,7 @@ STATIC mp_obj_t oled_ssd1306_make_new(const mp_obj_type_t *type, size_t n_args, { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { ARG_NEW_DC, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, }; // parse args From 16dbbdfe9cfab26a1bec88e23a8f97c75a0cbc6b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 16:43:31 +0100 Subject: [PATCH 162/809] nrf5/hal: Adding template files for ADC hal. --- nrf5/hal/hal_adc.c | 35 +++++++++++++++++++++++++ nrf5/hal/hal_adc.h | 63 +++++++++++++++++++++++++++++++++++++++++++++ nrf5/hal/hal_adce.c | 35 +++++++++++++++++++++++++ 3 files changed, 133 insertions(+) create mode 100644 nrf5/hal/hal_adc.c create mode 100644 nrf5/hal/hal_adc.h create mode 100644 nrf5/hal/hal_adce.c diff --git a/nrf5/hal/hal_adc.c b/nrf5/hal/hal_adc.c new file mode 100644 index 0000000000..635d2119b9 --- /dev/null +++ b/nrf5/hal/hal_adc.c @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "hal_adc.h" + +#ifdef HAL_ADC_MODULE_ENABLED && NRF51 + +void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init) { +} + +#endif // HAL_ADC_MODULE_ENABLED diff --git a/nrf5/hal/hal_adc.h b/nrf5/hal/hal_adc.h new file mode 100644 index 0000000000..ee7fefe9b5 --- /dev/null +++ b/nrf5/hal/hal_adc.h @@ -0,0 +1,63 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_ADC_H__ +#define HAL_ADC_H__ + +#include "nrf.h" + +#if NRF51 + +#define ADC_IRQ_NUM ADC_IRQn +#define ADC_BASE(x) ((NRF_ADC_Type *)NRF_ADC_BASE) +#define HAL_ADC_Type NRF_ADC_Type + +#else + +#define ADC_IRQ_NUM SAADC_IRQn +#define ADC_BASE(x) ((NRF_SAADC_Type *)NRF_SAADC_BASE) +#define HAL_ADC_Type NRF_ADC_Type + +#endif + +/** + * @brief ADC Configuration Structure definition + */ +typedef struct { +} hal_adc_init_t; + +/** + * @brief ADC handle Structure definition + */ +typedef struct __ADC_HandleTypeDef +{ + void *instance; /* ADC register base address */ + hal_adc_init_t init; /* ADC initialization parameters */ +} ADC_HandleTypeDef; + +void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init); + +#endif // HAL_ADC_H__ diff --git a/nrf5/hal/hal_adce.c b/nrf5/hal/hal_adce.c new file mode 100644 index 0000000000..f769fcd898 --- /dev/null +++ b/nrf5/hal/hal_adce.c @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "hal_adc.h" + +#ifdef HAL_ADCE_MODULE_ENABLED && NRF52 + +void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init) { +} + +#endif // HAL_ADCE_MODULE_ENABLED From 72b7e596ee0c9ea580e8ca06d156448927bfa599 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 16:46:43 +0100 Subject: [PATCH 163/809] nrf5/hal: Adding template files for TWI (i2c) hal. --- nrf5/hal/hal_twi.c | 36 +++++++++++++++++++ nrf5/hal/hal_twi.h | 86 +++++++++++++++++++++++++++++++++++++++++++++ nrf5/hal/hal_twie.c | 40 +++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 nrf5/hal/hal_twi.c create mode 100644 nrf5/hal/hal_twi.h create mode 100644 nrf5/hal/hal_twie.c diff --git a/nrf5/hal/hal_twi.c b/nrf5/hal/hal_twi.c new file mode 100644 index 0000000000..d9b7935179 --- /dev/null +++ b/nrf5/hal/hal_twi.c @@ -0,0 +1,36 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "hal_twi.h" + +#ifdef HAL_TWI_MODULE_ENABLED + +void hal_twi_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { +} + +#endif // HAL_TWI_MODULE_ENABLED + diff --git a/nrf5/hal/hal_twi.h b/nrf5/hal/hal_twi.h new file mode 100644 index 0000000000..7151db87d8 --- /dev/null +++ b/nrf5/hal/hal_twi.h @@ -0,0 +1,86 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_TWI_H__ +#define HAL_TWI_H__ + +#include "nrf.h" + +#define TWI_BASE_POINTERS (const uint32_t[]){NRF_TWI0_BASE, NRF_TWI1_BASE} +#define TWI_BASE(x) ((NRF_TWI_Type *)TWI_BASE_POINTERS[x]) + +#if NRF51 + +#define TWI_IRQ_VALUES (const uint32_t[]){SPI0_TWI0_IRQn, SPI1_TWI1_IRQn} + +#elif NRF52 + +#define TWI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn} + +#endif + +#if NRF52 + +/** + * @brief TWIM Configuration Structure definition + */ +typedef struct { +} hal_twim_init_t; + +/** + * @brief TWIS Configuration Structure definition + */ +typedef struct { +} hal_twis_init_t; + +#endif + +/** + * @brief TWI Configuration Structure definition + */ +typedef struct { +} hal_twi_init_t; + +typedef enum { + HAL_TWI_MASTER, + HAL_TWI_SLAVE +} hal_twi_mode_t; + +/** + * @brief TWI handle Structure definition + */ +typedef struct __TWI_HandleTypeDef +{ + NRF_TWI_Type *instance; /* TWI register base address */ + hal_twi_init_t init; /* TWI initialization parameters */ + uint8_t id; /* TWI instance id */ + hal_twi_mode_t mode; /* TWI master/slave */ +} TWI_HandleTypeDef; + +void hal_twi_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init); + +#endif // HAL_TWI_H__ diff --git a/nrf5/hal/hal_twie.c b/nrf5/hal/hal_twie.c new file mode 100644 index 0000000000..67897b520d --- /dev/null +++ b/nrf5/hal/hal_twie.c @@ -0,0 +1,40 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "hal_twi.h" + +#ifdef HAL_TWIM_MODULE_ENABLED + +// EasyDMA variants +#define TWI_MASTER_BASE(x) ((NRF_TWIM_Type *)TWI_BASE_POINTERS[x]) +#define TWI_SLAVE_BASE(x) ((NRF_TWIS_Type *)TWI_BASE_POINTERS[x]) + +void hal_twi_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { +} + +#endif // HAL_TWIM_MODULE_ENABLED + From d7eec2032e5cdfe67cb6b0e09b414aa0c7a06bc1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 16:49:55 +0100 Subject: [PATCH 164/809] nrf5/i2c: Adding files for hardware i2c machine module and adding config param in mpconfigport to disable by default. --- nrf5/i2c.c | 138 ++++++++++++++++++++++++++++++++++++++++++++ nrf5/i2c.h | 36 ++++++++++++ nrf5/mpconfigport.h | 3 + 3 files changed, 177 insertions(+) create mode 100644 nrf5/i2c.c create mode 100644 nrf5/i2c.h diff --git a/nrf5/i2c.c b/nrf5/i2c.c new file mode 100644 index 0000000000..54d42e5fc3 --- /dev/null +++ b/nrf5/i2c.c @@ -0,0 +1,138 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "i2c.h" +#include "hal_twi.h" + +#if MICROPY_PY_MACHINE_HW_I2C + +typedef struct _machine_i2c_obj_t { + mp_obj_base_t base; + TWI_HandleTypeDef *i2c; +} machine_i2c_obj_t; + +TWI_HandleTypeDef I2CHandle0 = {.instance = NULL, .id = 0}; +TWI_HandleTypeDef I2CHandle1 = {.instance = NULL, .id = 1}; + +STATIC const machine_i2c_obj_t machine_i2c_obj[] = { + {{&machine_i2c_type}, &I2CHandle0}, + {{&machine_i2c_type}, &I2CHandle1}, +}; + +void i2c_init0(void) { + // reset the I2C handles + memset(&I2CHandle0, 0, sizeof(TWI_HandleTypeDef)); + I2CHandle0.instance = TWI_BASE(0); + memset(&I2CHandle1, 0, sizeof(TWI_HandleTypeDef)); + I2CHandle0.instance = TWI_BASE(1); +} + +STATIC int i2c_find(mp_obj_t id) { + // given an integer id + int i2c_id = mp_obj_get_int(id); + if (i2c_id >= 0 && i2c_id <= MP_ARRAY_SIZE(machine_i2c_obj) + && machine_i2c_obj[i2c_id].i2c != NULL) { + return i2c_id; + } + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "I2C(%d) does not exist", i2c_id)); +} + +STATIC void i2c_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + machine_i2c_obj_t *self = o; + mp_printf(print, "I2C(%u)", self->i2c->id); +} + +/******************************************************************************/ +/* MicroPython bindings for machine API */ + +// for make_new +enum { + ARG_NEW_id, +}; + +STATIC mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { + // index -1 does not exist + return mp_const_none; + // TODO: raise exception + } + + // get static peripheral object + int i2c_id = i2c_find(args[ARG_NEW_id].u_obj); + const machine_i2c_obj_t *self = &machine_i2c_obj[i2c_id]; + + hal_twi_init(self->i2c->instance, &self->i2c->init); + + return MP_OBJ_FROM_PTR(self); +} + +STATIC const mp_map_elem_t pyb_i2c_locals_dict_table[] = { + // instance methods +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&machine_i2c_init_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_deinit), (mp_obj_t)&machine_i2c_deinit_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_is_ready), (mp_obj_t)&machine_i2c_is_ready_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_scan), (mp_obj_t)&machine_i2c_scan_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_send), (mp_obj_t)&machine_i2c_send_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_recv), (mp_obj_t)&machine_i2c_recv_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_mem_read), (mp_obj_t)&machine_i2c_mem_read_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_mem_write), (mp_obj_t)&machine_i2c_mem_write_obj }, +#endif + // class constants + /// \constant MASTER - for initialising the bus to master mode + /// \constant SLAVE - for initialising the bus to slave mode + { MP_OBJ_NEW_QSTR(MP_QSTR_MASTER), MP_OBJ_NEW_SMALL_INT(HAL_TWI_MASTER) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SLAVE), MP_OBJ_NEW_SMALL_INT(HAL_TWI_SLAVE) }, +}; + +STATIC MP_DEFINE_CONST_DICT(pyb_i2c_locals_dict, pyb_i2c_locals_dict_table); + +const mp_obj_type_t machine_i2c_type = { + { &mp_type_type }, + .name = MP_QSTR_I2C, + .print = i2c_print, + .make_new = machine_i2c_make_new, +#if 0 + .locals_dict = (mp_obj_t)&machine_i2c_locals_dict +#endif +}; + +#endif // MICROPY_PY_MACHINE_HW_I2C diff --git a/nrf5/i2c.h b/nrf5/i2c.h new file mode 100644 index 0000000000..46a93a8a63 --- /dev/null +++ b/nrf5/i2c.h @@ -0,0 +1,36 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef I2C_H__ +#define I2C_H__ + +#include "hal_twi.h" + +extern const mp_obj_type_t machine_i2c_type; + +void i2c_init0(void); + +#endif // I2C_H__ diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index d37ed6b0be..a6f55d9086 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -104,6 +104,9 @@ #define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) #define MICROPY_PY_FRAMEBUF (0) +#ifndef MICROPY_PY_MACHINE_HW_I2C +#define MICROPY_PY_MACHINE_HW_I2C (0) +#endif #ifndef MICROPY_PY_MACHINE_SPI #define MICROPY_PY_MACHINE_SPI (1) From 8ca63e71967b759a699edbf807dc4fd184831c5d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 16:52:45 +0100 Subject: [PATCH 165/809] nrf5/boards: Enable TWI hal for pca10028 (nrf51), pca10040 (nrf52832) and pca10056 (nrf52840) boards. --- nrf5/boards/pca10028/nrf51_hal_conf.h | 1 + nrf5/boards/pca10040/nrf52_hal_conf.h | 6 ++++-- nrf5/boards/pca10056/nrf52_hal_conf.h | 8 ++++++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/nrf5/boards/pca10028/nrf51_hal_conf.h b/nrf5/boards/pca10028/nrf51_hal_conf.h index 4bd11e1dd5..160574ba3c 100644 --- a/nrf5/boards/pca10028/nrf51_hal_conf.h +++ b/nrf5/boards/pca10028/nrf51_hal_conf.h @@ -6,5 +6,6 @@ #define HAL_TIME_MODULE_ENABLED #define HAL_RTC_MODULE_ENABLED #define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10040/nrf52_hal_conf.h b/nrf5/boards/pca10040/nrf52_hal_conf.h index f19e49744b..b375d9aac7 100644 --- a/nrf5/boards/pca10040/nrf52_hal_conf.h +++ b/nrf5/boards/pca10040/nrf52_hal_conf.h @@ -2,12 +2,14 @@ #define NRF52_HAL_CONF_H__ #define HAL_UART_MODULE_ENABLED -// #define HAL_UARTE_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED -// #define HAL_SPIE_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED #define HAL_PWM_MODULE_ENABLED #define HAL_RTC_MODULE_ENABLED #define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED +// #define HAL_UARTE_MODULE_ENABLED +// #define HAL_SPIE_MODULE_ENABLED +// #define HAL_TWIE_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ diff --git a/nrf5/boards/pca10056/nrf52_hal_conf.h b/nrf5/boards/pca10056/nrf52_hal_conf.h index 1ea1005c3c..b375d9aac7 100644 --- a/nrf5/boards/pca10056/nrf52_hal_conf.h +++ b/nrf5/boards/pca10056/nrf52_hal_conf.h @@ -2,10 +2,14 @@ #define NRF52_HAL_CONF_H__ #define HAL_UART_MODULE_ENABLED -// #define HAL_UARTE_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED -// #define HAL_SPIE_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED #define HAL_PWM_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED +// #define HAL_UARTE_MODULE_ENABLED +// #define HAL_SPIE_MODULE_ENABLED +// #define HAL_TWIE_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ From 383db817f9847252afeed9fb27dbe26a4ad85acb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 16:54:00 +0100 Subject: [PATCH 166/809] nrf5/boards: Enable hardware I2C machine module for pca10028 (nrf51), pca10040 (nrf52832) and pca10056 (nrf52840) boards. --- nrf5/boards/pca10028/mpconfigboard.h | 1 + nrf5/boards/pca10040/mpconfigboard.h | 1 + nrf5/boards/pca10056/mpconfigboard.h | 1 + 3 files changed, 3 insertions(+) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index b1faec748e..1c3f5bf02a 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -33,6 +33,7 @@ #define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_HW_I2C (1) #define MICROPY_PY_USOCKET (0) #define MICROPY_PY_NETWORK (0) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 52d67cb44f..b5a41264f8 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -34,6 +34,7 @@ #define MICROPY_PY_MACHINE_SPI (1) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_HW_I2C (1) #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index 810618b276..ed0070301a 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -32,6 +32,7 @@ #define MICROPY_PY_MACHINE_PWM (1) #define MICROPY_PY_MACHINE_SPI (1) +#define MICROPY_PY_MACHINE_HW_I2C (1) #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) From d1f5e0992bd934b6108ed013d2c169ef5ee1eeee Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 16:54:56 +0100 Subject: [PATCH 167/809] nrf5: Add i2c.c, i2c machine module, and hal_twi into build. --- nrf5/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index ea0a86354f..7f38dbed8a 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -116,6 +116,8 @@ SRC_HAL = $(addprefix hal/,\ hal_time.c \ hal_rtc.c \ hal_timer.c \ + hal_twi.c \ + hal_twie.c \ ) ifeq ($(MCU_VARIANT), nrf52) @@ -132,6 +134,7 @@ SRC_C += \ uart.c \ spi.c \ pwm.c \ + i2c.c \ help.c \ gccollect.c \ pin_named_pins.c \ From 3b0fe69366b47ba51368d5368036423388dc731c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 17:02:41 +0100 Subject: [PATCH 168/809] nrf5/hal: Removing chip variant guard for hal_adc*, and let this be up to the hal conf file to not mess up at the moment. --- nrf5/hal/hal_adc.c | 2 +- nrf5/hal/hal_adce.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/hal/hal_adc.c b/nrf5/hal/hal_adc.c index 635d2119b9..413a3f1bb3 100644 --- a/nrf5/hal/hal_adc.c +++ b/nrf5/hal/hal_adc.c @@ -27,7 +27,7 @@ #include "mphalport.h" #include "hal_adc.h" -#ifdef HAL_ADC_MODULE_ENABLED && NRF51 +#ifdef HAL_ADC_MODULE_ENABLED void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init) { } diff --git a/nrf5/hal/hal_adce.c b/nrf5/hal/hal_adce.c index f769fcd898..b78afddbe8 100644 --- a/nrf5/hal/hal_adce.c +++ b/nrf5/hal/hal_adce.c @@ -27,7 +27,7 @@ #include "mphalport.h" #include "hal_adc.h" -#ifdef HAL_ADCE_MODULE_ENABLED && NRF52 +#ifdef HAL_ADCE_MODULE_ENABLED void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init) { } From 7016ece34d81b53dc26e5920536e505756bdb65a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 17:04:08 +0100 Subject: [PATCH 169/809] nrf5/boards: Enable ADC/SAADC hal for pca10028 (nrf51), pca10040 (nrf52832) and pca10056 (nrf52840) boards. --- nrf5/boards/pca10028/nrf51_hal_conf.h | 1 + nrf5/boards/pca10040/nrf52_hal_conf.h | 2 ++ nrf5/boards/pca10056/nrf52_hal_conf.h | 2 ++ 3 files changed, 5 insertions(+) diff --git a/nrf5/boards/pca10028/nrf51_hal_conf.h b/nrf5/boards/pca10028/nrf51_hal_conf.h index 160574ba3c..1b87bf9942 100644 --- a/nrf5/boards/pca10028/nrf51_hal_conf.h +++ b/nrf5/boards/pca10028/nrf51_hal_conf.h @@ -7,5 +7,6 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10040/nrf52_hal_conf.h b/nrf5/boards/pca10040/nrf52_hal_conf.h index b375d9aac7..4d45893ee1 100644 --- a/nrf5/boards/pca10040/nrf52_hal_conf.h +++ b/nrf5/boards/pca10040/nrf52_hal_conf.h @@ -8,8 +8,10 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED +// #define HAL_ADCE_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ diff --git a/nrf5/boards/pca10056/nrf52_hal_conf.h b/nrf5/boards/pca10056/nrf52_hal_conf.h index b375d9aac7..4d45893ee1 100644 --- a/nrf5/boards/pca10056/nrf52_hal_conf.h +++ b/nrf5/boards/pca10056/nrf52_hal_conf.h @@ -8,8 +8,10 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED +// #define HAL_ADCE_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ From 002ece145e81734418951eec08610692004f4d4f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 17:04:53 +0100 Subject: [PATCH 170/809] nrf5: Adding hal_adc* into build. --- nrf5/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 7f38dbed8a..2f2bd8ef4c 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -118,6 +118,8 @@ SRC_HAL = $(addprefix hal/,\ hal_timer.c \ hal_twi.c \ hal_twie.c \ + hal_adc.c \ + hal_adce.c \ ) ifeq ($(MCU_VARIANT), nrf52) From 0edf96fba61c2458ff76aaf4dbbc74a21d2fe54c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 17:16:32 +0100 Subject: [PATCH 171/809] nrf5/adc: Adding ADC machine module base files. Implementation missing. --- nrf5/adc.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ nrf5/adc.h | 34 +++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 nrf5/adc.c create mode 100644 nrf5/adc.h diff --git a/nrf5/adc.c b/nrf5/adc.c new file mode 100644 index 0000000000..aa1f27be6e --- /dev/null +++ b/nrf5/adc.c @@ -0,0 +1,60 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "adc.h" +#include "hal_adc.h" + +#if MICROPY_PY_MACHINE_ADC + +typedef struct _machine_adc_obj_t { + mp_obj_base_t base; + ADC_HandleTypeDef *adc; +} machine_adc_obj_t; + +/******************************************************************************/ +/* MicroPython bindings for machine API */ + +STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + return MP_OBJ_FROM_PTR(self); +} + +const mp_obj_type_t machine_adc_type = { + { &mp_type_type }, + .name = MP_QSTR_ADC, +#if 0 + .print = adc_print, + .make_new = machine_adc_make_new, + .locals_dict = (mp_obj_t)&machine_adc_locals_dict +#endif +}; + +#endif // MICROPY_PY_MACHINE_ADC diff --git a/nrf5/adc.h b/nrf5/adc.h new file mode 100644 index 0000000000..a9f68e73da --- /dev/null +++ b/nrf5/adc.h @@ -0,0 +1,34 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef ADC_H__ +#define ADC_H__ + +#include "hal_adc.h" + +extern const mp_obj_type_t machine_adc_type; + +#endif // ADC_H__ From 6e6f13986861314e4d1a5ef5a32b4348c5aa1fed Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 17:18:54 +0100 Subject: [PATCH 172/809] nrf5: Adding new config for ADC module in mpconfigport.h. --- nrf5/mpconfigport.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index a6f55d9086..0b78313cf7 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -104,6 +104,10 @@ #define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) #define MICROPY_PY_FRAMEBUF (0) +#ifndef MICROPY_PY_MACHINE_ADC +#define MICROPY_PY_MACHINE_ADC (0) +#endif + #ifndef MICROPY_PY_MACHINE_HW_I2C #define MICROPY_PY_MACHINE_HW_I2C (0) #endif From e952ab16b353bc15f369734815f14a068f70224c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 17:20:18 +0100 Subject: [PATCH 173/809] nrf5: Add add ADC machine module into build. --- nrf5/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 2f2bd8ef4c..924a32b402 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -151,6 +151,7 @@ SRC_C += \ modnetwork.c \ timer.c \ rtc.c \ + adc.c \ lcd_mono_fb.c \ DRIVERS_SRC_C += $(addprefix drivers/,\ From a0b0e137859178052b4fbd77113a5d9f1e05fa38 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 17:28:38 +0100 Subject: [PATCH 174/809] nrf5/boards: Enable ADC machine module for pca10028, pca10040 and pca10056. --- nrf5/boards/pca10028/mpconfigboard.h | 1 + nrf5/boards/pca10040/mpconfigboard.h | 1 + nrf5/boards/pca10056/mpconfigboard.h | 1 + 3 files changed, 3 insertions(+) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 1c3f5bf02a..1e44ceef1a 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -34,6 +34,7 @@ #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_MACHINE_HW_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_USOCKET (0) #define MICROPY_PY_NETWORK (0) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index b5a41264f8..e5d0106087 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -35,6 +35,7 @@ #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_MACHINE_HW_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index ed0070301a..2e08970d9d 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -33,6 +33,7 @@ #define MICROPY_PY_MACHINE_PWM (1) #define MICROPY_PY_MACHINE_SPI (1) #define MICROPY_PY_MACHINE_HW_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) From 728f98dc07506210598fa4a0a3b5af16114a1617 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 17:29:15 +0100 Subject: [PATCH 175/809] nrf5/adc: Updating module to compile. --- nrf5/adc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/adc.c b/nrf5/adc.c index aa1f27be6e..79c8bc7104 100644 --- a/nrf5/adc.c +++ b/nrf5/adc.c @@ -44,15 +44,15 @@ typedef struct _machine_adc_obj_t { /* MicroPython bindings for machine API */ STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - return MP_OBJ_FROM_PTR(self); + return mp_const_none; } const mp_obj_type_t machine_adc_type = { { &mp_type_type }, .name = MP_QSTR_ADC, + .make_new = machine_adc_make_new, #if 0 .print = adc_print, - .make_new = machine_adc_make_new, .locals_dict = (mp_obj_t)&machine_adc_locals_dict #endif }; From bcf47b465efeb587fb33063df3e0935aab1163fb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 17:29:50 +0100 Subject: [PATCH 176/809] nrf5/hal: Updating hal_adc header to use correct Type for ADC on nrf52. --- nrf5/hal/hal_adc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/hal/hal_adc.h b/nrf5/hal/hal_adc.h index ee7fefe9b5..1dbea697b9 100644 --- a/nrf5/hal/hal_adc.h +++ b/nrf5/hal/hal_adc.h @@ -39,7 +39,7 @@ #define ADC_IRQ_NUM SAADC_IRQn #define ADC_BASE(x) ((NRF_SAADC_Type *)NRF_SAADC_BASE) -#define HAL_ADC_Type NRF_ADC_Type +#define HAL_ADC_Type NRF_SAADC_Type #endif From 5d5d06ff41e906f0ff017057f7fdcbf505026b55 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 20:12:32 +0100 Subject: [PATCH 177/809] nrf5/boards: Updating make-pins.py to generate ADC pin settings from board pins.csv. --- nrf5/boards/make-pins.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/nrf5/boards/make-pins.py b/nrf5/boards/make-pins.py index c9ff8ede12..f8756a5d92 100644 --- a/nrf5/boards/make-pins.py +++ b/nrf5/boards/make-pins.py @@ -115,8 +115,7 @@ class Pin(object): return (adc,channel) = adc_str.split('_') for idx in range(3, len(adc)): - adc_num = int(adc[idx]) # 1, 2, or 3 - self.adc_num |= (1 << (adc_num - 1)) + self.adc_num = int(adc[idx]) self.adc_channel = int(channel[2:]) def parse_af(self, af_idx, af_strs_in): @@ -204,7 +203,7 @@ class Pins(object): if pin.port == port_num and pin.pin == pin_num: return pin - def parse_af_file(self, filename, pinname_col, af_col): + def parse_af_file(self, filename, pinname_col, af_col, af_col_end): with open(filename, 'r') as csvfile: rows = csv.reader(csvfile) for row in rows: @@ -214,8 +213,10 @@ class Pins(object): continue pin = Pin(port_num, pin_num) for af_idx in range(af_col, len(row)): - if af_idx >= af_col: + if af_idx < af_col_end: pin.parse_af(af_idx - af_col, row[af_idx]) + elif af_idx == af_col_end: + pin.parse_adc(row[af_idx]) self.cpu_pins.append(NamedPin(pin.cpu_pin_name(), pin)) def parse_board_file(self, filename): @@ -376,7 +377,7 @@ def main(): print('//') if args.af_filename: print('// --af {:s}'.format(args.af_filename)) - pins.parse_af_file(args.af_filename, 1, 2) + pins.parse_af_file(args.af_filename, 1, 2, 2) if args.board_filename: print('// --board {:s}'.format(args.board_filename)) From affe0f8e9885747eb22b4f7cd081307de9506f35 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 20:13:59 +0100 Subject: [PATCH 178/809] nrf5: Updating nrf51_af.csv to reflect pins having ADC on the chip. --- nrf5/nrf51_af.csv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/nrf5/nrf51_af.csv b/nrf5/nrf51_af.csv index b54aaa1e31..2fc34a06a0 100644 --- a/nrf5/nrf51_af.csv +++ b/nrf5/nrf51_af.csv @@ -1,10 +1,10 @@ PA0,PA0 -PA1,PA1 -PA2,PA2 -PA3,PA3 -PA4,PA4 -PA5,PA5 -PA6,PA6 +PA1,PA1,ADC0_IN2 +PA2,PA2,ADC0_IN3 +PA3,PA3,ADC0_IN4 +PA4,PA4,ADC0_IN5 +PA5,PA5,ADC0_IN6 +PA6,PA6,ADC0_IN7 PA7,PA7 PA8,PA8 PA9,PA9 From 8349fd0bb9977e17014064b4c3a5aae22eb989e4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 20:14:53 +0100 Subject: [PATCH 179/809] nrf5/boards: Tuning linker script for nrf51822_ac to get some more heap. --- nrf5/boards/nrf51822_ac.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/nrf51822_ac.ld b/nrf5/boards/nrf51822_ac.ld index 51fd503b58..2c591cd2f2 100644 --- a/nrf5/boards/nrf51822_ac.ld +++ b/nrf5/boards/nrf51822_ac.ld @@ -14,7 +14,7 @@ MEMORY /* produce a link error if there is not this amount of RAM for these sections */ _minimum_stack_size = 2K; -_minimum_heap_size = 10K; +_minimum_heap_size = 20K; /* top end of the stack */ @@ -23,6 +23,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20001000; /* tunable */ +_heap_end = 0x20005000; /* tunable */ INCLUDE "boards/common.ld" From 3e112c40f380b45ab9580ca68745c8f1ab7140d2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 20:18:04 +0100 Subject: [PATCH 180/809] nrf5/boards: Adding ADC config to pca10028 pins.csv --- nrf5/boards/pca10028/pins.csv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/nrf5/boards/pca10028/pins.csv b/nrf5/boards/pca10028/pins.csv index 2b16969869..c239ba4903 100644 --- a/nrf5/boards/pca10028/pins.csv +++ b/nrf5/boards/pca10028/pins.csv @@ -1,10 +1,10 @@ PA0,PA0 -PA1,PA1 -PA2,PA2 -PA3,PA3 -PA4,PA4 -PA5,PA5 -PA6,PA6 +PA1,PA1,ADC0_IN2 +PA2,PA2,ADC0_IN3 +PA3,PA3,ADC0_IN4 +PA4,PA4,ADC0_IN5 +PA5,PA5,ADC0_IN6 +PA6,PA6,ADC0_IN7 PA7,PA7 UART_RTS,PA8 UART_TX,PA9 From 994341fc3b4dba61a6fef47d7ce05dae9ef9830d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 20:19:31 +0100 Subject: [PATCH 181/809] nrf5/boards: Enabling ADCE (SAADC) variant of adc hal to match hardware on nrf52 series. --- nrf5/boards/pca10040/nrf52_hal_conf.h | 3 +-- nrf5/boards/pca10056/nrf52_hal_conf.h | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/nrf5/boards/pca10040/nrf52_hal_conf.h b/nrf5/boards/pca10040/nrf52_hal_conf.h index 4d45893ee1..7ae58853c4 100644 --- a/nrf5/boards/pca10040/nrf52_hal_conf.h +++ b/nrf5/boards/pca10040/nrf52_hal_conf.h @@ -8,10 +8,9 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED +#define HAL_ADCE_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED -// #define HAL_ADCE_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ diff --git a/nrf5/boards/pca10056/nrf52_hal_conf.h b/nrf5/boards/pca10056/nrf52_hal_conf.h index 4d45893ee1..7ae58853c4 100644 --- a/nrf5/boards/pca10056/nrf52_hal_conf.h +++ b/nrf5/boards/pca10056/nrf52_hal_conf.h @@ -8,10 +8,9 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED +#define HAL_ADCE_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED -// #define HAL_ADCE_MODULE_ENABLED #endif // NRF52_HAL_CONF_H__ From 38bb518e1923f72f543da459d03954986579a5be Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 22:01:20 +0100 Subject: [PATCH 182/809] nrf5/adc: Adding updated adc module. --- nrf5/adc.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 81 insertions(+), 4 deletions(-) diff --git a/nrf5/adc.c b/nrf5/adc.c index 79c8bc7104..35fb9fa4bb 100644 --- a/nrf5/adc.c +++ b/nrf5/adc.c @@ -40,21 +40,98 @@ typedef struct _machine_adc_obj_t { ADC_HandleTypeDef *adc; } machine_adc_obj_t; +/// \method __str__() +/// Return a string describing the ADC object. +STATIC void machine_adc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + machine_adc_obj_t *self = o; + + (void)self; + + mp_printf(print, "ADC()"); +} + /******************************************************************************/ /* MicroPython bindings for machine API */ +// for make_new +enum { + ARG_NEW_PIN, +}; + STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { ARG_NEW_PIN, MP_ARG_REQUIRED | MP_ARG_INT }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + machine_adc_obj_t *s = m_new_obj(machine_adc_obj_t); + s->base.type = type; + + mp_int_t channel_num; + + if (args[ARG_NEW_PIN].u_int > 0) { + channel_num = args[ARG_NEW_PIN].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Channel number not set")); + } + + s->adc->init.channel = channel_num; + + hal_adc_init(ADC_BASE, &s->adc->init); + + return MP_OBJ_FROM_PTR(s); +} + +/// \method init() +mp_obj_t machine_adc_init(mp_obj_t self_in) { + hal_adc_start(ADC_BASE); return mp_const_none; } +STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_machine_adc_init_obj, machine_adc_init); + +/// \method deinit() +mp_obj_t machine_adc_deinit(mp_obj_t self_in) { + hal_adc_stop(ADC_BASE); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_machine_adc_deinit_obj, machine_adc_deinit); + +/// \method value() +/// Read adc level. +mp_obj_t machine_adc_value(mp_obj_t self_in) { + return MP_OBJ_NEW_SMALL_INT(hal_adc_value(ADC_BASE)); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_machine_adc_value_obj, machine_adc_value); + +/// \method battery_level() +/// Get battery level in percentage. +mp_obj_t machine_adc_battery_level(void) { + return MP_OBJ_NEW_SMALL_INT(hal_adc_battery_level(ADC_BASE)); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(mp_machine_adc_battery_level_obj, machine_adc_battery_level); + +STATIC const mp_map_elem_t machine_adc_locals_dict_table[] = { + // instance methods + { MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&mp_machine_adc_init_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_deinit), (mp_obj_t)&mp_machine_adc_deinit_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_value), (mp_obj_t)&mp_machine_adc_value_obj }, + + // class methods + { MP_OBJ_NEW_QSTR(MP_QSTR_battery_level), (mp_obj_t)&mp_machine_adc_battery_level_obj }, +}; + +STATIC MP_DEFINE_CONST_DICT(machine_adc_locals_dict, machine_adc_locals_dict_table); const mp_obj_type_t machine_adc_type = { { &mp_type_type }, .name = MP_QSTR_ADC, .make_new = machine_adc_make_new, -#if 0 - .print = adc_print, - .locals_dict = (mp_obj_t)&machine_adc_locals_dict -#endif + .locals_dict = (mp_obj_t)&machine_adc_locals_dict, + .print = machine_adc_print, }; #endif // MICROPY_PY_MACHINE_ADC From 4da435376d968df98d27d1cde1c953aab532d807 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 22:12:41 +0100 Subject: [PATCH 183/809] nrf5/hal: Updating hal_adc* with more api functions. --- nrf5/hal/hal_adc.c | 109 ++++++++++++++++++++++++++++++++++++++++++++ nrf5/hal/hal_adc.h | 24 +++++++++- nrf5/hal/hal_adce.c | 14 ++++++ 3 files changed, 145 insertions(+), 2 deletions(-) diff --git a/nrf5/hal/hal_adc.c b/nrf5/hal/hal_adc.c index 413a3f1bb3..fb46961404 100644 --- a/nrf5/hal/hal_adc.c +++ b/nrf5/hal/hal_adc.c @@ -24,12 +24,121 @@ * THE SOFTWARE. */ +#include #include "mphalport.h" #include "hal_adc.h" #ifdef HAL_ADC_MODULE_ENABLED +#define ADC_REF_VOLTAGE_IN_MILLIVOLTS (1200) // Reference voltage (in milli volts) used by ADC while doing conversion. +#define ADC_PRE_SCALING_COMPENSATION (3) // The ADC is configured to use VDD with 1/3 prescaling as input. And hence the result of conversion is to be multiplied by 3 to get the actual value of the battery voltage. +#define DIODE_FWD_VOLT_DROP_MILLIVOLTS (270) // Typical forward voltage drop of the diode (Part no: SD103ATW-7-F) that is connected in series with the voltage supply. This is the voltage drop when the forward current is 1mA. Source: Data sheet of 'SURFACE MOUNT SCHOTTKY BARRIER DIODE ARRAY' available at www.diodes.com. + +#define ADC_RESULT_IN_MILLI_VOLTS(ADC_VALUE)\ + ((((ADC_VALUE) * ADC_REF_VOLTAGE_IN_MILLIVOLTS) / 255) * ADC_PRE_SCALING_COMPENSATION) + +static const uint32_t hal_adc_input_lookup[] = { + ADC_CONFIG_PSEL_AnalogInput0 << ADC_CONFIG_PSEL_Pos, + ADC_CONFIG_PSEL_AnalogInput1 << ADC_CONFIG_PSEL_Pos, + ADC_CONFIG_PSEL_AnalogInput2 << ADC_CONFIG_PSEL_Pos, + ADC_CONFIG_PSEL_AnalogInput3 << ADC_CONFIG_PSEL_Pos, + ADC_CONFIG_PSEL_AnalogInput4 << ADC_CONFIG_PSEL_Pos, + ADC_CONFIG_PSEL_AnalogInput5 << ADC_CONFIG_PSEL_Pos, + ADC_CONFIG_PSEL_AnalogInput6 << ADC_CONFIG_PSEL_Pos, + ADC_CONFIG_PSEL_AnalogInput7 << ADC_CONFIG_PSEL_Pos +}; + + +static uint8_t battery_level_in_percent(const uint16_t mvolts) +{ + uint8_t battery_level; + + if (mvolts >= 3000) { + battery_level = 100; + } else if (mvolts > 2900) { + battery_level = 100 - ((3000 - mvolts) * 58) / 100; + } else if (mvolts > 2740) { + battery_level = 42 - ((2900 - mvolts) * 24) / 160; + } else if (mvolts > 2440) { + battery_level = 18 - ((2740 - mvolts) * 12) / 300; + } else if (mvolts > 2100) { + battery_level = 6 - ((2440 - mvolts) * 6) / 340; + } else { + battery_level = 0; + } + + return battery_level; +} + + void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init) { + + while (p_instance->ENABLE && p_instance->BUSY) + { + // spin loop if another user is in progress of sampling + } + + p_instance->INTENSET = ADC_INTENSET_END_Msk; + p_instance->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos) + | (ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling << ADC_CONFIG_INPSEL_Pos) + | (ADC_CONFIG_REFSEL_VBG << ADC_CONFIG_REFSEL_Pos) + | (hal_adc_input_lookup[p_adc_init->channel]) + | (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos); +} + +void hal_adc_start(HAL_ADC_Type * p_instance) { + p_instance->ENABLE = ADC_ENABLE_ENABLE_Enabled; +} + +void hal_adc_stop(HAL_ADC_Type * p_instance) { + p_instance->ENABLE = ADC_ENABLE_ENABLE_Disabled; +} + +uint8_t hal_adc_value(HAL_ADC_Type * p_instance) { + + p_instance->EVENTS_END = 0; + p_instance->TASKS_START = 1; + + while (!p_instance->EVENTS_END) { + ; + } + + uint8_t adc_result = p_instance->RESULT; + + p_instance->EVENTS_END = 0; + p_instance->TASKS_STOP = 1; + + return adc_result; +} + +uint8_t hal_adc_battery_level(HAL_ADC_Type * p_instance) { + p_instance->INTENSET = ADC_INTENSET_END_Msk; + p_instance->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos) + | (ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling << ADC_CONFIG_INPSEL_Pos) + | (ADC_CONFIG_REFSEL_VBG << ADC_CONFIG_REFSEL_Pos) + | (ADC_CONFIG_PSEL_Disabled << ADC_CONFIG_PSEL_Pos) + | (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos); + + p_instance->EVENTS_END = 0; + p_instance->ENABLE = ADC_ENABLE_ENABLE_Enabled; + + p_instance->EVENTS_END = 0; + p_instance->TASKS_START = 1; + + while (!p_instance->EVENTS_END) { + ; + } + + uint8_t adc_result; + uint16_t batt_lvl_in_milli_volts; + + p_instance->EVENTS_END = 0; + adc_result = p_instance->RESULT; + p_instance->TASKS_STOP = 1; + + batt_lvl_in_milli_volts = ADC_RESULT_IN_MILLI_VOLTS(adc_result) + DIODE_FWD_VOLT_DROP_MILLIVOLTS; + return battery_level_in_percent(batt_lvl_in_milli_volts); + } #endif // HAL_ADC_MODULE_ENABLED diff --git a/nrf5/hal/hal_adc.h b/nrf5/hal/hal_adc.h index 1dbea697b9..8fd19d14b7 100644 --- a/nrf5/hal/hal_adc.h +++ b/nrf5/hal/hal_adc.h @@ -27,26 +27,38 @@ #ifndef HAL_ADC_H__ #define HAL_ADC_H__ +#include + #include "nrf.h" #if NRF51 #define ADC_IRQ_NUM ADC_IRQn -#define ADC_BASE(x) ((NRF_ADC_Type *)NRF_ADC_BASE) +#define ADC_BASE ((NRF_ADC_Type *)NRF_ADC_BASE) #define HAL_ADC_Type NRF_ADC_Type #else #define ADC_IRQ_NUM SAADC_IRQn -#define ADC_BASE(x) ((NRF_SAADC_Type *)NRF_SAADC_BASE) +#define ADC_BASE ((NRF_SAADC_Type *)NRF_SAADC_BASE) #define HAL_ADC_Type NRF_SAADC_Type #endif +typedef enum { + HAL_ADC_CHANNEL_2 = 2, + HAL_ADC_CHANNEL_3, + HAL_ADC_CHANNEL_4, + HAL_ADC_CHANNEL_5, + HAL_ADC_CHANNEL_6, + HAL_ADC_CHANNEL_7, +} hal_adc_channel_t; + /** * @brief ADC Configuration Structure definition */ typedef struct { + hal_adc_channel_t channel; } hal_adc_init_t; /** @@ -60,4 +72,12 @@ typedef struct __ADC_HandleTypeDef void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init); +void hal_adc_start(HAL_ADC_Type * p_instance); + +void hal_adc_stop(HAL_ADC_Type * p_instance); + +uint8_t hal_adc_value(HAL_ADC_Type * p_instance); + +uint8_t hal_adc_battery_level(HAL_ADC_Type * p_instance); + #endif // HAL_ADC_H__ diff --git a/nrf5/hal/hal_adce.c b/nrf5/hal/hal_adce.c index b78afddbe8..21f1a7e8ee 100644 --- a/nrf5/hal/hal_adce.c +++ b/nrf5/hal/hal_adce.c @@ -32,4 +32,18 @@ void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init) { } +void hal_adc_start(HAL_ADC_Type * p_instance) { +} + +void hal_adc_stop(HAL_ADC_Type * p_instance) { +} + +uint8_t hal_adc_value(HAL_ADC_Type * p_instance) { + return 0; +} + +uint8_t hal_adc_battery_level(HAL_ADC_Type * p_instance) { + return 0; +} + #endif // HAL_ADCE_MODULE_ENABLED From 719bdcfed446ed9b0cfd6084ed96087f9aeb47d9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 11 Jan 2017 22:13:18 +0100 Subject: [PATCH 184/809] nrf5: Adding adc module to machine module. --- nrf5/modmachine.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/nrf5/modmachine.c b/nrf5/modmachine.c index 7f6a52fc20..1826135baa 100644 --- a/nrf5/modmachine.c +++ b/nrf5/modmachine.c @@ -42,6 +42,10 @@ #if MICROPY_PY_MACHINE_PWM #include "pwm.h" #endif +#if MICROPY_PY_MACHINE_ADC +#include "adc.h" +#endif + #define PYB_RESET_HARD (0) #define PYB_RESET_WDT (1) @@ -167,7 +171,9 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { #if MICROPY_PY_MACHINE_SPI { MP_OBJ_NEW_QSTR(MP_QSTR_SPI), (mp_obj_t)&machine_hard_spi_type }, #endif - +#if MICROPY_PY_MACHINE_ADC + { MP_OBJ_NEW_QSTR(MP_QSTR_ADC), (mp_obj_t)&machine_adc_type }, +#endif #if MICROPY_PY_MACHINE_PWM { MP_OBJ_NEW_QSTR(MP_QSTR_PWM), (mp_obj_t)&machine_hard_pwm_type }, #endif From 24abb69eec72ca685063c24ad709358efc1d0712 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 12 Jan 2017 08:47:16 +0100 Subject: [PATCH 185/809] nrf5/rtc: Correcting RTC1 base error in rtc template. --- nrf5/rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/rtc.c b/nrf5/rtc.c index 3aae1e36fe..9a4913d88d 100644 --- a/nrf5/rtc.c +++ b/nrf5/rtc.c @@ -53,7 +53,7 @@ void rtc_init0(void) { memset(&RTCHandle0, 0, sizeof(RTC_HandleTypeDef)); RTCHandle0.instance = RTC0; memset(&RTCHandle1, 0, sizeof(RTC_HandleTypeDef)); - RTCHandle0.instance = RTC1; + RTCHandle1.instance = RTC1; } STATIC int rtc_find(mp_obj_t id) { From 6c54ed9a095acfb1fa412bf57c713b7ad60f28ee Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 12 Jan 2017 17:20:08 +0100 Subject: [PATCH 186/809] nrf5/adc: Updating adc module and hal with a new interface. No need for keeping peripheral base address in structure when there is only one peripheral (nrf51). --- nrf5/adc.c | 75 +++++++++++++++++++++++---------------------- nrf5/hal/hal_adc.c | 67 ++++++++++++++++------------------------ nrf5/hal/hal_adc.h | 18 +++-------- nrf5/hal/hal_adce.c | 13 ++------ 4 files changed, 72 insertions(+), 101 deletions(-) diff --git a/nrf5/adc.c b/nrf5/adc.c index 35fb9fa4bb..6d407d2840 100644 --- a/nrf5/adc.c +++ b/nrf5/adc.c @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2016 Glenn Ruben Bakke + * Copyright (c) 2017 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -40,6 +40,37 @@ typedef struct _machine_adc_obj_t { ADC_HandleTypeDef *adc; } machine_adc_obj_t; +ADC_HandleTypeDef ADCHandle0 = {.config.channel = 2}; +ADC_HandleTypeDef ADCHandle1 = {.config.channel = 3}; +ADC_HandleTypeDef ADCHandle2 = {.config.channel = 4}; +ADC_HandleTypeDef ADCHandle3 = {.config.channel = 5}; +ADC_HandleTypeDef ADCHandle4 = {.config.channel = 6}; +ADC_HandleTypeDef ADCHandle5 = {.config.channel = 7}; + +STATIC const machine_adc_obj_t machine_adc_obj[] = { + {{&machine_adc_type}, &ADCHandle0}, + {{&machine_adc_type}, &ADCHandle1}, + {{&machine_adc_type}, &ADCHandle2}, + {{&machine_adc_type}, &ADCHandle3}, + {{&machine_adc_type}, &ADCHandle4}, + {{&machine_adc_type}, &ADCHandle5}, +}; + +STATIC int adc_find(mp_obj_t id) { + // given an integer id + int adc_id = mp_obj_get_int(id); + + int adc_idx = adc_id - 2; + + if (adc_idx >= 0 && adc_idx <= MP_ARRAY_SIZE(machine_adc_obj) + && machine_adc_obj[adc_idx].adc != NULL) { + return adc_idx; + } + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "ADC(%d) does not exist", adc_id)); +} + + /// \method __str__() /// Return a string describing the ADC object. STATIC void machine_adc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { @@ -60,64 +91,36 @@ enum { STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { - { ARG_NEW_PIN, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_PIN, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1) } }, }; // parse args mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - machine_adc_obj_t *s = m_new_obj(machine_adc_obj_t); - s->base.type = type; + int adc_id = adc_find(args[ARG_NEW_PIN].u_obj); + const machine_adc_obj_t *self = &machine_adc_obj[adc_id]; - mp_int_t channel_num; - - if (args[ARG_NEW_PIN].u_int > 0) { - channel_num = args[ARG_NEW_PIN].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Channel number not set")); - } - - s->adc->init.channel = channel_num; - - hal_adc_init(ADC_BASE, &s->adc->init); - - return MP_OBJ_FROM_PTR(s); + return MP_OBJ_FROM_PTR(self); } -/// \method init() -mp_obj_t machine_adc_init(mp_obj_t self_in) { - hal_adc_start(ADC_BASE); - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_machine_adc_init_obj, machine_adc_init); - -/// \method deinit() -mp_obj_t machine_adc_deinit(mp_obj_t self_in) { - hal_adc_stop(ADC_BASE); - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_machine_adc_deinit_obj, machine_adc_deinit); - /// \method value() /// Read adc level. mp_obj_t machine_adc_value(mp_obj_t self_in) { - return MP_OBJ_NEW_SMALL_INT(hal_adc_value(ADC_BASE)); + machine_adc_obj_t *self = self_in; + return MP_OBJ_NEW_SMALL_INT(hal_adc_channel_value(&self->adc->config)); } STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_machine_adc_value_obj, machine_adc_value); /// \method battery_level() /// Get battery level in percentage. mp_obj_t machine_adc_battery_level(void) { - return MP_OBJ_NEW_SMALL_INT(hal_adc_battery_level(ADC_BASE)); + return MP_OBJ_NEW_SMALL_INT(hal_adc_battery_level()); } STATIC MP_DEFINE_CONST_FUN_OBJ_0(mp_machine_adc_battery_level_obj, machine_adc_battery_level); STATIC const mp_map_elem_t machine_adc_locals_dict_table[] = { // instance methods - { MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&mp_machine_adc_init_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_deinit), (mp_obj_t)&mp_machine_adc_deinit_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_value), (mp_obj_t)&mp_machine_adc_value_obj }, // class methods diff --git a/nrf5/hal/hal_adc.c b/nrf5/hal/hal_adc.c index fb46961404..17a63fee5c 100644 --- a/nrf5/hal/hal_adc.c +++ b/nrf5/hal/hal_adc.c @@ -70,75 +70,60 @@ static uint8_t battery_level_in_percent(const uint16_t mvolts) return battery_level; } - -void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init) { - - while (p_instance->ENABLE && p_instance->BUSY) - { - // spin loop if another user is in progress of sampling - } - - p_instance->INTENSET = ADC_INTENSET_END_Msk; - p_instance->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos) +uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) { + ADC_BASE->INTENSET = ADC_INTENSET_END_Msk; + ADC_BASE->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos) | (ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling << ADC_CONFIG_INPSEL_Pos) - | (ADC_CONFIG_REFSEL_VBG << ADC_CONFIG_REFSEL_Pos) - | (hal_adc_input_lookup[p_adc_init->channel]) - | (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos); -} + | (ADC_CONFIG_REFSEL_VBG << ADC_CONFIG_REFSEL_Pos) + | (hal_adc_input_lookup[p_adc_conf->channel]) + | (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos); -void hal_adc_start(HAL_ADC_Type * p_instance) { - p_instance->ENABLE = ADC_ENABLE_ENABLE_Enabled; -} + ADC_BASE->EVENTS_END = 0; + ADC_BASE->ENABLE = ADC_ENABLE_ENABLE_Enabled; -void hal_adc_stop(HAL_ADC_Type * p_instance) { - p_instance->ENABLE = ADC_ENABLE_ENABLE_Disabled; -} + ADC_BASE->EVENTS_END = 0; + ADC_BASE->TASKS_START = 1; -uint8_t hal_adc_value(HAL_ADC_Type * p_instance) { - - p_instance->EVENTS_END = 0; - p_instance->TASKS_START = 1; - - while (!p_instance->EVENTS_END) { + while (!ADC_BASE->EVENTS_END) { ; } - uint8_t adc_result = p_instance->RESULT; + uint8_t adc_result; - p_instance->EVENTS_END = 0; - p_instance->TASKS_STOP = 1; + ADC_BASE->EVENTS_END = 0; + adc_result = ADC_BASE->RESULT; + ADC_BASE->TASKS_STOP = 1; return adc_result; } -uint8_t hal_adc_battery_level(HAL_ADC_Type * p_instance) { - p_instance->INTENSET = ADC_INTENSET_END_Msk; - p_instance->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos) +uint16_t hal_adc_battery_level(void) { + ADC_BASE->INTENSET = ADC_INTENSET_END_Msk; + ADC_BASE->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos) | (ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling << ADC_CONFIG_INPSEL_Pos) | (ADC_CONFIG_REFSEL_VBG << ADC_CONFIG_REFSEL_Pos) | (ADC_CONFIG_PSEL_Disabled << ADC_CONFIG_PSEL_Pos) | (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos); - p_instance->EVENTS_END = 0; - p_instance->ENABLE = ADC_ENABLE_ENABLE_Enabled; + ADC_BASE->EVENTS_END = 0; + ADC_BASE->ENABLE = ADC_ENABLE_ENABLE_Enabled; - p_instance->EVENTS_END = 0; - p_instance->TASKS_START = 1; + ADC_BASE->EVENTS_END = 0; + ADC_BASE->TASKS_START = 1; - while (!p_instance->EVENTS_END) { + while (!ADC_BASE->EVENTS_END) { ; } uint8_t adc_result; uint16_t batt_lvl_in_milli_volts; - p_instance->EVENTS_END = 0; - adc_result = p_instance->RESULT; - p_instance->TASKS_STOP = 1; + ADC_BASE->EVENTS_END = 0; + adc_result = ADC_BASE->RESULT; + ADC_BASE->TASKS_STOP = 1; batt_lvl_in_milli_volts = ADC_RESULT_IN_MILLI_VOLTS(adc_result) + DIODE_FWD_VOLT_DROP_MILLIVOLTS; return battery_level_in_percent(batt_lvl_in_milli_volts); - } #endif // HAL_ADC_MODULE_ENABLED diff --git a/nrf5/hal/hal_adc.h b/nrf5/hal/hal_adc.h index 8fd19d14b7..deca7d90a7 100644 --- a/nrf5/hal/hal_adc.h +++ b/nrf5/hal/hal_adc.h @@ -59,25 +59,17 @@ typedef enum { */ typedef struct { hal_adc_channel_t channel; -} hal_adc_init_t; +} hal_adc_config_t; /** * @brief ADC handle Structure definition */ -typedef struct __ADC_HandleTypeDef -{ - void *instance; /* ADC register base address */ - hal_adc_init_t init; /* ADC initialization parameters */ +typedef struct __ADC_HandleTypeDef { + hal_adc_config_t config; /* ADC config parameters */ } ADC_HandleTypeDef; -void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init); +uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf); -void hal_adc_start(HAL_ADC_Type * p_instance); - -void hal_adc_stop(HAL_ADC_Type * p_instance); - -uint8_t hal_adc_value(HAL_ADC_Type * p_instance); - -uint8_t hal_adc_battery_level(HAL_ADC_Type * p_instance); +uint16_t hal_adc_battery_level(void); #endif // HAL_ADC_H__ diff --git a/nrf5/hal/hal_adce.c b/nrf5/hal/hal_adce.c index 21f1a7e8ee..3fd52cef91 100644 --- a/nrf5/hal/hal_adce.c +++ b/nrf5/hal/hal_adce.c @@ -29,20 +29,11 @@ #ifdef HAL_ADCE_MODULE_ENABLED -void hal_adc_init(HAL_ADC_Type * p_instance, hal_adc_init_t const * p_adc_init) { -} - -void hal_adc_start(HAL_ADC_Type * p_instance) { -} - -void hal_adc_stop(HAL_ADC_Type * p_instance) { -} - -uint8_t hal_adc_value(HAL_ADC_Type * p_instance) { +uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) { return 0; } -uint8_t hal_adc_battery_level(HAL_ADC_Type * p_instance) { +uint16_t hal_adc_battery_level(void) { return 0; } From a5bb966614bc1cedecf9141733b0aaa00d6bf782 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 12 Jan 2017 19:54:07 +0100 Subject: [PATCH 187/809] nrf5/boards: Updating pca10028 (nrf51) board config. Enable SPI machine module. Enable flow control on UART. Correcting SPI CLK, MISO and MOSI pin assignments. --- nrf5/boards/pca10028/mpconfigboard.h | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 1e44ceef1a..01dcda767f 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -30,6 +30,10 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" +#define MICROPY_PY_DISPLAY (0) +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) + +#define MICROPY_PY_MACHINE_SPI (1) #define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) @@ -62,15 +66,19 @@ // UART config #define MICROPY_HW_UART1_RX (11) #define MICROPY_HW_UART1_TX (9) +#define MICROPY_HW_UART1_CTS (10) +#define MICROPY_HW_UART1_RTS (8) #define MICROPY_HW_UART1_RX_PORT (0) #define MICROPY_HW_UART1_TX_PORT (0) -#define MICROPY_HW_UART1_HWFC (0) +#define MICROPY_HW_UART1_CTS_PORT (0) +#define MICROPY_HW_UART1_RTS_PORT (0) +#define MICROPY_HW_UART1_HWFC (1) // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" -#define MICROPY_HW_SPI0_SCK (1) // A3 -#define MICROPY_HW_SPI0_MOSI (2) // A2 -#define MICROPY_HW_SPI0_MISO (3) // A1 +#define MICROPY_HW_SPI0_SCK (29) +#define MICROPY_HW_SPI0_MOSI (25) +#define MICROPY_HW_SPI0_MISO (28) #define MICROPY_HW_SPI0_SCK_PORT (0) #define MICROPY_HW_SPI0_MISO_PORT (0) #define MICROPY_HW_SPI0_MOSI_PORT (0) From 46caefbeeb941f18f9a958005391c7d8edc83bc2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 16:15:21 +0100 Subject: [PATCH 188/809] nrf5/drivers: Adding a new framebuffer implementation to replace the mono_fb. --- nrf5/drivers/display/framebuffer.c | 116 +++++++++++++++++++++++++++++ nrf5/drivers/display/framebuffer.h | 97 ++++++++++++++++++++++++ 2 files changed, 213 insertions(+) create mode 100644 nrf5/drivers/display/framebuffer.c create mode 100644 nrf5/drivers/display/framebuffer.h diff --git a/nrf5/drivers/display/framebuffer.c b/nrf5/drivers/display/framebuffer.c new file mode 100644 index 0000000000..988c7715ec --- /dev/null +++ b/nrf5/drivers/display/framebuffer.c @@ -0,0 +1,116 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include +#include "py/obj.h" +#include "framebuffer.h" + +#if MICROPY_PY_DISPLAY_FRAMEBUFFER + +void framebuffer_init(framebuffer_t * p_fb, framebuffer_init_t * p_init_conf) { + uint16_t width = p_init_conf->width; + uint16_t height = p_init_conf->height; + + if (p_init_conf->line_orientation == FRAMEBUFFER_LINE_DIR_HORIZONTAL) { + uint16_t dirty_row_stride = height / 8; + p_fb->fb_dirty = m_new(framebuffer_byte_t, dirty_row_stride); + p_fb->fb_dirty_stride = dirty_row_stride; + p_fb->fb_stride = width / 8; + } else { // FRAMEBUFFER_LINE_DIR_VERTICAL + uint16_t dirty_column_stride = width / 8; + p_fb->fb_dirty = m_new(framebuffer_byte_t, dirty_column_stride); + p_fb->fb_dirty_stride = dirty_column_stride; + p_fb->fb_stride = height / 8; + } + + p_fb->fb_new = m_new(framebuffer_byte_t, (width * height / 8)); + + if (p_init_conf->double_buffer) { + p_fb->fb_old = m_new(framebuffer_byte_t, (width * height / 8)); + } + p_fb->line_orientation = p_init_conf->line_orientation; + p_fb->screen_width = width; + p_fb->screen_height = height; +} + + +void framebuffer_flip(framebuffer_t * p_fb) { + if (p_fb->fb_double) { + framebuffer_byte_t * old = p_fb->fb_old; + p_fb->fb_old = p_fb->fb_new; + p_fb->fb_new = old; + } +} + +void framebuffer_pixel_set(framebuffer_t * p_fb, uint16_t x, uint16_t y) { + if (p_fb->line_orientation == FRAMEBUFFER_LINE_DIR_HORIZONTAL) { + uint16_t col = (x / 8); + uint16_t row = y; + uint8_t bit_pos = x % 8; + + p_fb->fb_new[row * (p_fb->fb_stride) + col].byte |= (1 << bit_pos); + p_fb->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); + } else { + uint16_t col = x; + uint16_t row = (y / 8); + uint8_t bit_pos = y % 8; + + p_fb->fb_new[col * (p_fb->fb_stride) + row].byte |= (1 << bit_pos); + p_fb->fb_dirty[x / 8].byte |= (uint8_t)(0x1 << x % 8); + } +} + +void framebuffer_pixel_clear(framebuffer_t * p_fb, uint16_t x, uint16_t y) { + if (p_fb->line_orientation == FRAMEBUFFER_LINE_DIR_HORIZONTAL) { + uint16_t col = (x / 8); + uint16_t row = y; + uint8_t bit_pos = x % 8; + + p_fb->fb_new[row * (p_fb->fb_stride) + col].byte &= ~(1 << bit_pos); + p_fb->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); + } else { + uint16_t col = x; + uint16_t row = (y / 8); + uint8_t bit_pos = y % 8; + + p_fb->fb_new[col * (p_fb->fb_stride) + row].byte &= ~(1 << bit_pos); + p_fb->fb_dirty[x / 8].byte |= (uint8_t)(0x1 << x % 8); + } +} + +void framebuffer_clear(framebuffer_t * p_fb) { + memset(p_fb->fb_new, 0x00, p_fb->screen_width * p_fb->screen_height / 8); + memset(p_fb->fb_dirty, 0xFF, p_fb->fb_dirty_stride); +} + +void framebuffer_fill(framebuffer_t * p_fb) { + memset(p_fb->fb_new, 0xFF, p_fb->screen_width * p_fb->screen_height / 8); + memset(p_fb->fb_dirty, 0xFF, p_fb->fb_dirty_stride); +} + +#endif // MICROPY_PY_DISPLAY_FRAMEBUFFER diff --git a/nrf5/drivers/display/framebuffer.h b/nrf5/drivers/display/framebuffer.h new file mode 100644 index 0000000000..1c9ad05b7c --- /dev/null +++ b/nrf5/drivers/display/framebuffer.h @@ -0,0 +1,97 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef DISPLAY_FRAMEBUFFER_H__ +#define DISPLAY_FRAMEBUFFER_H__ + +#include +#include + +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} bits_le_t; + +typedef struct { + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +} bits_be_t; + +typedef struct { + union { + uint8_t byte; + bits_le_t bits_le; + bits_be_t bits_be; + }; +} framebuffer_byte_t; + +typedef enum { + FRAMEBUFFER_LINE_DIR_HORIZONTAL, + FRAMEBUFFER_LINE_DIR_VERTICAL +} framebuffer_line_orientation_t; + +typedef struct { + framebuffer_byte_t * fb_new; + framebuffer_byte_t * fb_old; + uint16_t fb_stride; + bool fb_double; + framebuffer_byte_t * fb_dirty; + uint16_t fb_dirty_stride; + uint16_t fb_orientation; + uint16_t screen_height; + uint16_t screen_width; + framebuffer_line_orientation_t line_orientation; +} framebuffer_t; + +typedef struct { + uint16_t width; + uint16_t height; + framebuffer_line_orientation_t line_orientation; + bool double_buffer; +} framebuffer_init_t; + +void framebuffer_init(framebuffer_t * p_fb, framebuffer_init_t * p_init_conf); +void framebuffer_deinit(framebuffer_t * p_fb); + +void framebuffer_flip(framebuffer_t * p_fb); +void framebuffer_pixel_set(framebuffer_t * p_fb, uint16_t x, uint16_t y); +void framebuffer_pixel_clear(framebuffer_t * p_fb, uint16_t x, uint16_t y); +void framebuffer_clear(framebuffer_t * p_fb); +void framebuffer_fill(framebuffer_t * p_fb); + +#endif // DISPLAY_FRAMEBUFFER_H__ From 56b3655f7ec10f96c5236683d4e4e0cae8df496e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 16:21:27 +0100 Subject: [PATCH 189/809] nrf5/drivers: Adding new structures to moddisplay. Adding a display_t structure to cast all other displays into, to retrieve function pointer table of a display object type. Also adding the function table structure which needs to be filled by any display object. --- nrf5/drivers/display/moddisplay.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/nrf5/drivers/display/moddisplay.h b/nrf5/drivers/display/moddisplay.h index 353097710e..82ff595027 100644 --- a/nrf5/drivers/display/moddisplay.h +++ b/nrf5/drivers/display/moddisplay.h @@ -27,4 +27,20 @@ #ifndef MODDISPLAY_H__ #define MODDISPLAY_H__ +typedef struct _display_t display_t; + +typedef void (*pixel_set_callback_t)(void * p_display, + uint16_t x, + uint16_t y, + uint16_t color); + +typedef struct _display_draw_callbacks_t { + pixel_set_callback_t pixel_set; +} display_draw_callbacks_t; + +typedef struct _display_t { + mp_obj_base_t base; + display_draw_callbacks_t draw_callbacks; +} display_t; + #endif // MODDISPLAY_H__ From 63fc32e56f9fad6126118f613639ef2055a877c4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 17:28:41 +0100 Subject: [PATCH 190/809] nrf5/adc: Adding all 8 instances to adc python module. Valid for both nrf51 and nrf52. --- nrf5/adc.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/nrf5/adc.c b/nrf5/adc.c index 6d407d2840..2adb318b6e 100644 --- a/nrf5/adc.c +++ b/nrf5/adc.c @@ -40,12 +40,14 @@ typedef struct _machine_adc_obj_t { ADC_HandleTypeDef *adc; } machine_adc_obj_t; -ADC_HandleTypeDef ADCHandle0 = {.config.channel = 2}; -ADC_HandleTypeDef ADCHandle1 = {.config.channel = 3}; -ADC_HandleTypeDef ADCHandle2 = {.config.channel = 4}; -ADC_HandleTypeDef ADCHandle3 = {.config.channel = 5}; -ADC_HandleTypeDef ADCHandle4 = {.config.channel = 6}; -ADC_HandleTypeDef ADCHandle5 = {.config.channel = 7}; +ADC_HandleTypeDef ADCHandle0 = {.config.channel = 0}; +ADC_HandleTypeDef ADCHandle1 = {.config.channel = 1}; +ADC_HandleTypeDef ADCHandle2 = {.config.channel = 2}; +ADC_HandleTypeDef ADCHandle3 = {.config.channel = 3}; +ADC_HandleTypeDef ADCHandle4 = {.config.channel = 4}; +ADC_HandleTypeDef ADCHandle5 = {.config.channel = 5}; +ADC_HandleTypeDef ADCHandle6 = {.config.channel = 6}; +ADC_HandleTypeDef ADCHandle7 = {.config.channel = 7}; STATIC const machine_adc_obj_t machine_adc_obj[] = { {{&machine_adc_type}, &ADCHandle0}, @@ -54,13 +56,15 @@ STATIC const machine_adc_obj_t machine_adc_obj[] = { {{&machine_adc_type}, &ADCHandle3}, {{&machine_adc_type}, &ADCHandle4}, {{&machine_adc_type}, &ADCHandle5}, + {{&machine_adc_type}, &ADCHandle6}, + {{&machine_adc_type}, &ADCHandle7}, }; STATIC int adc_find(mp_obj_t id) { // given an integer id int adc_id = mp_obj_get_int(id); - int adc_idx = adc_id - 2; + int adc_idx = adc_id; if (adc_idx >= 0 && adc_idx <= MP_ARRAY_SIZE(machine_adc_obj) && machine_adc_obj[adc_idx].adc != NULL) { From 496de3a839df3a90c85702181442b9c5bef20dad Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 17:51:49 +0100 Subject: [PATCH 191/809] nrf52/hal: Adding adce (saadc) implementation for nrf52 to sample values on a channel. --- nrf5/hal/hal_adce.c | 82 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 80 insertions(+), 2 deletions(-) diff --git a/nrf5/hal/hal_adce.c b/nrf5/hal/hal_adce.c index 3fd52cef91..a121e93177 100644 --- a/nrf5/hal/hal_adce.c +++ b/nrf5/hal/hal_adce.c @@ -23,14 +23,92 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ - +#include #include "mphalport.h" #include "hal_adc.h" #ifdef HAL_ADCE_MODULE_ENABLED +static const uint32_t hal_adc_input_lookup_pos[] = { + SAADC_CH_PSELP_PSELP_AnalogInput0 << SAADC_CH_PSELP_PSELP_Pos, + SAADC_CH_PSELP_PSELP_AnalogInput1 << SAADC_CH_PSELP_PSELP_Pos, + SAADC_CH_PSELP_PSELP_AnalogInput2 << SAADC_CH_PSELP_PSELP_Pos, + SAADC_CH_PSELP_PSELP_AnalogInput3 << SAADC_CH_PSELP_PSELP_Pos, + SAADC_CH_PSELP_PSELP_AnalogInput4 << SAADC_CH_PSELP_PSELP_Pos, + SAADC_CH_PSELP_PSELP_AnalogInput5 << SAADC_CH_PSELP_PSELP_Pos, + SAADC_CH_PSELP_PSELP_AnalogInput6 << SAADC_CH_PSELP_PSELP_Pos, + SAADC_CH_PSELP_PSELP_AnalogInput7 << SAADC_CH_PSELP_PSELP_Pos +}; + +#define HAL_ADCE_PSELP_NOT_CONNECTED (SAADC_CH_PSELP_PSELP_NC << SAADC_CH_PSELP_PSELP_Pos) +#define HAL_ADCE_PSELP_VDD (SAADC_CH_PSELP_PSELP_VDD << SAADC_CH_PSELP_PSELP_Pos) + +static const uint32_t hal_adc_input_lookup_neg[] = { + SAADC_CH_PSELN_PSELN_AnalogInput0 << SAADC_CH_PSELN_PSELN_Pos, + SAADC_CH_PSELN_PSELN_AnalogInput1 << SAADC_CH_PSELN_PSELN_Pos, + SAADC_CH_PSELN_PSELN_AnalogInput2 << SAADC_CH_PSELN_PSELN_Pos, + SAADC_CH_PSELN_PSELN_AnalogInput3 << SAADC_CH_PSELN_PSELN_Pos, + SAADC_CH_PSELN_PSELN_AnalogInput4 << SAADC_CH_PSELN_PSELN_Pos, + SAADC_CH_PSELN_PSELN_AnalogInput5 << SAADC_CH_PSELN_PSELN_Pos, + SAADC_CH_PSELN_PSELN_AnalogInput6 << SAADC_CH_PSELN_PSELN_Pos, + SAADC_CH_PSELN_PSELN_AnalogInput7 << SAADC_CH_PSELN_PSELN_Pos +}; + +#define HAL_ADCE_PSELN_NOT_CONNECTED (SAADC_CH_PSELN_PSELN_NC << SAADC_CH_PSELN_PSELN_Pos) +#define HAL_ADCE_PSELN_VDD (SAADC_CH_PSELN_PSELN_VDD << SAADC_CH_PSELN_PSELN_Pos) + uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) { - return 0; + int16_t result = 0; + + // configure to use VDD/4 and gain 1/4 + ADC_BASE->CH[0].CONFIG = (SAADC_CH_CONFIG_GAIN_Gain1_4 << SAADC_CH_CONFIG_GAIN_Pos) + | (SAADC_CH_CONFIG_MODE_SE << SAADC_CH_CONFIG_MODE_Pos) + | (SAADC_CH_CONFIG_REFSEL_VDD1_4 << SAADC_CH_CONFIG_REFSEL_Pos) + | (SAADC_CH_CONFIG_RESN_Bypass << SAADC_CH_CONFIG_RESN_Pos) + | (SAADC_CH_CONFIG_RESP_Bypass << SAADC_CH_CONFIG_RESP_Pos) + | (SAADC_CH_CONFIG_TACQ_3us << SAADC_CH_CONFIG_TACQ_Pos); + + // positive input + ADC_BASE->CH[0].PSELP = hal_adc_input_lookup_pos[p_adc_conf->channel]; // HAL_ADCE_PSELP_VDD; + ADC_BASE->CH[0].PSELN = HAL_ADCE_PSELN_NOT_CONNECTED; + + ADC_BASE->RESOLUTION = SAADC_RESOLUTION_VAL_8bit << SAADC_RESOLUTION_VAL_Pos; + ADC_BASE->RESULT.MAXCNT = 1; + ADC_BASE->RESULT.PTR = (uint32_t)&result; + ADC_BASE->SAMPLERATE = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos; + ADC_BASE->ENABLE = SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos; + + // calibrate ADC + ADC_BASE->TASKS_CALIBRATEOFFSET = 1; + while (ADC_BASE->EVENTS_CALIBRATEDONE == 0) { + ; + } + ADC_BASE->EVENTS_CALIBRATEDONE = 0; + while (ADC_BASE->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos)) { + ; + } + + // start the ADC + ADC_BASE->TASKS_START = 1; + while (ADC_BASE->EVENTS_STARTED == 0) { + ; + } + ADC_BASE->EVENTS_STARTED = 0; + + // sample ADC + ADC_BASE->TASKS_SAMPLE = 1; + while (ADC_BASE->EVENTS_END == 0) { + ; + } + ADC_BASE->EVENTS_END = 0; + + ADC_BASE->TASKS_STOP = 1; + while (ADC_BASE->EVENTS_STOPPED == 0) { + ; + } + ADC_BASE->EVENTS_STOPPED = 0; + + return result; } uint16_t hal_adc_battery_level(void) { From c87716d715fc959b33d960d780e3545e7723c182 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 17:53:30 +0100 Subject: [PATCH 192/809] nrf5/boards: Adding ADC pins in pins.csv file for pca10056 (nrf52840). --- nrf5/boards/pca10056/pins.csv | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/nrf5/boards/pca10056/pins.csv b/nrf5/boards/pca10056/pins.csv index da863e75ab..f2f7f19672 100644 --- a/nrf5/boards/pca10056/pins.csv +++ b/nrf5/boards/pca10056/pins.csv @@ -1,9 +1,9 @@ PA0,PA0 PA1,PA1 -PA2,PA2 -PA3,PA3 -PA4,PA4 -PA5,PA5 +PA2,PA2,ADC0_IN0 +PA3,PA3,ADC0_IN1 +PA4,PA4,ADC0_IN2 +PA5,PA5,ADC0_IN3 PA6,PA6 PA7,PA7 PA8,PA8 @@ -26,10 +26,10 @@ PA24,PA24 PA25,PA25 PA26,PA26 PA27,PA27 -PA28,PA28 -PA29,PA29 -PA30,PA30 -PA31,PA31 +PA28,PA28,ADC0_IN4 +PA29,PA29,ADC0_IN5 +PA30,PA30,ADC0_IN6 +PA31,PA31,ADC0_IN7 PB0,PB0 PB1,PB1 PB2,PB2 From 2b383b4ede81f1246ac96d2548d033ba706d9d24 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 17:55:35 +0100 Subject: [PATCH 193/809] nrf5/hal: Removing stdio.h include in adce.c which were used for debugging. --- nrf5/hal/hal_adce.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/hal/hal_adce.c b/nrf5/hal/hal_adce.c index a121e93177..fbfe7750b3 100644 --- a/nrf5/hal/hal_adce.c +++ b/nrf5/hal/hal_adce.c @@ -23,7 +23,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include + #include "mphalport.h" #include "hal_adc.h" From 4c06455105f00b3b50c5dccafff045d848b42533 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:06:48 +0100 Subject: [PATCH 194/809] nrf5/drivers: Moving oled ssd1306 driver over to new framebuffer layout. Moving some of the draw algorithms into the object in order to optimize the speed on writing data from the framebuffer. --- nrf5/drivers/display/oled_ssd1306_driver.c | 19 +++- nrf5/drivers/display/oled_ssd1306_driver.h | 4 +- nrf5/drivers/display/oled_ssd1306_obj.c | 118 +++++++++++++++------ 3 files changed, 101 insertions(+), 40 deletions(-) diff --git a/nrf5/drivers/display/oled_ssd1306_driver.c b/nrf5/drivers/display/oled_ssd1306_driver.c index 07b3224515..7083a66927 100644 --- a/nrf5/drivers/display/oled_ssd1306_driver.c +++ b/nrf5/drivers/display/oled_ssd1306_driver.c @@ -32,6 +32,8 @@ #include "hal_spi.h" #include "hal_time.h" +#include "framebuffer.h" + #if MICROPY_PY_DISPLAY_OLED_SSD1306 static pin_obj_t * mp_cs_pin; @@ -146,14 +148,14 @@ void driver_ssd1306_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_ob static void set_col(uint16_t start_col, uint16_t end_col) { - cmd_write(SET_COL_ADDR); /* Column Command address */ + cmd_write(SET_COL_ADDR); // column command address cmd_write(start_col & 0xFF ); cmd_write(end_col & 0xFF); } static void set_page(uint16_t start_page, uint16_t end_page) { - cmd_write(SET_PAGE_ADDR); /* Column Command address */ + cmd_write(SET_PAGE_ADDR); // page command address cmd_write(start_page & 0xFF); cmd_write(end_page & 0xFF); } @@ -188,8 +190,19 @@ void driver_ssd1306_clear(uint16_t color) mp_hal_pin_high(mp_cs_pin); } -void driver_ssd1306_update_line(uint16_t line, fb_byte_t * p_bytes, uint16_t len, bool compressed) { +void driver_ssd1306_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { + set_col(line, line); + set_page(0, 63); + mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + for (uint8_t i = 0; i < len; i++) { + uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; + raw_write(byte); + } + + mp_hal_pin_high(mp_cs_pin); } #endif diff --git a/nrf5/drivers/display/oled_ssd1306_driver.h b/nrf5/drivers/display/oled_ssd1306_driver.h index 0312f87914..c9b33ab02d 100644 --- a/nrf5/drivers/display/oled_ssd1306_driver.h +++ b/nrf5/drivers/display/oled_ssd1306_driver.h @@ -30,12 +30,12 @@ #include "py/mphal.h" #include "hal_spi.h" -#include "lcd_mono_fb.h" +#include "framebuffer.h" void driver_ssd1306_init(NRF_SPI_Type * p_instance, pin_obj_t * cs_pin, pin_obj_t * dc_pin, pin_obj_t * reset_pin); void driver_ssd1306_clear(uint16_t color); -void driver_ssd1306_update_line(uint16_t line, fb_byte_t * p_bytes, uint16_t len, bool compressed); +void driver_ssd1306_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); #endif // OLED_SSD1306_DRIVER_H__ diff --git a/nrf5/drivers/display/oled_ssd1306_obj.c b/nrf5/drivers/display/oled_ssd1306_obj.c index 655189cb74..c6410bcd8a 100644 --- a/nrf5/drivers/display/oled_ssd1306_obj.c +++ b/nrf5/drivers/display/oled_ssd1306_obj.c @@ -24,8 +24,6 @@ * THE SOFTWARE. */ -#include - #include "py/obj.h" #include "py/runtime.h" #include "py/mphal.h" @@ -38,27 +36,35 @@ /// \moduleref display /// \class SSD1306 - SSD1306 TFT LCD display driver. +#include "moddisplay.h" +#include "framebuffer.h" #include "pin.h" #include "spi.h" -#include "lcd_mono_fb.h" typedef struct _oled_ssd1306_obj_t { mp_obj_base_t base; + display_draw_callbacks_t draw_callbacks; + framebuffer_t * framebuffer; machine_hard_spi_obj_t *spi; pin_obj_t * pin_cs; pin_obj_t * pin_dc; pin_obj_t * pin_reset; - mp_obj_framebuf_t * framebuffer; } oled_ssd1306_obj_t; -static void dirty_line_update_cb(mp_obj_framebuf_t * p_framebuffer, - uint16_t line, - fb_byte_t * p_new, - fb_byte_t * p_old) { - // the lcd does not have double buffer needs, skip it. - (void)p_old; +#define OLED_SSD1306_COLOR_BLACK 0 +#define OLED_SSD1306_COLOR_WHITE 1 - driver_ssd1306_update_line(line, p_new, p_framebuffer->bytes_stride, true); +static void set_pixel(void * p_display, + uint16_t x, + uint16_t y, + uint16_t color) { + oled_ssd1306_obj_t *self = (oled_ssd1306_obj_t *)p_display; + + if (color == OLED_SSD1306_COLOR_BLACK) { + framebuffer_pixel_clear(self->framebuffer, x, y); + } else { + framebuffer_pixel_set(self->framebuffer, x, y); + } } /// \method __str__() @@ -83,9 +89,12 @@ STATIC void oled_ssd1306_print(const mp_print_t *print, mp_obj_t o, mp_print_kin self->pin_reset->port, self->pin_reset->pin); - mp_printf(print, " FB(width=%u, height=%u, dir=%u))\n", - self->framebuffer->width, - self->framebuffer->height); + mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", + self->framebuffer->screen_width, + self->framebuffer->screen_height, + self->framebuffer->line_orientation, + self->framebuffer->fb_stride, + self->framebuffer->fb_dirty_stride); } // for make_new @@ -100,6 +109,18 @@ enum { /* +Example for nrf51822 / pca10028: + +from machine import Pin, SPI +from display import SSD1306 +cs = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) +dc = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +d = SSD1306(128, 64, spi, cs, dc, reset) +d.text("Hello World!", 32, 32) +d.show() + Example for nrf52832 / pca10040: from machine import Pin, SPI @@ -107,7 +128,7 @@ from display import SSD1306 cs = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) reset = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) dc = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=4000000) +spi = SPI(0, baudrate=8000000) d = SSD1306(128, 64, spi, cs, dc, reset) d.text("Hello World!", 32, 32) d.show() @@ -141,6 +162,7 @@ STATIC mp_obj_t oled_ssd1306_make_new(const mp_obj_type_t *type, size_t n_args, oled_ssd1306_obj_t *s = m_new_obj_with_finaliser(oled_ssd1306_obj_t); s->base.type = type; + s->draw_callbacks.pixel_set = set_pixel; mp_int_t width; mp_int_t height; @@ -187,15 +209,22 @@ STATIC mp_obj_t oled_ssd1306_make_new(const mp_obj_type_t *type, size_t n_args, "Display Reset Pin not set")); } - // direction arg not yet configurable - mp_int_t vertical = true; - s->framebuffer = lcd_mono_fb_helper_make_new(width, height, vertical); + framebuffer_init_t init_conf = { + .width = width, + .height = height, + .line_orientation = FRAMEBUFFER_LINE_DIR_VERTICAL, + .double_buffer = false + }; + + s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); + + framebuffer_init(s->framebuffer, &init_conf); driver_ssd1306_init(s->spi->pyb->spi->instance, s->pin_cs, s->pin_dc, s->pin_reset); // Default to black background driver_ssd1306_clear(0); - // display_clear_screen(s->framebuffer, 0x0); + framebuffer_clear(s->framebuffer); return MP_OBJ_FROM_PTR(s); } @@ -207,20 +236,40 @@ STATIC mp_obj_t oled_ssd1306_make_new(const mp_obj_type_t *type, size_t n_args, STATIC mp_obj_t oled_ssd1306_fill(mp_obj_t self_in, mp_obj_t color) { oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(self_in); - driver_ssd1306_clear((uint8_t)mp_obj_get_int(color)); - - display_clear_screen(self->framebuffer, (uint8_t)mp_obj_get_int(color)); + if (color == MP_OBJ_NEW_SMALL_INT(OLED_SSD1306_COLOR_BLACK)) { + framebuffer_clear(self->framebuffer); + } else { + framebuffer_fill(self->framebuffer); + } return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(oled_ssd1306_fill_obj, oled_ssd1306_fill); +static void render(framebuffer_t * p_framebuffer) { + for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { + if (p_framebuffer->fb_dirty[i].byte != 0) { + for (uint16_t b = 0; b < 8; b++) { + if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { + uint16_t line_num = (i * 8) + b; + driver_ssd1306_update_line(line_num, + &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], + p_framebuffer->fb_stride); + } + } + + p_framebuffer->fb_dirty[i].byte = 0x00; + } + } +} + /// \method show() /// Display content in framebuffer. STATIC mp_obj_t oled_ssd1306_show(size_t n_args, const mp_obj_t *args) { oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(args[0]); - display_update(self->framebuffer, false, dirty_line_update_cb); + render(self->framebuffer); + framebuffer_flip(self->framebuffer); return mp_const_none; } @@ -250,18 +299,13 @@ STATIC mp_obj_t oled_ssd1306_pixel(size_t n_args, const mp_obj_t *args) { oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(args[0]); mp_int_t x = mp_obj_get_int(args[1]); mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color; - if (n_args >= 3) { - color = mp_obj_get_int(args[3]); - } - (void)self; - (void)x; - (void)y; - (void)color; + mp_int_t color = mp_obj_get_int(args[3]); + + set_pixel(self, x, y, color); return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1306_pixel_obj, 3, 4, oled_ssd1306_pixel); +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1306_pixel_obj, 4, 4, oled_ssd1306_pixel); /// \method pixel(text, x, y, [color]) /// Write one pixel in framebuffer. @@ -278,8 +322,12 @@ STATIC mp_obj_t oled_ssd1306_text(size_t n_args, const mp_obj_t *args) { color = mp_obj_get_int(args[3]); } - display_print_string(self->framebuffer, x, y, str); + //display_print_string(self->framebuffer, x, y, str); + (void)x; + (void)y; + (void)self; + (void)str; (void)color; return mp_const_none; @@ -304,8 +352,8 @@ STATIC const mp_map_elem_t oled_ssd1306_locals_dict_table[] = { #if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&oled_ssd1306_bitmap_obj) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_BLACK) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_WHITE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(OLED_SSD1306_COLOR_BLACK) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(OLED_SSD1306_COLOR_WHITE) }, { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, }; From bfca15bdffeb4271d589f91f25055718a660a636 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:18:14 +0100 Subject: [PATCH 195/809] nrf5/drivers: Adding draw module with circle, rectangle and text functions. Can be used by any display object which implements display callback functions. --- nrf5/drivers/graphic/draw.c | 185 ++++++++++++++++++++++++++++++++++++ nrf5/drivers/graphic/draw.h | 26 +++++ 2 files changed, 211 insertions(+) create mode 100644 nrf5/drivers/graphic/draw.c create mode 100644 nrf5/drivers/graphic/draw.h diff --git a/nrf5/drivers/graphic/draw.c b/nrf5/drivers/graphic/draw.c new file mode 100644 index 0000000000..114d0288c0 --- /dev/null +++ b/nrf5/drivers/graphic/draw.c @@ -0,0 +1,185 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/mphal.h" + +#include "moddisplay.h" +#include "font_petme128_8x8.h" + +/// \method circle(display, radius, x, y, color, [fill]) +/// Draw a circle in the display framebuffer. +STATIC mp_obj_t draw_circle(mp_uint_t n_args, const mp_obj_t *args) { + display_t * screen = MP_OBJ_TO_PTR(args[0]); + + mp_uint_t radius = mp_obj_get_int(args[1]); + mp_uint_t xc = mp_obj_get_int(args[2]); + mp_uint_t yc = mp_obj_get_int(args[3]); + mp_uint_t color = mp_obj_get_int(args[4]); + + pixel_set_callback_t pixel_set_cb = screen->draw_callbacks.pixel_set; + + // algorithm borrowed from: + // http://stackoverflow.com/a/35541416 + + uint16_t y = radius; + uint16_t x = 0; + int d = 3 - 2 * radius; + + while (x <= y) { + for (uint16_t hor = 0; hor < x + 1; hor++) { + pixel_set_cb(screen, xc+hor, yc+y, color); + pixel_set_cb(screen, xc-hor, yc+y, color); + pixel_set_cb(screen, xc+hor, yc-y, color); + pixel_set_cb(screen, xc-hor, yc-y, color); + pixel_set_cb(screen, xc+x, yc+hor, color); + pixel_set_cb(screen, xc-x, yc+hor, color); + pixel_set_cb(screen, xc+x, yc-hor, color); + pixel_set_cb(screen, xc-x, yc-hor, color); + pixel_set_cb(screen, xc+hor, yc+x, color); + pixel_set_cb(screen, xc-hor, yc+x, color); + pixel_set_cb(screen, xc+hor, yc-x, color); + pixel_set_cb(screen, xc-hor, yc-x, color); + pixel_set_cb(screen, xc+y, yc+hor, color); + pixel_set_cb(screen, xc-y, yc+hor, color); + pixel_set_cb(screen, xc+y, yc-hor, color); + pixel_set_cb(screen, xc-y, yc-hor, color); + } + + if (d < 0) { + d = d + 4 * x + 6; + } else { + d = d + 4 * (x-y) + 10; + y = y - 1; + } + + x = x + 1; + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(graphics_draw_circle_obj, 5, 6, draw_circle); + +STATIC void graphics_draw_char(display_t * screen, uint16_t x, uint16_t y, char ch, uint16_t color, uint8_t font_size) { + + pixel_set_callback_t pixel_set_cb = screen->draw_callbacks.pixel_set; + + uint16_t col = x; + for (uint8_t i = 0; i < 8; i++) { + uint16_t current_col = col + (i * font_size); + + for (uint8_t y_pos = 0; y_pos < 8; y_pos++) { + if ((((uint8_t)font_petme128_8x8[((ch - 32) * 8) + i]) >> y_pos) & 0x01) { + for (uint8_t s_w = 0; s_w < font_size; s_w++) { + for (uint8_t s_h = 0; s_h < font_size; s_h++) { + + uint16_t pix_x = current_col + s_w; + uint16_t pix_y = y + (y_pos * font_size) + s_h; + + pixel_set_cb(screen, pix_x, pix_y, color); + } + } + } else { + for (uint8_t s_w = 0; s_w < font_size; s_w++) { + for (uint8_t s_h = 0; s_h < font_size; s_h++) { + uint16_t pix_x = current_col + s_w; + uint16_t pix_y = y + (y_pos * font_size) + s_h; + + pixel_set_cb(screen, pix_x, pix_y, !color); + } + } + } + } + } +} + +STATIC mp_obj_t graphics_draw_text(size_t n_args, const mp_obj_t *args) { + display_t * screen = MP_OBJ_TO_PTR(args[0]); + + const char *str = mp_obj_str_get_str(args[1]); + mp_int_t x = mp_obj_get_int(args[2]); + mp_int_t y = mp_obj_get_int(args[3]); + mp_int_t color = 0; + if (n_args >= 4) { + color = mp_obj_get_int(args[4]); + } + + uint8_t font_size = 1; + + uint16_t str_len = strlen(str); + for (uint16_t i = 0; i < str_len; i++) { + graphics_draw_char(screen, x + (i * 8 * font_size), y, str[i], color, font_size); + } + + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(graphics_draw_text_obj, 4, 5, graphics_draw_text); + +/// \method rectangle(display, x0, y0, x1, y1, color, [fill]) +STATIC mp_obj_t draw_rectangle(mp_uint_t n_args, const mp_obj_t *args) { + display_t * screen = MP_OBJ_TO_PTR(args[0]); + mp_uint_t x0 = mp_obj_get_int(args[1]); + mp_uint_t y0 = mp_obj_get_int(args[2]); + mp_uint_t x1 = mp_obj_get_int(args[3]); + mp_uint_t y1 = mp_obj_get_int(args[4]); + mp_uint_t color = mp_obj_get_int(args[5]); + + pixel_set_callback_t pixel_set_cb = screen->draw_callbacks.pixel_set; + + // horizontals + for (mp_uint_t hpos = x0; hpos <= x1; hpos++) { + pixel_set_cb(screen, hpos, y0, color); + pixel_set_cb(screen, hpos, y1, color); + } + // verticals + for (mp_uint_t vpos = y0; vpos <= y1; vpos++) { + pixel_set_cb(screen, x0, vpos, color); + pixel_set_cb(screen, x1, vpos, color); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(graphics_draw_rectangle_obj, 6, 7, draw_rectangle); + + +STATIC const mp_map_elem_t graphics_globals_dict_table[] = { + // class methods + { MP_OBJ_NEW_QSTR(MP_QSTR_circle), (mp_obj_t)&graphics_draw_circle_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)&graphics_draw_text_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_rectangle), (mp_obj_t)&graphics_draw_rectangle_obj }, +}; + +STATIC MP_DEFINE_CONST_DICT(graphics_globals_dict, graphics_globals_dict_table); + +const mp_obj_module_t graphics_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&graphics_globals_dict, +}; diff --git a/nrf5/drivers/graphic/draw.h b/nrf5/drivers/graphic/draw.h new file mode 100644 index 0000000000..79419c6862 --- /dev/null +++ b/nrf5/drivers/graphic/draw.h @@ -0,0 +1,26 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + From b609ce85b58b667bf562b6040ce66e3d252784b8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:31:22 +0100 Subject: [PATCH 196/809] nrf5: Adding configuration defines for the graphics module (draw) and enabling this by default if using oled ssd1306 display which has a compatible python object definition. --- nrf5/mpconfigport.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 0b78313cf7..bebc429fc1 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -145,6 +145,8 @@ #define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) +#define MICROPY_PY_LCD_MONO_FB (0) +#define MICROPY_PY_DISPLAY_FRAMEBUFFER (0) #elif MICROPY_PY_DISPLAY @@ -170,6 +172,11 @@ #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #endif +#if MICROPY_PY_DISPLAY_OLED_SSD1306 +#define MICROPY_PY_DISPLAY_FRAMEBUFFER (1) +#define MICROPY_PY_DISPLAY_GRAPHICS (1) +#endif + #endif // MICROPY_PY_DISPLAY #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) @@ -205,6 +212,7 @@ extern const struct _mp_obj_module_t mp_module_usocket; extern const struct _mp_obj_module_t mp_module_network; extern const struct _mp_obj_module_t mp_module_lcd_mono_fb; extern const struct _mp_obj_module_t mp_module_display; +extern const struct _mp_obj_module_t graphics_module; #if MICROPY_PY_USOCKET #define SOCKET_BUILTIN_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_usocket), (mp_obj_t)&mp_module_usocket }, @@ -232,6 +240,13 @@ extern const struct _mp_obj_module_t mp_module_display; #define DISPLAY_MODULE #endif +#if MICROPY_PY_DISPLAY_GRAPHICS +#define GRAPHICS_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_draw), (mp_obj_t)&graphics_module }, +#else +#define GRAPHICS_MODULE +#endif + + #if BLUETOOTH_SD extern const struct _mp_obj_module_t ble_module; #define MICROPY_PORT_BUILTIN_MODULES \ @@ -245,6 +260,7 @@ extern const struct _mp_obj_module_t ble_module; NETWORK_BUILTIN_MODULE \ LCD_MONO_FB_MODULE \ DISPLAY_MODULE \ + GRAPHICS_MODULE \ #else @@ -256,6 +272,7 @@ extern const struct _mp_obj_module_t ble_module; { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ LCD_MONO_FB_MODULE \ DISPLAY_MODULE \ + GRAPHICS_MODULE \ #endif // BLUETOOTH_SD From 13161d0eaca4a11387696b19119f63d9225da922 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:32:11 +0100 Subject: [PATCH 197/809] nrf5/drivers: Adding defines to exclude implementation of draw.c module if not enabled. --- nrf5/drivers/graphic/draw.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/drivers/graphic/draw.c b/nrf5/drivers/graphic/draw.c index 114d0288c0..3dfb60a5b6 100644 --- a/nrf5/drivers/graphic/draw.c +++ b/nrf5/drivers/graphic/draw.c @@ -33,6 +33,8 @@ #include "moddisplay.h" #include "font_petme128_8x8.h" +#if MICROPY_PY_DISPLAY_GRAPHICS + /// \method circle(display, radius, x, y, color, [fill]) /// Draw a circle in the display framebuffer. STATIC mp_obj_t draw_circle(mp_uint_t n_args, const mp_obj_t *args) { @@ -183,3 +185,5 @@ const mp_obj_module_t graphics_module = { .base = { &mp_type_module }, .globals = (mp_obj_dict_t*)&graphics_globals_dict, }; + +#endif // MICROPY_PY_DISPLAY_GRAPHICS From 1bbbb9dcae58d24f47cb52929f7e618dd1c6c9d1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:32:59 +0100 Subject: [PATCH 198/809] nrf5: Enable display/framebuffer.c and graphic/draw.c into the build. --- nrf5/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 924a32b402..3cc3af24c7 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -162,6 +162,8 @@ DRIVERS_SRC_C += $(addprefix drivers/,\ display/lcd_ili9341_driver.c \ display/oled_ssd1306_obj.c \ display/oled_ssd1306_driver.c \ + display/framebuffer.c \ + graphic/draw.c \ ) #ifeq ($(SD), ) From 7edea7848d759b3e789a4004c9e5b6cc586a8e13 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:34:52 +0100 Subject: [PATCH 199/809] nrf51/boards: Enable display driver and oled ssd1306 (also bringing in framebuffer and graphics module) into the pca10028 target. --- nrf5/boards/pca10028/mpconfigboard.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 01dcda767f..b5ba1afc2c 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -30,8 +30,10 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" -#define MICROPY_PY_DISPLAY (0) -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) +#define MICROPY_PY_DISPLAY (1) +#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) +#define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) #define MICROPY_PY_MACHINE_SPI (1) #define MICROPY_PY_MACHINE_PWM (0) From c6fc0a134ca5ba76c16f95b2ef65151e14a472dd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:37:53 +0100 Subject: [PATCH 200/809] nrf51/boards: Increasing heap and stack size in the pca10028 board. --- nrf5/boards/nrf51822_ac.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/boards/nrf51822_ac.ld b/nrf5/boards/nrf51822_ac.ld index 2c591cd2f2..28f8068420 100644 --- a/nrf5/boards/nrf51822_ac.ld +++ b/nrf5/boards/nrf51822_ac.ld @@ -13,8 +13,8 @@ MEMORY } /* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 2K; -_minimum_heap_size = 20K; +_minimum_stack_size = 4K; +_minimum_heap_size = 24K; /* top end of the stack */ @@ -23,6 +23,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20005000; /* tunable */ +_heap_end = 0x20006000; /* tunable */ INCLUDE "boards/common.ld" From 73be85dd6d7d1dfd8f450bd00cbf96f67f95be02 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:39:57 +0100 Subject: [PATCH 201/809] nrf52/boards: Increasing the stack and heap in pca10056 (nrf52840) target from 2k/32k to 40k/128k to debug some buffer problems when running large frozen python programs. --- nrf5/boards/nrf52840_aa.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/boards/nrf52840_aa.ld b/nrf5/boards/nrf52840_aa.ld index 96365f54eb..43b4458315 100644 --- a/nrf5/boards/nrf52840_aa.ld +++ b/nrf5/boards/nrf52840_aa.ld @@ -12,8 +12,8 @@ MEMORY } /* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 2K; -_minimum_heap_size = 32K; +_minimum_stack_size = 40K; +_minimum_heap_size = 128K; /* top end of the stack */ @@ -22,6 +22,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20008000; /* tunable */ +_heap_end = 0x20020000; /* tunable */ INCLUDE "boards/common.ld" From b0a730d48218be937fba665588484fde322d1030 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:47:13 +0100 Subject: [PATCH 202/809] nrf5/examples: Adding 2048 game using OLED SSD1306 128x64 display and analog joystick. --- nrf5/examples/game2048.py | 348 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 348 insertions(+) create mode 100644 nrf5/examples/game2048.py diff --git a/nrf5/examples/game2048.py b/nrf5/examples/game2048.py new file mode 100644 index 0000000000..2533dc06de --- /dev/null +++ b/nrf5/examples/game2048.py @@ -0,0 +1,348 @@ +# This file is part of the Micro Python project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2017 Glenn Ruben Bakke +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +''' +Usage: + +from game2048 import Game +g = Game() +g.start() + +''' + +from machine import ADC +from machine import Pin, SPI +from display import SSD1306 +import draw +import time + +font_128 = [ + " x xx xx", + " xx x x x x", + "x x x x x", + " x x xx", + " x x x x", + " x x x x", + " xxx xxxx xx" +] + +font_256 = [ + " xx xxxx xx", + "x x x x x", + " x xxx x ", + " x x xxxx", + " x x x x", + "x x x x", + "xxxx xxx xx" +] + +font_512 = [ + "xxxx x xx", + "x xx x x", + "xxx x x x", + " x x x", + " x x x", + " x x x", + "xxx xxx xxxx" +] + +font_1024 = [ + " xx x x x x", + "x x x x x x x x", + " x x x x x x", + " x x x x xxx", + " x x x x x", + " x x x x x", + " x x xxx x" +] + +font_2048 = [ + " x x x x x", + "x x x x x x x x", + " x x x x x x x", + " x x x xxx x", + "x x x x x x", + "x x x x x x", + "xxx x x x" +] + +DIR_UP = const(0x1) +DIR_DOWN = const(0x2) +DIR_LEFT = const(0x3) +DIR_RIGHT = const(0x4) +DIR_CENTER = const(0x5) + +class Game: + def __init__(self): + +# # setup harware for nrf51822 / pca10028 +# cs = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) +# reset = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) +# dc = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) +# spi = SPI(0, baudrate=8000000) +# self.screen = SSD1306(128, 64, spi, cs, dc, reset) +# self.x_adc = ADC(2) +# self.y_adc = ADC(3) +# self.adc_threshold = 205 + + # setup harware for nrf52840 / pca10056 + cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) + reset = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) + dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) + spi = SPI(0, baudrate=8000000) + self.screen = SSD1306(128, 64, spi, cs, dc, reset) + self.x_adc = ADC(1) + self.y_adc = ADC(2) + self.adc_threshold = 130 + + # game setup + self.grid = [[0, 0, 0, 0], [0, 0, 0, 0], [0, 0, 0, 0], [0, 0, 0, 0]] + self._rand = 1337 + self.not_game_over = True + self.score = 0 + + + def move(self, dir): + if (dir == DIR_UP): + # float up + for col in range(0, 4): + for row1 in range(1, 5): + for row0 in range(1, row1): + if self.grid[col][row0 - 1] == 0: + if self.grid[col][row0]: + self.grid[col][row0 - 1] = self.grid[col][row0] + self.grid[col][row0] = 0 + # collapse + for col in range(0, 4): + for row0 in range(0, 3): + if self.grid[col][row0] == self.grid[col][row0 + 1]: + self.grid[col][row0] += self.grid[col][row0] + self.score += self.grid[col][row0] + self.grid[col][row0 + 1] = 0 + # float up + for col in range(0, 4): + for row1 in range(1, 5): + for row0 in range(1, row1): + if self.grid[col][row0 - 1] == 0: + if self.grid[col][row0]: + self.grid[col][row0 - 1] = self.grid[col][row0] + self.grid[col][row0] = 0 + elif (dir == DIR_DOWN): + # float down + for col in range(0, 4): + for row1 in range(1, 5): + for row0 in range(row1, 4): + if self.grid[col][row0] == 0: + if self.grid[col][row0 - 1]: + self.grid[col][row0] = self.grid[col][row0 - 1] + self.grid[col][row0 - 1] = 0 + # collapse + for col in range(0, 4): + for row0 in range(1, 4): + if self.grid[col][row0] == self.grid[col][row0 - 1]: + self.grid[col][row0] += self.grid[col][row0] + self.score += self.grid[col][row0] + self.grid[col][row0 - 1] = 0 + # float down + for col in range(0, 4): + for row1 in range(1, 5): + for row0 in range(row1, 4): + if self.grid[col][row0] == 0: + if self.grid[col][row0 - 1]: + self.grid[col][row0] = self.grid[col][row0 - 1] + self.grid[col][row0 - 1] = 0 + elif (dir == DIR_LEFT): + # float left + for row in range(0, 4): + for col1 in range(1, 5): + for col0 in range(1, col1): + if self.grid[col0 - 1][row] == 0: + if self.grid[col0][row]: + self.grid[col0 - 1][row] = self.grid[col0][row] + self.grid[col0][row] = 0 + # collapse + for row in range(0, 4): + for col0 in range(0, 3): + if self.grid[col0][row] == self.grid[col0 + 1][row]: + self.grid[col0][row] += self.grid[col0][row] + self.score += self.grid[col0][row] + self.grid[col0 + 1][row] = 0 + # float left + for row in range(0, 4): + for col1 in range(1, 5): + for col0 in range(1, col1): + if self.grid[col0 - 1][row] == 0: + if self.grid[col0][row]: + self.grid[col0 - 1][row] = self.grid[col0][row] + self.grid[col0][row] = 0 + elif (dir == DIR_RIGHT): + # float right + for row in range(0, 4): + for col1 in range(1, 5): + for col0 in range(col1, 4): + if self.grid[col0][row] == 0: + if self.grid[col0 - 1][row]: + self.grid[col0][row] = self.grid[col0 - 1][row] + self.grid[col0 - 1][row] = 0 + # collapse + for row in range(0, 4): + for col0 in range(1, 4): + if self.grid[col0][row] == self.grid[col0 - 1][row]: + self.grid[col0][row] += self.grid[col0][row] + self.score += self.grid[col0][row] + self.grid[col0 - 1][row] = 0 + # float right + for row in range(0, 4): + for col1 in range(1, 5): + for col0 in range(col1, 4): + if self.grid[col0][row] == 0: + if self.grid[col0 - 1][row]: + self.grid[col0][row] = self.grid[col0 - 1][row] + self.grid[col0 - 1][row] = 0 + def set_val(self, x, y, val): + self.grid[x][y] = val + def get_val(self, x, y): + return self.grid[x][y] + def draw_high_number(self, font, x, y): + for rel_y, line in enumerate(font): + for rel_x in range(0, len(line)): + if (line[rel_x] == 'x'): + self.screen.pixel(x + rel_x, y + rel_y, 1) + def draw_tile(self, x, y): + val = self.get_val(x, y) + if val != 0: + x0 = x * 16 + y0 = y * 16 + if (val < 16): + draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) + draw.text(self.screen, str(val), x0 + 4, y0 + 4, 1) + elif val == 16: + draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) + draw.text(self.screen, "1", x0 + 1, y0 + 4, 1) + draw.text(self.screen, "6", x0 + 7, y0 + 4, 1) + elif val == 32: + draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) + draw.text(self.screen, "3", x0 + 1, y0 + 4, 1) + draw.text(self.screen, "2", x0 + 7, y0 + 4, 1) + elif val == 64: + draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) + draw.text(self.screen, "6", x0 + 1, y0 + 4, 1) + draw.text(self.screen, "4", x0 + 7, y0 + 4, 1) + elif val == 128: + draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) + self.draw_high_number(font_128, x0 + 1, y0 + 4) + elif val == 256: + draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) + self.draw_high_number(font_256, x0 + 1, y0 + 4) + elif val == 512: + draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) + self.draw_high_number(font_512, x0 + 1, y0 + 4) + elif val == 1024: + draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) + self.draw_high_number(font_1024, x0 + 1, y0 + 4) + elif val == 2048: + draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) + self.draw_high_number(font_2048, x0 + 1, y0 + 4) + def read_stick_x(self): + return self.x_adc.value() + def read_stick_y(self): + return self.y_adc.value() + def wait_for_move(self): + x_val = self.read_stick_x() + y_val = self.read_stick_y() + if x_val > self.adc_threshold + 15: + return DIR_RIGHT + elif x_val < self.adc_threshold - 15: + return DIR_LEFT + if y_val > self.adc_threshold + 15: + return DIR_UP + elif y_val < self.adc_threshold - 15: + return DIR_DOWN + return DIR_CENTER + def get_free_tiles(self): + list = [] + for x in range(0, 4): + for y in range(0, 4): + if self.get_val(x, y) == 0: + list.append((x, y)) + return list + def draw_all_tiles(self): + for x in range(0, 4): + for y in range(0, 4): + self.draw_tile(x, y) + def rand(self, mod=0): + self._rand = ((214013*self._rand+2531011)>>16)&0x7FFF + if mod: + return self._rand % mod + else: + return self._rand + def add_random_tile(self): + free_tiles = self.get_free_tiles() + if free_tiles: + x,y = free_tiles[self.rand(len(free_tiles))] + new_val = 2 << self.rand(2) + self.set_val(x, y, new_val) + return True + else: + return False + def draw_score(self): + draw.text(self.screen, "Score:", 70, 10, 1) + draw.text(self.screen, str(self.score), 70, 20, 1) + def clear_grid(self): + # Because the the double array does not initialize correctly + # in micropython, we do an explicit clear + for i in range(0, 4): + for j in range(0, 4): + self.grid[i][j] = 0 + def start(self): + self.screen.fill(0) + draw.text(self.screen, "Touch the stick", 10, 20, 1) + draw.text(self.screen, " to start the", 10, 30, 1) + draw.text(self.screen, " game! =)", 10, 40, 1) + self.screen.show() + in_center = False + x_move = True + y_move = True + wait_for_center = False + self.clear_grid() + while self.not_game_over: + move_dir = self.wait_for_move() + if move_dir != DIR_CENTER and wait_for_center == False: + self.move(move_dir) + self.screen.fill(0) + res = self.add_random_tile() + if not res: + self.not_game_over = False + else: + self.draw_all_tiles() + self.draw_score() + self.screen.show() + wait_for_center = True + if move_dir == DIR_CENTER: + wait_for_center = False + self.screen.fill(0) + draw.text(self.screen, "Game Over!", 10, 20, 1) + draw.text(self.screen, "Score:", 10, 30, 1) + draw.text(self.screen, str(self.score), 10, 40, 1) + self.screen.show() \ No newline at end of file From 0380d2e781dbe418e4f8a23a204c112d692a7266 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 19:59:09 +0100 Subject: [PATCH 203/809] nrf5/examples: Adding a extra global variable to the game which breaks the game execution. --- nrf5/examples/game2048.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/examples/game2048.py b/nrf5/examples/game2048.py index 2533dc06de..4bf5b170a3 100644 --- a/nrf5/examples/game2048.py +++ b/nrf5/examples/game2048.py @@ -87,6 +87,10 @@ font_2048 = [ "xxx x x x" ] +font_4096 = [ + "x" +] + DIR_UP = const(0x1) DIR_DOWN = const(0x2) DIR_LEFT = const(0x3) From 5618be883bf82a3d5124391d2cfdf54618bb20db Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 20:32:24 +0100 Subject: [PATCH 204/809] nrf5/drivers: Adding example in comment on how to use the ili9341 driver with nrf51/pca10028 board. --- nrf5/drivers/display/lcd_ili9341_obj.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/drivers/display/lcd_ili9341_obj.c index b90de7950b..63be8f4a57 100644 --- a/nrf5/drivers/display/lcd_ili9341_obj.c +++ b/nrf5/drivers/display/lcd_ili9341_obj.c @@ -95,6 +95,18 @@ enum { }; /* + +Example for nrf51822 / pca10028: + +from machine import Pin, SPI +from display import ILI9341 +cs = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) +dc = Pin("A18", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +d = ILI9341(240, 320, spi, cs, dc) +d.text("Hello World!", 32, 32) +d.show() + Example for nrf52832 / pca10040: from machine import Pin, SPI From 8603fc833f344f5d369843926f4b771975f53034 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 22:42:49 +0100 Subject: [PATCH 205/809] nrf5: Adding micropython mem_info() to be included in mpconfigport.h. --- nrf5/mpconfigport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index bebc429fc1..17522acaf7 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -74,7 +74,7 @@ #define MICROPY_PY_BUILTINS_EXECFILE (0) #define MICROPY_PY_BUILTINS_COMPILE (1) #define MICROPY_PY_ALL_SPECIAL_METHODS (0) -#define MICROPY_PY_MICROPYTHON_MEM_INFO (0) +#define MICROPY_PY_MICROPYTHON_MEM_INFO (1) #define MICROPY_PY_ARRAY_SLICE_ASSIGN (0) #define MICROPY_PY_BUILTINS_SLICE_ATTRS (0) #define MICROPY_PY_SYS_EXIT (1) From 535f44b8bf7781ab13671c921ce22535cfa745e4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 22:46:23 +0100 Subject: [PATCH 206/809] nrf5/drivers: Updating ili9341 driver to use new framebuffer, and removing the compressed param from the line update function. --- nrf5/drivers/display/lcd_ili9341_driver.c | 22 ++++++++++------------ nrf5/drivers/display/lcd_ili9341_driver.h | 4 ++-- 2 files changed, 12 insertions(+), 14 deletions(-) diff --git a/nrf5/drivers/display/lcd_ili9341_driver.c b/nrf5/drivers/display/lcd_ili9341_driver.c index 87e193185d..adf5eac5d1 100644 --- a/nrf5/drivers/display/lcd_ili9341_driver.c +++ b/nrf5/drivers/display/lcd_ili9341_driver.c @@ -226,7 +226,7 @@ void driver_ili9341_clear(uint16_t color) mp_hal_pin_high(mp_cs_pin); } -void driver_ili9341_update_line(uint16_t line, fb_byte_t * p_bytes, uint16_t len, bool compressed) { +void driver_ili9341_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { set_col(0, 239); set_page(line, line); @@ -235,17 +235,15 @@ void driver_ili9341_update_line(uint16_t line, fb_byte_t * p_bytes, uint16_t len mp_hal_pin_high(mp_dc_pin); mp_hal_pin_low(mp_cs_pin); - if (compressed == true) { - for (uint16_t i = 0; i < len; i++) { - for (uint8_t pixel_pos = 0; pixel_pos < 8; pixel_pos++) { - uint8_t byte = (uint8_t)((uint8_t * )p_bytes)[i]; - if (((byte >> pixel_pos) & 0x1) == 0x0) { - data_write(0x00); - data_write(0x00); - } else { - data_write(0xFF); - data_write(0xFF); - } + for (uint16_t i = 0; i < len; i++) { + for (uint8_t pixel_pos = 0; pixel_pos < 8; pixel_pos++) { + uint8_t byte = (uint8_t)((uint8_t * )p_bytes)[i]; + if (((byte >> pixel_pos) & 0x1) == 0x0) { + data_write(0x00); + data_write(0x00); + } else { + data_write(0xFF); + data_write(0xFF); } } } diff --git a/nrf5/drivers/display/lcd_ili9341_driver.h b/nrf5/drivers/display/lcd_ili9341_driver.h index b420ae97ab..aa01ecfaa4 100644 --- a/nrf5/drivers/display/lcd_ili9341_driver.h +++ b/nrf5/drivers/display/lcd_ili9341_driver.h @@ -30,12 +30,12 @@ #include "py/mphal.h" #include "hal_spi.h" -#include "lcd_mono_fb.h" +#include "framebuffer.h" void driver_ili9341_init(NRF_SPI_Type * p_instance, pin_obj_t * cs_pin, pin_obj_t * dc_pin); void driver_ili9341_clear(uint16_t color); -void driver_ili9341_update_line(uint16_t line, fb_byte_t * p_bytes, uint16_t len, bool compressed); +void driver_ili9341_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); #endif // LCD_ILI9341_DRIVER_H__ From 6ab233a5baae1451c23bcb314d9d006a58566204 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 15 Jan 2017 22:47:30 +0100 Subject: [PATCH 207/809] nrf5/drivers: Updating ili9341 display object to use new framebuffer. --- nrf5/drivers/display/lcd_ili9341_obj.c | 100 +++++++++++++++++-------- 1 file changed, 70 insertions(+), 30 deletions(-) diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/drivers/display/lcd_ili9341_obj.c index 63be8f4a57..facd8b8728 100644 --- a/nrf5/drivers/display/lcd_ili9341_obj.c +++ b/nrf5/drivers/display/lcd_ili9341_obj.c @@ -38,26 +38,34 @@ /// \moduleref display /// \class ILI9341 - ILI9341 TFT LCD display driver. +#include "moddisplay.h" +#include "framebuffer.h" #include "pin.h" #include "spi.h" -#include "lcd_mono_fb.h" typedef struct _lcd_ili9341_obj_t { mp_obj_base_t base; + display_draw_callbacks_t draw_callbacks; + framebuffer_t * framebuffer; machine_hard_spi_obj_t *spi; pin_obj_t * pin_cs; pin_obj_t * pin_dc; - mp_obj_framebuf_t * framebuffer; } lcd_ili9341_obj_t; -static void dirty_line_update_cb(mp_obj_framebuf_t * p_framebuffer, - uint16_t line, - fb_byte_t * p_new, - fb_byte_t * p_old) { - // the lcd does not have double buffer needs, skip it. - (void)p_old; +#define LCD_ILI9341_COLOR_BLACK 0 +#define LCD_ILI9341_COLOR_WHITE 1 - driver_ili9341_update_line(line, p_new, p_framebuffer->bytes_stride, true); +static void set_pixel(void * p_display, + uint16_t x, + uint16_t y, + uint16_t color) { + lcd_ili9341_obj_t *self = (lcd_ili9341_obj_t *)p_display; + + if (color == LCD_ILI9341_COLOR_BLACK) { + framebuffer_pixel_clear(self->framebuffer, x, y); + } else { + framebuffer_pixel_set(self->framebuffer, x, y); + } } /// \method __str__() @@ -80,9 +88,12 @@ STATIC void lcd_ili9341_print(const mp_print_t *print, mp_obj_t o, mp_print_kind self->pin_dc->port, self->pin_dc->pin); - mp_printf(print, " FB(width=%u, height=%u, dir=%u))\n", - self->framebuffer->width, - self->framebuffer->height); + mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", + self->framebuffer->screen_width, + self->framebuffer->screen_height, + self->framebuffer->line_orientation, + self->framebuffer->fb_stride, + self->framebuffer->fb_dirty_stride); } // for make_new @@ -145,6 +156,7 @@ STATIC mp_obj_t lcd_ili9341_make_new(const mp_obj_type_t *type, size_t n_args, s lcd_ili9341_obj_t *s = m_new_obj_with_finaliser(lcd_ili9341_obj_t); s->base.type = type; + s->draw_callbacks.pixel_set = set_pixel; mp_int_t width; mp_int_t height; @@ -184,15 +196,22 @@ STATIC mp_obj_t lcd_ili9341_make_new(const mp_obj_type_t *type, size_t n_args, s "Display DC Pin not set")); } - // direction arg not yet configurable - mp_int_t vertical = true; - s->framebuffer = lcd_mono_fb_helper_make_new(width, height, vertical); + framebuffer_init_t init_conf = { + .width = width, + .height = height, + .line_orientation = FRAMEBUFFER_LINE_DIR_HORIZONTAL, + .double_buffer = false + }; + + s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); + + framebuffer_init(s->framebuffer, &init_conf); driver_ili9341_init(s->spi->pyb->spi->instance, s->pin_cs, s->pin_dc); // Default to white background - driver_ili9341_clear(0xFFFF); + driver_ili9341_clear(0x0000); - display_clear_screen(s->framebuffer, 0x1); + framebuffer_clear(s->framebuffer); return MP_OBJ_FROM_PTR(s); } @@ -204,18 +223,40 @@ STATIC mp_obj_t lcd_ili9341_make_new(const mp_obj_type_t *type, size_t n_args, s STATIC mp_obj_t lcd_ili9341_fill(mp_obj_t self_in, mp_obj_t color) { lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(self_in); - display_clear_screen(self->framebuffer, (uint8_t)mp_obj_get_int(color)); + if (color == MP_OBJ_NEW_SMALL_INT(LCD_ILI9341_COLOR_BLACK)) { + framebuffer_clear(self->framebuffer); + } else { + framebuffer_fill(self->framebuffer); + } return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_ili9341_fill_obj, lcd_ili9341_fill); +static void render(framebuffer_t * p_framebuffer) { + for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { + if (p_framebuffer->fb_dirty[i].byte != 0) { + for (uint16_t b = 0; b < 8; b++) { + if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { + uint16_t line_num = (i * 8) + b; + driver_ili9341_update_line(line_num, + &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], + p_framebuffer->fb_stride); + } + } + + p_framebuffer->fb_dirty[i].byte = 0x00; + } + } +} + /// \method show() /// Display content in framebuffer. STATIC mp_obj_t lcd_ili9341_show(size_t n_args, const mp_obj_t *args) { lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(args[0]); - display_update(self->framebuffer, false, dirty_line_update_cb); + render(self->framebuffer); + framebuffer_flip(self->framebuffer); return mp_const_none; } @@ -245,14 +286,9 @@ STATIC mp_obj_t lcd_ili9341_pixel(size_t n_args, const mp_obj_t *args) { lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(args[0]); mp_int_t x = mp_obj_get_int(args[1]); mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color; - if (n_args >= 3) { - color = mp_obj_get_int(args[3]); - } - (void)self; - (void)x; - (void)y; - (void)color; + mp_int_t color = mp_obj_get_int(args[3]); + + set_pixel(self, x, y, color); return mp_const_none; } @@ -273,8 +309,12 @@ STATIC mp_obj_t lcd_ili9341_text(size_t n_args, const mp_obj_t *args) { color = mp_obj_get_int(args[3]); } - display_print_string(self->framebuffer, x, y, str); + // display_print_string(self->framebuffer, x, y, str); + (void)x; + (void)y; + (void)self; + (void)str; (void)color; return mp_const_none; @@ -299,8 +339,8 @@ STATIC const mp_map_elem_t lcd_ili9341_locals_dict_table[] = { #if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&lcd_ili9341_bitmap_obj) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_BLACK) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_WHITE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_ILI9341_COLOR_BLACK) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_ILI9341_COLOR_WHITE) }, { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, }; From 40ee0006809ebe8f0dcf93480ed77a99e71b3fad Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 16 Jan 2017 23:34:41 +0100 Subject: [PATCH 208/809] nrf5/drivers: Adding ssd1305 oled driver. This is very similar to ssd1306, so a merge will happen soon. --- nrf5/mpconfigport.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 17522acaf7..f1166cd7f1 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -168,6 +168,11 @@ #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #endif +#if MICROPY_PY_DISPLAY_OLED_SSD1305 +#define MICROPY_PY_DISPLAY_FRAMEBUFFER (1) +#define MICROPY_PY_DISPLAY_GRAPHICS (1) +#endif + #ifndef MICROPY_PY_DISPLAY_OLED_SSD1306 #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #endif From 733040e64739e4b37110661b8673d30d3de2ecf5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 16 Jan 2017 23:37:52 +0100 Subject: [PATCH 209/809] nrf5/drivers: Adding ssd1305 oled driver. This is very similar to ssd1306, so a merge will happen soon. --- nrf5/drivers/display/moddisplay.c | 7 +- nrf5/drivers/display/oled_ssd1305_driver.c | 207 ++++++++++++ nrf5/drivers/display/oled_ssd1305_driver.h | 41 +++ nrf5/drivers/display/oled_ssd1305_obj.c | 371 +++++++++++++++++++++ nrf5/drivers/display/oled_ssd1305_obj.h | 35 ++ 5 files changed, 659 insertions(+), 2 deletions(-) create mode 100644 nrf5/drivers/display/oled_ssd1305_driver.c create mode 100644 nrf5/drivers/display/oled_ssd1305_driver.h create mode 100644 nrf5/drivers/display/oled_ssd1305_obj.c create mode 100644 nrf5/drivers/display/oled_ssd1305_obj.h diff --git a/nrf5/drivers/display/moddisplay.c b/nrf5/drivers/display/moddisplay.c index 8bd6035724..56e2bf2073 100644 --- a/nrf5/drivers/display/moddisplay.c +++ b/nrf5/drivers/display/moddisplay.c @@ -30,6 +30,7 @@ #include "epaper_sld00200p_obj.h" #include "lcd_ili9341_obj.h" +#include "oled_ssd1305_obj.h" #include "oled_ssd1306_obj.h" STATIC const mp_map_elem_t mp_module_display_globals_table[] = { @@ -40,13 +41,15 @@ STATIC const mp_map_elem_t mp_module_display_globals_table[] = { #if MICROPY_PY_DISPLAY_LCD_ILI9341 { MP_OBJ_NEW_QSTR(MP_QSTR_ILI9341), (mp_obj_t)&lcd_ili9341_type }, #endif +#if MICROPY_PY_DISPLAY_OLED_SSD1305 + { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1305), (mp_obj_t)&oled_ssd1305_type }, +#endif #if MICROPY_PY_DISPLAY_OLED_SSD1306 { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1306), (mp_obj_t)&oled_ssd1306_type }, #endif #if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1289), (mp_obj_t)&lcd_ssd1289_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_LS027b7DH01), (mp_obj_t)&lcd_ls027b7dh01_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1305), (mp_obj_t)&oled_ssd1305_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_LS027b7DH01), (mp_obj_t)&lcd_ls027b7dh01_type } #endif }; diff --git a/nrf5/drivers/display/oled_ssd1305_driver.c b/nrf5/drivers/display/oled_ssd1305_driver.c new file mode 100644 index 0000000000..95fc8f26c5 --- /dev/null +++ b/nrf5/drivers/display/oled_ssd1305_driver.c @@ -0,0 +1,207 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "py/mphal.h" + +#include "oled_ssd1305_driver.h" +#include "hal_spi.h" +#include "hal_time.h" + +#include "framebuffer.h" + +#if MICROPY_PY_DISPLAY_OLED_SSD1305 + +static pin_obj_t * mp_cs_pin; +static pin_obj_t * mp_dc_pin; +static pin_obj_t * mp_reset_pin; +static NRF_SPI_Type * mp_instance; + + +static void raw_write(uint8_t value) +{ + hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); + +} + +static void cmd_write(uint8_t value) +{ + mp_hal_pin_low(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); + + mp_hal_pin_high(mp_cs_pin); +} + +#define SET_CONTRAST (0x81) +#define SET_ENTIRE_ON (0xa4) +#define SET_NORM_INV (0xa6) +#define SET_DISP (0xae) +#define SET_MEM_ADDR (0x20) +#define SET_COL_ADDR (0x21) +#define SET_PAGE_ADDR (0x22) +#define SET_DISP_START_LINE (0x40) +#define SET_SEG_REMAP (0xa0) +#define SET_MUX_RATIO (0xa8) +#define SET_COM_OUT_DIR (0xc0) +#define SET_DISP_OFFSET (0xd3) +#define SET_COM_PIN_CFG (0xda) +#define SET_DISP_CLK_DIV (0xd5) +#define SET_PRECHARGE (0xd9) +#define SET_VCOM_DESEL (0xdb) +#define SET_CHARGE_PUMP (0x8d) + +void driver_ssd1305_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_obj_t * p_dc_pin, pin_obj_t * p_reset_pin) +{ + mp_instance = p_instance; + mp_cs_pin = p_cs_pin; + mp_dc_pin = p_dc_pin; + mp_reset_pin = p_reset_pin; + + mp_hal_pin_high(mp_cs_pin); + mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_high(mp_reset_pin); + + // power on display + mp_hal_pin_high(mp_reset_pin); + mp_hal_delay_ms(1); + mp_hal_pin_low(mp_reset_pin); + mp_hal_delay_ms(10); + mp_hal_pin_high(mp_reset_pin); + + // Turn off + cmd_write(SET_DISP | 0x00); // off + + // address setting + cmd_write(SET_MEM_ADDR); + cmd_write(0x00); // horizontal + + // resolution and layout + cmd_write(SET_DISP_START_LINE | 0x00); + cmd_write(SET_SEG_REMAP | 0x00); // column addr 127 mapped to SEG0 + cmd_write(SET_MUX_RATIO); + + uint16_t height = 64; // TODO: configurable + cmd_write(height - 1); // height - 1 + cmd_write(SET_COM_OUT_DIR | 0x08); // scan from COM[N] to COM0 + cmd_write(SET_DISP_OFFSET); + cmd_write(0x00); + cmd_write(SET_COM_PIN_CFG); + if (height == 32) { + cmd_write(0x02); + } else { + cmd_write(0x12); + } + // timing and driving scheme + cmd_write(SET_DISP_CLK_DIV); + cmd_write(0x80); + cmd_write(SET_PRECHARGE); + bool external_vcc = false; + if (external_vcc == true) { + cmd_write(0x22); + } else { + cmd_write(0xf1); + } + cmd_write(SET_VCOM_DESEL); + cmd_write(0x30); // 0.83*Vcc + // display + cmd_write(SET_CONTRAST); + cmd_write(0xff); // maximum + cmd_write(SET_ENTIRE_ON); // output follows RAM contents + cmd_write(SET_NORM_INV); // not inverted + // charge pump + cmd_write(SET_CHARGE_PUMP); + if (external_vcc == true) { + cmd_write(0x10); + } else { + cmd_write(0x14); + } + // on + cmd_write(SET_DISP | 0x01); +} + +static void set_col(uint16_t start_col, uint16_t end_col) +{ + cmd_write(SET_COL_ADDR); // column command address + cmd_write(start_col & 0xFF ); + cmd_write(end_col & 0xFF); +} + +static void set_page(uint16_t start_page, uint16_t end_page) +{ + cmd_write(SET_PAGE_ADDR); // page command address + cmd_write(start_page & 0xFF); + cmd_write(end_page & 0xFF); +} + +void driver_ssd1305_clear(uint16_t color) +{ + uint16_t width = 128; + uint16_t height = 64; + + uint16_t x0 = 0; + uint16_t x1 = width - 1; + uint16_t y0 = 0; + uint16_t y1 = height -1; + + if (width == 64) { + // displays with width of 64 pixels are shifted by 32 + x0 += 32; + x1 += 32; + } + + uint16_t num_of_pages = height / 8; + set_col(x0, x1); + set_page(y0, y1); + + mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + for (uint16_t i = 0; i < (width * num_of_pages); i++) { + raw_write(color); + } + + mp_hal_pin_high(mp_cs_pin); +} + +void driver_ssd1305_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { + set_col(line, line); + set_page(0, 63); + + mp_hal_pin_high(mp_dc_pin); + mp_hal_pin_low(mp_cs_pin); + + for (uint8_t i = 0; i < len; i++) { + uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; + raw_write(byte); + } + + mp_hal_pin_high(mp_cs_pin); +} + +#endif diff --git a/nrf5/drivers/display/oled_ssd1305_driver.h b/nrf5/drivers/display/oled_ssd1305_driver.h new file mode 100644 index 0000000000..5a030b7a87 --- /dev/null +++ b/nrf5/drivers/display/oled_ssd1305_driver.h @@ -0,0 +1,41 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OLED_SSD1305_DRIVER_H__ +#define OLED_SSD1305_DRIVER_H__ + +#include "py/mphal.h" + +#include "hal_spi.h" +#include "framebuffer.h" + +void driver_ssd1305_init(NRF_SPI_Type * p_instance, pin_obj_t * cs_pin, pin_obj_t * dc_pin, pin_obj_t * reset_pin); + +void driver_ssd1305_clear(uint16_t color); + +void driver_ssd1305_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); + +#endif // OLED_SSD1305_DRIVER_H__ diff --git a/nrf5/drivers/display/oled_ssd1305_obj.c b/nrf5/drivers/display/oled_ssd1305_obj.c new file mode 100644 index 0000000000..84874b6e70 --- /dev/null +++ b/nrf5/drivers/display/oled_ssd1305_obj.c @@ -0,0 +1,371 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "genhdr/pins.h" + +#include "oled_ssd1305_driver.h" + +#if MICROPY_PY_DISPLAY_OLED_SSD1305 + +/// \moduleref display +/// \class SSD1305 - SSD1305 TFT LCD display driver. + +#include "moddisplay.h" +#include "framebuffer.h" +#include "pin.h" +#include "spi.h" + +typedef struct _oled_ssd1305_obj_t { + mp_obj_base_t base; + display_draw_callbacks_t draw_callbacks; + framebuffer_t * framebuffer; + machine_hard_spi_obj_t *spi; + pin_obj_t * pin_cs; + pin_obj_t * pin_dc; + pin_obj_t * pin_reset; +} oled_ssd1305_obj_t; + +#define OLED_SSD1305_COLOR_BLACK 0 +#define OLED_SSD1305_COLOR_WHITE 1 + +static void set_pixel(void * p_display, + uint16_t x, + uint16_t y, + uint16_t color) { + oled_ssd1305_obj_t *self = (oled_ssd1305_obj_t *)p_display; + + if (color == OLED_SSD1305_COLOR_BLACK) { + framebuffer_pixel_clear(self->framebuffer, x, y); + } else { + framebuffer_pixel_set(self->framebuffer, x, y); + } +} + +/// \method __str__() +/// Return a string describing the SSD1305 object. +STATIC void oled_ssd1305_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + oled_ssd1305_obj_t *self = o; + + mp_printf(print, "SSD1305(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", + self->spi->pyb->spi->init.mosi_pin_port, + self->spi->pyb->spi->init.mosi_pin, + self->spi->pyb->spi->init.miso_pin_port, + self->spi->pyb->spi->init.miso_pin, + self->spi->pyb->spi->init.clk_pin_port, + self->spi->pyb->spi->init.clk_pin + ); + + mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u), reset=(port=%u, pin=%u),\n", + self->pin_cs->port, + self->pin_cs->pin, + self->pin_dc->port, + self->pin_dc->pin, + self->pin_reset->port, + self->pin_reset->pin); + + mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", + self->framebuffer->screen_width, + self->framebuffer->screen_height, + self->framebuffer->line_orientation, + self->framebuffer->fb_stride, + self->framebuffer->fb_dirty_stride); +} + +// for make_new +enum { + ARG_NEW_WIDTH, + ARG_NEW_HEIGHT, + ARG_NEW_SPI, + ARG_NEW_CS, + ARG_NEW_DC, + ARG_NEW_RESET +}; + +/* + +Example for nrf51822 / pca10028: + +from machine import Pin, SPI +from display import SSD1305 +cs = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) +dc = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +d = SSD1305(128, 64, spi, cs, dc, reset) +d.text("Hello World!", 32, 32) +d.show() + +Example for nrf52832 / pca10040: + +from machine import Pin, SPI +from display import SSD1305 +cs = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) +dc = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +d = SSD1305(128, 64, spi, cs, dc, reset) +d.text("Hello World!", 32, 32) +d.show() + +Example for nrf52840 / pca10056: + +from machine import Pin, SPI +from display import SSD1305 +cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) +dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +d = SSD1305(128, 64, spi, cs, dc, reset) +d.text("Hello World!", 32, 32) +d.show() + +*/ +STATIC mp_obj_t oled_ssd1305_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_DC, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + oled_ssd1305_obj_t *s = m_new_obj_with_finaliser(oled_ssd1305_obj_t); + s->base.type = type; + s->draw_callbacks.pixel_set = set_pixel; + + mp_int_t width; + mp_int_t height; + + if (args[ARG_NEW_WIDTH].u_int > 0) { + width = args[ARG_NEW_WIDTH].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display width not set")); + } + + if (args[ARG_NEW_HEIGHT].u_int > 0) { + height = args[ARG_NEW_HEIGHT].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display height not set")); + } + + if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { + s->spi = args[ARG_NEW_SPI].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display SPI not set")); + } + + if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { + s->pin_cs = args[ARG_NEW_CS].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display CS Pin not set")); + } + + if (args[ARG_NEW_DC].u_obj != MP_OBJ_NULL) { + s->pin_dc = args[ARG_NEW_DC].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display DC Pin not set")); + } + + if (args[ARG_NEW_RESET].u_obj != MP_OBJ_NULL) { + s->pin_reset = args[ARG_NEW_RESET].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Reset Pin not set")); + } + + framebuffer_init_t init_conf = { + .width = width, + .height = height, + .line_orientation = FRAMEBUFFER_LINE_DIR_VERTICAL, + .double_buffer = false + }; + + s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); + + framebuffer_init(s->framebuffer, &init_conf); + + driver_ssd1305_init(s->spi->pyb->spi->instance, s->pin_cs, s->pin_dc, s->pin_reset); + // Default to black background + driver_ssd1305_clear(0); + + framebuffer_clear(s->framebuffer); + + return MP_OBJ_FROM_PTR(s); +} + +// text + +/// \method fill(color) +/// Fill framebuffer with the color defined as argument. +STATIC mp_obj_t oled_ssd1305_fill(mp_obj_t self_in, mp_obj_t color) { + oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (color == MP_OBJ_NEW_SMALL_INT(OLED_SSD1305_COLOR_BLACK)) { + framebuffer_clear(self->framebuffer); + } else { + framebuffer_fill(self->framebuffer); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(oled_ssd1305_fill_obj, oled_ssd1305_fill); + +static void render(framebuffer_t * p_framebuffer) { + for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { + if (p_framebuffer->fb_dirty[i].byte != 0) { + for (uint16_t b = 0; b < 8; b++) { + if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { + uint16_t line_num = (i * 8) + b; + driver_ssd1305_update_line(line_num, + &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], + p_framebuffer->fb_stride); + } + } + + p_framebuffer->fb_dirty[i].byte = 0x00; + } + } +} + +/// \method show() +/// Display content in framebuffer. +STATIC mp_obj_t oled_ssd1305_show(size_t n_args, const mp_obj_t *args) { + oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(args[0]); + + render(self->framebuffer); + framebuffer_flip(self->framebuffer); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1305_show_obj, 1, 2, oled_ssd1305_show); + +/// \method refresh([num_of_refresh]) +/// Refresh content in framebuffer. +/// +/// - With no argument, 1 refresh will be done. +/// - With `num_of_refresh` given, The whole framebuffer will be considered +/// dirty and will be refreshed the given number of times. +STATIC mp_obj_t oled_ssd1305_refresh(mp_obj_t self_in) { + oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(oled_ssd1305_refresh_obj, oled_ssd1305_refresh); + +/// \method pixel(x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color of the pixel in framebuffer will be returend. +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t oled_ssd1305_pixel(size_t n_args, const mp_obj_t *args) { + oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t x = mp_obj_get_int(args[1]); + mp_int_t y = mp_obj_get_int(args[2]); + mp_int_t color = mp_obj_get_int(args[3]); + + set_pixel(self, x, y, color); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1305_pixel_obj, 4, 4, oled_ssd1305_pixel); + +/// \method pixel(text, x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color will be the opposite of background (fill color). +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t oled_ssd1305_text(size_t n_args, const mp_obj_t *args) { + oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(args[0]); + const char *str = mp_obj_str_get_str(args[1]); + mp_int_t x = mp_obj_get_int(args[2]); + mp_int_t y = mp_obj_get_int(args[3]); + mp_int_t color; + if (n_args >= 4) { + color = mp_obj_get_int(args[3]); + } + + //display_print_string(self->framebuffer, x, y, str); + + (void)x; + (void)y; + (void)self; + (void)str; + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1305_text_obj, 4, 5, oled_ssd1305_text); + +STATIC mp_obj_t oled_ssd1305_del(mp_obj_t self_in) { + oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(oled_ssd1305_del_obj, oled_ssd1305_del); + +STATIC const mp_map_elem_t oled_ssd1305_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&oled_ssd1305_del_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&oled_ssd1305_fill_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&oled_ssd1305_show_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&oled_ssd1305_text_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&oled_ssd1305_pixel_obj) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&oled_ssd1305_bitmap_obj) }, +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(OLED_SSD1305_COLOR_BLACK) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(OLED_SSD1305_COLOR_WHITE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, +}; + +STATIC MP_DEFINE_CONST_DICT(oled_ssd1305_locals_dict, oled_ssd1305_locals_dict_table); + +const mp_obj_type_t oled_ssd1305_type = { + { &mp_type_type }, + .name = MP_QSTR_SSD1305, + .print = oled_ssd1305_print, + .make_new = oled_ssd1305_make_new, + .locals_dict = (mp_obj_t)&oled_ssd1305_locals_dict +}; + +#endif // MICROPY_PY_DISPLAY_OLED_SSD1305 diff --git a/nrf5/drivers/display/oled_ssd1305_obj.h b/nrf5/drivers/display/oled_ssd1305_obj.h new file mode 100644 index 0000000000..23a9f935db --- /dev/null +++ b/nrf5/drivers/display/oled_ssd1305_obj.h @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OLED_SSD1305_H__ +#define OLED_SSD1305_H__ + +#include + +extern const mp_obj_type_t oled_ssd1305_type; + +#endif // OLED_SSD1305_H__ + From 00a59ed8d69457dcf5ee31bd0cad7e85a3ee9bd9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 16 Jan 2017 23:39:50 +0100 Subject: [PATCH 210/809] nrf5/boards: Enable ssd1305 oled display to be default for pca10028 for now. --- nrf5/boards/pca10028/mpconfigboard.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index b5ba1afc2c..c4eab19cf1 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -33,7 +33,8 @@ #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) +#define MICROPY_PY_DISPLAY_OLED_SSD1305 (1) +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #define MICROPY_PY_MACHINE_SPI (1) #define MICROPY_PY_MACHINE_PWM (0) From 174562f95b1ca3ad6bf58a22c7ebc314991729cf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 17 Jan 2017 00:36:48 +0100 Subject: [PATCH 211/809] nrf5: Adding configuration define for sharp memory display series in mpconfigport.h preparing for driver to be included. --- nrf5/mpconfigport.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index f1166cd7f1..a3f45bad2a 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -143,6 +143,7 @@ #define MICROPY_PY_DISPLAY (0) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) +#define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (0) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #define MICROPY_PY_LCD_MONO_FB (0) @@ -164,6 +165,15 @@ #define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) #endif +#ifndef MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX +#define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (0) +#endif + +#if MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX +#define MICROPY_PY_DISPLAY_FRAMEBUFFER (1) +#define MICROPY_PY_DISPLAY_GRAPHICS (1) +#endif + #ifndef MICROPY_PY_DISPLAY_OLED_SSD1305 #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #endif From 16489fced250f1e5bfaef7648de696f3c96eab56 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 17 Jan 2017 23:15:30 +0100 Subject: [PATCH 212/809] nrf5/drivers: Adding sharp memory display driver. For now hardcoded to 2.7 inch variant. --- nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c | 111 +++++ nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.h | 47 +++ nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c | 392 ++++++++++++++++++ nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.h | 35 ++ 4 files changed, 585 insertions(+) create mode 100644 nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c create mode 100644 nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.h create mode 100644 nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c create mode 100644 nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.h diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c b/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c new file mode 100644 index 0000000000..0fbd18cf1b --- /dev/null +++ b/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c @@ -0,0 +1,111 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "py/mphal.h" + +#include "lcd_ls0xxb7dxxx_driver.h" +#include "hal_spi.h" +#include "hal_time.h" + +#include "framebuffer.h" + +#if MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX + +static pin_obj_t * mp_cs_pin; +static pin_obj_t * mp_disp_pin; +static pin_obj_t * mp_extcomin_pin; +static pin_obj_t * mp_extmode_pin; +static pin_obj_t * mp_power_control_pin; +static pin_obj_t * mp_power_charge_pin; +static NRF_SPI_Type * mp_instance; + + +static void raw_write(uint8_t value) +{ + hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); +} + +void driver_ls0xxb7dxxx_init(NRF_SPI_Type * p_instance, + pin_obj_t * p_cs_pin, + pin_obj_t * p_disp_pin, + pin_obj_t * p_ext_com_in_pin, + pin_obj_t * p_ext_mode_pin, + pin_obj_t * p_power_control_pin, + pin_obj_t * p_power_charge_pin) { + mp_instance = p_instance; + mp_cs_pin = p_cs_pin; + mp_disp_pin = p_disp_pin; + mp_extcomin_pin = p_ext_com_in_pin; + mp_extmode_pin = p_ext_mode_pin; + mp_power_control_pin = p_power_control_pin; + mp_power_charge_pin = p_power_charge_pin; + + mp_hal_pin_high(mp_extcomin_pin); + mp_hal_pin_low(mp_disp_pin); + mp_hal_pin_low(mp_cs_pin); + mp_hal_pin_low(mp_extmode_pin); + mp_hal_pin_low(mp_power_charge_pin); + mp_hal_pin_low(mp_power_control_pin); + + // power on display + mp_hal_pin_high(mp_power_charge_pin); + mp_hal_pin_high(mp_power_control_pin); + + // display on + mp_hal_pin_high(mp_disp_pin); + + mp_hal_pin_low(mp_extcomin_pin); + +} + +void driver_ls0xxb7dxxx_clear(uint16_t color) +{ + mp_hal_pin_high(mp_cs_pin); + raw_write(0x04); // clear command + raw_write(0x00); + mp_hal_pin_low(mp_cs_pin); +} + +void driver_ls0xxb7dxxx_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { + + mp_hal_pin_high(mp_cs_pin); + raw_write(0x01); + + raw_write(line); + for (uint8_t i = 0; i < len; i++) + { + uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; + raw_write(~byte); + } + raw_write(0x00); + + raw_write(0x00); + mp_hal_pin_low(mp_cs_pin); +} + +#endif diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.h b/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.h new file mode 100644 index 0000000000..380fba0b23 --- /dev/null +++ b/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.h @@ -0,0 +1,47 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LCD_LS0XXB7DXXX_DRIVER_H__ +#define LCD_LS0XXB7DXXX_DRIVER_H__ + +#include "py/mphal.h" + +#include "hal_spi.h" +#include "framebuffer.h" + +void driver_ls0xxb7dxxx_init(NRF_SPI_Type * p_instance, + pin_obj_t * p_cs_pin, + pin_obj_t * p_disp_pin, + pin_obj_t * p_ext_com_in_pin, + pin_obj_t * p_ext_mode_pin, + pin_obj_t * p_power_control_pin, + pin_obj_t * p_power_charge_pin); + +void driver_ls0xxb7dxxx_clear(uint16_t color); + +void driver_ls0xxb7dxxx_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); + +#endif // LCD_LS0XXB7DXXX_DRIVER_H__ diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c new file mode 100644 index 0000000000..a03d710663 --- /dev/null +++ b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c @@ -0,0 +1,392 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "genhdr/pins.h" + +#include "lcd_ls0xxb7dxxx_driver.h" + +#if MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX + +/// \moduleref display +/// \class LS0XXB7DXXX - LS0XXB7DXXX TFT LCD display driver. + +#include "moddisplay.h" +#include "framebuffer.h" +#include "pin.h" +#include "spi.h" + +typedef struct _lcd_ls0xxb7dxxx_obj_t { + mp_obj_base_t base; + display_draw_callbacks_t draw_callbacks; + framebuffer_t * framebuffer; + machine_hard_spi_obj_t *spi; + pin_obj_t * pin_cs; + pin_obj_t * pin_disp; + pin_obj_t * pin_extcomin; + pin_obj_t * pin_extmode; + pin_obj_t * pin_power_control; + pin_obj_t * pin_power_charge; +} lcd_ls0xxb7dxxx_obj_t; + +#define LCD_LS0XXB7DXXX_COLOR_WHITE 0 +#define LCD_LS0XXB7DXXX_COLOR_BLACK 1 + +static void set_pixel(void * p_display, + uint16_t x, + uint16_t y, + uint16_t color) { + lcd_ls0xxb7dxxx_obj_t *self = (lcd_ls0xxb7dxxx_obj_t *)p_display; + + if (color == LCD_LS0XXB7DXXX_COLOR_BLACK) { + framebuffer_pixel_clear(self->framebuffer, x, y); + } else { + framebuffer_pixel_set(self->framebuffer, x, y); + } +} + +/// \method __str__() +/// Return a string describing the LS0XXB7DXXX object. +STATIC void lcd_ls0xxb7dxxx_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + lcd_ls0xxb7dxxx_obj_t *self = o; + + mp_printf(print, "LS0XXB7DXXX(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", + self->spi->pyb->spi->init.mosi_pin_port, + self->spi->pyb->spi->init.mosi_pin, + self->spi->pyb->spi->init.clk_pin_port, + self->spi->pyb->spi->init.clk_pin + ); + + mp_printf(print, " cs=(port=%u, pin=%u), disp=(port=%u, pin=%u), extcomin=(port=%u, pin=%u),\n", + self->pin_cs->port, + self->pin_cs->pin, + self->pin_disp->port, + self->pin_disp->pin, + self->pin_extcomin->port, + self->pin_extcomin->pin); + mp_printf(print, " extmode=(port=%u, pin=%u), power_control=(port=%u, pin=%u), power_charge=(port=%u, pin=%u),\n", + self->pin_extmode->port, + self->pin_extmode->pin, + self->pin_power_control->port, + self->pin_power_control->pin, + self->pin_power_charge->port, + self->pin_power_charge->pin); + + mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", + self->framebuffer->screen_width, + self->framebuffer->screen_height, + self->framebuffer->line_orientation, + self->framebuffer->fb_stride, + self->framebuffer->fb_dirty_stride); +} + +// for make_new +enum { + ARG_NEW_WIDTH, + ARG_NEW_HEIGHT, + ARG_NEW_SPI, + ARG_NEW_CS, + ARG_NEW_DISP, + ARG_NEW_EXTCOMIN, + ARG_NEW_EXTMODE, + ARG_NEW_POWER_CONTROL, + ARG_NEW_POWER_CHARGE +}; + +/* + +Example for nrf52840 / pca10056: + +from machine import Pin, SPI +from display import LS0XXB7DXXX +cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) +disp = Pin("B4", mode=Pin.OUT, pull=Pin.PULL_UP) +extcomin = Pin("A28", mode=Pin.OUT, pull=Pin.PULL_UP) +extmode = Pin("B5", mode=Pin.OUT, pull=Pin.PULL_UP) +power_control = Pin("A29", mode=Pin.OUT, pull=Pin.PULL_UP) +power_charge = Pin("A30", mode=Pin.OUT, pull=Pin.PULL_UP) +spi = SPI(0, baudrate=8000000) +d = LS0XXB7DXXX(400, 240, spi, cs, disp, extcomin, extmode, power_control, power_charge) +d.text("Hello World!", 32, 32) +d.show() + +*/ +STATIC mp_obj_t lcd_ls0xxb7dxxx_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_DISP, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_EXTCOMIN, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_EXTMODE, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_POWER_CONTROL, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_POWER_CHARGE, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + lcd_ls0xxb7dxxx_obj_t *s = m_new_obj_with_finaliser(lcd_ls0xxb7dxxx_obj_t); + s->base.type = type; + s->draw_callbacks.pixel_set = set_pixel; + + mp_int_t width; + mp_int_t height; + + if (args[ARG_NEW_WIDTH].u_int > 0) { + width = args[ARG_NEW_WIDTH].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display width not set")); + } + + if (args[ARG_NEW_HEIGHT].u_int > 0) { + height = args[ARG_NEW_HEIGHT].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display height not set")); + } + + if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { + s->spi = args[ARG_NEW_SPI].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display SPI not set")); + } + + if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { + s->pin_cs = args[ARG_NEW_CS].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display CS Pin not set")); + } + + if (args[ARG_NEW_DISP].u_obj != MP_OBJ_NULL) { + s->pin_disp = args[ARG_NEW_DISP].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Disp Pin not set")); + } + + if (args[ARG_NEW_EXTCOMIN].u_obj != MP_OBJ_NULL) { + s->pin_extcomin = args[ARG_NEW_EXTCOMIN].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display ExtComIn Pin not set")); + } + + if (args[ARG_NEW_EXTMODE].u_obj != MP_OBJ_NULL) { + s->pin_extmode = args[ARG_NEW_EXTMODE].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display ExtMode Pin not set")); + } + + if (args[ARG_NEW_POWER_CONTROL].u_obj != MP_OBJ_NULL) { + s->pin_power_control = args[ARG_NEW_POWER_CONTROL].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display PowerControl Pin not set")); + } + + if (args[ARG_NEW_POWER_CHARGE].u_obj != MP_OBJ_NULL) { + s->pin_power_charge = args[ARG_NEW_POWER_CHARGE].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display PowerCharge Pin not set")); + } + + framebuffer_init_t init_conf = { + .width = width, + .height = height, + .line_orientation = FRAMEBUFFER_LINE_DIR_VERTICAL, + .double_buffer = false + }; + + s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); + + framebuffer_init(s->framebuffer, &init_conf); + + driver_ls0xxb7dxxx_init(s->spi->pyb->spi->instance, + s->pin_cs, + s->pin_disp, + s->pin_extcomin, + s->pin_extmode, + s->pin_power_control, + s->pin_power_charge); + + // Default to black background + driver_ls0xxb7dxxx_clear(0); + + framebuffer_clear(s->framebuffer); + + return MP_OBJ_FROM_PTR(s); +} + +// text + +/// \method fill(color) +/// Fill framebuffer with the color defined as argument. +STATIC mp_obj_t lcd_ls0xxb7dxxx_fill(mp_obj_t self_in, mp_obj_t color) { + lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (color == MP_OBJ_NEW_SMALL_INT(LCD_LS0XXB7DXXX_COLOR_BLACK)) { + framebuffer_clear(self->framebuffer); + } else { + framebuffer_fill(self->framebuffer); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_ls0xxb7dxxx_fill_obj, lcd_ls0xxb7dxxx_fill); + +static void render(framebuffer_t * p_framebuffer) { + for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { + if (p_framebuffer->fb_dirty[i].byte != 0) { + for (uint16_t b = 0; b < 8; b++) { + if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { + uint16_t line_num = (i * 8) + b; + driver_ls0xxb7dxxx_update_line(line_num, + &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], + p_framebuffer->fb_stride); + } + } + + p_framebuffer->fb_dirty[i].byte = 0x00; + } + } +} + +/// \method show() +/// Display content in framebuffer. +STATIC mp_obj_t lcd_ls0xxb7dxxx_show(size_t n_args, const mp_obj_t *args) { + lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(args[0]); + + render(self->framebuffer); + framebuffer_flip(self->framebuffer); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ls0xxb7dxxx_show_obj, 1, 2, lcd_ls0xxb7dxxx_show); + +/// \method refresh([num_of_refresh]) +/// Refresh content in framebuffer. +/// +/// - With no argument, 1 refresh will be done. +/// - With `num_of_refresh` given, The whole framebuffer will be considered +/// dirty and will be refreshed the given number of times. +STATIC mp_obj_t lcd_ls0xxb7dxxx_refresh(mp_obj_t self_in) { + lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ls0xxb7dxxx_refresh_obj, lcd_ls0xxb7dxxx_refresh); + +/// \method pixel(x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color of the pixel in framebuffer will be returend. +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t lcd_ls0xxb7dxxx_pixel(size_t n_args, const mp_obj_t *args) { + lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t x = mp_obj_get_int(args[1]); + mp_int_t y = mp_obj_get_int(args[2]); + mp_int_t color = mp_obj_get_int(args[3]); + + set_pixel(self, x, y, color); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ls0xxb7dxxx_pixel_obj, 4, 4, lcd_ls0xxb7dxxx_pixel); + +/// \method pixel(text, x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color will be the opposite of background (fill color). +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t lcd_ls0xxb7dxxx_text(size_t n_args, const mp_obj_t *args) { + lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(args[0]); + const char *str = mp_obj_str_get_str(args[1]); + mp_int_t x = mp_obj_get_int(args[2]); + mp_int_t y = mp_obj_get_int(args[3]); + mp_int_t color; + if (n_args >= 4) { + color = mp_obj_get_int(args[3]); + } + + //display_print_string(self->framebuffer, x, y, str); + + (void)x; + (void)y; + (void)self; + (void)str; + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ls0xxb7dxxx_text_obj, 4, 5, lcd_ls0xxb7dxxx_text); + +STATIC mp_obj_t lcd_ls0xxb7dxxx_del(mp_obj_t self_in) { + lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ls0xxb7dxxx_del_obj, lcd_ls0xxb7dxxx_del); + +STATIC const mp_map_elem_t lcd_ls0xxb7dxxx_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&lcd_ls0xxb7dxxx_del_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&lcd_ls0xxb7dxxx_fill_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&lcd_ls0xxb7dxxx_show_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&lcd_ls0xxb7dxxx_text_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&lcd_ls0xxb7dxxx_pixel_obj) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&lcd_ls0xxb7dxxx_bitmap_obj) }, +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_LS0XXB7DXXX_COLOR_BLACK) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_LS0XXB7DXXX_COLOR_WHITE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, +}; + +STATIC MP_DEFINE_CONST_DICT(lcd_ls0xxb7dxxx_locals_dict, lcd_ls0xxb7dxxx_locals_dict_table); + +const mp_obj_type_t lcd_ls0xxb7dxxx_type = { + { &mp_type_type }, + .name = MP_QSTR_LS0XXB7DXXX, + .print = lcd_ls0xxb7dxxx_print, + .make_new = lcd_ls0xxb7dxxx_make_new, + .locals_dict = (mp_obj_t)&lcd_ls0xxb7dxxx_locals_dict +}; + +#endif // MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.h b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.h new file mode 100644 index 0000000000..a1f2b3f833 --- /dev/null +++ b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.h @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LCD_LS0XXB7DXXX_H__ +#define LCD_LS0XXB7DXXX_H__ + +#include + +extern const mp_obj_type_t lcd_ls0xxb7dxxx_type; + +#endif // LCD_LS0XXB7DXXX_H__ + From ca34429617599e073a0415ef46066d379b41cfc3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 18 Jan 2017 23:01:53 +0100 Subject: [PATCH 213/809] nrf5/drivers: Tuning memory lcd driver a bit. Fixing small mp_printf usage bug. --- nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c index a03d710663..faa73daee5 100644 --- a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c +++ b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c @@ -75,7 +75,7 @@ static void set_pixel(void * p_display, STATIC void lcd_ls0xxb7dxxx_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { lcd_ls0xxb7dxxx_obj_t *self = o; - mp_printf(print, "LS0XXB7DXXX(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", + mp_printf(print, "LS0XXB7DXXX(SPI(mosi=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", self->spi->pyb->spi->init.mosi_pin_port, self->spi->pyb->spi->init.mosi_pin, self->spi->pyb->spi->init.clk_pin_port, @@ -226,7 +226,7 @@ STATIC mp_obj_t lcd_ls0xxb7dxxx_make_new(const mp_obj_type_t *type, size_t n_arg framebuffer_init_t init_conf = { .width = width, .height = height, - .line_orientation = FRAMEBUFFER_LINE_DIR_VERTICAL, + .line_orientation = FRAMEBUFFER_LINE_DIR_HORIZONTAL, .double_buffer = false }; @@ -243,7 +243,7 @@ STATIC mp_obj_t lcd_ls0xxb7dxxx_make_new(const mp_obj_type_t *type, size_t n_arg s->pin_power_charge); // Default to black background - driver_ls0xxb7dxxx_clear(0); + driver_ls0xxb7dxxx_clear(0x00); framebuffer_clear(s->framebuffer); @@ -258,9 +258,9 @@ STATIC mp_obj_t lcd_ls0xxb7dxxx_fill(mp_obj_t self_in, mp_obj_t color) { lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(self_in); if (color == MP_OBJ_NEW_SMALL_INT(LCD_LS0XXB7DXXX_COLOR_BLACK)) { - framebuffer_clear(self->framebuffer); - } else { framebuffer_fill(self->framebuffer); + } else { + framebuffer_clear(self->framebuffer); } return mp_const_none; From 4cef9cd480b91b77ece2dbcc4e50ab677e46c3ea Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 20:04:49 +0100 Subject: [PATCH 214/809] nrf5/spi: Adding posibility to configure SPI firstbit mode to LSB or MSB. Default is MSB. Updating python module and hal driver. --- nrf5/hal/hal_spi.c | 2 +- nrf5/hal/hal_spi.h | 22 +++++++++++++++------- nrf5/spi.c | 6 +++--- 3 files changed, 19 insertions(+), 11 deletions(-) diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c index 72cb716e3e..1923d425d2 100644 --- a/nrf5/hal/hal_spi.c +++ b/nrf5/hal/hal_spi.c @@ -85,7 +85,7 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi break; } - if (p_spi_init->lsb_first) { + if (p_spi_init->firstbit == HAL_SPI_LSB_FIRST) { p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_LsbFirst << SPI_CONFIG_ORDER_Pos)); } else { p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos)); diff --git a/nrf5/hal/hal_spi.h b/nrf5/hal/hal_spi.h index 852ea8b444..1513b894dc 100644 --- a/nrf5/hal/hal_spi.h +++ b/nrf5/hal/hal_spi.h @@ -73,6 +73,14 @@ typedef enum { HAL_SPI_MODE_CPOL1_CPHA1 // CPOL = 1, CPHA = 1 (data on trailing edge) } hal_spi_mode_t; +/** + * @brief SPI firstbit mode definition + */ +typedef enum { + HAL_SPI_MSB_FIRST = 0, + HAL_SPI_LSB_FIRST +} hal_spi_firstbit_t; + /** * @brief SPI Configuration Structure definition */ @@ -83,7 +91,7 @@ typedef struct { uint8_t mosi_pin_port; uint8_t miso_pin_port; uint8_t clk_pin_port; - bool lsb_first; + hal_spi_firstbit_t firstbit; hal_spi_mode_t mode; uint32_t irq_priority; hal_spi_clk_freq_t freq; @@ -94,15 +102,15 @@ typedef struct { */ typedef struct __SPI_HandleTypeDef { - NRF_SPI_Type *instance; /* SPI registers base address */ - hal_spi_init_t init; /* SPI initialization parameters */ + NRF_SPI_Type *instance; /* SPI registers base address */ + hal_spi_init_t init; /* SPI initialization parameters */ } SPI_HandleTypeDef; void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init); -void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, - uint16_t transfer_size, - const uint8_t * tx_data, - uint8_t * rx_data); +void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, + uint16_t transfer_size, + const uint8_t * tx_data, + uint8_t * rx_data); #endif // HAL_SPI_H__ diff --git a/nrf5/spi.c b/nrf5/spi.c index d61fb5b1bf..a9a31337d2 100644 --- a/nrf5/spi.c +++ b/nrf5/spi.c @@ -221,8 +221,8 @@ STATIC const mp_rom_map_elem_t machine_spi_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&mp_machine_spi_write_obj) }, { MP_ROM_QSTR(MP_QSTR_write_readinto), MP_ROM_PTR(&mp_machine_spi_write_readinto_obj) }, - { MP_ROM_QSTR(MP_QSTR_MSB), MP_ROM_INT(0) }, // SPI_FIRSTBIT_MSB - { MP_ROM_QSTR(MP_QSTR_LSB), MP_ROM_INT(1) }, // SPI_FIRSTBIT_LSB + { MP_ROM_QSTR(MP_QSTR_MSB), MP_ROM_INT(HAL_SPI_MSB_FIRST) }, // SPI_FIRSTBIT_MSB + { MP_ROM_QSTR(MP_QSTR_LSB), MP_ROM_INT(HAL_SPI_LSB_FIRST) }, // SPI_FIRSTBIT_LSB }; STATIC MP_DEFINE_CONST_DICT(machine_spi_locals_dict, machine_spi_locals_dict_table); @@ -280,7 +280,7 @@ STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) { self->pyb->spi->init.irq_priority = 4; self->pyb->spi->init.mode = HAL_SPI_MODE_CPOL0_CPHA0; - self->pyb->spi->init.lsb_first = false; + self->pyb->spi->init.firstbit = (args[ARG_NEW_firstbit].u_int == 0) ? HAL_SPI_MSB_FIRST : HAL_SPI_LSB_FIRST;; hal_spi_master_init(self->pyb->spi->instance, &self->pyb->spi->init); return MP_OBJ_FROM_PTR(self); From 158edcad2c5555ccc87dd97b9224b4ec9e999016 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 20:43:23 +0100 Subject: [PATCH 215/809] nrf5/drivers: Updating sharp memory display driver and python module to a working state. --- nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c | 10 +++++++++- nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c | 8 ++++---- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c b/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c index 0fbd18cf1b..686a626682 100644 --- a/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c +++ b/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c @@ -92,12 +92,17 @@ void driver_ls0xxb7dxxx_clear(uint16_t color) } void driver_ls0xxb7dxxx_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { + // update single line - 0x01 <50bytes data> 0x00 0x00 + // update multi line - 0x01 <50bytes data> 0x00 [ <50bytes data> 0x00] 0x00 mp_hal_pin_high(mp_cs_pin); + + mp_hal_delay_us(3); + raw_write(0x01); raw_write(line); - for (uint8_t i = 0; i < len; i++) + for (uint8_t i = 0; i < 50; i++) { uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; raw_write(~byte); @@ -105,6 +110,9 @@ void driver_ls0xxb7dxxx_update_line(uint16_t line, framebuffer_byte_t * p_bytes, raw_write(0x00); raw_write(0x00); + + mp_hal_delay_us(1); + mp_hal_pin_low(mp_cs_pin); } diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c index faa73daee5..d70ee9fbed 100644 --- a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c +++ b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c @@ -54,8 +54,8 @@ typedef struct _lcd_ls0xxb7dxxx_obj_t { pin_obj_t * pin_power_charge; } lcd_ls0xxb7dxxx_obj_t; -#define LCD_LS0XXB7DXXX_COLOR_WHITE 0 -#define LCD_LS0XXB7DXXX_COLOR_BLACK 1 +#define LCD_LS0XXB7DXXX_COLOR_BLACK 0 +#define LCD_LS0XXB7DXXX_COLOR_WHITE 1 static void set_pixel(void * p_display, uint16_t x, @@ -64,9 +64,9 @@ static void set_pixel(void * p_display, lcd_ls0xxb7dxxx_obj_t *self = (lcd_ls0xxb7dxxx_obj_t *)p_display; if (color == LCD_LS0XXB7DXXX_COLOR_BLACK) { - framebuffer_pixel_clear(self->framebuffer, x, y); - } else { framebuffer_pixel_set(self->framebuffer, x, y); + } else { + framebuffer_pixel_clear(self->framebuffer, x, y); } } From b06114dc8dabec2045656c495b53e2d979da5677 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 20:44:27 +0100 Subject: [PATCH 216/809] nrf5: Adding ssd1305 and ls0xxb7dxxx (sharp memory display) drivers to be included in build. --- nrf5/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 3cc3af24c7..d81523a1b1 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -160,6 +160,10 @@ DRIVERS_SRC_C += $(addprefix drivers/,\ display/epaper_sld00200p_driver.c \ display/lcd_ili9341_obj.c \ display/lcd_ili9341_driver.c \ + display/lcd_ls0xxb7dxxx_obj.c \ + display/lcd_ls0xxb7dxxx_driver.c \ + display/oled_ssd1305_obj.c \ + display/oled_ssd1305_driver.c \ display/oled_ssd1306_obj.c \ display/oled_ssd1306_driver.c \ display/framebuffer.c \ From 5f9c556092c38b51f391121453ec0ba3303070f4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 20:45:51 +0100 Subject: [PATCH 217/809] nrf5/drivers: Adding ls0xxb7dxx to display module. --- nrf5/drivers/display/moddisplay.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/display/moddisplay.c b/nrf5/drivers/display/moddisplay.c index 56e2bf2073..1e14c4a449 100644 --- a/nrf5/drivers/display/moddisplay.c +++ b/nrf5/drivers/display/moddisplay.c @@ -30,6 +30,7 @@ #include "epaper_sld00200p_obj.h" #include "lcd_ili9341_obj.h" +#include "lcd_ls0xxb7dxxx_obj.h" #include "oled_ssd1305_obj.h" #include "oled_ssd1306_obj.h" @@ -41,6 +42,9 @@ STATIC const mp_map_elem_t mp_module_display_globals_table[] = { #if MICROPY_PY_DISPLAY_LCD_ILI9341 { MP_OBJ_NEW_QSTR(MP_QSTR_ILI9341), (mp_obj_t)&lcd_ili9341_type }, #endif +#if MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX + { MP_OBJ_NEW_QSTR(MP_QSTR_LS0XXB7DXXX), (mp_obj_t)&lcd_ls0xxb7dxxx_type }, +#endif #if MICROPY_PY_DISPLAY_OLED_SSD1305 { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1305), (mp_obj_t)&oled_ssd1305_type }, #endif @@ -48,8 +52,7 @@ STATIC const mp_map_elem_t mp_module_display_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1306), (mp_obj_t)&oled_ssd1306_type }, #endif #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1289), (mp_obj_t)&lcd_ssd1289_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_LS027b7DH01), (mp_obj_t)&lcd_ls027b7dh01_type } + { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1289), (mp_obj_t)&lcd_ssd1289_type } #endif }; From 8e6b51a60562e50e206d83fc786aef56a34f2872 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 20:46:58 +0100 Subject: [PATCH 218/809] nrf5/boards: Enable LS0XXB7DXXX display module in pca10056 board config. --- nrf5/boards/pca10056/mpconfigboard.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index 2e08970d9d..91f7e00bc8 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -39,6 +39,7 @@ #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) +#define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) From 225b3dfd19b866d95e37921f5f2041d8b5cf7ca2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 20:49:27 +0100 Subject: [PATCH 219/809] nrf5/drivers: Updating python example in comment for ls0xxb7dxx display module. --- nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c index d70ee9fbed..63a48eb3d1 100644 --- a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c +++ b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c @@ -124,15 +124,16 @@ Example for nrf52840 / pca10056: from machine import Pin, SPI from display import LS0XXB7DXXX +import draw cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) disp = Pin("B4", mode=Pin.OUT, pull=Pin.PULL_UP) extcomin = Pin("A28", mode=Pin.OUT, pull=Pin.PULL_UP) extmode = Pin("B5", mode=Pin.OUT, pull=Pin.PULL_UP) power_control = Pin("A29", mode=Pin.OUT, pull=Pin.PULL_UP) power_charge = Pin("A30", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) +spi = SPI(0, baudrate=2000000, firstbit=SPI.LSB) d = LS0XXB7DXXX(400, 240, spi, cs, disp, extcomin, extmode, power_control, power_charge) -d.text("Hello World!", 32, 32) +draw.text(d, "Hello World!", 32, 32) d.show() */ From 1f7bc76361d958d2e85b1d8839a5f5abc11a72d0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 20:55:00 +0100 Subject: [PATCH 220/809] nrf5/drivers: Removing debug printf's from epaper display python module. --- nrf5/drivers/display/epaper_sld00200p_obj.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/nrf5/drivers/display/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper_sld00200p_obj.c index 164a70b009..d78986d408 100644 --- a/nrf5/drivers/display/epaper_sld00200p_obj.c +++ b/nrf5/drivers/display/epaper_sld00200p_obj.c @@ -24,8 +24,6 @@ * THE SOFTWARE. */ -#include - #include "py/obj.h" #include "py/runtime.h" #include "py/mphal.h" @@ -227,7 +225,6 @@ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_ar if (args[ARG_NEW_BORDER].u_obj != MP_OBJ_NULL) { s->pin_border = args[ARG_NEW_BORDER].u_obj; - printf("BORDER PIN %u\n", s->pin_border->pin); } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Display Border Pin not set")); @@ -235,7 +232,6 @@ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_ar if (args[ARG_NEW_BUSY].u_obj != MP_OBJ_NULL) { s->pin_busy = args[ARG_NEW_BUSY].u_obj; - printf("BUSY PIN %u\n", s->pin_busy->pin); } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Display Busy Pin not set")); @@ -243,7 +239,6 @@ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_ar if (args[ARG_NEW_RESET].u_obj != MP_OBJ_NULL) { s->pin_reset = args[ARG_NEW_RESET].u_obj; - printf("RESET PIN %u\n", s->pin_reset->pin); } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Display Reset Pin not set")); From adccc2fa137a9e1165c56d1586745259fb001359 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 22:25:24 +0100 Subject: [PATCH 221/809] nrf5/drivers: Updating epaper driver sld00200p to use new framebuffer. --- .../drivers/display/epaper_sld00200p_driver.c | 2 +- .../drivers/display/epaper_sld00200p_driver.h | 4 +- nrf5/drivers/display/epaper_sld00200p_obj.c | 116 +++++++++++++----- 3 files changed, 85 insertions(+), 37 deletions(-) diff --git a/nrf5/drivers/display/epaper_sld00200p_driver.c b/nrf5/drivers/display/epaper_sld00200p_driver.c index d13570d666..30ce590ce5 100644 --- a/nrf5/drivers/display/epaper_sld00200p_driver.c +++ b/nrf5/drivers/display/epaper_sld00200p_driver.c @@ -437,7 +437,7 @@ void driver_sld00200p_clear(uint16_t color) { mp_hal_delay_ms(100); } -void driver_sld00200p_update_line(uint16_t line, fb_byte_t * p_bytes, fb_byte_t * p_old, uint16_t len, bool compressed) { +void driver_sld00200p_update_line(uint16_t line, framebuffer_byte_t * p_bytes, framebuffer_byte_t * p_old, uint16_t len) { epaper_sld00200p_line(line, (uint8_t *)p_old, 0x00, EPD_COMP); epaper_sld00200p_line(line, (uint8_t *)p_old, 0xAA, EPD_WHITE); epaper_sld00200p_line(line, (uint8_t *)p_bytes, 0xAA, EPD_INV); diff --git a/nrf5/drivers/display/epaper_sld00200p_driver.h b/nrf5/drivers/display/epaper_sld00200p_driver.h index ff997340cf..81470d0abc 100644 --- a/nrf5/drivers/display/epaper_sld00200p_driver.h +++ b/nrf5/drivers/display/epaper_sld00200p_driver.h @@ -33,7 +33,7 @@ #include "hal_spi.h" #include "hal_pwm.h" -#include "lcd_mono_fb.h" +#include "framebuffer.h" typedef enum { @@ -58,7 +58,7 @@ void driver_sld00200p_deinit(void); void driver_sld00200p_clear(uint16_t color); -void driver_sld00200p_update_line(uint16_t line, fb_byte_t * p_bytes, fb_byte_t * p_old, uint16_t len, bool compressed); +void driver_sld00200p_update_line(uint16_t line, framebuffer_byte_t * p_bytes, framebuffer_byte_t * p_bytes_old, uint16_t len); #endif // NRF52 diff --git a/nrf5/drivers/display/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper_sld00200p_obj.c index d78986d408..b2d02c4375 100644 --- a/nrf5/drivers/display/epaper_sld00200p_obj.c +++ b/nrf5/drivers/display/epaper_sld00200p_obj.c @@ -42,10 +42,13 @@ #include "pwm.h" #include "hal_spi.h" #include "hal_pwm.h" -#include "lcd_mono_fb.h" +#include "moddisplay.h" +#include "framebuffer.h" typedef struct _epaper_sld00200p_obj_t { mp_obj_base_t base; + display_draw_callbacks_t draw_callbacks; + framebuffer_t * framebuffer; machine_hard_spi_obj_t *spi; machine_hard_pwm_obj_t *pwm; pin_obj_t * pin_cs; @@ -57,14 +60,22 @@ typedef struct _epaper_sld00200p_obj_t { #if 0 pin_obj_t * pin_temp_sensor; #endif - mp_obj_framebuf_t * framebuffer; } epaper_sld00200p_obj_t; -static void dirty_line_update_cb(mp_obj_framebuf_t * p_framebuffer, - uint16_t line, - fb_byte_t * p_new, - fb_byte_t * p_old) { - driver_sld00200p_update_line(line, p_new, p_old, p_framebuffer->bytes_stride, true); +#define EPAPER_SLD00200P_COLOR_BLACK 0 +#define EPAPER_SLD00200P_COLOR_WHITE 1 + +static void set_pixel(void * p_display, + uint16_t x, + uint16_t y, + uint16_t color) { + epaper_sld00200p_obj_t *self = (epaper_sld00200p_obj_t *)p_display; + + if (color == EPAPER_SLD00200P_COLOR_BLACK) { + framebuffer_pixel_clear(self->framebuffer, x, y); + } else { + framebuffer_pixel_set(self->framebuffer, x, y); + } } /// \method __str__() @@ -101,10 +112,12 @@ STATIC void epaper_sld00200_print(const mp_print_t *print, mp_obj_t o, mp_print_ self->pin_discharge->port, self->pin_discharge->pin); - mp_printf(print, " FB(width=%u, height=%u, dir=%u))\n", - self->framebuffer->width, - self->framebuffer->height); - + mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", + self->framebuffer->screen_width, + self->framebuffer->screen_height, + self->framebuffer->line_orientation, + self->framebuffer->fb_stride, + self->framebuffer->fb_dirty_stride); } // for make_new @@ -125,6 +138,7 @@ enum { /* from machine import Pin, SPI, PWM from display import SLD00200P +import draw reset = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) panel_on = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) discharge = Pin("A19", mode=Pin.OUT, pull=Pin.PULL_UP) @@ -134,13 +148,14 @@ cs = Pin("A22", mode=Pin.OUT, pull=Pin.PULL_UP) spi = SPI(0, baudrate=8000000) pwm = PWM(0, Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP), freq=PWM.FREQ_250KHZ, duty=50, period=2) d = SLD00200P(264, 176, spi, pwm, cs, panel_on, border, busy, reset, discharge) -d.text("Hello World!", 32, 32) +draw.text(d, "Hello World!", 32, 32) d.show() Example for nrf52840 / pca10056: from machine import Pin, SPI, PWM from display import SLD00200P +import draw reset = Pin("B7", mode=Pin.OUT, pull=Pin.PULL_UP) panel_on = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) discharge = Pin("B9", mode=Pin.OUT, pull=Pin.PULL_UP) @@ -150,7 +165,7 @@ cs = Pin("B12", mode=Pin.OUT, pull=Pin.PULL_UP) spi = SPI(0, baudrate=8000000) pwm = PWM(0, Pin("B6", mode=Pin.OUT, pull=Pin.PULL_UP), freq=PWM.FREQ_250KHZ, duty=50, period=2) d = SLD00200P(264, 176, spi, pwm, cs, panel_on, border, busy, reset, discharge) -d.text("Hello World!", 32, 32) +draw.text(d, "Hello World!", 32, 32) d.show() */ @@ -177,6 +192,7 @@ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_ar epaper_sld00200p_obj_t *s = m_new_obj_with_finaliser(epaper_sld00200p_obj_t); s->base.type = type; + s->draw_callbacks.pixel_set = set_pixel; mp_int_t width; mp_int_t height; @@ -260,9 +276,16 @@ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_ar } #endif - // direction arg not yet configurable - mp_int_t vertical = false; - s->framebuffer = lcd_mono_fb_helper_make_new(width, height, vertical); + framebuffer_init_t init_conf = { + .width = width, + .height = height, + .line_orientation = FRAMEBUFFER_LINE_DIR_HORIZONTAL, + .double_buffer = false + }; + + s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); + + framebuffer_init(s->framebuffer, &init_conf); driver_sld00200p_init(s->spi->pyb->spi->instance, s->pwm->pyb->pwm->instance, @@ -276,7 +299,7 @@ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_ar // Default to white background driver_sld00200p_clear(0x00); - display_clear_screen(s->framebuffer, 0x0); + framebuffer_clear(s->framebuffer); driver_sld00200p_deinit(); @@ -289,12 +312,37 @@ STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_ar /// Fill framebuffer with the color defined as argument. STATIC mp_obj_t epaper_sld00200p_fill(mp_obj_t self_in, mp_obj_t color) { epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(self_in); - (void)self; + + if (color == MP_OBJ_NEW_SMALL_INT(EPAPER_SLD00200P_COLOR_BLACK)) { + framebuffer_clear(self->framebuffer); + } else { + framebuffer_fill(self->framebuffer); + } return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(epaper_sld00200p_fill_obj, epaper_sld00200p_fill); +static void render(framebuffer_t * p_framebuffer, bool refresh) { + for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { + if (p_framebuffer->fb_dirty[i].byte != 0 || refresh) { + for (uint16_t b = 0; b < 8; b++) { + if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) || refresh) { + uint16_t line_num = (i * 8) + b; + driver_sld00200p_update_line(line_num, + &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], + &p_framebuffer->fb_old[line_num * p_framebuffer->fb_stride], + p_framebuffer->fb_stride); + } + } + + if (refresh == false) { + p_framebuffer->fb_dirty[i].byte = 0x00; + } + } + } +} + /// \method show([num_of_refresh]) /// Display content in framebuffer. /// @@ -313,11 +361,12 @@ STATIC mp_obj_t epaper_sld00200p_show(size_t n_args, const mp_obj_t *args) { } driver_sld00200p_reinit(); - display_update(self->framebuffer, false, dirty_line_update_cb); + render(self->framebuffer, false); + framebuffer_flip(self->framebuffer); if (num_of_refresh > 0) { while (num_of_refresh > 0) { - display_update(self->framebuffer, true, dirty_line_update_cb); + render(self->framebuffer, true); num_of_refresh--; } } @@ -347,12 +396,12 @@ STATIC mp_obj_t epaper_sld00200p_refresh(size_t n_args, const mp_obj_t *args) { if (num_of_refresh > 0) { while (num_of_refresh > 0) { - display_update(self->framebuffer, true, dirty_line_update_cb); + render(self->framebuffer, true); num_of_refresh--; } } else { // default to one refresh - display_update(self->framebuffer, true, dirty_line_update_cb); + render(self->framebuffer, true); } driver_sld00200p_deinit(); @@ -370,14 +419,9 @@ STATIC mp_obj_t epaper_sld00200p_pixel(size_t n_args, const mp_obj_t *args) { epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); mp_int_t x = mp_obj_get_int(args[1]); mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color; - if (n_args >= 3) { - color = mp_obj_get_int(args[3]); - } - (void)self; - (void)x; - (void)y; - (void)color; + mp_int_t color = mp_obj_get_int(args[3]); + + set_pixel(self, x, y, color); return mp_const_none; } @@ -398,9 +442,13 @@ STATIC mp_obj_t epaper_sld00200p_text(size_t n_args, const mp_obj_t *args) { color = mp_obj_get_int(args[3]); } - (void)color; +// display_print_string(self->framebuffer, x, y, str); - display_print_string(self->framebuffer, x, y, str); + (void)x; + (void)y; + (void)self; + (void)str; + (void)color; return mp_const_none; } @@ -426,8 +474,8 @@ STATIC const mp_rom_map_elem_t epaper_sld00200p_locals_dict_table[] = { #if 0 { MP_ROM_QSTR(MP_QSTR_bitmap), MP_ROM_PTR(&epaper_sld00200p_bitmap_obj) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_BLACK) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_WHITE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(EPAPER_SLD00200P_COLOR_BLACK) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(EPAPER_SLD00200P_COLOR_WHITE) }, }; From 96c8f9c0825559ff039c7e09793a9ca0f4055adb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 22:30:11 +0100 Subject: [PATCH 222/809] nrf5/drivers: Enable framebuffer and graphics module to be compiled in by default if display is selected into the compilation. --- nrf5/mpconfigport.h | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index a3f45bad2a..7d957d106c 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -146,15 +146,21 @@ #define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (0) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) -#define MICROPY_PY_LCD_MONO_FB (0) #define MICROPY_PY_DISPLAY_FRAMEBUFFER (0) +#define MICROPY_PY_DISPLAY_GRAPHICS (0) #elif MICROPY_PY_DISPLAY // Default to include Monochrome Framebuffer // if display module is selected. -#ifndef MICROPY_PY_LCD_MONO_FB -#define MICROPY_PY_LCD_MONO_FB (1) +#ifndef MICROPY_PY_DISPLAY_FRAMEBUFFER +#define MICROPY_PY_DISPLAY_FRAMEBUFFER (1) +#endif + +// Default to include graphics library if +// display modue is selected. +#ifndef MICROPY_PY_DISPLAY_GRAPHICS +#define MICROPY_PY_DISPLAY_GRAPHICS (1) #endif #ifndef MICROPY_PY_DISPLAY_EPAPER_SLD00200P @@ -169,29 +175,14 @@ #define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (0) #endif -#if MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX -#define MICROPY_PY_DISPLAY_FRAMEBUFFER (1) -#define MICROPY_PY_DISPLAY_GRAPHICS (1) -#endif - #ifndef MICROPY_PY_DISPLAY_OLED_SSD1305 #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #endif -#if MICROPY_PY_DISPLAY_OLED_SSD1305 -#define MICROPY_PY_DISPLAY_FRAMEBUFFER (1) -#define MICROPY_PY_DISPLAY_GRAPHICS (1) -#endif - #ifndef MICROPY_PY_DISPLAY_OLED_SSD1306 #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #endif -#if MICROPY_PY_DISPLAY_OLED_SSD1306 -#define MICROPY_PY_DISPLAY_FRAMEBUFFER (1) -#define MICROPY_PY_DISPLAY_GRAPHICS (1) -#endif - #endif // MICROPY_PY_DISPLAY #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) From 506601bef7704e63308dd7059a1348e4f43f09b7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 22:30:42 +0100 Subject: [PATCH 223/809] nrf5: Remove old framebuffer implementation from being included into the build. --- nrf5/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index d81523a1b1..c72d089867 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -152,7 +152,6 @@ SRC_C += \ timer.c \ rtc.c \ adc.c \ - lcd_mono_fb.c \ DRIVERS_SRC_C += $(addprefix drivers/,\ display/moddisplay.c \ From 0156ebd2775f1f9ebc59b8b3a313b0744b1f48f0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 22:31:27 +0100 Subject: [PATCH 224/809] nrf5: Removing old framebuffer implementation. --- nrf5/lcd_mono_fb.c | 384 --------------------------------------------- nrf5/lcd_mono_fb.h | 91 ----------- 2 files changed, 475 deletions(-) delete mode 100644 nrf5/lcd_mono_fb.c delete mode 100644 nrf5/lcd_mono_fb.h diff --git a/nrf5/lcd_mono_fb.c b/nrf5/lcd_mono_fb.c deleted file mode 100644 index 2ce900e6e8..0000000000 --- a/nrf5/lcd_mono_fb.c +++ /dev/null @@ -1,384 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2016 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "py/nlr.h" -#include "py/obj.h" -#include "py/runtime.h" - -#include "lcd_mono_fb.h" -#include "font_petme128_8x8.h" - -#if MICROPY_PY_LCD_MONO_FB - -STATIC void lcd_enable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { - uint16_t column = (x / 8); - uint16_t line = y; - uint8_t bit_pos = x % 8; - - p_framebuffer->fb_bytes[line * (p_framebuffer->bytes_stride) + column].byte |= (1 << bit_pos); - p_framebuffer->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); -} - -STATIC void lcd_disable_pixel(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y) { - uint16_t column = (x / 8); - uint16_t line = y; - uint8_t bit_pos = x % 8; - - p_framebuffer->fb_bytes[line * (p_framebuffer->bytes_stride) + column].byte &= ~(1 << bit_pos); - p_framebuffer->fb_dirty[y/8].byte |= (uint8_t)(0x1 << y % 8); -} - -STATIC void lcd_init(mp_obj_framebuf_t * p_framebuffer) { - p_framebuffer->fg_color = LCD_BLACK; - p_framebuffer->bg_color = LCD_WHITE; - - memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); - memset(p_framebuffer->fb_dirty, 0x00, p_framebuffer->dirty_stride); -} - -STATIC void lcd_fg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { - p_framebuffer->fg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; -} - -#if 0 -STATIC uint16_t lcd_fg_color_get(mp_obj_framebuf_t * p_framebuffer) { - return p_framebuffer->fg_color; -} -#endif - -STATIC void lcd_bg_color_set(mp_obj_framebuf_t * p_framebuffer, uint16_t color) { - p_framebuffer->bg_color = (color == 0) ? LCD_BLACK : LCD_WHITE; -} - -#if 0 -STATIC uint16_t lcd_bg_color_get(mp_obj_framebuf_t * p_framebuffer) { - return p_framebuffer->bg_color; -} -#endif - -void display_clear_screen(mp_obj_framebuf_t * p_framebuffer, uint8_t color) { - - lcd_bg_color_set(p_framebuffer, color); - lcd_fg_color_set(p_framebuffer, !color); - - if (p_framebuffer->bg_color == LCD_BLACK) { - memset(p_framebuffer->fb_bytes, 0x00, p_framebuffer->bytes_stride * p_framebuffer->height); - } else { - memset(p_framebuffer->fb_bytes, 0xFF, p_framebuffer->bytes_stride * p_framebuffer->height); - } - memset(p_framebuffer->fb_dirty, 0xFF, p_framebuffer->dirty_stride); -} - -STATIC void lcd_print_char(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, char ch) { - uint16_t col = x; - for (uint8_t i = 0; i < 8; i++) { - - uint16_t current_col = col + (i * p_framebuffer->font_size); - - for (uint8_t y_pos = 0; y_pos < 8; y_pos++) { - if ((((uint8_t)font_petme128_8x8[((ch - 32) * 8) + i]) >> y_pos) & 0x01) { - for (uint8_t s_w = 0; s_w < p_framebuffer->font_size; s_w++) { - for (uint8_t s_h = 0; s_h < p_framebuffer->font_size; s_h++) { - if (p_framebuffer->fg_color < LCD_WHITE) { - lcd_disable_pixel(p_framebuffer, - current_col + s_w, - y + (y_pos * p_framebuffer->font_size) + s_h); - } else { - lcd_enable_pixel(p_framebuffer, - current_col + s_w, - y + (y_pos * p_framebuffer->font_size) + s_h); - } - } - } - } else { - for (uint8_t s_w = 0; s_w < p_framebuffer->font_size; s_w++) { - for (uint8_t s_h = 0; s_h < p_framebuffer->font_size; s_h++) { - if (p_framebuffer->bg_color < LCD_WHITE) { - lcd_disable_pixel(p_framebuffer, - current_col + s_w, - y + (y_pos * p_framebuffer->font_size) + s_h); - } else { - lcd_enable_pixel(p_framebuffer, - current_col + s_w, - y + (y_pos * p_framebuffer->font_size) + s_h); - } - } - } - } - } - } -} - -#if 0 -STATIC void lcd_font_size_set(mp_obj_framebuf_t * p_framebuffer, uint8_t size) { - m_font_size = size; -} - -STATIC uint8_t lcd_font_size_get(mp_obj_framebuf_t * p_framebuffer) { - return m_font_size; -} -#endif - -void display_print_string(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, const char * p_str) { - uint16_t str_len = strlen(p_str); - for (uint16_t i = 0; i < str_len; i++) { - lcd_print_char(p_framebuffer, x + (i * 8 * p_framebuffer->font_size), y, p_str[i]); - } -} - -STATIC void lcd_pixel_draw(mp_obj_framebuf_t * p_framebuffer, uint16_t x, uint16_t y, uint16_t color) { - if (color < LCD_WHITE) { - lcd_disable_pixel(p_framebuffer, x, y); - } else { - lcd_enable_pixel(p_framebuffer, x, y); - } -} - -void display_update(mp_obj_framebuf_t * p_framebuffer, bool refresh, lcd_update_line_callback_t c_callback) { - for (uint16_t i = 0; i < p_framebuffer->dirty_stride; i++) { - if (p_framebuffer->fb_dirty[i].byte != 0 || refresh) { - for (uint16_t b = 0; b < 8; b++) { - if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) || refresh) { - uint16_t line_num = (i * 8) + b; - - if (c_callback != NULL) - { - if (p_framebuffer->fb_old == NULL) { - c_callback(p_framebuffer, - line_num, - &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride], - NULL); - } - } else { - mp_obj_t args[4]; - mp_uint_t num_of_args = 3; - args[0] = p_framebuffer; - args[1] = MP_OBJ_NEW_SMALL_INT(line_num); - - if (refresh == false) { - args[2] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, - &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); - } else { - args[2] = mp_const_none; - } - - if (p_framebuffer->fb_old != NULL) { - args[3] = mp_obj_new_bytearray_by_ref(p_framebuffer->bytes_stride, - &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride]); - num_of_args = 4; - } - - mp_call_function_n_kw(p_framebuffer->line_update_cb, num_of_args, 0, args); - } - - // update old buffer - if (p_framebuffer->fb_old != NULL) { - memcpy(&p_framebuffer->fb_old[line_num * p_framebuffer->bytes_stride], - &p_framebuffer->fb_bytes[line_num * p_framebuffer->bytes_stride], - p_framebuffer->dirty_stride); - } - } - } - - if (refresh == false) { - p_framebuffer->fb_dirty[i].byte = 0x00; - } - } - } -} - -mp_obj_t lcd_mono_fb_helper_make_new(mp_int_t width, mp_int_t height, mp_int_t vertical) { - - mp_obj_framebuf_t *o = m_new_obj(mp_obj_framebuf_t); - o->base.type = &mp_type_object; - - o->width = width; - o->height = height; - - o->bytes_stride = o->width / 8; - o->dirty_stride = o->height / 8; - - o->fb_bytes = m_new(fb_byte_t, (o->bytes_stride) * o->height); - o->fb_dirty = m_new(fb_byte_t, o->dirty_stride); - - // default to not use double buffer - o->fb_old = NULL; - - o->font_size = 1; - - lcd_init(o); - - return MP_OBJ_FROM_PTR(o); -} - -STATIC mp_obj_t lcd_mono_fb_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { - mp_arg_check_num(n_args, n_kw, 3, 4, false); - - mp_obj_framebuf_t *o = m_new_obj(mp_obj_framebuf_t); - o->base.type = type; - - o->line_update_cb = args[0]; - - o->width = mp_obj_get_int(args[1]); - o->height = mp_obj_get_int(args[2]); - - o->bytes_stride = o->width / 8; - o->dirty_stride = o->height / 8; - - o->fb_bytes = m_new(fb_byte_t, (o->bytes_stride) * o->height); - o->fb_dirty = m_new(fb_byte_t, o->dirty_stride); - - // default to not use double buffer - o->fb_old = NULL; - - o->font_size = 1; - - if (n_args >= 4) { - if (mp_obj_is_true(args[3])) { - o->fb_old = m_new(fb_byte_t, (o->bytes_stride) * o->height); - } - } - - lcd_init(o); - - return MP_OBJ_FROM_PTR(o); -} - -STATIC mp_obj_t lcd_mono_fb_fill(mp_obj_t self_in, mp_obj_t col_in) { - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); - mp_int_t col = mp_obj_get_int(col_in); - - display_clear_screen(self, col); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_mono_fb_fill_obj, lcd_mono_fb_fill); - -STATIC mp_obj_t lcd_mono_fb_pixel(size_t n_args, const mp_obj_t *args) { - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(args[0]); - mp_int_t x = mp_obj_get_int(args[1]); - mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color = mp_obj_get_int(args[3]); - - lcd_pixel_draw(self, x, y, color); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_mono_fb_pixel_obj, 3, 4, lcd_mono_fb_pixel); - -STATIC mp_obj_t lcd_mono_fb_scroll(mp_obj_t self_in, mp_obj_t xstep_in, mp_obj_t ystep_in) { -#if 0 - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); - mp_int_t xstep = mp_obj_get_int(xstep_in); - mp_int_t ystep = mp_obj_get_int(ystep_in); -#endif - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_3(lcd_mono_fb_scroll_obj, lcd_mono_fb_scroll); - -STATIC mp_obj_t lcd_mono_fb_text(size_t n_args, const mp_obj_t *args) { - // extract arguments - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(args[0]); - const char *str = mp_obj_str_get_str(args[1]); - mp_int_t x0 = mp_obj_get_int(args[2]); - mp_int_t y0 = mp_obj_get_int(args[3]); - - display_print_string(self, x0, y0, str); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_mono_fb_text_obj, 4, 5, lcd_mono_fb_text); - - -STATIC mp_obj_t lcd_mono_fb_show(mp_obj_t self_in) { - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); - - display_update(self, false, NULL); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_show_obj, lcd_mono_fb_show); - -STATIC mp_obj_t lcd_mono_fb_refresh(mp_obj_t self_in) { - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); - - display_update(self, true, NULL); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_refresh_obj, lcd_mono_fb_refresh); - - -STATIC mp_obj_t lcd_mono_fb_del(mp_obj_t self_in) { - mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); - - m_free(self->fb_bytes); - m_free(self->fb_dirty); - - if (self->fb_old != NULL) { - // free double buffer if used - m_free(self->fb_old); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_mono_fb_del_obj, lcd_mono_fb_del); - -STATIC const mp_rom_map_elem_t lcd_mono_fb_locals_dict_table[] = { - { MP_ROM_QSTR(MP_QSTR___del__), MP_ROM_PTR(&lcd_mono_fb_del_obj) }, - { MP_ROM_QSTR(MP_QSTR_fill), MP_ROM_PTR(&lcd_mono_fb_fill_obj) }, - { MP_ROM_QSTR(MP_QSTR_pixel), MP_ROM_PTR(&lcd_mono_fb_pixel_obj) }, - { MP_ROM_QSTR(MP_QSTR_scroll), MP_ROM_PTR(&lcd_mono_fb_scroll_obj) }, - { MP_ROM_QSTR(MP_QSTR_text), MP_ROM_PTR(&lcd_mono_fb_text_obj) }, - { MP_ROM_QSTR(MP_QSTR_show), MP_ROM_PTR(&lcd_mono_fb_show_obj) }, - { MP_ROM_QSTR(MP_QSTR_refresh), MP_ROM_PTR(&lcd_mono_fb_refresh_obj) }, -}; -STATIC MP_DEFINE_CONST_DICT(lcd_mono_fb_locals_dict, lcd_mono_fb_locals_dict_table); - -STATIC const mp_obj_type_t mp_type_lcd_mono_fb = { - { &mp_type_type }, - .name = MP_QSTR_MonoFB, - .make_new = lcd_mono_fb_make_new, - .locals_dict = (mp_obj_t)&lcd_mono_fb_locals_dict, -}; - -STATIC const mp_rom_map_elem_t lcd_mono_fb_module_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_lcd_mono_fb) }, - { MP_ROM_QSTR(MP_QSTR_MonoFB), MP_ROM_PTR(&mp_type_lcd_mono_fb) }, -}; - -STATIC MP_DEFINE_CONST_DICT(lcd_mono_fb_module_globals, lcd_mono_fb_module_globals_table); - -const mp_obj_module_t mp_module_lcd_mono_fb = { - .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&lcd_mono_fb_module_globals, -}; - -#endif // MICROPY_PY_LCD_MONO_FB diff --git a/nrf5/lcd_mono_fb.h b/nrf5/lcd_mono_fb.h deleted file mode 100644 index 8ab748a58e..0000000000 --- a/nrf5/lcd_mono_fb.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2016 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef LCD_MONO_FB_H__ -#define LCD_MONO_FB_H__ - -extern const mp_obj_module_t mp_module_lcd_mono_fb; - -#include - -#define LCD_BLACK 0 -#define LCD_WHITE 1 - -typedef struct { - uint8_t bit0 : 1; - uint8_t bit1 : 1; - uint8_t bit2 : 1; - uint8_t bit3 : 1; - uint8_t bit4 : 1; - uint8_t bit5 : 1; - uint8_t bit6 : 1; - uint8_t bit7 : 1; -} bits_t; - -typedef struct { - union { - uint8_t byte; - bits_t bits; - }; -} fb_byte_t; - -typedef struct { - mp_obj_base_t base; - fb_byte_t * fb_bytes; - fb_byte_t * fb_old; - fb_byte_t * fb_dirty; - uint16_t height; - uint16_t width; - mp_uint_t bytes_stride; - mp_uint_t dirty_stride; - mp_obj_t line_update_cb; - mp_uint_t bg_color; - mp_uint_t fg_color; - mp_uint_t font_size; -} mp_obj_framebuf_t; - - -typedef void (*lcd_update_line_callback_t)(mp_obj_framebuf_t * p_framebuffer, - uint16_t line, - fb_byte_t * p_new, - fb_byte_t * p_old); - -// Functions for other drivers to use to create framebuffer instances using c. - -mp_obj_t lcd_mono_fb_helper_make_new(mp_int_t width, mp_int_t height, mp_int_t direction); - -void display_clear_screen(mp_obj_framebuf_t * p_framebuffer, uint8_t color); - -void display_update(mp_obj_framebuf_t * p_framebuffer, - bool refresh, - lcd_update_line_callback_t c_callback); - -void display_print_string(mp_obj_framebuf_t * p_framebuffer, - uint16_t x, - uint16_t y, - const char * p_str); - -#endif From 6124e8db76be756b3e7b51bba3ed7373ac9b8da6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 19 Jan 2017 22:47:23 +0100 Subject: [PATCH 225/809] nrf5: Adding configuration defines for SSD1289 lcd driver. --- nrf5/mpconfigport.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 7d957d106c..cb1922cdac 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -144,6 +144,7 @@ #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) #define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (0) +#define MICROPY_PY_DISPLAY_LCD_SSD1289 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #define MICROPY_PY_DISPLAY_FRAMEBUFFER (0) @@ -175,6 +176,10 @@ #define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (0) #endif +#ifndef MICROPY_PY_DISPLAY_LCD_SSD1289 +#define MICROPY_PY_DISPLAY_LCD_SSD1289 (0) +#endif + #ifndef MICROPY_PY_DISPLAY_OLED_SSD1305 #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #endif From 34aeaf97c12cf724495a6155c175c556b1c38881 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 20 Jan 2017 19:17:31 +0100 Subject: [PATCH 226/809] nrf5/drivers: Adding rgb16.h with macro to convert 5-6-5 rgb values into a 16-bit value. --- nrf5/drivers/display/rgb16.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 nrf5/drivers/display/rgb16.h diff --git a/nrf5/drivers/display/rgb16.h b/nrf5/drivers/display/rgb16.h new file mode 100644 index 0000000000..149182f0a8 --- /dev/null +++ b/nrf5/drivers/display/rgb16.h @@ -0,0 +1,33 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RGB16_H__ +#define RGB16_H__ + +#define RGB16(rrrrr32, gggggg64, bbbbb32) \ +(((rrrrr32 & 248) | gggggg64 >> 5) << 8) + ((gggggg64 & 28)<< 3 | bbbbb32 >> 3) + +#endif // RGB16_H__ From c1a609653ffbcc64674882374b3cd51d382144a7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 20 Jan 2017 19:31:10 +0100 Subject: [PATCH 227/809] nrf5/drivers: Adding space in macro. --- nrf5/drivers/display/rgb16.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/drivers/display/rgb16.h b/nrf5/drivers/display/rgb16.h index 149182f0a8..96977d4123 100644 --- a/nrf5/drivers/display/rgb16.h +++ b/nrf5/drivers/display/rgb16.h @@ -28,6 +28,6 @@ #define RGB16_H__ #define RGB16(rrrrr32, gggggg64, bbbbb32) \ -(((rrrrr32 & 248) | gggggg64 >> 5) << 8) + ((gggggg64 & 28)<< 3 | bbbbb32 >> 3) +(((rrrrr32 & 248) | gggggg64 >> 5) << 8) + ((gggggg64 & 28) << 3 | bbbbb32 >> 3) #endif // RGB16_H__ From e52ec391205a341ff92a2fb72af22847518994c3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 21 Jan 2017 21:22:02 +0100 Subject: [PATCH 228/809] nrf5/drivers: Optimizing update_line in ili9341 driver a bit. --- nrf5/drivers/display/lcd_ili9341_driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/drivers/display/lcd_ili9341_driver.c b/nrf5/drivers/display/lcd_ili9341_driver.c index adf5eac5d1..b6c4b2f7f2 100644 --- a/nrf5/drivers/display/lcd_ili9341_driver.c +++ b/nrf5/drivers/display/lcd_ili9341_driver.c @@ -236,8 +236,8 @@ void driver_ili9341_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uin mp_hal_pin_low(mp_cs_pin); for (uint16_t i = 0; i < len; i++) { + uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; for (uint8_t pixel_pos = 0; pixel_pos < 8; pixel_pos++) { - uint8_t byte = (uint8_t)((uint8_t * )p_bytes)[i]; if (((byte >> pixel_pos) & 0x1) == 0x0) { data_write(0x00); data_write(0x00); From 2c1420b0840f48ee0c74a3a5491762ff067d9832 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 21 Jan 2017 21:44:26 +0100 Subject: [PATCH 229/809] nrf5/hal: Adding hal template files for 32mhz Quad SPI peripheral. --- nrf5/hal/hal_qspie.c | 32 ++++++++++++++++++++++++++++++++ nrf5/hal/hal_qspie.h | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 nrf5/hal/hal_qspie.c create mode 100644 nrf5/hal/hal_qspie.h diff --git a/nrf5/hal/hal_qspie.c b/nrf5/hal/hal_qspie.c new file mode 100644 index 0000000000..334a4853dd --- /dev/null +++ b/nrf5/hal/hal_qspie.c @@ -0,0 +1,32 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "hal_qspie.h" + +#ifdef HAL_QSPIE_MODULE_ENABLED + +#endif // HAL_QSPIE_MODULE_ENABLED diff --git a/nrf5/hal/hal_qspie.h b/nrf5/hal/hal_qspie.h new file mode 100644 index 0000000000..23e6dc27fa --- /dev/null +++ b/nrf5/hal/hal_qspie.h @@ -0,0 +1,38 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_QSPIE_H__ +#define HAL_QSPIE_H__ + +#if NRF52840_XXAA + +#include + +#else +#error "Device not supported." +#endif + +#endif // HAL_QSPIE_H__ From a7f3217c957bac5d45eea8653bc46a09e3a6b0ca Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 22 Jan 2017 18:31:42 +0100 Subject: [PATCH 230/809] nrf5/hal: Adding QSPI base and IRQ num in c-file. --- nrf5/hal/hal_qspie.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nrf5/hal/hal_qspie.c b/nrf5/hal/hal_qspie.c index 334a4853dd..e29bf0be76 100644 --- a/nrf5/hal/hal_qspie.c +++ b/nrf5/hal/hal_qspie.c @@ -29,4 +29,7 @@ #ifdef HAL_QSPIE_MODULE_ENABLED +#define QSPI_IRQ_NUM QSPI_IRQn +#define QSPI_BASE ((NRF_QSPI_Type *)NRF_QSPI_BASE) + #endif // HAL_QSPIE_MODULE_ENABLED From e02c90dca52ce5d8b46368e2131f05f377546c75 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 22 Jan 2017 19:15:24 +0100 Subject: [PATCH 231/809] nrf5/hal: Updating clock frequency enums and lookup table for quad spi. --- nrf5/hal/hal_qspie.c | 9 +++++++++ nrf5/hal/hal_qspie.h | 20 ++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/nrf5/hal/hal_qspie.c b/nrf5/hal/hal_qspie.c index e29bf0be76..f9e9352918 100644 --- a/nrf5/hal/hal_qspie.c +++ b/nrf5/hal/hal_qspie.c @@ -32,4 +32,13 @@ #define QSPI_IRQ_NUM QSPI_IRQn #define QSPI_BASE ((NRF_QSPI_Type *)NRF_QSPI_BASE) +// frequency, 32 MHz / (SCKFREQ + 1) +static const uint32_t hal_qspi_frequency_lookup[] = { + QSPI_FREQUENCY_FREQUENCY_M2 = (15 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 2 Mbps + QSPI_FREQUENCY_FREQUENCY_M4 = (7 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 4 Mbps + QSPI_FREQUENCY_FREQUENCY_M8 = (3 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 8 Mbps + QSPI_FREQUENCY_FREQUENCY_M16 = (1 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 16 Mbps + QSPI_FREQUENCY_FREQUENCY_M32 = (0 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps +}; + #endif // HAL_QSPIE_MODULE_ENABLED diff --git a/nrf5/hal/hal_qspie.h b/nrf5/hal/hal_qspie.h index 23e6dc27fa..0916678824 100644 --- a/nrf5/hal/hal_qspie.h +++ b/nrf5/hal/hal_qspie.h @@ -35,4 +35,24 @@ #error "Device not supported." #endif +/** + * @brief Quad SPI clock frequency type definition + */ +typedef enum { + HAL_FREQ_2_Mbps, + HAL_FREQ_4_Mbps, + HAL_FREQ_8_Mbps, + HAL_FREQ_16_Mbps, + HAL_FREQ_32_Mbps +} hal_qspi_clk_freq_t; + +/** + * @brief Quad SPI mode configuration type definition + */ +typedef enum { + HAL_QSPI_MODE_SINGLE_LINE, + HAL_QSPI_MODE_DUAL_LINE, + HAL_QSPI_MODE_QUAL_LINE +} hal_qspi_mode_t; + #endif // HAL_QSPIE_H__ From e40c385c6a86f4f96fd9760dbcc8953825cf5ec3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 22 Jan 2017 22:18:44 +0100 Subject: [PATCH 232/809] nrf5: Syncing code after upmerge with master. --- nrf5/Makefile | 28 +++++++--------- nrf5/boards/microbit/mpconfigboard.h | 2 +- nrf5/boards/pca10000/mpconfigboard.h | 2 +- nrf5/boards/pca10001/mpconfigboard.h | 2 +- nrf5/boards/pca10028/mpconfigboard.h | 2 +- nrf5/boards/pca10040/mpconfigboard.h | 2 +- nrf5/boards/pca10056/mpconfigboard.h | 2 +- nrf5/help.c | 21 ++---------- nrf5/lexerfatfs.c | 35 -------------------- nrf5/mpconfigport.h | 10 ++++-- nrf5/spi.c | 49 +++++++++++++++++++++++++--- nrf5/uart.c | 2 -- 12 files changed, 72 insertions(+), 85 deletions(-) delete mode 100644 nrf5/lexerfatfs.c diff --git a/nrf5/Makefile b/nrf5/Makefile index c72d089867..dcac81dcdd 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -37,7 +37,7 @@ endif # qstr definitions (must come before including py.mk) QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h -FROZEN_MPY_DIR = modules +FROZEN_DIR = modules # include py core make definitions include ../py/py.mk @@ -78,8 +78,6 @@ CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) CFLAGS += -fno-strict-aliasing CFLAGS += -Iboards/$(BOARD) CFLAGS += -DNRF5_HAL_H='<$(MCU_VARIANT)_hal.h>' -CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool -CFLAGS += -DMICROPY_MODULE_FROZEN_MPY LDFLAGS = $(CFLAGS) LDFLAGS += -Xlinker -Map=$(@:.elf=.map) @@ -101,7 +99,6 @@ SRC_LIB = $(addprefix lib/,\ libc/string0.c \ mp-readline/readline.c \ utils/pyexec.c \ - utils/pyhelp.c \ timeutils/timeutils.c \ fatfs/ff.c \ fatfs/option/ccsbcs.c \ @@ -146,7 +143,6 @@ SRC_C += \ moduos.c \ fatfs_port.c \ builtin_open.c \ - lexerfatfs.c \ modusocket.c \ modnetwork.c \ timer.c \ @@ -187,8 +183,6 @@ OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_HAL:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(DRIVERS_SRC_C:.c=.o)) OBJ += $(BUILD)/pins_gen.o -OBJ += $(BUILD)/$(BUILD)/frozen_mpy.o - $(BUILD)/$(FATFS_DIR)/ff.o: COPT += -Os $(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os @@ -256,16 +250,18 @@ GEN_PINS_QSTR = $(BUILD)/pins_qstr.h GEN_PINS_AF_CONST = $(HEADER_BUILD)/pins_af_const.h GEN_PINS_AF_PY = $(BUILD)/pins_af.py -# to build .mpy files from .py files -$(BUILD)/$(FROZEN_MPY_DIR)/%.mpy: $(FROZEN_MPY_DIR)/%.py - @$(ECHO) "MPY $<" - $(Q)$(MKDIR) -p $(dir $@) - $(Q)$(MPY_CROSS) -o $@ -s $(^:$(FROZEN_MPY_DIR)/%=%) $^ +ifneq ($(FROZEN_DIR),) +# To use frozen source modules, put your .py files in a subdirectory (eg scripts/) +# and then invoke make with FROZEN_DIR=scripts (be sure to build from scratch). +CFLAGS += -DMICROPY_MODULE_FROZEN_STR +endif -# to build frozen_mpy.c from all .mpy files -$(BUILD)/frozen_mpy.c: $(FROZEN_MPY_MPY_FILES) $(BUILD)/genhdr/qstrdefs.generated.h - @$(ECHO) "Creating $@" - $(Q)$(PYTHON) $(MPY_TOOL) -f -q $(BUILD)/genhdr/qstrdefs.preprocessed.h -mlongint-impl mpz $(FROZEN_MPY_MPY_FILES) > $@ +ifneq ($(FROZEN_MPY_DIR),) +# To use frozen bytecode, put your .py files in a subdirectory (eg frozen/) and +# then invoke make with FROZEN_MPY_DIR=frozen (be sure to build from scratch). +CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool +CFLAGS += -DMICROPY_MODULE_FROZEN_MPY +endif include ../py/mkrules.mk include mkrules.mk diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index ed655896ea..7de7f4ac95 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -30,7 +30,7 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51" -#define MICROPY_PY_MACHINE_SPI (0) +#define MICROPY_PY_MACHINE_HW_SPI (0) #define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TIMER (0) #define MICROPY_PY_MACHINE_RTC (0) diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf5/boards/pca10000/mpconfigboard.h index e38ae686c1..01840d26e8 100644 --- a/nrf5/boards/pca10000/mpconfigboard.h +++ b/nrf5/boards/pca10000/mpconfigboard.h @@ -30,7 +30,7 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" -#define MICROPY_PY_MACHINE_SPI (0) +#define MICROPY_PY_MACHINE_HW_SPI (0) #define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_HW_HAS_SWITCH (0) diff --git a/nrf5/boards/pca10001/mpconfigboard.h b/nrf5/boards/pca10001/mpconfigboard.h index b440b7f900..06570af7c4 100644 --- a/nrf5/boards/pca10001/mpconfigboard.h +++ b/nrf5/boards/pca10001/mpconfigboard.h @@ -30,7 +30,7 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" -#define MICROPY_PY_MACHINE_SPI (0) +#define MICROPY_PY_MACHINE_HW_SPI (0) #define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_HW_HAS_SWITCH (0) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index c4eab19cf1..1b558b3b7f 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -36,7 +36,7 @@ #define MICROPY_PY_DISPLAY_OLED_SSD1305 (1) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) -#define MICROPY_PY_MACHINE_SPI (1) +#define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index e5d0106087..58e7aaff1a 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -31,7 +31,7 @@ #define MICROPY_PY_SYS_PLATFORM "nrf52-DK" #define MICROPY_PY_MACHINE_PWM (1) -#define MICROPY_PY_MACHINE_SPI (1) +#define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_MACHINE_HW_I2C (1) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index 91f7e00bc8..cf711ae1bb 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -31,7 +31,7 @@ #define MICROPY_PY_SYS_PLATFORM "nrf52840-PDK" #define MICROPY_PY_MACHINE_PWM (1) -#define MICROPY_PY_MACHINE_SPI (1) +#define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_HW_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) diff --git a/nrf5/help.c b/nrf5/help.c index a3a12bd19c..f17439a19d 100644 --- a/nrf5/help.c +++ b/nrf5/help.c @@ -25,16 +25,13 @@ * THE SOFTWARE. */ -#include - -#include "lib/utils/pyhelp.h" -#include "mpconfigboard.h" +#include "py/builtin.h" #if BLUETOOTH_SD #include "help_sd.h" #endif -STATIC const char help_text[] = +const char * nrf5_help_text = "Welcome to MicroPython!\n" "\n" "For online help please visit http://micropython.org/help/.\n" @@ -51,17 +48,3 @@ HELP_TEXT_SD "\n" "For further help on a specific object, type help(obj)\n" ; - -STATIC mp_obj_t pyb_help(uint n_args, const mp_obj_t *args) { - if (n_args == 0) { - // print a general help message - printf("%s", help_text); - - } else { - // try to print something sensible about the given object - pyhelp_print_obj(args[0]); - } - - return mp_const_none; -} -MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_builtin_help_obj, 0, 1, pyb_help); diff --git a/nrf5/lexerfatfs.c b/nrf5/lexerfatfs.c deleted file mode 100644 index fd7f62dfdd..0000000000 --- a/nrf5/lexerfatfs.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2013, 2014 Damien P. George - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/lexer.h" - -mp_lexer_t *fat_vfs_lexer_new_from_file(const char *filename); - -// TODO: Instead of such shims, probably better to let port #define -// mp_lexer_new_from_file to a function it wants to use. -mp_lexer_t *mp_lexer_new_from_file(const char *filename) { - return fat_vfs_lexer_new_from_file(filename); -} diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index cb1922cdac..aafcd3812c 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -50,6 +50,7 @@ #define MICROPY_OPT_COMPUTED_GOTO (0) #define MICROPY_OPT_CACHE_MAP_LOOKUP_IN_BYTECODE (0) #define MICROPY_OPT_MPZ_BITWISE (0) +#define MICROPY_READER_FATFS (1) // fatfs configuration used in ffconf.h #define MICROPY_FATFS_ENABLE_LFN (1) @@ -73,6 +74,9 @@ #define MICROPY_PY_BUILTINS_FROZENSET (1) #define MICROPY_PY_BUILTINS_EXECFILE (0) #define MICROPY_PY_BUILTINS_COMPILE (1) +#define MICROPY_PY_BUILTINS_HELP (1) +#define MICROPY_PY_BUILTINS_HELP_TEXT nrf5_help_text +#define MICROPY_PY_BUILTINS_HELP_MODULES (1) #define MICROPY_PY_ALL_SPECIAL_METHODS (0) #define MICROPY_PY_MICROPYTHON_MEM_INFO (1) #define MICROPY_PY_ARRAY_SLICE_ASSIGN (0) @@ -100,7 +104,7 @@ #define MICROPY_PY_MACHINE (1) #define MICROPY_PY_MACHINE_PULSE (0) #define MICROPY_PY_MACHINE_I2C (0) - +#define MICROPY_PY_MACHINE_SPI (0) #define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) #define MICROPY_PY_FRAMEBUF (0) @@ -112,8 +116,8 @@ #define MICROPY_PY_MACHINE_HW_I2C (0) #endif -#ifndef MICROPY_PY_MACHINE_SPI -#define MICROPY_PY_MACHINE_SPI (1) +#ifndef MICROPY_PY_MACHINE_HW_SPI +#define MICROPY_PY_MACHINE_HW_SPI (1) #endif #ifndef MICROPY_PY_MACHINE_PWM diff --git a/nrf5/spi.c b/nrf5/spi.c index a9a31337d2..7e3d831e88 100644 --- a/nrf5/spi.c +++ b/nrf5/spi.c @@ -37,7 +37,7 @@ #include "spi.h" #include "hal_spi.h" -#if MICROPY_PY_MACHINE_SPI +#if MICROPY_PY_MACHINE_HW_SPI /// \moduleref pyb /// \class SPI - a master-driven serial protocol @@ -113,7 +113,7 @@ void spi_init(SPI_HandleTypeDef *spi, bool enable_nss_pin) { void spi_deinit(SPI_HandleTypeDef *spi) { } -STATIC void spi_transfer(const pyb_spi_obj_t * self, size_t len, const uint8_t * src, uint8_t * dest, uint32_t timeout) { +STATIC void spi_transfer(const pyb_spi_obj_t * self, size_t len, const void * src, void * dest) { hal_spi_master_tx_rx(self->spi->instance, len, src, dest); } @@ -296,9 +296,50 @@ STATIC void machine_hard_spi_deinit(mp_obj_t self_in) { STATIC void machine_hard_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8_t *src, uint8_t *dest) { machine_hard_spi_obj_t *self = (machine_hard_spi_obj_t*)self_in; - spi_transfer(self->pyb, len, src, dest, 100); + spi_transfer(self->pyb, len, src, dest); } + +STATIC mp_obj_t mp_machine_spi_read(size_t n_args, const mp_obj_t *args) { + vstr_t vstr; + vstr_init_len(&vstr, mp_obj_get_int(args[1])); + memset(vstr.buf, n_args == 3 ? mp_obj_get_int(args[2]) : 0, vstr.len); + spi_transfer(args[0], vstr.len, vstr.buf, vstr.buf); + return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr); +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_spi_read_obj, 2, 3, mp_machine_spi_read); + +STATIC mp_obj_t mp_machine_spi_readinto(size_t n_args, const mp_obj_t *args) { + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_WRITE); + memset(bufinfo.buf, n_args == 3 ? mp_obj_get_int(args[2]) : 0, bufinfo.len); + spi_transfer(args[0], bufinfo.len, bufinfo.buf, bufinfo.buf); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_spi_readinto_obj, 2, 3, mp_machine_spi_readinto); + +STATIC mp_obj_t mp_machine_spi_write(mp_obj_t self, mp_obj_t wr_buf) { + mp_buffer_info_t src; + mp_get_buffer_raise(wr_buf, &src, MP_BUFFER_READ); + spi_transfer(self, src.len, (const uint8_t*)src.buf, NULL); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_2(mp_machine_spi_write_obj, mp_machine_spi_write); + +STATIC mp_obj_t mp_machine_spi_write_readinto(mp_obj_t self, mp_obj_t wr_buf, mp_obj_t rd_buf) { + mp_buffer_info_t src; + mp_get_buffer_raise(wr_buf, &src, MP_BUFFER_READ); + mp_buffer_info_t dest; + mp_get_buffer_raise(rd_buf, &dest, MP_BUFFER_WRITE); + if (src.len != dest.len) { + mp_raise_ValueError("buffers must be the same length"); + } + spi_transfer(self, src.len, src.buf, dest.buf); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_3(mp_machine_spi_write_readinto_obj, mp_machine_spi_write_readinto); + + STATIC const mp_machine_spi_p_t machine_hard_spi_p = { .transfer = machine_hard_spi_transfer, }; @@ -312,4 +353,4 @@ const mp_obj_type_t machine_hard_spi_type = { .locals_dict = (mp_obj_t)&machine_spi_locals_dict, }; -#endif // MICROPY_PY_MACHINE_SPI +#endif // MICROPY_PY_MACHINE_HW_SPI diff --git a/nrf5/uart.c b/nrf5/uart.c index 4edaea3881..a510c834a9 100644 --- a/nrf5/uart.c +++ b/nrf5/uart.c @@ -348,8 +348,6 @@ STATIC const mp_map_elem_t pyb_uart_locals_dict_table[] = { /// \method read([nbytes]) { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&mp_stream_read_obj }, - /// \method readall() - { MP_OBJ_NEW_QSTR(MP_QSTR_readall), (mp_obj_t)&mp_stream_readall_obj }, /// \method readline() { MP_OBJ_NEW_QSTR(MP_QSTR_readline), (mp_obj_t)&mp_stream_unbuffered_readline_obj}, /// \method readinto(buf[, nbytes]) From 1bd9003338306fd6c307ea1bd3fdd7920e204804 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 22 Jan 2017 23:04:25 +0100 Subject: [PATCH 233/809] nrf5/hal: Adding more types to quad SPI header. --- nrf5/hal/hal_qspie.h | 53 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/nrf5/hal/hal_qspie.h b/nrf5/hal/hal_qspie.h index 0916678824..c62d32ac51 100644 --- a/nrf5/hal/hal_qspie.h +++ b/nrf5/hal/hal_qspie.h @@ -47,12 +47,57 @@ typedef enum { } hal_qspi_clk_freq_t; /** - * @brief Quad SPI mode configuration type definition + * @brief Quad SPI mode type definition */ typedef enum { - HAL_QSPI_MODE_SINGLE_LINE, - HAL_QSPI_MODE_DUAL_LINE, - HAL_QSPI_MODE_QUAL_LINE + HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge) + HAL_SPI_MODE_CPOL1_CPHA1 = 3 // CPOL = 1, CPHA = 1 (data on trailing edge) } hal_qspi_mode_t; +/** + * @brief Quad SPI data line configuration type definition + */ +typedef enum { + HAL_QSPI_DATA_LINE_SINGLE, + HAL_QSPI_DATA_LINE_DUAL, + HAL_QSPI_DATA_LINE_QUAL +} hal_qspi_data_line_t; + + + +/** + * @brief Quad SPI Configuration Structure definition + */ +typedef struct { + uint8_t d0_mosi_pin; + uint8_t d1_miso_pin; + uint8_t d2_pin; + uint8_t d3_pin; + uint8_t clk_pin; + uint8_t d0_mosi_pin_port; + uint8_t d1_miso_pin_port; + uint8_t d2_pin_port; + uint8_t d3_pin_port; + uint8_t clk_pin_port; + hal_qspi_mode_t mode; + hal_qspi_data_line_t data_line; + hal_qspi_clk_freq_t freq; +} hal_qspi_init_t; + +/** + * @brief Quad SPI handle Structure definition + */ +typedef struct __QSPI_HandleTypeDef +{ + NRF_QSPI_Type *instance; /* QSPI registers base address */ + hal_qspi_init_t init; /* QSPI initialization parameters */ +} QSPI_HandleTypeDef; + +void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init); + +void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance, + uint16_t transfer_size, + const uint8_t * tx_data, + uint8_t * rx_data); + #endif // HAL_QSPIE_H__ From 0662e1ccf5a44475a217d55b80783f2cf2873dcb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 23 Jan 2017 00:10:04 +0100 Subject: [PATCH 234/809] nrf5/hal: Aligning assignment in hal_adc.c --- nrf5/hal/hal_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/hal/hal_adc.c b/nrf5/hal/hal_adc.c index 17a63fee5c..e39a1f35cc 100644 --- a/nrf5/hal/hal_adc.c +++ b/nrf5/hal/hal_adc.c @@ -91,7 +91,7 @@ uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) { uint8_t adc_result; ADC_BASE->EVENTS_END = 0; - adc_result = ADC_BASE->RESULT; + adc_result = ADC_BASE->RESULT; ADC_BASE->TASKS_STOP = 1; return adc_result; From fcd9ce201559fc99db75f9719d38f5216b595beb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 23 Jan 2017 00:11:50 +0100 Subject: [PATCH 235/809] nrf5/hal: Updating Quad SPI hal driver. --- nrf5/hal/hal_qspie.c | 69 ++++++++++++++++++++++++++++++++++++++++++++ nrf5/hal/hal_qspie.h | 3 ++ 2 files changed, 72 insertions(+) diff --git a/nrf5/hal/hal_qspie.c b/nrf5/hal/hal_qspie.c index f9e9352918..d8f86347e7 100644 --- a/nrf5/hal/hal_qspie.c +++ b/nrf5/hal/hal_qspie.c @@ -41,4 +41,73 @@ static const uint32_t hal_qspi_frequency_lookup[] = { QSPI_FREQUENCY_FREQUENCY_M32 = (0 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps }; +void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init) +{ + // configure SCK + QSPI_BASE->PSEL.SCK = (p_qspi_init->clk_pin << QSPI_PSEL_SCK_PIN_Pos) + | (p_qspi_init->clk_pin_port << QSPI_PSEL_SCK_PORT_Pos) + | (QSPI_PSEL_SCK_CONNECT_Connected << QSPI_PSEL_SCK_CONNECT_Pos); + + // configure CS + if (p_qspi_init->use_csn) { + QSPI_BASE->PSEL.CSN = (p_qspi_init->clk_pin << QSPI_PSEL_CSN_PIN_Pos) + | (p_qspi_init->clk_pin_port << QSPI_PSEL_CSN_PORT_Pos) + | (QSPI_PSEL_CSN_CONNECT_Connected << QSPI_PSEL_CSN_CONNECT_Pos); + } else { + QSPI_BASE->PSEL.CSN = (QSPI_PSEL_CSN_CONNECT_Disconnected << QSPI_PSEL_CSN_CONNECT_Pos); + } + + // configure MOSI/IO0, valid for all configurations + QSPI_BASE->PSEL.IO0 = (p_qspi_init->d0_mosi_pin << QSPI_PSEL_IO0_PIN_Pos) + | (p_qspi_init->d0_mosi_pin_port << QSPI_PSEL_IO0_PORT_Pos) + | (QSPI_PSEL_IO0_CONNECT_Connected << QSPI_PSEL_IO0_CONNECT_Pos); + + if (p_qspi_init->data_line != HAL_QSPI_DATA_LINE_SINGLE) { + // configure MISO/IO1 + QSPI_BASE->PSEL.IO1 = (p_qspi_init->d1_miso_pin << QSPI_PSEL_IO1_PIN_Pos) + | (p_qspi_init->d1_miso_pin_port << QSPI_PSEL_IO1_PORT_Pos) + | (QSPI_PSEL_IO1_CONNECT_Connected << QSPI_PSEL_IO1_CONNECT_Pos); + + if (p_qspi_init->data_line == HAL_QSPI_DATA_LINE_QUAD) + // configure IO2 + QSPI_BASE->PSEL.IO2 = (p_qspi_init->d2_pin << QSPI_PSEL_IO2_PIN_Pos) + | (p_qspi_init->d2_pin_port << QSPI_PSEL_IO2_PORT_Pos) + | (QSPI_PSEL_IO2_CONNECT_Connected << QSPI_PSEL_IO2_CONNECT_Pos); + + // configure IO3 + QSPI_BASE->PSEL.IO3 = (p_qspi_init->d3_pin << QSPI_PSEL_IO3_PIN_Pos) + | (p_qspi_init->d3_pin_port << QSPI_PSEL_IO3_PORT_Pos) + | (QSPI_PSEL_IO3_CONNECT_Connected << QSPI_PSEL_IO3_CONNECT_Pos); + } + } + + uint32_t mode; + switch (p_spi_init->mode) { + case HAL_SPI_MODE_CPOL0_CPHA0: + mode = (QSPI_IFCONFIG1_SPIMODE_MODE0 << QSPI_IFCONFIG1_SPIMODE_Pos); + break; + case HAL_SPI_MODE_CPOL1_CPHA1: + mode = (QSPI_IFCONFIG1_SPIMODE_MODE3 << QSPI_IFCONFIG1_SPIMODE_Pos); + break; + default: + mode = 0; + break; + } + + // interface config1 + QSPI_BASE->IFCONFIG1 = hal_qspi_frequency_lookup[p_qspi_init->freq] + | mode + | (1 << QSPI_IFCONFIG1_SCKDELAY_Pos); // number of 16 MHz periods (62.5 ns) + + QSPI_BASE->ENABLE = 1; +} + +void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance, + uint16_t transfer_size, + const uint8_t * tx_data, + uint8_t * rx_data) +{ + +} + #endif // HAL_QSPIE_MODULE_ENABLED diff --git a/nrf5/hal/hal_qspie.h b/nrf5/hal/hal_qspie.h index c62d32ac51..99c1c4cee9 100644 --- a/nrf5/hal/hal_qspie.h +++ b/nrf5/hal/hal_qspie.h @@ -74,11 +74,14 @@ typedef struct { uint8_t d2_pin; uint8_t d3_pin; uint8_t clk_pin; + uint8_t csn_pin; uint8_t d0_mosi_pin_port; uint8_t d1_miso_pin_port; uint8_t d2_pin_port; uint8_t d3_pin_port; uint8_t clk_pin_port; + uint8_t csn_pin_port; + bool use_csn; hal_qspi_mode_t mode; hal_qspi_data_line_t data_line; hal_qspi_clk_freq_t freq; From 5cc48901192e6f510012aed69f5d7585cf15f3bf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 23 Jan 2017 00:33:27 +0100 Subject: [PATCH 236/809] nrf5/hal: Fixing compile issues in quad SPI driver. --- nrf5/hal/hal_qspie.c | 53 ++++++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 22 deletions(-) diff --git a/nrf5/hal/hal_qspie.c b/nrf5/hal/hal_qspie.c index d8f86347e7..c4c59534fb 100644 --- a/nrf5/hal/hal_qspie.c +++ b/nrf5/hal/hal_qspie.c @@ -34,55 +34,55 @@ // frequency, 32 MHz / (SCKFREQ + 1) static const uint32_t hal_qspi_frequency_lookup[] = { - QSPI_FREQUENCY_FREQUENCY_M2 = (15 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 2 Mbps - QSPI_FREQUENCY_FREQUENCY_M4 = (7 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 4 Mbps - QSPI_FREQUENCY_FREQUENCY_M8 = (3 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 8 Mbps - QSPI_FREQUENCY_FREQUENCY_M16 = (1 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 16 Mbps - QSPI_FREQUENCY_FREQUENCY_M32 = (0 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps + (15 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 2 Mbps + (7 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 4 Mbps + (3 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 8 Mbps + (1 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 16 Mbps + (0 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps }; void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init) { // configure SCK - QSPI_BASE->PSEL.SCK = (p_qspi_init->clk_pin << QSPI_PSEL_SCK_PIN_Pos) - | (p_qspi_init->clk_pin_port << QSPI_PSEL_SCK_PORT_Pos) - | (QSPI_PSEL_SCK_CONNECT_Connected << QSPI_PSEL_SCK_CONNECT_Pos); + p_instance->PSEL.SCK = (p_qspi_init->clk_pin << QSPI_PSEL_SCK_PIN_Pos) + | (p_qspi_init->clk_pin_port << QSPI_PSEL_SCK_PORT_Pos) + | (QSPI_PSEL_SCK_CONNECT_Connected << QSPI_PSEL_SCK_CONNECT_Pos); // configure CS if (p_qspi_init->use_csn) { - QSPI_BASE->PSEL.CSN = (p_qspi_init->clk_pin << QSPI_PSEL_CSN_PIN_Pos) - | (p_qspi_init->clk_pin_port << QSPI_PSEL_CSN_PORT_Pos) - | (QSPI_PSEL_CSN_CONNECT_Connected << QSPI_PSEL_CSN_CONNECT_Pos); + p_instance->PSEL.CSN = (p_qspi_init->clk_pin << QSPI_PSEL_CSN_PIN_Pos) + | (p_qspi_init->clk_pin_port << QSPI_PSEL_CSN_PORT_Pos) + | (QSPI_PSEL_CSN_CONNECT_Connected << QSPI_PSEL_CSN_CONNECT_Pos); } else { - QSPI_BASE->PSEL.CSN = (QSPI_PSEL_CSN_CONNECT_Disconnected << QSPI_PSEL_CSN_CONNECT_Pos); + p_instance->PSEL.CSN = (QSPI_PSEL_CSN_CONNECT_Disconnected << QSPI_PSEL_CSN_CONNECT_Pos); } // configure MOSI/IO0, valid for all configurations - QSPI_BASE->PSEL.IO0 = (p_qspi_init->d0_mosi_pin << QSPI_PSEL_IO0_PIN_Pos) + p_instance->PSEL.IO0 = (p_qspi_init->d0_mosi_pin << QSPI_PSEL_IO0_PIN_Pos) | (p_qspi_init->d0_mosi_pin_port << QSPI_PSEL_IO0_PORT_Pos) | (QSPI_PSEL_IO0_CONNECT_Connected << QSPI_PSEL_IO0_CONNECT_Pos); if (p_qspi_init->data_line != HAL_QSPI_DATA_LINE_SINGLE) { // configure MISO/IO1 - QSPI_BASE->PSEL.IO1 = (p_qspi_init->d1_miso_pin << QSPI_PSEL_IO1_PIN_Pos) + p_instance->PSEL.IO1 = (p_qspi_init->d1_miso_pin << QSPI_PSEL_IO1_PIN_Pos) | (p_qspi_init->d1_miso_pin_port << QSPI_PSEL_IO1_PORT_Pos) | (QSPI_PSEL_IO1_CONNECT_Connected << QSPI_PSEL_IO1_CONNECT_Pos); - if (p_qspi_init->data_line == HAL_QSPI_DATA_LINE_QUAD) + if (p_qspi_init->data_line == HAL_QSPI_DATA_LINE_QUAD) { // configure IO2 - QSPI_BASE->PSEL.IO2 = (p_qspi_init->d2_pin << QSPI_PSEL_IO2_PIN_Pos) + p_instance->PSEL.IO2 = (p_qspi_init->d2_pin << QSPI_PSEL_IO2_PIN_Pos) | (p_qspi_init->d2_pin_port << QSPI_PSEL_IO2_PORT_Pos) | (QSPI_PSEL_IO2_CONNECT_Connected << QSPI_PSEL_IO2_CONNECT_Pos); // configure IO3 - QSPI_BASE->PSEL.IO3 = (p_qspi_init->d3_pin << QSPI_PSEL_IO3_PIN_Pos) + p_instance->PSEL.IO3 = (p_qspi_init->d3_pin << QSPI_PSEL_IO3_PIN_Pos) | (p_qspi_init->d3_pin_port << QSPI_PSEL_IO3_PORT_Pos) | (QSPI_PSEL_IO3_CONNECT_Connected << QSPI_PSEL_IO3_CONNECT_Pos); } } uint32_t mode; - switch (p_spi_init->mode) { + switch (p_qspi_init->mode) { case HAL_SPI_MODE_CPOL0_CPHA0: mode = (QSPI_IFCONFIG1_SPIMODE_MODE0 << QSPI_IFCONFIG1_SPIMODE_Pos); break; @@ -95,11 +95,11 @@ void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_ } // interface config1 - QSPI_BASE->IFCONFIG1 = hal_qspi_frequency_lookup[p_qspi_init->freq] - | mode - | (1 << QSPI_IFCONFIG1_SCKDELAY_Pos); // number of 16 MHz periods (62.5 ns) + p_instance->IFCONFIG1 = hal_qspi_frequency_lookup[p_qspi_init->freq] + | mode + | (1 << QSPI_IFCONFIG1_SCKDELAY_Pos); // number of 16 MHz periods (62.5 ns) - QSPI_BASE->ENABLE = 1; + p_instance->ENABLE = 1; } void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance, @@ -107,7 +107,16 @@ void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance, const uint8_t * tx_data, uint8_t * rx_data) { + p_instance->READ.DST = (uint32_t)rx_data; + p_instance->READ.CNT = transfer_size; + p_instance->READ.SRC = (uint32_t)tx_data; + p_instance->READ.CNT = transfer_size; + p_instance->TASKS_ACTIVATE = 1; + while (p_instance->EVENTS_READY == 0) { + ; + } + p_instance->TASKS_ACTIVATE = 0; } #endif // HAL_QSPIE_MODULE_ENABLED From c442588b9275926c75f71799c720d7a5d0ba9cff Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 25 Jan 2017 19:47:25 +0100 Subject: [PATCH 237/809] nrf5/drivers: Adding ssd1289 lcd tft driver and python module. --- nrf5/drivers/display/lcd_ssd1289_driver.c | 225 ++++++++++ nrf5/drivers/display/lcd_ssd1289_driver.h | 52 +++ nrf5/drivers/display/lcd_ssd1289_obj.c | 516 ++++++++++++++++++++++ nrf5/drivers/display/lcd_ssd1289_obj.h | 35 ++ 4 files changed, 828 insertions(+) create mode 100644 nrf5/drivers/display/lcd_ssd1289_driver.c create mode 100644 nrf5/drivers/display/lcd_ssd1289_driver.h create mode 100644 nrf5/drivers/display/lcd_ssd1289_obj.c create mode 100644 nrf5/drivers/display/lcd_ssd1289_obj.h diff --git a/nrf5/drivers/display/lcd_ssd1289_driver.c b/nrf5/drivers/display/lcd_ssd1289_driver.c new file mode 100644 index 0000000000..db2bae8030 --- /dev/null +++ b/nrf5/drivers/display/lcd_ssd1289_driver.c @@ -0,0 +1,225 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "py/mphal.h" + +#include "lcd_ssd1289_driver.h" +#include "hal_time.h" + +#include "framebuffer.h" + +#if MICROPY_PY_DISPLAY_LCD_SSD1289 + +static pin_obj_t * mp_cs_pin; +static pin_obj_t * mp_rs_pin; +static pin_obj_t * mp_wr_pin; +static pin_obj_t * mp_reset_pin; +static pin_obj_t * mp_d0_pin; +static pin_obj_t * mp_d1_pin; +static pin_obj_t * mp_d2_pin; +static pin_obj_t * mp_d3_pin; +static pin_obj_t * mp_d4_pin; +static pin_obj_t * mp_d5_pin; +static pin_obj_t * mp_d6_pin; +static pin_obj_t * mp_d7_pin; + +static void data_port_write(uint8_t byte) { + mp_hal_pin_write(mp_d0_pin, (byte >> 0) & 0x1); + mp_hal_pin_write(mp_d1_pin, (byte >> 1) & 0x1); + mp_hal_pin_write(mp_d2_pin, (byte >> 2) & 0x1); + mp_hal_pin_write(mp_d3_pin, (byte >> 3) & 0x1); + mp_hal_pin_write(mp_d4_pin, (byte >> 4) & 0x1); + mp_hal_pin_write(mp_d5_pin, (byte >> 5) & 0x1); + mp_hal_pin_write(mp_d6_pin, (byte >> 6) & 0x1); + mp_hal_pin_write(mp_d7_pin, (byte >> 7) & 0x1); + mp_hal_pin_low(mp_wr_pin); + mp_hal_delay_us(20); + mp_hal_pin_high(mp_wr_pin); +} + +static void cmd_write(uint8_t cmd) { + mp_hal_pin_low(mp_rs_pin); + mp_hal_delay_us(20); + data_port_write(0x00); + mp_hal_delay_us(20); + data_port_write(cmd); +} + +static void data_write(uint16_t value) { + mp_hal_pin_high(mp_rs_pin); + + uint8_t high_byte = (uint8_t)(value >> 8); + uint8_t low_byte = (uint8_t)(value & 0xFF); + mp_hal_delay_us(20); + data_port_write(high_byte); + mp_hal_delay_us(20); + data_port_write(low_byte); +} + +#define LCD_WRITE(a, b) { \ + cmd_write(a); \ + data_write(b); } + +void driver_ssd1289_init(pin_obj_t * p_cs_pin, + pin_obj_t * p_rs_pin, + pin_obj_t * p_wr_pin, + pin_obj_t * p_reset_pin, + pin_obj_t * p_d0_pin, + pin_obj_t * p_d1_pin, + pin_obj_t * p_d2_pin, + pin_obj_t * p_d3_pin, + pin_obj_t * p_d4_pin, + pin_obj_t * p_d5_pin, + pin_obj_t * p_d6_pin, + pin_obj_t * p_d7_pin) { + + mp_cs_pin = p_cs_pin; + mp_rs_pin = p_rs_pin; + mp_wr_pin = p_wr_pin; + mp_reset_pin = p_reset_pin; + mp_d0_pin = p_d0_pin; + mp_d1_pin = p_d1_pin; + mp_d2_pin = p_d2_pin; + mp_d3_pin = p_d3_pin; + mp_d4_pin = p_d4_pin; + mp_d5_pin = p_d5_pin; + mp_d6_pin = p_d6_pin; + mp_d7_pin = p_d7_pin; + + mp_hal_pin_low(mp_d0_pin); + mp_hal_pin_low(mp_d1_pin); + mp_hal_pin_low(mp_d2_pin); + mp_hal_pin_low(mp_d3_pin); + mp_hal_pin_low(mp_d4_pin); + mp_hal_pin_low(mp_d5_pin); + mp_hal_pin_low(mp_d6_pin); + mp_hal_pin_low(mp_d7_pin); + + mp_hal_pin_low(mp_rs_pin); + mp_hal_pin_low(mp_wr_pin); + + mp_hal_pin_low(mp_cs_pin); + + mp_hal_pin_high(mp_reset_pin); + mp_hal_delay_ms(20); + mp_hal_pin_high(mp_reset_pin); + + LCD_WRITE(0x00,0x0001); + LCD_WRITE(0x03,0xA8A4); + LCD_WRITE(0x0C,0x0000); + LCD_WRITE(0x0D,0x080C); + LCD_WRITE(0x0E,0x2B00); + LCD_WRITE(0x1E,0x00B7); + LCD_WRITE(0x01,0x2B3F); + LCD_WRITE(0x02,0x0600); + LCD_WRITE(0x10,0x0000); + LCD_WRITE(0x11,0x6070); + LCD_WRITE(0x05,0x0000); + LCD_WRITE(0x06,0x0000); + LCD_WRITE(0x16,0xEF1C); + LCD_WRITE(0x17,0x0003); + LCD_WRITE(0x07,0x0233); + LCD_WRITE(0x0B,0x0000); + LCD_WRITE(0x0F,0x0000); + LCD_WRITE(0x41,0x0000); + LCD_WRITE(0x42,0x0000); + LCD_WRITE(0x48,0x0000); + LCD_WRITE(0x49,0x013F); + LCD_WRITE(0x4A,0x0000); + LCD_WRITE(0x4B,0x0000); + LCD_WRITE(0x44,0xEF00); + LCD_WRITE(0x45,0x0000); + LCD_WRITE(0x46,0x013F); + LCD_WRITE(0x30,0x0707); + LCD_WRITE(0x31,0x0204); + LCD_WRITE(0x32,0x0204); + LCD_WRITE(0x33,0x0502); + LCD_WRITE(0x34,0x0507); + LCD_WRITE(0x35,0x0204); + LCD_WRITE(0x36,0x0204); + LCD_WRITE(0x37,0x0502); + LCD_WRITE(0x3A,0x0302); + LCD_WRITE(0x3B,0x0302); + LCD_WRITE(0x23,0x0000); + LCD_WRITE(0x24,0x0000); + LCD_WRITE(0x25,0x8000); + LCD_WRITE(0x4f,0x0000); + LCD_WRITE(0x4e,0x0000); + cmd_write(0x22); + + mp_hal_pin_high(mp_cs_pin); +} + +static void set_xy(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) { + LCD_WRITE(0x44, (y1 << 8) + y0); + LCD_WRITE(0x45, 319 - x1); + LCD_WRITE(0x46, 319 - x0); + LCD_WRITE(0x4e, y0); + LCD_WRITE(0x4f, 319 - x1); + cmd_write(0x22); +} + +void driver_ssd1289_clear(uint16_t color) { + uint16_t x; + uint16_t y; + uint16_t lcd_x_size = 240; + uint16_t lcd_y_size = 320; + + mp_hal_pin_low(mp_cs_pin); + + set_xy(0, 0, lcd_y_size - 1, lcd_x_size - 1); + + for (x = 0; x < lcd_x_size; x++) { + for (y = 0; y < lcd_y_size; y++) { + data_write(color); + } + } + + mp_hal_pin_high(mp_cs_pin); +} + +void driver_ssd1289_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { + set_xy(0, line, 319, line); + + mp_hal_pin_low(mp_cs_pin); + + for (uint8_t i = 0; i < len; i++) { + uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; + for (uint8_t pixel_pos = 0; pixel_pos < 8; pixel_pos++) { + if (((byte >> pixel_pos) & 0x1) == 0x0) { + data_write(0x0000); + } else { + data_write(0xFFFF); + } + } + } + + mp_hal_pin_high(mp_cs_pin); +} + +#endif // MICROPY_PY_DISPLAY_LCD_SSD1289 diff --git a/nrf5/drivers/display/lcd_ssd1289_driver.h b/nrf5/drivers/display/lcd_ssd1289_driver.h new file mode 100644 index 0000000000..58b36618d8 --- /dev/null +++ b/nrf5/drivers/display/lcd_ssd1289_driver.h @@ -0,0 +1,52 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LCD_SSD1289_DRIVER_H__ +#define LCD_SSD1289_DRIVER_H__ + +#include "py/mphal.h" + +#include "framebuffer.h" + +void driver_ssd1289_init(pin_obj_t * p_cs_pin, + pin_obj_t * p_rs_pin, + pin_obj_t * p_wr_pin, + pin_obj_t * p_reset_pin, + pin_obj_t * p_d0_pin, + pin_obj_t * p_d1_pin, + pin_obj_t * p_d2_pin, + pin_obj_t * p_d3_pin, + pin_obj_t * p_d4_pin, + pin_obj_t * p_d5_pin, + pin_obj_t * p_d6_pin, + pin_obj_t * p_d7_pin); + + +void driver_ssd1289_clear(uint16_t color); + +void driver_ssd1289_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); + +#endif // LCD_SSD1289_DRIVER_H__ diff --git a/nrf5/drivers/display/lcd_ssd1289_obj.c b/nrf5/drivers/display/lcd_ssd1289_obj.c new file mode 100644 index 0000000000..24382ab6f3 --- /dev/null +++ b/nrf5/drivers/display/lcd_ssd1289_obj.c @@ -0,0 +1,516 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "genhdr/pins.h" + +#include "lcd_ssd1289_driver.h" + +#if MICROPY_PY_DISPLAY_LCD_SSD1289 + +/// \moduleref display +/// \class SSD1289 - SSD1289 TFT LCD display driver. + +#include "moddisplay.h" +#include "framebuffer.h" +#include "pin.h" + +typedef struct _lcd_ssd1289_obj_t { + mp_obj_base_t base; + display_draw_callbacks_t draw_callbacks; + framebuffer_t * framebuffer; + pin_obj_t * pin_cs; + pin_obj_t * pin_rs; + pin_obj_t * pin_wr; + pin_obj_t * pin_reset; + pin_obj_t * pin_d0; + pin_obj_t * pin_d1; + pin_obj_t * pin_d2; + pin_obj_t * pin_d3; + pin_obj_t * pin_d4; + pin_obj_t * pin_d5; + pin_obj_t * pin_d6; + pin_obj_t * pin_d7; +} lcd_ssd1289_obj_t; + +#define LCD_SSD1289_COLOR_BLACK 0 +#define LCD_SSD1289_COLOR_WHITE 1 + +static void set_pixel(void * p_display, + uint16_t x, + uint16_t y, + uint16_t color) { + lcd_ssd1289_obj_t *self = (lcd_ssd1289_obj_t *)p_display; + + if (color == LCD_SSD1289_COLOR_BLACK) { + framebuffer_pixel_clear(self->framebuffer, x, y); + } else { + framebuffer_pixel_set(self->framebuffer, x, y); + } +} + +/// \method __str__() +/// Return a string describing the SSD1289 object. +STATIC void lcd_ssd1289_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + lcd_ssd1289_obj_t *self = o; + + mp_printf(print, "SSD1289(cs=(port=%u, pin=%u), rs=(port=%u, pin=%u),\n", + self->pin_cs->port, + self->pin_cs->pin, + self->pin_rs->port, + self->pin_rs->pin); + + mp_printf(print, " wr=(port=%u, pin=%u), reset=(port=%u, pin=%u),\n", + self->pin_wr->port, + self->pin_wr->pin, + self->pin_reset->port, + self->pin_reset->pin); + + mp_printf(print, " d0=(port=%u, pin=%u), d1=(port=%u, pin=%u),\n", + self->pin_d0->port, + self->pin_d0->pin, + self->pin_d1->port, + self->pin_d1->pin); + + mp_printf(print, " d2=(port=%u, pin=%u), d3=(port=%u, pin=%u),\n", + self->pin_d2->port, + self->pin_d2->pin, + self->pin_d3->port, + self->pin_d3->pin); + + mp_printf(print, " d4=(port=%u, pin=%u), d5=(port=%u, pin=%u),\n", + self->pin_d4->port, + self->pin_d4->pin, + self->pin_d5->port, + self->pin_d5->pin); + + mp_printf(print, " d6=(port=%u, pin=%u), d7=(port=%u, pin=%u),\n", + self->pin_d6->port, + self->pin_d6->pin, + self->pin_d7->port, + self->pin_d7->pin); + + + mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", + self->framebuffer->screen_width, + self->framebuffer->screen_height, + self->framebuffer->line_orientation, + self->framebuffer->fb_stride, + self->framebuffer->fb_dirty_stride); +} + +// for make_new +enum { + ARG_NEW_WIDTH, + ARG_NEW_HEIGHT, + ARG_NEW_CS, + ARG_NEW_RS, + ARG_NEW_WR, + ARG_NEW_RESET, + ARG_NEW_D0, + ARG_NEW_D1, + ARG_NEW_D2, + ARG_NEW_D3, + ARG_NEW_D4, + ARG_NEW_D5, + ARG_NEW_D6, + ARG_NEW_D7, + +}; + +/* + +Example for nrf51822 / pca10028: + +from machine import Pin +from display import SSD1289 +import draw +cs = Pin("A1", mode=Pin.OUT, pull=Pin.PULL_UP) +rs = Pin("A2", mode=Pin.OUT, pull=Pin.PULL_UP) +wr = Pin("A3", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("A4", mode=Pin.OUT, pull=Pin.PULL_UP) + +d0 = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) +d1 = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) +d2 = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) +d3 = Pin("A15", mode=Pin.OUT, pull=Pin.PULL_UP) +d4 = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) +d5 = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) +d6 = Pin("A18", mode=Pin.OUT, pull=Pin.PULL_UP) +d7 = Pin("A19", mode=Pin.OUT, pull=Pin.PULL_UP) + +d = SSD1289(320, 240, cs, rs, wr, reset, d0, d1, d2, d3, d4, d5, d6, d7) +draw.text(d, "Hello World!", 32, 32) +d.show() + +Example for nrf52832 / pca10040: + +from machine import Pin +from display import SSD1289 +import draw +cs = Pin("A3", mode=Pin.OUT, pull=Pin.PULL_UP) +rs = Pin("A4", mode=Pin.OUT, pull=Pin.PULL_UP) +wr = Pin("A28", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("A29", mode=Pin.OUT, pull=Pin.PULL_UP) + +d0 = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) +d1 = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) +d2 = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) +d3 = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) +d4 = Pin("A15", mode=Pin.OUT, pull=Pin.PULL_UP) +d5 = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) +d6 = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) +d7 = Pin("A18", mode=Pin.OUT, pull=Pin.PULL_UP) + +d = SSD1289(240, 320, cs, rs, wr, reset, d0, d1, d2, d3, d4, d5, d6, d7) +draw.text(d, "Hello World!", 32, 32) +d.show() + +Example for nrf52840 / pca10056: + +from machine import Pin +from display import SSD1289 +import draw +cs = Pin("A3", mode=Pin.OUT, pull=Pin.PULL_UP) +rs = Pin("A4", mode=Pin.OUT, pull=Pin.PULL_UP) +wr = Pin("A28", mode=Pin.OUT, pull=Pin.PULL_UP) +reset = Pin("A29", mode=Pin.OUT, pull=Pin.PULL_UP) + +d0 = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) +d1 = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) +d2 = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) +d3 = Pin("B4", mode=Pin.OUT, pull=Pin.PULL_UP) +d4 = Pin("B5", mode=Pin.OUT, pull=Pin.PULL_UP) +d5 = Pin("B6", mode=Pin.OUT, pull=Pin.PULL_UP) +d6 = Pin("B7", mode=Pin.OUT, pull=Pin.PULL_UP) +d7 = Pin("B8", mode=Pin.OUT, pull=Pin.PULL_UP) + +d = SSD1289(320, 240, cs, rs, wr, reset, d0, d1, d2, d3, d4, d5, d6, d7) +draw.text(d, "Hello World!", 32, 32) +d.show() + +*/ +STATIC mp_obj_t lcd_ssd1289_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, + { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_RS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_WR, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_D0, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_D1, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_D2, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_D3, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_D4, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_D5, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_D6, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_D7, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + lcd_ssd1289_obj_t *s = m_new_obj_with_finaliser(lcd_ssd1289_obj_t); + s->base.type = type; + s->draw_callbacks.pixel_set = set_pixel; + + mp_int_t width; + mp_int_t height; + + if (args[ARG_NEW_WIDTH].u_int > 0) { + width = args[ARG_NEW_WIDTH].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display width not set")); + } + + if (args[ARG_NEW_HEIGHT].u_int > 0) { + height = args[ARG_NEW_HEIGHT].u_int; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display height not set")); + } + + if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { + s->pin_cs = args[ARG_NEW_CS].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display CS Pin not set")); + } + + if (args[ARG_NEW_RS].u_obj != MP_OBJ_NULL) { + s->pin_rs = args[ARG_NEW_RS].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display RS Pin not set")); + } + + if (args[ARG_NEW_WR].u_obj != MP_OBJ_NULL) { + s->pin_wr = args[ARG_NEW_WR].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display WR Pin not set")); + } + + if (args[ARG_NEW_RESET].u_obj != MP_OBJ_NULL) { + s->pin_reset = args[ARG_NEW_RESET].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Reset Pin not set")); + } + + if (args[ARG_NEW_D0].u_obj != MP_OBJ_NULL) { + s->pin_d0 = args[ARG_NEW_D0].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Data 0 Pin not set")); + } + + if (args[ARG_NEW_D1].u_obj != MP_OBJ_NULL) { + s->pin_d1 = args[ARG_NEW_D1].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Data 1 Pin not set")); + } + + if (args[ARG_NEW_D2].u_obj != MP_OBJ_NULL) { + s->pin_d2 = args[ARG_NEW_D2].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Data 2 Pin not set")); + } + + if (args[ARG_NEW_D3].u_obj != MP_OBJ_NULL) { + s->pin_d3 = args[ARG_NEW_D3].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Data 3 Pin not set")); + } + + if (args[ARG_NEW_D4].u_obj != MP_OBJ_NULL) { + s->pin_d4 = args[ARG_NEW_D4].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Data 4 Pin not set")); + } + + if (args[ARG_NEW_D5].u_obj != MP_OBJ_NULL) { + s->pin_d5 = args[ARG_NEW_D5].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Data 5 Pin not set")); + } + + if (args[ARG_NEW_D6].u_obj != MP_OBJ_NULL) { + s->pin_d6 = args[ARG_NEW_D6].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Data 6 Pin not set")); + } + + if (args[ARG_NEW_D7].u_obj != MP_OBJ_NULL) { + s->pin_d7 = args[ARG_NEW_D7].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Display Data 7 Pin not set")); + } + + framebuffer_init_t init_conf = { + .width = width, + .height = height, + .line_orientation = FRAMEBUFFER_LINE_DIR_HORIZONTAL, + .double_buffer = false + }; + + s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); + + framebuffer_init(s->framebuffer, &init_conf); + + driver_ssd1289_init(s->pin_cs, + s->pin_rs, + s->pin_wr, + s->pin_reset, + s->pin_d0, + s->pin_d1, + s->pin_d2, + s->pin_d3, + s->pin_d4, + s->pin_d5, + s->pin_d6, + s->pin_d7); + + // Default to black background + driver_ssd1289_clear(0x00FF); + + framebuffer_clear(s->framebuffer); + + return MP_OBJ_FROM_PTR(s); +} + +// text + +/// \method fill(color) +/// Fill framebuffer with the color defined as argument. +STATIC mp_obj_t lcd_ssd1289_fill(mp_obj_t self_in, mp_obj_t color) { + lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (color == MP_OBJ_NEW_SMALL_INT(LCD_SSD1289_COLOR_BLACK)) { + framebuffer_clear(self->framebuffer); + } else { + framebuffer_fill(self->framebuffer); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_ssd1289_fill_obj, lcd_ssd1289_fill); + +static void render(framebuffer_t * p_framebuffer) { + for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { + if (p_framebuffer->fb_dirty[i].byte != 0) { + for (uint16_t b = 0; b < 8; b++) { + if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { + uint16_t line_num = (i * 8) + b; + driver_ssd1289_update_line(line_num, + &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], + p_framebuffer->fb_stride); + } + } + + p_framebuffer->fb_dirty[i].byte = 0x00; + } + } +} + +/// \method show() +/// Display content in framebuffer. +STATIC mp_obj_t lcd_ssd1289_show(size_t n_args, const mp_obj_t *args) { + lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(args[0]); + + render(self->framebuffer); + framebuffer_flip(self->framebuffer); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ssd1289_show_obj, 1, 2, lcd_ssd1289_show); + +/// \method refresh([num_of_refresh]) +/// Refresh content in framebuffer. +/// +/// - With no argument, 1 refresh will be done. +/// - With `num_of_refresh` given, The whole framebuffer will be considered +/// dirty and will be refreshed the given number of times. +STATIC mp_obj_t lcd_ssd1289_refresh(mp_obj_t self_in) { + lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ssd1289_refresh_obj, lcd_ssd1289_refresh); + +/// \method pixel(x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color of the pixel in framebuffer will be returend. +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t lcd_ssd1289_pixel(size_t n_args, const mp_obj_t *args) { + lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(args[0]); + mp_int_t x = mp_obj_get_int(args[1]); + mp_int_t y = mp_obj_get_int(args[2]); + mp_int_t color = mp_obj_get_int(args[3]); + + set_pixel(self, x, y, color); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ssd1289_pixel_obj, 4, 4, lcd_ssd1289_pixel); + +/// \method pixel(text, x, y, [color]) +/// Write one pixel in framebuffer. +/// +/// - With no argument, the color will be the opposite of background (fill color). +/// - With `color` given, sets the pixel to the color given. +STATIC mp_obj_t lcd_ssd1289_text(size_t n_args, const mp_obj_t *args) { + lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(args[0]); + const char *str = mp_obj_str_get_str(args[1]); + mp_int_t x = mp_obj_get_int(args[2]); + mp_int_t y = mp_obj_get_int(args[3]); + mp_int_t color; + if (n_args >= 4) { + color = mp_obj_get_int(args[3]); + } + + //display_print_string(self->framebuffer, x, y, str); + + (void)x; + (void)y; + (void)self; + (void)str; + (void)color; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ssd1289_text_obj, 4, 5, lcd_ssd1289_text); + +STATIC mp_obj_t lcd_ssd1289_del(mp_obj_t self_in) { + lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ssd1289_del_obj, lcd_ssd1289_del); + +STATIC const mp_map_elem_t lcd_ssd1289_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&lcd_ssd1289_del_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&lcd_ssd1289_fill_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&lcd_ssd1289_show_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&lcd_ssd1289_text_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&lcd_ssd1289_pixel_obj) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&lcd_ssd1289_bitmap_obj) }, +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_SSD1289_COLOR_BLACK) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_SSD1289_COLOR_WHITE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, +}; + +STATIC MP_DEFINE_CONST_DICT(lcd_ssd1289_locals_dict, lcd_ssd1289_locals_dict_table); + +const mp_obj_type_t lcd_ssd1289_type = { + { &mp_type_type }, + .name = MP_QSTR_SSD1289, + .print = lcd_ssd1289_print, + .make_new = lcd_ssd1289_make_new, + .locals_dict = (mp_obj_t)&lcd_ssd1289_locals_dict +}; + +#endif // MICROPY_PY_DISPLAY_LCD_SSD1289 diff --git a/nrf5/drivers/display/lcd_ssd1289_obj.h b/nrf5/drivers/display/lcd_ssd1289_obj.h new file mode 100644 index 0000000000..7105c110cc --- /dev/null +++ b/nrf5/drivers/display/lcd_ssd1289_obj.h @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LCD_SSD1289_H__ +#define LCD_SSD1289_H__ + +#include + +extern const mp_obj_type_t lcd_ssd1289_type; + +#endif // LCD_SSD1289_H__ + From 83b234f878491913a3c4477a959ad790c1788eaa Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 25 Jan 2017 19:49:30 +0100 Subject: [PATCH 238/809] nrf5: Adding ssd1289 driver and python module into build. --- nrf5/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index dcac81dcdd..fe935f0c15 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -157,6 +157,8 @@ DRIVERS_SRC_C += $(addprefix drivers/,\ display/lcd_ili9341_driver.c \ display/lcd_ls0xxb7dxxx_obj.c \ display/lcd_ls0xxb7dxxx_driver.c \ + display/lcd_ssd1289_obj.c \ + display/lcd_ssd1289_driver.c \ display/oled_ssd1305_obj.c \ display/oled_ssd1305_driver.c \ display/oled_ssd1306_obj.c \ From 0fdcd2eac7ef317d64ac95a4d89bc245b6676881 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 25 Jan 2017 19:51:14 +0100 Subject: [PATCH 239/809] nrf5/boards: Adding ssd1289 lcd module in pca10040 (nrf52832) board. --- nrf5/boards/pca10040/mpconfigboard.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 58e7aaff1a..9d1f14f559 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -40,6 +40,7 @@ #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) +#define MICROPY_PY_DISPLAY_LCD_SSD1289 (1) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) #define MICROPY_HW_HAS_SWITCH (0) From 197c052ca6851e02d8b46efcb6c3f33ecddd7af6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 25 Jan 2017 19:52:18 +0100 Subject: [PATCH 240/809] nrf5/drivers: Activate ssd1289 object in the display module. --- nrf5/drivers/display/moddisplay.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/nrf5/drivers/display/moddisplay.c b/nrf5/drivers/display/moddisplay.c index 1e14c4a449..ca4db0b454 100644 --- a/nrf5/drivers/display/moddisplay.c +++ b/nrf5/drivers/display/moddisplay.c @@ -31,6 +31,7 @@ #include "epaper_sld00200p_obj.h" #include "lcd_ili9341_obj.h" #include "lcd_ls0xxb7dxxx_obj.h" +#include "lcd_ssd1289_obj.h" #include "oled_ssd1305_obj.h" #include "oled_ssd1306_obj.h" @@ -45,15 +46,15 @@ STATIC const mp_map_elem_t mp_module_display_globals_table[] = { #if MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX { MP_OBJ_NEW_QSTR(MP_QSTR_LS0XXB7DXXX), (mp_obj_t)&lcd_ls0xxb7dxxx_type }, #endif +#if MICROPY_PY_DISPLAY_LCD_SSD1289 + { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1289), (mp_obj_t)&lcd_ssd1289_type }, +#endif #if MICROPY_PY_DISPLAY_OLED_SSD1305 { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1305), (mp_obj_t)&oled_ssd1305_type }, #endif #if MICROPY_PY_DISPLAY_OLED_SSD1306 { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1306), (mp_obj_t)&oled_ssd1306_type }, #endif -#if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1289), (mp_obj_t)&lcd_ssd1289_type } -#endif }; From 437f3d24773de75745ccf0f57c7cb08727a81788 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 21:24:31 +0100 Subject: [PATCH 241/809] nrf5/hal: Updating SPI hal with full list of SPI interfaces as lookup tables for all devices. Updating init struct to pass Pin instance pointers instead of uint pin number and ports. --- nrf5/hal/hal_spi.c | 18 ++++++------ nrf5/hal/hal_spi.h | 71 ++++++++++++++++++++++++++-------------------- 2 files changed, 50 insertions(+), 39 deletions(-) diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c index 1923d425d2..7218c69d6b 100644 --- a/nrf5/hal/hal_spi.c +++ b/nrf5/hal/hal_spi.c @@ -43,23 +43,23 @@ static const uint32_t hal_spi_frequency_lookup[] = { }; void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) { - hal_gpio_cfg_pin(p_spi_init->clk_pin_port, p_spi_init->clk_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_spi_init->mosi_pin_port, p_spi_init->mosi_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_spi_init->miso_pin_port, p_spi_init->miso_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->clk_pin->port, p_spi_init->clk_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->mosi_pin->port, p_spi_init->mosi_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->miso_pin->port, p_spi_init->miso_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); #if NRF51 p_instance->PSELSCK = p_spi_init->clk_pin; p_instance->PSELMOSI = p_spi_init->mosi_pin; p_instance->PSELMISO = p_spi_init->miso_pin; #else - p_instance->PSEL.SCK = p_spi_init->clk_pin; - p_instance->PSEL.MOSI = p_spi_init->mosi_pin; - p_instance->PSEL.MISO = p_spi_init->miso_pin; + p_instance->PSEL.SCK = p_spi_init->clk_pin->pin; + p_instance->PSEL.MOSI = p_spi_init->mosi_pin->pin; + p_instance->PSEL.MISO = p_spi_init->miso_pin->pin; #if NRF52840_XXAA - p_instance->PSEL.SCK |= (p_spi_init->clk_pin_port << SPI_PSEL_SCK_PORT_Pos); - p_instance->PSEL.MOSI |= (p_spi_init->mosi_pin_port << SPI_PSEL_MOSI_PORT_Pos); - p_instance->PSEL.MISO |= (p_spi_init->miso_pin_port << SPI_PSEL_MISO_PORT_Pos); + p_instance->PSEL.SCK |= (p_spi_init->clk_pin->port << SPI_PSEL_SCK_PORT_Pos); + p_instance->PSEL.MOSI |= (p_spi_init->mosi_pin->port << SPI_PSEL_MOSI_PORT_Pos); + p_instance->PSEL.MISO |= (p_spi_init->miso_pin->port << SPI_PSEL_MISO_PORT_Pos); #endif #endif diff --git a/nrf5/hal/hal_spi.h b/nrf5/hal/hal_spi.h index 1513b894dc..56e03dffec 100644 --- a/nrf5/hal/hal_spi.h +++ b/nrf5/hal/hal_spi.h @@ -31,36 +31,50 @@ #include "nrf.h" #if NRF51 - -#define SPI0 ((NRF_SPI_Type *) NRF_SPI0) -#define SPI0_IRQ_NUM SPI0_TWI0_IRQn -#define SPI1 ((NRF_SPI_Type *) NRF_SPI1) -#define SPI1_IRQ_NUM SPI1_TWI1_IRQn - -#elif NRF52 - -#define SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) -#define SPI0_IRQ_NUM SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn -#define SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) -#define SPI1_IRQ_NUM SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn -#define SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) -#define SPI2_IRQ_NUM SPIM2_SPIS2_SPI2_IRQn - -#else -#error "Device not supported." + #define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, NRF_SPI1_BASE} + #define SPI_IRQ_VALUES (const uint32_t[]){SPI0_TWI0_IRQn, SPI1_TWI1_IRQn} #endif +#if NRF52 + #ifdef NRF52832_XXAA + #define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, \ + NRF_SPI1_BASE, \ + NRF_SPI2_BASE} + #define SPI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, \ + SPIM2_SPIS2_SPI2_IRQn} + #endif + + #ifdef NRF52840_XXAA + #define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, \ + NRF_SPI1_BASE, \ + NRF_SPI2_BASE, \ + NRF_SPIM3_BASE} + #define SPI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, \ + SPIM2_SPIS2_SPI2_IRQn, \ + SPIM3_IRQn} + #endif +#endif + +#define SPI_BASE(x) ((NRF_SPI_Type *)SPI_BASE_POINTERS[x]) +#define SPI_IRQ_NUM(x) (SPI_IRQ_VALUES[x]) + /** * @brief SPI clock frequency type definition */ typedef enum { - HAL_FREQ_125_Kbps = 0, - HAL_FREQ_250_Kbps, - HAL_FREQ_500_Kbps, - HAL_FREQ_1_Mbps, - HAL_FREQ_2_Mbps, - HAL_FREQ_4_Mbps, - HAL_FREQ_8_Mbps + HAL_SPI_FREQ_125_Kbps = 0, + HAL_SPI_FREQ_250_Kbps, + HAL_SPI_FREQ_500_Kbps, + HAL_SPI_FREQ_1_Mbps, + HAL_SPI_FREQ_2_Mbps, + HAL_SPI_FREQ_4_Mbps, + HAL_SPI_FREQ_8_Mbps, +#if NRF52840_XXAA + HAL_SPI_FREQ_16_Mbps, + HAL_SPI_FREQ_32_Mbps +#endif } hal_spi_clk_freq_t; /** @@ -85,12 +99,9 @@ typedef enum { * @brief SPI Configuration Structure definition */ typedef struct { - uint8_t mosi_pin; - uint8_t miso_pin; - uint8_t clk_pin; - uint8_t mosi_pin_port; - uint8_t miso_pin_port; - uint8_t clk_pin_port; + const pin_obj_t * mosi_pin; + const pin_obj_t * miso_pin; + const pin_obj_t * clk_pin; hal_spi_firstbit_t firstbit; hal_spi_mode_t mode; uint32_t irq_priority; From 8653ac9ef8449794f88d5b218af34cf7f264f5d0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 21:27:59 +0100 Subject: [PATCH 242/809] nrf5/spi: Adding multiple instances of machine SPI depending on which chip is targeted (nrf51/nrf52832/nrf52540). Updating board config requirement to give variable name of const pointer to Pin instead of a Pin name. Adding support of giving keyword set mosi/miso/clk pin through constructor. --- nrf5/spi.c | 83 ++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 56 insertions(+), 27 deletions(-) diff --git a/nrf5/spi.c b/nrf5/spi.c index 7e3d831e88..c5956c806f 100644 --- a/nrf5/spi.c +++ b/nrf5/spi.c @@ -63,24 +63,41 @@ /// spi.send_recv(b'1234', buf) # send 4 bytes and receive 4 into buf /// spi.send_recv(buf, buf) # send/recv 4 bytes from/to buf -#if defined(MICROPY_HW_SPI0_SCK) SPI_HandleTypeDef SPIHandle0 = {.instance = NULL}; -#endif +SPI_HandleTypeDef SPIHandle1 = {.instance = NULL}; +#if NRF52 +SPI_HandleTypeDef SPIHandle2 = {.instance = NULL}; +#if NRF52840_XXAA +SPI_HandleTypeDef SPIHandle3 = {.instance = NULL}; // 32 Mbs master only +#endif // NRF52840_XXAA +#endif // NRF52 STATIC const pyb_spi_obj_t machine_spi_obj[] = { - #if defined(MICROPY_HW_SPI0_SCK) {{&machine_hard_spi_type}, &SPIHandle0}, - #else - {{&machine_hard_spi_type}, NULL}, - #endif + {{&machine_hard_spi_type}, &SPIHandle1}, +#if NRF52 + {{&machine_hard_spi_type}, &SPIHandle2}, +#if NRF52840_XXAA + {{&machine_hard_spi_type}, &SPIHandle3}, +#endif // NRF52840_XXAA +#endif // NRF52 + }; void spi_init0(void) { // reset the SPI handles - #if defined(MICROPY_HW_SPI0_SCK) memset(&SPIHandle0, 0, sizeof(SPI_HandleTypeDef)); - SPIHandle0.instance = SPI0; - #endif + SPIHandle0.instance = SPI_BASE(0); + memset(&SPIHandle1, 0, sizeof(SPI_HandleTypeDef)); + SPIHandle1.instance = SPI_BASE(1); +#if NRF52 + memset(&SPIHandle2, 0, sizeof(SPI_HandleTypeDef)); + SPIHandle2.instance = SPI_BASE(2); +#if NRF52840_XXAA + memset(&SPIHandle3, 0, sizeof(SPI_HandleTypeDef)); + SPIHandle3.instance = SPI_BASE(3); +#endif // NRF52840_XXAA +#endif // NRF52 } STATIC int spi_find(mp_obj_t id) { @@ -114,7 +131,7 @@ void spi_deinit(SPI_HandleTypeDef *spi) { } STATIC void spi_transfer(const pyb_spi_obj_t * self, size_t len, const void * src, void * dest) { - hal_spi_master_tx_rx(self->spi->instance, len, src, dest); + hal_spi_master_tx_rx(self->spi->instance, len, src, dest); } STATIC void spi_print(const mp_print_t *print, SPI_HandleTypeDef *spi, bool legacy) { @@ -231,6 +248,13 @@ STATIC MP_DEFINE_CONST_DICT(machine_spi_locals_dict, machine_spi_locals_dict_tab STATIC const machine_hard_spi_obj_t machine_hard_spi_obj[] = { {{&machine_hard_spi_type}, &machine_spi_obj[0]}, + {{&machine_hard_spi_type}, &machine_spi_obj[1]}, +#if NRF52 + {{&machine_hard_spi_type}, &machine_spi_obj[2]}, +#if NRF52840_XXAA + {{&machine_hard_spi_type}, &machine_spi_obj[3]}, +#endif +#endif }; STATIC void machine_hard_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { @@ -248,34 +272,39 @@ STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) { && args[ARG_NEW_mosi].u_obj != MP_OBJ_NULL && args[ARG_NEW_miso].u_obj != MP_OBJ_NULL) { - self->pyb->spi->init.clk_pin = mp_obj_get_int(args[ARG_NEW_sck].u_obj); - self->pyb->spi->init.mosi_pin = mp_obj_get_int(args[ARG_NEW_mosi].u_obj); - self->pyb->spi->init.miso_pin = mp_obj_get_int(args[ARG_NEW_miso].u_obj); + self->pyb->spi->init.clk_pin = args[ARG_NEW_sck].u_obj; + self->pyb->spi->init.mosi_pin = args[ARG_NEW_mosi].u_obj; + self->pyb->spi->init.miso_pin = args[ARG_NEW_miso].u_obj; } else { - self->pyb->spi->init.clk_pin = MICROPY_HW_SPI0_SCK; - self->pyb->spi->init.mosi_pin = MICROPY_HW_SPI0_MOSI; - self->pyb->spi->init.miso_pin = MICROPY_HW_SPI0_MISO; - self->pyb->spi->init.clk_pin_port = MICROPY_HW_SPI0_SCK_PORT; - self->pyb->spi->init.mosi_pin_port = MICROPY_HW_SPI0_MOSI_PORT; - self->pyb->spi->init.miso_pin_port = MICROPY_HW_SPI0_MISO_PORT; + self->pyb->spi->init.clk_pin = &MICROPY_HW_SPI0_SCK; + self->pyb->spi->init.mosi_pin = &MICROPY_HW_SPI0_MOSI; + self->pyb->spi->init.miso_pin = &MICROPY_HW_SPI0_MISO; } int baudrate = args[ARG_NEW_baudrate].u_int; if (baudrate <= 125000) { - self->pyb->spi->init.freq = HAL_FREQ_125_Kbps; + self->pyb->spi->init.freq = HAL_SPI_FREQ_125_Kbps; } else if (baudrate <= 250000) { - self->pyb->spi->init.freq = HAL_FREQ_250_Kbps; + self->pyb->spi->init.freq = HAL_SPI_FREQ_250_Kbps; } else if (baudrate <= 500000) { - self->pyb->spi->init.freq = HAL_FREQ_500_Kbps; + self->pyb->spi->init.freq = HAL_SPI_FREQ_500_Kbps; } else if (baudrate <= 1000000) { - self->pyb->spi->init.freq = HAL_FREQ_1_Mbps; + self->pyb->spi->init.freq = HAL_SPI_FREQ_1_Mbps; } else if (baudrate <= 2000000) { - self->pyb->spi->init.freq = HAL_FREQ_2_Mbps; + self->pyb->spi->init.freq = HAL_SPI_FREQ_2_Mbps; } else if (baudrate <= 4000000) { - self->pyb->spi->init.freq = HAL_FREQ_4_Mbps; - } else { - self->pyb->spi->init.freq = HAL_FREQ_8_Mbps; + self->pyb->spi->init.freq = HAL_SPI_FREQ_4_Mbps; + } else if (baudrate <= 8000000) { + self->pyb->spi->init.freq = HAL_SPI_FREQ_8_Mbps; +#if NRF52840_XXAA + } else if (baudrate <= 16000000) { + self->pyb->spi->init.freq = HAL_SPI_FREQ_16_Mbps; + } else if (baudrate <= 32000000) { + self->pyb->spi->init.freq = HAL_SPI_FREQ_32_Mbps; +#endif + } else { // Default + self->pyb->spi->init.freq = HAL_SPI_FREQ_1_Mbps; } self->pyb->spi->init.irq_priority = 4; From f94836ef74a3ccb952add9c55d2fe9b236cf473d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 21:29:24 +0100 Subject: [PATCH 243/809] nrf5: Updating main.c to enable SPI if MICROPY_PY_MACHINE_HW_SPI is set. This diverge from regular MICROPY_PY_MACHINE_SPI config. Fixing missing init of SPI after renaming port SPI enable define. --- nrf5/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/main.c b/nrf5/main.c index 61202f09b0..5b52975d82 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -103,7 +103,7 @@ int main(int argc, char **argv) { pin_init0(); -#if MICROPY_PY_MACHINE_SPI +#if MICROPY_PY_MACHINE_HW_SPI spi_init0(); #endif From afcf07ca7634fad1ca345f456dba65415478ec80 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 21:31:24 +0100 Subject: [PATCH 244/809] nrf5: Updating modmachine to add SPI in globals dict when MICROPY_PY_MACHINE_HW_SPI define is set. This diverge from regular MICROPY_PY_MACHINE_SPI config. Fixes missing SPI in the machine module after renaming port SPI enable define. --- nrf5/modmachine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modmachine.c b/nrf5/modmachine.c index 1826135baa..fdff283803 100644 --- a/nrf5/modmachine.c +++ b/nrf5/modmachine.c @@ -168,7 +168,7 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_deepsleep), (mp_obj_t)&machine_deepsleep_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_reset_cause), (mp_obj_t)&machine_reset_cause_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_Pin), (mp_obj_t)&pin_type }, -#if MICROPY_PY_MACHINE_SPI +#if MICROPY_PY_MACHINE_HW_SPI { MP_OBJ_NEW_QSTR(MP_QSTR_SPI), (mp_obj_t)&machine_hard_spi_type }, #endif #if MICROPY_PY_MACHINE_ADC From 3c6c6c6d0599d23232949a6e34a02527e6a4945d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 21:57:38 +0100 Subject: [PATCH 245/809] nrf5/hal: Updating uart hal to use pointers to Pin objects instead of uint pin and port number. --- nrf5/hal/hal_uart.h | 20 ++++++++------------ nrf5/hal/hal_uarte.c | 30 ++++++++++++++++++++---------- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/nrf5/hal/hal_uart.h b/nrf5/hal/hal_uart.h index 32e91ad6f4..48c39ca1b2 100644 --- a/nrf5/hal/hal_uart.h +++ b/nrf5/hal/hal_uart.h @@ -109,18 +109,14 @@ typedef struct } UART_HandleTypeDef; typedef struct { - uint8_t rx_pin; /**< RX pin number. */ - uint8_t tx_pin; /**< TX pin number. */ - uint8_t rts_pin; /**< RTS pin number, only used if flow control is enabled. */ - uint8_t cts_pin; /**< CTS pin number, only used if flow control is enabled. */ - uint8_t rx_pin_port; /**< RX port number. */ - uint8_t tx_pin_port; /**< TX port number. */ - uint8_t rts_pin_port; /**< RTS port number, only used if flow control is enabled. */ - uint8_t cts_pin_port; /**< CTS port number, only used if flow control is enabled. */ - bool flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ - bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ - uint32_t baud_rate; /**< Baud rate configuration. */ - uint32_t irq_priority; /**< UARTE IRQ priority. */ + const pin_obj_t * rx_pin; /**< RX pin. */ + const pin_obj_t * tx_pin; /**< TX pin. */ + const pin_obj_t * rts_pin; /**< RTS pin, only used if flow control is enabled. */ + const pin_obj_t * cts_pin; /**< CTS pin, only used if flow control is enabled. */ + bool flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ + bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ + uint32_t baud_rate; /**< Baud rate configuration. */ + uint32_t irq_priority; /**< UARTE IRQ priority. */ } hal_uart_init_t; diff --git a/nrf5/hal/hal_uarte.c b/nrf5/hal/hal_uarte.c index 496c40e9b1..cde143502c 100644 --- a/nrf5/hal/hal_uarte.c +++ b/nrf5/hal/hal_uarte.c @@ -83,9 +83,9 @@ void nrf_sendchar(int ch) { } void nrf_uart_init(hal_uart_init_t const * p_uart_init) { - hal_gpio_cfg_pin(p_uart_init->tx_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_pin_set(p_uart_init->tx_pin); - hal_gpio_cfg_pin(p_uart_init->rx_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_pin_set(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin); + hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); UARTE_BASE->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]); @@ -99,16 +99,26 @@ void nrf_uart_init(hal_uart_init_t const * p_uart_init) { UARTE_BASE->CONFIG = (uint32_t)hwfc | (uint32_t)parity; - UARTE_BASE->PSEL.RXD = p_uart_init->rx_pin; - UARTE_BASE->PSEL.TXD = p_uart_init->tx_pin; + UARTE_BASE->PSEL.RXD = p_uart_init->rx_pin->pin; + UARTE_BASE->PSEL.TXD = p_uart_init->tx_pin->pin; + +#if NRF52840_XXAA + UARTE_BASE->PSEL.RXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos); + UARTE_BASE->PSEL.TXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos); +#endif if (hwfc) { - hal_gpio_cfg_pin(p_uart_init->cts_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_uart_init->rts_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_pin_set(p_uart_init->rts_pin); + hal_gpio_cfg_pin(p_uart_init->cts_pin->port, p_uart_init->cts_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_pin_set(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin); - UARTE_BASE->PSEL.RTS = p_uart_init->rts_pin; - UARTE_BASE->PSEL.CTS = p_uart_init->cts_pin; + UARTE_BASE->PSEL.RTS = p_uart_init->rts_pin->pin; + UARTE_BASE->PSEL.CTS = p_uart_init->cts_pin->pin; + +#if NRF52840_XXAA + UARTE_BASE->PSEL.RTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_RTS_PORT_Pos); + UARTE_BASE->PSEL.CTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_CTS_PORT_Pos); +#endif } nrf_uart_irq_enable(p_uart_init->irq_priority); From d87d0141b35cff81c11e68eb231525e418b8f326 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 21:58:12 +0100 Subject: [PATCH 246/809] nrf5/hal: Updating uart hal to use pointers to Pin objects instead of uint pin and port number. --- nrf5/hal/hal_uart.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/nrf5/hal/hal_uart.c b/nrf5/hal/hal_uart.c index a9e3698e69..c2fa9085a0 100644 --- a/nrf5/hal/hal_uart.c +++ b/nrf5/hal/hal_uart.c @@ -100,32 +100,29 @@ void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_comple } void nrf_uart_init(hal_uart_init_t const * p_uart_init) { - hal_gpio_cfg_pin(p_uart_init->tx_pin_port, p_uart_init->tx_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_uart_init->tx_pin_port, p_uart_init->rx_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_pin_clear(p_uart_init->tx_pin_port, p_uart_init->tx_pin); + hal_gpio_pin_clear(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin); + + UART_BASE->PSELTXD = p_uart_init->tx_pin->pin; + UART_BASE->PSELRXD = p_uart_init->rx_pin->pin; - UART_BASE->PSELTXD = p_uart_init->tx_pin; #if NRF52840_XXAA - UART_BASE->PSELTXD |= (p_uart_init->tx_pin_port << UARTE_PSEL_TXD_PORT_Pos); -#endif - UART_BASE->PSELRXD = p_uart_init->rx_pin; -#if NRF52840_XXAA - UART_BASE->PSELRXD |= (p_uart_init->rx_pin_port << UARTE_PSEL_RXD_PORT_Pos); + UART_BASE->PSELTXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos); + UART_BASE->PSELRXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos); #endif + if (p_uart_init->flow_control) { -#if MICROPY_HW_UART1_HWFC - hal_gpio_cfg_pin(p_uart_init->rts_pin_port, p_uart_init->rts_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_uart_init->cts_pin_port, p_uart_init->cts_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_uart_init->cts_pin->port, p_uart_init->cts_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); + + UART_BASE->PSELCTS = p_uart_init->cts_pin->pin; + UART_BASE->PSELRTS = p_uart_init->rts_pin->pin; - UART_BASE->PSELCTS = p_uart_init->cts_pin; #if NRF52840_XXAA - UART_BASE->PSELCTS |= (p_uart_init->cts_pin_port << UARTE_PSEL_CTS_PORT_Pos); -#endif - UART_BASE->PSELRTS = p_uart_init->rts_pin; -#if NRF52840_XXAA - UART_BASE->PSELRTS |= (p_uart_init->rts_pin_port << UARTE_PSEL_RTS_PORT_Pos); -#endif + UART_BASE->PSELCTS |= (p_uart_init->cts_pin->port << UARTE_PSEL_CTS_PORT_Pos); + UART_BASE->PSELRTS |= (p_uart_init->rts_pin->port << UARTE_PSEL_RTS_PORT_Pos); #endif UART_BASE->CONFIG = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos); From 632afd1fa81a9cd72af4f4eb4696948d9b7b381b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 21:59:37 +0100 Subject: [PATCH 247/809] nrf5/uart: Updating uart module to use new config hal config structure members for pins. Changing board config provided pins to use const pointers from generated pins instead of pin name. --- nrf5/uart.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/nrf5/uart.c b/nrf5/uart.c index a510c834a9..98370378bb 100644 --- a/nrf5/uart.c +++ b/nrf5/uart.c @@ -34,6 +34,8 @@ #include "py/stream.h" #include "py/mperrno.h" #include "py/mphal.h" +#include "pin.h" +#include "genhdr/pins.h" #include "uart.h" #include "mpconfigboard.h" @@ -215,16 +217,12 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, con .irq_priority = 6 #endif }; - uart_init.rx_pin = MICROPY_HW_UART1_RX; - uart_init.tx_pin = MICROPY_HW_UART1_TX; - uart_init.rx_pin_port = MICROPY_HW_UART1_RX_PORT; - uart_init.tx_pin_port = MICROPY_HW_UART1_TX_PORT; + uart_init.rx_pin = &MICROPY_HW_UART1_RX; + uart_init.tx_pin = &MICROPY_HW_UART1_TX; #if MICROPY_HW_UART1_HWFC - uart_init.rts_pin = MICROPY_HW_UART1_RTS; - uart_init.cts_pin = MICROPY_HW_UART1_CTS; - uart_init.rts_pin_port = MICROPY_HW_UART1_RTS_PORT; - uart_init.cts_pin_port = MICROPY_HW_UART1_CTS_PORT; + uart_init.rts_pin = &MICROPY_HW_UART1_RTS; + uart_init.cts_pin = &MICROPY_HW_UART1_CTS; #endif nrf_uart_init(&uart_init); From 0254cab228794e3e63780ceb91b216695ff15b57 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 22:01:43 +0100 Subject: [PATCH 248/809] nrf5/hal: Updating SPI DMA variant with more frequencies, and allowing rx and tx buffers to be NULL. --- nrf5/hal/hal_spie.c | 90 ++++++++++++++++++++------------------------- 1 file changed, 39 insertions(+), 51 deletions(-) diff --git a/nrf5/hal/hal_spie.c b/nrf5/hal/hal_spie.c index dd1a8865ef..994f9914d1 100644 --- a/nrf5/hal/hal_spie.c +++ b/nrf5/hal/hal_spie.c @@ -32,51 +32,36 @@ #ifdef HAL_SPIE_MODULE_ENABLED -#if NRF52 - -#define SPIM0 ((NRF_SPI_Type *) NRF_SPIM0_BASE) -#define SPIM0_IRQ_NUM SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn -#define SPIM1 ((NRF_SPI_Type *) NRF_SPIM1_BASE) -#define SPIM1_IRQ_NUM SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn -#define SPIM2 ((NRF_SPI_Type *) NRF_SPIM2_BASE) -#define SPIM2_IRQ_NUM SPIM2_SPIS2_SPI2_IRQn - -#else -#error "Device not supported." -#endif - -static uint32_t m_ss_pin; - static const uint32_t hal_spi_frequency_lookup[] = { - SPI_FREQUENCY_FREQUENCY_K125, // 125 kbps - SPI_FREQUENCY_FREQUENCY_K250, // 250 kbps - SPI_FREQUENCY_FREQUENCY_K500, // 500 kbps - SPI_FREQUENCY_FREQUENCY_M1, // 1 Mbps - SPI_FREQUENCY_FREQUENCY_M2, // 2 Mbps - SPI_FREQUENCY_FREQUENCY_M4, // 4 Mbps - SPI_FREQUENCY_FREQUENCY_M8 // 8 Mbps + SPIM_FREQUENCY_FREQUENCY_K125, // 125 kbps + SPIM_FREQUENCY_FREQUENCY_K250, // 250 kbps + SPIM_FREQUENCY_FREQUENCY_K500, // 500 kbps + SPIM_FREQUENCY_FREQUENCY_M1, // 1 Mbps + SPIM_FREQUENCY_FREQUENCY_M2, // 2 Mbps + SPIM_FREQUENCY_FREQUENCY_M4, // 4 Mbps + SPIM_FREQUENCY_FREQUENCY_M8, // 8 Mbps +#if NRF52840_XXAA + SPIM_FREQUENCY_FREQUENCY_M16, // 16 Mbps + SPIM_FREQUENCY_FREQUENCY_M32, // 32 Mbps +#endif }; void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) { - // cast to master type - NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance; + // cast to master type + NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance; - hal_gpio_pin_set(p_spi_init->enable_pin); - m_ss_pin = p_spi_init->enable_pin; + hal_gpio_cfg_pin(p_spi_init->clk_pin->port, p_spi_init->clk_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->mosi_pin->port, p_spi_init->mosi_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + hal_gpio_cfg_pin(p_spi_init->miso_pin->port, p_spi_init->miso_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_spi_init->clk_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_spi_init->mosi_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_spi_init->miso_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); - hal_gpio_cfg_pin(p_spi_init->enable_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); + spim_instance->PSEL.SCK = p_spi_init->clk_pin->pin; + spim_instance->PSEL.MOSI = p_spi_init->mosi_pin->pin; + spim_instance->PSEL.MISO = p_spi_init->miso_pin->pin; -#if NRF51 - spim_instance->PSELSCK = p_spi_init->clk_pin; - spim_instance->PSELMOSI = p_spi_init->mosi_pin; - spim_instance->PSELMISO = p_spi_init->miso_pin; -#else - spim_instance->PSEL.SCK = p_spi_init->clk_pin; - spim_instance->PSEL.MOSI = p_spi_init->mosi_pin; - spim_instance->PSEL.MISO = p_spi_init->miso_pin; +#if NRF52840_XXAA + spim_instance->PSEL.SCK |= (p_spi_init->clk_pin->port << SPIM_PSEL_SCK_PORT_Pos); + spim_instance->PSEL.MOSI |= (p_spi_init->mosi_pin->port << SPIM_PSEL_MOSI_PORT_Pos); + spim_instance->PSEL.MISO |= (p_spi_init->miso_pin->port << SPIM_PSEL_MISO_PORT_Pos); #endif spim_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq]; @@ -100,7 +85,7 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi break; } - if (p_spi_init->lsb_first) { + if (p_spi_init->firstbit == HAL_SPI_LSB_FIRST) { spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_LsbFirst << SPIM_CONFIG_ORDER_Pos)); } else { spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos)); @@ -112,24 +97,27 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, const uint8_t * tx_data, uint8_t * rx_data) { - // cast to master type - NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance; + // cast to master type + NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance; - hal_gpio_pin_clear(m_ss_pin); + if (tx_data != NULL) { + spim_instance->TXD.PTR = (uint32_t)(tx_data); + spim_instance->TXD.MAXCNT = transfer_size; + } - spim_instance->TXD.PTR = (uint32_t)(tx_data); - spim_instance->TXD.MAXCNT = transfer_size; - spim_instance->RXD.PTR = (uint32_t)(rx_data); - spim_instance->RXD.MAXCNT = transfer_size; + if (rx_data != NULL) { + spim_instance->RXD.PTR = (uint32_t)(rx_data); + spim_instance->RXD.MAXCNT = transfer_size; + } spim_instance->TASKS_START = 1; - while((0 == spim_instance->EVENTS_END)); + while(spim_instance->EVENTS_END != 1) { + ; + } - spim_instance->EVENTS_END = 0; - spim_instance->TASKS_STOP = 1; - - hal_gpio_pin_set(m_ss_pin); + spim_instance->EVENTS_END = 0; + spim_instance->TASKS_STOP = 1; } #endif // HAL_SPIE_MODULE_ENABLED From b4d53ad560646d127a558059d9a43b5d322af216 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 22:08:39 +0100 Subject: [PATCH 249/809] nrf5/drivers: Updating display objects to use new SPI pin configuration in print function. --- nrf5/drivers/display/epaper_sld00200p_obj.c | 14 +++++++------- nrf5/drivers/display/lcd_ili9341_obj.c | 13 ++++++------- nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c | 9 ++++----- nrf5/drivers/display/oled_ssd1305_obj.c | 13 ++++++------- nrf5/drivers/display/oled_ssd1306_obj.c | 13 ++++++------- 5 files changed, 29 insertions(+), 33 deletions(-) diff --git a/nrf5/drivers/display/epaper_sld00200p_obj.c b/nrf5/drivers/display/epaper_sld00200p_obj.c index b2d02c4375..df2d5d6d98 100644 --- a/nrf5/drivers/display/epaper_sld00200p_obj.c +++ b/nrf5/drivers/display/epaper_sld00200p_obj.c @@ -84,13 +84,13 @@ STATIC void epaper_sld00200_print(const mp_print_t *print, mp_obj_t o, mp_print_ epaper_sld00200p_obj_t *self = o; mp_printf(print, "SLD00200(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin_port, - self->spi->pyb->spi->init.mosi_pin, - self->spi->pyb->spi->init.miso_pin_port, - self->spi->pyb->spi->init.miso_pin, - self->spi->pyb->spi->init.clk_pin_port, - self->spi->pyb->spi->init.clk_pin - ); + self->spi->pyb->spi->init.mosi_pin->port, + self->spi->pyb->spi->init.mosi_pin->pin, + self->spi->pyb->spi->init.miso_pin->port, + self->spi->pyb->spi->init.miso_pin->pin, + self->spi->pyb->spi->init.clk_pin->port, + self->spi->pyb->spi->init.clk_pin->pin); + mp_printf(print, " PWM(pwm_pin=%u),\n", self->pwm->pyb->pwm->init.pwm_pin); diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/drivers/display/lcd_ili9341_obj.c index facd8b8728..968b3bf858 100644 --- a/nrf5/drivers/display/lcd_ili9341_obj.c +++ b/nrf5/drivers/display/lcd_ili9341_obj.c @@ -74,13 +74,12 @@ STATIC void lcd_ili9341_print(const mp_print_t *print, mp_obj_t o, mp_print_kind lcd_ili9341_obj_t *self = o; mp_printf(print, "ILI9341(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin_port, - self->spi->pyb->spi->init.mosi_pin, - self->spi->pyb->spi->init.miso_pin_port, - self->spi->pyb->spi->init.miso_pin, - self->spi->pyb->spi->init.clk_pin_port, - self->spi->pyb->spi->init.clk_pin - ); + self->spi->pyb->spi->init.mosi_pin->port, + self->spi->pyb->spi->init.mosi_pin->pin, + self->spi->pyb->spi->init.miso_pin->port, + self->spi->pyb->spi->init.miso_pin->pin, + self->spi->pyb->spi->init.clk_pin->port, + self->spi->pyb->spi->init.clk_pin->pin); mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u),\n", self->pin_cs->port, diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c index 63a48eb3d1..afbc1f6203 100644 --- a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c +++ b/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c @@ -76,11 +76,10 @@ STATIC void lcd_ls0xxb7dxxx_print(const mp_print_t *print, mp_obj_t o, mp_print_ lcd_ls0xxb7dxxx_obj_t *self = o; mp_printf(print, "LS0XXB7DXXX(SPI(mosi=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin_port, - self->spi->pyb->spi->init.mosi_pin, - self->spi->pyb->spi->init.clk_pin_port, - self->spi->pyb->spi->init.clk_pin - ); + self->spi->pyb->spi->init.mosi_pin->port, + self->spi->pyb->spi->init.mosi_pin->pin, + self->spi->pyb->spi->init.clk_pin->port, + self->spi->pyb->spi->init.clk_pin->pin); mp_printf(print, " cs=(port=%u, pin=%u), disp=(port=%u, pin=%u), extcomin=(port=%u, pin=%u),\n", self->pin_cs->port, diff --git a/nrf5/drivers/display/oled_ssd1305_obj.c b/nrf5/drivers/display/oled_ssd1305_obj.c index 84874b6e70..59b52ee277 100644 --- a/nrf5/drivers/display/oled_ssd1305_obj.c +++ b/nrf5/drivers/display/oled_ssd1305_obj.c @@ -73,13 +73,12 @@ STATIC void oled_ssd1305_print(const mp_print_t *print, mp_obj_t o, mp_print_kin oled_ssd1305_obj_t *self = o; mp_printf(print, "SSD1305(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin_port, - self->spi->pyb->spi->init.mosi_pin, - self->spi->pyb->spi->init.miso_pin_port, - self->spi->pyb->spi->init.miso_pin, - self->spi->pyb->spi->init.clk_pin_port, - self->spi->pyb->spi->init.clk_pin - ); + self->spi->pyb->spi->init.mosi_pin->port, + self->spi->pyb->spi->init.mosi_pin->pin, + self->spi->pyb->spi->init.miso_pin->port, + self->spi->pyb->spi->init.miso_pin->pin, + self->spi->pyb->spi->init.clk_pin->port, + self->spi->pyb->spi->init.clk_pin->pin); mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u), reset=(port=%u, pin=%u),\n", self->pin_cs->port, diff --git a/nrf5/drivers/display/oled_ssd1306_obj.c b/nrf5/drivers/display/oled_ssd1306_obj.c index c6410bcd8a..55e5094996 100644 --- a/nrf5/drivers/display/oled_ssd1306_obj.c +++ b/nrf5/drivers/display/oled_ssd1306_obj.c @@ -73,13 +73,12 @@ STATIC void oled_ssd1306_print(const mp_print_t *print, mp_obj_t o, mp_print_kin oled_ssd1306_obj_t *self = o; mp_printf(print, "SSD1306(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin_port, - self->spi->pyb->spi->init.mosi_pin, - self->spi->pyb->spi->init.miso_pin_port, - self->spi->pyb->spi->init.miso_pin, - self->spi->pyb->spi->init.clk_pin_port, - self->spi->pyb->spi->init.clk_pin - ); + self->spi->pyb->spi->init.mosi_pin->port, + self->spi->pyb->spi->init.mosi_pin->pin, + self->spi->pyb->spi->init.miso_pin->port, + self->spi->pyb->spi->init.miso_pin->pin, + self->spi->pyb->spi->init.clk_pin->port, + self->spi->pyb->spi->init.clk_pin->pin); mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u), reset=(port=%u, pin=%u),\n", self->pin_cs->port, From 0b0cb196083e4171468dda2cca37c822a2e11b9f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 22:10:36 +0100 Subject: [PATCH 250/809] nrf5/hal: Updating hal QSPI header with define guard to filter out usage of undefined structures and names when compiling against non-52840 targets. --- nrf5/hal/hal_qspie.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_qspie.h b/nrf5/hal/hal_qspie.h index 99c1c4cee9..85b9a6021f 100644 --- a/nrf5/hal/hal_qspie.h +++ b/nrf5/hal/hal_qspie.h @@ -27,6 +27,8 @@ #ifndef HAL_QSPIE_H__ #define HAL_QSPIE_H__ +#ifdef HAL_QSPIE_MODULE_ENABLED + #if NRF52840_XXAA #include @@ -60,7 +62,7 @@ typedef enum { typedef enum { HAL_QSPI_DATA_LINE_SINGLE, HAL_QSPI_DATA_LINE_DUAL, - HAL_QSPI_DATA_LINE_QUAL + HAL_QSPI_DATA_LINE_QUAD } hal_qspi_data_line_t; @@ -103,4 +105,6 @@ void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance, const uint8_t * tx_data, uint8_t * rx_data); +#endif // HAL_QSPIE_MODULE_ENABLED + #endif // HAL_QSPIE_H__ From 6387490e4a9eba61dbae91eeaa2ea097644a8067 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 22:15:35 +0100 Subject: [PATCH 251/809] nrf5/boards: Updating board configuration for pca10056 (nrf52840) with new pin configuration scheme for SPI and UART. --- nrf5/boards/pca10056/mpconfigboard.h | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index cf711ae1bb..e46765f67c 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -62,27 +62,18 @@ #define MICROPY_HW_LED4 (16) // LED4 // UART config -#define MICROPY_HW_UART1_RX (8) -#define MICROPY_HW_UART1_TX (6) -#define MICROPY_HW_UART1_CTS (7) -#define MICROPY_HW_UART1_RTS (5) - -#define MICROPY_HW_UART1_RX_PORT (0) -#define MICROPY_HW_UART1_TX_PORT (0) -#define MICROPY_HW_UART1_CTS_PORT (0) -#define MICROPY_HW_UART1_RTS_PORT (0) - +#define MICROPY_HW_UART1_RX (pin_A8) +#define MICROPY_HW_UART1_TX (pin_A6) +#define MICROPY_HW_UART1_CTS (pin_A7) +#define MICROPY_HW_UART1_RTS (pin_A5) #define MICROPY_HW_UART1_HWFC (1) // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" -#define MICROPY_HW_SPI0_SCK (15) // B15 (Arduino D13) -#define MICROPY_HW_SPI0_MOSI (13) // B13 (Arduino D11) -#define MICROPY_HW_SPI0_MISO (14) // B14 (Arduino D12) -#define MICROPY_HW_SPI0_SCK_PORT (1) -#define MICROPY_HW_SPI0_MOSI_PORT (1) -#define MICROPY_HW_SPI0_MISO_PORT (1) +#define MICROPY_HW_SPI0_SCK (pin_B15) +#define MICROPY_HW_SPI0_MOSI (pin_B13) +#define MICROPY_HW_SPI0_MISO (pin_B14) #define MICROPY_HW_PWM0_NAME "PWM0" #define MICROPY_HW_PWM1_NAME "PWM1" From 9009ad67b031d2d4a9a566d504cd27f029ca3dc3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 22:29:58 +0100 Subject: [PATCH 252/809] nrf5/boards: Updating boards to comply to new style of configuring pins for uart and spi. --- nrf5/boards/microbit/mpconfigboard.h | 6 ++---- nrf5/boards/pca10000/mpconfigboard.h | 6 ++---- nrf5/boards/pca10001/mpconfigboard.h | 12 ++++-------- nrf5/boards/pca10028/mpconfigboard.h | 24 +++++++++--------------- nrf5/boards/pca10031/mpconfigboard.h | 21 +++++++-------------- nrf5/boards/pca10040/mpconfigboard.h | 23 +++++++---------------- 6 files changed, 31 insertions(+), 61 deletions(-) diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index 7de7f4ac95..fd5fc7dfed 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -59,10 +59,8 @@ #define MICROPY_HW_LED4 (24) // LED4 // UART config -#define MICROPY_HW_UART1_RX (25) -#define MICROPY_HW_UART1_TX (24) -#define MICROPY_HW_UART1_RX_PORT (0) -#define MICROPY_HW_UART1_TX_PORT (0) +#define MICROPY_HW_UART1_RX (pin_A25) +#define MICROPY_HW_UART1_TX (pin_A24) #define MICROPY_HW_UART1_HWFC (0) #define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf5/boards/pca10000/mpconfigboard.h index 01840d26e8..ac955eb61b 100644 --- a/nrf5/boards/pca10000/mpconfigboard.h +++ b/nrf5/boards/pca10000/mpconfigboard.h @@ -54,10 +54,8 @@ #define MICROPY_HW_LED_BLUE (23) // BLUE // UART config -#define MICROPY_HW_UART1_RX (11) -#define MICROPY_HW_UART1_TX (9) -#define MICROPY_HW_UART1_RX_PORT (0) -#define MICROPY_HW_UART1_TX_PORT (0) +#define MICROPY_HW_UART1_RX (pin_A11) +#define MICROPY_HW_UART1_TX (pin_A9) #define MICROPY_HW_UART1_HWFC (0) #define HELP_TEXT_BOARD_LED "1,2,3" diff --git a/nrf5/boards/pca10001/mpconfigboard.h b/nrf5/boards/pca10001/mpconfigboard.h index 06570af7c4..8380dcf76d 100644 --- a/nrf5/boards/pca10001/mpconfigboard.h +++ b/nrf5/boards/pca10001/mpconfigboard.h @@ -53,14 +53,10 @@ #define MICROPY_HW_LED2 (19) // LED2 // UART config -#define MICROPY_HW_UART1_RX (11) -#define MICROPY_HW_UART1_TX (9) -#define MICROPY_HW_UART1_CTS (10) -#define MICROPY_HW_UART1_RTS (8) -#define MICROPY_HW_UART1_RX_PORT (0) -#define MICROPY_HW_UART1_TX_PORT (0) -#define MICROPY_HW_UART1_RTS_PORT (0) -#define MICROPY_HW_UART1_CTS_PORT (0) +#define MICROPY_HW_UART1_RX (pin_A11) +#define MICROPY_HW_UART1_TX (pin_A9) +#define MICROPY_HW_UART1_CTS (pin_A10) +#define MICROPY_HW_UART1_RTS (pin_A8) #define MICROPY_HW_UART1_HWFC (1) #define HELP_TEXT_BOARD_LED "1,2" diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 1b558b3b7f..26b62cc361 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -33,7 +33,8 @@ #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) -#define MICROPY_PY_DISPLAY_OLED_SSD1305 (1) +#define MICROPY_PY_DISPLAY_LCD_SSD1289 (1) +#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #define MICROPY_PY_MACHINE_HW_SPI (1) @@ -67,23 +68,16 @@ #define MICROPY_HW_LED4 (24) // LED4 // UART config -#define MICROPY_HW_UART1_RX (11) -#define MICROPY_HW_UART1_TX (9) -#define MICROPY_HW_UART1_CTS (10) -#define MICROPY_HW_UART1_RTS (8) -#define MICROPY_HW_UART1_RX_PORT (0) -#define MICROPY_HW_UART1_TX_PORT (0) -#define MICROPY_HW_UART1_CTS_PORT (0) -#define MICROPY_HW_UART1_RTS_PORT (0) +#define MICROPY_HW_UART1_RX (pin_A11) +#define MICROPY_HW_UART1_TX (pin_A9) +#define MICROPY_HW_UART1_CTS (pin_A10) +#define MICROPY_HW_UART1_RTS (pin_A8) #define MICROPY_HW_UART1_HWFC (1) // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" -#define MICROPY_HW_SPI0_SCK (29) -#define MICROPY_HW_SPI0_MOSI (25) -#define MICROPY_HW_SPI0_MISO (28) -#define MICROPY_HW_SPI0_SCK_PORT (0) -#define MICROPY_HW_SPI0_MISO_PORT (0) -#define MICROPY_HW_SPI0_MOSI_PORT (0) +#define MICROPY_HW_SPI0_SCK (pin_A29) +#define MICROPY_HW_SPI0_MOSI (pin_A25) +#define MICROPY_HW_SPI0_MISO (pin_A28) #define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10031/mpconfigboard.h b/nrf5/boards/pca10031/mpconfigboard.h index 2afee5fbfc..e28112c69b 100644 --- a/nrf5/boards/pca10031/mpconfigboard.h +++ b/nrf5/boards/pca10031/mpconfigboard.h @@ -53,23 +53,16 @@ #define MICROPY_HW_LED_BLUE (23) // BLUE // UART config -#define MICROPY_HW_UART1_RX (11) -#define MICROPY_HW_UART1_TX (9) -#define MICROPY_HW_UART1_CTS (10) -#define MICROPY_HW_UART1_RTS (8) -#define MICROPY_HW_UART1_RX_PORT (0) -#define MICROPY_HW_UART1_TX_PORT (0) -#define MICROPY_HW_UART1_CTS_PORT (0) -#define MICROPY_HW_UART1_RTS_PORT (0) +#define MICROPY_HW_UART1_RX (pin_A11) +#define MICROPY_HW_UART1_TX (pin_A9) +#define MICROPY_HW_UART1_CTS (pin_A10) +#define MICROPY_HW_UART1_RTS (pin_A8) #define MICROPY_HW_UART1_HWFC (0) // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" -#define MICROPY_HW_SPI0_SCK (15) // A15 -#define MICROPY_HW_SPI0_MOSI (16) // A16 -#define MICROPY_HW_SPI0_MISO (17) // A17 -#define MICROPY_HW_SPI0_SCK_PORT (0) -#define MICROPY_HW_SPI0_MISO_PORT (0) -#define MICROPY_HW_SPI0_MOSI_PORT (0) +#define MICROPY_HW_SPI0_SCK (pin_A15) +#define MICROPY_HW_SPI0_MOSI (pin_A16) +#define MICROPY_HW_SPI0_MISO (pin_A17) #define HELP_TEXT_BOARD_LED "1,2,3" diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 9d1f14f559..b4791b8689 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -64,26 +64,17 @@ #define MICROPY_HW_LED4 (20) // LED4 // UART config -#define MICROPY_HW_UART1_RX (8) -#define MICROPY_HW_UART1_TX (6) -#define MICROPY_HW_UART1_CTS (7) -#define MICROPY_HW_UART1_RTS (5) - -#define MICROPY_HW_UART1_RX_PORT (0) -#define MICROPY_HW_UART1_TX_PORT (0) -#define MICROPY_HW_UART1_CTS_PORT (0) -#define MICROPY_HW_UART1_RTS_PORT (0) - +#define MICROPY_HW_UART1_RX (pin_A8) +#define MICROPY_HW_UART1_TX (pin_A6) +#define MICROPY_HW_UART1_CTS (pin_A7) +#define MICROPY_HW_UART1_RTS (pin_A5) #define MICROPY_HW_UART1_HWFC (1) // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" -#define MICROPY_HW_SPI0_SCK (25) // A25 (Arduino D13) -#define MICROPY_HW_SPI0_MOSI (23) // A23 (Arduino D11) -#define MICROPY_HW_SPI0_MISO (24) // A24 (Arduino D12) -#define MICROPY_HW_SPI0_SCK_PORT (0) -#define MICROPY_HW_SPI0_MOSI_PORT (0) -#define MICROPY_HW_SPI0_MISO_PORT (0) +#define MICROPY_HW_SPI0_SCK (pin_A25) // (Arduino D13) +#define MICROPY_HW_SPI0_MOSI (pin_A23) // (Arduino D11) +#define MICROPY_HW_SPI0_MISO (pin_A24) // (Arduino D12) #define MICROPY_HW_PWM0_NAME "PWM0" #define MICROPY_HW_PWM1_NAME "PWM1" From 87e7ab8862ed96cd352b121b68bd6f5186d69131 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 22:31:23 +0100 Subject: [PATCH 253/809] nrf5/hal: Fixing nrf51 SPI pin configuration to use pin member of struct. --- nrf5/hal/hal_spi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c index 7218c69d6b..e710a89be3 100644 --- a/nrf5/hal/hal_spi.c +++ b/nrf5/hal/hal_spi.c @@ -48,9 +48,9 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi hal_gpio_cfg_pin(p_spi_init->miso_pin->port, p_spi_init->miso_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); #if NRF51 - p_instance->PSELSCK = p_spi_init->clk_pin; - p_instance->PSELMOSI = p_spi_init->mosi_pin; - p_instance->PSELMISO = p_spi_init->miso_pin; + p_instance->PSELSCK = p_spi_init->clk_pin->pin; + p_instance->PSELMOSI = p_spi_init->mosi_pin->pin; + p_instance->PSELMISO = p_spi_init->miso_pin->pin; #else p_instance->PSEL.SCK = p_spi_init->clk_pin->pin; p_instance->PSEL.MOSI = p_spi_init->mosi_pin->pin; From d37d799204c786a633e839d2127b4c78c91d27e6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 22:56:30 +0100 Subject: [PATCH 254/809] nrf5/drivers: Updating examples in comment in oled ssd1305 object to use the draw module. --- nrf5/drivers/display/oled_ssd1305_obj.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/nrf5/drivers/display/oled_ssd1305_obj.c b/nrf5/drivers/display/oled_ssd1305_obj.c index 59b52ee277..6b83a53550 100644 --- a/nrf5/drivers/display/oled_ssd1305_obj.c +++ b/nrf5/drivers/display/oled_ssd1305_obj.c @@ -117,31 +117,33 @@ reset = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) dc = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) spi = SPI(0, baudrate=8000000) d = SSD1305(128, 64, spi, cs, dc, reset) -d.text("Hello World!", 32, 32) +draw.text(d, "Hello World!", 32, 32) d.show() Example for nrf52832 / pca10040: from machine import Pin, SPI from display import SSD1305 +import draw cs = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) reset = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) dc = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) spi = SPI(0, baudrate=8000000) d = SSD1305(128, 64, spi, cs, dc, reset) -d.text("Hello World!", 32, 32) +draw.text(d, "Hello World!", 32, 32) d.show() Example for nrf52840 / pca10056: from machine import Pin, SPI from display import SSD1305 +import draw cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) reset = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) spi = SPI(0, baudrate=8000000) d = SSD1305(128, 64, spi, cs, dc, reset) -d.text("Hello World!", 32, 32) +draw.text(d, "Hello World!", 32, 32) d.show() */ From 726fe1aa2714127e66a16f44a7847ae6a93665a4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 26 Jan 2017 23:37:19 +0100 Subject: [PATCH 255/809] nrf5/examples: Updating game file to use ssd1305 display driver. --- nrf5/examples/game2048.py | 20 +++----------------- 1 file changed, 3 insertions(+), 17 deletions(-) diff --git a/nrf5/examples/game2048.py b/nrf5/examples/game2048.py index 4bf5b170a3..3d321d92c5 100644 --- a/nrf5/examples/game2048.py +++ b/nrf5/examples/game2048.py @@ -33,7 +33,7 @@ g.start() from machine import ADC from machine import Pin, SPI -from display import SSD1306 +from display import SSD1305 import draw import time @@ -77,20 +77,6 @@ font_1024 = [ " x x xxx x" ] -font_2048 = [ - " x x x x x", - "x x x x x x x x", - " x x x x x x x", - " x x x xxx x", - "x x x x x x", - "x x x x x x", - "xxx x x x" -] - -font_4096 = [ - "x" -] - DIR_UP = const(0x1) DIR_DOWN = const(0x2) DIR_LEFT = const(0x3) @@ -105,7 +91,7 @@ class Game: # reset = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) # dc = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) # spi = SPI(0, baudrate=8000000) -# self.screen = SSD1306(128, 64, spi, cs, dc, reset) +# self.screen = SSD1305(128, 64, spi, cs, dc, reset) # self.x_adc = ADC(2) # self.y_adc = ADC(3) # self.adc_threshold = 205 @@ -115,7 +101,7 @@ class Game: reset = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) spi = SPI(0, baudrate=8000000) - self.screen = SSD1306(128, 64, spi, cs, dc, reset) + self.screen = SSD1305(128, 64, spi, cs, dc, reset) self.x_adc = ADC(1) self.y_adc = ADC(2) self.adc_threshold = 130 From 1c778f020f2b83f84e478a0367c14e12b26907cc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 28 Jan 2017 22:54:44 +0100 Subject: [PATCH 256/809] nrf5/hal: Updating TWI with frequency enums. --- nrf5/hal/hal_twi.c | 6 ++++++ nrf5/hal/hal_twi.h | 29 +++++++++++++++++++++-------- nrf5/hal/hal_twie.c | 10 ++++++++-- 3 files changed, 35 insertions(+), 10 deletions(-) diff --git a/nrf5/hal/hal_twi.c b/nrf5/hal/hal_twi.c index d9b7935179..e318d2021f 100644 --- a/nrf5/hal/hal_twi.c +++ b/nrf5/hal/hal_twi.c @@ -29,6 +29,12 @@ #ifdef HAL_TWI_MODULE_ENABLED +static const uint32_t hal_twi_frequency_lookup[] = { + TWI_FREQUENCY_FREQUENCY_K100, // 100 kbps + TWI_FREQUENCY_FREQUENCY_K250, // 250 kbps + TWI_FREQUENCY_FREQUENCY_K400, // 400 kbps +}; + void hal_twi_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { } diff --git a/nrf5/hal/hal_twi.h b/nrf5/hal/hal_twi.h index 7151db87d8..5e2d10c31e 100644 --- a/nrf5/hal/hal_twi.h +++ b/nrf5/hal/hal_twi.h @@ -60,25 +60,38 @@ typedef struct { #endif /** - * @brief TWI Configuration Structure definition + * @brief TWI clock frequency type definition */ -typedef struct { -} hal_twi_init_t; +typedef enum { + HAL_TWI_FREQ_100_Kbps = 0, + HAL_TWI_FREQ_250_Kbps, + HAL_TWI_FREQ_400_Kbps +} hal_twi_clk_freq_t; +/** + * @brief TWI role type definition + */ typedef enum { HAL_TWI_MASTER, HAL_TWI_SLAVE -} hal_twi_mode_t; +} hal_twi_role_t; + +/** + * @brief TWI Configuration Structure definition + */ +typedef struct { + uint8_t id; /* TWI instance id */ + hal_twi_role_t role; /* TWI master/slave */ + hal_twi_clk_freq_t freq; /* TWI frequency */ +} hal_twi_init_t; /** * @brief TWI handle Structure definition */ typedef struct __TWI_HandleTypeDef { - NRF_TWI_Type *instance; /* TWI register base address */ - hal_twi_init_t init; /* TWI initialization parameters */ - uint8_t id; /* TWI instance id */ - hal_twi_mode_t mode; /* TWI master/slave */ + NRF_TWI_Type *instance; /* TWI register base address */ + hal_twi_init_t init; /* TWI initialization parameters */ } TWI_HandleTypeDef; void hal_twi_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init); diff --git a/nrf5/hal/hal_twie.c b/nrf5/hal/hal_twie.c index 67897b520d..cc20b2c97d 100644 --- a/nrf5/hal/hal_twie.c +++ b/nrf5/hal/hal_twie.c @@ -27,14 +27,20 @@ #include "mphalport.h" #include "hal_twi.h" -#ifdef HAL_TWIM_MODULE_ENABLED +#ifdef HAL_TWIE_MODULE_ENABLED // EasyDMA variants #define TWI_MASTER_BASE(x) ((NRF_TWIM_Type *)TWI_BASE_POINTERS[x]) #define TWI_SLAVE_BASE(x) ((NRF_TWIS_Type *)TWI_BASE_POINTERS[x]) +static const uint32_t hal_twi_frequency_lookup[] = { + TWIM_FREQUENCY_FREQUENCY_K100, // 100 kbps + TWIM_FREQUENCY_FREQUENCY_K250, // 250 kbps + TWIM_FREQUENCY_FREQUENCY_K400, // 400 kbps +}; + void hal_twi_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { } -#endif // HAL_TWIM_MODULE_ENABLED +#endif // HAL_TWIE_MODULE_ENABLED From 9787c4af7b616bfd816cd78dbb9cb32a5e7379d0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 28 Jan 2017 22:55:35 +0100 Subject: [PATCH 257/809] nrf5/i2c: Updating module to use new struct layout from hal_twi.h --- nrf5/i2c.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/i2c.c b/nrf5/i2c.c index 54d42e5fc3..bcbdb30641 100644 --- a/nrf5/i2c.c +++ b/nrf5/i2c.c @@ -40,8 +40,8 @@ typedef struct _machine_i2c_obj_t { TWI_HandleTypeDef *i2c; } machine_i2c_obj_t; -TWI_HandleTypeDef I2CHandle0 = {.instance = NULL, .id = 0}; -TWI_HandleTypeDef I2CHandle1 = {.instance = NULL, .id = 1}; +TWI_HandleTypeDef I2CHandle0 = {.instance = NULL, .init.id = 0}; +TWI_HandleTypeDef I2CHandle1 = {.instance = NULL, .init.id = 1}; STATIC const machine_i2c_obj_t machine_i2c_obj[] = { {{&machine_i2c_type}, &I2CHandle0}, @@ -69,7 +69,7 @@ STATIC int i2c_find(mp_obj_t id) { STATIC void i2c_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { machine_i2c_obj_t *self = o; - mp_printf(print, "I2C(%u)", self->i2c->id); + mp_printf(print, "I2C(%u)", self->i2c->init.id); } /******************************************************************************/ From 97a3fd4f3a3a6ebf540b3951479d29dfbabbb97a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 28 Jan 2017 23:45:30 +0100 Subject: [PATCH 258/809] nrf5/hal: Adding members to TWI config struct, device address and scl/sda pin. Renaming and adding function such that twi slave and master has seperate init function. Started implementation of master init function for nrf52 using DMA (hal_twie.c). --- nrf5/hal/hal_twi.c | 5 ++++- nrf5/hal/hal_twi.h | 8 +++++++- nrf5/hal/hal_twie.c | 21 ++++++++++++++++++++- 3 files changed, 31 insertions(+), 3 deletions(-) diff --git a/nrf5/hal/hal_twi.c b/nrf5/hal/hal_twi.c index e318d2021f..d71f29d5a8 100644 --- a/nrf5/hal/hal_twi.c +++ b/nrf5/hal/hal_twi.c @@ -35,7 +35,10 @@ static const uint32_t hal_twi_frequency_lookup[] = { TWI_FREQUENCY_FREQUENCY_K400, // 400 kbps }; -void hal_twi_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { +void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { +} + +void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { } #endif // HAL_TWI_MODULE_ENABLED diff --git a/nrf5/hal/hal_twi.h b/nrf5/hal/hal_twi.h index 5e2d10c31e..4bc3fc6792 100644 --- a/nrf5/hal/hal_twi.h +++ b/nrf5/hal/hal_twi.h @@ -81,8 +81,11 @@ typedef enum { */ typedef struct { uint8_t id; /* TWI instance id */ + const pin_obj_t * scl_pin; /* TWI SCL pin */ + const pin_obj_t * sda_pin; /* TWI SDA pin */ hal_twi_role_t role; /* TWI master/slave */ hal_twi_clk_freq_t freq; /* TWI frequency */ + uint32_t dev_addr; /* TWI master device address */ } hal_twi_init_t; /** @@ -94,6 +97,9 @@ typedef struct __TWI_HandleTypeDef hal_twi_init_t init; /* TWI initialization parameters */ } TWI_HandleTypeDef; -void hal_twi_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init); +void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init); + +void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init); + #endif // HAL_TWI_H__ diff --git a/nrf5/hal/hal_twie.c b/nrf5/hal/hal_twie.c index cc20b2c97d..404bb3efbc 100644 --- a/nrf5/hal/hal_twie.c +++ b/nrf5/hal/hal_twie.c @@ -39,7 +39,26 @@ static const uint32_t hal_twi_frequency_lookup[] = { TWIM_FREQUENCY_FREQUENCY_K400, // 400 kbps }; -void hal_twi_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { +void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { + // cast to master type + NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance; + + twim_instance->PSEL.SCL = p_twi_init->scl_pin->pin; + twim_instance->PSEL.SDA = p_twi_init->sda_pin->pin; + +#if NRF52840_XXAA + twim_instance->PSEL.SCL |= (p_twi_init->scl_pin->port << TWIM_PSEL_SCL_PORT_Pos); + twim_instance->PSEL.SDA |= (p_twi_init->sda_pin->port << TWIM_PSEL_SDA_PORT_Pos); +#endif + twim_instance->ADDRESS = p_twi_init->dev_addr; + twim_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq]; + +} + +void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { + // cast to slave type + NRF_TWIS_Type * twis_instance = (NRF_TWIS_Type *)p_instance; + (void)twis_instance; } #endif // HAL_TWIE_MODULE_ENABLED From 1421ca4adcfd337f8af0194c6ca1908af1f2afd0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 28 Jan 2017 23:46:31 +0100 Subject: [PATCH 259/809] nrf5/i2c: Updating i2c module to new new hal api, as master is initialized with its own init function. --- nrf5/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/i2c.c b/nrf5/i2c.c index bcbdb30641..2b6764209e 100644 --- a/nrf5/i2c.c +++ b/nrf5/i2c.c @@ -99,7 +99,7 @@ STATIC mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, s int i2c_id = i2c_find(args[ARG_NEW_id].u_obj); const machine_i2c_obj_t *self = &machine_i2c_obj[i2c_id]; - hal_twi_init(self->i2c->instance, &self->i2c->init); + hal_twi_master_init(self->i2c->instance, &self->i2c->init); return MP_OBJ_FROM_PTR(self); } From f529aa9e671c542859b80f0ab63d89a70bb28088 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 29 Jan 2017 16:38:13 +0100 Subject: [PATCH 260/809] nrf5/i2c: Updating i2c machine module with new constructor parameters to set scl and sda pins. Also updating print funciton to debug pin number and port number for the gpio set. --- nrf5/i2c.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/nrf5/i2c.c b/nrf5/i2c.c index 2b6764209e..cc4e0f037f 100644 --- a/nrf5/i2c.c +++ b/nrf5/i2c.c @@ -69,7 +69,12 @@ STATIC int i2c_find(mp_obj_t id) { STATIC void i2c_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { machine_i2c_obj_t *self = o; - mp_printf(print, "I2C(%u)", self->i2c->init.id); + mp_printf(print, "I2C(%u, scl=(port=%u, pin=%u), sda=(port=%u, pin=%u))", + self->i2c->init.id, + self->i2c->init.scl_pin->port, + self->i2c->init.scl_pin->pin, + self->i2c->init.sda_pin->port, + self->i2c->init.sda_pin->pin); } /******************************************************************************/ @@ -77,27 +82,39 @@ STATIC void i2c_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) // for make_new enum { - ARG_NEW_id, + ARG_NEW_ID, + ARG_NEW_SCL, + ARG_NEW_SDA, }; STATIC mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { - { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + { MP_QSTR_ID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + { ARG_NEW_SCL, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_SDA, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, }; // parse args mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { - // index -1 does not exist - return mp_const_none; - // TODO: raise exception + // get static peripheral object + int i2c_id = i2c_find(args[ARG_NEW_ID].u_obj); + const machine_i2c_obj_t *self = &machine_i2c_obj[i2c_id]; + + if (args[ARG_NEW_SCL].u_obj != MP_OBJ_NULL) { + self->i2c->init.scl_pin = args[ARG_NEW_SCL].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "I2C SCL Pin not set")); } - // get static peripheral object - int i2c_id = i2c_find(args[ARG_NEW_id].u_obj); - const machine_i2c_obj_t *self = &machine_i2c_obj[i2c_id]; + if (args[ARG_NEW_SDA].u_obj != MP_OBJ_NULL) { + self->i2c->init.sda_pin = args[ARG_NEW_SDA].u_obj; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "I2C SDA Pin not set")); + } hal_twi_master_init(self->i2c->instance, &self->i2c->init); From bfc67dd99c332a80a0eaf151099fe1af459cd5f5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 29 Jan 2017 16:38:48 +0100 Subject: [PATCH 261/809] nrf5: Updating main.c to initialize the i2c machine module if selected. --- nrf5/main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/main.c b/nrf5/main.c index 5b52975d82..b17c9ea187 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -47,6 +47,7 @@ #include "nrf.h" #include "pin.h" #include "spi.h" +#include "i2c.h" #if MICROPY_PY_MACHINE_PWM #include "pwm.h" #endif @@ -107,6 +108,10 @@ int main(int argc, char **argv) { spi_init0(); #endif +#if MICROPY_PY_MACHINE_HW_I2C + i2c_init0(); +#endif + #if MICROPY_PY_MACHINE_PWM pwm_init0(); #endif From fec5c750681e4d78b9785bf7e49baf9c2d0cc52f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 29 Jan 2017 16:41:18 +0100 Subject: [PATCH 262/809] nrf5: Adding i2c class to machine module globals table. --- nrf5/modmachine.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/modmachine.c b/nrf5/modmachine.c index fdff283803..2a25e92174 100644 --- a/nrf5/modmachine.c +++ b/nrf5/modmachine.c @@ -39,6 +39,7 @@ #include "gccollect.h" #include "pin.h" #include "spi.h" +#include "i2c.h" #if MICROPY_PY_MACHINE_PWM #include "pwm.h" #endif @@ -171,6 +172,9 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { #if MICROPY_PY_MACHINE_HW_SPI { MP_OBJ_NEW_QSTR(MP_QSTR_SPI), (mp_obj_t)&machine_hard_spi_type }, #endif +#if MICROPY_PY_MACHINE_HW_I2C + { MP_OBJ_NEW_QSTR(MP_QSTR_I2C), (mp_obj_t)&machine_i2c_type }, +#endif #if MICROPY_PY_MACHINE_ADC { MP_OBJ_NEW_QSTR(MP_QSTR_ADC), (mp_obj_t)&machine_adc_type }, #endif From bb9cd36314abb6a6c252f5a4dd3aa99739736332 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 29 Jan 2017 17:53:01 +0100 Subject: [PATCH 263/809] nrf5/i2c: Backing up before trying out extmod i2c integration. --- nrf5/i2c.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/nrf5/i2c.c b/nrf5/i2c.c index cc4e0f037f..d9f8d2fe58 100644 --- a/nrf5/i2c.c +++ b/nrf5/i2c.c @@ -124,20 +124,14 @@ STATIC mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, s STATIC const mp_map_elem_t pyb_i2c_locals_dict_table[] = { // instance methods #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&machine_i2c_init_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_deinit), (mp_obj_t)&machine_i2c_deinit_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_is_ready), (mp_obj_t)&machine_i2c_is_ready_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_scan), (mp_obj_t)&machine_i2c_scan_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_send), (mp_obj_t)&machine_i2c_send_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_recv), (mp_obj_t)&machine_i2c_recv_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_mem_read), (mp_obj_t)&machine_i2c_mem_read_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_mem_write), (mp_obj_t)&machine_i2c_mem_write_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_scan), (mp_obj_t)&machine_i2c_scan_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readfrom), (mp_obj_t)&machine_i2c_readfrom_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readfrom_into), (mp_obj_t)&machine_i2c_readfrom_into_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_writeto), (mp_obj_t)&machine_i2c_writeto_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readfrom_mem), (mp_obj_t)&machine_i2c_readfrom_mem_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readfrom_mem_into), (mp_obj_t)&machine_i2c_readfrom_mem_into_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_writeto_mem), (mp_obj_t)&machine_i2c_writeto_mem_obj }, #endif - // class constants - /// \constant MASTER - for initialising the bus to master mode - /// \constant SLAVE - for initialising the bus to slave mode - { MP_OBJ_NEW_QSTR(MP_QSTR_MASTER), MP_OBJ_NEW_SMALL_INT(HAL_TWI_MASTER) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_SLAVE), MP_OBJ_NEW_SMALL_INT(HAL_TWI_SLAVE) }, }; STATIC MP_DEFINE_CONST_DICT(pyb_i2c_locals_dict, pyb_i2c_locals_dict_table); From 61c026e51f71f52e60ee8df0063e114188d00069 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 30 Jan 2017 00:31:00 +0100 Subject: [PATCH 264/809] nrf5/i2c: Adopting use of extmod/machine_i2c module as base for port's machine i2c module. --- nrf5/i2c.c | 92 ++++++++++++++++++++++++--------------------- nrf5/modmachine.c | 2 +- nrf5/mpconfigport.h | 9 +---- 3 files changed, 52 insertions(+), 51 deletions(-) diff --git a/nrf5/i2c.c b/nrf5/i2c.c index d9f8d2fe58..a94752ac28 100644 --- a/nrf5/i2c.c +++ b/nrf5/i2c.c @@ -30,22 +30,25 @@ #include "py/nlr.h" #include "py/runtime.h" #include "py/mphal.h" +#include "extmod/machine_i2c.h" #include "i2c.h" #include "hal_twi.h" -#if MICROPY_PY_MACHINE_HW_I2C +#if MICROPY_PY_MACHINE_I2C -typedef struct _machine_i2c_obj_t { +STATIC const mp_obj_type_t machine_hard_i2c_type; + +typedef struct _machine_hard_i2c_obj_t { mp_obj_base_t base; TWI_HandleTypeDef *i2c; -} machine_i2c_obj_t; +} machine_hard_i2c_obj_t; TWI_HandleTypeDef I2CHandle0 = {.instance = NULL, .init.id = 0}; TWI_HandleTypeDef I2CHandle1 = {.instance = NULL, .init.id = 1}; -STATIC const machine_i2c_obj_t machine_i2c_obj[] = { - {{&machine_i2c_type}, &I2CHandle0}, - {{&machine_i2c_type}, &I2CHandle1}, +STATIC const machine_hard_i2c_obj_t machine_hard_i2c_obj[] = { + {{&machine_hard_i2c_type}, &I2CHandle0}, + {{&machine_hard_i2c_type}, &I2CHandle1}, }; void i2c_init0(void) { @@ -59,16 +62,16 @@ void i2c_init0(void) { STATIC int i2c_find(mp_obj_t id) { // given an integer id int i2c_id = mp_obj_get_int(id); - if (i2c_id >= 0 && i2c_id <= MP_ARRAY_SIZE(machine_i2c_obj) - && machine_i2c_obj[i2c_id].i2c != NULL) { + if (i2c_id >= 0 && i2c_id <= MP_ARRAY_SIZE(machine_hard_i2c_obj) + && machine_hard_i2c_obj[i2c_id].i2c != NULL) { return i2c_id; } nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "I2C(%d) does not exist", i2c_id)); } -STATIC void i2c_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - machine_i2c_obj_t *self = o; +STATIC void machine_hard_i2c_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + machine_hard_i2c_obj_t *self = o; mp_printf(print, "I2C(%u, scl=(port=%u, pin=%u), sda=(port=%u, pin=%u))", self->i2c->init.id, self->i2c->init.scl_pin->port, @@ -82,16 +85,18 @@ STATIC void i2c_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) // for make_new enum { - ARG_NEW_ID, - ARG_NEW_SCL, - ARG_NEW_SDA, + ARG_NEW_id, + ARG_NEW_scl, + ARG_NEW_sda, + ARG_NEW_freq, + ARG_NEW_timeout, }; -STATIC mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { +mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { - { MP_QSTR_ID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, - { ARG_NEW_SCL, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_SDA, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_id, MP_ARG_REQUIRED | MP_ARG_OBJ }, + { ARG_NEW_scl, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_sda, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, }; // parse args @@ -99,18 +104,18 @@ STATIC mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, s mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); // get static peripheral object - int i2c_id = i2c_find(args[ARG_NEW_ID].u_obj); - const machine_i2c_obj_t *self = &machine_i2c_obj[i2c_id]; + int i2c_id = i2c_find(args[ARG_NEW_id].u_obj); + const machine_hard_i2c_obj_t *self = &machine_hard_i2c_obj[i2c_id]; - if (args[ARG_NEW_SCL].u_obj != MP_OBJ_NULL) { - self->i2c->init.scl_pin = args[ARG_NEW_SCL].u_obj; + if (args[ARG_NEW_scl].u_obj != MP_OBJ_NULL) { + self->i2c->init.scl_pin = args[ARG_NEW_scl].u_obj; } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "I2C SCL Pin not set")); } - if (args[ARG_NEW_SDA].u_obj != MP_OBJ_NULL) { - self->i2c->init.sda_pin = args[ARG_NEW_SDA].u_obj; + if (args[ARG_NEW_sda].u_obj != MP_OBJ_NULL) { + self->i2c->init.sda_pin = args[ARG_NEW_sda].u_obj; } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "I2C SDA Pin not set")); @@ -121,29 +126,30 @@ STATIC mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, s return MP_OBJ_FROM_PTR(self); } -STATIC const mp_map_elem_t pyb_i2c_locals_dict_table[] = { - // instance methods -#if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_scan), (mp_obj_t)&machine_i2c_scan_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readfrom), (mp_obj_t)&machine_i2c_readfrom_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readfrom_into), (mp_obj_t)&machine_i2c_readfrom_into_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_writeto), (mp_obj_t)&machine_i2c_writeto_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readfrom_mem), (mp_obj_t)&machine_i2c_readfrom_mem_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readfrom_mem_into), (mp_obj_t)&machine_i2c_readfrom_mem_into_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_writeto_mem), (mp_obj_t)&machine_i2c_writeto_mem_obj }, -#endif +#include + +int machine_hard_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t *dest, size_t len, bool stop) { + printf("machine_hard_i2c_readfrom called\n"); + return 0; +} + +int machine_hard_i2c_writeto(mp_obj_base_t *self_in, uint16_t addr, const uint8_t *src, size_t len, bool stop) { + printf("machine_hard_i2c_writeto called\n"); + return 0; +} + +STATIC const mp_machine_i2c_p_t machine_hard_i2c_p = { + .readfrom = machine_hard_i2c_readfrom, + .writeto = machine_hard_i2c_writeto, }; -STATIC MP_DEFINE_CONST_DICT(pyb_i2c_locals_dict, pyb_i2c_locals_dict_table); - -const mp_obj_type_t machine_i2c_type = { +STATIC const mp_obj_type_t machine_hard_i2c_type = { { &mp_type_type }, .name = MP_QSTR_I2C, - .print = i2c_print, - .make_new = machine_i2c_make_new, -#if 0 - .locals_dict = (mp_obj_t)&machine_i2c_locals_dict -#endif + .print = machine_hard_i2c_print, + .make_new = machine_hard_i2c_make_new, + .protocol = &machine_hard_i2c_p, + .locals_dict = (mp_obj_dict_t*)&mp_machine_soft_i2c_locals_dict, }; -#endif // MICROPY_PY_MACHINE_HW_I2C +#endif // MICROPY_PY_MACHINE_I2C diff --git a/nrf5/modmachine.c b/nrf5/modmachine.c index 2a25e92174..7b5b6f01b7 100644 --- a/nrf5/modmachine.c +++ b/nrf5/modmachine.c @@ -172,7 +172,7 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { #if MICROPY_PY_MACHINE_HW_SPI { MP_OBJ_NEW_QSTR(MP_QSTR_SPI), (mp_obj_t)&machine_hard_spi_type }, #endif -#if MICROPY_PY_MACHINE_HW_I2C +#if MICROPY_PY_MACHINE_I2C { MP_OBJ_NEW_QSTR(MP_QSTR_I2C), (mp_obj_t)&machine_i2c_type }, #endif #if MICROPY_PY_MACHINE_ADC diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index aafcd3812c..d6ed8fa77a 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -30,8 +30,6 @@ #include // options to control how Micro Python is built -// options to control how Micro Python is built - #define MICROPY_ALLOC_PATH_MAX (512) #define MICROPY_PERSISTENT_CODE_LOAD (0) #define MICROPY_EMIT_THUMB (0) @@ -103,7 +101,8 @@ #define MICROPY_PY_UTIME_MP_HAL (1) #define MICROPY_PY_MACHINE (1) #define MICROPY_PY_MACHINE_PULSE (0) -#define MICROPY_PY_MACHINE_I2C (0) +#define MICROPY_PY_MACHINE_I2C (1) +#define MICROPY_PY_MACHINE_I2C_MAKE_NEW machine_hard_i2c_make_new #define MICROPY_PY_MACHINE_SPI (0) #define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) #define MICROPY_PY_FRAMEBUF (0) @@ -112,10 +111,6 @@ #define MICROPY_PY_MACHINE_ADC (0) #endif -#ifndef MICROPY_PY_MACHINE_HW_I2C -#define MICROPY_PY_MACHINE_HW_I2C (0) -#endif - #ifndef MICROPY_PY_MACHINE_HW_SPI #define MICROPY_PY_MACHINE_HW_SPI (1) #endif From 8ffe804c24897a075ab1e765638be9f0c96e120c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 30 Jan 2017 00:32:19 +0100 Subject: [PATCH 265/809] nrf5/hal: Adding new macros functions to mphalport.h which are used by extmod i2c machine module. --- nrf5/mphalport.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/nrf5/mphalport.h b/nrf5/mphalport.h index 5c62754727..ae3f65b5bb 100644 --- a/nrf5/mphalport.h +++ b/nrf5/mphalport.h @@ -133,10 +133,15 @@ int mp_hal_stdin_rx_chr(void); void mp_hal_stdout_tx_str(const char *str); #define mp_hal_pin_obj_t const pin_obj_t* -#define mp_hal_pin_high(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTSET = (p)->pin_mask) -#define mp_hal_pin_low(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask) -#define mp_hal_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1) -#define mp_hal_pin_write(p, v) do { if (v) { mp_hal_pin_high(p); } else { mp_hal_pin_low(p); } } while (0) +#define mp_hal_get_pin_obj(o) pin_find(o) +#define mp_hal_pin_high(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTSET = (p)->pin_mask) +#define mp_hal_pin_low(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask) +#define mp_hal_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1) +#define mp_hal_pin_write(p, v) do { if (v) { mp_hal_pin_high(p); } else { mp_hal_pin_low(p); } } while (0) +#define mp_hal_pin_od_low(p) mp_hal_pin_low(p) +#define mp_hal_pin_od_high(p) mp_hal_pin_high(p) +#define mp_hal_pin_open_drain(p) hal_gpio_cfg_pin(p->port, p->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED) + // TODO: empty implementation for now. Used by machine_spi.c:69 #define mp_hal_delay_us_fast(p) From ed976e07fe140e7ecce477ffb011e568b0cbe0d1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 30 Jan 2017 21:32:20 +0100 Subject: [PATCH 266/809] nrf5/hal: Adding i2c master functions for tx and rx in hal header. --- nrf5/hal/hal_twi.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_twi.h b/nrf5/hal/hal_twi.h index 4bc3fc6792..4797d1a1e8 100644 --- a/nrf5/hal/hal_twi.h +++ b/nrf5/hal/hal_twi.h @@ -85,7 +85,6 @@ typedef struct { const pin_obj_t * sda_pin; /* TWI SDA pin */ hal_twi_role_t role; /* TWI master/slave */ hal_twi_clk_freq_t freq; /* TWI frequency */ - uint32_t dev_addr; /* TWI master device address */ } hal_twi_init_t; /** @@ -99,6 +98,17 @@ typedef struct __TWI_HandleTypeDef void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init); +void hal_twi_master_tx(NRF_TWI_Type * p_instance, + uint8_t addr, + uint16_t transfer_size, + const uint8_t * tx_data); + +void hal_twi_master_rx(NRF_TWI_Type * p_instance, + uint8_t addr, + uint16_t transfer_size, + const uint8_t * rx_data); + + void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init); From 5004a6f8118a8a9f376f12877d1d8f5abbb2a567 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 30 Jan 2017 23:05:27 +0100 Subject: [PATCH 267/809] nrf5/hal: Updating twi master tx with stop parameter. --- nrf5/hal/hal_twi.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_twi.h b/nrf5/hal/hal_twi.h index 4797d1a1e8..8332992ba0 100644 --- a/nrf5/hal/hal_twi.h +++ b/nrf5/hal/hal_twi.h @@ -27,6 +27,7 @@ #ifndef HAL_TWI_H__ #define HAL_TWI_H__ +#include #include "nrf.h" #define TWI_BASE_POINTERS (const uint32_t[]){NRF_TWI0_BASE, NRF_TWI1_BASE} @@ -101,7 +102,8 @@ void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi void hal_twi_master_tx(NRF_TWI_Type * p_instance, uint8_t addr, uint16_t transfer_size, - const uint8_t * tx_data); + const uint8_t * tx_data, + bool stop); void hal_twi_master_rx(NRF_TWI_Type * p_instance, uint8_t addr, From 4a568ec1ed4d8eabfbda3047b3161d69c6ede0ee Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 31 Jan 2017 22:36:47 +0100 Subject: [PATCH 268/809] nrf5/hal: Updating TWI DMA implementation. Suspend not working on tx. Rx not implemented yet. --- nrf5/hal/hal_twie.c | 52 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_twie.c b/nrf5/hal/hal_twie.c index 404bb3efbc..c784fa1364 100644 --- a/nrf5/hal/hal_twie.c +++ b/nrf5/hal/hal_twie.c @@ -50,8 +50,58 @@ void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi twim_instance->PSEL.SCL |= (p_twi_init->scl_pin->port << TWIM_PSEL_SCL_PORT_Pos); twim_instance->PSEL.SDA |= (p_twi_init->sda_pin->port << TWIM_PSEL_SDA_PORT_Pos); #endif - twim_instance->ADDRESS = p_twi_init->dev_addr; twim_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq]; + twim_instance->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos); +} + +#include + +void hal_twi_master_tx(NRF_TWI_Type * p_instance, + uint8_t addr, + uint16_t transfer_size, + const uint8_t * tx_data, + bool stop) { + // cast to master type + NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance; + + twim_instance->ADDRESS = addr; + + printf("Hal I2C transfer size: %u, addr: %x, stop: %u\n", transfer_size, addr, stop); + twim_instance->TXD.MAXCNT = transfer_size; + twim_instance->TXD.PTR = (uint32_t)tx_data; + + if (stop) { + twim_instance->SHORTS = TWIM_SHORTS_LASTTX_STOP_Msk; + } else { + twim_instance->SHORTS = TWIM_SHORTS_LASTTX_SUSPEND_Msk; + } + + if (twim_instance->EVENTS_SUSPENDED == 1) { + printf("Resuming\n"); + twim_instance->EVENTS_SUSPENDED = 0; + twim_instance->EVENTS_STOPPED = 0; + twim_instance->TASKS_RESUME = 1; // in case of resume + } else { + printf("Starting\n"); + twim_instance->EVENTS_SUSPENDED = 0; + twim_instance->EVENTS_STOPPED = 0; + twim_instance->TASKS_STARTTX = 1; + } + + printf("Going into loop\n"); + while (twim_instance->EVENTS_STOPPED == 0 && twim_instance->EVENTS_SUSPENDED == 0) { + ; + } +} + +void hal_twi_master_rx(NRF_TWI_Type * p_instance, + uint8_t addr, + uint16_t transfer_size, + const uint8_t * rx_data) { + // cast to master type + NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance; + + twim_instance->ADDRESS = addr; } From 4b38644531bbbd73df44e80ac5c92bd4d05e34be Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 31 Jan 2017 22:46:04 +0100 Subject: [PATCH 269/809] nrf5/hal: Updating twi driver with template functions. --- nrf5/hal/hal_twi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/nrf5/hal/hal_twi.c b/nrf5/hal/hal_twi.c index d71f29d5a8..fe729df6a1 100644 --- a/nrf5/hal/hal_twi.c +++ b/nrf5/hal/hal_twi.c @@ -38,6 +38,21 @@ static const uint32_t hal_twi_frequency_lookup[] = { void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { } +void hal_twi_master_tx(NRF_TWI_Type * p_instance, + uint8_t addr, + uint16_t transfer_size, + const uint8_t * tx_data, + bool stop) { + +} + +void hal_twi_master_rx(NRF_TWI_Type * p_instance, + uint8_t addr, + uint16_t transfer_size, + const uint8_t * rx_data) { + +} + void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { } From 9e6acda85cb17ea85d27e880d05df1c39c1fbaec Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 31 Jan 2017 22:48:07 +0100 Subject: [PATCH 270/809] nrf5/i2c: Making use of hal twi tx function in writeto function. --- nrf5/i2c.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/nrf5/i2c.c b/nrf5/i2c.c index a94752ac28..539fb5a748 100644 --- a/nrf5/i2c.c +++ b/nrf5/i2c.c @@ -121,6 +121,8 @@ mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, siz "I2C SDA Pin not set")); } + self->i2c->init.freq = HAL_TWI_FREQ_100_Kbps; + hal_twi_master_init(self->i2c->instance, &self->i2c->init); return MP_OBJ_FROM_PTR(self); @@ -134,7 +136,10 @@ int machine_hard_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t *de } int machine_hard_i2c_writeto(mp_obj_base_t *self_in, uint16_t addr, const uint8_t *src, size_t len, bool stop) { - printf("machine_hard_i2c_writeto called\n"); + machine_hard_i2c_obj_t *self = (machine_hard_i2c_obj_t *)self_in; + + hal_twi_master_tx(self->i2c->instance, addr, len, src, stop); + return 0; } From 44daeb7d949c9a5ab184df885cf462ae1942c0e5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 18:08:28 +0100 Subject: [PATCH 271/809] nrf5/boards: Updating s110 SD linker script for micro:bit. --- nrf5/boards/microbit/mpconfigboard_s110.mk | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/microbit/mpconfigboard_s110.mk b/nrf5/boards/microbit/mpconfigboard_s110.mk index 54766bd429..0cd554415f 100644 --- a/nrf5/boards/microbit/mpconfigboard_s110.mk +++ b/nrf5/boards/microbit/mpconfigboard_s110.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_ac_s110.ld - +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/nrf51822_aa_s110.ld +FLASHER = pyocd From 0066f226aab5d51fa1183509fc476c5a57814cb5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 18:29:51 +0100 Subject: [PATCH 272/809] nrf5/boards: Activating all display drivers in pca10056 board. --- nrf5/boards/pca10056/mpconfigboard.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index e46765f67c..c8f195761a 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -38,8 +38,10 @@ #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) #define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (1) +#define MICROPY_PY_DISPLAY_LCD_SSD1289 (1) +#define MICROPY_PY_DISPLAY_OLED_SSD1305 (1) +#define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) From 14d4a8def854666196c314fe64686e66f985b7a3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 18:33:03 +0100 Subject: [PATCH 273/809] nrf5: Making i2c configurable from board configuration in case board has to sacrifice the i2c machine module. --- nrf5/mpconfigport.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index d6ed8fa77a..9c3c29ad69 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -101,7 +101,6 @@ #define MICROPY_PY_UTIME_MP_HAL (1) #define MICROPY_PY_MACHINE (1) #define MICROPY_PY_MACHINE_PULSE (0) -#define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_I2C_MAKE_NEW machine_hard_i2c_make_new #define MICROPY_PY_MACHINE_SPI (0) #define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) @@ -111,6 +110,10 @@ #define MICROPY_PY_MACHINE_ADC (0) #endif +#ifndef MICROPY_PY_MACHINE_I2C +#define MICROPY_PY_MACHINE_I2C (0) +#endif + #ifndef MICROPY_PY_MACHINE_HW_SPI #define MICROPY_PY_MACHINE_HW_SPI (1) #endif From 4cbdbc9a4bd5323f496805adb47e8f5fa464970d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 18:41:44 +0100 Subject: [PATCH 274/809] nrf5: Renaming configuration define in board configs using i2c from MICROPY_PY_MACHINE_HW_I2C to MICROPY_PY_MACHINE_I2C as the config is overlapping with the latter. --- nrf5/boards/pca10028/mpconfigboard.h | 2 +- nrf5/boards/pca10056/mpconfigboard.h | 2 +- nrf5/main.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 26b62cc361..6b9de477d6 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -41,7 +41,7 @@ #define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) -#define MICROPY_PY_MACHINE_HW_I2C (1) +#define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_USOCKET (0) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index c8f195761a..308c9a1c9f 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -32,7 +32,7 @@ #define MICROPY_PY_MACHINE_PWM (1) #define MICROPY_PY_MACHINE_HW_SPI (1) -#define MICROPY_PY_MACHINE_HW_I2C (1) +#define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_DISPLAY (1) diff --git a/nrf5/main.c b/nrf5/main.c index b17c9ea187..af87938e22 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -108,7 +108,7 @@ int main(int argc, char **argv) { spi_init0(); #endif -#if MICROPY_PY_MACHINE_HW_I2C +#if MICROPY_PY_MACHINE_I2C i2c_init0(); #endif From 5e9e48e9e3d67c346ac96bd2aa7f1234cfc2058d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 18:43:12 +0100 Subject: [PATCH 275/809] nrf5: Renaming configuration define in board configs using i2c from MICROPY_PY_MACHINE_HW_I2C to MICROPY_PY_MACHINE_I2C as the config is overlapping with the latter. --- nrf5/boards/pca10040/mpconfigboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index b4791b8689..fcb62a5fe6 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -34,7 +34,7 @@ #define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) -#define MICROPY_PY_MACHINE_HW_I2C (1) +#define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_DISPLAY (1) From 70d64e2892bff6adb3068807a49d65f3b1a35696 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 19:37:29 +0100 Subject: [PATCH 276/809] nrf5: Removing hal_twie.c from being compiled in. --- nrf5/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index fe935f0c15..f48736f664 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -114,7 +114,6 @@ SRC_HAL = $(addprefix hal/,\ hal_rtc.c \ hal_timer.c \ hal_twi.c \ - hal_twie.c \ hal_adc.c \ hal_adce.c \ ) From 0629abac53a34e6b4eecd4257f1d773fde1c45a0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 20:03:50 +0100 Subject: [PATCH 277/809] nrf5/hal: Started implementation of hal_twi.c (non-DMA). Init function started. --- nrf5/hal/hal_twi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_twi.c b/nrf5/hal/hal_twi.c index fe729df6a1..fe68613fb8 100644 --- a/nrf5/hal/hal_twi.c +++ b/nrf5/hal/hal_twi.c @@ -36,6 +36,19 @@ static const uint32_t hal_twi_frequency_lookup[] = { }; void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { + +#if NRF52840_XXAA + p_instance->PSEL.SCL = p_twi_init->scl_pin->pin; + p_instance->PSEL.SDA = p_twi_init->sda_pin->pin; + p_instance->PSEL.SCL |= (p_twi_init->scl_pin->port << TWI_PSEL_SCL_PORT_Pos); + p_instance->PSEL.SDA |= (p_twi_init->sda_pin->port << TWI_PSEL_SDA_PORT_Pos); +#else + p_instance->PSELSCL = p_twi_init->scl_pin->pin; + p_instance->PSELSDA = p_twi_init->sda_pin->pin; +#endif + + p_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq]; + p_instance->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos); } void hal_twi_master_tx(NRF_TWI_Type * p_instance, @@ -43,7 +56,7 @@ void hal_twi_master_tx(NRF_TWI_Type * p_instance, uint16_t transfer_size, const uint8_t * tx_data, bool stop) { - + p_instance->ADDRESS = addr; } void hal_twi_master_rx(NRF_TWI_Type * p_instance, From fed06e278b3d2f83c9bf6f660e1fb3db8f71822f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 20:51:43 +0100 Subject: [PATCH 278/809] nrf5/hal: Updating hal_twi.c with tx function which partly works. Bytes are clocked out a bit out of order. --- nrf5/hal/hal_twi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/nrf5/hal/hal_twi.c b/nrf5/hal/hal_twi.c index fe68613fb8..42e5ca92e1 100644 --- a/nrf5/hal/hal_twi.c +++ b/nrf5/hal/hal_twi.c @@ -56,7 +56,22 @@ void hal_twi_master_tx(NRF_TWI_Type * p_instance, uint16_t transfer_size, const uint8_t * tx_data, bool stop) { + + uint16_t number_of_txd_bytes = 0; + p_instance->ADDRESS = addr; + + while (number_of_txd_bytes < transfer_size) { + p_instance->TXD = (uint32_t)(tx_data[number_of_txd_bytes]); + p_instance->EVENTS_TXDSENT = 0; + p_instance->TASKS_STARTTX = 1; + + // wait for the transaction complete + while (p_instance->EVENTS_TXDSENT == 0) { + ; + } + number_of_txd_bytes++; + } } void hal_twi_master_rx(NRF_TWI_Type * p_instance, From c7162720c19aa460bfee7162f3676a7ae90afef6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 22:55:25 +0100 Subject: [PATCH 279/809] nrf5/hal: Updating hal_twi.c with tx function. Gets multiple startup bytes for each clocked byte. --- nrf5/hal/hal_twi.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/nrf5/hal/hal_twi.c b/nrf5/hal/hal_twi.c index 42e5ca92e1..4e38b96c8e 100644 --- a/nrf5/hal/hal_twi.c +++ b/nrf5/hal/hal_twi.c @@ -50,7 +50,7 @@ void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi p_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq]; p_instance->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos); } - +#include void hal_twi_master_tx(NRF_TWI_Type * p_instance, uint8_t addr, uint16_t transfer_size, @@ -62,16 +62,26 @@ void hal_twi_master_tx(NRF_TWI_Type * p_instance, p_instance->ADDRESS = addr; while (number_of_txd_bytes < transfer_size) { - p_instance->TXD = (uint32_t)(tx_data[number_of_txd_bytes]); p_instance->EVENTS_TXDSENT = 0; + p_instance->TXD = tx_data[number_of_txd_bytes]; p_instance->TASKS_STARTTX = 1; // wait for the transaction complete while (p_instance->EVENTS_TXDSENT == 0) { ; } + number_of_txd_bytes++; } + + if (stop) { + p_instance->EVENTS_STOPPED = 0; + p_instance->TASKS_STOP = 1; + + while (p_instance->EVENTS_STOPPED == 0) { + ; + } + } } void hal_twi_master_rx(NRF_TWI_Type * p_instance, From 2517ce48f84b4089916fee8f1083e3bd0876de4d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 23:43:52 +0100 Subject: [PATCH 280/809] nrf5/examples: Updating ssd1306.py driver to work with i2c master write implementation. --- nrf5/examples/ssd1306.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/nrf5/examples/ssd1306.py b/nrf5/examples/ssd1306.py index 843ff377a0..aac2beb986 100644 --- a/nrf5/examples/ssd1306.py +++ b/nrf5/examples/ssd1306.py @@ -113,12 +113,8 @@ class SSD1306_I2C(SSD1306): self.i2c.writeto(self.addr, self.temp) def write_data(self, buf): - self.temp[0] = self.addr << 1 - self.temp[1] = 0x40 # Co=0, D/C#=1 - self.i2c.start() - self.i2c.write(self.temp) - self.i2c.write(buf) - self.i2c.stop() + buffer = bytearray([0x40]) + buf # Co=0, D/C#=1 + self.i2c.writeto(self.addr, buffer) def poweron(self): pass From cd096f604e305c2118cd65c6735234ea714cca38 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 23:45:44 +0100 Subject: [PATCH 281/809] nrf5/hal: Updating hal_twi.c tx implementation to a working state. STARTTX only issued once, before looping bytes. --- nrf5/hal/hal_twi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/nrf5/hal/hal_twi.c b/nrf5/hal/hal_twi.c index 4e38b96c8e..9da0cd6d0a 100644 --- a/nrf5/hal/hal_twi.c +++ b/nrf5/hal/hal_twi.c @@ -61,19 +61,25 @@ void hal_twi_master_tx(NRF_TWI_Type * p_instance, p_instance->ADDRESS = addr; - while (number_of_txd_bytes < transfer_size) { - p_instance->EVENTS_TXDSENT = 0; - p_instance->TXD = tx_data[number_of_txd_bytes]; - p_instance->TASKS_STARTTX = 1; + p_instance->EVENTS_TXDSENT = 0; + p_instance->TXD = tx_data[number_of_txd_bytes]; + p_instance->TASKS_STARTTX = 1; + + while (number_of_txd_bytes < transfer_size) { // wait for the transaction complete while (p_instance->EVENTS_TXDSENT == 0) { ; } number_of_txd_bytes++; + + // TODO: This could go one byte out of bound. + p_instance->TXD = tx_data[number_of_txd_bytes]; + p_instance->EVENTS_TXDSENT = 0; } + if (stop) { p_instance->EVENTS_STOPPED = 0; p_instance->TASKS_STOP = 1; From e8b4a97d7d1a109688b0d1264adc4a81224a2d2c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 23:47:30 +0100 Subject: [PATCH 282/809] nrf5/hal: Line wrapping params in hal_spi.c to make it easier to read. --- nrf5/hal/hal_spi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_spi.c b/nrf5/hal/hal_spi.c index e710a89be3..86758e840f 100644 --- a/nrf5/hal/hal_spi.c +++ b/nrf5/hal/hal_spi.c @@ -95,7 +95,10 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi p_instance->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos); } -void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, const uint8_t * tx_data, uint8_t * rx_data) { +void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, + uint16_t transfer_size, + const uint8_t * tx_data, + uint8_t * rx_data) { uint16_t number_of_txd_bytes = 0; From 5ae960947c2f96221b213d0d4bf3a31429139c9a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Feb 2017 23:50:43 +0100 Subject: [PATCH 283/809] nrf5/examples: Updating ssd1306.py example with a comment describing proceedure on how to use the I2C variant of the driver. --- nrf5/examples/ssd1306.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/nrf5/examples/ssd1306.py b/nrf5/examples/ssd1306.py index aac2beb986..d9bb957618 100644 --- a/nrf5/examples/ssd1306.py +++ b/nrf5/examples/ssd1306.py @@ -1,5 +1,14 @@ # MicroPython SSD1306 OLED driver, I2C and SPI interfaces +# Example usage for I2C on pca10040 / pca10056 +# +# from machine import Pin, I2C +# from ssd1306 import SSD1306_I2C +# self.scl = Pin("A3", mode=Pin.OUT, pull=Pin.PULL_UP) +# self.sda = Pin("A4", mode=Pin.OUT, pull=Pin.PULL_UP) +# self.i2c = I2C(0, self.scl, self.sda) +# self.ssd = SSD1306_I2C(128, 64, self.i2c) + import time import framebuf from machine import SPI, Pin From 4ddc213d7f99f7167e0cc5c6fa3f82de2f69be2e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 3 Feb 2017 19:28:16 +0100 Subject: [PATCH 284/809] nrf5/boards: Updating board makefiles for s132 and s1xx target for pca10040 (nrf52832) by adding sub variant and device define to the makefiles. --- nrf5/boards/pca10040/mpconfigboard_s132.mk | 2 ++ nrf5/boards/pca10040/mpconfigboard_s1xx.mk | 2 ++ 2 files changed, 4 insertions(+) diff --git a/nrf5/boards/pca10040/mpconfigboard_s132.mk b/nrf5/boards/pca10040/mpconfigboard_s132.mk index 090a08b4b6..c0bdd5b3ca 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s132.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s132.mk @@ -1,4 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 +MCU_SUB_VARIANT = nrf52832 LD_FILE = boards/nrf52832_aa_s132.ld +NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk index 81727fe5de..5bfeca122c 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk @@ -1,4 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 +MCU_SUB_VARIANT = nrf52832 LD_FILE = boards/nrf52832_aa_s1xx.ld +NRF_DEFINES += -DNRF52832_XXAA From 918617d1eb1449e615edeb0834bb036a0ff8da19 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Feb 2017 01:12:30 +0100 Subject: [PATCH 285/809] nrf5/sdk: Adding work-in-progress script to connect to bluetooth le REPL using bluepy python module in linux. --- nrf5/sdk/sdk_12.1.0/ble_repl_linux.py | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 nrf5/sdk/sdk_12.1.0/ble_repl_linux.py diff --git a/nrf5/sdk/sdk_12.1.0/ble_repl_linux.py b/nrf5/sdk/sdk_12.1.0/ble_repl_linux.py new file mode 100644 index 0000000000..5e599fe85b --- /dev/null +++ b/nrf5/sdk/sdk_12.1.0/ble_repl_linux.py @@ -0,0 +1,46 @@ +from bluepy.btle import Scanner, DefaultDelegate, Peripheral, UUID +import struct + +class NotificationDelegate(DefaultDelegate): + def __init__(self): + DefaultDelegate.__init__(self) + + def handleNotification(self, cHandle, data): + print data + +def find_mac_by_name(name): + scanner = Scanner(iface=1) + devices = scanner.scan(5.0) + + found_device = None + for dev in devices: + print "Device %s (%s), RSSI=%d dB" % (dev.addr, dev.addrType, dev.rssi) + for (adtype, desc, value) in dev.getScanData(): + if (desc == "Short Local Name"): + if value == name: + found_device = dev + break + + if found_device: + break + return dev + +dev = find_mac_by_name("micr") +peri = Peripheral(dev) +peri.setDelegate(NotificationDelegate()) + +# service = peri.getServiceByUUID(UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e")) + +rx_char = peri.getCharacteristics(uuid=UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e"))[0] +tx_char = peri.getCharacteristics(uuid=UUID("6e400003-b5a3-f393-e0a9-e50e24dcca9e"))[0] + +# enable cccd +cccd = peri.writeCharacteristic(0x0e, struct.pack(' Date: Sat, 4 Feb 2017 16:08:42 +0100 Subject: [PATCH 286/809] nrf5: Updating main.c to use MICROPY_PY_BLE_NUS as switch for regular uart initialization or bluetooth le uart initialization. --- nrf5/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/main.c b/nrf5/main.c index af87938e22..d7a0f813ef 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -91,7 +91,7 @@ int main(int argc, char **argv) { gc_init(&_heap_start, &_heap_end); -#if (BLUETOOTH_SD == 132) +#if MICROPY_PY_BLE_NUS nrf52_ble_init(); #endif @@ -125,7 +125,7 @@ int main(int argc, char **argv) { timer_init0(); */ -#if (BLUETOOTH_SD != 132) +#if (MICROPY_PY_BLE_NUS == 0) uart_init0(); { mp_obj_t args[2] = { From b6d54cbcafb7a2a2062caf5aac704ffce8c21d52 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Feb 2017 16:15:49 +0100 Subject: [PATCH 287/809] nrf5: Fallback to HW UART when not Bluetooth LE UART has been enabled. --- nrf5/mphalport.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/mphalport.c b/nrf5/mphalport.c index 2de06d2314..b1accbc8f0 100644 --- a/nrf5/mphalport.c +++ b/nrf5/mphalport.c @@ -48,7 +48,7 @@ void mp_hal_set_interrupt_char(int c) { } -#if (BLUETOOTH_SD != 132) +#if (MICROPY_PY_BLE_NUS == 0) int mp_hal_stdin_rx_chr(void) { for (;;) { if (MP_STATE_PORT(pyb_stdio_uart) != NULL && uart_rx_any(MP_STATE_PORT(pyb_stdio_uart))) { @@ -64,7 +64,7 @@ void mp_hal_stdout_tx_str(const char *str) { mp_hal_stdout_tx_strn(str, strlen(str)); } -#if (BLUETOOTH_SD != 132) +#if (MICROPY_PY_BLE_NUS == 0) void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) { if (MP_STATE_PORT(pyb_stdio_uart) != NULL) { uart_tx_strn(MP_STATE_PORT(pyb_stdio_uart), str, len); From f8a71311ed5876bb7b4a97f18043aa67f5621c8e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Feb 2017 16:24:50 +0100 Subject: [PATCH 288/809] nrf5/sdk: Adding compilation config whether to include BLE NUS implementation. Config found in sdk/nrf5_sdk_conf.h. NUS enabled for s132 targets by default. --- nrf5/sdk/sdk_12.1.0/nrf52_ble.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/nrf5/sdk/sdk_12.1.0/nrf52_ble.c b/nrf5/sdk/sdk_12.1.0/nrf52_ble.c index abaec5eac4..7a47f704ee 100644 --- a/nrf5/sdk/sdk_12.1.0/nrf52_ble.c +++ b/nrf5/sdk/sdk_12.1.0/nrf52_ble.c @@ -1,3 +1,7 @@ +#include "py/mpconfig.h" + +#if MICROPY_PY_BLE_NUS + #include "nrf52_ble.h" #include "nrf52_board.h" @@ -485,3 +489,5 @@ mp_hal_stdin_rx_chr() power_manage(); } } + +#endif // MICROPY_PY_BLE_NUS From 357b21ae721171b4dcbba428d848937e6fd4bf95 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Feb 2017 19:32:40 +0100 Subject: [PATCH 289/809] nrf5/drivers: Adding template for ubluepy module. --- nrf5/drivers/ble/modubluepy.c | 72 +++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 nrf5/drivers/ble/modubluepy.c diff --git a/nrf5/drivers/ble/modubluepy.c b/nrf5/drivers/ble/modubluepy.c new file mode 100644 index 0000000000..a49eeddcf4 --- /dev/null +++ b/nrf5/drivers/ble/modubluepy.c @@ -0,0 +1,72 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" + +#if MICROPY_PY_UBLUEPY + +STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy) }, +#if 0 +#if MICROPY_PY_UBLUEPY_PERIPHERAL + { MP_OBJ_NEW_QSTR(MP_QSTR_Peripheral), (mp_obj_t)&ubluepy_peripheral_type }, +#endif +#if MICROPY_PY_UBLUEPY_CENTRAL + { MP_OBJ_NEW_QSTR(MP_QSTR_Central), (mp_obj_t)&ubluepy_central_type }, +#endif +#if MICROPY_PY_UBLUEPY_SCANNER + { MP_OBJ_NEW_QSTR(MP_QSTR_Scanner), (mp_obj_t)&ubluepy_scanner_type }, +#endif +#if MICROPY_PY_UBLUEPY_CENTRAL + { MP_OBJ_NEW_QSTR(MP_QSTR_ScanEntry), (mp_obj_t)&ubluepy_scan_entry_type }, +#endif +#if MICROPY_PY_UBLUEPY_DEFAULT_DELEGATE + { MP_OBJ_NEW_QSTR(MP_QSTR_DefaultDelegate), (mp_obj_t)&ubluepy_default_delegate_type }, +#endif +#if MICROPY_PY_UBLUEPY_UUID + { MP_OBJ_NEW_QSTR(MP_QSTR_UUID), (mp_obj_t)&ubluepy_uuid_type }, +#endif +#if MICROPY_PY_UBLUEPY_SERVICE + { MP_OBJ_NEW_QSTR(MP_QSTR_Service), (mp_obj_t)&ubluepy_service_type }, +#endif +#if MICROPY_PY_UBLUEPY_CHARACTERISTIC + { MP_OBJ_NEW_QSTR(MP_QSTR_Characteristic), (mp_obj_t)&ubluepy_characteristic_type }, +#endif +#if MICROPY_PY_UBLUEPY_DESCRIPTOR + { MP_OBJ_NEW_QSTR(MP_QSTR_Descriptor), (mp_obj_t)&ubluepy_descriptor_type }, +#endif +#endif // 0 +}; + + +STATIC MP_DEFINE_CONST_DICT(mp_module_ubluepy_globals, mp_module_ubluepy_globals_table); + +const mp_obj_module_t mp_module_ubluepy = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&mp_module_ubluepy_globals, +}; + +#endif // MICROPY_PY_UBLUEPY From e68681804ee6546c94d9bcf55397c753e7809fe2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Feb 2017 23:46:29 +0100 Subject: [PATCH 290/809] nrf5: Renaming python modules folder to freeze to give the folder its right meaning. The scripts put into this folder will be frozen. --- nrf5/Makefile | 2 +- nrf5/{modules => freeze}/test.py | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{modules => freeze}/test.py (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index f48736f664..d378334715 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -37,7 +37,7 @@ endif # qstr definitions (must come before including py.mk) QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h -FROZEN_DIR = modules +FROZEN_DIR = freeze # include py core make definitions include ../py/py.mk diff --git a/nrf5/modules/test.py b/nrf5/freeze/test.py similarity index 100% rename from nrf5/modules/test.py rename to nrf5/freeze/test.py From ab21a6a915ef0221fe9ee02b987135a939cd8dcc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Feb 2017 23:51:11 +0100 Subject: [PATCH 291/809] nrf5/drivers: Renaming folder to modules. --- nrf5/Makefile | 4 ++-- nrf5/{drivers => modules}/ble/modubluepy.c | 0 nrf5/{drivers => modules}/display/epaper_sld00200p_driver.c | 0 nrf5/{drivers => modules}/display/epaper_sld00200p_driver.h | 0 nrf5/{drivers => modules}/display/epaper_sld00200p_obj.c | 0 nrf5/{drivers => modules}/display/epaper_sld00200p_obj.h | 0 nrf5/{drivers => modules}/display/framebuffer.c | 0 nrf5/{drivers => modules}/display/framebuffer.h | 0 nrf5/{drivers => modules}/display/lcd_ili9341_driver.c | 0 nrf5/{drivers => modules}/display/lcd_ili9341_driver.h | 0 nrf5/{drivers => modules}/display/lcd_ili9341_obj.c | 0 nrf5/{drivers => modules}/display/lcd_ili9341_obj.h | 0 nrf5/{drivers => modules}/display/lcd_ls0xxb7dxxx_driver.c | 0 nrf5/{drivers => modules}/display/lcd_ls0xxb7dxxx_driver.h | 0 nrf5/{drivers => modules}/display/lcd_ls0xxb7dxxx_obj.c | 0 nrf5/{drivers => modules}/display/lcd_ls0xxb7dxxx_obj.h | 0 nrf5/{drivers => modules}/display/lcd_ssd1289_driver.c | 0 nrf5/{drivers => modules}/display/lcd_ssd1289_driver.h | 0 nrf5/{drivers => modules}/display/lcd_ssd1289_obj.c | 0 nrf5/{drivers => modules}/display/lcd_ssd1289_obj.h | 0 nrf5/{drivers => modules}/display/moddisplay.c | 0 nrf5/{drivers => modules}/display/moddisplay.h | 0 nrf5/{drivers => modules}/display/oled_ssd1305_driver.c | 0 nrf5/{drivers => modules}/display/oled_ssd1305_driver.h | 0 nrf5/{drivers => modules}/display/oled_ssd1305_obj.c | 0 nrf5/{drivers => modules}/display/oled_ssd1305_obj.h | 0 nrf5/{drivers => modules}/display/oled_ssd1306_driver.c | 0 nrf5/{drivers => modules}/display/oled_ssd1306_driver.h | 0 nrf5/{drivers => modules}/display/oled_ssd1306_obj.c | 0 nrf5/{drivers => modules}/display/oled_ssd1306_obj.h | 0 nrf5/{drivers => modules}/display/rgb16.h | 0 nrf5/{drivers => modules}/graphic/draw.c | 0 nrf5/{drivers => modules}/graphic/draw.h | 0 33 files changed, 2 insertions(+), 2 deletions(-) rename nrf5/{drivers => modules}/ble/modubluepy.c (100%) rename nrf5/{drivers => modules}/display/epaper_sld00200p_driver.c (100%) rename nrf5/{drivers => modules}/display/epaper_sld00200p_driver.h (100%) rename nrf5/{drivers => modules}/display/epaper_sld00200p_obj.c (100%) rename nrf5/{drivers => modules}/display/epaper_sld00200p_obj.h (100%) rename nrf5/{drivers => modules}/display/framebuffer.c (100%) rename nrf5/{drivers => modules}/display/framebuffer.h (100%) rename nrf5/{drivers => modules}/display/lcd_ili9341_driver.c (100%) rename nrf5/{drivers => modules}/display/lcd_ili9341_driver.h (100%) rename nrf5/{drivers => modules}/display/lcd_ili9341_obj.c (100%) rename nrf5/{drivers => modules}/display/lcd_ili9341_obj.h (100%) rename nrf5/{drivers => modules}/display/lcd_ls0xxb7dxxx_driver.c (100%) rename nrf5/{drivers => modules}/display/lcd_ls0xxb7dxxx_driver.h (100%) rename nrf5/{drivers => modules}/display/lcd_ls0xxb7dxxx_obj.c (100%) rename nrf5/{drivers => modules}/display/lcd_ls0xxb7dxxx_obj.h (100%) rename nrf5/{drivers => modules}/display/lcd_ssd1289_driver.c (100%) rename nrf5/{drivers => modules}/display/lcd_ssd1289_driver.h (100%) rename nrf5/{drivers => modules}/display/lcd_ssd1289_obj.c (100%) rename nrf5/{drivers => modules}/display/lcd_ssd1289_obj.h (100%) rename nrf5/{drivers => modules}/display/moddisplay.c (100%) rename nrf5/{drivers => modules}/display/moddisplay.h (100%) rename nrf5/{drivers => modules}/display/oled_ssd1305_driver.c (100%) rename nrf5/{drivers => modules}/display/oled_ssd1305_driver.h (100%) rename nrf5/{drivers => modules}/display/oled_ssd1305_obj.c (100%) rename nrf5/{drivers => modules}/display/oled_ssd1305_obj.h (100%) rename nrf5/{drivers => modules}/display/oled_ssd1306_driver.c (100%) rename nrf5/{drivers => modules}/display/oled_ssd1306_driver.h (100%) rename nrf5/{drivers => modules}/display/oled_ssd1306_obj.c (100%) rename nrf5/{drivers => modules}/display/oled_ssd1306_obj.h (100%) rename nrf5/{drivers => modules}/display/rgb16.h (100%) rename nrf5/{drivers => modules}/graphic/draw.c (100%) rename nrf5/{drivers => modules}/graphic/draw.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index d378334715..605f1d385f 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -60,7 +60,7 @@ INC += -I./device INC += -I./device/$(MCU_VARIANT) INC += -I./hal INC += -I./hal/$(MCU_VARIANT) -INC += -I./drivers/display +INC += -I./modules/display INC += -I../lib/mp-readline NRF_DEFINES += -D$(MCU_VARIANT_UPPER) @@ -148,7 +148,7 @@ SRC_C += \ rtc.c \ adc.c \ -DRIVERS_SRC_C += $(addprefix drivers/,\ +DRIVERS_SRC_C += $(addprefix modules/,\ display/moddisplay.c \ display/epaper_sld00200p_obj.c \ display/epaper_sld00200p_driver.c \ diff --git a/nrf5/drivers/ble/modubluepy.c b/nrf5/modules/ble/modubluepy.c similarity index 100% rename from nrf5/drivers/ble/modubluepy.c rename to nrf5/modules/ble/modubluepy.c diff --git a/nrf5/drivers/display/epaper_sld00200p_driver.c b/nrf5/modules/display/epaper_sld00200p_driver.c similarity index 100% rename from nrf5/drivers/display/epaper_sld00200p_driver.c rename to nrf5/modules/display/epaper_sld00200p_driver.c diff --git a/nrf5/drivers/display/epaper_sld00200p_driver.h b/nrf5/modules/display/epaper_sld00200p_driver.h similarity index 100% rename from nrf5/drivers/display/epaper_sld00200p_driver.h rename to nrf5/modules/display/epaper_sld00200p_driver.h diff --git a/nrf5/drivers/display/epaper_sld00200p_obj.c b/nrf5/modules/display/epaper_sld00200p_obj.c similarity index 100% rename from nrf5/drivers/display/epaper_sld00200p_obj.c rename to nrf5/modules/display/epaper_sld00200p_obj.c diff --git a/nrf5/drivers/display/epaper_sld00200p_obj.h b/nrf5/modules/display/epaper_sld00200p_obj.h similarity index 100% rename from nrf5/drivers/display/epaper_sld00200p_obj.h rename to nrf5/modules/display/epaper_sld00200p_obj.h diff --git a/nrf5/drivers/display/framebuffer.c b/nrf5/modules/display/framebuffer.c similarity index 100% rename from nrf5/drivers/display/framebuffer.c rename to nrf5/modules/display/framebuffer.c diff --git a/nrf5/drivers/display/framebuffer.h b/nrf5/modules/display/framebuffer.h similarity index 100% rename from nrf5/drivers/display/framebuffer.h rename to nrf5/modules/display/framebuffer.h diff --git a/nrf5/drivers/display/lcd_ili9341_driver.c b/nrf5/modules/display/lcd_ili9341_driver.c similarity index 100% rename from nrf5/drivers/display/lcd_ili9341_driver.c rename to nrf5/modules/display/lcd_ili9341_driver.c diff --git a/nrf5/drivers/display/lcd_ili9341_driver.h b/nrf5/modules/display/lcd_ili9341_driver.h similarity index 100% rename from nrf5/drivers/display/lcd_ili9341_driver.h rename to nrf5/modules/display/lcd_ili9341_driver.h diff --git a/nrf5/drivers/display/lcd_ili9341_obj.c b/nrf5/modules/display/lcd_ili9341_obj.c similarity index 100% rename from nrf5/drivers/display/lcd_ili9341_obj.c rename to nrf5/modules/display/lcd_ili9341_obj.c diff --git a/nrf5/drivers/display/lcd_ili9341_obj.h b/nrf5/modules/display/lcd_ili9341_obj.h similarity index 100% rename from nrf5/drivers/display/lcd_ili9341_obj.h rename to nrf5/modules/display/lcd_ili9341_obj.h diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c b/nrf5/modules/display/lcd_ls0xxb7dxxx_driver.c similarity index 100% rename from nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.c rename to nrf5/modules/display/lcd_ls0xxb7dxxx_driver.c diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.h b/nrf5/modules/display/lcd_ls0xxb7dxxx_driver.h similarity index 100% rename from nrf5/drivers/display/lcd_ls0xxb7dxxx_driver.h rename to nrf5/modules/display/lcd_ls0xxb7dxxx_driver.h diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c b/nrf5/modules/display/lcd_ls0xxb7dxxx_obj.c similarity index 100% rename from nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.c rename to nrf5/modules/display/lcd_ls0xxb7dxxx_obj.c diff --git a/nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.h b/nrf5/modules/display/lcd_ls0xxb7dxxx_obj.h similarity index 100% rename from nrf5/drivers/display/lcd_ls0xxb7dxxx_obj.h rename to nrf5/modules/display/lcd_ls0xxb7dxxx_obj.h diff --git a/nrf5/drivers/display/lcd_ssd1289_driver.c b/nrf5/modules/display/lcd_ssd1289_driver.c similarity index 100% rename from nrf5/drivers/display/lcd_ssd1289_driver.c rename to nrf5/modules/display/lcd_ssd1289_driver.c diff --git a/nrf5/drivers/display/lcd_ssd1289_driver.h b/nrf5/modules/display/lcd_ssd1289_driver.h similarity index 100% rename from nrf5/drivers/display/lcd_ssd1289_driver.h rename to nrf5/modules/display/lcd_ssd1289_driver.h diff --git a/nrf5/drivers/display/lcd_ssd1289_obj.c b/nrf5/modules/display/lcd_ssd1289_obj.c similarity index 100% rename from nrf5/drivers/display/lcd_ssd1289_obj.c rename to nrf5/modules/display/lcd_ssd1289_obj.c diff --git a/nrf5/drivers/display/lcd_ssd1289_obj.h b/nrf5/modules/display/lcd_ssd1289_obj.h similarity index 100% rename from nrf5/drivers/display/lcd_ssd1289_obj.h rename to nrf5/modules/display/lcd_ssd1289_obj.h diff --git a/nrf5/drivers/display/moddisplay.c b/nrf5/modules/display/moddisplay.c similarity index 100% rename from nrf5/drivers/display/moddisplay.c rename to nrf5/modules/display/moddisplay.c diff --git a/nrf5/drivers/display/moddisplay.h b/nrf5/modules/display/moddisplay.h similarity index 100% rename from nrf5/drivers/display/moddisplay.h rename to nrf5/modules/display/moddisplay.h diff --git a/nrf5/drivers/display/oled_ssd1305_driver.c b/nrf5/modules/display/oled_ssd1305_driver.c similarity index 100% rename from nrf5/drivers/display/oled_ssd1305_driver.c rename to nrf5/modules/display/oled_ssd1305_driver.c diff --git a/nrf5/drivers/display/oled_ssd1305_driver.h b/nrf5/modules/display/oled_ssd1305_driver.h similarity index 100% rename from nrf5/drivers/display/oled_ssd1305_driver.h rename to nrf5/modules/display/oled_ssd1305_driver.h diff --git a/nrf5/drivers/display/oled_ssd1305_obj.c b/nrf5/modules/display/oled_ssd1305_obj.c similarity index 100% rename from nrf5/drivers/display/oled_ssd1305_obj.c rename to nrf5/modules/display/oled_ssd1305_obj.c diff --git a/nrf5/drivers/display/oled_ssd1305_obj.h b/nrf5/modules/display/oled_ssd1305_obj.h similarity index 100% rename from nrf5/drivers/display/oled_ssd1305_obj.h rename to nrf5/modules/display/oled_ssd1305_obj.h diff --git a/nrf5/drivers/display/oled_ssd1306_driver.c b/nrf5/modules/display/oled_ssd1306_driver.c similarity index 100% rename from nrf5/drivers/display/oled_ssd1306_driver.c rename to nrf5/modules/display/oled_ssd1306_driver.c diff --git a/nrf5/drivers/display/oled_ssd1306_driver.h b/nrf5/modules/display/oled_ssd1306_driver.h similarity index 100% rename from nrf5/drivers/display/oled_ssd1306_driver.h rename to nrf5/modules/display/oled_ssd1306_driver.h diff --git a/nrf5/drivers/display/oled_ssd1306_obj.c b/nrf5/modules/display/oled_ssd1306_obj.c similarity index 100% rename from nrf5/drivers/display/oled_ssd1306_obj.c rename to nrf5/modules/display/oled_ssd1306_obj.c diff --git a/nrf5/drivers/display/oled_ssd1306_obj.h b/nrf5/modules/display/oled_ssd1306_obj.h similarity index 100% rename from nrf5/drivers/display/oled_ssd1306_obj.h rename to nrf5/modules/display/oled_ssd1306_obj.h diff --git a/nrf5/drivers/display/rgb16.h b/nrf5/modules/display/rgb16.h similarity index 100% rename from nrf5/drivers/display/rgb16.h rename to nrf5/modules/display/rgb16.h diff --git a/nrf5/drivers/graphic/draw.c b/nrf5/modules/graphic/draw.c similarity index 100% rename from nrf5/drivers/graphic/draw.c rename to nrf5/modules/graphic/draw.c diff --git a/nrf5/drivers/graphic/draw.h b/nrf5/modules/graphic/draw.h similarity index 100% rename from nrf5/drivers/graphic/draw.h rename to nrf5/modules/graphic/draw.h From 8c404909e1f85cfce970bf2a442f6e5b3c9b70d1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Feb 2017 23:56:42 +0100 Subject: [PATCH 292/809] nrf5/machine: Moving modmachine into modules/machine folder. Updating Makefile. --- nrf5/Makefile | 3 ++- nrf5/{ => modules/machine}/modmachine.c | 0 nrf5/{ => modules/machine}/modmachine.h | 0 3 files changed, 2 insertions(+), 1 deletion(-) rename nrf5/{ => modules/machine}/modmachine.c (100%) rename nrf5/{ => modules/machine}/modmachine.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 605f1d385f..cd7bad669a 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -61,6 +61,7 @@ INC += -I./device/$(MCU_VARIANT) INC += -I./hal INC += -I./hal/$(MCU_VARIANT) INC += -I./modules/display +INC += -I./modules/machine INC += -I../lib/mp-readline NRF_DEFINES += -D$(MCU_VARIANT_UPPER) @@ -136,7 +137,6 @@ SRC_C += \ help.c \ gccollect.c \ pin_named_pins.c \ - modmachine.c \ pin.c \ modutime.c \ moduos.c \ @@ -164,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ display/oled_ssd1306_driver.c \ display/framebuffer.c \ graphic/draw.c \ + machine/modmachine.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/modmachine.c b/nrf5/modules/machine/modmachine.c similarity index 100% rename from nrf5/modmachine.c rename to nrf5/modules/machine/modmachine.c diff --git a/nrf5/modmachine.h b/nrf5/modules/machine/modmachine.h similarity index 100% rename from nrf5/modmachine.h rename to nrf5/modules/machine/modmachine.h From cb2d040726e84f778d18df3ed0eb8ad5e1026c2f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 00:00:42 +0100 Subject: [PATCH 293/809] nrf5/uart: Moving uart module into modules/machine to start converting it into machine module and not pyb. --- nrf5/Makefile | 2 +- nrf5/{ => modules/machine}/uart.c | 0 nrf5/{ => modules/machine}/uart.h | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/machine}/uart.c (100%) rename nrf5/{ => modules/machine}/uart.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index cd7bad669a..9dde4f7756 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -130,7 +130,6 @@ SRC_C += \ modpyb.c \ led.c \ mphalport.c \ - uart.c \ spi.c \ pwm.c \ i2c.c \ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ display/framebuffer.c \ graphic/draw.c \ machine/modmachine.c \ + machine/uart.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/uart.c b/nrf5/modules/machine/uart.c similarity index 100% rename from nrf5/uart.c rename to nrf5/modules/machine/uart.c diff --git a/nrf5/uart.h b/nrf5/modules/machine/uart.h similarity index 100% rename from nrf5/uart.h rename to nrf5/modules/machine/uart.h From ab1994b2b27404dc160465d80967bc5c265c9986 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 00:03:49 +0100 Subject: [PATCH 294/809] nrf5/spi: Moving spi module into modules/machine. --- nrf5/Makefile | 2 +- nrf5/{ => modules/machine}/spi.c | 0 nrf5/{ => modules/machine}/spi.h | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/machine}/spi.c (100%) rename nrf5/{ => modules/machine}/spi.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 9dde4f7756..81391d8579 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -130,7 +130,6 @@ SRC_C += \ modpyb.c \ led.c \ mphalport.c \ - spi.c \ pwm.c \ i2c.c \ help.c \ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ graphic/draw.c \ machine/modmachine.c \ machine/uart.c \ + machine/spi.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/spi.c b/nrf5/modules/machine/spi.c similarity index 100% rename from nrf5/spi.c rename to nrf5/modules/machine/spi.c diff --git a/nrf5/spi.h b/nrf5/modules/machine/spi.h similarity index 100% rename from nrf5/spi.h rename to nrf5/modules/machine/spi.h From eea975cd25ba20f0cda8ed5c964780746fc104a5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 00:05:20 +0100 Subject: [PATCH 295/809] nrf5/i2c: Moving i2c module into modules/machine. --- nrf5/Makefile | 2 +- nrf5/{ => modules/machine}/i2c.c | 0 nrf5/{ => modules/machine}/i2c.h | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/machine}/i2c.c (100%) rename nrf5/{ => modules/machine}/i2c.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 81391d8579..a4a47e3a6c 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -131,7 +131,6 @@ SRC_C += \ led.c \ mphalport.c \ pwm.c \ - i2c.c \ help.c \ gccollect.c \ pin_named_pins.c \ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/modmachine.c \ machine/uart.c \ machine/spi.c \ + machine/i2c.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/i2c.c b/nrf5/modules/machine/i2c.c similarity index 100% rename from nrf5/i2c.c rename to nrf5/modules/machine/i2c.c diff --git a/nrf5/i2c.h b/nrf5/modules/machine/i2c.h similarity index 100% rename from nrf5/i2c.h rename to nrf5/modules/machine/i2c.h From 616d76cb7a7267f6befff1d98a27d9573a3c29f7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 16:17:12 +0100 Subject: [PATCH 296/809] nrf5/adc: Moving adc module into modules/machine. --- nrf5/Makefile | 2 +- nrf5/{ => modules/machine}/adc.c | 0 nrf5/{ => modules/machine}/adc.h | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/machine}/adc.c (100%) rename nrf5/{ => modules/machine}/adc.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index a4a47e3a6c..578bb056cd 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -143,7 +143,6 @@ SRC_C += \ modnetwork.c \ timer.c \ rtc.c \ - adc.c \ DRIVERS_SRC_C += $(addprefix modules/,\ display/moddisplay.c \ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/uart.c \ machine/spi.c \ machine/i2c.c \ + machine/adc.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/adc.c b/nrf5/modules/machine/adc.c similarity index 100% rename from nrf5/adc.c rename to nrf5/modules/machine/adc.c diff --git a/nrf5/adc.h b/nrf5/modules/machine/adc.h similarity index 100% rename from nrf5/adc.h rename to nrf5/modules/machine/adc.h From 93eb53357993e7ab48347fda448bfa4c9e0dc688 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 19:56:24 +0100 Subject: [PATCH 297/809] nrf5/pin: Moving pin module into modules/machine. --- nrf5/Makefile | 2 +- nrf5/{ => modules/machine}/pin.c | 0 nrf5/{ => modules/machine}/pin.h | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/machine}/pin.c (100%) rename nrf5/{ => modules/machine}/pin.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 578bb056cd..c67e88153f 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -134,7 +134,6 @@ SRC_C += \ help.c \ gccollect.c \ pin_named_pins.c \ - pin.c \ modutime.c \ moduos.c \ fatfs_port.c \ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/spi.c \ machine/i2c.c \ machine/adc.c \ + machine/pin.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/pin.c b/nrf5/modules/machine/pin.c similarity index 100% rename from nrf5/pin.c rename to nrf5/modules/machine/pin.c diff --git a/nrf5/pin.h b/nrf5/modules/machine/pin.h similarity index 100% rename from nrf5/pin.h rename to nrf5/modules/machine/pin.h From 9295f2df295eaa59378077cd4ada2732a5fa346d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 19:59:34 +0100 Subject: [PATCH 298/809] nrf5/timer: Moving timer module into modules/machine. --- nrf5/Makefile | 2 +- nrf5/{ => modules/machine}/timer.c | 0 nrf5/{ => modules/machine}/timer.h | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/machine}/timer.c (100%) rename nrf5/{ => modules/machine}/timer.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index c67e88153f..310b936331 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -140,7 +140,6 @@ SRC_C += \ builtin_open.c \ modusocket.c \ modnetwork.c \ - timer.c \ rtc.c \ DRIVERS_SRC_C += $(addprefix modules/,\ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/i2c.c \ machine/adc.c \ machine/pin.c \ + machine/timer.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/timer.c b/nrf5/modules/machine/timer.c similarity index 100% rename from nrf5/timer.c rename to nrf5/modules/machine/timer.c diff --git a/nrf5/timer.h b/nrf5/modules/machine/timer.h similarity index 100% rename from nrf5/timer.h rename to nrf5/modules/machine/timer.h From a7103ef551f2519224fe96f7a0b3db6f158083fb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 20:01:15 +0100 Subject: [PATCH 299/809] nrf5/rtc: Moving rtc module into modules/machine. --- nrf5/Makefile | 2 +- nrf5/{ => modules/machine}/rtc.c | 0 nrf5/{ => modules/machine}/rtc.h | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/machine}/rtc.c (100%) rename nrf5/{ => modules/machine}/rtc.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 310b936331..e6e1c650bc 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -140,7 +140,6 @@ SRC_C += \ builtin_open.c \ modusocket.c \ modnetwork.c \ - rtc.c \ DRIVERS_SRC_C += $(addprefix modules/,\ display/moddisplay.c \ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/adc.c \ machine/pin.c \ machine/timer.c \ + machine/rtc.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/rtc.c b/nrf5/modules/machine/rtc.c similarity index 100% rename from nrf5/rtc.c rename to nrf5/modules/machine/rtc.c diff --git a/nrf5/rtc.h b/nrf5/modules/machine/rtc.h similarity index 100% rename from nrf5/rtc.h rename to nrf5/modules/machine/rtc.h From 86019632910ddaacaf2fed18cf348159413db78c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 20:03:52 +0100 Subject: [PATCH 300/809] nrf5/pwm: Moving pwm module into modules/machine. --- nrf5/Makefile | 2 +- nrf5/{ => modules/machine}/pwm.c | 0 nrf5/{ => modules/machine}/pwm.h | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/machine}/pwm.c (100%) rename nrf5/{ => modules/machine}/pwm.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index e6e1c650bc..7f58013030 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -130,7 +130,6 @@ SRC_C += \ modpyb.c \ led.c \ mphalport.c \ - pwm.c \ help.c \ gccollect.c \ pin_named_pins.c \ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/pin.c \ machine/timer.c \ machine/rtc.c \ + machine/pwm.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/pwm.c b/nrf5/modules/machine/pwm.c similarity index 100% rename from nrf5/pwm.c rename to nrf5/modules/machine/pwm.c diff --git a/nrf5/pwm.h b/nrf5/modules/machine/pwm.h similarity index 100% rename from nrf5/pwm.h rename to nrf5/modules/machine/pwm.h From 42e9b0f73520fd4acb3a26d4b3564058064d5a5d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 20:06:06 +0100 Subject: [PATCH 301/809] nrf5/led: Moving led module into modules/machine. --- nrf5/{ => modules/machine}/led.c | 0 nrf5/{ => modules/machine}/led.h | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/{ => modules/machine}/led.c (100%) rename nrf5/{ => modules/machine}/led.h (100%) diff --git a/nrf5/led.c b/nrf5/modules/machine/led.c similarity index 100% rename from nrf5/led.c rename to nrf5/modules/machine/led.c diff --git a/nrf5/led.h b/nrf5/modules/machine/led.h similarity index 100% rename from nrf5/led.h rename to nrf5/modules/machine/led.h From 3c71e754619eb2683828ecea57004d98ba7251c0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 20:06:24 +0100 Subject: [PATCH 302/809] nrf5/led: Moving led module into modules/machine. --- nrf5/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 7f58013030..6f9447e927 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -128,7 +128,6 @@ endif SRC_C += \ main.c \ modpyb.c \ - led.c \ mphalport.c \ help.c \ gccollect.c \ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/timer.c \ machine/rtc.c \ machine/pwm.c \ + machine/led.c \ ) #ifeq ($(SD), ) From 9fcef29dfa3e131466dd25c3c7cd51a9ac229778 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 20:15:50 +0100 Subject: [PATCH 303/809] nrf5/usocket: Moving usocket module into modules/usocket. --- nrf5/Makefile | 2 +- nrf5/{ => modules/usocket}/modusocket.c | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/usocket}/modusocket.c (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 6f9447e927..58265dd310 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -136,7 +136,6 @@ SRC_C += \ moduos.c \ fatfs_port.c \ builtin_open.c \ - modusocket.c \ modnetwork.c \ DRIVERS_SRC_C += $(addprefix modules/,\ @@ -165,6 +164,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/rtc.c \ machine/pwm.c \ machine/led.c \ + usocket/modusocket.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/modusocket.c b/nrf5/modules/usocket/modusocket.c similarity index 100% rename from nrf5/modusocket.c rename to nrf5/modules/usocket/modusocket.c From 0983f43ae1f7a2acf12365f161a1d4bfcc295863 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 20:19:52 +0100 Subject: [PATCH 304/809] nrf5/network: Moving network module into modules/network. Adding include path to network as its needed by the usocket module. --- nrf5/Makefile | 3 ++- nrf5/{ => modules/network}/modnetwork.c | 0 nrf5/{ => modules/network}/modnetwork.h | 0 3 files changed, 2 insertions(+), 1 deletion(-) rename nrf5/{ => modules/network}/modnetwork.c (100%) rename nrf5/{ => modules/network}/modnetwork.h (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 58265dd310..14043e1abf 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -62,6 +62,7 @@ INC += -I./hal INC += -I./hal/$(MCU_VARIANT) INC += -I./modules/display INC += -I./modules/machine +INC += -I./modules/network INC += -I../lib/mp-readline NRF_DEFINES += -D$(MCU_VARIANT_UPPER) @@ -136,7 +137,6 @@ SRC_C += \ moduos.c \ fatfs_port.c \ builtin_open.c \ - modnetwork.c \ DRIVERS_SRC_C += $(addprefix modules/,\ display/moddisplay.c \ @@ -165,6 +165,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/pwm.c \ machine/led.c \ usocket/modusocket.c \ + network/modnetwork.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/modnetwork.c b/nrf5/modules/network/modnetwork.c similarity index 100% rename from nrf5/modnetwork.c rename to nrf5/modules/network/modnetwork.c diff --git a/nrf5/modnetwork.h b/nrf5/modules/network/modnetwork.h similarity index 100% rename from nrf5/modnetwork.h rename to nrf5/modules/network/modnetwork.h From 65fb0c9829f7da73bbffa47a00e6a86a01a9b9cb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 20:25:27 +0100 Subject: [PATCH 305/809] nrf5/uos: Moving uos module into modules/uos. --- nrf5/Makefile | 2 +- nrf5/{ => modules/uos}/moduos.c | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/uos}/moduos.c (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 14043e1abf..7f1b6b62b3 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -134,7 +134,6 @@ SRC_C += \ gccollect.c \ pin_named_pins.c \ modutime.c \ - moduos.c \ fatfs_port.c \ builtin_open.c \ @@ -166,6 +165,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/led.c \ usocket/modusocket.c \ network/modnetwork.c \ + uos/moduos.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/moduos.c b/nrf5/modules/uos/moduos.c similarity index 100% rename from nrf5/moduos.c rename to nrf5/modules/uos/moduos.c From 2ad9426917dab526e8ab7ae8cc8105b2a89fd663 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 20:28:26 +0100 Subject: [PATCH 306/809] nrf5/utime: Moving utime module into modules/utime. --- nrf5/Makefile | 2 +- nrf5/{ => modules/utime}/modutime.c | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/utime}/modutime.c (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 7f1b6b62b3..85353567bc 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -133,7 +133,6 @@ SRC_C += \ help.c \ gccollect.c \ pin_named_pins.c \ - modutime.c \ fatfs_port.c \ builtin_open.c \ @@ -166,6 +165,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ usocket/modusocket.c \ network/modnetwork.c \ uos/moduos.c \ + utime/modutime.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/modutime.c b/nrf5/modules/utime/modutime.c similarity index 100% rename from nrf5/modutime.c rename to nrf5/modules/utime/modutime.c From 2b1ceadfab2e42b78ee43d8b9fd93901317600a8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 20:30:58 +0100 Subject: [PATCH 307/809] nrf5/pyb: Moving pyb module into modules/pyb. --- nrf5/Makefile | 2 +- nrf5/{ => modules/pyb}/modpyb.c | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/{ => modules/pyb}/modpyb.c (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index 85353567bc..984281e4b2 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -128,7 +128,6 @@ endif SRC_C += \ main.c \ - modpyb.c \ mphalport.c \ help.c \ gccollect.c \ @@ -166,6 +165,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ network/modnetwork.c \ uos/moduos.c \ utime/modutime.c \ + pyb/modpyb.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/modpyb.c b/nrf5/modules/pyb/modpyb.c similarity index 100% rename from nrf5/modpyb.c rename to nrf5/modules/pyb/modpyb.c From 21c4e4633ba76f6ba8d40c9ff687dc1583b49cd9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 21:10:06 +0100 Subject: [PATCH 308/809] nrf5/modules: Adding new template file for ubluepy Peripheral class. --- nrf5/modules/ble/ubluepy_peripheral.c | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 nrf5/modules/ble/ubluepy_peripheral.c diff --git a/nrf5/modules/ble/ubluepy_peripheral.c b/nrf5/modules/ble/ubluepy_peripheral.c new file mode 100644 index 0000000000..1aff1105b3 --- /dev/null +++ b/nrf5/modules/ble/ubluepy_peripheral.c @@ -0,0 +1,31 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" + +#if MICROPY_PY_UBLUEPY_PERIPHERAL + +#endif // MICROPY_PY_UBLUEPY_PERIPHERAL From 73d00c98a0da9d58f645c2cf07f7d9afdc9f8ec9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Feb 2017 21:10:44 +0100 Subject: [PATCH 309/809] nrf5/modules: Renaming ble module folder to ubluepy. --- nrf5/modules/{ble => ubluepy}/modubluepy.c | 0 nrf5/modules/{ble => ubluepy}/ubluepy_peripheral.c | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/modules/{ble => ubluepy}/modubluepy.c (100%) rename nrf5/modules/{ble => ubluepy}/ubluepy_peripheral.c (100%) diff --git a/nrf5/modules/ble/modubluepy.c b/nrf5/modules/ubluepy/modubluepy.c similarity index 100% rename from nrf5/modules/ble/modubluepy.c rename to nrf5/modules/ubluepy/modubluepy.c diff --git a/nrf5/modules/ble/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c similarity index 100% rename from nrf5/modules/ble/ubluepy_peripheral.c rename to nrf5/modules/ubluepy/ubluepy_peripheral.c From 3cd518af3a730bf502df12e5ac09c9daa0e63b9c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Feb 2017 20:19:06 +0100 Subject: [PATCH 310/809] nrf5/modules: Updating ubluepy with class function placeholders. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 1aff1105b3..da1770c6b7 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -28,4 +28,43 @@ #if MICROPY_PY_UBLUEPY_PERIPHERAL +STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { +#if 0 + +// #if UBLUEPY_CENTRAL + { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getServiceByUUID), (mp_obj_t)(&ubluepy_peripheral_get_service_by_uuid_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_peripheral_get_chars_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getDescriptors), (mp_obj_t)(&ubluepy_peripheral_get_descs_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_waitForNotifications), (mp_obj_t)(&ubluepy_peripheral_wait_for_notif_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, +// #if UBLUEPY_PERIPHERAL + { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setService), (mp_obj_t)(&ubluepy_peripheral_set_service_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setCharacteristic), (mp_obj_t)(&ubluepy_peripheral_set_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setDescriptor), (mp_obj_t)(&ubluepy_peripheral_set_desc_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, +// #if UBLUEPY_BROADCASTER + { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_peripheral_locals_dict, ubluepy_peripheral_locals_dict_table); + +const mp_obj_type_t ubluepy_peripheral_type = { + { &mp_type_type }, + .name = MP_QSTR_Peripheral, +#if 0 + .print = ubluepy_peripheral_print, + .make_new = ubluepy_peripheral_make_new, + .locals_dict = (mp_obj_t)&ubluepy_peripheral_locals_dict +#endif +}; + #endif // MICROPY_PY_UBLUEPY_PERIPHERAL From c2fb8bf9c2db705b90a2d16e8af470bf2f388832 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Feb 2017 20:36:36 +0100 Subject: [PATCH 311/809] nrf5/modules: Adding ubluepy service class template. --- nrf5/modules/ubluepy/ubluepy_service.c | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 nrf5/modules/ubluepy/ubluepy_service.c diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c new file mode 100644 index 0000000000..3b5d64f09b --- /dev/null +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -0,0 +1,49 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" + +#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL + +STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristic), (mp_obj_t)(&ubluepy_service_get_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setCharacteristic), (mp_obj_t)(&ubluepy_service_set_char_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_service_locals_dict, ubluepy_service_locals_dict_table); + +const mp_obj_type_t ubluepy_service_type = { + { &mp_type_type }, + .name = MP_QSTR_Service, +#if 0 + .print = ubluepy_service_print, + .make_new = ubluepy_service_make_new, + .locals_dict = (mp_obj_t)&ubluepy_service_locals_dict +#endif +}; + +#endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL From 4cda1b37fde404e58f768287baeffd18505ca35a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Feb 2017 20:41:42 +0100 Subject: [PATCH 312/809] nrf5/modules: Adding missing #endif. Also adding to property templates to the lolcal dict. --- nrf5/modules/ubluepy/ubluepy_service.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 3b5d64f09b..3bb11716a2 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -32,6 +32,10 @@ STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { #if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristic), (mp_obj_t)(&ubluepy_service_get_char_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_setCharacteristic), (mp_obj_t)(&ubluepy_service_set_char_obj) }, + // Properties + { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_service_get_peripheral_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_service_get_uuid_obj) }, +#endif }; STATIC MP_DEFINE_CONST_DICT(ubluepy_service_locals_dict, ubluepy_service_locals_dict_table); From ef5228ae57cb92c287797acaaa41393f496d3ebf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Feb 2017 20:48:01 +0100 Subject: [PATCH 313/809] nrf5/modules: Adding ubluepy characteristic class template. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 nrf5/modules/ubluepy/ubluepy_characteristic.c diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c new file mode 100644 index 0000000000..0deb3f35df --- /dev/null +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -0,0 +1,58 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" + +#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL + +STATIC const mp_map_elem_t ubluepy_characteristic_locals_dict_table[] = { +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)(&ubluepy_characteristic_read_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_write), (mp_obj_t)(&ubluepy_characteristic_write_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_supportsRead), (mp_obj_t)(&ubluepy_characteristic_supports_read_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_propertiesToString), (mp_obj_t)(&ubluepy_characteristic_properties_to_str_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getHandle), (mp_obj_t)(&ubluepy_characteristic_get_handle_obj) }, + + // Properties + { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_characteristic_get_peripheral_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_characteristic_get_uuid_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_properties), (mp_obj_t)(&ubluepy_characteristic_get_properties_obj) }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_characteristic_locals_dict, ubluepy_characteristic_locals_dict_table); + +const mp_obj_type_t ubluepy_characteristic_type = { + { &mp_type_type }, + .name = MP_QSTR_Characteristic, +#if 0 + .print = ubluepy_characteristic_print, + .make_new = ubluepy_characteristic_make_new, + .locals_dict = (mp_obj_t)&ubluepy_characteristic_locals_dict +#endif +}; + +#endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL From b6779fa95a9294ffa8ebd3f554027bdde9822ab7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Feb 2017 20:51:24 +0100 Subject: [PATCH 314/809] nrf5/modules: Adding ubluepy UUID class template. --- nrf5/modules/ubluepy/ubluepy_uuid.c | 51 +++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 nrf5/modules/ubluepy/ubluepy_uuid.c diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c new file mode 100644 index 0000000000..02545f0e18 --- /dev/null +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -0,0 +1,51 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" + +#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL + +STATIC const mp_map_elem_t ubluepy_uuid_locals_dict_table[] = { +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_getCommonName), (mp_obj_t)(&ubluepy_uuid_get_common_name_obj) }, + // Properties + { MP_OBJ_NEW_QSTR(MP_QSTR_binVal), (mp_obj_t)(&ubluepy_uuid_bin_val_obj) }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_uuid_locals_dict, ubluepy_uuid_locals_dict_table); + +const mp_obj_type_t ubluepy_uuid_type = { + { &mp_type_type }, + .name = MP_QSTR_UUID, +#if 0 + .print = ubluepy_uuid_print, + .make_new = ubluepy_uuid_make_new, + .locals_dict = (mp_obj_t)&ubluepy_uuid_locals_dict +#endif +}; + +#endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL From 723943abde3e9de5e14ee40df5e0d5fe25352c97 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 7 Feb 2017 22:17:55 +0100 Subject: [PATCH 315/809] nrf5/modules: Adding new and print function to ubluepy peripheral class. Template functions only. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 37 +++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index da1770c6b7..7e9f43a6ba 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -26,8 +26,43 @@ #include "py/obj.h" + + #if MICROPY_PY_UBLUEPY_PERIPHERAL +typedef struct _ubluepy_peripheral_obj_t { + mp_obj_base_t base; + // services +} ubluepy_peripheral_obj_t; + +STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + ubluepy_peripheral_obj_t * self = o; + mp_printf(print, "Peripheral"); +} + +// for make_new +enum { + ARG_NEW_DEVICE_ADDR, + ARG_NEW_ADDR_TYPE +}; + +STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { ARG_NEW_DEVICE_ADDR, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_ADDR_TYPE, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + ubluepy_peripheral_obj_t *s = m_new_obj(ubluepy_peripheral_obj_t); + s->base.type = type; + + return MP_OBJ_FROM_PTR(s); +} + + STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { #if 0 @@ -60,11 +95,9 @@ STATIC MP_DEFINE_CONST_DICT(ubluepy_peripheral_locals_dict, ubluepy_peripheral_l const mp_obj_type_t ubluepy_peripheral_type = { { &mp_type_type }, .name = MP_QSTR_Peripheral, -#if 0 .print = ubluepy_peripheral_print, .make_new = ubluepy_peripheral_make_new, .locals_dict = (mp_obj_t)&ubluepy_peripheral_locals_dict -#endif }; #endif // MICROPY_PY_UBLUEPY_PERIPHERAL From 0f609cd79952b24f5340b2f3a88a2a75e4ded68a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 7 Feb 2017 23:30:12 +0100 Subject: [PATCH 316/809] nrf5: Aligning code after upmerge with master. Mostly FAT FS related updates. Not tested after merge. --- nrf5/Makefile | 9 +- nrf5/fatfs_port.c | 17 +- nrf5/main.c | 3 - nrf5/modules/machine/modmachine.c | 4 +- nrf5/modules/uos/moduos.c | 287 +++--------------------------- nrf5/mpconfigport.h | 15 +- 6 files changed, 42 insertions(+), 293 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 984281e4b2..8b0a37b81b 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -43,7 +43,7 @@ FROZEN_DIR = freeze include ../py/py.mk -FATFS_DIR = lib/fatfs +FATFS_DIR = lib/oofatfs MPY_CROSS = ../mpy-cross/mpy-cross MPY_TOOL = ../tools/mpy-tool.py @@ -76,7 +76,7 @@ CFLAGS_MCU_m0 = $(CFLAGS_CORTEX_M) --short-enums -mtune=cortex-m0 -mcpu=cortex-m CFLAGS += $(CFLAGS_MCU_$(MCU_SERIES)) -CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) +CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) $(CFLAGS_MOD) CFLAGS += -fno-strict-aliasing CFLAGS += -Iboards/$(BOARD) CFLAGS += -DNRF5_HAL_H='<$(MCU_VARIANT)_hal.h>' @@ -102,8 +102,8 @@ SRC_LIB = $(addprefix lib/,\ mp-readline/readline.c \ utils/pyexec.c \ timeutils/timeutils.c \ - fatfs/ff.c \ - fatfs/option/ccsbcs.c \ + oofatfs/ff.c \ + oofatfs/option/unicode.c \ netutils/netutils.c \ ) @@ -133,7 +133,6 @@ SRC_C += \ gccollect.c \ pin_named_pins.c \ fatfs_port.c \ - builtin_open.c \ DRIVERS_SRC_C += $(addprefix modules/,\ display/moddisplay.c \ diff --git a/nrf5/fatfs_port.c b/nrf5/fatfs_port.c index c7b15a703c..4d44e2d1d5 100644 --- a/nrf5/fatfs_port.c +++ b/nrf5/fatfs_port.c @@ -24,23 +24,10 @@ * THE SOFTWARE. */ -#include "py/mphal.h" #include "py/runtime.h" -#include "lib/fatfs/ff.h" /* FatFs lower layer API */ -#include "lib/fatfs/diskio.h" /* FatFs lower layer API */ -//#include "rtc.h" - -const PARTITION VolToPart[MICROPY_FATFS_VOLUMES] = { - {0, 1}, // Logical drive 0 ==> Physical drive 0, 1st partition - {1, 0}, // Logical drive 1 ==> Physical drive 1 (auto detection) - {2, 0}, // Logical drive 2 ==> Physical drive 2 (auto detection) - {3, 0}, // Logical drive 3 ==> Physical drive 3 (auto detection) - /* - {0, 2}, // Logical drive 2 ==> Physical drive 0, 2nd partition - {0, 3}, // Logical drive 3 ==> Physical drive 0, 3rd partition - */ -}; +#include "lib/oofatfs/ff.h" DWORD get_fattime(void) { + // TODO: Implement this function. For now, fake it. return ((2000 + 2016 - 1980) << 25) | ((12) << 21) | ((4) << 16) | ((00) << 11) | ((18) << 5) | (23 / 2); } diff --git a/nrf5/main.c b/nrf5/main.c index d7a0f813ef..b998e84e98 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -223,9 +223,6 @@ void HardFault_Handler(void) #endif } -mp_import_stat_t mp_import_stat(const char *path) { - return MP_IMPORT_STAT_NO_EXIST; -} void nlr_jump_fail(void *val) { } diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 7b5b6f01b7..101123dcce 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -34,8 +34,8 @@ #include "extmod/machine_pulse.h" #include "extmod/machine_i2c.h" #include "lib/utils/pyexec.h" -#include "lib/fatfs/ff.h" -#include "lib/fatfs/diskio.h" +#include "lib/oofatfs/ff.h" +#include "lib/oofatfs/diskio.h" #include "gccollect.h" #include "pin.h" #include "spi.h" diff --git a/nrf5/modules/uos/moduos.c b/nrf5/modules/uos/moduos.c index e3bf4c1ae1..35bc3f0e64 100644 --- a/nrf5/modules/uos/moduos.c +++ b/nrf5/modules/uos/moduos.c @@ -31,15 +31,14 @@ #include "py/runtime.h" #include "py/objtuple.h" #include "py/objstr.h" +#include "lib/oofatfs/ff.h" +#include "lib/oofatfs/diskio.h" +#include "extmod/vfs.h" +#include "extmod/vfs_fat.h" #include "genhdr/mpversion.h" -#include "lib/fatfs/ff.h" -#include "lib/fatfs/diskio.h" -#include "lib/timeutils/timeutils.h" +//#include "timeutils.h" //#include "rng.h" #include "uart.h" -#include "extmod/vfs_fat_file.h" -//#include "sdcard.h" -#include "extmod/fsusermount.h" //#include "portmodules.h" /// \module os - basic "operating system" services @@ -80,255 +79,13 @@ STATIC mp_obj_t os_uname(void) { } STATIC MP_DEFINE_CONST_FUN_OBJ_0(os_uname_obj, os_uname); -/// \function chdir(path) -/// Change current directory. -STATIC mp_obj_t os_chdir(mp_obj_t path_in) { - const char *path; - path = mp_obj_str_get_str(path_in); - - FRESULT res = f_chdrive(path); - - if (res == FR_OK) { - res = f_chdir(path); - } - - if (res != FR_OK) { - // TODO should be mp_type_FileNotFoundError - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "No such file or directory: '%s'", path)); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_chdir_obj, os_chdir); - -/// \function getcwd() -/// Get the current directory. -STATIC mp_obj_t os_getcwd(void) { - char buf[MICROPY_ALLOC_PATH_MAX + 1]; - FRESULT res = f_getcwd(buf, sizeof buf); - - if (res != FR_OK) { - mp_raise_OSError(fresult_to_errno_table[res]); - } - - return mp_obj_new_str(buf, strlen(buf), false); -} -STATIC MP_DEFINE_CONST_FUN_OBJ_0(os_getcwd_obj, os_getcwd); - -/// \function listdir([dir]) -/// With no argument, list the current directory. Otherwise list the given directory. -STATIC mp_obj_t os_listdir(mp_uint_t n_args, const mp_obj_t *args) { - bool is_str_type = true; - const char *path; - if (n_args == 1) { - if (mp_obj_get_type(args[0]) == &mp_type_bytes) { - is_str_type = false; - } - path = mp_obj_str_get_str(args[0]); - } else { - path = ""; - } - - // "hack" to list root directory - if (path[0] == '/' && path[1] == '\0') { - mp_obj_t dir_list = mp_obj_new_list(0, NULL); - for (size_t i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(fs_user_mount)); ++i) { - fs_user_mount_t *vfs = MP_STATE_PORT(fs_user_mount)[i]; - if (vfs != NULL) { - mp_obj_list_append(dir_list, mp_obj_new_str(vfs->str + 1, vfs->len - 1, false)); - } - } - return dir_list; - } - - return fat_vfs_listdir(path, is_str_type); -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(os_listdir_obj, 0, 1, os_listdir); - -/// \function mkdir(path) -/// Create a new directory. -STATIC mp_obj_t os_mkdir(mp_obj_t path_o) { - const char *path = mp_obj_str_get_str(path_o); - FRESULT res = f_mkdir(path); - switch (res) { - case FR_OK: - return mp_const_none; - case FR_EXIST: - // TODO should be FileExistsError - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "File exists: '%s'", path)); - default: - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error creating directory '%s'", path)); - } -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_mkdir_obj, os_mkdir); - -/// \function remove(path) -/// Remove a file. -STATIC mp_obj_t os_remove(mp_obj_t path_o) { - const char *path = mp_obj_str_get_str(path_o); - // TODO check that path is actually a file before trying to unlink it - FRESULT res = f_unlink(path); - switch (res) { - case FR_OK: - return mp_const_none; - default: - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error removing file '%s'", path)); - } -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_remove_obj, os_remove); - -/// \function rename(old_path, new_path) -/// Rename a file -STATIC mp_obj_t os_rename(mp_obj_t path_in, mp_obj_t path_out) { - const char *old_path = mp_obj_str_get_str(path_in); - const char *new_path = mp_obj_str_get_str(path_out); - FRESULT res = f_rename(old_path, new_path); - switch (res) { - case FR_OK: - return mp_const_none; - default: - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error renaming file '%s' to '%s'", old_path, new_path)); - } - -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(os_rename_obj, os_rename); - -/// \function rmdir(path) -/// Remove a directory. -STATIC mp_obj_t os_rmdir(mp_obj_t path_o) { - const char *path = mp_obj_str_get_str(path_o); - // TODO check that path is actually a directory before trying to unlink it - FRESULT res = f_unlink(path); - switch (res) { - case FR_OK: - return mp_const_none; - default: - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error removing directory '%s'", path)); - } -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_rmdir_obj, os_rmdir); - -// Checks for path equality, ignoring trailing slashes: -// path_equal(/, /) -> true -// path_equal(/flash//, /flash) -> true -// second argument must be in canonical form (meaning no trailing slash, unless it's just /) -STATIC bool path_equal(const char *path, const char *path_canonical) { - for (; *path_canonical != '\0' && *path == *path_canonical; ++path, ++path_canonical) { - } - if (*path_canonical != '\0') { - return false; - } - for (; *path == '/'; ++path) { - } - return *path == '\0'; -} - -/// \function stat(path) -/// Get the status of a file or directory. -STATIC mp_obj_t os_stat(mp_obj_t path_in) { - const char *path = mp_obj_str_get_str(path_in); - - FILINFO fno; -#if _USE_LFN - fno.lfname = NULL; - fno.lfsize = 0; -#endif - - FRESULT res; - if (path_equal(path, "/")) { - // stat root directory - fno.fsize = 0; - fno.fdate = 0; - fno.ftime = 0; - fno.fattrib = AM_DIR; - } else { - res = FR_NO_PATH; - for (size_t i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(fs_user_mount)); ++i) { - fs_user_mount_t *vfs = MP_STATE_PORT(fs_user_mount)[i]; - if (vfs != NULL && path_equal(path, vfs->str)) { - // stat mounted device directory - fno.fsize = 0; - fno.fdate = 0; - fno.ftime = 0; - fno.fattrib = AM_DIR; - res = FR_OK; - } - } - if (res == FR_NO_PATH) { - // stat normal file - res = f_stat(path, &fno); - } - if (res != FR_OK) { - mp_raise_OSError(fresult_to_errno_table[res]); - } - } - - mp_obj_tuple_t *t = mp_obj_new_tuple(10, NULL); - mp_int_t mode = 0; - if (fno.fattrib & AM_DIR) { - mode |= 0x4000; // stat.S_IFDIR - } else { - mode |= 0x8000; // stat.S_IFREG - } - mp_int_t seconds = timeutils_seconds_since_2000( - 1980 + ((fno.fdate >> 9) & 0x7f), - (fno.fdate >> 5) & 0x0f, - fno.fdate & 0x1f, - (fno.ftime >> 11) & 0x1f, - (fno.ftime >> 5) & 0x3f, - 2 * (fno.ftime & 0x1f) - ); - t->items[0] = MP_OBJ_NEW_SMALL_INT(mode); // st_mode - t->items[1] = MP_OBJ_NEW_SMALL_INT(0); // st_ino - t->items[2] = MP_OBJ_NEW_SMALL_INT(0); // st_dev - t->items[3] = MP_OBJ_NEW_SMALL_INT(0); // st_nlink - t->items[4] = MP_OBJ_NEW_SMALL_INT(0); // st_uid - t->items[5] = MP_OBJ_NEW_SMALL_INT(0); // st_gid - t->items[6] = MP_OBJ_NEW_SMALL_INT(fno.fsize); // st_size - t->items[7] = MP_OBJ_NEW_SMALL_INT(seconds); // st_atime - t->items[8] = MP_OBJ_NEW_SMALL_INT(seconds); // st_mtime - t->items[9] = MP_OBJ_NEW_SMALL_INT(seconds); // st_ctime - - return t; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_stat_obj, os_stat); - -STATIC mp_obj_t os_statvfs(mp_obj_t path_in) { - const char *path = mp_obj_str_get_str(path_in); - - DWORD nclst; - FATFS *fatfs; - FRESULT res = f_getfree(path, &nclst, &fatfs); - if (res != FR_OK) { - goto error; - } - - mp_obj_tuple_t *t = mp_obj_new_tuple(10, NULL); - - t->items[0] = MP_OBJ_NEW_SMALL_INT(fatfs->csize * 512); // f_bsize - block size - t->items[1] = t->items[0]; // f_frsize - fragment size - t->items[2] = MP_OBJ_NEW_SMALL_INT((fatfs->n_fatent - 2) * fatfs->csize); // f_blocks - total number of blocks - t->items[3] = MP_OBJ_NEW_SMALL_INT(nclst); // f_bfree - number of free blocks - t->items[4] = t->items[3]; // f_bavail - free blocks avail to unpriviledged users - t->items[5] = MP_OBJ_NEW_SMALL_INT(0); // f_files - # inodes - t->items[6] = MP_OBJ_NEW_SMALL_INT(0); // f_ffree - # free inodes - t->items[7] = MP_OBJ_NEW_SMALL_INT(0); // f_favail - # free inodes avail to unpriviledges users - t->items[8] = MP_OBJ_NEW_SMALL_INT(0); // f_flags - t->items[9] = MP_OBJ_NEW_SMALL_INT(_MAX_LFN); // f_namemax - - return t; - -error: - mp_raise_OSError(fresult_to_errno_table[res]); -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_statvfs_obj, os_statvfs); - /// \function sync() /// Sync all filesystems. STATIC mp_obj_t os_sync(void) { - disk_ioctl(0, CTRL_SYNC, NULL); - disk_ioctl(1, CTRL_SYNC, NULL); - disk_ioctl(2, CTRL_SYNC, NULL); + for (mp_vfs_mount_t *vfs = MP_STATE_VM(vfs_mount_table); vfs != NULL; vfs = vfs->next) { + // this assumes that vfs->obj is fs_user_mount_t with block device functions + disk_ioctl(MP_OBJ_TO_PTR(vfs->obj), CTRL_SYNC, NULL); + } return mp_const_none; } MP_DEFINE_CONST_FUN_OBJ_0(mod_os_sync_obj, os_sync); @@ -376,16 +133,16 @@ STATIC const mp_map_elem_t os_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_uname), (mp_obj_t)&os_uname_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_chdir), (mp_obj_t)&os_chdir_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getcwd), (mp_obj_t)&os_getcwd_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_listdir), (mp_obj_t)&os_listdir_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_mkdir), (mp_obj_t)&os_mkdir_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_remove), (mp_obj_t)&os_remove_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_rename),(mp_obj_t)&os_rename_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_rmdir), (mp_obj_t)&os_rmdir_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_stat), (mp_obj_t)&os_stat_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_statvfs), (mp_obj_t)&os_statvfs_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_unlink), (mp_obj_t)&os_remove_obj }, // unlink aliases to remove + { MP_OBJ_NEW_QSTR(MP_QSTR_chdir), (mp_obj_t)&mp_vfs_chdir_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getcwd), (mp_obj_t)&mp_vfs_getcwd_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_listdir), (mp_obj_t)&mp_vfs_listdir_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_mkdir), (mp_obj_t)&mp_vfs_mkdir_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_remove), (mp_obj_t)&mp_vfs_remove_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_rename),(mp_obj_t)&mp_vfs_rename_obj}, + { MP_OBJ_NEW_QSTR(MP_QSTR_rmdir), (mp_obj_t)&mp_vfs_rmdir_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_stat), (mp_obj_t)&mp_vfs_stat_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_statvfs), (mp_obj_t)&mp_vfs_statvfs_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_unlink), (mp_obj_t)&mp_vfs_remove_obj }, // unlink aliases to remove { MP_OBJ_NEW_QSTR(MP_QSTR_sync), (mp_obj_t)&mod_os_sync_obj }, @@ -398,9 +155,9 @@ STATIC const mp_map_elem_t os_module_globals_table[] = { // these are MicroPython extensions { MP_OBJ_NEW_QSTR(MP_QSTR_dupterm), (mp_obj_t)&mod_os_dupterm_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_mount), (mp_obj_t)&fsuser_mount_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_umount), (mp_obj_t)&fsuser_umount_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_mkfs), (mp_obj_t)&fsuser_mkfs_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_mount), (mp_obj_t)&mp_vfs_mount_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_umount), (mp_obj_t)&mp_vfs_umount_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_VfsFat), (mp_obj_t)&mp_fat_vfs_type }, }; STATIC MP_DEFINE_CONST_DICT(os_module_globals, os_module_globals_table); diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 9c3c29ad69..6e710c9553 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -36,6 +36,7 @@ #define MICROPY_EMIT_INLINE_THUMB (0) #define MICROPY_COMP_MODULE_CONST (0) #define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0) +#define MICROPY_READER_VFS (1) #define MICROPY_ENABLE_GC (1) #define MICROPY_ENABLE_FINALISER (1) #define MICROPY_STACK_CHECK (0) @@ -48,16 +49,24 @@ #define MICROPY_OPT_COMPUTED_GOTO (0) #define MICROPY_OPT_CACHE_MAP_LOOKUP_IN_BYTECODE (0) #define MICROPY_OPT_MPZ_BITWISE (0) -#define MICROPY_READER_FATFS (1) +#define MICROPY_VFS (1) +#define MICROPY_VFS_FAT (1) // fatfs configuration used in ffconf.h #define MICROPY_FATFS_ENABLE_LFN (1) #define MICROPY_FATFS_LFN_CODE_PAGE (437) /* 1=SFN/ANSI 437=LFN/U.S.(OEM) */ #define MICROPY_FATFS_USE_LABEL (1) #define MICROPY_FATFS_RPATH (2) -#define MICROPY_FATFS_VOLUMES (4) #define MICROPY_FATFS_MULTI_PARTITION (1) -#define MICROPY_FSUSERMOUNT (1) + +// TODO these should be generic, not bound to fatfs +#define mp_type_fileio fatfs_type_fileio +#define mp_type_textio fatfs_type_textio + +// use vfs's functions for import stat and builtin open +#define mp_import_stat mp_vfs_import_stat +#define mp_builtin_open mp_vfs_open +#define mp_builtin_open_obj mp_vfs_open_obj #define MICROPY_STREAMS_NON_BLOCK (1) #define MICROPY_MODULE_WEAK_LINKS (1) From 35a7aa133102d1e6ee952fa6952b580a74c83ac7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 8 Feb 2017 00:05:37 +0100 Subject: [PATCH 317/809] nrf5: Adding ubluepy module to builtins if bluetooth stack is selected. Disable NUS profile by default. Adding source for ubluepy module into makefile to be included in build. The source is only linked if MICROPY_PY_UBLUEPY is set. --- nrf5/Makefile | 5 +++++ nrf5/mpconfigport.h | 10 +++++++++- nrf5/sdk/nrf5_sdk_conf.h | 3 ++- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 8b0a37b81b..d6096b9400 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -165,6 +165,11 @@ DRIVERS_SRC_C += $(addprefix modules/,\ uos/moduos.c \ utime/modutime.c \ pyb/modpyb.c \ + ubluepy/modubluepy.c \ + ubluepy/ubluepy_peripheral.c \ + ubluepy/ubluepy_service.c \ + ubluepy/ubluepy_characteristic.c \ + ubluepy/ubluepy_uuid.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 6e710c9553..a9f3f8ee45 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -235,6 +235,7 @@ extern const struct _mp_obj_module_t mp_module_network; extern const struct _mp_obj_module_t mp_module_lcd_mono_fb; extern const struct _mp_obj_module_t mp_module_display; extern const struct _mp_obj_module_t graphics_module; +extern const struct _mp_obj_module_t mp_module_ubluepy; #if MICROPY_PY_USOCKET #define SOCKET_BUILTIN_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_usocket), (mp_obj_t)&mp_module_usocket }, @@ -263,11 +264,17 @@ extern const struct _mp_obj_module_t graphics_module; #endif #if MICROPY_PY_DISPLAY_GRAPHICS -#define GRAPHICS_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_draw), (mp_obj_t)&graphics_module }, +#define GRAPHICS_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_draw), (mp_obj_t)&graphics_module }, #else #define GRAPHICS_MODULE #endif +#if MICROPY_PY_UBLUEPY +#define UBLUEPY_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy), (mp_obj_t)&mp_module_ubluepy }, +#else +#define UBLUEPY_MODULE +#endif + #if BLUETOOTH_SD extern const struct _mp_obj_module_t ble_module; @@ -283,6 +290,7 @@ extern const struct _mp_obj_module_t ble_module; LCD_MONO_FB_MODULE \ DISPLAY_MODULE \ GRAPHICS_MODULE \ + UBLUEPY_MODULE \ #else diff --git a/nrf5/sdk/nrf5_sdk_conf.h b/nrf5/sdk/nrf5_sdk_conf.h index ab256be1f3..3e898b7aed 100644 --- a/nrf5/sdk/nrf5_sdk_conf.h +++ b/nrf5/sdk/nrf5_sdk_conf.h @@ -17,7 +17,8 @@ #elif (BLUETOOTH_SD == 132) #define MICROPY_PY_BLE (1) -#define MICROPY_PY_BLE_NUS (1) +#define MICROPY_PY_BLE_NUS (0) +#define MICROPY_PY_UBLUEPY (1) #else #error "SD not supported" From 323533c3d35cbc361c65f2667de39b74027df2dd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 8 Feb 2017 18:45:49 +0100 Subject: [PATCH 318/809] nrf5/sdk: Adding configuration to enable the ubluepy peripheral class when using softdevice 132 from the SDK. --- nrf5/sdk/nrf5_sdk_conf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/sdk/nrf5_sdk_conf.h b/nrf5/sdk/nrf5_sdk_conf.h index 3e898b7aed..84facef84b 100644 --- a/nrf5/sdk/nrf5_sdk_conf.h +++ b/nrf5/sdk/nrf5_sdk_conf.h @@ -19,6 +19,7 @@ #define MICROPY_PY_BLE (1) #define MICROPY_PY_BLE_NUS (0) #define MICROPY_PY_UBLUEPY (1) +#define MICROPY_PY_UBLUEPY_PERIPHERAL (1) #else #error "SD not supported" From 9057fe550b84a30753f4b5f33548c0e778cf27f3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 8 Feb 2017 18:47:33 +0100 Subject: [PATCH 319/809] nrf5/modules: Extending the implementation of UUID class in ubluepy. --- nrf5/modules/ubluepy/ubluepy_uuid.c | 42 ++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index 02545f0e18..b2f900f1c1 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -25,8 +25,44 @@ */ #include "py/obj.h" +#include "py/runtime.h" -#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL +#if MICROPY_PY_UBLUEPY + +typedef struct _ubluepy_uuid_obj_t { + mp_obj_base_t base; + // UUID value +} ubluepy_uuid_obj_t; + +STATIC void ubluepy_uuid_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + ubluepy_uuid_obj_t * self = (ubluepy_uuid_obj_t *)o; + (void)self; + mp_printf(print, "UUID(value)"); +} + +STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + + enum { ARG_NEW_UUID }; + + static const mp_arg_t allowed_args[] = { + { ARG_NEW_UUID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + ubluepy_uuid_obj_t *s = m_new_obj(ubluepy_uuid_obj_t); + s->base.type = type; + + // Check if UUID is of one of the following types and convert it: + // int from 0 -> 0xFFFFFFFF + // str value + // another UUID + // any other value that can be converted to hex string. + + return MP_OBJ_FROM_PTR(s); +} STATIC const mp_map_elem_t ubluepy_uuid_locals_dict_table[] = { #if 0 @@ -41,11 +77,9 @@ STATIC MP_DEFINE_CONST_DICT(ubluepy_uuid_locals_dict, ubluepy_uuid_locals_dict_t const mp_obj_type_t ubluepy_uuid_type = { { &mp_type_type }, .name = MP_QSTR_UUID, -#if 0 .print = ubluepy_uuid_print, .make_new = ubluepy_uuid_make_new, .locals_dict = (mp_obj_t)&ubluepy_uuid_locals_dict -#endif }; -#endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL +#endif // MICROPY_PY_UBLUEPY From 0264f68698cda9108ad61b2ba7c638b2fd0ac250 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 8 Feb 2017 18:48:35 +0100 Subject: [PATCH 320/809] nrf5/modules: Extending the implementation of Peripheral class in ubluepy. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 79 +++++++++++++++++------ 1 file changed, 61 insertions(+), 18 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 7e9f43a6ba..d46982413c 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -25,10 +25,10 @@ */ #include "py/obj.h" +#include "py/runtime.h" - -#if MICROPY_PY_UBLUEPY_PERIPHERAL +#if MICROPY_PY_UBLUEPY typedef struct _ubluepy_peripheral_obj_t { mp_obj_base_t base; @@ -36,17 +36,17 @@ typedef struct _ubluepy_peripheral_obj_t { } ubluepy_peripheral_obj_t; STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - ubluepy_peripheral_obj_t * self = o; + ubluepy_peripheral_obj_t * self = (ubluepy_peripheral_obj_t *)o; + (void)self; mp_printf(print, "Peripheral"); } -// for make_new -enum { - ARG_NEW_DEVICE_ADDR, - ARG_NEW_ADDR_TYPE -}; - STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + enum { + ARG_NEW_DEVICE_ADDR, + ARG_NEW_ADDR_TYPE + }; + static const mp_arg_t allowed_args[] = { { ARG_NEW_DEVICE_ADDR, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { ARG_NEW_ADDR_TYPE, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, @@ -63,10 +63,46 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ } -STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { -#if 0 +/// \method advertise() +/// Start advertising. +/// +STATIC mp_obj_t peripheral_advertise(mp_obj_t self_in) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); -// #if UBLUEPY_CENTRAL + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_advertise_obj, peripheral_advertise); + +/// \method disconnect() +/// disconnect connection. +/// +STATIC mp_obj_t peripheral_disconnect(mp_obj_t self_in) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_disconnect_obj, peripheral_disconnect); + +/// \method addService(Service) +/// Add service to the Peripheral. +/// +STATIC mp_obj_t peripheral_add_service(mp_obj_t self_in, mp_obj_t uuid) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_add_service_obj, peripheral_add_service); + + + +STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { +#if MICROPY_PY_UBLUEPY_CENTRAL { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, @@ -77,17 +113,24 @@ STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_waitForNotifications), (mp_obj_t)(&ubluepy_peripheral_wait_for_notif_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, -// #if UBLUEPY_PERIPHERAL +#endif +#if MICROPY_PY_UBLUEPY_PERIPHERAL { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setService), (mp_obj_t)(&ubluepy_peripheral_set_service_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setCharacteristic), (mp_obj_t)(&ubluepy_peripheral_set_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setDescriptor), (mp_obj_t)(&ubluepy_peripheral_set_desc_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_addService), (mp_obj_t)(&ubluepy_peripheral_add_service_obj) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_peripheral_add_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_addDescriptor), (mp_obj_t)(&ubluepy_peripheral_add_desc_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, -// #if UBLUEPY_BROADCASTER +#endif +#endif +#if MICROPY_PY_UBLUEPY_BROADCASTER { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, #endif +#if MICROPY_PY_UBLUEPY_OBSERVER + // Nothing yet. +#endif }; STATIC MP_DEFINE_CONST_DICT(ubluepy_peripheral_locals_dict, ubluepy_peripheral_locals_dict_table); @@ -100,4 +143,4 @@ const mp_obj_type_t ubluepy_peripheral_type = { .locals_dict = (mp_obj_t)&ubluepy_peripheral_locals_dict }; -#endif // MICROPY_PY_UBLUEPY_PERIPHERAL +#endif // MICROPY_PY_UBLUEPY From ddc31d4084bb039ecbeb5e9ceeefd5eecf235372 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 8 Feb 2017 18:49:29 +0100 Subject: [PATCH 321/809] nrf5/modules: Adding Peripheral, Service and UUID class to the ubluepy module globals table. --- nrf5/modules/ubluepy/modubluepy.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.c b/nrf5/modules/ubluepy/modubluepy.c index a49eeddcf4..488c4b69c4 100644 --- a/nrf5/modules/ubluepy/modubluepy.c +++ b/nrf5/modules/ubluepy/modubluepy.c @@ -28,37 +28,35 @@ #if MICROPY_PY_UBLUEPY +extern const mp_obj_type_t ubluepy_peripheral_type; +extern const mp_obj_type_t ubluepy_service_type; +extern const mp_obj_type_t ubluepy_uuid_type; + STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy) }, -#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy) }, #if MICROPY_PY_UBLUEPY_PERIPHERAL - { MP_OBJ_NEW_QSTR(MP_QSTR_Peripheral), (mp_obj_t)&ubluepy_peripheral_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Peripheral), (mp_obj_t)&ubluepy_peripheral_type }, #endif #if MICROPY_PY_UBLUEPY_CENTRAL - { MP_OBJ_NEW_QSTR(MP_QSTR_Central), (mp_obj_t)&ubluepy_central_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Central), (mp_obj_t)&ubluepy_central_type }, #endif #if MICROPY_PY_UBLUEPY_SCANNER - { MP_OBJ_NEW_QSTR(MP_QSTR_Scanner), (mp_obj_t)&ubluepy_scanner_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Scanner), (mp_obj_t)&ubluepy_scanner_type }, #endif #if MICROPY_PY_UBLUEPY_CENTRAL - { MP_OBJ_NEW_QSTR(MP_QSTR_ScanEntry), (mp_obj_t)&ubluepy_scan_entry_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ScanEntry), (mp_obj_t)&ubluepy_scan_entry_type }, #endif #if MICROPY_PY_UBLUEPY_DEFAULT_DELEGATE { MP_OBJ_NEW_QSTR(MP_QSTR_DefaultDelegate), (mp_obj_t)&ubluepy_default_delegate_type }, #endif -#if MICROPY_PY_UBLUEPY_UUID - { MP_OBJ_NEW_QSTR(MP_QSTR_UUID), (mp_obj_t)&ubluepy_uuid_type }, -#endif -#if MICROPY_PY_UBLUEPY_SERVICE - { MP_OBJ_NEW_QSTR(MP_QSTR_Service), (mp_obj_t)&ubluepy_service_type }, -#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_UUID), (mp_obj_t)&ubluepy_uuid_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Service), (mp_obj_t)&ubluepy_service_type }, #if MICROPY_PY_UBLUEPY_CHARACTERISTIC - { MP_OBJ_NEW_QSTR(MP_QSTR_Characteristic), (mp_obj_t)&ubluepy_characteristic_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Characteristic), (mp_obj_t)&ubluepy_characteristic_type }, #endif #if MICROPY_PY_UBLUEPY_DESCRIPTOR - { MP_OBJ_NEW_QSTR(MP_QSTR_Descriptor), (mp_obj_t)&ubluepy_descriptor_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Descriptor), (mp_obj_t)&ubluepy_descriptor_type }, #endif -#endif // 0 }; From 8a551e135486be91784e9a4cc38e6580a57821aa Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 9 Feb 2017 23:05:12 +0100 Subject: [PATCH 322/809] nrf5/modules: Updating ubluepy UUID class with constructor that can construct an object based on hex value of 16-bit or string of 16-bit prefixed with '0x'. --- nrf5/modules/ubluepy/ubluepy_uuid.c | 55 ++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index b2f900f1c1..4ba23d2ea0 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -26,20 +26,35 @@ #include "py/obj.h" #include "py/runtime.h" +#include "py/objstr.h" +#include "py/misc.h" #if MICROPY_PY_UBLUEPY +// farward declare type +const mp_obj_type_t ubluepy_uuid_type; + +typedef enum { + UBLUEPY_UUID_16_BIT, + UBLUEPY_UUID_128_BIT +} ubluepy_uuid_type_t; + typedef struct _ubluepy_uuid_obj_t { - mp_obj_base_t base; - // UUID value + mp_obj_base_t base; + ubluepy_uuid_type_t type; + uint8_t value[16]; } ubluepy_uuid_obj_t; STATIC void ubluepy_uuid_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_uuid_obj_t * self = (ubluepy_uuid_obj_t *)o; - (void)self; - mp_printf(print, "UUID(value)"); + if (self->type == UBLUEPY_UUID_16_BIT) { + mp_printf(print, "UUID(" HEX2_FMT HEX2_FMT ")", self->value[1], self->value[0]); + } else { + + } } +#include STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { enum { ARG_NEW_UUID }; @@ -55,6 +70,38 @@ STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, ubluepy_uuid_obj_t *s = m_new_obj(ubluepy_uuid_obj_t); s->base.type = type; + mp_obj_t uuid_obj = args[ARG_NEW_UUID].u_obj; + + if (uuid_obj == MP_OBJ_NULL) { + return MP_OBJ_FROM_PTR(s); + } + + if (MP_OBJ_IS_INT(uuid_obj)) { + s->type = UBLUEPY_UUID_16_BIT; + s->value[1] = (((uint16_t)mp_obj_get_int(uuid_obj)) >> 8) & 0xFF; + s->value[0] = ((uint8_t)mp_obj_get_int(uuid_obj)) & 0xFF; + } else if (MP_OBJ_IS_STR(uuid_obj)) { + GET_STR_DATA_LEN(uuid_obj, str_data, str_len); + if (str_len == 6) { // Assume hex digit prefixed with 0x + s->value[0] = unichar_xdigit_value(str_data[5]); + s->value[0] += unichar_xdigit_value(str_data[4]) << 4; + s->value[1] = unichar_xdigit_value(str_data[3]); + s->value[1] += unichar_xdigit_value(str_data[2]) << 4; + } else if (str_len == 36) { + printf("string length 36\n"); + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Invalid UUID string length")); + } + } else if (MP_OBJ_IS_TYPE(uuid_obj, &ubluepy_uuid_type)) { + printf("copy of UUID object\n"); + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Invalid UUID parameter")); + } + + // "6e400002-b5a3-f393-e0a9-e50e24dcca9e" + // Check if UUID is of one of the following types and convert it: // int from 0 -> 0xFFFFFFFF // str value From b93644221e61209550af7d50b8065ed4465c24b8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 9 Feb 2017 23:56:32 +0100 Subject: [PATCH 323/809] nrf5/sdk: Adding new function to the softdevice handler driver to add vendor specific uuids and return an index to the entry back by reference. --- nrf5/sdk/softdevice.c | 18 ++++++++++++++++++ nrf5/sdk/softdevice.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index e59ddd66d1..439a56a16d 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -26,12 +26,19 @@ #include #include + +#include "py/runtime.h" #include "softdevice.h" #include "mpconfigport.h" #include "nrf_sdm.h" #include "ble_gap.h" #include "ble.h" // sd_ble_uuid_encode +#define SD_TEST_OR_ENABLE() \ +if (sd_enabled() == 0) { \ + (void)sd_enable(); \ +} + #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -199,3 +206,14 @@ void sd_advertise(void) { printf("Advertisment start status: " UINT_FMT "\n", (uint16_t)err_code); } + +bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx) { + SD_TEST_OR_ENABLE(); + + if (sd_ble_uuid_vs_add((ble_uuid128_t const *)p_uuid, idx) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not add Vendor Specific 128-bit UUID.")); + } + + return true; +} diff --git a/nrf5/sdk/softdevice.h b/nrf5/sdk/softdevice.h index 78cb60a127..341f93072d 100644 --- a/nrf5/sdk/softdevice.h +++ b/nrf5/sdk/softdevice.h @@ -25,6 +25,7 @@ */ #include +#include uint32_t sd_enable(void); @@ -36,3 +37,4 @@ void sd_address_get(void); void sd_advertise(void); +bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx); From f549c8df430a23842a6249fbb2fda77e96cb4f01 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 10 Feb 2017 00:02:35 +0100 Subject: [PATCH 324/809] nrf5/modules: Updating ubluepy UUID class constructor with some naive parsing of 128-bit UUIDs, and pass this to the softdevice driver for registration. --- nrf5/modules/ubluepy/ubluepy_uuid.c | 62 ++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index 4ba23d2ea0..f4cc332bd9 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -29,6 +29,8 @@ #include "py/objstr.h" #include "py/misc.h" +#include "softdevice.h" + #if MICROPY_PY_UBLUEPY // farward declare type @@ -42,15 +44,18 @@ typedef enum { typedef struct _ubluepy_uuid_obj_t { mp_obj_base_t base; ubluepy_uuid_type_t type; - uint8_t value[16]; + uint8_t value[2]; + uint8_t uuid_vs_idx; } ubluepy_uuid_obj_t; STATIC void ubluepy_uuid_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_uuid_obj_t * self = (ubluepy_uuid_obj_t *)o; if (self->type == UBLUEPY_UUID_16_BIT) { - mp_printf(print, "UUID(" HEX2_FMT HEX2_FMT ")", self->value[1], self->value[0]); + mp_printf(print, "UUID(uuid: 0x" HEX2_FMT HEX2_FMT ")", + self->value[1], self->value[0]); } else { - + mp_printf(print, "UUID(uuid: 0x" HEX2_FMT HEX2_FMT ", VS idx: " HEX2_FMT ")", + self->value[1], self->value[0], self->uuid_vs_idx); } } @@ -83,12 +88,55 @@ STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, } else if (MP_OBJ_IS_STR(uuid_obj)) { GET_STR_DATA_LEN(uuid_obj, str_data, str_len); if (str_len == 6) { // Assume hex digit prefixed with 0x + s->type = UBLUEPY_UUID_16_BIT; s->value[0] = unichar_xdigit_value(str_data[5]); s->value[0] += unichar_xdigit_value(str_data[4]) << 4; s->value[1] = unichar_xdigit_value(str_data[3]); s->value[1] += unichar_xdigit_value(str_data[2]) << 4; } else if (str_len == 36) { + s->type = UBLUEPY_UUID_128_BIT; + uint8_t buffer[16]; + buffer[0] = unichar_xdigit_value(str_data[35]); + buffer[0] += unichar_xdigit_value(str_data[34]) << 4; + buffer[1] = unichar_xdigit_value(str_data[33]); + buffer[1] += unichar_xdigit_value(str_data[32]) << 4; + buffer[2] = unichar_xdigit_value(str_data[31]); + buffer[2] += unichar_xdigit_value(str_data[30]) << 4; + buffer[3] = unichar_xdigit_value(str_data[29]); + buffer[3] += unichar_xdigit_value(str_data[28]) << 4; + buffer[4] = unichar_xdigit_value(str_data[27]); + buffer[4] += unichar_xdigit_value(str_data[26]) << 4; + buffer[5] = unichar_xdigit_value(str_data[25]); + buffer[5] += unichar_xdigit_value(str_data[24]) << 4; + // 23 '-' + buffer[6] = unichar_xdigit_value(str_data[22]); + buffer[6] += unichar_xdigit_value(str_data[21]) << 4; + buffer[7] = unichar_xdigit_value(str_data[20]); + buffer[7] += unichar_xdigit_value(str_data[19]) << 4; + // 18 '-' + buffer[8] = unichar_xdigit_value(str_data[17]); + buffer[8] += unichar_xdigit_value(str_data[16]) << 4; + buffer[9] = unichar_xdigit_value(str_data[15]); + buffer[9] += unichar_xdigit_value(str_data[14]) << 4; + // 13 '-' + buffer[10] = unichar_xdigit_value(str_data[12]); + buffer[10] += unichar_xdigit_value(str_data[11]) << 4; + buffer[11] = unichar_xdigit_value(str_data[10]); + buffer[11] += unichar_xdigit_value(str_data[9]) << 4; + // 8 '-' + // 16-bit field + s->value[0] = unichar_xdigit_value(str_data[7]); + s->value[0] += unichar_xdigit_value(str_data[6]) << 4; + s->value[1] = unichar_xdigit_value(str_data[5]); + s->value[1] += unichar_xdigit_value(str_data[4]) << 4; + + buffer[14] = unichar_xdigit_value(str_data[3]); + buffer[14] += unichar_xdigit_value(str_data[2]) << 4; + buffer[15] = unichar_xdigit_value(str_data[1]); + buffer[15] += unichar_xdigit_value(str_data[0]) << 4; + printf("string length 36\n"); + sd_uuid_add_vs(s->value, &s->uuid_vs_idx); } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Invalid UUID string length")); @@ -100,14 +148,6 @@ STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, "Invalid UUID parameter")); } - // "6e400002-b5a3-f393-e0a9-e50e24dcca9e" - - // Check if UUID is of one of the following types and convert it: - // int from 0 -> 0xFFFFFFFF - // str value - // another UUID - // any other value that can be converted to hex string. - return MP_OBJ_FROM_PTR(s); } From 322302676462e2504b0fffa8033269ae80a8a4d4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 10 Feb 2017 21:03:30 +0100 Subject: [PATCH 325/809] nrf5: Adding ubluepy to include path. --- nrf5/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index d6096b9400..c85b3685db 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -63,6 +63,7 @@ INC += -I./hal/$(MCU_VARIANT) INC += -I./modules/display INC += -I./modules/machine INC += -I./modules/network +INC += -I./modules/ubluepy INC += -I../lib/mp-readline NRF_DEFINES += -D$(MCU_VARIANT_UPPER) From fad456d18fe9e41fc61560d832a54f642b1b9ecc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 10 Feb 2017 21:09:03 +0100 Subject: [PATCH 326/809] nrf5/modules: Updating ubluepy with more implementation in UUID and Service. Adding function in bluetooth le driver which adds services to the bluetooth stack. Making service take UUID object and Service type (primary/secondary) as constructor parameter in Service class. --- nrf5/modules/ubluepy/modubluepy.h | 59 ++++++++++++++++++++++++++ nrf5/modules/ubluepy/ubluepy_service.c | 58 ++++++++++++++++++++++++- nrf5/modules/ubluepy/ubluepy_uuid.c | 24 +++-------- nrf5/sdk/softdevice.c | 18 ++++++++ nrf5/sdk/softdevice.h | 9 ++++ 5 files changed, 148 insertions(+), 20 deletions(-) create mode 100644 nrf5/modules/ubluepy/modubluepy.h diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h new file mode 100644 index 0000000000..35bf58d639 --- /dev/null +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -0,0 +1,59 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef UBLUEPY_H__ +#define UBLUEPY_H__ + +#include "py/obj.h" + +extern const mp_obj_type_t ubluepy_uuid_type; +extern const mp_obj_type_t ubluepy_service_type; + +typedef enum { + UBLUEPY_UUID_16_BIT, + UBLUEPY_UUID_128_BIT +} ubluepy_uuid_type_t; + +typedef enum { + UBLUEPY_SERVICE_PRIMARY = 1, + UBLUEPY_SERVICE_SECONDARY = 2 +} ubluepy_service_type_t; + +typedef struct _ubluepy_uuid_obj_t { + mp_obj_base_t base; + ubluepy_uuid_type_t type; + uint8_t value[2]; + uint8_t uuid_vs_idx; +} ubluepy_uuid_obj_t; + +typedef struct _ubluepy_service_obj_t { + mp_obj_base_t base; + uint16_t handle; + uint8_t type; + ubluepy_uuid_obj_t * p_uuid; +} ubluepy_service_obj_t; + +#endif // UBLUEPY_H__ diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 3bb11716a2..43335eb6df 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -25,9 +25,63 @@ */ #include "py/obj.h" +#include "modubluepy.h" +#include "py/runtime.h" + +#include "softdevice.h" #if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL +STATIC void ubluepy_service_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + ubluepy_service_obj_t * self = (ubluepy_service_obj_t *)o; + + mp_printf(print, "Service(handle: 0x" HEX2_FMT ")", self->handle); +} + +STATIC mp_obj_t ubluepy_service_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + + enum { ARG_NEW_UUID, ARG_NEW_TYPE }; + + static const mp_arg_t allowed_args[] = { + { ARG_NEW_UUID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_TYPE, MP_ARG_INT, {.u_int = UBLUEPY_SERVICE_PRIMARY} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + ubluepy_service_obj_t *s = m_new_obj(ubluepy_service_obj_t); + s->base.type = type; + + mp_obj_t uuid_obj = args[ARG_NEW_UUID].u_obj; + + if (uuid_obj == MP_OBJ_NULL) { + return MP_OBJ_FROM_PTR(s); + } + + if (MP_OBJ_IS_TYPE(uuid_obj, &ubluepy_uuid_type)) { + s->p_uuid = MP_OBJ_TO_PTR(uuid_obj); + + uint8_t type = args[ARG_NEW_TYPE].u_int; + if (type > 0 && type <= UBLUEPY_SERVICE_PRIMARY) { + s->type = type; + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Invalid Service type")); + } + + (void)sd_service_add(s); + + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Invalid UUID parameter")); + } + + return MP_OBJ_FROM_PTR(s); +} + + STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { #if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristic), (mp_obj_t)(&ubluepy_service_get_char_obj) }, @@ -36,6 +90,8 @@ STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_service_get_peripheral_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_service_get_uuid_obj) }, #endif + { MP_OBJ_NEW_QSTR(MP_QSTR_PRIMARY), MP_OBJ_NEW_SMALL_INT(UBLUEPY_SERVICE_PRIMARY) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SECONDARY), MP_OBJ_NEW_SMALL_INT(UBLUEPY_SERVICE_SECONDARY) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_service_locals_dict, ubluepy_service_locals_dict_table); @@ -43,11 +99,9 @@ STATIC MP_DEFINE_CONST_DICT(ubluepy_service_locals_dict, ubluepy_service_locals_ const mp_obj_type_t ubluepy_service_type = { { &mp_type_type }, .name = MP_QSTR_Service, -#if 0 .print = ubluepy_service_print, .make_new = ubluepy_service_make_new, .locals_dict = (mp_obj_t)&ubluepy_service_locals_dict -#endif }; #endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index f4cc332bd9..667c6b29e1 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -29,25 +29,11 @@ #include "py/objstr.h" #include "py/misc.h" +#include "modubluepy.h" #include "softdevice.h" #if MICROPY_PY_UBLUEPY -// farward declare type -const mp_obj_type_t ubluepy_uuid_type; - -typedef enum { - UBLUEPY_UUID_16_BIT, - UBLUEPY_UUID_128_BIT -} ubluepy_uuid_type_t; - -typedef struct _ubluepy_uuid_obj_t { - mp_obj_base_t base; - ubluepy_uuid_type_t type; - uint8_t value[2]; - uint8_t uuid_vs_idx; -} ubluepy_uuid_obj_t; - STATIC void ubluepy_uuid_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_uuid_obj_t * self = (ubluepy_uuid_obj_t *)o; if (self->type == UBLUEPY_UUID_16_BIT) { @@ -59,7 +45,6 @@ STATIC void ubluepy_uuid_print(const mp_print_t *print, mp_obj_t o, mp_print_kin } } -#include STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { enum { ARG_NEW_UUID }; @@ -135,14 +120,17 @@ STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, buffer[15] = unichar_xdigit_value(str_data[1]); buffer[15] += unichar_xdigit_value(str_data[0]) << 4; - printf("string length 36\n"); sd_uuid_add_vs(s->value, &s->uuid_vs_idx); } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Invalid UUID string length")); } } else if (MP_OBJ_IS_TYPE(uuid_obj, &ubluepy_uuid_type)) { - printf("copy of UUID object\n"); + // deep copy instance + ubluepy_uuid_obj_t * p_old = MP_OBJ_TO_PTR(uuid_obj); + s->type = p_old->type; + s->value[0] = p_old->value[0]; + s->value[1] = p_old->value[1]; } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Invalid UUID parameter")); diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 439a56a16d..34e4504e73 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -217,3 +217,21 @@ bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx) { return true; } + +bool sd_service_add(ubluepy_service_obj_t * p_service_obj) { + SD_TEST_OR_ENABLE(); + + ble_uuid_t uuid; + uuid.type = p_service_obj->p_uuid->type; + uuid.uuid = (uint16_t)(*(uint16_t *)&p_service_obj->p_uuid->value[0]); + + if (sd_ble_gatts_service_add(p_service_obj->type, + &uuid, + &p_service_obj->handle) != 0) + { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not add Service.")); + } + + return true; +} diff --git a/nrf5/sdk/softdevice.h b/nrf5/sdk/softdevice.h index 341f93072d..5cc68d0320 100644 --- a/nrf5/sdk/softdevice.h +++ b/nrf5/sdk/softdevice.h @@ -24,9 +24,14 @@ * THE SOFTWARE. */ +#ifndef BLUETOOTH_LE_DRIVER_H__ +#define BLUETOOTH_LE_DRIVER_H__ + #include #include +#include "modubluepy.h" + uint32_t sd_enable(void); void sd_disable(void); @@ -38,3 +43,7 @@ void sd_address_get(void); void sd_advertise(void); bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx); + +bool sd_service_add(ubluepy_service_obj_t * p_service_obj); + +#endif // BLUETOOTH_LE_DRIVER_H__ From 5f19113c94331162ea1d7101d29e73ef393129f9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 14:19:08 +0100 Subject: [PATCH 327/809] nrf5/modules: Adding ubluepy charactaristic type struct. --- nrf5/modules/ubluepy/modubluepy.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 35bf58d639..f905ac458b 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -56,4 +56,11 @@ typedef struct _ubluepy_service_obj_t { ubluepy_uuid_obj_t * p_uuid; } ubluepy_service_obj_t; +typedef struct _ubluepy_characteristic_obj_t { + mp_obj_base_t base; + uint16_t handle; + ubluepy_uuid_obj_t * p_uuid; +} ubluepy_characteristic_obj_t; + + #endif // UBLUEPY_H__ From 7f26704e27b0678cd1ae12336d8f41a83be8fff2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 14:20:01 +0100 Subject: [PATCH 328/809] nrf5/modules: Re-arranging includes in ubluepy_service.c --- nrf5/modules/ubluepy/ubluepy_service.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 43335eb6df..d9d119281e 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -25,9 +25,8 @@ */ #include "py/obj.h" -#include "modubluepy.h" #include "py/runtime.h" - +#include "modubluepy.h" #include "softdevice.h" #if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL From c127938103d11ac390b6a02105b53d47825e717b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 14:21:05 +0100 Subject: [PATCH 329/809] nrf5/modules: Updating ubluepy characteristic implementation. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 42 ++++++++++++++++++- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index 0deb3f35df..403f8e09be 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -25,9 +25,49 @@ */ #include "py/obj.h" +#include "py/runtime.h" +#include "modubluepy.h" #if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL +STATIC void ubluepy_characteristic_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + ubluepy_characteristic_obj_t * self = (ubluepy_characteristic_obj_t *)o; + + mp_printf(print, "Characteristic(handle: 0x" HEX2_FMT ")", self->handle); +} + +STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + + enum { ARG_NEW_UUID }; + + static const mp_arg_t allowed_args[] = { + { ARG_NEW_UUID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + ubluepy_characteristic_obj_t *s = m_new_obj(ubluepy_characteristic_obj_t); + s->base.type = type; + + mp_obj_t uuid_obj = args[ARG_NEW_UUID].u_obj; + + if (uuid_obj == MP_OBJ_NULL) { + return MP_OBJ_FROM_PTR(s); + } + + if (MP_OBJ_IS_TYPE(uuid_obj, &ubluepy_uuid_type)) { + s->p_uuid = MP_OBJ_TO_PTR(uuid_obj); + // (void)sd_characterstic_add(s); + } else { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Invalid UUID parameter")); + } + + return MP_OBJ_FROM_PTR(s); +} + STATIC const mp_map_elem_t ubluepy_characteristic_locals_dict_table[] = { #if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)(&ubluepy_characteristic_read_obj) }, @@ -48,11 +88,9 @@ STATIC MP_DEFINE_CONST_DICT(ubluepy_characteristic_locals_dict, ubluepy_characte const mp_obj_type_t ubluepy_characteristic_type = { { &mp_type_type }, .name = MP_QSTR_Characteristic, -#if 0 .print = ubluepy_characteristic_print, .make_new = ubluepy_characteristic_make_new, .locals_dict = (mp_obj_t)&ubluepy_characteristic_locals_dict -#endif }; #endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL From c58063359846a893295cbf9810e283ebbb9472f7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 14:35:00 +0100 Subject: [PATCH 330/809] nrf5/modules: Adding characteristic class to ubluepy globals table. --- nrf5/modules/ubluepy/modubluepy.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.c b/nrf5/modules/ubluepy/modubluepy.c index 488c4b69c4..94325b1a8a 100644 --- a/nrf5/modules/ubluepy/modubluepy.c +++ b/nrf5/modules/ubluepy/modubluepy.c @@ -31,6 +31,7 @@ extern const mp_obj_type_t ubluepy_peripheral_type; extern const mp_obj_type_t ubluepy_service_type; extern const mp_obj_type_t ubluepy_uuid_type; +extern const mp_obj_type_t ubluepy_characteristic_type; STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy) }, @@ -51,9 +52,7 @@ STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { #endif { MP_OBJ_NEW_QSTR(MP_QSTR_UUID), (mp_obj_t)&ubluepy_uuid_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_Service), (mp_obj_t)&ubluepy_service_type }, -#if MICROPY_PY_UBLUEPY_CHARACTERISTIC { MP_OBJ_NEW_QSTR(MP_QSTR_Characteristic), (mp_obj_t)&ubluepy_characteristic_type }, -#endif #if MICROPY_PY_UBLUEPY_DESCRIPTOR { MP_OBJ_NEW_QSTR(MP_QSTR_Descriptor), (mp_obj_t)&ubluepy_descriptor_type }, #endif From a43f5cdd4e0f232f822f4007a56f41fc40030ced Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 16:00:43 +0100 Subject: [PATCH 331/809] nrf5/modules: Adding more members to ublue characteristic object structure. --- nrf5/modules/ubluepy/modubluepy.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index f905ac458b..900daef54e 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -60,6 +60,10 @@ typedef struct _ubluepy_characteristic_obj_t { mp_obj_base_t base; uint16_t handle; ubluepy_uuid_obj_t * p_uuid; + uint16_t service_handle; + uint16_t user_desc_handle; + uint16_t cccd_handle; + uint16_t sccd_handle; } ubluepy_characteristic_obj_t; From c9aa561aadbdd8acd44c892a27383eee9663e50e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 16:01:50 +0100 Subject: [PATCH 332/809] nrf5/modules: Adding function in bluetooth le driver to add characteristic to the bluetooth le stack. --- nrf5/sdk/softdevice.c | 64 +++++++++++++++++++++++++++++++++++++++++++ nrf5/sdk/softdevice.h | 2 ++ 2 files changed, 66 insertions(+) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 34e4504e73..385d9e8fd9 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -235,3 +235,67 @@ bool sd_service_add(ubluepy_service_obj_t * p_service_obj) { return true; } + +bool sd_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj) { + ble_gatts_char_md_t char_md; + ble_gatts_attr_md_t cccd_md; + ble_gatts_attr_t attr_char_value; + ble_uuid_t uuid; + ble_gatts_attr_md_t attr_md; + + memset(&cccd_md, 0, sizeof(cccd_md)); + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm); + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.write_perm); + + cccd_md.vloc = BLE_GATTS_VLOC_STACK; + + memset(&char_md, 0, sizeof(char_md)); + + char_md.char_props.notify = 1; + char_md.p_char_user_desc = NULL; + char_md.p_char_pf = NULL; + char_md.p_user_desc_md = NULL; + char_md.p_cccd_md = &cccd_md; + char_md.p_sccd_md = NULL; + + + uuid.type = p_char_obj->p_uuid->type; + uuid.uuid = (uint16_t)(*(uint16_t *)&p_char_obj->p_uuid->value[0]); + + memset(&attr_md, 0, sizeof(attr_md)); + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.read_perm); + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm); + + attr_md.vloc = BLE_GATTS_VLOC_STACK; + attr_md.rd_auth = 0; + attr_md.wr_auth = 0; + attr_md.vlen = 1; + + memset(&attr_char_value, 0, sizeof(attr_char_value)); + + attr_char_value.p_uuid = &uuid; + attr_char_value.p_attr_md = &attr_md; + attr_char_value.init_len = sizeof(uint8_t); + attr_char_value.init_offs = 0; + attr_char_value.max_len = (GATT_MTU_SIZE_DEFAULT - 3); + + ble_gatts_char_handles_t handles; + + if (sd_ble_gatts_characteristic_add(p_char_obj->service_handle, + &char_md, + &attr_char_value, + &handles) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not add Characteristic.")); + } + + // apply handles to object instance + p_char_obj->handle = handles.value_handle; + p_char_obj->user_desc_handle = handles.user_desc_handle; + p_char_obj->cccd_handle = handles.cccd_handle; + p_char_obj->sccd_handle = handles.sccd_handle; + + return true; +} diff --git a/nrf5/sdk/softdevice.h b/nrf5/sdk/softdevice.h index 5cc68d0320..a1ccce7d3f 100644 --- a/nrf5/sdk/softdevice.h +++ b/nrf5/sdk/softdevice.h @@ -46,4 +46,6 @@ bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx); bool sd_service_add(ubluepy_service_obj_t * p_service_obj); +bool sd_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj); + #endif // BLUETOOTH_LE_DRIVER_H__ From d6b12b63d0c6afd5ba32a4049494857887ceee80 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 16:04:48 +0100 Subject: [PATCH 333/809] nrf5/modules: Adding function function to add characteristics to the ubluepy service. Enable function in service's local dict table. --- nrf5/modules/ubluepy/ubluepy_service.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index d9d119281e..536e4943f9 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -80,12 +80,28 @@ STATIC mp_obj_t ubluepy_service_make_new(const mp_obj_type_t *type, size_t n_arg return MP_OBJ_FROM_PTR(s); } +/// \method addCharacteristic(Service) +/// Add Characteristic to the Service. +/// +STATIC mp_obj_t service_add_characteristic(mp_obj_t self_in, mp_obj_t characteristic) { + ubluepy_service_obj_t * self = MP_OBJ_TO_PTR(self_in); + ubluepy_characteristic_obj_t * p_char = MP_OBJ_TO_PTR(characteristic); + + p_char->service_handle = self->handle; + + bool retval = sd_characteristic_add(p_char); + + return mp_obj_new_bool(retval); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_service_add_char_obj, service_add_characteristic); STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { #if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristic), (mp_obj_t)(&ubluepy_service_get_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setCharacteristic), (mp_obj_t)(&ubluepy_service_set_char_obj) }, - // Properties +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_service_add_char_obj) }, +#if 0 + // Properties { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_service_get_peripheral_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_service_get_uuid_obj) }, #endif From 8cc0eb23d98544f33cbf29cfbbf126cfa8e94668 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 17:37:48 +0100 Subject: [PATCH 334/809] nrf5/modules: Adding new structure to ubluepy in order to pass advertisment data information to the bluetooth le stack. --- nrf5/modules/ubluepy/modubluepy.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 900daef54e..df534b37d0 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -66,5 +66,9 @@ typedef struct _ubluepy_characteristic_obj_t { uint16_t sccd_handle; } ubluepy_characteristic_obj_t; +typedef struct _ubluepy_advertise_data_t { + uint8_t * p_device_name; + uint8_t device_name_len; +} ubluepy_advertise_data_t; #endif // UBLUEPY_H__ From 1a3ae62fd11d403707b7193b0d137395a5ac11f4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 17:41:16 +0100 Subject: [PATCH 335/809] nrf5/sdk: Updating softdevice driver with function to set advertisment data and start advertisment. Does not apply device name yet. Work in progress. --- nrf5/sdk/softdevice.c | 54 +++++++++++++++++++++++++++++++++++++++++++ nrf5/sdk/softdevice.h | 1 + 2 files changed, 55 insertions(+) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 385d9e8fd9..36a3723704 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -299,3 +299,57 @@ bool sd_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj) { return true; } + +bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { + SD_TEST_OR_ENABLE(); + + uint8_t byte_pos = 0; + + uint8_t adv_data[BLE_GAP_ADV_MAX_SIZE]; + + if (p_adv_params->device_name_len > 0) { + ble_gap_conn_sec_mode_t sec_mode; + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); + + if (sd_ble_gap_device_name_set(&sec_mode, + p_adv_params->p_device_name, + p_adv_params->device_name_len) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not apply device name in the stack.")); + } + + adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + p_adv_params->device_name_len); + byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; + adv_data[byte_pos] = BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME; + // memcpy(&adv_data[byte_pos], p_adv_params->p_device_name, p_adv_params->device_name_len); + // increment position counter to see if it fits, and in case more content should + // follow in this adv packet. + byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; + byte_pos += p_adv_params->device_name_len; + } + + // scan response data not set + if (sd_ble_gap_adv_data_set(adv_data, byte_pos, NULL, 0) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not apply advertisment data.")); + } + printf("Set Adv data size: " UINT_FMT "\n", byte_pos); + + ble_gap_adv_params_t m_adv_params; + + // initialize advertising params + memset(&m_adv_params, 0, sizeof(m_adv_params)); + m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_NONCONN_IND; + m_adv_params.p_peer_addr = NULL; // Undirected advertisement. + m_adv_params.fp = BLE_GAP_ADV_FP_ANY; + m_adv_params.interval = NON_CONNECTABLE_ADV_INTERVAL; + m_adv_params.timeout = APP_CFG_NON_CONN_ADV_TIMEOUT; + + if (sd_ble_gap_adv_start(&m_adv_params) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not start advertisment.")); + } + + return true; +} diff --git a/nrf5/sdk/softdevice.h b/nrf5/sdk/softdevice.h index a1ccce7d3f..ba79d89866 100644 --- a/nrf5/sdk/softdevice.h +++ b/nrf5/sdk/softdevice.h @@ -48,4 +48,5 @@ bool sd_service_add(ubluepy_service_obj_t * p_service_obj); bool sd_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj); +bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params); #endif // BLUETOOTH_LE_DRIVER_H__ From 3a68e40102741835cc759f6f2c8e642a19cf6bf4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 17:43:47 +0100 Subject: [PATCH 336/809] nrf5/modules: Turning ubluepy peripheral advertisment function into a keyword argument function so that it would be possible to set device name, service uuids, or manually constructed data payload. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 45 +++++++++++++++++++---- 1 file changed, 38 insertions(+), 7 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index d46982413c..0a4750e23c 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -26,10 +26,12 @@ #include "py/obj.h" #include "py/runtime.h" - +#include "py/objstr.h" #if MICROPY_PY_UBLUEPY +#include "softdevice.h" + typedef struct _ubluepy_peripheral_obj_t { mp_obj_base_t base; // services @@ -62,18 +64,47 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ return MP_OBJ_FROM_PTR(s); } - -/// \method advertise() +/// \method advertise(device_name, [service=[service1, service2, ...]], [data=bytearray]) /// Start advertising. /// -STATIC mp_obj_t peripheral_advertise(mp_obj_t self_in) { - ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); +STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_device_name, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_services, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_data, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; - (void)self; + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + mp_obj_t device_name_obj = args[0].u_obj; + mp_obj_t service_obj = args[1].u_obj; + mp_obj_t data_obj = args[2].u_obj; + + ubluepy_advertise_data_t adv_data; + + if (device_name_obj != MP_OBJ_NULL && MP_OBJ_IS_STR(device_name_obj)) { + GET_STR_DATA_LEN(device_name_obj, str_data, str_len); + + adv_data.p_device_name = (uint8_t *)str_data; + adv_data.device_name_len = str_len; + } + + if (service_obj != MP_OBJ_NULL) { + + } + + if (data_obj != MP_OBJ_NULL) { + + } + + (void)sd_advertise_data(&adv_data); return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_advertise_obj, peripheral_advertise); +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(ubluepy_peripheral_advertise_obj, 1, peripheral_advertise); /// \method disconnect() /// disconnect connection. From b65553e57f62d8ecd73e5a33e277258f48ca2582 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 18:02:22 +0100 Subject: [PATCH 337/809] nrf5/sdk: Successful device name advertisment. Added flags to advertisment packet and enable device name byte copy into the advertisment data. --- nrf5/sdk/softdevice.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 36a3723704..2eb694e391 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -319,16 +319,27 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { "Can not apply device name in the stack.")); } + printf("Device name applied\n"); + adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + p_adv_params->device_name_len); byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; adv_data[byte_pos] = BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME; - // memcpy(&adv_data[byte_pos], p_adv_params->p_device_name, p_adv_params->device_name_len); + byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; + memcpy(&adv_data[byte_pos], p_adv_params->p_device_name, p_adv_params->device_name_len); // increment position counter to see if it fits, and in case more content should // follow in this adv packet. - byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; byte_pos += p_adv_params->device_name_len; } + // set flags, default to disc mode + adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + BLE_AD_TYPE_FLAGS_DATA_SIZE); + byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; + adv_data[byte_pos] = BLE_GAP_AD_TYPE_FLAGS; + byte_pos += BLE_AD_TYPE_FLAGS_DATA_SIZE; + adv_data[byte_pos] = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE; + byte_pos += 1; + + // scan response data not set if (sd_ble_gap_adv_data_set(adv_data, byte_pos, NULL, 0) != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, From ff9cefa6b29e94b01b32707db41480bf7aa3adeb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 11 Feb 2017 18:09:22 +0100 Subject: [PATCH 338/809] nrf5/modules: Adding a few examples in the modubluepy.h to get easier copy paste when implementing. --- nrf5/modules/ubluepy/modubluepy.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index df534b37d0..959704418b 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -27,6 +27,25 @@ #ifndef UBLUEPY_H__ #define UBLUEPY_H__ +/* Examples: + +Advertisment: + +from ubluepy import Peripheral +p = Peripheral() +p.advertise(device_name="MicroPython") + +DB setup: + +from ubluepy import Service, Characteristic, UUID +u0 = UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e") +s = Service(u0) +u1 = UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e") +c = Characteristic(u1) +s.addCharacteristic(c) + +*/ + #include "py/obj.h" extern const mp_obj_type_t ubluepy_uuid_type; From 9d24742351a7e90ca972a091b0506714c7754d56 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Feb 2017 14:23:13 +0100 Subject: [PATCH 339/809] nrf5/modules: Updating ubluepy peripheral class to use mp_const_none instead of MP_OBJ_NULL for unset values in advertisment method parameter list. Adding extraction of the service list in the advertisment method. The list is not yet handled. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 0a4750e23c..9353cab265 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -69,9 +69,9 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ /// STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { static const mp_arg_t allowed_args[] = { - { MP_QSTR_device_name, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { MP_QSTR_services, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { MP_QSTR_data, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_device_name, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_services, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_data, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, }; // parse args @@ -85,18 +85,21 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, ubluepy_advertise_data_t adv_data; - if (device_name_obj != MP_OBJ_NULL && MP_OBJ_IS_STR(device_name_obj)) { + if (device_name_obj != mp_const_none && MP_OBJ_IS_STR(device_name_obj)) { GET_STR_DATA_LEN(device_name_obj, str_data, str_len); adv_data.p_device_name = (uint8_t *)str_data; adv_data.device_name_len = str_len; } - if (service_obj != MP_OBJ_NULL) { - + if (service_obj != mp_const_none) { + mp_obj_t * services; + mp_uint_t num_services; + mp_obj_get_array(service_obj, &num_services, &services); +// printf("Number of services passed to advertise(): %u\n", num_services); } - if (data_obj != MP_OBJ_NULL) { + if (data_obj != mp_const_none) { } From 90523d6ae019cd0f8a5ac6864917229d32a9b281 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Feb 2017 14:24:15 +0100 Subject: [PATCH 340/809] nrf5/sdk: Adding static boolean for keeping track of whether advertisment is in progress in the bluetooth driver. Now, advertisment can be restarted with new data any time. --- nrf5/sdk/softdevice.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 2eb694e391..eb7ddc4749 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -26,6 +26,7 @@ #include #include +#include #include "py/runtime.h" #include "softdevice.h" @@ -39,6 +40,8 @@ if (sd_enabled() == 0) { \ (void)sd_enable(); \ } +bool m_adv_in_progress = false; + #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -357,10 +360,19 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { m_adv_params.interval = NON_CONNECTABLE_ADV_INTERVAL; m_adv_params.timeout = APP_CFG_NON_CONN_ADV_TIMEOUT; + if (m_adv_in_progress && sd_ble_gap_adv_stop() != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not stop advertisment.")); + } + + m_adv_in_progress = false; + if (sd_ble_gap_adv_start(&m_adv_params) != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not start advertisment.")); } + m_adv_in_progress = true; + return true; } From 2d72fe85183c57415afbfe3ded426adabbb4b0a4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Feb 2017 15:14:41 +0100 Subject: [PATCH 341/809] nrf5/modules: Updating ubluepy module header usage example. Correcting enum for UUID types to start index from 1. Expanding advertisment data structure to also include service list members. --- nrf5/modules/ubluepy/modubluepy.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 959704418b..170fb191b3 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -37,13 +37,14 @@ p.advertise(device_name="MicroPython") DB setup: -from ubluepy import Service, Characteristic, UUID +from ubluepy import Service, Characteristic, UUID, Peripheral u0 = UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e") s = Service(u0) u1 = UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e") c = Characteristic(u1) s.addCharacteristic(c) - +p = Peripheral() +p.advertise(device_name="MicroPython", services=[s]) */ #include "py/obj.h" @@ -52,7 +53,7 @@ extern const mp_obj_type_t ubluepy_uuid_type; extern const mp_obj_type_t ubluepy_service_type; typedef enum { - UBLUEPY_UUID_16_BIT, + UBLUEPY_UUID_16_BIT = 1, UBLUEPY_UUID_128_BIT } ubluepy_uuid_type_t; @@ -86,8 +87,11 @@ typedef struct _ubluepy_characteristic_obj_t { } ubluepy_characteristic_obj_t; typedef struct _ubluepy_advertise_data_t { - uint8_t * p_device_name; - uint8_t device_name_len; + uint8_t * p_device_name; + uint8_t device_name_len; + mp_obj_t * p_services; + uint8_t num_of_services; + } ubluepy_advertise_data_t; #endif // UBLUEPY_H__ From 18aab4a6b90c47c442e4d300a62073f8f4c6c643 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Feb 2017 15:17:30 +0100 Subject: [PATCH 342/809] nrf5/modules: Updating advertisment method in peripheral class to memset advertisment structure. Also applying service list if set to the advertisment structure. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 9353cab265..a85eb20a77 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -24,6 +24,7 @@ * THE SOFTWARE. */ +#include #include "py/obj.h" #include "py/runtime.h" #include "py/objstr.h" @@ -84,6 +85,7 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, mp_obj_t data_obj = args[2].u_obj; ubluepy_advertise_data_t adv_data; + memset(&adv_data, 0, sizeof(ubluepy_advertise_data_t)); if (device_name_obj != mp_const_none && MP_OBJ_IS_STR(device_name_obj)) { GET_STR_DATA_LEN(device_name_obj, str_data, str_len); @@ -93,10 +95,14 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, } if (service_obj != mp_const_none) { - mp_obj_t * services; + mp_obj_t * services = NULL; mp_uint_t num_services; mp_obj_get_array(service_obj, &num_services, &services); -// printf("Number of services passed to advertise(): %u\n", num_services); + + if (num_services > 0) { + adv_data.p_services = services; + adv_data.num_of_services = num_services; + } } if (data_obj != mp_const_none) { From 2d58fc6625e74096bb3c1a916ba371d22fb94945 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Feb 2017 15:20:41 +0100 Subject: [PATCH 343/809] nrf5/sdk: Updating advertisment funciton in bluetooth le driver to iterate through services passed in and calculate individiual uuid sizes. --- nrf5/sdk/softdevice.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index eb7ddc4749..64927ce504 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -342,6 +342,27 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { adv_data[byte_pos] = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE; byte_pos += 1; + if (p_adv_params->num_of_services > 0) { + uint8_t encoded_size = 0; + for (uint8_t i = 0; i < p_adv_params->num_of_services; i++) { + ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i]; + + ble_uuid_t uuid; + uuid.type = p_service->p_uuid->type; + uuid.uuid = (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]); + + // calculate total size of uuids + if (sd_ble_uuid_encode(&uuid, &encoded_size, NULL) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can encode UUID to check length.")); + } + + printf("ADV: uuid size: %u, type: %u, uuid: %u\n", encoded_size, p_service->p_uuid->type, (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0])); + + } + + } + // scan response data not set if (sd_ble_gap_adv_data_set(adv_data, byte_pos, NULL, 0) != 0) { From 0a0ab8344e4b3c8db7d4fdbe7dd71cb2abd4c68d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Feb 2017 23:03:55 +0100 Subject: [PATCH 344/809] nrf5/sdk: Updating advertisment function in bluetooth le driver to add 128-bit complete service UUID provided in service list to the advertisment packet. --- nrf5/sdk/softdevice.c | 79 +++++++++++++++++++++++++++++++++---------- 1 file changed, 61 insertions(+), 18 deletions(-) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 64927ce504..8a6400080f 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -158,8 +158,8 @@ void sd_address_get(void) { // URL // URL suffix, 0x01 = ".com" #define EDDYSTONE_DATA 0x10, 0xEE, 0x00, 'm', 'i', 'c', 'r', 'o', 'p', 'y', 't', 'h', 'o', 'n', 0x01 - -#define BLE_ADV_AD_TYPE_FIELD_SIZE 1 +#define BLE_ADV_LENGTH_FIELD_SIZE 1 +#define BLE_ADV_AD_TYPE_FIELD_SIZE 1 #define BLE_AD_TYPE_FLAGS_DATA_SIZE 1 #define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) @@ -224,18 +224,33 @@ bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx) { bool sd_service_add(ubluepy_service_obj_t * p_service_obj) { SD_TEST_OR_ENABLE(); - ble_uuid_t uuid; - uuid.type = p_service_obj->p_uuid->type; - uuid.uuid = (uint16_t)(*(uint16_t *)&p_service_obj->p_uuid->value[0]); + if (p_service_obj->p_uuid->type > BLE_UUID_TYPE_BLE) { - if (sd_ble_gatts_service_add(p_service_obj->type, - &uuid, - &p_service_obj->handle) != 0) - { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can not add Service.")); + ble_uuid_t uuid; + uuid.type = p_service_obj->p_uuid->uuid_vs_idx; + uuid.uuid = (uint16_t)(*(uint16_t *)&p_service_obj->p_uuid->value[0]); + + if (sd_ble_gatts_service_add(p_service_obj->type, + &uuid, + &p_service_obj->handle) != 0) + { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not add Service.")); + } + } else if (p_service_obj->p_uuid->type == BLE_UUID_TYPE_BLE) { + + ble_uuid_t uuid; + uuid.type = p_service_obj->p_uuid->type; + uuid.uuid = (uint16_t)(*(uint16_t *)&p_service_obj->p_uuid->value[0]); + + if (sd_ble_gatts_service_add(p_service_obj->type, + &uuid, + &p_service_obj->handle) != 0) + { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not add Service.")); + } } - return true; } @@ -325,7 +340,7 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { printf("Device name applied\n"); adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + p_adv_params->device_name_len); - byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; + byte_pos += BLE_ADV_LENGTH_FIELD_SIZE; adv_data[byte_pos] = BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME; byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; memcpy(&adv_data[byte_pos], p_adv_params->p_device_name, p_adv_params->device_name_len); @@ -336,31 +351,59 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { // set flags, default to disc mode adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + BLE_AD_TYPE_FLAGS_DATA_SIZE); - byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; + byte_pos += BLE_ADV_LENGTH_FIELD_SIZE; adv_data[byte_pos] = BLE_GAP_AD_TYPE_FLAGS; byte_pos += BLE_AD_TYPE_FLAGS_DATA_SIZE; adv_data[byte_pos] = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE; byte_pos += 1; if (p_adv_params->num_of_services > 0) { - uint8_t encoded_size = 0; + + uint8_t size_byte_pos = byte_pos; + + // skip length byte for now, apply total length post calculation + byte_pos += BLE_ADV_LENGTH_FIELD_SIZE; + + adv_data[byte_pos] = BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE; + byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; + + uint8_t uuid_total_size = 0; + uint8_t encoded_size = 0; + for (uint8_t i = 0; i < p_adv_params->num_of_services; i++) { ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i]; ble_uuid_t uuid; - uuid.type = p_service->p_uuid->type; + uuid.type = p_service->p_uuid->uuid_vs_idx; uuid.uuid = (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]); // calculate total size of uuids if (sd_ble_uuid_encode(&uuid, &encoded_size, NULL) != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can encode UUID to check length.")); + "Can not encode UUID, to check length.")); } - printf("ADV: uuid size: %u, type: %u, uuid: %u\n", encoded_size, p_service->p_uuid->type, (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0])); + // do encoding into the adv buffer + if (sd_ble_uuid_encode(&uuid, &encoded_size, &adv_data[byte_pos]) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can encode UUID into the advertisment packet.")); + } + printf("encoded uuid for service %u: ", 0); + for (uint8_t j = 0; j < encoded_size; j++) { + printf(HEX2_FMT " ", adv_data[byte_pos + j]); + } + printf("\n"); + + uuid_total_size += encoded_size; // size of entry + byte_pos += encoded_size; // relative to adv data packet + printf("ADV: uuid size: %u, type: %u, uuid: %u, vs_idx: %u\n", + encoded_size, p_service->p_uuid->type, + (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]), + p_service->p_uuid->uuid_vs_idx); } + adv_data[size_byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + uuid_total_size); } From e432ab48423e07b865d867d78861a9a2957e5a3d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Feb 2017 23:04:48 +0100 Subject: [PATCH 345/809] nrf5/modules: Bugfix in ubluepy_uuid_make_new. Used wrong buffer to register vendor specific uuid to the bluetooth stack. --- nrf5/modules/ubluepy/ubluepy_uuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index 667c6b29e1..ddea56160b 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -120,7 +120,7 @@ STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, buffer[15] = unichar_xdigit_value(str_data[1]); buffer[15] += unichar_xdigit_value(str_data[0]) << 4; - sd_uuid_add_vs(s->value, &s->uuid_vs_idx); + sd_uuid_add_vs(buffer, &s->uuid_vs_idx); } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Invalid UUID string length")); From c4b60e6cf84804e65a48fcecdd0cb2290317ec5d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Feb 2017 23:05:32 +0100 Subject: [PATCH 346/809] nrf5/modules: Shortening down the device name to be advertised in the example to make it fit with a 128-bit complete UUID. --- nrf5/modules/ubluepy/modubluepy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 170fb191b3..1fae9b0a69 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -44,7 +44,7 @@ u1 = UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e") c = Characteristic(u1) s.addCharacteristic(c) p = Peripheral() -p.advertise(device_name="MicroPython", services=[s]) +p.advertise(device_name="micr", services=[s]) */ #include "py/obj.h" From 7a43228a2d1e25ef371cc0f2ebcc0c9fabeee37f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 13 Feb 2017 00:16:45 +0100 Subject: [PATCH 347/809] nrf5/sdk: Disable all sdk components from being included in the build while implementing ubluepy, overlap in IRQ handler symbol. --- nrf5/sdk/sdk_12.1.0/build.mk | 2 ++ nrf5/sdk/sdk_common.mk | 1 + 2 files changed, 3 insertions(+) diff --git a/nrf5/sdk/sdk_12.1.0/build.mk b/nrf5/sdk/sdk_12.1.0/build.mk index e14ec76448..6529861e2b 100644 --- a/nrf5/sdk/sdk_12.1.0/build.mk +++ b/nrf5/sdk/sdk_12.1.0/build.mk @@ -27,6 +27,7 @@ DEFINES += NRF_SD_BLE_API_VERSION=3 DEFINES += PEER_MANAGER_ENABLED=1 DEFINES += FDS_ENABLED=1 +ifeq ($(SDK_COMPOENTS), 1) # nordic SDK C sources (relative path) SDK_SRC_C += \ components/ble/ble_advertising/ble_advertising.c \ @@ -58,6 +59,7 @@ SDK_SRC_C += \ components/libraries/util/app_error.c \ components/libraries/util/app_error_weak.c \ components/drivers_nrf/common/nrf_drv_common.c +endif # include source folders (sort removes duplicates) SDK_INC_DIRS += $(sort $(dir $(SDK_SRC_C))) diff --git a/nrf5/sdk/sdk_common.mk b/nrf5/sdk/sdk_common.mk index cc75446b35..da1c35e2d2 100644 --- a/nrf5/sdk/sdk_common.mk +++ b/nrf5/sdk/sdk_common.mk @@ -12,6 +12,7 @@ else ifeq ($(SD), s130) SDK_MODULES = sdk_10.0.0 else ifeq ($(SD), s132) SDK_MODULES = sdk_12.1.0 + SDK_COMPONENTS = 0 else $(error No SDK configured for this SD) endif From a79c5ca7ab91e9fabee0768eece3cca30abbc52a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 13 Feb 2017 00:18:47 +0100 Subject: [PATCH 348/809] nrf5/sdk: Implementing simple event handler for bluetooth stack driver. --- nrf5/sdk/softdevice.c | 44 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 8a6400080f..ce14c3e852 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -35,6 +35,7 @@ #include "ble_gap.h" #include "ble.h" // sd_ble_uuid_encode + #define SD_TEST_OR_ENABLE() \ if (sd_enabled() == 0) { \ (void)sd_enable(); \ @@ -440,3 +441,46 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { return true; } + +static void ble_evt_handler(ble_evt_t * p_ble_evt) { + switch (p_ble_evt->header.evt_id) { + case BLE_GAP_EVT_CONNECTED: + printf(">>> GAP CONNECT\n"); + break; + + case BLE_GAP_EVT_DISCONNECTED: + printf(">>> GAP DISCONNECT\n"); + break; + + case BLE_GATTS_EVT_WRITE: + printf(">>> GATTS write\n"); + break; + + default: + printf(">>> unhandled evt: 0x" HEX2_FMT, p_ble_evt->header.evt_id); + break; + } +} + +static uint8_t m_ble_evt_buf[sizeof(ble_evt_t) + (GATT_MTU_SIZE_DEFAULT)] __attribute__ ((aligned (4))); + +#ifdef NRF51 +void SWI2_IRQHandler(void) { +#else +void SWI2_EGU2_IRQHandler(void) { +#endif + + printf("SWI2 IRQ\n"); + uint32_t evt_id; + uint32_t err_code; + do { + err_code = sd_evt_get(&evt_id); + // TODO: handle non ble events + } while (err_code != NRF_ERROR_NOT_FOUND && err_code != NRF_SUCCESS); + + uint16_t evt_len = sizeof(m_ble_evt_buf); + do { + err_code = sd_ble_evt_get(m_ble_evt_buf, &evt_len); + ble_evt_handler((ble_evt_t *)m_ble_evt_buf); + } while (err_code != NRF_ERROR_NOT_FOUND && err_code != NRF_SUCCESS); +} From 44f701946b81825b578177edf361d2c72ca58a49 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 13 Feb 2017 17:06:13 +0100 Subject: [PATCH 349/809] nrf5/sdk: Correcting advertisment packet in bluetooth driver in order to make the device connectable. --- nrf5/sdk/softdevice.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index ce14c3e852..37b835cd4a 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -97,7 +97,10 @@ uint32_t sd_enable(void) { ble_enable_params_t ble_enable_params; memset(&ble_enable_params, 0x00, sizeof(ble_enable_params)); ble_enable_params.gatts_enable_params.attr_tab_size = BLE_GATTS_ATTR_TAB_SIZE_DEFAULT; - ble_enable_params.gatts_enable_params.service_changed = 0; + ble_enable_params.gatts_enable_params.service_changed = 0; + ble_enable_params.gap_enable_params.periph_conn_count = 1; + ble_enable_params.gap_enable_params.central_conn_count = 1; + #if (BLUETOOTH_SD == 100) || (BLUETOOTH_SD == 110) @@ -415,15 +418,15 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { } printf("Set Adv data size: " UINT_FMT "\n", byte_pos); - ble_gap_adv_params_t m_adv_params; + static ble_gap_adv_params_t m_adv_params; // initialize advertising params memset(&m_adv_params, 0, sizeof(m_adv_params)); - m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_NONCONN_IND; - m_adv_params.p_peer_addr = NULL; // Undirected advertisement. + m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND; + m_adv_params.p_peer_addr = NULL; // undirected advertisement m_adv_params.fp = BLE_GAP_ADV_FP_ANY; - m_adv_params.interval = NON_CONNECTABLE_ADV_INTERVAL; - m_adv_params.timeout = APP_CFG_NON_CONN_ADV_TIMEOUT; + m_adv_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS); // approx 8 ms + m_adv_params.timeout = 0; // infinite advertisment if (m_adv_in_progress && sd_ble_gap_adv_stop() != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, @@ -431,10 +434,10 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { } m_adv_in_progress = false; - - if (sd_ble_gap_adv_start(&m_adv_params) != 0) { + uint32_t err_code = sd_ble_gap_adv_start(&m_adv_params); + if (err_code != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can not start advertisment.")); + "Can not start advertisment. status: 0x" HEX2_FMT, (uint16_t)err_code)); } m_adv_in_progress = true; From 66223b428533aae1e417881f91dbf9c6727fed8d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Feb 2017 20:18:53 +0100 Subject: [PATCH 350/809] nrf5/sdk: Fixing debug print in bluetooth driver to not use >>> prefix. Adding one more print for connection parameter update. --- nrf5/sdk/softdevice.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 37b835cd4a..9efe8f8327 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -446,17 +446,28 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { } static void ble_evt_handler(ble_evt_t * p_ble_evt) { +// S132 event ranges. +// Common 0x01 -> 0x0F +// GAP 0x10 -> 0x2F +// GATTC 0x30 -> 0x4F +// GATTS 0x50 -> 0x6F +// L2CAP 0x70 -> 0x8F + switch (p_ble_evt->header.evt_id) { case BLE_GAP_EVT_CONNECTED: - printf(">>> GAP CONNECT\n"); + printf("GAP CONNECT\n"); break; case BLE_GAP_EVT_DISCONNECTED: - printf(">>> GAP DISCONNECT\n"); + printf("GAP DISCONNECT\n"); break; case BLE_GATTS_EVT_WRITE: - printf(">>> GATTS write\n"); + printf("GATTS write\n"); + break; + + case BLE_GAP_EVT_CONN_PARAM_UPDATE: + printf("GAP CONN PARAM UPDATE\n"); break; default: @@ -473,7 +484,6 @@ void SWI2_IRQHandler(void) { void SWI2_EGU2_IRQHandler(void) { #endif - printf("SWI2 IRQ\n"); uint32_t evt_id; uint32_t err_code; do { From 881e90f7b5e86830682d199f751679e3e90fbc3f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 00:15:48 +0100 Subject: [PATCH 351/809] nrf5/modules: Adding template for ubluepy delegate class. --- nrf5/modules/ubluepy/ubluepy_delegate.c | 88 +++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 nrf5/modules/ubluepy/ubluepy_delegate.c diff --git a/nrf5/modules/ubluepy/ubluepy_delegate.c b/nrf5/modules/ubluepy/ubluepy_delegate.c new file mode 100644 index 0000000000..0b15caa27e --- /dev/null +++ b/nrf5/modules/ubluepy/ubluepy_delegate.c @@ -0,0 +1,88 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/runtime.h" +#include "modubluepy.h" + +#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL + +STATIC void ubluepy_delegate_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + ubluepy_delegate_obj_t * self = (ubluepy_delegate_obj_t *)o; + (void)self; + mp_printf(print, "DefaultDelegate()"); +} + +STATIC mp_obj_t ubluepy_delegate_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + ubluepy_delegate_obj_t *s = m_new_obj(ubluepy_delegate_obj_t); + s->base.type = type; + + return MP_OBJ_FROM_PTR(s); +} + +/// \method handleConnection() +/// Handle connection events. +/// +STATIC mp_obj_t delegate_handle_conn(mp_obj_t self_in) { + ubluepy_delegate_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_delegate_handle_conn_obj, delegate_handle_conn); + +/// \method handleNotification() +/// Handle notification events. +/// +STATIC mp_obj_t delegate_handle_notif(mp_obj_t self_in) { + ubluepy_delegate_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_delegate_handle_notif_obj, delegate_handle_notif); + +STATIC const mp_map_elem_t ubluepy_delegate_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_handleConnection), (mp_obj_t)(&ubluepy_delegate_handle_conn_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_handleNotification), (mp_obj_t)(&ubluepy_delegate_handle_notif_obj) }, +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_handleDiscovery), (mp_obj_t)(&ubluepy_delegate_handle_disc_obj) }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_delegate_locals_dict, ubluepy_delegate_locals_dict_table); + +const mp_obj_type_t ubluepy_delegate_type = { + { &mp_type_type }, + .name = MP_QSTR_DefaultDelegate, + .print = ubluepy_delegate_print, + .make_new = ubluepy_delegate_make_new, + .locals_dict = (mp_obj_t)&ubluepy_delegate_locals_dict +}; + +#endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL From 8b21ee762ef9bd7ef5c03bb040881421eb6d3d88 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 00:17:04 +0100 Subject: [PATCH 352/809] nrf5/modules: Adding new object struct for delegate class and adding a delegate struct member to Peripheral class to bookeep callback object when event occurs. --- nrf5/modules/ubluepy/modubluepy.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 1fae9b0a69..7754bc6918 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -86,12 +86,22 @@ typedef struct _ubluepy_characteristic_obj_t { uint16_t sccd_handle; } ubluepy_characteristic_obj_t; +typedef struct _ubluepy_delegate_obj_t { + mp_obj_base_t base; +} ubluepy_delegate_obj_t; + +typedef struct _ubluepy_peripheral_obj_t { + mp_obj_base_t base; + mp_obj_t delegate; +} ubluepy_peripheral_obj_t; + typedef struct _ubluepy_advertise_data_t { uint8_t * p_device_name; uint8_t device_name_len; mp_obj_t * p_services; uint8_t num_of_services; - } ubluepy_advertise_data_t; + + #endif // UBLUEPY_H__ From 4f6e235c68be07ab184403237e1a660b0854af0f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 00:17:47 +0100 Subject: [PATCH 353/809] nrf5: Adding ubluepy_delegate.c to list of source files to compile. --- nrf5/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index c85b3685db..b896ece981 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -171,6 +171,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ ubluepy/ubluepy_service.c \ ubluepy/ubluepy_characteristic.c \ ubluepy/ubluepy_uuid.c \ + ubluepy/ubluepy_delegate.c \ ) #ifeq ($(SD), ) From fd4e659da7c6396627cecc7cb659eef2e6e66860 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 00:18:32 +0100 Subject: [PATCH 354/809] nrf5/modules: Adding ubluepy delegate type to modubluepy globals table. --- nrf5/modules/ubluepy/modubluepy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.c b/nrf5/modules/ubluepy/modubluepy.c index 94325b1a8a..cd1aa6250a 100644 --- a/nrf5/modules/ubluepy/modubluepy.c +++ b/nrf5/modules/ubluepy/modubluepy.c @@ -32,6 +32,7 @@ extern const mp_obj_type_t ubluepy_peripheral_type; extern const mp_obj_type_t ubluepy_service_type; extern const mp_obj_type_t ubluepy_uuid_type; extern const mp_obj_type_t ubluepy_characteristic_type; +extern const mp_obj_type_t ubluepy_delegate_type; STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy) }, @@ -47,9 +48,7 @@ STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { #if MICROPY_PY_UBLUEPY_CENTRAL { MP_OBJ_NEW_QSTR(MP_QSTR_ScanEntry), (mp_obj_t)&ubluepy_scan_entry_type }, #endif -#if MICROPY_PY_UBLUEPY_DEFAULT_DELEGATE - { MP_OBJ_NEW_QSTR(MP_QSTR_DefaultDelegate), (mp_obj_t)&ubluepy_default_delegate_type }, -#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_DefaultDelegate), (mp_obj_t)&ubluepy_delegate_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_UUID), (mp_obj_t)&ubluepy_uuid_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_Service), (mp_obj_t)&ubluepy_service_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_Characteristic), (mp_obj_t)&ubluepy_characteristic_type }, From b493bfda6426cd1c2ea14f0ac2601f552ffdd6af Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 00:22:00 +0100 Subject: [PATCH 355/809] nrf5/modules: Adding 'withDelegate' function to peripheral class. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 31 ++++++++++++++++++----- 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index a85eb20a77..f5b488e83c 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -33,11 +33,6 @@ #include "softdevice.h" -typedef struct _ubluepy_peripheral_obj_t { - mp_obj_base_t base; - // services -} ubluepy_peripheral_obj_t; - STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_peripheral_obj_t * self = (ubluepy_peripheral_obj_t *)o; (void)self; @@ -65,6 +60,30 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ return MP_OBJ_FROM_PTR(s); } +#if 0 +static void peripheral_delegate(void) { + // delegate + mp_obj_t args[3]; + mp_uint_t num_of_args = 3; + args[0] = type; + args[1] = MP_OBJ_NEW_SMALL_INT(size); + args[2] = mp_obj_new_bytearray_by_ref(size, evt_data); + mp_call_function_n_kw(delegate->handleConnection, num_of_args, 0, args); +} +#endif + +/// \method withDelegate(DefaultDelegate) +/// Set delegate instance for handling Bluetooth LE events. +/// +STATIC mp_obj_t peripheral_with_delegate(mp_obj_t self_in, mp_obj_t delegate) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + + self->delegate = delegate; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_with_delegate_obj, peripheral_with_delegate); + /// \method advertise(device_name, [service=[service1, service2, ...]], [data=bytearray]) /// Start advertising. /// @@ -142,6 +161,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_add_service_obj, peripheral_ STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, #if MICROPY_PY_UBLUEPY_CENTRAL { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, @@ -149,7 +169,6 @@ STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_getServiceByUUID), (mp_obj_t)(&ubluepy_peripheral_get_service_by_uuid_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_peripheral_get_chars_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getDescriptors), (mp_obj_t)(&ubluepy_peripheral_get_descs_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_waitForNotifications), (mp_obj_t)(&ubluepy_peripheral_wait_for_notif_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, From 8d1b05563cfcb00d25f1972def1058ea9b6d9024 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 00:26:39 +0100 Subject: [PATCH 356/809] nrf5/modules: Moving includes inside config defines to make non-ubluepy targets compile again. --- nrf5/modules/ubluepy/ubluepy_service.c | 5 +++-- nrf5/modules/ubluepy/ubluepy_uuid.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 536e4943f9..5178e4e695 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -24,13 +24,14 @@ * THE SOFTWARE. */ + +#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL + #include "py/obj.h" #include "py/runtime.h" #include "modubluepy.h" #include "softdevice.h" -#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL - STATIC void ubluepy_service_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_service_obj_t * self = (ubluepy_service_obj_t *)o; diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index ddea56160b..dc880e67ae 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -24,6 +24,8 @@ * THE SOFTWARE. */ +#if MICROPY_PY_UBLUEPY + #include "py/obj.h" #include "py/runtime.h" #include "py/objstr.h" @@ -32,8 +34,6 @@ #include "modubluepy.h" #include "softdevice.h" -#if MICROPY_PY_UBLUEPY - STATIC void ubluepy_uuid_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_uuid_obj_t * self = (ubluepy_uuid_obj_t *)o; if (self->type == UBLUEPY_UUID_16_BIT) { From ec517a37f62aa181ae9d133f96e6a5e54eac6187 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 19:13:55 +0100 Subject: [PATCH 357/809] nrf5: Set ubluepy to disabled by default in mpconfigport.h if not configured. --- nrf5/mpconfigport.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index a9f3f8ee45..614c0d768c 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -209,6 +209,10 @@ #include "nrf5_sdk_conf.h" #endif +#ifndef MICROPY_PY_UBLUEPY +#define MICROPY_PY_UBLUEPY (0) +#endif + // type definitions for the specific machine #define BYTES_PER_WORD (4) From db75b5535cf3bea8a0eb209a98a19a52458c1946 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 19:30:45 +0100 Subject: [PATCH 358/809] nrf5/modules: Adding two new functions to ubluepy peripheral class to set specific handlers for notificaitons and connection related events. --- nrf5/modules/ubluepy/modubluepy.h | 2 + nrf5/modules/ubluepy/ubluepy_peripheral.c | 60 ++++++++++++++++------- 2 files changed, 45 insertions(+), 17 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 7754bc6918..aef5408542 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -93,6 +93,8 @@ typedef struct _ubluepy_delegate_obj_t { typedef struct _ubluepy_peripheral_obj_t { mp_obj_base_t base; mp_obj_t delegate; + mp_obj_t notif_handler; + mp_obj_t conn_handler; } ubluepy_peripheral_obj_t; typedef struct _ubluepy_advertise_data_t { diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index f5b488e83c..12d50fe96f 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -84,6 +84,30 @@ STATIC mp_obj_t peripheral_with_delegate(mp_obj_t self_in, mp_obj_t delegate) { } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_with_delegate_obj, peripheral_with_delegate); +/// \method setNotificationHandler(func) +/// Set handler for Bluetooth LE notification events. +/// +STATIC mp_obj_t peripheral_set_notif_handler(mp_obj_t self_in, mp_obj_t func) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + + self->notif_handler = func; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_set_notif_handler_obj, peripheral_set_notif_handler); + +/// \method setConnectionHandler(func) +/// Set handler for Bluetooth LE connection events. +/// +STATIC mp_obj_t peripheral_set_conn_handler(mp_obj_t self_in, mp_obj_t func) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + + self->conn_handler = func; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_set_conn_handler_obj, peripheral_set_conn_handler); + /// \method advertise(device_name, [service=[service1, service2, ...]], [data=bytearray]) /// Start advertising. /// @@ -161,27 +185,29 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_add_service_obj, peripheral_ STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setNotificationHandler), (mp_obj_t)(&ubluepy_peripheral_set_notif_handler_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setConnectionHandler), (mp_obj_t)(&ubluepy_peripheral_set_conn_handler_obj) }, #if MICROPY_PY_UBLUEPY_CENTRAL - { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getServiceByUUID), (mp_obj_t)(&ubluepy_peripheral_get_service_by_uuid_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_peripheral_get_chars_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getDescriptors), (mp_obj_t)(&ubluepy_peripheral_get_descs_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_waitForNotifications), (mp_obj_t)(&ubluepy_peripheral_wait_for_notif_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getServiceByUUID), (mp_obj_t)(&ubluepy_peripheral_get_service_by_uuid_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_peripheral_get_chars_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getDescriptors), (mp_obj_t)(&ubluepy_peripheral_get_descs_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_waitForNotifications), (mp_obj_t)(&ubluepy_peripheral_wait_for_notif_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, #endif #if MICROPY_PY_UBLUEPY_PERIPHERAL - { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_addService), (mp_obj_t)(&ubluepy_peripheral_add_service_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_addService), (mp_obj_t)(&ubluepy_peripheral_add_service_obj) }, #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_peripheral_add_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_addDescriptor), (mp_obj_t)(&ubluepy_peripheral_add_desc_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_peripheral_add_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_addDescriptor), (mp_obj_t)(&ubluepy_peripheral_add_desc_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, #endif #endif #if MICROPY_PY_UBLUEPY_BROADCASTER From d29539a395529038691b1afe309e4ab06cae548f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 19:33:11 +0100 Subject: [PATCH 359/809] nrf5/modules: Splitting includes to be inside or outside of the compile guard in ubluepy. This way, all micropython specific includes will be outside, and internal will be inside. This way, there will not be any dependency towards ubluepy headers if not compiled in. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 3 ++- nrf5/modules/ubluepy/ubluepy_delegate.c | 3 ++- nrf5/modules/ubluepy/ubluepy_service.c | 4 ++-- nrf5/modules/ubluepy/ubluepy_uuid.c | 4 ++-- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index 403f8e09be..bca1b184b1 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -26,10 +26,11 @@ #include "py/obj.h" #include "py/runtime.h" -#include "modubluepy.h" #if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL +#include "modubluepy.h" + STATIC void ubluepy_characteristic_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_characteristic_obj_t * self = (ubluepy_characteristic_obj_t *)o; diff --git a/nrf5/modules/ubluepy/ubluepy_delegate.c b/nrf5/modules/ubluepy/ubluepy_delegate.c index 0b15caa27e..7467398e68 100644 --- a/nrf5/modules/ubluepy/ubluepy_delegate.c +++ b/nrf5/modules/ubluepy/ubluepy_delegate.c @@ -26,10 +26,11 @@ #include "py/obj.h" #include "py/runtime.h" -#include "modubluepy.h" #if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL +#include "modubluepy.h" + STATIC void ubluepy_delegate_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_delegate_obj_t * self = (ubluepy_delegate_obj_t *)o; (void)self; diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 5178e4e695..a365f410c3 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -24,11 +24,11 @@ * THE SOFTWARE. */ +#include "py/obj.h" +#include "py/runtime.h" #if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL -#include "py/obj.h" -#include "py/runtime.h" #include "modubluepy.h" #include "softdevice.h" diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index dc880e67ae..11f54c7045 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -24,13 +24,13 @@ * THE SOFTWARE. */ -#if MICROPY_PY_UBLUEPY - #include "py/obj.h" #include "py/runtime.h" #include "py/objstr.h" #include "py/misc.h" +#if MICROPY_PY_UBLUEPY + #include "modubluepy.h" #include "softdevice.h" From 832a7ffd143199473c615c418c4d2962c14f8040 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 23:32:42 +0100 Subject: [PATCH 360/809] nrf5/modules: updating ubluepy and bluetooth driver to support python created event handler. Added registration of callback from ubluepy against the bluetooth driver and dispatching of events to the user supplied python function. --- nrf5/modules/ubluepy/modubluepy.h | 6 +++- nrf5/modules/ubluepy/ubluepy_peripheral.c | 37 ++++++++++++++--------- nrf5/sdk/softdevice.c | 11 ++++++- nrf5/sdk/softdevice.h | 3 ++ 4 files changed, 41 insertions(+), 16 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index aef5408542..685a54b5e9 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -37,6 +37,9 @@ p.advertise(device_name="MicroPython") DB setup: +def event_handler(id, length, data): + print("BLE event:", id, " length: ", length) + from ubluepy import Service, Characteristic, UUID, Peripheral u0 = UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e") s = Service(u0) @@ -44,6 +47,7 @@ u1 = UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e") c = Characteristic(u1) s.addCharacteristic(c) p = Peripheral() +p.setConnectionHandler(event_handler) p.advertise(device_name="micr", services=[s]) */ @@ -104,6 +108,6 @@ typedef struct _ubluepy_advertise_data_t { uint8_t num_of_services; } ubluepy_advertise_data_t; - +typedef void (*ubluepy_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t length, uint8_t * data); #endif // UBLUEPY_H__ diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 12d50fe96f..aa55b8ff48 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -39,6 +39,25 @@ STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_pri mp_printf(print, "Peripheral"); } +STATIC void event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t length, uint8_t * data) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + + mp_obj_t args[3]; + mp_uint_t num_of_args = 3; + args[0] = MP_OBJ_NEW_SMALL_INT(event_id); + args[1] = MP_OBJ_NEW_SMALL_INT(length); + if (data != NULL) { + args[2] = mp_obj_new_bytearray_by_ref(length, data); + } else { + args[2] = mp_const_none; + } + + // for now hard-code all events to conn_handler + mp_call_function_n_kw(self->conn_handler, num_of_args, 0, args); + + (void)self; +} + STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { enum { ARG_NEW_DEVICE_ADDR, @@ -46,8 +65,8 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ }; static const mp_arg_t allowed_args[] = { - { ARG_NEW_DEVICE_ADDR, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_ADDR_TYPE, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { ARG_NEW_DEVICE_ADDR, MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { ARG_NEW_ADDR_TYPE, MP_ARG_OBJ, {.u_obj = mp_const_none} }, }; // parse args @@ -57,21 +76,11 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ ubluepy_peripheral_obj_t *s = m_new_obj(ubluepy_peripheral_obj_t); s->base.type = type; + sd_event_handler_set(MP_OBJ_FROM_PTR(s), event_handler); + return MP_OBJ_FROM_PTR(s); } -#if 0 -static void peripheral_delegate(void) { - // delegate - mp_obj_t args[3]; - mp_uint_t num_of_args = 3; - args[0] = type; - args[1] = MP_OBJ_NEW_SMALL_INT(size); - args[2] = mp_obj_new_bytearray_by_ref(size, evt_data); - mp_call_function_n_kw(delegate->handleConnection, num_of_args, 0, args); -} -#endif - /// \method withDelegate(DefaultDelegate) /// Set delegate instance for handling Bluetooth LE events. /// diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 9efe8f8327..0cfd2beb27 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -41,7 +41,10 @@ if (sd_enabled() == 0) { \ (void)sd_enable(); \ } -bool m_adv_in_progress = false; +static bool m_adv_in_progress = false; + +static ubluepy_evt_callback_t ubluepy_event_handler; +static mp_obj_t mp_observer; #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -445,6 +448,11 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { return true; } +void sd_event_handler_set(mp_obj_t obj, ubluepy_evt_callback_t evt_handler) { + mp_observer = obj; + ubluepy_event_handler = evt_handler; +} + static void ble_evt_handler(ble_evt_t * p_ble_evt) { // S132 event ranges. // Common 0x01 -> 0x0F @@ -455,6 +463,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { switch (p_ble_evt->header.evt_id) { case BLE_GAP_EVT_CONNECTED: + ubluepy_event_handler(mp_observer, BLE_GAP_EVT_CONNECTED, p_ble_evt->header.evt_len - sizeof(uint16_t), NULL); printf("GAP CONNECT\n"); break; diff --git a/nrf5/sdk/softdevice.h b/nrf5/sdk/softdevice.h index ba79d89866..f17395e517 100644 --- a/nrf5/sdk/softdevice.h +++ b/nrf5/sdk/softdevice.h @@ -49,4 +49,7 @@ bool sd_service_add(ubluepy_service_obj_t * p_service_obj); bool sd_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj); bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params); + +void sd_event_handler_set(mp_obj_t obs, ubluepy_evt_callback_t evt_handler); + #endif // BLUETOOTH_LE_DRIVER_H__ From d88320b5b33bfb76528962699599578a31ad81bd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 23:57:23 +0100 Subject: [PATCH 361/809] nrf5/sdk: Updating bluetooth driver to have configurable logs. --- nrf5/sdk/softdevice.c | 62 +++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 26 deletions(-) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 0cfd2beb27..d5cfa56ef7 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -36,6 +36,14 @@ #include "ble.h" // sd_ble_uuid_encode +#define BLE_DRIVER_VERBOSE 0 +#if BLE_DRIVER_VERBOSE +#define BLE_DRIVER_LOG printf +#else +#define BLE_DRIVER_LOG(...) +#endif + + #define SD_TEST_OR_ENABLE() \ if (sd_enabled() == 0) { \ (void)sd_enable(); \ @@ -59,11 +67,11 @@ nrf_nvic_state_t nrf_nvic_state; #if (BLUETOOTH_SD == 100 ) || (BLUETOOTH_SD == 110) void softdevice_assert_handler(uint32_t pc, uint16_t line_number, const uint8_t * p_file_name) { - printf("ERROR: SoftDevice assert!!!"); + BLE_DRIVER_LOG("ERROR: SoftDevice assert!!!"); } #else void softdevice_assert_handler(uint32_t id, uint32_t pc, uint32_t info) { - printf("ERROR: SoftDevice assert!!!"); + BLE_DRIVER_LOG("ERROR: SoftDevice assert!!!"); } #endif uint32_t sd_enable(void) { @@ -86,7 +94,7 @@ uint32_t sd_enable(void) { softdevice_assert_handler); #endif - printf("SoftDevice enable status: " UINT_FMT "\n", (uint16_t)err_code); + BLE_DRIVER_LOG("SoftDevice enable status: " UINT_FMT "\n", (uint16_t)err_code); #if NRF51 err_code = sd_nvic_EnableIRQ(SWI2_IRQn); @@ -94,7 +102,7 @@ uint32_t sd_enable(void) { err_code = sd_nvic_EnableIRQ(SWI2_EGU2_IRQn); #endif - printf("IRQ enable status: " UINT_FMT "\n", (uint16_t)err_code); + BLE_DRIVER_LOG("IRQ enable status: " UINT_FMT "\n", (uint16_t)err_code); // Enable BLE stack. ble_enable_params_t ble_enable_params; @@ -113,14 +121,14 @@ uint32_t sd_enable(void) { #if (BLUETOOTH_SD == 132) uint32_t app_ram_start = 0x200039c0; err_code = sd_ble_enable(&ble_enable_params, &app_ram_start); // 8K SD headroom from linker script. - printf("BLE ram size: " UINT_FMT "\n", (uint16_t)app_ram_start); + BLE_DRIVER_LOG("BLE ram size: " UINT_FMT "\n", (uint16_t)app_ram_start); #else err_code = sd_ble_enable(&ble_enable_params, (uint32_t *)0x20001870); #endif #endif - printf("BLE enable status: " UINT_FMT "\n", (uint16_t)err_code); + BLE_DRIVER_LOG("BLE enable status: " UINT_FMT "\n", (uint16_t)err_code); return err_code; } @@ -132,10 +140,9 @@ void sd_disable(void) { uint8_t sd_enabled(void) { uint8_t is_enabled; uint32_t err_code = sd_softdevice_is_enabled(&is_enabled); + (void)err_code; -#if BLUETOOTH_SD_DEBUG - printf("Is enabled status: " UINT_FMT "\n", (uint16_t)err_code); -#endif + BLE_DRIVER_LOG("Is enabled status: " UINT_FMT "\n", (uint16_t)err_code); return is_enabled; } @@ -147,7 +154,7 @@ void sd_address_get(void) { #else uint32_t err_code = sd_ble_gap_addr_get(&local_ble_addr); #endif - printf("ble address, type: " HEX2_FMT ", " \ + BLE_DRIVER_LOG("ble address, type: " HEX2_FMT ", " \ "address: " HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT ":" \ HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT "\n", \ local_ble_addr.addr_type, \ @@ -179,9 +186,10 @@ void sd_advertise(void) { uint8_t encoded_size; uint8_t uuid_encoded[2]; uint32_t err_code = sd_ble_uuid_encode(&adv_uuids[0], &encoded_size, uuid_encoded); + (void)err_code; - printf("Encoded UUID size: " UINT_FMT ": result: " HEX2_FMT "\n", encoded_size, (uint16_t)err_code); - printf("Encoded UUID: " HEX2_FMT " " HEX2_FMT "\n", uuid_encoded[0], uuid_encoded[1]); + BLE_DRIVER_LOG("Encoded UUID size: " UINT_FMT ": result: " HEX2_FMT "\n", encoded_size, (uint16_t)err_code); + BLE_DRIVER_LOG("Encoded UUID: " HEX2_FMT " " HEX2_FMT "\n", uuid_encoded[0], uuid_encoded[1]); uint8_t eddystone_data[] = {EDDYSTONE_DATA}; // Temp buffer to calculate the size. @@ -200,7 +208,7 @@ void sd_advertise(void) { // Scan response data not set. err_code = sd_ble_gap_adv_data_set(adv_data, sizeof(adv_data), NULL, 0); - printf("Set Adv data status: " UINT_FMT ", size: " UINT_FMT "\n", (uint16_t)err_code, sizeof(adv_data)); + BLE_DRIVER_LOG("Set Adv data status: " UINT_FMT ", size: " UINT_FMT "\n", (uint16_t)err_code, sizeof(adv_data)); ble_gap_adv_params_t m_adv_params; @@ -214,7 +222,7 @@ void sd_advertise(void) { err_code = sd_ble_gap_adv_start(&m_adv_params); - printf("Advertisment start status: " UINT_FMT "\n", (uint16_t)err_code); + BLE_DRIVER_LOG("Advertisment start status: " UINT_FMT "\n", (uint16_t)err_code); } bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx) { @@ -344,7 +352,7 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { "Can not apply device name in the stack.")); } - printf("Device name applied\n"); + BLE_DRIVER_LOG("Device name applied\n"); adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + p_adv_params->device_name_len); byte_pos += BLE_ADV_LENGTH_FIELD_SIZE; @@ -396,15 +404,15 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { "Can encode UUID into the advertisment packet.")); } - printf("encoded uuid for service %u: ", 0); + BLE_DRIVER_LOG("encoded uuid for service %u: ", 0); for (uint8_t j = 0; j < encoded_size; j++) { - printf(HEX2_FMT " ", adv_data[byte_pos + j]); + BLE_DRIVER_LOG(HEX2_FMT " ", adv_data[byte_pos + j]); } - printf("\n"); + BLE_DRIVER_LOG("\n"); uuid_total_size += encoded_size; // size of entry byte_pos += encoded_size; // relative to adv data packet - printf("ADV: uuid size: %u, type: %u, uuid: %u, vs_idx: %u\n", + BLE_DRIVER_LOG("ADV: uuid size: %u, type: %u, uuid: %u, vs_idx: %u\n", encoded_size, p_service->p_uuid->type, (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]), p_service->p_uuid->uuid_vs_idx); @@ -419,7 +427,7 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not apply advertisment data.")); } - printf("Set Adv data size: " UINT_FMT "\n", byte_pos); + BLE_DRIVER_LOG("Set Adv data size: " UINT_FMT "\n", byte_pos); static ble_gap_adv_params_t m_adv_params; @@ -461,26 +469,28 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { // GATTS 0x50 -> 0x6F // L2CAP 0x70 -> 0x8F + ubluepy_event_handler(mp_observer, p_ble_evt->header.evt_id, p_ble_evt->header.evt_len - sizeof(uint16_t), NULL); + + switch (p_ble_evt->header.evt_id) { case BLE_GAP_EVT_CONNECTED: - ubluepy_event_handler(mp_observer, BLE_GAP_EVT_CONNECTED, p_ble_evt->header.evt_len - sizeof(uint16_t), NULL); - printf("GAP CONNECT\n"); + BLE_DRIVER_LOG("GAP CONNECT\n"); break; case BLE_GAP_EVT_DISCONNECTED: - printf("GAP DISCONNECT\n"); + BLE_DRIVER_LOG("GAP DISCONNECT\n"); break; case BLE_GATTS_EVT_WRITE: - printf("GATTS write\n"); + BLE_DRIVER_LOG("GATTS write\n"); break; case BLE_GAP_EVT_CONN_PARAM_UPDATE: - printf("GAP CONN PARAM UPDATE\n"); + BLE_DRIVER_LOG("GAP CONN PARAM UPDATE\n"); break; default: - printf(">>> unhandled evt: 0x" HEX2_FMT, p_ble_evt->header.evt_id); + BLE_DRIVER_LOG(">>> unhandled evt: 0x" HEX2_FMT, p_ble_evt->header.evt_id); break; } } From 18365135f722dbbd96a8f34b19e69e83aab248f5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 15 Feb 2017 23:58:23 +0100 Subject: [PATCH 362/809] nrf5/modules: Updating ubluepy example to turn led2 on and off when receiving connected and disconnect bluetooth event. --- nrf5/modules/ubluepy/modubluepy.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 685a54b5e9..f4a585fe24 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -37,10 +37,19 @@ p.advertise(device_name="MicroPython") DB setup: +from ubluepy import Service, Characteristic, UUID, Peripheral +from pyb import LED + def event_handler(id, length, data): print("BLE event:", id, " length: ", length) -from ubluepy import Service, Characteristic, UUID, Peripheral + if id == 16: + # connected + LED(2).on() + elif id == 17: + # disconnect + LED(2).off() + u0 = UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e") s = Service(u0) u1 = UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e") From 2fd55feb0cd2b68cf20a9bf0443933e45f994387 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 16 Feb 2017 18:49:47 +0100 Subject: [PATCH 363/809] nrf5/modules: Guarding callback to python event handler before issue the call in case it is not set. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 28 ++++++++++++++--------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index aa55b8ff48..c3db8211b2 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -42,18 +42,20 @@ STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_pri STATIC void event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t length, uint8_t * data) { ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); - mp_obj_t args[3]; - mp_uint_t num_of_args = 3; - args[0] = MP_OBJ_NEW_SMALL_INT(event_id); - args[1] = MP_OBJ_NEW_SMALL_INT(length); - if (data != NULL) { - args[2] = mp_obj_new_bytearray_by_ref(length, data); - } else { - args[2] = mp_const_none; - } + if (self->conn_handler != mp_const_none) { + mp_obj_t args[3]; + mp_uint_t num_of_args = 3; + args[0] = MP_OBJ_NEW_SMALL_INT(event_id); + args[1] = MP_OBJ_NEW_SMALL_INT(length); + if (data != NULL) { + args[2] = mp_obj_new_bytearray_by_ref(length, data); + } else { + args[2] = mp_const_none; + } - // for now hard-code all events to conn_handler - mp_call_function_n_kw(self->conn_handler, num_of_args, 0, args); + // for now hard-code all events to conn_handler + mp_call_function_n_kw(self->conn_handler, num_of_args, 0, args); + } (void)self; } @@ -78,6 +80,10 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ sd_event_handler_set(MP_OBJ_FROM_PTR(s), event_handler); + s->delegate = mp_const_none; + s->conn_handler = mp_const_none; + s->notif_handler = mp_const_none; + return MP_OBJ_FROM_PTR(s); } From 7ce31444a065ff225944b8833f50ab9aea277330 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 16 Feb 2017 23:18:07 +0100 Subject: [PATCH 364/809] nrf5: Adding target to flash bluetooth stack when using pyocd-flashtool. --- nrf5/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index b896ece981..d7aeb43984 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -219,6 +219,11 @@ else ifeq ($(FLASHER), pyocd) flash: $(BUILD)/firmware.elf pyocd-flashtool -t $(MCU_VARIANT) $(BUILD)/firmware.hex +sd: + pyocd-flashtool -t $(MCU_VARIANT) --chip_erase + pyocd-flashtool -t $(MCU_VARIANT) $(SOFTDEV_HEX) + pyocd-flashtool -t $(MCU_VARIANT) $(BUILD)/firmware.hex + endif $(BUILD)/firmware.elf: $(OBJ) From bba8221aa2041ae8414081d49f27c85019689760 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 17 Feb 2017 17:32:42 +0100 Subject: [PATCH 365/809] nrf5/modules: Updating bluetooth driver and ubluepy to use explicit gap event handler. Adding connection handle parameter to the gap handler from ubluepy. Resetting advertisment flag if connection event is recieved, in order to allow for subsequent advertisment if disconnected again. Example in ublupy header updated. --- nrf5/modules/ubluepy/modubluepy.h | 7 ++++--- nrf5/modules/ubluepy/ubluepy_peripheral.c | 16 +++++++++------- nrf5/sdk/softdevice.c | 15 +++++++-------- nrf5/sdk/softdevice.h | 2 +- 4 files changed, 21 insertions(+), 19 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index f4a585fe24..c6bec69825 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -40,8 +40,8 @@ DB setup: from ubluepy import Service, Characteristic, UUID, Peripheral from pyb import LED -def event_handler(id, length, data): - print("BLE event:", id, " length: ", length) +def event_handler(id, conn_handle, length, data): + print("BLE event:", id, "conn_handle:", conn_handle, "length:", length) if id == 16: # connected @@ -105,6 +105,7 @@ typedef struct _ubluepy_delegate_obj_t { typedef struct _ubluepy_peripheral_obj_t { mp_obj_base_t base; + uint16_t conn_handle; mp_obj_t delegate; mp_obj_t notif_handler; mp_obj_t conn_handler; @@ -117,6 +118,6 @@ typedef struct _ubluepy_advertise_data_t { uint8_t num_of_services; } ubluepy_advertise_data_t; -typedef void (*ubluepy_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t length, uint8_t * data); +typedef void (*ubluepy_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); #endif // UBLUEPY_H__ diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index c3db8211b2..6c9e2a751c 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -39,18 +39,19 @@ STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_pri mp_printf(print, "Peripheral"); } -STATIC void event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t length, uint8_t * data) { +STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data) { ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); if (self->conn_handler != mp_const_none) { - mp_obj_t args[3]; - mp_uint_t num_of_args = 3; + mp_obj_t args[4]; + mp_uint_t num_of_args = 4; args[0] = MP_OBJ_NEW_SMALL_INT(event_id); - args[1] = MP_OBJ_NEW_SMALL_INT(length); + args[1] = MP_OBJ_NEW_SMALL_INT(conn_handle); + args[2] = MP_OBJ_NEW_SMALL_INT(length); if (data != NULL) { - args[2] = mp_obj_new_bytearray_by_ref(length, data); + args[3] = mp_obj_new_bytearray_by_ref(length, data); } else { - args[2] = mp_const_none; + args[3] = mp_const_none; } // for now hard-code all events to conn_handler @@ -78,11 +79,12 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ ubluepy_peripheral_obj_t *s = m_new_obj(ubluepy_peripheral_obj_t); s->base.type = type; - sd_event_handler_set(MP_OBJ_FROM_PTR(s), event_handler); + sd_gap_event_handler_set(MP_OBJ_FROM_PTR(s), gap_event_handler); s->delegate = mp_const_none; s->conn_handler = mp_const_none; s->notif_handler = mp_const_none; + s->conn_handle = 0xFFFF; return MP_OBJ_FROM_PTR(s); } diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index d5cfa56ef7..07f8602667 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -51,8 +51,8 @@ if (sd_enabled() == 0) { \ static bool m_adv_in_progress = false; -static ubluepy_evt_callback_t ubluepy_event_handler; -static mp_obj_t mp_observer; +static ubluepy_gap_evt_callback_t ubluepy_gap_event_handler; +static mp_obj_t mp_observer; #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -456,9 +456,9 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { return true; } -void sd_event_handler_set(mp_obj_t obj, ubluepy_evt_callback_t evt_handler) { +void sd_gap_event_handler_set(mp_obj_t obj, ubluepy_gap_evt_callback_t evt_handler) { mp_observer = obj; - ubluepy_event_handler = evt_handler; + ubluepy_gap_event_handler = evt_handler; } static void ble_evt_handler(ble_evt_t * p_ble_evt) { @@ -468,17 +468,16 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { // GATTC 0x30 -> 0x4F // GATTS 0x50 -> 0x6F // L2CAP 0x70 -> 0x8F - - ubluepy_event_handler(mp_observer, p_ble_evt->header.evt_id, p_ble_evt->header.evt_len - sizeof(uint16_t), NULL); - - switch (p_ble_evt->header.evt_id) { case BLE_GAP_EVT_CONNECTED: BLE_DRIVER_LOG("GAP CONNECT\n"); + m_adv_in_progress = false; + ubluepy_gap_event_handler(mp_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); break; case BLE_GAP_EVT_DISCONNECTED: BLE_DRIVER_LOG("GAP DISCONNECT\n"); + ubluepy_gap_event_handler(mp_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); break; case BLE_GATTS_EVT_WRITE: diff --git a/nrf5/sdk/softdevice.h b/nrf5/sdk/softdevice.h index f17395e517..f3311c8054 100644 --- a/nrf5/sdk/softdevice.h +++ b/nrf5/sdk/softdevice.h @@ -50,6 +50,6 @@ bool sd_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj); bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params); -void sd_event_handler_set(mp_obj_t obs, ubluepy_evt_callback_t evt_handler); +void sd_gap_event_handler_set(mp_obj_t obs, ubluepy_gap_evt_callback_t evt_handler); #endif // BLUETOOTH_LE_DRIVER_H__ From 86c900313c2efb4138a5af750a3898426c006b30 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 17 Feb 2017 18:09:23 +0100 Subject: [PATCH 366/809] nrf5/sdk: Updating bluetooth driver to only set periph and central count if s132 bluetooth stack. These parameters does not exist in older stacks. --- nrf5/sdk/softdevice.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 07f8602667..37200874dc 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -109,9 +109,10 @@ uint32_t sd_enable(void) { memset(&ble_enable_params, 0x00, sizeof(ble_enable_params)); ble_enable_params.gatts_enable_params.attr_tab_size = BLE_GATTS_ATTR_TAB_SIZE_DEFAULT; ble_enable_params.gatts_enable_params.service_changed = 0; +#if (BLUETOOTH_SD == 132) ble_enable_params.gap_enable_params.periph_conn_count = 1; ble_enable_params.gap_enable_params.central_conn_count = 1; - +#endif #if (BLUETOOTH_SD == 100) || (BLUETOOTH_SD == 110) From 3ff245f667167309ec41941036daa358bc60209d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 17 Feb 2017 18:11:22 +0100 Subject: [PATCH 367/809] nrf5/sdk: Enable ubluepy module if s110 bluetooth stack is enabled. --- nrf5/sdk/nrf5_sdk_conf.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nrf5/sdk/nrf5_sdk_conf.h b/nrf5/sdk/nrf5_sdk_conf.h index 84facef84b..beac291931 100644 --- a/nrf5/sdk/nrf5_sdk_conf.h +++ b/nrf5/sdk/nrf5_sdk_conf.h @@ -13,6 +13,9 @@ #elif (BLUETOOTH_SD == 110) #define MICROPY_PY_BLE (1) +#define MICROPY_PY_BLE_NUS (0) +#define MICROPY_PY_UBLUEPY (1) +#define MICROPY_PY_UBLUEPY_PERIPHERAL (1) #elif (BLUETOOTH_SD == 132) From 5f4c464f29db16ac1bad83c5342f015176d98726 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 17 Feb 2017 19:02:24 +0100 Subject: [PATCH 368/809] nrf5/sdk: Renaming bluetooth driver functions to have ble_drv* prefix. Updating modules using it. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 4 ++-- nrf5/modules/ubluepy/ubluepy_service.c | 4 ++-- nrf5/modules/ubluepy/ubluepy_uuid.c | 2 +- nrf5/sdk/modble.c | 10 +++++----- nrf5/sdk/softdevice.c | 24 +++++++++++------------ nrf5/sdk/softdevice.h | 20 +++++++++---------- 6 files changed, 32 insertions(+), 32 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 6c9e2a751c..285132964c 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -79,7 +79,7 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ ubluepy_peripheral_obj_t *s = m_new_obj(ubluepy_peripheral_obj_t); s->base.type = type; - sd_gap_event_handler_set(MP_OBJ_FROM_PTR(s), gap_event_handler); + ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(s), gap_event_handler); s->delegate = mp_const_none; s->conn_handler = mp_const_none; @@ -169,7 +169,7 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, } - (void)sd_advertise_data(&adv_data); + (void)ble_drv_advertise_data(&adv_data); return mp_const_none; } diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index a365f410c3..c051c59c8a 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -71,7 +71,7 @@ STATIC mp_obj_t ubluepy_service_make_new(const mp_obj_type_t *type, size_t n_arg "Invalid Service type")); } - (void)sd_service_add(s); + (void)ble_drv_service_add(s); } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, @@ -90,7 +90,7 @@ STATIC mp_obj_t service_add_characteristic(mp_obj_t self_in, mp_obj_t characteri p_char->service_handle = self->handle; - bool retval = sd_characteristic_add(p_char); + bool retval = ble_drv_characteristic_add(p_char); return mp_obj_new_bool(retval); } diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index 11f54c7045..b6575cd2e5 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -120,7 +120,7 @@ STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, buffer[15] = unichar_xdigit_value(str_data[1]); buffer[15] += unichar_xdigit_value(str_data[0]) << 4; - sd_uuid_add_vs(buffer, &s->uuid_vs_idx); + ble_drv_uuid_add_vs(buffer, &s->uuid_vs_idx); } else { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Invalid UUID string length")); diff --git a/nrf5/sdk/modble.c b/nrf5/sdk/modble.c index 07655b0f83..40443a59df 100644 --- a/nrf5/sdk/modble.c +++ b/nrf5/sdk/modble.c @@ -38,7 +38,7 @@ /// Enable BLE softdevice. mp_obj_t ble_obj_enable(void) { printf("SoftDevice enabled\n"); - uint32_t err_code = sd_enable(); + uint32_t err_code = ble_drv_stack_enable(); if (err_code < 0) { // TODO: raise exception. } @@ -48,14 +48,14 @@ mp_obj_t ble_obj_enable(void) { /// \method disable() /// Disable BLE softdevice. mp_obj_t ble_obj_disable(void) { - sd_disable(); + ble_drv_stack_disable(); return mp_const_none; } /// \method enabled() /// Get state of whether the softdevice is enabled or not. mp_obj_t ble_obj_enabled(void) { - uint8_t is_enabled = sd_enabled(); + uint8_t is_enabled = ble_drv_stack_enabled(); mp_int_t enabled = is_enabled; return MP_OBJ_NEW_SMALL_INT(enabled); } @@ -63,14 +63,14 @@ mp_obj_t ble_obj_enabled(void) { /// \method address_print() /// Print device address. mp_obj_t ble_obj_address_print(void) { - sd_address_get(); + ble_drv_address_get(); return mp_const_none; } /// \method advertise() /// Bluetooth Low Energy advertise. mp_obj_t ble_obj_advertise(void) { - sd_advertise(); + ble_drv_advertise(); return mp_const_none; } diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/softdevice.c index 37200874dc..480274df5a 100644 --- a/nrf5/sdk/softdevice.c +++ b/nrf5/sdk/softdevice.c @@ -45,8 +45,8 @@ #define SD_TEST_OR_ENABLE() \ -if (sd_enabled() == 0) { \ - (void)sd_enable(); \ +if (ble_drv_stack_enabled() == 0) { \ + (void)ble_drv_stack_enable(); \ } static bool m_adv_in_progress = false; @@ -74,7 +74,7 @@ void softdevice_assert_handler(uint32_t id, uint32_t pc, uint32_t info) { BLE_DRIVER_LOG("ERROR: SoftDevice assert!!!"); } #endif -uint32_t sd_enable(void) { +uint32_t ble_drv_stack_enable(void) { #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) memset(&nrf_nvic_state, 0, sizeof(nrf_nvic_state_t)); #endif @@ -134,11 +134,11 @@ uint32_t sd_enable(void) { return err_code; } -void sd_disable(void) { +void ble_drv_stack_disable(void) { sd_softdevice_disable(); } -uint8_t sd_enabled(void) { +uint8_t ble_drv_stack_enabled(void) { uint8_t is_enabled; uint32_t err_code = sd_softdevice_is_enabled(&is_enabled); (void)err_code; @@ -148,7 +148,7 @@ uint8_t sd_enabled(void) { return is_enabled; } -void sd_address_get(void) { +void ble_drv_address_get(void) { ble_gap_addr_t local_ble_addr; #if (BLUETOOTH_SD != 132) uint32_t err_code = sd_ble_gap_address_get(&local_ble_addr); @@ -182,7 +182,7 @@ void sd_address_get(void) { #define APP_CFG_NON_CONN_ADV_TIMEOUT 0 // Disable timeout. #define NON_CONNECTABLE_ADV_INTERVAL MSEC_TO_UNITS(100, UNIT_0_625_MS) -void sd_advertise(void) { +void ble_drv_advertise(void) { ble_uuid_t adv_uuids[] = {{.uuid = EDDYSTONE_UUID, .type = BLE_UUID_TYPE_BLE}}; uint8_t encoded_size; uint8_t uuid_encoded[2]; @@ -226,7 +226,7 @@ void sd_advertise(void) { BLE_DRIVER_LOG("Advertisment start status: " UINT_FMT "\n", (uint16_t)err_code); } -bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx) { +bool ble_drv_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx) { SD_TEST_OR_ENABLE(); if (sd_ble_uuid_vs_add((ble_uuid128_t const *)p_uuid, idx) != 0) { @@ -237,7 +237,7 @@ bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx) { return true; } -bool sd_service_add(ubluepy_service_obj_t * p_service_obj) { +bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj) { SD_TEST_OR_ENABLE(); if (p_service_obj->p_uuid->type > BLE_UUID_TYPE_BLE) { @@ -270,7 +270,7 @@ bool sd_service_add(ubluepy_service_obj_t * p_service_obj) { return true; } -bool sd_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj) { +bool ble_drv_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj) { ble_gatts_char_md_t char_md; ble_gatts_attr_md_t cccd_md; ble_gatts_attr_t attr_char_value; @@ -334,7 +334,7 @@ bool sd_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj) { return true; } -bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { +bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { SD_TEST_OR_ENABLE(); uint8_t byte_pos = 0; @@ -457,7 +457,7 @@ bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params) { return true; } -void sd_gap_event_handler_set(mp_obj_t obj, ubluepy_gap_evt_callback_t evt_handler) { +void ble_drv_gap_event_handler_set(mp_obj_t obj, ubluepy_gap_evt_callback_t evt_handler) { mp_observer = obj; ubluepy_gap_event_handler = evt_handler; } diff --git a/nrf5/sdk/softdevice.h b/nrf5/sdk/softdevice.h index f3311c8054..5fdb675fad 100644 --- a/nrf5/sdk/softdevice.h +++ b/nrf5/sdk/softdevice.h @@ -32,24 +32,24 @@ #include "modubluepy.h" -uint32_t sd_enable(void); +uint32_t ble_drv_stack_enable(void); -void sd_disable(void); +void ble_drv_stack_disable(void); -uint8_t sd_enabled(void); +uint8_t ble_drv_stack_enabled(void); -void sd_address_get(void); +void ble_drv_address_get(void); -void sd_advertise(void); +void ble_drv_advertise(void); -bool sd_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx); +bool ble_drv_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx); -bool sd_service_add(ubluepy_service_obj_t * p_service_obj); +bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj); -bool sd_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj); +bool ble_drv_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj); -bool sd_advertise_data(ubluepy_advertise_data_t * p_adv_params); +bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params); -void sd_gap_event_handler_set(mp_obj_t obs, ubluepy_gap_evt_callback_t evt_handler); +void ble_drv_gap_event_handler_set(mp_obj_t obs, ubluepy_gap_evt_callback_t evt_handler); #endif // BLUETOOTH_LE_DRIVER_H__ From 793cf991ade96367954e139b62a42f3e8e8edc08 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 17 Feb 2017 19:06:11 +0100 Subject: [PATCH 369/809] nrf5/sdk: renaming softdevice.* to ble_drv.* --- nrf5/sdk/{softdevice.c => ble_drv.c} | 0 nrf5/sdk/{softdevice.h => ble_drv.h} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/sdk/{softdevice.c => ble_drv.c} (100%) rename nrf5/sdk/{softdevice.h => ble_drv.h} (100%) diff --git a/nrf5/sdk/softdevice.c b/nrf5/sdk/ble_drv.c similarity index 100% rename from nrf5/sdk/softdevice.c rename to nrf5/sdk/ble_drv.c diff --git a/nrf5/sdk/softdevice.h b/nrf5/sdk/ble_drv.h similarity index 100% rename from nrf5/sdk/softdevice.h rename to nrf5/sdk/ble_drv.h From 21f1d8c640263f5f0848bfb8e961ea97d43fb23c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 17 Feb 2017 19:10:24 +0100 Subject: [PATCH 370/809] nrf5: Updating all includes of softdevice.h to ble_drv.h --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 2 +- nrf5/modules/ubluepy/ubluepy_service.c | 2 +- nrf5/modules/ubluepy/ubluepy_uuid.c | 2 +- nrf5/sdk/ble_drv.c | 2 +- nrf5/sdk/modble.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 285132964c..6150113237 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -31,7 +31,7 @@ #if MICROPY_PY_UBLUEPY -#include "softdevice.h" +#include "ble_drv.h" STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_peripheral_obj_t * self = (ubluepy_peripheral_obj_t *)o; diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index c051c59c8a..baea19f6bc 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -30,7 +30,7 @@ #if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL #include "modubluepy.h" -#include "softdevice.h" +#include "ble_drv.h" STATIC void ubluepy_service_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_service_obj_t * self = (ubluepy_service_obj_t *)o; diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index b6575cd2e5..2bb6894e34 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -32,7 +32,7 @@ #if MICROPY_PY_UBLUEPY #include "modubluepy.h" -#include "softdevice.h" +#include "ble_drv.h" STATIC void ubluepy_uuid_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_uuid_obj_t * self = (ubluepy_uuid_obj_t *)o; diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index 480274df5a..d91f72a6aa 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -29,7 +29,7 @@ #include #include "py/runtime.h" -#include "softdevice.h" +#include "ble_drv.h" #include "mpconfigport.h" #include "nrf_sdm.h" #include "ble_gap.h" diff --git a/nrf5/sdk/modble.c b/nrf5/sdk/modble.c index 40443a59df..358ef70830 100644 --- a/nrf5/sdk/modble.c +++ b/nrf5/sdk/modble.c @@ -32,7 +32,7 @@ #include "led.h" #include "mpconfigboard.h" -#include "softdevice.h" +#include "ble_drv.h" /// \method enable() /// Enable BLE softdevice. From 9befd776faa879ecab1c9166f22e856a580e09b0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 17 Feb 2017 19:13:49 +0100 Subject: [PATCH 371/809] nrf5/sdk: Updating sdk_common.mk with new filename of bluetooth le driver. --- nrf5/sdk/sdk_common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/sdk/sdk_common.mk b/nrf5/sdk/sdk_common.mk index da1c35e2d2..183afc1f8a 100644 --- a/nrf5/sdk/sdk_common.mk +++ b/nrf5/sdk/sdk_common.mk @@ -25,4 +25,4 @@ INC += -I./sdk SRC_C += \ sdk/modble.c \ - sdk/softdevice.c + sdk/ble_drv.c From c81b606b018d4e4555aaf970040de2347aa50d55 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 17 Feb 2017 21:47:38 +0100 Subject: [PATCH 372/809] nrf5/sdk: Adding support for adding 16-bit uuid's in advertisment packet. The services in paramter list can mix 16-bit and 128-bit. --- nrf5/sdk/ble_drv.c | 139 ++++++++++++++++++++++++++++++++------------- 1 file changed, 101 insertions(+), 38 deletions(-) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index d91f72a6aa..a98ff15935 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -375,53 +375,116 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { if (p_adv_params->num_of_services > 0) { - uint8_t size_byte_pos = byte_pos; - - // skip length byte for now, apply total length post calculation - byte_pos += BLE_ADV_LENGTH_FIELD_SIZE; - - adv_data[byte_pos] = BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE; - byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; - - uint8_t uuid_total_size = 0; - uint8_t encoded_size = 0; + bool type_16bit_present = false; + bool type_128bit_present = false; for (uint8_t i = 0; i < p_adv_params->num_of_services; i++) { ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i]; - - ble_uuid_t uuid; - uuid.type = p_service->p_uuid->uuid_vs_idx; - uuid.uuid = (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]); - - // calculate total size of uuids - if (sd_ble_uuid_encode(&uuid, &encoded_size, NULL) != 0) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can not encode UUID, to check length.")); + if (p_service->p_uuid->type == UBLUEPY_UUID_16_BIT) { + type_16bit_present = true; } - // do encoding into the adv buffer - if (sd_ble_uuid_encode(&uuid, &encoded_size, &adv_data[byte_pos]) != 0) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can encode UUID into the advertisment packet.")); + if (p_service->p_uuid->type == UBLUEPY_UUID_128_BIT) { + type_128bit_present = true; } - - BLE_DRIVER_LOG("encoded uuid for service %u: ", 0); - for (uint8_t j = 0; j < encoded_size; j++) { - BLE_DRIVER_LOG(HEX2_FMT " ", adv_data[byte_pos + j]); - } - BLE_DRIVER_LOG("\n"); - - uuid_total_size += encoded_size; // size of entry - byte_pos += encoded_size; // relative to adv data packet - BLE_DRIVER_LOG("ADV: uuid size: %u, type: %u, uuid: %u, vs_idx: %u\n", - encoded_size, p_service->p_uuid->type, - (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]), - p_service->p_uuid->uuid_vs_idx); } - adv_data[size_byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + uuid_total_size); - } + if (type_16bit_present) { + uint8_t size_byte_pos = byte_pos; + // skip length byte for now, apply total length post calculation + byte_pos += BLE_ADV_LENGTH_FIELD_SIZE; + + adv_data[byte_pos] = BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE; + byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; + + uint8_t uuid_total_size = 0; + uint8_t encoded_size = 0; + + for (uint8_t i = 0; i < p_adv_params->num_of_services; i++) { + ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i]; + + ble_uuid_t uuid; + uuid.type = p_service->p_uuid->type; + uuid.uuid = (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]); + + // calculate total size of uuids + if (sd_ble_uuid_encode(&uuid, &encoded_size, NULL) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not encode UUID, to check length.")); + } + + // do encoding into the adv buffer + if (sd_ble_uuid_encode(&uuid, &encoded_size, &adv_data[byte_pos]) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can encode UUID into the advertisment packet.")); + } + + BLE_DRIVER_LOG("encoded uuid for service %u: ", 0); + for (uint8_t j = 0; j < encoded_size; j++) { + BLE_DRIVER_LOG(HEX2_FMT " ", adv_data[byte_pos + j]); + } + BLE_DRIVER_LOG("\n"); + + uuid_total_size += encoded_size; // size of entry + byte_pos += encoded_size; // relative to adv data packet + BLE_DRIVER_LOG("ADV: uuid size: %u, type: %u, uuid: %u, vs_idx: %u\n", + encoded_size, p_service->p_uuid->type, + (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]), + p_service->p_uuid->uuid_vs_idx); + } + + adv_data[size_byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + uuid_total_size); + } + + if (type_128bit_present) { + uint8_t size_byte_pos = byte_pos; + + // skip length byte for now, apply total length post calculation + byte_pos += BLE_ADV_LENGTH_FIELD_SIZE; + + adv_data[byte_pos] = BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE; + byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE; + + uint8_t uuid_total_size = 0; + uint8_t encoded_size = 0; + + for (uint8_t i = 0; i < p_adv_params->num_of_services; i++) { + ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i]; + + ble_uuid_t uuid; + uuid.type = p_service->p_uuid->uuid_vs_idx; + uuid.uuid = (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]); + + // calculate total size of uuids + if (sd_ble_uuid_encode(&uuid, &encoded_size, NULL) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not encode UUID, to check length.")); + } + + // do encoding into the adv buffer + if (sd_ble_uuid_encode(&uuid, &encoded_size, &adv_data[byte_pos]) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can encode UUID into the advertisment packet.")); + } + + BLE_DRIVER_LOG("encoded uuid for service %u: ", 0); + for (uint8_t j = 0; j < encoded_size; j++) { + BLE_DRIVER_LOG(HEX2_FMT " ", adv_data[byte_pos + j]); + } + BLE_DRIVER_LOG("\n"); + + uuid_total_size += encoded_size; // size of entry + byte_pos += encoded_size; // relative to adv data packet + BLE_DRIVER_LOG("ADV: uuid size: %u, type: %u, uuid: %u, vs_idx: %u\n", + encoded_size, p_service->p_uuid->type, + (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]), + p_service->p_uuid->uuid_vs_idx); + } + + adv_data[size_byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + uuid_total_size); + } + } // scan response data not set if (sd_ble_gap_adv_data_set(adv_data, byte_pos, NULL, 0) != 0) { From f0f6ad20b2eac281abe89675afb686a4f4e6d0b3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 17 Feb 2017 21:50:50 +0100 Subject: [PATCH 373/809] nrf5/modules: Updating example in ubluepy header with 16-bit uuid's commented out, to show usage. --- nrf5/modules/ubluepy/modubluepy.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index c6bec69825..1d8a19e4c1 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -50,9 +50,12 @@ def event_handler(id, conn_handle, length, data): # disconnect LED(2).off() +# u0 = UUID("0x180D") # HRM service +# u1 = UUID("0x2A37") # HRM measurement + u0 = UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e") -s = Service(u0) u1 = UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e") +s = Service(u0) c = Characteristic(u1) s.addCharacteristic(c) p = Peripheral() From af2f32ed6aae4eae8ec54856f8af20eb50bd2118 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 00:11:10 +0100 Subject: [PATCH 374/809] nrf5/modules: Adding constants class to ubluepy which will contain easy access to common bluetooth le numbers and definitions for the bluetooth stack. --- nrf5/Makefile | 1 + nrf5/modules/ubluepy/modubluepy.c | 2 + nrf5/modules/ubluepy/modubluepy.h | 6 +-- nrf5/modules/ubluepy/ubluepy_constants.c | 50 ++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 3 deletions(-) create mode 100644 nrf5/modules/ubluepy/ubluepy_constants.c diff --git a/nrf5/Makefile b/nrf5/Makefile index d7aeb43984..8db2e706ec 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -172,6 +172,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ ubluepy/ubluepy_characteristic.c \ ubluepy/ubluepy_uuid.c \ ubluepy/ubluepy_delegate.c \ + ubluepy/ubluepy_constants.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/modules/ubluepy/modubluepy.c b/nrf5/modules/ubluepy/modubluepy.c index cd1aa6250a..ea1b93c6ca 100644 --- a/nrf5/modules/ubluepy/modubluepy.c +++ b/nrf5/modules/ubluepy/modubluepy.c @@ -33,6 +33,7 @@ extern const mp_obj_type_t ubluepy_service_type; extern const mp_obj_type_t ubluepy_uuid_type; extern const mp_obj_type_t ubluepy_characteristic_type; extern const mp_obj_type_t ubluepy_delegate_type; +extern const mp_obj_type_t ubluepy_constants_type; STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy) }, @@ -52,6 +53,7 @@ STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_UUID), (mp_obj_t)&ubluepy_uuid_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_Service), (mp_obj_t)&ubluepy_service_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_Characteristic), (mp_obj_t)&ubluepy_characteristic_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_constants), (mp_obj_t)&ubluepy_constants_type }, #if MICROPY_PY_UBLUEPY_DESCRIPTOR { MP_OBJ_NEW_QSTR(MP_QSTR_Descriptor), (mp_obj_t)&ubluepy_descriptor_type }, #endif diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 1d8a19e4c1..aa5abbd72a 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -37,16 +37,16 @@ p.advertise(device_name="MicroPython") DB setup: -from ubluepy import Service, Characteristic, UUID, Peripheral +from ubluepy import Service, Characteristic, UUID, Peripheral, constants from pyb import LED def event_handler(id, conn_handle, length, data): print("BLE event:", id, "conn_handle:", conn_handle, "length:", length) - if id == 16: + if id == constants.EVT_GAP_CONNECTED: # connected LED(2).on() - elif id == 17: + elif id == constants.EVT_GAP_DISCONNECTED: # disconnect LED(2).off() diff --git a/nrf5/modules/ubluepy/ubluepy_constants.c b/nrf5/modules/ubluepy/ubluepy_constants.c new file mode 100644 index 0000000000..6e50439fb5 --- /dev/null +++ b/nrf5/modules/ubluepy/ubluepy_constants.c @@ -0,0 +1,50 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/runtime.h" + +#if MICROPY_PY_UBLUEPY + +#include "modubluepy.h" + +STATIC const mp_map_elem_t ubluepy_constants_locals_dict_table[] = { +#if (BLUETOOTH_SD == 132) + // GAP events + { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_OBJ_NEW_SMALL_INT(0x16) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_OBJ_NEW_SMALL_INT(0x17) }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_locals_dict, ubluepy_constants_locals_dict_table); + +const mp_obj_type_t ubluepy_constants_type = { + { &mp_type_type }, + .name = MP_QSTR_constants, + .locals_dict = (mp_obj_t)&ubluepy_constants_locals_dict +}; + +#endif // MICROPY_PY_UBLUEPY From e0fc8b88c1f3f01179ec3363fa4ff1359c1abf46 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 01:17:57 +0100 Subject: [PATCH 375/809] nrf5/modules: adding template functions for characteristic read and write. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index bca1b184b1..2150eb5f00 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -69,10 +69,35 @@ STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_ return MP_OBJ_FROM_PTR(s); } +/// \method read() +/// Read Characteristic value. +/// +STATIC mp_obj_t char_read(mp_obj_t self_in) { + ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); + (void)self; + // ble_drv_characteristic_read(); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_read_obj, char_read); + +/// \method write(data) +/// Write Characteristic value. +/// +STATIC mp_obj_t char_write(mp_obj_t self_in, mp_obj_t data) { + ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); + (void)self; + // ble_drv_characteristic_write(); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_characteristic_write_obj, char_write); + + STATIC const mp_map_elem_t ubluepy_characteristic_locals_dict_table[] = { -#if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)(&ubluepy_characteristic_read_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_write), (mp_obj_t)(&ubluepy_characteristic_write_obj) }, +#if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_supportsRead), (mp_obj_t)(&ubluepy_characteristic_supports_read_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_propertiesToString), (mp_obj_t)(&ubluepy_characteristic_properties_to_str_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getHandle), (mp_obj_t)(&ubluepy_characteristic_get_handle_obj) }, From 292c15bf1a592630a5d4475839960080fecfa944 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 01:19:43 +0100 Subject: [PATCH 376/809] nrf5/modules: Shuffle order of typedef in ubluepy header. Adding service pointer in characteristic object. Adding peripheral pointer to the service structure. When populated, the characteristic would get access to conn_handle and service handle through pointers. Also service would get access to peripheral instance. --- nrf5/modules/ubluepy/modubluepy.h | 45 ++++++++++++++++--------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index aa5abbd72a..f5bcc9835d 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -61,6 +61,7 @@ s.addCharacteristic(c) p = Peripheral() p.setConnectionHandler(event_handler) p.advertise(device_name="micr", services=[s]) + */ #include "py/obj.h" @@ -85,27 +86,6 @@ typedef struct _ubluepy_uuid_obj_t { uint8_t uuid_vs_idx; } ubluepy_uuid_obj_t; -typedef struct _ubluepy_service_obj_t { - mp_obj_base_t base; - uint16_t handle; - uint8_t type; - ubluepy_uuid_obj_t * p_uuid; -} ubluepy_service_obj_t; - -typedef struct _ubluepy_characteristic_obj_t { - mp_obj_base_t base; - uint16_t handle; - ubluepy_uuid_obj_t * p_uuid; - uint16_t service_handle; - uint16_t user_desc_handle; - uint16_t cccd_handle; - uint16_t sccd_handle; -} ubluepy_characteristic_obj_t; - -typedef struct _ubluepy_delegate_obj_t { - mp_obj_base_t base; -} ubluepy_delegate_obj_t; - typedef struct _ubluepy_peripheral_obj_t { mp_obj_base_t base; uint16_t conn_handle; @@ -114,6 +94,29 @@ typedef struct _ubluepy_peripheral_obj_t { mp_obj_t conn_handler; } ubluepy_peripheral_obj_t; +typedef struct _ubluepy_service_obj_t { + mp_obj_base_t base; + uint16_t handle; + uint8_t type; + ubluepy_uuid_obj_t * p_uuid; + ubluepy_peripheral_obj_t * p_periph; +} ubluepy_service_obj_t; + +typedef struct _ubluepy_characteristic_obj_t { + mp_obj_base_t base; + uint16_t handle; + ubluepy_uuid_obj_t * p_uuid; + uint16_t service_handle; + uint16_t user_desc_handle; + uint16_t cccd_handle; + uint16_t sccd_handle; + ubluepy_service_obj_t * p_service; +} ubluepy_characteristic_obj_t; + +typedef struct _ubluepy_delegate_obj_t { + mp_obj_base_t base; +} ubluepy_delegate_obj_t; + typedef struct _ubluepy_advertise_data_t { uint8_t * p_device_name; uint8_t device_name_len; From f5324060cc3f54a5bcf6bde1460d2e18baca2f03 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 13:07:00 +0100 Subject: [PATCH 377/809] nrf5/modules: Correcting event id numbers for connect and disconnect event in ubluepy_constants.py --- nrf5/modules/ubluepy/ubluepy_constants.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_constants.c b/nrf5/modules/ubluepy/ubluepy_constants.c index 6e50439fb5..922ab21fa2 100644 --- a/nrf5/modules/ubluepy/ubluepy_constants.c +++ b/nrf5/modules/ubluepy/ubluepy_constants.c @@ -34,8 +34,8 @@ STATIC const mp_map_elem_t ubluepy_constants_locals_dict_table[] = { #if (BLUETOOTH_SD == 132) // GAP events - { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_OBJ_NEW_SMALL_INT(0x16) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_OBJ_NEW_SMALL_INT(0x17) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_OBJ_NEW_SMALL_INT(16) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_OBJ_NEW_SMALL_INT(17) }, #endif }; From f3d8fc830e2987185782c42cf8b9a7ffbb805a68 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 13:10:59 +0100 Subject: [PATCH 378/809] nrf5/modules: Updating print to also include peripheral's connection handle. Setting pointer to service parent instance to NULL. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index 2150eb5f00..cf71a226c2 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -34,7 +34,8 @@ STATIC void ubluepy_characteristic_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_characteristic_obj_t * self = (ubluepy_characteristic_obj_t *)o; - mp_printf(print, "Characteristic(handle: 0x" HEX2_FMT ")", self->handle); + mp_printf(print, "Characteristic(handle: 0x" HEX2_FMT ", conn_handle: " HEX2_FMT ")", + self->handle, self->p_service->p_periph->conn_handle); } STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { @@ -66,6 +67,9 @@ STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_ "Invalid UUID parameter")); } + // clear pointer to service + s->p_service = NULL; + return MP_OBJ_FROM_PTR(s); } From f956947c2340ab6ebaf7bae475384981b55f6a0d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 13:15:08 +0100 Subject: [PATCH 379/809] nrf5/modules: Updating service object to clear pointer to parent peripheral instance. Also assinging pointer to the service when adding a new characteristic. --- nrf5/modules/ubluepy/ubluepy_service.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index baea19f6bc..d7e6095f07 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -78,6 +78,9 @@ STATIC mp_obj_t ubluepy_service_make_new(const mp_obj_type_t *type, size_t n_arg "Invalid UUID parameter")); } + // clear reference to peripheral + s->p_periph = NULL; + return MP_OBJ_FROM_PTR(s); } @@ -92,6 +95,10 @@ STATIC mp_obj_t service_add_characteristic(mp_obj_t self_in, mp_obj_t characteri bool retval = ble_drv_characteristic_add(p_char); + if (retval) { + p_char->p_service = self; + } + return mp_obj_new_bool(retval); } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_service_add_char_obj, service_add_characteristic); From 04f8891dc9d7347dec9a8e54d9c9171f3760c826 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 13:17:31 +0100 Subject: [PATCH 380/809] nrf5/modules: Updating peripheral class to assign periopheral parent pointer to service's thats added. Also added a hook in the bluetooth le event handler to store the connection handle value, to prevent any services or characteristics to handle this value themselves. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 6150113237..267a87a0f3 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -42,6 +42,12 @@ STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_pri STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data) { ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (event_id == 16) { // connect event + self->conn_handle = conn_handle; + } else if (event_id == 17) { // disconnect event + self->conn_handle = 0xFFFF; // invalid connection handle + } + if (self->conn_handler != mp_const_none) { mp_obj_t args[4]; mp_uint_t num_of_args = 4; @@ -190,10 +196,11 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_disconnect_obj, peripheral_d /// \method addService(Service) /// Add service to the Peripheral. /// -STATIC mp_obj_t peripheral_add_service(mp_obj_t self_in, mp_obj_t uuid) { - ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); +STATIC mp_obj_t peripheral_add_service(mp_obj_t self_in, mp_obj_t service) { + ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); + ubluepy_service_obj_t * p_service = MP_OBJ_TO_PTR(service); - (void)self; + p_service->p_periph = self; return mp_const_none; } From f800f22a79af6aa34ab48b318f926753d8f85af3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 13:20:03 +0100 Subject: [PATCH 381/809] nrf5/modules: Updating ubluepy example in the header file with new function call to add service to a peripheral instance. --- nrf5/modules/ubluepy/modubluepy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index f5bcc9835d..1d2c15469f 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -59,6 +59,7 @@ s = Service(u0) c = Characteristic(u1) s.addCharacteristic(c) p = Peripheral() +p.addService(s) p.setConnectionHandler(event_handler) p.advertise(device_name="micr", services=[s]) From 852dde6747201417100e60503834d07fe45b18ca Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 14:41:46 +0100 Subject: [PATCH 382/809] nrf5/modules: Removing connection handle from python gap event handler callback function. --- nrf5/modules/ubluepy/modubluepy.h | 4 ++-- nrf5/modules/ubluepy/ubluepy_peripheral.c | 11 +++++------ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 1d2c15469f..fc8aca5b8f 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -40,8 +40,8 @@ DB setup: from ubluepy import Service, Characteristic, UUID, Peripheral, constants from pyb import LED -def event_handler(id, conn_handle, length, data): - print("BLE event:", id, "conn_handle:", conn_handle, "length:", length) +def event_handler(id, length, data): + print("BLE event:", id, "length:", length) if id == constants.EVT_GAP_CONNECTED: # connected diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 267a87a0f3..9e8372dd6a 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -49,15 +49,14 @@ STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn } if (self->conn_handler != mp_const_none) { - mp_obj_t args[4]; - mp_uint_t num_of_args = 4; + mp_obj_t args[3]; + mp_uint_t num_of_args = 3; args[0] = MP_OBJ_NEW_SMALL_INT(event_id); - args[1] = MP_OBJ_NEW_SMALL_INT(conn_handle); - args[2] = MP_OBJ_NEW_SMALL_INT(length); + args[1] = MP_OBJ_NEW_SMALL_INT(length); if (data != NULL) { - args[3] = mp_obj_new_bytearray_by_ref(length, data); + args[2] = mp_obj_new_bytearray_by_ref(length, data); } else { - args[3] = mp_const_none; + args[2] = mp_const_none; } // for now hard-code all events to conn_handler From 8ffd167d4b852a8b5ac55d0aab926905b1dfd709 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 17:54:47 +0100 Subject: [PATCH 383/809] nrf5/modules: Adding new members in ubluepy peripheral and service object to keep track of child elements. Peripheral will have a list of services, and service will have a list of charactaristics. --- nrf5/modules/ubluepy/modubluepy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index fc8aca5b8f..bfb4e59b21 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -93,6 +93,7 @@ typedef struct _ubluepy_peripheral_obj_t { mp_obj_t delegate; mp_obj_t notif_handler; mp_obj_t conn_handler; + mp_obj_t service_list; } ubluepy_peripheral_obj_t; typedef struct _ubluepy_service_obj_t { @@ -101,6 +102,7 @@ typedef struct _ubluepy_service_obj_t { uint8_t type; ubluepy_uuid_obj_t * p_uuid; ubluepy_peripheral_obj_t * p_periph; + mp_obj_t char_list; } ubluepy_service_obj_t; typedef struct _ubluepy_characteristic_obj_t { From 577bf0724a0002608259227a36246fa9a8017838 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 17:57:10 +0100 Subject: [PATCH 384/809] nrf5/modules: Updating ubluepy peripheral. Creating empty service list in constructor. Appending services to the list when added. Added new function for retreiving the service list; getServices(). --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 9e8372dd6a..6428d171a8 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -28,6 +28,7 @@ #include "py/obj.h" #include "py/runtime.h" #include "py/objstr.h" +#include "py/objlist.h" #if MICROPY_PY_UBLUEPY @@ -91,6 +92,8 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ s->notif_handler = mp_const_none; s->conn_handle = 0xFFFF; + s->service_list = mp_obj_new_list(0, NULL); + return MP_OBJ_FROM_PTR(s); } @@ -201,20 +204,31 @@ STATIC mp_obj_t peripheral_add_service(mp_obj_t self_in, mp_obj_t service) { p_service->p_periph = self; + mp_obj_list_append(self->service_list, service); + return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_add_service_obj, peripheral_add_service); +/// \method disconnect() +/// disconnect connection. +/// +STATIC mp_obj_t peripheral_get_services(mp_obj_t self_in) { + ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); + + return self->service_list; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_get_services_obj, peripheral_get_services); STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_setNotificationHandler), (mp_obj_t)(&ubluepy_peripheral_set_notif_handler_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_setConnectionHandler), (mp_obj_t)(&ubluepy_peripheral_set_conn_handler_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, #if MICROPY_PY_UBLUEPY_CENTRAL { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getServiceByUUID), (mp_obj_t)(&ubluepy_peripheral_get_service_by_uuid_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_peripheral_get_chars_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getDescriptors), (mp_obj_t)(&ubluepy_peripheral_get_descs_obj) }, From 63ed32ecaa368991085649c9437c31fd9d9dacd6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 17:57:59 +0100 Subject: [PATCH 385/809] nrf5/modules: Correcting tabbing in ubluepy periheral impl. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 6428d171a8..6ea6081a5e 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -223,8 +223,8 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_get_services_obj, peripheral STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setNotificationHandler), (mp_obj_t)(&ubluepy_peripheral_set_notif_handler_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setConnectionHandler), (mp_obj_t)(&ubluepy_peripheral_set_conn_handler_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setNotificationHandler), (mp_obj_t)(&ubluepy_peripheral_set_notif_handler_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_setConnectionHandler), (mp_obj_t)(&ubluepy_peripheral_set_conn_handler_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, #if MICROPY_PY_UBLUEPY_CENTRAL { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, From 15d7353cb3b5d5409c451c3fb1099425b5981426 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 17:59:10 +0100 Subject: [PATCH 386/809] nrf5/modules: Changed return in ubluepy addService() function to return mp_const_none instead of boolean. --- nrf5/modules/ubluepy/ubluepy_service.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index d7e6095f07..63db27a73b 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -99,7 +99,8 @@ STATIC mp_obj_t service_add_characteristic(mp_obj_t self_in, mp_obj_t characteri p_char->p_service = self; } - return mp_obj_new_bool(retval); + // return mp_obj_new_bool(retval); + return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_service_add_char_obj, service_add_characteristic); From 1da82b2aeba3410646c360b6ff79892b3ee1c468 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 18:06:58 +0100 Subject: [PATCH 387/809] nrf5/modules: Updating ubluepy service. Creating empty characteristic list in constructor. Appending characteristic to the list when added. --- nrf5/modules/ubluepy/ubluepy_service.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 63db27a73b..8f47551394 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -26,6 +26,7 @@ #include "py/obj.h" #include "py/runtime.h" +#include "py/objlist.h" #if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL @@ -80,6 +81,7 @@ STATIC mp_obj_t ubluepy_service_make_new(const mp_obj_type_t *type, size_t n_arg // clear reference to peripheral s->p_periph = NULL; + s->char_list = mp_obj_new_list(0, NULL); return MP_OBJ_FROM_PTR(s); } @@ -99,6 +101,8 @@ STATIC mp_obj_t service_add_characteristic(mp_obj_t self_in, mp_obj_t characteri p_char->p_service = self; } + mp_obj_list_append(self->char_list, characteristic); + // return mp_obj_new_bool(retval); return mp_const_none; } From 307c2d6aedf1bbe4978e1d67a70aa86a39eab20e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 18:12:37 +0100 Subject: [PATCH 388/809] nrf5/modules: Updating method documentation in ubluepy peripheral class. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 6ea6081a5e..841f8ab79b 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -196,7 +196,7 @@ STATIC mp_obj_t peripheral_disconnect(mp_obj_t self_in) { STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_disconnect_obj, peripheral_disconnect); /// \method addService(Service) -/// Add service to the Peripheral. +/// Get all service registered in the Peripheral. /// STATIC mp_obj_t peripheral_add_service(mp_obj_t self_in, mp_obj_t service) { ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); @@ -210,7 +210,7 @@ STATIC mp_obj_t peripheral_add_service(mp_obj_t self_in, mp_obj_t service) { } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_add_service_obj, peripheral_add_service); -/// \method disconnect() +/// \method getServices() /// disconnect connection. /// STATIC mp_obj_t peripheral_get_services(mp_obj_t self_in) { From 655d6c9bcd0a2b1e4201fcdf428fd15a7a9f805e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 18:14:27 +0100 Subject: [PATCH 389/809] nrf5/modules: Adding new method, getCharacteristics(), in the ubluepy service class. The method returns the list of characteristics which has been added to the service instance. --- nrf5/modules/ubluepy/ubluepy_service.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 8f47551394..be9a799cec 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -108,11 +108,23 @@ STATIC mp_obj_t service_add_characteristic(mp_obj_t self_in, mp_obj_t characteri } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_service_add_char_obj, service_add_characteristic); +/// \method getCharacteristics() +/// Return list with all characteristics registered in the Service. +/// +STATIC mp_obj_t service_get_chars(mp_obj_t self_in) { + ubluepy_service_obj_t * self = MP_OBJ_TO_PTR(self_in); + + return self->char_list; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_service_get_chars_obj, service_get_chars); + + STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristic), (mp_obj_t)(&ubluepy_service_get_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristic), (mp_obj_t)(&ubluepy_service_get_char_obj) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_service_add_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_service_add_char_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_service_get_chars_obj) }, #if 0 // Properties { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_service_get_peripheral_obj) }, From 71475bb028c60357d045eea3ce0ce612cbec0c3d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 18:16:07 +0100 Subject: [PATCH 390/809] nrf5/modules: Updating method documentation in ubluepy peripheral and service. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 4 ++-- nrf5/modules/ubluepy/ubluepy_service.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 841f8ab79b..3b82de9d48 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -196,7 +196,7 @@ STATIC mp_obj_t peripheral_disconnect(mp_obj_t self_in) { STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_disconnect_obj, peripheral_disconnect); /// \method addService(Service) -/// Get all service registered in the Peripheral. +/// Add service to the Peripheral. /// STATIC mp_obj_t peripheral_add_service(mp_obj_t self_in, mp_obj_t service) { ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); @@ -211,7 +211,7 @@ STATIC mp_obj_t peripheral_add_service(mp_obj_t self_in, mp_obj_t service) { STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_add_service_obj, peripheral_add_service); /// \method getServices() -/// disconnect connection. +/// Return list with all service registered in the Peripheral. /// STATIC mp_obj_t peripheral_get_services(mp_obj_t self_in) { ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index be9a799cec..1ff5808233 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -86,7 +86,7 @@ STATIC mp_obj_t ubluepy_service_make_new(const mp_obj_type_t *type, size_t n_arg return MP_OBJ_FROM_PTR(s); } -/// \method addCharacteristic(Service) +/// \method addCharacteristic(Characteristic) /// Add Characteristic to the Service. /// STATIC mp_obj_t service_add_characteristic(mp_obj_t self_in, mp_obj_t characteristic) { From 9a08ed1a0878b94db9bde06fbf8d74b09a40035b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 18:38:31 +0100 Subject: [PATCH 391/809] nrf5/modules: Adding getCharacteristic method in ublupy service class. This function returns the characteristic with the given UUID if found, else None. The UUID parameter has to be of UUID class type, any other value, like strings will throw an exception. --- nrf5/modules/ubluepy/ubluepy_service.c | 34 ++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 1ff5808233..6400492cc3 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -118,11 +118,41 @@ STATIC mp_obj_t service_get_chars(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_service_get_chars_obj, service_get_chars); +/// \method getCharacteristic(UUID) +/// Return Characteristic with the given UUID. +/// +STATIC mp_obj_t service_get_characteristic(mp_obj_t self_in, mp_obj_t uuid) { + ubluepy_service_obj_t * self = MP_OBJ_TO_PTR(self_in); + ubluepy_uuid_obj_t * p_uuid = MP_OBJ_TO_PTR(uuid); + + // validate that there is an UUID object passed in as parameter + if (!(MP_OBJ_IS_TYPE(uuid, &ubluepy_uuid_type))) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Invalid UUID parameter")); + } + + mp_obj_t * chars = NULL; + mp_uint_t num_chars = 0; + mp_obj_get_array(self->char_list, &num_chars, &chars); + + for (uint8_t i = 0; i < num_chars; i++) { + ubluepy_characteristic_obj_t * p_char = (ubluepy_characteristic_obj_t *)chars[i]; + + bool type_match = p_char->p_uuid->type == p_uuid->type; + bool uuid_match = ((uint16_t)(*(uint16_t *)&p_char->p_uuid->value[0]) == + (uint16_t)(*(uint16_t *)&p_uuid->value[0])); + + if (type_match && uuid_match) { + return MP_OBJ_FROM_PTR(p_char); + } + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_service_get_char_obj, service_get_characteristic); STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { -#if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristic), (mp_obj_t)(&ubluepy_service_get_char_obj) }, -#endif { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_service_add_char_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_service_get_chars_obj) }, #if 0 From 98358e4400ff94a915893ff7f2d7e0dbb70ddecd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 21:11:39 +0100 Subject: [PATCH 392/809] nrf5/sdk: Adding template functions for attribute read/write/notify in bluetooth le driver. --- nrf5/sdk/ble_drv.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++ nrf5/sdk/ble_drv.h | 6 ++++++ 2 files changed, 59 insertions(+) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index a98ff15935..ecf565c864 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -520,6 +520,59 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { return true; } +void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { + ble_gatts_value_t gatts_value; + memset(&gatts_value, 0, sizeof(gatts_value)); + + gatts_value.len = len; + gatts_value.offset = 0; + gatts_value.p_value = p_data; + + uint32_t err_code = sd_ble_gatts_value_get(conn_handle, + handle, + &gatts_value); + if (err_code != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not read attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); + } + +} +void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { + ble_gatts_value_t gatts_value; + memset(&gatts_value, 0, sizeof(gatts_value)); + + gatts_value.len = len; + gatts_value.offset = 0; + gatts_value.p_value = p_data; + + uint32_t err_code = sd_ble_gatts_value_set(conn_handle, handle, &gatts_value); + + if (err_code != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not write attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); + } +} + +void ble_drv_attr_notif(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { + uint16_t hvx_len = len; + ble_gatts_hvx_params_t hvx_params; + + memset(&hvx_params, 0, sizeof(hvx_params)); + + hvx_params.handle = handle; + hvx_params.type = BLE_GATT_HVX_NOTIFICATION; + hvx_params.offset = 0; + hvx_params.p_len = &hvx_len; + hvx_params.p_data = p_data; + + uint32_t err_code = sd_ble_gatts_hvx(conn_handle, &hvx_params); + + if (err_code != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not notify attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); + } +} + void ble_drv_gap_event_handler_set(mp_obj_t obj, ubluepy_gap_evt_callback_t evt_handler) { mp_observer = obj; ubluepy_gap_event_handler = evt_handler; diff --git a/nrf5/sdk/ble_drv.h b/nrf5/sdk/ble_drv.h index 5fdb675fad..7fbef8bd67 100644 --- a/nrf5/sdk/ble_drv.h +++ b/nrf5/sdk/ble_drv.h @@ -52,4 +52,10 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params); void ble_drv_gap_event_handler_set(mp_obj_t obs, ubluepy_gap_evt_callback_t evt_handler); +void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); + +void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); + +void ble_drv_attr_notif(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); + #endif // BLUETOOTH_LE_DRIVER_H__ From 6a374dc5a28977fa4d0c340b1980e88178960dbc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 22:48:48 +0100 Subject: [PATCH 393/809] nrf5/modules: Adding object structure for ubluepy descriptor. --- nrf5/modules/ubluepy/modubluepy.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index bfb4e59b21..24f01f49bb 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -116,6 +116,12 @@ typedef struct _ubluepy_characteristic_obj_t { ubluepy_service_obj_t * p_service; } ubluepy_characteristic_obj_t; +typedef struct _ubluepy_descriptor_obj_t { + mp_obj_base_t base; + uint16_t handle; + ubluepy_uuid_obj_t * p_uuid; +} ubluepy_descriptor_obj_t; + typedef struct _ubluepy_delegate_obj_t { mp_obj_base_t base; } ubluepy_delegate_obj_t; From 842b83cbd8f7e82d4d03bd6ba0a98309ba43f52b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 22:49:18 +0100 Subject: [PATCH 394/809] nrf5/modules: Adding template for ubluepy descriptor class implementation. --- nrf5/modules/ubluepy/ubluepy_descriptor.c | 82 +++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 nrf5/modules/ubluepy/ubluepy_descriptor.c diff --git a/nrf5/modules/ubluepy/ubluepy_descriptor.c b/nrf5/modules/ubluepy/ubluepy_descriptor.c new file mode 100644 index 0000000000..959764a327 --- /dev/null +++ b/nrf5/modules/ubluepy/ubluepy_descriptor.c @@ -0,0 +1,82 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/runtime.h" +#include "py/objstr.h" +#include "py/misc.h" + +#if MICROPY_PY_UBLUEPY + +#include "modubluepy.h" +#include "ble_drv.h" + +STATIC void ubluepy_descriptor_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + ubluepy_descriptor_obj_t * self = (ubluepy_descriptor_obj_t *)o; + + mp_printf(print, "Descriptor(uuid: 0x" HEX2_FMT HEX2_FMT ")", + self->p_uuid->value[1], self->p_uuid->value[0]); +} + +STATIC mp_obj_t ubluepy_descriptor_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + + enum { ARG_NEW_UUID }; + + static const mp_arg_t allowed_args[] = { + { ARG_NEW_UUID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + ubluepy_descriptor_obj_t * s = m_new_obj(ubluepy_descriptor_obj_t); + s->base.type = type; + + mp_obj_t uuid_obj = args[ARG_NEW_UUID].u_obj; + + (void)uuid_obj; + + return MP_OBJ_FROM_PTR(s); +} + +STATIC const mp_map_elem_t ubluepy_descriptor_locals_dict_table[] = { +#if 0 + { MP_OBJ_NEW_QSTR(MP_QSTR_binVal), (mp_obj_t)(&ubluepy_descriptor_bin_val_obj) }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_descriptor_locals_dict, ubluepy_descriptor_locals_dict_table); + +const mp_obj_type_t ubluepy_descriptor_type = { + { &mp_type_type }, + .name = MP_QSTR_Descriptor, + .print = ubluepy_descriptor_print, + .make_new = ubluepy_descriptor_make_new, + .locals_dict = (mp_obj_t)&ubluepy_descriptor_locals_dict +}; + +#endif // MICROPY_PY_UBLUEPY From 4fe4c2967f4cea86f605ea62a249115dfe6bc40d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 22:49:50 +0100 Subject: [PATCH 395/809] nrf5: Adding ubluepy_descriptor.c into source list to compile. --- nrf5/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 8db2e706ec..d39dec4f26 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -173,6 +173,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ ubluepy/ubluepy_uuid.c \ ubluepy/ubluepy_delegate.c \ ubluepy/ubluepy_constants.c \ + ubluepy/ubluepy_descriptor.c \ ) #ifeq ($(SD), ) From 45144ee8a8c22294a64eaca5caa73bf803a35b03 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 18 Feb 2017 23:10:59 +0100 Subject: [PATCH 396/809] nrf5/modules: Adding constant for CCCD uuid in ubluepy constants dict. --- nrf5/modules/ubluepy/ubluepy_constants.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/modules/ubluepy/ubluepy_constants.c b/nrf5/modules/ubluepy/ubluepy_constants.c index 922ab21fa2..4670b62272 100644 --- a/nrf5/modules/ubluepy/ubluepy_constants.c +++ b/nrf5/modules/ubluepy/ubluepy_constants.c @@ -37,6 +37,7 @@ STATIC const mp_map_elem_t ubluepy_constants_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_OBJ_NEW_SMALL_INT(16) }, { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_OBJ_NEW_SMALL_INT(17) }, #endif + { MP_OBJ_NEW_QSTR(MP_QSTR_UUID_CCCD), MP_OBJ_NEW_SMALL_INT(0x2902) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_locals_dict, ubluepy_constants_locals_dict_table); From 29b283f69745baaf68138a0b26f5e3e8f7a5fe2c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 19 Feb 2017 00:08:05 +0100 Subject: [PATCH 397/809] nrf5/sdk: Adding support for setting gatts handler in the bluetooth le driver. --- nrf5/sdk/ble_drv.c | 23 +++++++++++++++++------ nrf5/sdk/ble_drv.h | 2 ++ 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index ecf565c864..09c4b2b379 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -52,7 +52,10 @@ if (ble_drv_stack_enabled() == 0) { \ static bool m_adv_in_progress = false; static ubluepy_gap_evt_callback_t ubluepy_gap_event_handler; -static mp_obj_t mp_observer; +static ubluepy_gatts_evt_callback_t ubluepy_gatts_event_handler; + +static mp_obj_t mp_gap_observer; +static mp_obj_t mp_gatts_observer; #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -278,10 +281,8 @@ bool ble_drv_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj) { ble_gatts_attr_md_t attr_md; memset(&cccd_md, 0, sizeof(cccd_md)); - BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm); BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.write_perm); - cccd_md.vloc = BLE_GATTS_VLOC_STACK; memset(&char_md, 0, sizeof(char_md)); @@ -574,10 +575,15 @@ void ble_drv_attr_notif(uint16_t conn_handle, uint16_t handle, uint16_t len, uin } void ble_drv_gap_event_handler_set(mp_obj_t obj, ubluepy_gap_evt_callback_t evt_handler) { - mp_observer = obj; + mp_gap_observer = obj; ubluepy_gap_event_handler = evt_handler; } +void ble_drv_gatts_event_handler_set(mp_obj_t obj, ubluepy_gatts_evt_callback_t evt_handler) { + mp_gatts_observer = obj; + ubluepy_gatts_event_handler = evt_handler; +} + static void ble_evt_handler(ble_evt_t * p_ble_evt) { // S132 event ranges. // Common 0x01 -> 0x0F @@ -589,16 +595,21 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GAP_EVT_CONNECTED: BLE_DRIVER_LOG("GAP CONNECT\n"); m_adv_in_progress = false; - ubluepy_gap_event_handler(mp_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); + ubluepy_gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); break; case BLE_GAP_EVT_DISCONNECTED: BLE_DRIVER_LOG("GAP DISCONNECT\n"); - ubluepy_gap_event_handler(mp_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); + ubluepy_gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); + break; + + case BLE_GATTS_EVT_HVC: + ubluepy_gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gatts_evt.params.hvc.handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); break; case BLE_GATTS_EVT_WRITE: BLE_DRIVER_LOG("GATTS write\n"); + ubluepy_gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gatts_evt.params.write.handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); break; case BLE_GAP_EVT_CONN_PARAM_UPDATE: diff --git a/nrf5/sdk/ble_drv.h b/nrf5/sdk/ble_drv.h index 7fbef8bd67..8f8075a8c7 100644 --- a/nrf5/sdk/ble_drv.h +++ b/nrf5/sdk/ble_drv.h @@ -52,6 +52,8 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params); void ble_drv_gap_event_handler_set(mp_obj_t obs, ubluepy_gap_evt_callback_t evt_handler); +void ble_drv_gatts_event_handler_set(mp_obj_t obj, ubluepy_gatts_evt_callback_t evt_handler); + void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); From ac14bb473692f7ce0f910b74e132eaa824eafd5e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 19 Feb 2017 00:09:11 +0100 Subject: [PATCH 398/809] nrf5/modules: Adding new callback type in modubluepy for gatts events. --- nrf5/modules/ubluepy/modubluepy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 24f01f49bb..6ac0421ccf 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -134,5 +134,6 @@ typedef struct _ubluepy_advertise_data_t { } ubluepy_advertise_data_t; typedef void (*ubluepy_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); +typedef void (*ubluepy_gatts_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); #endif // UBLUEPY_H__ From 10e7c16351204dfe73273d093f9174a7b942e00b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 19 Feb 2017 00:10:27 +0100 Subject: [PATCH 399/809] nrf5/modules: Adding new gatts handler and registration of it during creation of a peripheral object. Also, added forwarding to python callback function (for now the same as for GAP). --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 3b82de9d48..a0a196913b 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -67,6 +67,26 @@ STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn (void)self; } +STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->conn_handler != mp_const_none) { + mp_obj_t args[3]; + mp_uint_t num_of_args = 3; + args[0] = MP_OBJ_NEW_SMALL_INT(event_id); + args[1] = MP_OBJ_NEW_SMALL_INT(length); + if (data != NULL) { + args[2] = mp_obj_new_bytearray_by_ref(length, data); + } else { + args[2] = mp_const_none; + } + + // for now hard-code all events to conn_handler + mp_call_function_n_kw(self->conn_handler, num_of_args, 0, args); + } + +} + STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { enum { ARG_NEW_DEVICE_ADDR, @@ -86,6 +106,7 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ s->base.type = type; ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(s), gap_event_handler); + ble_drv_gatts_event_handler_set(MP_OBJ_FROM_PTR(s), gatts_event_handler); s->delegate = mp_const_none; s->conn_handler = mp_const_none; From 486d05ff17f8fee8626e27ca26ce00041952beef Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 19 Feb 2017 19:00:31 +0100 Subject: [PATCH 400/809] nrf5/boards: Releasing more RAM for heap use in the nrf51 s110 linker script. --- nrf5/boards/nrf51822_aa_s110.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/nrf51822_aa_s110.ld b/nrf5/boards/nrf51822_aa_s110.ld index e798bf3afe..e63b50aadc 100644 --- a/nrf5/boards/nrf51822_aa_s110.ld +++ b/nrf5/boards/nrf51822_aa_s110.ld @@ -9,12 +9,12 @@ MEMORY FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */ FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 159 KiB */ - RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x002000 /* 8 KiB */ + RAM (xrw) : ORIGIN = 0x20001000, LENGTH = 0x003000 /* 12 KiB */ } /* produce a link error if there is not this amount of RAM for these sections */ _minimum_stack_size = 2K; -_minimum_heap_size = 4K; +_minimum_heap_size = 8K; /* top end of the stack */ From 7c0195da6cfd5fb9123d08826d2e29f72b7e87d4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 19 Feb 2017 19:06:12 +0100 Subject: [PATCH 401/809] nrf5/modules: Syncing uart module code after upmerge with upstream master. --- nrf5/modules/machine/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/machine/uart.c b/nrf5/modules/machine/uart.c index 98370378bb..6001ba44bf 100644 --- a/nrf5/modules/machine/uart.c +++ b/nrf5/modules/machine/uart.c @@ -439,7 +439,7 @@ const mp_obj_type_t pyb_uart_type = { .name = MP_QSTR_UART, .print = pyb_uart_print, .make_new = pyb_uart_make_new, - .getiter = mp_identity, + .getiter = mp_identity_getiter, .iternext = mp_stream_unbuffered_iter, .protocol = &uart_stream_p, .locals_dict = (mp_obj_t)&pyb_uart_locals_dict, From 89fc67a9f80ded40d712938ed9c2895eac1d4e28 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 20 Feb 2017 20:22:23 +0100 Subject: [PATCH 402/809] nrf5/modules: Adding new members to ubluepy characteristic object, props and attrs. Adding enum typedefs for various properties and attributes. --- nrf5/modules/ubluepy/modubluepy.h | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 6ac0421ccf..032c0a1990 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -55,9 +55,12 @@ def event_handler(id, length, data): u0 = UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e") u1 = UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e") +u2 = UUID("6e400003-b5a3-f393-e0a9-e50e24dcca9e") s = Service(u0) -c = Characteristic(u1) -s.addCharacteristic(c) +c0 = Characteristic(u1, props = Characteristic.PROP_BROADCAST, attrs = Characteristic.ATTR_CCCD) +c1 = Characteristic(u2) +s.addCharacteristic(c0) +s.addCharacteristic(c1) p = Peripheral() p.addService(s) p.setConnectionHandler(event_handler) @@ -113,6 +116,8 @@ typedef struct _ubluepy_characteristic_obj_t { uint16_t user_desc_handle; uint16_t cccd_handle; uint16_t sccd_handle; + uint8_t props; + uint8_t attrs; ubluepy_service_obj_t * p_service; } ubluepy_characteristic_obj_t; @@ -133,6 +138,21 @@ typedef struct _ubluepy_advertise_data_t { uint8_t num_of_services; } ubluepy_advertise_data_t; +typedef enum _ubluepy_prop_t { + UBLUEPY_PROP_BROADCAST = 0x01, + UBLUEPY_PROP_READ = 0x02, + UBLUEPY_PROP_WRITE_WO_RESP = 0x04, + UBLUEPY_PROP_WRITE = 0x08, + UBLUEPY_PROP_NOTIFY = 0x10, + UBLUEPY_PROP_INDICATE = 0x20, + UBLUEPY_PROP_AUTH_SIGNED_WR = 0x40, +} ubluepy_prop_t; + +typedef enum _ubluepy_attr_t { + UBLUEPY_ATTR_CCCD = 0x01, + UBLUEPY_ATTR_SCCD = 0x02, +} ubluepy_attr_t; + typedef void (*ubluepy_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); typedef void (*ubluepy_gatts_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); From a973dde6031ccacb21e59232946aed2b8aafe436 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 20 Feb 2017 20:24:27 +0100 Subject: [PATCH 403/809] nrf5/sdk: Adding parsing of characteristic properties and attributes (extra descriptions for the characteristic, for now cccd). --- nrf5/sdk/ble_drv.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index 09c4b2b379..89de92aee8 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -280,20 +280,34 @@ bool ble_drv_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj) { ble_uuid_t uuid; ble_gatts_attr_md_t attr_md; - memset(&cccd_md, 0, sizeof(cccd_md)); - BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm); - BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.write_perm); - cccd_md.vloc = BLE_GATTS_VLOC_STACK; - memset(&char_md, 0, sizeof(char_md)); - char_md.char_props.notify = 1; + char_md.char_props.broadcast = (p_char_obj->props & UBLUEPY_PROP_BROADCAST) ? 1 : 0; + char_md.char_props.read = (p_char_obj->props & UBLUEPY_PROP_READ) ? 1 : 0; + char_md.char_props.write_wo_resp = (p_char_obj->props & UBLUEPY_PROP_WRITE_WO_RESP) ? 1 : 0; + char_md.char_props.write = (p_char_obj->props & UBLUEPY_PROP_WRITE) ? 1 : 0; + char_md.char_props.notify = (p_char_obj->props & UBLUEPY_PROP_NOTIFY) ? 1 : 0; + char_md.char_props.indicate = (p_char_obj->props & UBLUEPY_PROP_INDICATE) ? 1 : 0; +#if 0 + char_md.char_props.auth_signed_wr = (p_char_obj->props & UBLUEPY_PROP_NOTIFY) ? 1 : 0; +#endif + + char_md.p_char_user_desc = NULL; char_md.p_char_pf = NULL; char_md.p_user_desc_md = NULL; - char_md.p_cccd_md = &cccd_md; char_md.p_sccd_md = NULL; + // if cccd + if (p_char_obj->attrs & UBLUEPY_ATTR_CCCD) { + memset(&cccd_md, 0, sizeof(cccd_md)); + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm); + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.write_perm); + cccd_md.vloc = BLE_GATTS_VLOC_STACK; + char_md.p_cccd_md = &cccd_md; + } else { + char_md.p_cccd_md = NULL; + } uuid.type = p_char_obj->p_uuid->type; uuid.uuid = (uint16_t)(*(uint16_t *)&p_char_obj->p_uuid->value[0]); From 601f07cbf249e3fb16112b6de6ed6ac0279c108e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 20 Feb 2017 20:28:19 +0100 Subject: [PATCH 404/809] nrf5/modules: Adding props and attrs parameter to ubluepy characteristic constructor to override default values. Adding method for reading characteristic properties. Adding values to the local dict table that gives possibility to OR together a configuration of properties and attributes in the keyword argument during construction. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 46 ++++++++++++++++--- 1 file changed, 39 insertions(+), 7 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index cf71a226c2..f726f9bbdb 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -39,11 +39,10 @@ STATIC void ubluepy_characteristic_print(const mp_print_t *print, mp_obj_t o, mp } STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - - enum { ARG_NEW_UUID }; - static const mp_arg_t allowed_args[] = { - { ARG_NEW_UUID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_uuid, MP_ARG_REQUIRED| MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_props, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UBLUEPY_PROP_READ | UBLUEPY_PROP_WRITE} }, + { MP_QSTR_attrs, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, }; // parse args @@ -53,9 +52,9 @@ STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_ ubluepy_characteristic_obj_t *s = m_new_obj(ubluepy_characteristic_obj_t); s->base.type = type; - mp_obj_t uuid_obj = args[ARG_NEW_UUID].u_obj; + mp_obj_t uuid_obj = args[0].u_obj; - if (uuid_obj == MP_OBJ_NULL) { + if (uuid_obj == mp_const_none) { return MP_OBJ_FROM_PTR(s); } @@ -67,6 +66,14 @@ STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_ "Invalid UUID parameter")); } + if (args[1].u_int > 0) { + s->props = (uint8_t)args[1].u_int; + } + + if (args[2].u_int > 0) { + s->attrs = (uint8_t)args[2].u_int; + } + // clear pointer to service s->p_service = NULL; @@ -98,6 +105,15 @@ STATIC mp_obj_t char_write(mp_obj_t self_in, mp_obj_t data) { STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_characteristic_write_obj, char_write); +/// \method properties() +/// Read Characteristic value properties. +/// +STATIC mp_obj_t char_properties(mp_obj_t self_in) { + ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); + return MP_OBJ_NEW_SMALL_INT(self->props); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_get_properties_obj, char_properties); + STATIC const mp_map_elem_t ubluepy_characteristic_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)(&ubluepy_characteristic_read_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_write), (mp_obj_t)(&ubluepy_characteristic_write_obj) }, @@ -109,7 +125,23 @@ STATIC const mp_map_elem_t ubluepy_characteristic_locals_dict_table[] = { // Properties { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_characteristic_get_peripheral_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_characteristic_get_uuid_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_properties), (mp_obj_t)(&ubluepy_characteristic_get_properties_obj) }, +#endif + { MP_OBJ_NEW_QSTR(MP_QSTR_properties), (mp_obj_t)(&ubluepy_characteristic_get_properties_obj) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_BROADCAST), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_BROADCAST) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_READ), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_READ) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_WRITE_WO_RESP), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_WRITE_WO_RESP) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_WRITE), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_WRITE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_NOTIFY), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_NOTIFY) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_INDICATE), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_INDICATE) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_AUTH_SIGNED_WR), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_AUTH_SIGNED_WR) }, + +#if MICROPY_PY_UBLUEPY_PERIPHERAL + { MP_OBJ_NEW_QSTR(MP_QSTR_ATTR_CCCD), MP_OBJ_NEW_SMALL_INT(UBLUEPY_ATTR_CCCD) }, +#endif + +#if MICROPY_PY_UBLUEPY_CENTRAL + { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_AUTH_SIGNED_WR), MP_OBJ_NEW_SMALL_INT(UBLUEPY_ATTR_SCCD) }, #endif }; From 7223950864868d85e94255c7fb7cce8707df31c1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 20 Feb 2017 21:26:19 +0100 Subject: [PATCH 405/809] nrf5/sdk: Remaning bluetooth driver function ble_drv_attr_notif to *_notify. --- nrf5/sdk/ble_drv.c | 3 ++- nrf5/sdk/ble_drv.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index 89de92aee8..abedf2936b 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -552,6 +552,7 @@ void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint } } + void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { ble_gatts_value_t gatts_value; memset(&gatts_value, 0, sizeof(gatts_value)); @@ -568,7 +569,7 @@ void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uin } } -void ble_drv_attr_notif(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { +void ble_drv_attr_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { uint16_t hvx_len = len; ble_gatts_hvx_params_t hvx_params; diff --git a/nrf5/sdk/ble_drv.h b/nrf5/sdk/ble_drv.h index 8f8075a8c7..9fc80215ed 100644 --- a/nrf5/sdk/ble_drv.h +++ b/nrf5/sdk/ble_drv.h @@ -58,6 +58,6 @@ void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); -void ble_drv_attr_notif(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); +void ble_drv_attr_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); #endif // BLUETOOTH_LE_DRIVER_H__ From c9bfcb5bc5774b6c9a35f45a800028ac978c70ba Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 20 Feb 2017 21:27:21 +0100 Subject: [PATCH 406/809] nrf5/modules: Implementing characteristic write method. Possible to use write for both write and notifications. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index f726f9bbdb..313ac8ec4b 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -30,6 +30,7 @@ #if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL #include "modubluepy.h" +#include "ble_drv.h" STATIC void ubluepy_characteristic_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_characteristic_obj_t * self = (ubluepy_characteristic_obj_t *)o; @@ -97,8 +98,21 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_read_obj, char_read); /// STATIC mp_obj_t char_write(mp_obj_t self_in, mp_obj_t data) { ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); - (void)self; - // ble_drv_characteristic_write(); + + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(data, &bufinfo, MP_BUFFER_READ); + + if (self->props & UBLUEPY_PROP_NOTIFY) { + ble_drv_attr_notify(self->p_service->p_periph->conn_handle, + self->handle, + bufinfo.len, + bufinfo.buf); + } else { + ble_drv_attr_write(self->p_service->p_periph->conn_handle, + self->handle, + bufinfo.len, + bufinfo.buf); + } return mp_const_none; } From acb5c7b4eee9d3d8c5050013713a1099e4c872a8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 20 Feb 2017 21:28:07 +0100 Subject: [PATCH 407/809] nrf5/modules: Updating ubluepy example in header to align with bluetooth uart service characteristic's. --- nrf5/modules/ubluepy/modubluepy.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 032c0a1990..8e580af16c 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -57,8 +57,8 @@ u0 = UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e") u1 = UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e") u2 = UUID("6e400003-b5a3-f393-e0a9-e50e24dcca9e") s = Service(u0) -c0 = Characteristic(u1, props = Characteristic.PROP_BROADCAST, attrs = Characteristic.ATTR_CCCD) -c1 = Characteristic(u2) +c0 = Characteristic(u1, props = Characteristic.PROP_WRITE | Characteristic.PROP_WRITE_WO_RESP) +c1 = Characteristic(u2, props = Characteristic.PROP_NOTIFY, attrs = Characteristic.ATTR_CCCD) s.addCharacteristic(c0) s.addCharacteristic(c1) p = Peripheral() From 80b2d7e4ad4064bda774bf19a8757b18d2ee8684 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 21 Feb 2017 00:15:51 +0100 Subject: [PATCH 408/809] nrf5/sdk: Backing up ubluepy version of ble uart service for Bluetooth LE REPL. --- nrf5/sdk/ble_uart.c | 161 ++++++++++++++++++++++++++++++++++++++++++++ nrf5/sdk/ble_uart.h | 35 ++++++++++ 2 files changed, 196 insertions(+) create mode 100644 nrf5/sdk/ble_uart.c create mode 100644 nrf5/sdk/ble_uart.h diff --git a/nrf5/sdk/ble_uart.c b/nrf5/sdk/ble_uart.c new file mode 100644 index 0000000000..1164158352 --- /dev/null +++ b/nrf5/sdk/ble_uart.c @@ -0,0 +1,161 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "ble_uart.h" + +#if MICROPY_PY_BLE_NUS + +static ubluepy_uuid_obj_t uuid_obj_service = { + .base.type = &ubluepy_uuid_type, + .type = UBLUEPY_UUID_128_BIT, + .value = {0x01, 0x00} +}; + +static ubluepy_uuid_obj_t uuid_obj_char_tx = { + .base.type = &ubluepy_uuid_type, + .type = UBLUEPY_UUID_128_BIT, + .value = {0x02, 0x00} +}; + +static ubluepy_uuid_obj_t uuid_obj_char_rx = { + .base.type = &ubluepy_uuid_type, + .type = UBLUEPY_UUID_128_BIT, + .value = {0x03, 0x00} +}; + +static ubluepy_service_obj_t ble_uart_service = { + .base.type = &ubluepy_service_type, + .p_uuid = &uuid_obj_service, + .type = UBLUEPY_SERVICE_PRIMARY +}; + +static ubluepy_characteristic_obj_t ble_uart_char_tx = { + .base.type = &ubluepy_characteristic_type, + .p_uuid = &uuid_obj_char_tx, + .props = UBLUEPY_PROP_WRITE | UBLUEPY_PROP_WRITE_WO_RESP, + .attrs = 0, +}; + +static ubluepy_characteristic_obj_t ble_uart_char_rx = { + .base.type = &ubluepy_characteristic_type, + .p_uuid = &uuid_obj_char_rx, + .props = UBLUEPY_PROP_NOTIFY, + .attrs = UBLUEPY_ATTR_CCCD, +}; + +static ubluepy_peripheral_obj_t ble_uart_peripheral = { + .base.type = &ubluepy_peripheral_type, + .conn_handle = 0xFFFF, +}; + +int mp_hal_stdin_rx_chr(void) { + return 0; +} + +void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) { + +} + +STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data) { + ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); + + if (event_id == 16) { // connect event + self->conn_handle = conn_handle; + } else if (event_id == 17) { // disconnect event + self->conn_handle = 0xFFFF; // invalid connection handle + } +} + +STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data) { + ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); + (void)self; +} + +void ble_uart_init0(void) { + uint8_t base_uuid[] = {0x9E, 0xCA, 0xDC, 0x24, 0x0E, 0xE5, 0xA9, 0xE0, 0x93, 0xF3, 0xA3, 0xB5, 0x00, 0x00, 0x40, 0x6E}; + uint8_t uuid_vs_idx; + + (void)ble_drv_uuid_add_vs(base_uuid, &uuid_vs_idx); + + uuid_obj_service.uuid_vs_idx = uuid_vs_idx; + uuid_obj_char_tx.uuid_vs_idx = uuid_vs_idx; + uuid_obj_char_rx.uuid_vs_idx = uuid_vs_idx; + + (void)ble_drv_service_add(&ble_uart_service); + ble_uart_service.char_list = mp_obj_new_list(0, NULL); + + // add TX characteristic + ble_uart_char_tx.service_handle = ble_uart_service.handle; + bool retval = ble_drv_characteristic_add(&ble_uart_char_tx); + if (retval) { + ble_uart_char_tx.p_service = &ble_uart_service; + } + mp_obj_list_append(ble_uart_service.char_list, MP_OBJ_FROM_PTR(&ble_uart_char_tx)); + + // add RX characteristic + ble_uart_char_rx.service_handle = ble_uart_service.handle; + retval = ble_drv_characteristic_add(&ble_uart_char_rx); + if (retval) { + ble_uart_char_rx.p_service = &ble_uart_service; + } + mp_obj_list_append(ble_uart_service.char_list, MP_OBJ_FROM_PTR(&ble_uart_char_rx)); + + + + // setup the peripheral + (void)ble_uart_peripheral; + + ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(&ble_uart_peripheral), gap_event_handler); + ble_drv_gatts_event_handler_set(MP_OBJ_FROM_PTR(&ble_uart_peripheral), gatts_event_handler); + + ble_uart_peripheral.conn_handle = 0xFFFF; + + char device_name[] = "mpus"; + + mp_obj_t service_list = mp_obj_new_list(0, NULL); + mp_obj_list_append(service_list, MP_OBJ_FROM_PTR(&ble_uart_service)); + + mp_obj_t * services = NULL; + mp_uint_t num_services; + mp_obj_get_array(service_list, &num_services, &services); + + ubluepy_advertise_data_t adv_data = { + .p_services = services, + .num_of_services = num_services, + .p_device_name = (uint8_t *)device_name, + .device_name_len = strlen(device_name) + }; + + (void)device_name; + (void)services; + + (void)ble_drv_advertise_data(&adv_data); +} + + +#endif // MICROPY_PY_BLE_NUS + diff --git a/nrf5/sdk/ble_uart.h b/nrf5/sdk/ble_uart.h new file mode 100644 index 0000000000..6d341cf5bf --- /dev/null +++ b/nrf5/sdk/ble_uart.h @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef BLUETOOTH_LE_UART_H__ +#define BLUETOOTH_LE_UART_H__ + +#include "modubluepy.h" +#include "ble_drv.h" + +void ble_uart_init0(void); + +#endif // BLUETOOTH_LE_UART_H__ From 3e66898c379ae86f2e34a981d4645273b7b220f0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 21 Feb 2017 23:37:52 +0100 Subject: [PATCH 409/809] nrf5/sdk: Updating bluetooth le uart implemenatation to block until cccd is written. --- nrf5/sdk/ble_uart.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/nrf5/sdk/ble_uart.c b/nrf5/sdk/ble_uart.c index 1164158352..b6f7318821 100644 --- a/nrf5/sdk/ble_uart.c +++ b/nrf5/sdk/ble_uart.c @@ -57,7 +57,7 @@ static ubluepy_characteristic_obj_t ble_uart_char_tx = { .base.type = &ubluepy_characteristic_type, .p_uuid = &uuid_obj_char_tx, .props = UBLUEPY_PROP_WRITE | UBLUEPY_PROP_WRITE_WO_RESP, - .attrs = 0, + .attrs = 0, }; static ubluepy_characteristic_obj_t ble_uart_char_rx = { @@ -72,12 +72,33 @@ static ubluepy_peripheral_obj_t ble_uart_peripheral = { .conn_handle = 0xFFFF, }; +static bool cccd_enabled; + int mp_hal_stdin_rx_chr(void) { return 0; } -void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) { +void mp_hal_stdout_tx_strn(const char *str, size_t len) { + uint8_t *buf = (uint8_t *)str; + size_t send_len; + while (len > 0) { + if (len >= 20) { + send_len = 20; // (GATT_MTU_SIZE_DEFAULT - 3) + } else { + send_len = len; + } + + ubluepy_characteristic_obj_t * p_char = &ble_uart_char_rx; + + ble_drv_attr_notify(p_char->p_service->p_periph->conn_handle, + p_char->handle, + send_len, + buf); + + len -= send_len; + buf += send_len; + } } STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data) { @@ -93,6 +114,12 @@ STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data) { ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); (void)self; + + if (event_id == 80) { // gatts write + if (ble_uart_char_rx.cccd_handle == attr_handle) { + cccd_enabled = true; + } + } } void ble_uart_init0(void) { @@ -128,6 +155,9 @@ void ble_uart_init0(void) { // setup the peripheral (void)ble_uart_peripheral; + ble_uart_peripheral.service_list = mp_obj_new_list(0, NULL); + mp_obj_list_append(ble_uart_peripheral.service_list, MP_OBJ_FROM_PTR(&ble_uart_service)); + ble_uart_service.p_periph = &ble_uart_peripheral; ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(&ble_uart_peripheral), gap_event_handler); ble_drv_gatts_event_handler_set(MP_OBJ_FROM_PTR(&ble_uart_peripheral), gatts_event_handler); @@ -153,7 +183,13 @@ void ble_uart_init0(void) { (void)device_name; (void)services; + cccd_enabled = false; + (void)ble_drv_advertise_data(&adv_data); + + while (cccd_enabled != true) { + ; + } } From 09fd2b86d14bd6d2ad3b8d41536804df5a94bd56 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 21 Feb 2017 23:38:35 +0100 Subject: [PATCH 410/809] nrf5: Updating main to initialize bluetooth le uart module right before bluetooth REPL is started. --- nrf5/main.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/nrf5/main.c b/nrf5/main.c index b998e84e98..b3a2620056 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -53,8 +53,8 @@ #endif #include "timer.h" -#if (BLUETOOTH_SD == 132) -#include "nrf52_ble.h" +#if (MICROPY_PY_BLE_NUS) +#include "ble_uart.h" #endif void do_str(const char *src, mp_parse_input_kind_t input_kind) { @@ -91,10 +91,6 @@ int main(int argc, char **argv) { gc_init(&_heap_start, &_heap_end); -#if MICROPY_PY_BLE_NUS - nrf52_ble_init(); -#endif - mp_init(); mp_obj_list_init(mp_sys_path, 0); mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script) @@ -125,8 +121,9 @@ int main(int argc, char **argv) { timer_init0(); */ -#if (MICROPY_PY_BLE_NUS == 0) uart_init0(); + +#if (MICROPY_PY_BLE_NUS == 0) { mp_obj_t args[2] = { MP_OBJ_NEW_SMALL_INT(PYB_UART_1), @@ -189,6 +186,10 @@ int main(int argc, char **argv) { // The REPL mode can change, or it can request a soft reset. int ret_code = 0; +#if MICROPY_PY_BLE_NUS + ble_uart_init0(); +#endif + for (;;) { ret_code = pyexec_friendly_repl(); if (ret_code != 0) { From 7fee0cdde155dc500d1a10e2070c7096d3af426a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 22 Feb 2017 19:10:18 +0100 Subject: [PATCH 411/809] nrf5/modules: Expose ubluepy characteristic and peripheral types as external declaration in ublupy header. --- nrf5/modules/ubluepy/modubluepy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 8e580af16c..71c9f82300 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -72,6 +72,8 @@ p.advertise(device_name="micr", services=[s]) extern const mp_obj_type_t ubluepy_uuid_type; extern const mp_obj_type_t ubluepy_service_type; +extern const mp_obj_type_t ubluepy_characteristic_type; +extern const mp_obj_type_t ubluepy_peripheral_type; typedef enum { UBLUEPY_UUID_16_BIT = 1, From f10abda60af8f0bb809d36096167a0ff8735c97c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 22 Feb 2017 19:54:02 +0100 Subject: [PATCH 412/809] nrf5/sdk: Updating bluetooth le driver to extract data length and pointer from the event structure upon gatts write operation. --- nrf5/sdk/ble_drv.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index abedf2936b..bca671b482 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -624,7 +624,12 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GATTS_EVT_WRITE: BLE_DRIVER_LOG("GATTS write\n"); - ubluepy_gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gatts_evt.params.write.handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); + + uint16_t handle = p_ble_evt->evt.gatts_evt.params.write.handle; + uint16_t data_len = p_ble_evt->evt.gatts_evt.params.write.len; + uint8_t * p_data = &p_ble_evt->evt.gatts_evt.params.write.data[0]; + + ubluepy_gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, handle, data_len, p_data); break; case BLE_GAP_EVT_CONN_PARAM_UPDATE: From 6b898d1d675d96c1a0e9526fd9aabbe7cf782115 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 23 Feb 2017 21:52:23 +0100 Subject: [PATCH 413/809] nrf5/sdk: Adding macro based ringbuffer written by Philip Thrasher. source: https://github.com/pthrasher/c-generic-ring-buffer/blob/master/ringbuffer.h. Copyright noticed copied into the file, and file reviewed by Philip. --- nrf5/sdk/ringbuffer.h | 99 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 nrf5/sdk/ringbuffer.h diff --git a/nrf5/sdk/ringbuffer.h b/nrf5/sdk/ringbuffer.h new file mode 100644 index 0000000000..3f54a6200c --- /dev/null +++ b/nrf5/sdk/ringbuffer.h @@ -0,0 +1,99 @@ +/* The MIT License (MIT) + * + * Copyright (c) 2013 Philip Thrasher + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * Philip Thrasher's Crazy Awesome Ring Buffer Macros! + * + * Below you will find some naughty macros for easy owning and manipulating + * generic ring buffers. Yes, they are slightly evil in readability, but they + * are really fast, and they work great. + * + * Example usage: + * + * #include + * + * // So we can use this in any method, this gives us a typedef + * // named 'intBuffer'. + * ringBuffer_typedef(int, intBuffer); + * + * int main() { + * // Declare vars. + * intBuffer myBuffer; + * + * bufferInit(myBuffer,1024,int); + * + * // We must have the pointer. All of the macros deal with the pointer. + * // (except for init.) + * intBuffer* myBuffer_ptr; + * myBuffer_ptr = &myBuffer; + * + * // Write two values. + * bufferWrite(myBuffer_ptr,37); + * bufferWrite(myBuffer_ptr,72); + * + * // Read a value into a local variable. + * int first; + * bufferRead(myBuffer_ptr,first); + * assert(first == 37); // true + * + * int second; + * bufferRead(myBuffer_ptr,second); + * assert(second == 72); // true + * + * return 0; + * } + * + */ + +#ifndef _ringbuffer_h +#define _ringbuffer_h + +#define ringBuffer_typedef(T, NAME) \ + typedef struct { \ + int size; \ + int start; \ + int end; \ + T* elems; \ + } NAME + +#define bufferInit(BUF, S, T) \ + BUF.size = S+1; \ + BUF.start = 0; \ + BUF.end = 0; \ + BUF.elems = (T*)calloc(BUF.size, sizeof(T)) + + +#define bufferDestroy(BUF) free(BUF->elems) +#define nextStartIndex(BUF) ((BUF->start + 1) % BUF->size) +#define nextEndIndex(BUF) ((BUF->end + 1) % BUF->size) +#define isBufferEmpty(BUF) (BUF->end == BUF->start) +#define isBufferFull(BUF) (nextEndIndex(BUF) == BUF->start) + +#define bufferWrite(BUF, ELEM) \ + BUF->elems[BUF->end] = ELEM; \ + BUF->end = (BUF->end + 1) % BUF->size; \ + if (isBufferEmpty(BUF)) { \ + BUF->start = nextStartIndex(BUF); \ + } + +#define bufferRead(BUF, ELEM) \ + ELEM = BUF->elems[BUF->start]; \ + BUF->start = nextStartIndex(BUF); + +#endif From 3882b0e2ffb096328b00ee453fb92e3d08a3400b Mon Sep 17 00:00:00 2001 From: Bander Ajba Date: Fri, 24 Feb 2017 00:38:08 +0300 Subject: [PATCH 414/809] added support for hardware temperature sensor --- nrf5/Makefile | 2 + nrf5/boards/nrf51822_ac_s110.ld | 2 +- nrf5/boards/pca10028/mpconfigboard.h | 3 +- nrf5/boards/pca10028/nrf51_hal_conf.h | 1 + nrf5/hal/hal_temp.c | 57 ++++++++++++ nrf5/hal/hal_temp.h | 47 ++++++++++ nrf5/modules/machine/modmachine.c | 6 ++ nrf5/modules/machine/temp.c | 121 ++++++++++++++++++++++++++ nrf5/modules/machine/temp.h | 43 +++++++++ 9 files changed, 280 insertions(+), 2 deletions(-) create mode 100644 nrf5/hal/hal_temp.c create mode 100644 nrf5/hal/hal_temp.h create mode 100644 nrf5/modules/machine/temp.c create mode 100644 nrf5/modules/machine/temp.h diff --git a/nrf5/Makefile b/nrf5/Makefile index d39dec4f26..7b91770a8b 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -119,6 +119,7 @@ SRC_HAL = $(addprefix hal/,\ hal_twi.c \ hal_adc.c \ hal_adce.c \ + hal_temp.c \ ) ifeq ($(MCU_VARIANT), nrf52) @@ -161,6 +162,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/rtc.c \ machine/pwm.c \ machine/led.c \ + machine/temp.c \ usocket/modusocket.c \ network/modnetwork.c \ uos/moduos.c \ diff --git a/nrf5/boards/nrf51822_ac_s110.ld b/nrf5/boards/nrf51822_ac_s110.ld index ec1aff397d..90d76ec57e 100644 --- a/nrf5/boards/nrf51822_ac_s110.ld +++ b/nrf5/boards/nrf51822_ac_s110.ld @@ -9,7 +9,7 @@ MEMORY FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */ FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 159 KiB */ - RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x006000 /* 24 KiB */ + RAM (xrw) : ORIGIN = 0x20001800, LENGTH = 0x002800 /* 12 KiB */ } /* produce a link error if there is not this amount of RAM for these sections */ diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 6b9de477d6..814351168f 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -43,6 +43,7 @@ #define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) +#define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_PY_USOCKET (0) #define MICROPY_PY_NETWORK (0) @@ -72,7 +73,7 @@ #define MICROPY_HW_UART1_TX (pin_A9) #define MICROPY_HW_UART1_CTS (pin_A10) #define MICROPY_HW_UART1_RTS (pin_A8) -#define MICROPY_HW_UART1_HWFC (1) +#define MICROPY_HW_UART1_HWFC (0) // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" diff --git a/nrf5/boards/pca10028/nrf51_hal_conf.h b/nrf5/boards/pca10028/nrf51_hal_conf.h index 1b87bf9942..e83e2d346e 100644 --- a/nrf5/boards/pca10028/nrf51_hal_conf.h +++ b/nrf5/boards/pca10028/nrf51_hal_conf.h @@ -8,5 +8,6 @@ #define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/hal/hal_temp.c b/nrf5/hal/hal_temp.c new file mode 100644 index 0000000000..c885fdc66f --- /dev/null +++ b/nrf5/hal/hal_temp.c @@ -0,0 +1,57 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "mphalport.h" +#include "hal_temp.h" + +#ifdef HAL_TEMP_MODULE_ENABLED + +/** + * @brief Function for preparing the temp module for temperature measurement. + * + * This function initializes the TEMP module and writes to the hidden configuration register. + */ +void hal_temp_init(void) +{ + /**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */ + *(uint32_t *) 0x4000C504 = 0; +} + +/** + * @brief Function for reading temperature measurement. + * + * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value. + */ +int32_t hal_temp_read(void) +{ + hal_temp_init(); + /**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */ + return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP); +} +/**@endcond */ + +#endif // HAL_ADC_MODULE_ENABLED diff --git a/nrf5/hal/hal_temp.h b/nrf5/hal/hal_temp.h new file mode 100644 index 0000000000..fbab6ebc4d --- /dev/null +++ b/nrf5/hal/hal_temp.h @@ -0,0 +1,47 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#ifndef NRF_TEMP_H__ +#define NRF_TEMP_H__ + +#include "nrf.h" + +/** +* @defgroup nrf_temperature TEMP (temperature) abstraction +* @{ +* @ingroup nrf_drivers temperature_example +* @brief Temperature module init and read functions. +* +*/ + +/**@cond NO_DOXYGEN */ +#define MASK_SIGN (0x00000200UL) +#define MASK_SIGN_EXTENSION (0xFFFFFC00UL) + +/** + * @brief Function for preparing the temp module for temperature measurement. + * + * This function initializes the TEMP module and writes to the hidden configuration register. + */ +void hal_temp_init(void); + +/** + * @brief Function for reading temperature measurement. + * + * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value. + */ +int32_t hal_temp_read(void); +/**@endcond */ + +/** @} */ + +#endif \ No newline at end of file diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 101123dcce..fa3fbec2ff 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -46,6 +46,9 @@ #if MICROPY_PY_MACHINE_ADC #include "adc.h" #endif +#if MICROPY_PY_MACHINE_TEMP +#include "temp.h" +#endif #define PYB_RESET_HARD (0) @@ -180,6 +183,9 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { #endif #if MICROPY_PY_MACHINE_PWM { MP_OBJ_NEW_QSTR(MP_QSTR_PWM), (mp_obj_t)&machine_hard_pwm_type }, +#endif +#if MICROPY_PY_MACHINE_TEMP + { MP_OBJ_NEW_QSTR(MP_QSTR_TEMP), (mp_obj_t)&machine_temp_type }, #endif { MP_OBJ_NEW_QSTR(MP_QSTR_HARD_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_HARD) }, { MP_OBJ_NEW_QSTR(MP_QSTR_WDT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_WDT) }, diff --git a/nrf5/modules/machine/temp.c b/nrf5/modules/machine/temp.c new file mode 100644 index 0000000000..02ae73b894 --- /dev/null +++ b/nrf5/modules/machine/temp.c @@ -0,0 +1,121 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/nlr.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "temp.h" +#include "hal_temp.h" + +#if MICROPY_PY_MACHINE_TEMP + +typedef struct _machine_temp_obj_t { + mp_obj_base_t base; + TEMP_HandleTypeDef *temp; +} machine_temp_obj_t; + +TEMP_HandleTypeDef TEMPHandle0 = {.instance = NULL }; + + +STATIC const machine_temp_obj_t machine_temp_obj = { + {&machine_temp_type}, &TEMPHandle0 +}; + +/// \method __str__() +/// Return a string describing the ADC object. +STATIC void machine_temp_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + machine_temp_obj_t *self = o; + + (void)self; + + mp_printf(print, "TEMP"); +} + +/******************************************************************************/ +/* MicroPython bindings for machine API */ + +STATIC mp_obj_t machine_temp_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + { }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + memset(&TEMPHandle0, 0, sizeof(TEMP_HandleTypeDef)); + TEMPHandle0.instance = TEMP_BASE; + + const machine_temp_obj_t *self = &machine_temp_obj; + + return MP_OBJ_FROM_PTR(self); +} + +/// \method read() +/// Get temperature. +mp_obj_t machine_temp_read(void) { + int32_t volatile temp; + + NRF_TEMP->TASKS_START = 1; /** Start the temperature measurement. */ + + /* Busy wait while temperature measurement is not finished, you can skip waiting if you enable interrupt for DATARDY event and read the result in the interrupt. */ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + while (NRF_TEMP->EVENTS_DATARDY == 0) + { + // Do nothing. + } + NRF_TEMP->EVENTS_DATARDY = 0; + + /**@note Workaround for PAN_028 rev2.0A anomaly 29 - TEMP: Stop task clears the TEMP register. */ + temp = (hal_temp_read() / 4); + + /**@note Workaround for PAN_028 rev2.0A anomaly 30 - TEMP: Temp module analog front end does not power down when DATARDY event occurs. */ + NRF_TEMP->TASKS_STOP = 1; /** Stop the temperature measurement. */ + + return MP_OBJ_NEW_SMALL_INT(temp); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(mp_machine_temp_read_obj, machine_temp_read); + +STATIC const mp_map_elem_t machine_temp_locals_dict_table[] = { + // instance methods + // class methods + { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&mp_machine_temp_read_obj }, +}; + +STATIC MP_DEFINE_CONST_DICT(machine_temp_locals_dict, machine_temp_locals_dict_table); + +const mp_obj_type_t machine_temp_type = { + { &mp_type_type }, + .name = MP_QSTR_TEMP, + .make_new = machine_temp_make_new, + .locals_dict = (mp_obj_t)&machine_temp_locals_dict, + .print = machine_temp_print, +}; + +#endif // MICROPY_PY_MACHINE_TEMP diff --git a/nrf5/modules/machine/temp.h b/nrf5/modules/machine/temp.h new file mode 100644 index 0000000000..4d84d5e892 --- /dev/null +++ b/nrf5/modules/machine/temp.h @@ -0,0 +1,43 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef TEMP_H__ +#define TEMP_H__ + +#include "hal_temp.h" + +extern const mp_obj_type_t machine_temp_type; + +#define TEMP_BASE (NRF_TEMP_Type *)NRF_TEMP + +typedef struct __TEMP_HandleTypeDef +{ + NRF_TEMP_Type *instance; /* RTC registers base address */ +} TEMP_HandleTypeDef; + +int32_t temp_read(void); + +#endif // TEMP_H__ From e60a06563ec8ebb277d630cdac0b964525f8855e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 24 Feb 2017 15:03:53 +0100 Subject: [PATCH 415/809] nrf5/boards: Updating pca10028 bluetooth stack targets to have a MCU_SUB_VARIANT. --- nrf5/boards/pca10028/mpconfigboard_s110.mk | 1 + nrf5/boards/pca10028/mpconfigboard_s120.mk | 1 + nrf5/boards/pca10028/mpconfigboard_s130.mk | 1 + 3 files changed, 3 insertions(+) diff --git a/nrf5/boards/pca10028/mpconfigboard_s110.mk b/nrf5/boards/pca10028/mpconfigboard_s110.mk index 54766bd429..ea7b9c3e9c 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s110.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 +MCU_SUB_VARIANT = nrf51822 LD_FILE = boards/nrf51822_ac_s110.ld diff --git a/nrf5/boards/pca10028/mpconfigboard_s120.mk b/nrf5/boards/pca10028/mpconfigboard_s120.mk index e9b7770dd0..ad896186f0 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s120.mk @@ -1,3 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 +MCU_SUB_VARIANT = nrf51822 LD_FILE = boards/nrf51822_ac_s120.ld diff --git a/nrf5/boards/pca10028/mpconfigboard_s130.mk b/nrf5/boards/pca10028/mpconfigboard_s130.mk index 3f55086b49..5e6e49268b 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s130.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 +MCU_SUB_VARIANT = nrf51822 LD_FILE = boards/nrf51822_ac_s130.ld From bfda169dfea3c00a0db29564e548a2ff67a28456 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 24 Feb 2017 15:08:32 +0100 Subject: [PATCH 416/809] nrf5/modules: Updating ubluepy example to print out gatts write events with data. --- nrf5/modules/ubluepy/modubluepy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 71c9f82300..c9d924a8bf 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -49,6 +49,8 @@ def event_handler(id, length, data): elif id == constants.EVT_GAP_DISCONNECTED: # disconnect LED(2).off() + elif id == 80: + print("id 80, data:", data) # u0 = UUID("0x180D") # HRM service # u1 = UUID("0x2A37") # HRM measurement From 64b23e11279138414967ff36671d4f8ba675a087 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 24 Feb 2017 15:14:12 +0100 Subject: [PATCH 417/809] nrf5/sdk: Backing up progress in BLE UART driver. Adding ringbuffer in order to poll bytes from recieved data in REPL main loop. --- nrf5/sdk/ble_uart.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/nrf5/sdk/ble_uart.c b/nrf5/sdk/ble_uart.c index b6f7318821..f673ca20c3 100644 --- a/nrf5/sdk/ble_uart.c +++ b/nrf5/sdk/ble_uart.c @@ -26,6 +26,8 @@ #include #include "ble_uart.h" +#include "ringbuffer.h" +#include "hal/hal_time.h" #if MICROPY_PY_BLE_NUS @@ -74,8 +76,21 @@ static ubluepy_peripheral_obj_t ble_uart_peripheral = { static bool cccd_enabled; +ringBuffer_typedef(uint8_t, ringbuffer_t); + +static ringbuffer_t m_rx_ring_buffer; +static ringbuffer_t * mp_rx_ring_buffer = &m_rx_ring_buffer; +static uint8_t m_rx_ring_buffer_data[128]; + + int mp_hal_stdin_rx_chr(void) { - return 0; + while (isBufferEmpty(mp_rx_ring_buffer)) { + ; + } + + uint8_t byte; + bufferRead(mp_rx_ring_buffer, byte); + return (int)byte; } void mp_hal_stdout_tx_strn(const char *str, size_t len) { @@ -101,6 +116,14 @@ void mp_hal_stdout_tx_strn(const char *str, size_t len) { } } +void mp_hal_stdout_tx_strn_cooked(const char *str, mp_uint_t len) { + for (uint8_t i = 0; i < len; i++) { + mp_hal_stdout_tx_strn(&str[i], 1); + // for now put in a small delay as it could look like packets are issued to fast. + mp_hal_delay_ms(10); + } +} + STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data) { ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); @@ -118,7 +141,11 @@ STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t at if (event_id == 80) { // gatts write if (ble_uart_char_rx.cccd_handle == attr_handle) { cccd_enabled = true; - } + } else if (ble_uart_char_tx.handle == attr_handle) { + for (uint16_t i = 0; i < length; i++) { + bufferWrite(mp_rx_ring_buffer, data[i]); + } + } } } @@ -151,8 +178,6 @@ void ble_uart_init0(void) { } mp_obj_list_append(ble_uart_service.char_list, MP_OBJ_FROM_PTR(&ble_uart_char_rx)); - - // setup the peripheral (void)ble_uart_peripheral; ble_uart_peripheral.service_list = mp_obj_new_list(0, NULL); @@ -185,6 +210,12 @@ void ble_uart_init0(void) { cccd_enabled = false; + // initialize ring buffer + m_rx_ring_buffer.size = sizeof(m_rx_ring_buffer_data) + 1; + m_rx_ring_buffer.start = 0; + m_rx_ring_buffer.end = 0; + m_rx_ring_buffer.elems = m_rx_ring_buffer_data; + (void)ble_drv_advertise_data(&adv_data); while (cccd_enabled != true) { From 65f3e16775ef8691fb177c6afcb49a0ca46dd2a5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Feb 2017 01:29:13 +0100 Subject: [PATCH 418/809] nrf5: Setting stack top in main.c. Thanks dhylands for pointing this out. --- nrf5/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/main.c b/nrf5/main.c index b3a2620056..d8f91c2336 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -82,6 +82,8 @@ extern uint32_t _heap_end; int main(int argc, char **argv) { + mp_stack_set_top(&_ram_end); + // Stack limit should be less than real stack size, so we have a chance // to recover from limit hit. (Limit is measured in bytes.) mp_stack_set_limit((char*)&_ram_end - (char*)&_heap_end - 400); From dcd980381d35c75abb647f0dfac3006a5f64557e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Feb 2017 01:30:33 +0100 Subject: [PATCH 419/809] nrf5: Updating Makefile to use correct variable for setting directory of file to freeze as mpy. --- nrf5/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index d39dec4f26..bedf42d0fc 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -37,7 +37,7 @@ endif # qstr definitions (must come before including py.mk) QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h -FROZEN_DIR = freeze +FROZEN_MPY_DIR = freeze # include py core make definitions include ../py/py.mk From d3c3fa4a7416ea424399429b9a35f719cb08ca3e Mon Sep 17 00:00:00 2001 From: Dave Hylands Date: Sat, 25 Feb 2017 16:52:46 -0800 Subject: [PATCH 420/809] Fix up Makefile dependencies I also didn't see any real reason for mkrules.mk to exist, so I merged the contents into Makefile. Now you can do: ``` make BOARD=pca10028 clean make BOARD=pca10028 flash ``` and it will work properly. --- nrf5/Makefile | 38 ++++++++++++++++++++++++++------------ nrf5/mkrules.mk | 10 ---------- 2 files changed, 26 insertions(+), 22 deletions(-) delete mode 100644 nrf5/mkrules.mk diff --git a/nrf5/Makefile b/nrf5/Makefile index d39dec4f26..2aafe3cfd4 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -198,37 +198,51 @@ OBJ += $(BUILD)/pins_gen.o $(BUILD)/$(FATFS_DIR)/ff.o: COPT += -Os $(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os -.phony: all flash sd +.phony: all flash sd binary hex -all: $(BUILD)/firmware.elf binary hex +all: binary hex + +OUTPUT_FILENAME = firmware + +## Create binary .bin file from the .out file +binary: $(BUILD)/$(OUTPUT_FILENAME).bin + +$(BUILD)/$(OUTPUT_FILENAME).bin: $(BUILD)/$(OUTPUT_FILENAME).elf + $(OBJCOPY) -O binary $< $@ + +## Create binary .hex file from the .out file +hex: $(BUILD)/$(OUTPUT_FILENAME).hex + +$(BUILD)/$(OUTPUT_FILENAME).hex: $(BUILD)/$(OUTPUT_FILENAME).elf + $(OBJCOPY) -O ihex $< $@ FLASHER ?= ifeq ($(FLASHER),) -flash: $(BUILD)/firmware.elf - nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT) +flash: $(BUILD)/$(OUTPUT_FILENAME).hex + nrfjprog --program $< --sectorerase -f $(MCU_VARIANT) nrfjprog --reset -f $(MCU_VARIANT) -sd: +sd: $(BUILD)/$(OUTPUT_FILENAME).hex nrfjprog --eraseall -f $(MCU_VARIANT) nrfjprog --program $(SOFTDEV_HEX) -f $(MCU_VARIANT) - nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT) + nrfjprog --program $< --sectorerase -f $(MCU_VARIANT) nrfjprog --reset -f $(MCU_VARIANT) else ifeq ($(FLASHER), pyocd) -flash: $(BUILD)/firmware.elf - pyocd-flashtool -t $(MCU_VARIANT) $(BUILD)/firmware.hex +flash: $(BUILD)/$(OUTPUT_FILENAME).hex + pyocd-flashtool -t $(MCU_VARIANT) $< -sd: +sd: $(BUILD)/$(OUTPUT_FILENAME).hex pyocd-flashtool -t $(MCU_VARIANT) --chip_erase pyocd-flashtool -t $(MCU_VARIANT) $(SOFTDEV_HEX) - pyocd-flashtool -t $(MCU_VARIANT) $(BUILD)/firmware.hex + pyocd-flashtool -t $(MCU_VARIANT) $< endif -$(BUILD)/firmware.elf: $(OBJ) +$(BUILD)/$(OUTPUT_FILENAME).elf: $(OBJ) $(ECHO) "LINK $@" $(Q)$(CC) $(LDFLAGS) -o $@ $(OBJ) $(LIBS) $(Q)$(SIZE) $@ @@ -280,4 +294,4 @@ CFLAGS += -DMICROPY_MODULE_FROZEN_MPY endif include ../py/mkrules.mk -include mkrules.mk + diff --git a/nrf5/mkrules.mk b/nrf5/mkrules.mk deleted file mode 100644 index 6ae98cdc8d..0000000000 --- a/nrf5/mkrules.mk +++ /dev/null @@ -1,10 +0,0 @@ -OUTPUT_FILENAME = firmware - -## Create binary .bin file from the .out file -binary: - $(OBJCOPY) -O binary $(BUILD)/$(OUTPUT_FILENAME).elf $(BUILD)/$(OUTPUT_FILENAME).bin - -## Create binary .hex file from the .out file -hex: - $(OBJCOPY) -O ihex $(BUILD)/$(OUTPUT_FILENAME).elf $(BUILD)/$(OUTPUT_FILENAME).hex - From 378c40b4da456d487fb92d9ed0e82ad8222d48e9 Mon Sep 17 00:00:00 2001 From: Bander Ajba Date: Sun, 26 Feb 2017 11:14:17 +0300 Subject: [PATCH 421/809] did required modification to merge the temperature sensore module --- nrf5/boards/nrf51822_ac_s110.ld | 2 +- nrf5/boards/pca10000/mpconfigboard.h | 1 + nrf5/boards/pca10000/nrf51_hal_conf.h | 1 + nrf5/boards/pca10001/mpconfigboard.h | 4 +- nrf5/boards/pca10001/nrf51_hal_conf.h | 5 +++ nrf5/boards/pca10028/mpconfigboard.h | 2 +- nrf5/boards/pca10031/mpconfigboard.h | 1 + nrf5/boards/pca10031/nrf51_hal_conf.h | 1 + nrf5/boards/pca10040/mpconfigboard.h | 1 + nrf5/boards/pca10040/nrf52_hal_conf.h | 1 + nrf5/boards/pca10056/mpconfigboard.h | 1 + nrf5/boards/pca10056/nrf52_hal_conf.h | 1 + nrf5/hal/hal_temp.c | 40 +++++++++++--------- nrf5/hal/hal_temp.h | 54 ++++++++++++--------------- nrf5/modules/machine/temp.c | 41 +++----------------- nrf5/modules/machine/temp.h | 11 +----- 16 files changed, 69 insertions(+), 98 deletions(-) diff --git a/nrf5/boards/nrf51822_ac_s110.ld b/nrf5/boards/nrf51822_ac_s110.ld index 90d76ec57e..5df19da487 100644 --- a/nrf5/boards/nrf51822_ac_s110.ld +++ b/nrf5/boards/nrf51822_ac_s110.ld @@ -9,7 +9,7 @@ MEMORY FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */ FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 159 KiB */ - RAM (xrw) : ORIGIN = 0x20001800, LENGTH = 0x002800 /* 12 KiB */ + RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x006000 /* 12 KiB */ } /* produce a link error if there is not this amount of RAM for these sections */ diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf5/boards/pca10000/mpconfigboard.h index ac955eb61b..9646ced77c 100644 --- a/nrf5/boards/pca10000/mpconfigboard.h +++ b/nrf5/boards/pca10000/mpconfigboard.h @@ -32,6 +32,7 @@ #define MICROPY_PY_MACHINE_HW_SPI (0) #define MICROPY_PY_MACHINE_PWM (0) +#define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) diff --git a/nrf5/boards/pca10000/nrf51_hal_conf.h b/nrf5/boards/pca10000/nrf51_hal_conf.h index 1848c81034..c1ac8268ea 100644 --- a/nrf5/boards/pca10000/nrf51_hal_conf.h +++ b/nrf5/boards/pca10000/nrf51_hal_conf.h @@ -3,5 +3,6 @@ #define HAL_UART_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10001/mpconfigboard.h b/nrf5/boards/pca10001/mpconfigboard.h index 8380dcf76d..985eb31a29 100644 --- a/nrf5/boards/pca10001/mpconfigboard.h +++ b/nrf5/boards/pca10001/mpconfigboard.h @@ -32,6 +32,7 @@ #define MICROPY_PY_MACHINE_HW_SPI (0) #define MICROPY_PY_MACHINE_PWM (0) +#define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) @@ -46,6 +47,7 @@ #define MICROPY_HW_ENABLE_DAC (0) #define MICROPY_HW_ENABLE_CAN (0) + #define MICROPY_HW_LED_COUNT (2) #define MICROPY_HW_LED_PULLUP (0) @@ -57,6 +59,6 @@ #define MICROPY_HW_UART1_TX (pin_A9) #define MICROPY_HW_UART1_CTS (pin_A10) #define MICROPY_HW_UART1_RTS (pin_A8) -#define MICROPY_HW_UART1_HWFC (1) +#define MICROPY_HW_UART1_HWFC (0) #define HELP_TEXT_BOARD_LED "1,2" diff --git a/nrf5/boards/pca10001/nrf51_hal_conf.h b/nrf5/boards/pca10001/nrf51_hal_conf.h index 8ea72b4107..f5a1c6adb8 100644 --- a/nrf5/boards/pca10001/nrf51_hal_conf.h +++ b/nrf5/boards/pca10001/nrf51_hal_conf.h @@ -4,5 +4,10 @@ #define HAL_UART_MODULE_ENABLED // #define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 814351168f..e69de00951 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -73,7 +73,7 @@ #define MICROPY_HW_UART1_TX (pin_A9) #define MICROPY_HW_UART1_CTS (pin_A10) #define MICROPY_HW_UART1_RTS (pin_A8) -#define MICROPY_HW_UART1_HWFC (0) +#define MICROPY_HW_UART1_HWFC (1) // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" diff --git a/nrf5/boards/pca10031/mpconfigboard.h b/nrf5/boards/pca10031/mpconfigboard.h index e28112c69b..43c0693f7f 100644 --- a/nrf5/boards/pca10031/mpconfigboard.h +++ b/nrf5/boards/pca10031/mpconfigboard.h @@ -31,6 +31,7 @@ #define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" #define MICROPY_PY_MACHINE_PWM (0) +#define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) diff --git a/nrf5/boards/pca10031/nrf51_hal_conf.h b/nrf5/boards/pca10031/nrf51_hal_conf.h index 67cbc983ba..ecc150fe9e 100644 --- a/nrf5/boards/pca10031/nrf51_hal_conf.h +++ b/nrf5/boards/pca10031/nrf51_hal_conf.h @@ -4,5 +4,6 @@ #define HAL_UART_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index fcb62a5fe6..12f0cb5d35 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -36,6 +36,7 @@ #define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) +#define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) diff --git a/nrf5/boards/pca10040/nrf52_hal_conf.h b/nrf5/boards/pca10040/nrf52_hal_conf.h index 7ae58853c4..585506b8d6 100644 --- a/nrf5/boards/pca10040/nrf52_hal_conf.h +++ b/nrf5/boards/pca10040/nrf52_hal_conf.h @@ -9,6 +9,7 @@ #define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED #define HAL_ADCE_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index 308c9a1c9f..a4673057f5 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -34,6 +34,7 @@ #define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) +#define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_PY_DISPLAY (1) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) diff --git a/nrf5/boards/pca10056/nrf52_hal_conf.h b/nrf5/boards/pca10056/nrf52_hal_conf.h index 7ae58853c4..585506b8d6 100644 --- a/nrf5/boards/pca10056/nrf52_hal_conf.h +++ b/nrf5/boards/pca10056/nrf52_hal_conf.h @@ -9,6 +9,7 @@ #define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED #define HAL_ADCE_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED diff --git a/nrf5/hal/hal_temp.c b/nrf5/hal/hal_temp.c index c885fdc66f..7d6015e1af 100644 --- a/nrf5/hal/hal_temp.c +++ b/nrf5/hal/hal_temp.c @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2017 Glenn Ruben Bakke + * Copyright (c) 2017 Bander F. Ajba * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,28 +30,32 @@ #ifdef HAL_TEMP_MODULE_ENABLED -/** - * @brief Function for preparing the temp module for temperature measurement. - * - * This function initializes the TEMP module and writes to the hidden configuration register. - */ void hal_temp_init(void) { - /**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */ + // @note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module *(uint32_t *) 0x4000C504 = 0; } -/** - * @brief Function for reading temperature measurement. - * - * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value. - */ int32_t hal_temp_read(void) -{ +{ + int32_t volatile temp; hal_temp_init(); - /**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */ - return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP); -} -/**@endcond */ -#endif // HAL_ADC_MODULE_ENABLED + NRF_TEMP->TASKS_START = 1; // Start the temperature measurement. + + while (NRF_TEMP->EVENTS_DATARDY == 0) + { + // Do nothing. + } + + NRF_TEMP->EVENTS_DATARDY = 0; + + // @note Workaround for PAN_028 rev2.0A anomaly 29 - TEMP: Stop task clears the TEMP register. + temp = (((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP) / 4); + + // @note Workaround for PAN_028 rev2.0A anomaly 30 - TEMP: Temp module analog front end does not power down when DATARDY event occurs. + NRF_TEMP->TASKS_STOP = 1; // Stop the temperature measurement. + return temp; +} + +#endif // HAL_TEMP_MODULE_ENABLED diff --git a/nrf5/hal/hal_temp.h b/nrf5/hal/hal_temp.h index fbab6ebc4d..4ae5d15b05 100644 --- a/nrf5/hal/hal_temp.h +++ b/nrf5/hal/hal_temp.h @@ -1,47 +1,39 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. +/* + * This file is part of the Micro Python project, http://micropython.org/ * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * The MIT License (MIT) * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * Copyright (c) 2017 Bander F. Ajba * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. */ -#ifndef NRF_TEMP_H__ -#define NRF_TEMP_H__ +#ifndef HAL_TEMP_H__ +#define HAL_TEMP_H__ #include "nrf.h" -/** -* @defgroup nrf_temperature TEMP (temperature) abstraction -* @{ -* @ingroup nrf_drivers temperature_example -* @brief Temperature module init and read functions. -* -*/ - -/**@cond NO_DOXYGEN */ #define MASK_SIGN (0x00000200UL) #define MASK_SIGN_EXTENSION (0xFFFFFC00UL) -/** - * @brief Function for preparing the temp module for temperature measurement. - * - * This function initializes the TEMP module and writes to the hidden configuration register. - */ void hal_temp_init(void); -/** - * @brief Function for reading temperature measurement. - * - * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value. - */ int32_t hal_temp_read(void); -/**@endcond */ - -/** @} */ #endif \ No newline at end of file diff --git a/nrf5/modules/machine/temp.c b/nrf5/modules/machine/temp.c index 02ae73b894..1f5687f6ab 100644 --- a/nrf5/modules/machine/temp.c +++ b/nrf5/modules/machine/temp.c @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2017 Glenn Ruben Bakke + * Copyright (c) 2017 Bander F. Ajba * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,22 +35,12 @@ #if MICROPY_PY_MACHINE_TEMP -typedef struct _machine_temp_obj_t { - mp_obj_base_t base; - TEMP_HandleTypeDef *temp; -} machine_temp_obj_t; - -TEMP_HandleTypeDef TEMPHandle0 = {.instance = NULL }; - - -STATIC const machine_temp_obj_t machine_temp_obj = { - {&machine_temp_type}, &TEMPHandle0 -}; +typedef mp_obj_type_t machine_temp_type_t; /// \method __str__() /// Return a string describing the ADC object. STATIC void machine_temp_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - machine_temp_obj_t *self = o; + machine_temp_type_t *self = o; (void)self; @@ -69,10 +59,7 @@ STATIC mp_obj_t machine_temp_make_new(const mp_obj_type_t *type, size_t n_args, mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - memset(&TEMPHandle0, 0, sizeof(TEMP_HandleTypeDef)); - TEMPHandle0.instance = TEMP_BASE; - - const machine_temp_obj_t *self = &machine_temp_obj; + const machine_temp_type_t *self = (machine_temp_type_t*) NRF_TEMP_BASE; return MP_OBJ_FROM_PTR(self); } @@ -80,25 +67,7 @@ STATIC mp_obj_t machine_temp_make_new(const mp_obj_type_t *type, size_t n_args, /// \method read() /// Get temperature. mp_obj_t machine_temp_read(void) { - int32_t volatile temp; - - NRF_TEMP->TASKS_START = 1; /** Start the temperature measurement. */ - - /* Busy wait while temperature measurement is not finished, you can skip waiting if you enable interrupt for DATARDY event and read the result in the interrupt. */ - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ - while (NRF_TEMP->EVENTS_DATARDY == 0) - { - // Do nothing. - } - NRF_TEMP->EVENTS_DATARDY = 0; - - /**@note Workaround for PAN_028 rev2.0A anomaly 29 - TEMP: Stop task clears the TEMP register. */ - temp = (hal_temp_read() / 4); - - /**@note Workaround for PAN_028 rev2.0A anomaly 30 - TEMP: Temp module analog front end does not power down when DATARDY event occurs. */ - NRF_TEMP->TASKS_STOP = 1; /** Stop the temperature measurement. */ - - return MP_OBJ_NEW_SMALL_INT(temp); + return MP_OBJ_NEW_SMALL_INT(hal_temp_read()); } STATIC MP_DEFINE_CONST_FUN_OBJ_0(mp_machine_temp_read_obj, machine_temp_read); diff --git a/nrf5/modules/machine/temp.h b/nrf5/modules/machine/temp.h index 4d84d5e892..588d93107d 100644 --- a/nrf5/modules/machine/temp.h +++ b/nrf5/modules/machine/temp.h @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2017 Glenn Ruben Bakke + * Copyright (c) 2017 Bander F. Ajba * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,17 +27,8 @@ #ifndef TEMP_H__ #define TEMP_H__ -#include "hal_temp.h" - extern const mp_obj_type_t machine_temp_type; -#define TEMP_BASE (NRF_TEMP_Type *)NRF_TEMP - -typedef struct __TEMP_HandleTypeDef -{ - NRF_TEMP_Type *instance; /* RTC registers base address */ -} TEMP_HandleTypeDef; - int32_t temp_read(void); #endif // TEMP_H__ From 66542c34b9d88370a643fa608364e460ffb7abef Mon Sep 17 00:00:00 2001 From: Bander Ajba Date: Sun, 26 Feb 2017 11:17:07 +0300 Subject: [PATCH 422/809] did required modification to merge the temperature sensore module --- nrf5/boards/nrf51822_ac_s110.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/nrf51822_ac_s110.ld b/nrf5/boards/nrf51822_ac_s110.ld index 5df19da487..ec1aff397d 100644 --- a/nrf5/boards/nrf51822_ac_s110.ld +++ b/nrf5/boards/nrf51822_ac_s110.ld @@ -9,7 +9,7 @@ MEMORY FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */ FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 159 KiB */ - RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x006000 /* 12 KiB */ + RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x006000 /* 24 KiB */ } /* produce a link error if there is not this amount of RAM for these sections */ From e52ebb095c5686d7c1a4aa6bc816b49ed86859a8 Mon Sep 17 00:00:00 2001 From: Bander Ajba Date: Mon, 27 Feb 2017 21:37:32 +0300 Subject: [PATCH 423/809] fixed temp module to allow for instance support --- nrf5/hal/hal_temp.c | 9 +++------ nrf5/modules/machine/modmachine.c | 2 +- nrf5/modules/machine/temp.c | 28 +++++++++++++++++++--------- 3 files changed, 23 insertions(+), 16 deletions(-) diff --git a/nrf5/hal/hal_temp.c b/nrf5/hal/hal_temp.c index 7d6015e1af..fa08c25279 100644 --- a/nrf5/hal/hal_temp.c +++ b/nrf5/hal/hal_temp.c @@ -30,21 +30,18 @@ #ifdef HAL_TEMP_MODULE_ENABLED -void hal_temp_init(void) -{ +void hal_temp_init(void) { // @note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module *(uint32_t *) 0x4000C504 = 0; } -int32_t hal_temp_read(void) -{ +int32_t hal_temp_read(void) { int32_t volatile temp; hal_temp_init(); NRF_TEMP->TASKS_START = 1; // Start the temperature measurement. - while (NRF_TEMP->EVENTS_DATARDY == 0) - { + while (NRF_TEMP->EVENTS_DATARDY == 0) { // Do nothing. } diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index fa3fbec2ff..9fc28f95e5 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -185,7 +185,7 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_PWM), (mp_obj_t)&machine_hard_pwm_type }, #endif #if MICROPY_PY_MACHINE_TEMP - { MP_OBJ_NEW_QSTR(MP_QSTR_TEMP), (mp_obj_t)&machine_temp_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Temp), (mp_obj_t)&machine_temp_type }, #endif { MP_OBJ_NEW_QSTR(MP_QSTR_HARD_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_HARD) }, { MP_OBJ_NEW_QSTR(MP_QSTR_WDT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_WDT) }, diff --git a/nrf5/modules/machine/temp.c b/nrf5/modules/machine/temp.c index 1f5687f6ab..01188485cd 100644 --- a/nrf5/modules/machine/temp.c +++ b/nrf5/modules/machine/temp.c @@ -35,16 +35,22 @@ #if MICROPY_PY_MACHINE_TEMP -typedef mp_obj_type_t machine_temp_type_t; +typedef struct _machine_temp_obj_t { + mp_obj_base_t base; +} machine_temp_obj_t; + +STATIC const machine_temp_obj_t machine_temp_obj; + +#define TEMP_BASE (NRF_TEMP_Type *)NRF_TEMP /// \method __str__() -/// Return a string describing the ADC object. +/// Return a string describing the Temp object. STATIC void machine_temp_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - machine_temp_type_t *self = o; + machine_temp_obj_t *self = o; (void)self; - mp_printf(print, "TEMP"); + mp_printf(print, "Temp.read()"); } /******************************************************************************/ @@ -58,18 +64,22 @@ STATIC mp_obj_t machine_temp_make_new(const mp_obj_type_t *type, size_t n_args, // parse args mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - - const machine_temp_type_t *self = (machine_temp_type_t*) NRF_TEMP_BASE; + + machine_temp_obj_t *self = m_new_obj(machine_temp_obj_t); + + self->base.type = &machine_temp_type; return MP_OBJ_FROM_PTR(self); } /// \method read() /// Get temperature. -mp_obj_t machine_temp_read(void) { +STATIC mp_obj_t machine_temp_read(mp_uint_t n_args, const mp_obj_t *args) { + return MP_OBJ_NEW_SMALL_INT(hal_temp_read()); } -STATIC MP_DEFINE_CONST_FUN_OBJ_0(mp_machine_temp_read_obj, machine_temp_read); + +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_temp_read_obj, 0, 1, machine_temp_read); STATIC const mp_map_elem_t machine_temp_locals_dict_table[] = { // instance methods @@ -81,7 +91,7 @@ STATIC MP_DEFINE_CONST_DICT(machine_temp_locals_dict, machine_temp_locals_dict_t const mp_obj_type_t machine_temp_type = { { &mp_type_type }, - .name = MP_QSTR_TEMP, + .name = MP_QSTR_Temp, .make_new = machine_temp_make_new, .locals_dict = (mp_obj_t)&machine_temp_locals_dict, .print = machine_temp_print, From 12a6cb0fbf45b36d337575a9006236fcd1afce85 Mon Sep 17 00:00:00 2001 From: Bander Ajba Date: Mon, 27 Feb 2017 21:46:53 +0300 Subject: [PATCH 424/809] fixed temp module to allow for instance support --- nrf5/modules/machine/temp.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/nrf5/modules/machine/temp.c b/nrf5/modules/machine/temp.c index 01188485cd..1818784b65 100644 --- a/nrf5/modules/machine/temp.c +++ b/nrf5/modules/machine/temp.c @@ -39,10 +39,6 @@ typedef struct _machine_temp_obj_t { mp_obj_base_t base; } machine_temp_obj_t; -STATIC const machine_temp_obj_t machine_temp_obj; - -#define TEMP_BASE (NRF_TEMP_Type *)NRF_TEMP - /// \method __str__() /// Return a string describing the Temp object. STATIC void machine_temp_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { From b032d765ff772c990b17b9976bf40976f2198ce5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 27 Feb 2017 23:40:39 +0100 Subject: [PATCH 425/809] nrf5/sdk: Backing up progress in bluetooth le driver. Adding new gap and gatts handlers. Added handling of tx complete events when using notification, responding to MTU request, and setting of default connection parameters. --- nrf5/sdk/ble_drv.c | 124 +++++++++++++++++++++++++++++++++------------ 1 file changed, 92 insertions(+), 32 deletions(-) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index bca671b482..59155ea823 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -43,13 +43,36 @@ #define BLE_DRIVER_LOG(...) #endif +#define EDDYSTONE_UUID 0xFEAA // UUID for Eddystone beacons, Big Endian. + +// URL Frame Type, fixed at 0x10. +// RSSI, 0xEE = -18 dB is the approximate signal strength at 0 m. +// URL prefix, 0x00 = "http://www". +// URL +// URL suffix, 0x01 = ".com" +#define EDDYSTONE_DATA 0x10, 0xEE, 0x00, 'm', 'i', 'c', 'r', 'o', 'p', 'y', 't', 'h', 'o', 'n', 0x01 +#define BLE_ADV_LENGTH_FIELD_SIZE 1 +#define BLE_ADV_AD_TYPE_FIELD_SIZE 1 +#define BLE_AD_TYPE_FLAGS_DATA_SIZE 1 + +#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) +#define UNIT_0_625_MS (625) +#define UNIT_10_MS (10000) +#define APP_CFG_NON_CONN_ADV_TIMEOUT 0 // Disable timeout. +#define NON_CONNECTABLE_ADV_INTERVAL MSEC_TO_UNITS(100, UNIT_0_625_MS) + +#define BLE_MIN_CONN_INTERVAL MSEC_TO_UNITS(12, UNIT_0_625_MS) +#define BLE_MAX_CONN_INTERVAL MSEC_TO_UNITS(12, UNIT_0_625_MS) +#define BLE_SLAVE_LATENCY 0 +#define BLE_CONN_SUP_TIMEOUT MSEC_TO_UNITS(4000, UNIT_10_MS) #define SD_TEST_OR_ENABLE() \ if (ble_drv_stack_enabled() == 0) { \ (void)ble_drv_stack_enable(); \ } -static bool m_adv_in_progress = false; +static volatile bool m_adv_in_progress = false; +static volatile bool m_tx_in_progress = false; static ubluepy_gap_evt_callback_t ubluepy_gap_event_handler; static ubluepy_gatts_evt_callback_t ubluepy_gatts_event_handler; @@ -134,6 +157,40 @@ uint32_t ble_drv_stack_enable(void) { BLE_DRIVER_LOG("BLE enable status: " UINT_FMT "\n", (uint16_t)err_code); + // set up security mode + ble_gap_conn_params_t gap_conn_params; + ble_gap_conn_sec_mode_t sec_mode; + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); + + const char device_name[] = "micr"; + + err_code = sd_ble_gap_device_name_set(&sec_mode, + (const uint8_t *)device_name, + strlen(device_name)); + + if (sd_ble_gap_device_name_set(&sec_mode, + (const uint8_t *)device_name, + strlen(device_name)) != 0) { + + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Cannot set GAP parameters.")); + } + + // set connection parameters + memset(&gap_conn_params, 0, sizeof(gap_conn_params)); + + gap_conn_params.min_conn_interval = BLE_MIN_CONN_INTERVAL; + gap_conn_params.max_conn_interval = BLE_MAX_CONN_INTERVAL; + gap_conn_params.slave_latency = BLE_SLAVE_LATENCY; + gap_conn_params.conn_sup_timeout = BLE_CONN_SUP_TIMEOUT; + + if (sd_ble_gap_ppcp_set(&gap_conn_params) != 0) { + + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Cannot set PPCP parameters.")); + } + return err_code; } @@ -159,32 +216,15 @@ void ble_drv_address_get(void) { uint32_t err_code = sd_ble_gap_addr_get(&local_ble_addr); #endif BLE_DRIVER_LOG("ble address, type: " HEX2_FMT ", " \ - "address: " HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT ":" \ - HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT "\n", \ - local_ble_addr.addr_type, \ - local_ble_addr.addr[5], local_ble_addr.addr[4], local_ble_addr.addr[3], \ - local_ble_addr.addr[2], local_ble_addr.addr[1], local_ble_addr.addr[0]); + "address: " HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT ":" \ + HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT "\n", \ + local_ble_addr.addr_type, \ + local_ble_addr.addr[5], local_ble_addr.addr[4], local_ble_addr.addr[3], \ + local_ble_addr.addr[2], local_ble_addr.addr[1], local_ble_addr.addr[0]); (void)err_code; } -#define EDDYSTONE_UUID 0xFEAA // UUID for Eddystone beacons, Big Endian. - -// URL Frame Type, fixed at 0x10. -// RSSI, 0xEE = -18 dB is the approximate signal strength at 0 m. -// URL prefix, 0x00 = "http://www". -// URL -// URL suffix, 0x01 = ".com" -#define EDDYSTONE_DATA 0x10, 0xEE, 0x00, 'm', 'i', 'c', 'r', 'o', 'p', 'y', 't', 'h', 'o', 'n', 0x01 -#define BLE_ADV_LENGTH_FIELD_SIZE 1 -#define BLE_ADV_AD_TYPE_FIELD_SIZE 1 -#define BLE_AD_TYPE_FLAGS_DATA_SIZE 1 - -#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) -#define UNIT_0_625_MS (625) -#define APP_CFG_NON_CONN_ADV_TIMEOUT 0 // Disable timeout. -#define NON_CONNECTABLE_ADV_INTERVAL MSEC_TO_UNITS(100, UNIT_0_625_MS) - void ble_drv_advertise(void) { ble_uuid_t adv_uuids[] = {{.uuid = EDDYSTONE_UUID, .type = BLE_UUID_TYPE_BLE}}; uint8_t encoded_size; @@ -251,8 +291,7 @@ bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj) { if (sd_ble_gatts_service_add(p_service_obj->type, &uuid, - &p_service_obj->handle) != 0) - { + &p_service_obj->handle) != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not add Service.")); } @@ -264,8 +303,7 @@ bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj) { if (sd_ble_gatts_service_add(p_service_obj->type, &uuid, - &p_service_obj->handle) != 0) - { + &p_service_obj->handle) != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not add Service.")); } @@ -364,8 +402,8 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { if (sd_ble_gap_device_name_set(&sec_mode, p_adv_params->p_device_name, p_adv_params->device_name_len) != 0) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can not apply device name in the stack.")); + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not apply device name in the stack.")); } BLE_DRIVER_LOG("Device name applied\n"); @@ -581,9 +619,13 @@ void ble_drv_attr_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, ui hvx_params.p_len = &hvx_len; hvx_params.p_data = p_data; - uint32_t err_code = sd_ble_gatts_hvx(conn_handle, &hvx_params); + while (m_tx_in_progress) { + ; + } - if (err_code != 0) { + m_tx_in_progress = true; + uint32_t err_code; + if ((err_code = sd_ble_gatts_hvx(conn_handle, &hvx_params)) != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not notify attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); } @@ -611,6 +653,9 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { BLE_DRIVER_LOG("GAP CONNECT\n"); m_adv_in_progress = false; ubluepy_gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); + ble_gap_conn_params_t conn_params; + (void)sd_ble_gap_ppcp_get(&conn_params); + (void)sd_ble_gap_conn_param_update(p_ble_evt->evt.gap_evt.conn_handle, &conn_params); break; case BLE_GAP_EVT_DISCONNECTED: @@ -636,8 +681,23 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { BLE_DRIVER_LOG("GAP CONN PARAM UPDATE\n"); break; + case BLE_GATTS_EVT_SYS_ATTR_MISSING: + // No system attributes have been stored. + (void)sd_ble_gatts_sys_attr_set(p_ble_evt->evt.gatts_evt.conn_handle, NULL, 0, 0); + break; + + case BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST: + BLE_DRIVER_LOG("GATTS EVT EXCHANGE MTU REQUEST\n"); + (void)sd_ble_gatts_exchange_mtu_reply(p_ble_evt->evt.gatts_evt.conn_handle, 23); // MAX MTU size + break; + + case BLE_EVT_TX_COMPLETE: + BLE_DRIVER_LOG("BLE EVT TX COMPLETE\n"); + m_tx_in_progress = false; + break; + default: - BLE_DRIVER_LOG(">>> unhandled evt: 0x" HEX2_FMT, p_ble_evt->header.evt_id); + BLE_DRIVER_LOG(">>> unhandled evt: 0x" HEX2_FMT "\n", p_ble_evt->header.evt_id); break; } } From 382f718cfc1e4d41c61839ae20fd7fad2426d1cd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 27 Feb 2017 23:46:05 +0100 Subject: [PATCH 426/809] nrf5/sdk: Updating BLE UART implementation by swapping TX and RX uuid and characterisitic handling. Removed dummy write delay of 10 ms. --- nrf5/sdk/ble_uart.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/nrf5/sdk/ble_uart.c b/nrf5/sdk/ble_uart.c index f673ca20c3..8d675f11f2 100644 --- a/nrf5/sdk/ble_uart.c +++ b/nrf5/sdk/ble_uart.c @@ -40,13 +40,13 @@ static ubluepy_uuid_obj_t uuid_obj_service = { static ubluepy_uuid_obj_t uuid_obj_char_tx = { .base.type = &ubluepy_uuid_type, .type = UBLUEPY_UUID_128_BIT, - .value = {0x02, 0x00} + .value = {0x03, 0x00} }; static ubluepy_uuid_obj_t uuid_obj_char_rx = { .base.type = &ubluepy_uuid_type, .type = UBLUEPY_UUID_128_BIT, - .value = {0x03, 0x00} + .value = {0x02, 0x00} }; static ubluepy_service_obj_t ble_uart_service = { @@ -55,16 +55,16 @@ static ubluepy_service_obj_t ble_uart_service = { .type = UBLUEPY_SERVICE_PRIMARY }; -static ubluepy_characteristic_obj_t ble_uart_char_tx = { +static ubluepy_characteristic_obj_t ble_uart_char_rx = { .base.type = &ubluepy_characteristic_type, - .p_uuid = &uuid_obj_char_tx, + .p_uuid = &uuid_obj_char_rx, .props = UBLUEPY_PROP_WRITE | UBLUEPY_PROP_WRITE_WO_RESP, .attrs = 0, }; -static ubluepy_characteristic_obj_t ble_uart_char_rx = { +static ubluepy_characteristic_obj_t ble_uart_char_tx = { .base.type = &ubluepy_characteristic_type, - .p_uuid = &uuid_obj_char_rx, + .p_uuid = &uuid_obj_char_tx, .props = UBLUEPY_PROP_NOTIFY, .attrs = UBLUEPY_ATTR_CCCD, }; @@ -104,7 +104,7 @@ void mp_hal_stdout_tx_strn(const char *str, size_t len) { send_len = len; } - ubluepy_characteristic_obj_t * p_char = &ble_uart_char_rx; + ubluepy_characteristic_obj_t * p_char = &ble_uart_char_tx; ble_drv_attr_notify(p_char->p_service->p_periph->conn_handle, p_char->handle, @@ -119,8 +119,6 @@ void mp_hal_stdout_tx_strn(const char *str, size_t len) { void mp_hal_stdout_tx_strn_cooked(const char *str, mp_uint_t len) { for (uint8_t i = 0; i < len; i++) { mp_hal_stdout_tx_strn(&str[i], 1); - // for now put in a small delay as it could look like packets are issued to fast. - mp_hal_delay_ms(10); } } @@ -139,9 +137,9 @@ STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t at (void)self; if (event_id == 80) { // gatts write - if (ble_uart_char_rx.cccd_handle == attr_handle) { + if (ble_uart_char_tx.cccd_handle == attr_handle) { cccd_enabled = true; - } else if (ble_uart_char_tx.handle == attr_handle) { + } else if (ble_uart_char_rx.handle == attr_handle) { for (uint16_t i = 0; i < length; i++) { bufferWrite(mp_rx_ring_buffer, data[i]); } From 0e723091f9b4a787241aabfedfdccaa7ed754887 Mon Sep 17 00:00:00 2001 From: Bander Ajba Date: Tue, 28 Feb 2017 09:34:13 +0300 Subject: [PATCH 427/809] minor documentation and extra tabs removal fixes --- nrf5/hal/hal_temp.c | 4 ++-- nrf5/modules/machine/temp.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/hal/hal_temp.c b/nrf5/hal/hal_temp.c index fa08c25279..98b27ed725 100644 --- a/nrf5/hal/hal_temp.c +++ b/nrf5/hal/hal_temp.c @@ -36,8 +36,8 @@ void hal_temp_init(void) { } int32_t hal_temp_read(void) { - int32_t volatile temp; - hal_temp_init(); + int32_t volatile temp; + hal_temp_init(); NRF_TEMP->TASKS_START = 1; // Start the temperature measurement. diff --git a/nrf5/modules/machine/temp.c b/nrf5/modules/machine/temp.c index 1818784b65..a5b660c00f 100644 --- a/nrf5/modules/machine/temp.c +++ b/nrf5/modules/machine/temp.c @@ -46,7 +46,7 @@ STATIC void machine_temp_print(const mp_print_t *print, mp_obj_t o, mp_print_kin (void)self; - mp_printf(print, "Temp.read()"); + mp_printf(print, "Temp"); } /******************************************************************************/ From 216c97ff9ada99704abe15dc104d7b65ab07bafb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 28 Feb 2017 23:13:02 +0100 Subject: [PATCH 428/809] nrf5/sdk: Adding compiler guard around exchange MTU request event. As s110 is not having this event or function call to answer on a MTU exchange request, this is excluded for all other version than s132 for now. --- nrf5/sdk/ble_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index 59155ea823..13eca28569 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -686,10 +686,12 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { (void)sd_ble_gatts_sys_attr_set(p_ble_evt->evt.gatts_evt.conn_handle, NULL, 0, 0); break; +#if (BLUETOOTH_SD == 132) case BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST: BLE_DRIVER_LOG("GATTS EVT EXCHANGE MTU REQUEST\n"); (void)sd_ble_gatts_exchange_mtu_reply(p_ble_evt->evt.gatts_evt.conn_handle, 23); // MAX MTU size break; +#endif case BLE_EVT_TX_COMPLETE: BLE_DRIVER_LOG("BLE EVT TX COMPLETE\n"); From 9472196ee7b543b6a485a5c8d79f79e299816121 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 28 Feb 2017 23:18:31 +0100 Subject: [PATCH 429/809] nrf5: Force implementation of tx_str_cooked function if BLE NUS enabled. If BLE UART service has been enabled, the mp_hal_stdout_tx_strn_cooked is not defined by default anymore, and has to be implemented by the UART driver (in this case BLE). --- nrf5/mphalport.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/nrf5/mphalport.c b/nrf5/mphalport.c index b1accbc8f0..92c6d34af2 100644 --- a/nrf5/mphalport.c +++ b/nrf5/mphalport.c @@ -58,22 +58,20 @@ int mp_hal_stdin_rx_chr(void) { return 0; } -#endif -void mp_hal_stdout_tx_str(const char *str) { - mp_hal_stdout_tx_strn(str, strlen(str)); -} - -#if (MICROPY_PY_BLE_NUS == 0) void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) { if (MP_STATE_PORT(pyb_stdio_uart) != NULL) { uart_tx_strn(MP_STATE_PORT(pyb_stdio_uart), str, len); } } -#endif void mp_hal_stdout_tx_strn_cooked(const char *str, mp_uint_t len) { if (MP_STATE_PORT(pyb_stdio_uart) != NULL) { uart_tx_strn_cooked(MP_STATE_PORT(pyb_stdio_uart), str, len); } } +#endif + +void mp_hal_stdout_tx_str(const char *str) { + mp_hal_stdout_tx_strn(str, strlen(str)); +} From 84313b0261d08b47ed3f5acc3d1a6c89f8733547 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 28 Feb 2017 23:28:09 +0100 Subject: [PATCH 430/809] nrf5/sdk: Removing include of sdk_12.1.0's build.mk As no sources are needed from the SDK this build makefile can be deleted. --- nrf5/sdk/sdk_12.1.0/sdk.mk | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/sdk/sdk_12.1.0/sdk.mk b/nrf5/sdk/sdk_12.1.0/sdk.mk index 2c744f013d..69c314a0fb 100644 --- a/nrf5/sdk/sdk_12.1.0/sdk.mk +++ b/nrf5/sdk/sdk_12.1.0/sdk.mk @@ -1,8 +1,6 @@ INC += -I./$(SDK_MODULES_PATH) -include $(SDK_MODULES_PATH)build.mk - INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers/$(MCU_VARIANT) CFLAGS += -DBLUETOOTH_SD_DEBUG=1 From e8761682b797012f9f9aedd8d1df55c4bf714d15 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 28 Feb 2017 23:30:36 +0100 Subject: [PATCH 431/809] nrf5/sdk: Add ble_uart.c to source list ble_uart.c implements UART Bluetooth service on top of the bluetooth stack driver api calls. Can be enabled to be compiled in by defining MICROPY_PY_BLE_NUS = 1 in nrf5_sdk_conf.h. --- nrf5/sdk/sdk_common.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/nrf5/sdk/sdk_common.mk b/nrf5/sdk/sdk_common.mk index 183afc1f8a..e4609ba123 100644 --- a/nrf5/sdk/sdk_common.mk +++ b/nrf5/sdk/sdk_common.mk @@ -25,4 +25,5 @@ INC += -I./sdk SRC_C += \ sdk/modble.c \ - sdk/ble_drv.c + sdk/ble_drv.c \ + sdk/ble_uart.c From ac677efb8b54ffb7477bc76f4fae15a7132a4a42 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 28 Feb 2017 23:33:54 +0100 Subject: [PATCH 432/809] nrf5: Add default config for MICROPY_PY_BLE_NUS (0) Disable Bluetooth UART to be used for REPL by default. Can be overridden in nrf5_sdk_conf.h. It is defined in mpconfigport.h as it is connected to mphalport.c, where the config is used to determine whether default print functions should be using HW UART or Bluetooth UART. --- nrf5/mpconfigport.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 614c0d768c..903bb6848f 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -213,6 +213,10 @@ #define MICROPY_PY_UBLUEPY (0) #endif +#ifndef MICROPY_PY_BLE_NUS +#define MICROPY_PY_BLE_NUS (0) +#endif + // type definitions for the specific machine #define BYTES_PER_WORD (4) From 58cc59cfbe47fbbcb01484b6f5b98e9f3b49e1cb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 28 Feb 2017 23:40:46 +0100 Subject: [PATCH 433/809] nrf5/sdk: Removing ble_repl_linux.py Script does not really work very well with blocking char read and async ble notifications printing data when terminal stdout is blocked by readchar. Bluetooth UART profile implemented in ble_uart.c is now working with tralamazza's nus_console nodejs script. Ref: https://github.com/tralamazza/nus_console --- nrf5/sdk/sdk_12.1.0/ble_repl_linux.py | 46 --------------------------- 1 file changed, 46 deletions(-) delete mode 100644 nrf5/sdk/sdk_12.1.0/ble_repl_linux.py diff --git a/nrf5/sdk/sdk_12.1.0/ble_repl_linux.py b/nrf5/sdk/sdk_12.1.0/ble_repl_linux.py deleted file mode 100644 index 5e599fe85b..0000000000 --- a/nrf5/sdk/sdk_12.1.0/ble_repl_linux.py +++ /dev/null @@ -1,46 +0,0 @@ -from bluepy.btle import Scanner, DefaultDelegate, Peripheral, UUID -import struct - -class NotificationDelegate(DefaultDelegate): - def __init__(self): - DefaultDelegate.__init__(self) - - def handleNotification(self, cHandle, data): - print data - -def find_mac_by_name(name): - scanner = Scanner(iface=1) - devices = scanner.scan(5.0) - - found_device = None - for dev in devices: - print "Device %s (%s), RSSI=%d dB" % (dev.addr, dev.addrType, dev.rssi) - for (adtype, desc, value) in dev.getScanData(): - if (desc == "Short Local Name"): - if value == name: - found_device = dev - break - - if found_device: - break - return dev - -dev = find_mac_by_name("micr") -peri = Peripheral(dev) -peri.setDelegate(NotificationDelegate()) - -# service = peri.getServiceByUUID(UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e")) - -rx_char = peri.getCharacteristics(uuid=UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e"))[0] -tx_char = peri.getCharacteristics(uuid=UUID("6e400003-b5a3-f393-e0a9-e50e24dcca9e"))[0] - -# enable cccd -cccd = peri.writeCharacteristic(0x0e, struct.pack(' Date: Tue, 28 Feb 2017 23:57:08 +0100 Subject: [PATCH 434/809] nrf52: Removing folder to not confuse which folder is in development --- nrf52/.gitignore | 1 - nrf52/Makefile | 141 ------- nrf52/README.md | 46 --- nrf52/boards/D52Q/README.md | 3 - nrf52/boards/D52Q/build.mk | 5 - nrf52/boards/D52Q/d52q_board.c | 7 - nrf52/boards/D52Q/nrf52_board.h | 9 - nrf52/boards/PCA10040/README.md | 3 - nrf52/boards/PCA10040/build.mk | 7 - nrf52/boards/PCA10040/nrf52_board.h | 9 - nrf52/boards/PCA10040/pca10040_board.c | 7 - nrf52/gcc_nrf52_s132.ld | 23 -- nrf52/main.c | 59 --- nrf52/mods/build.mk | 4 - nrf52/mods/builtin.c | 54 --- nrf52/mp_functions.c | 21 - nrf52/mpconfigport.h | 95 ----- nrf52/mphalport.h | 2 - nrf52/nordic/.gitignore | 7 - nrf52/nordic/build.mk | 105 ----- nrf52/nordic/gcc_startup_nrf52.S | 524 ------------------------- nrf52/nrf52_app_error.c | 19 - nrf52/nrf52_ble.c | 481 ----------------------- nrf52/nrf52_ble.h | 4 - nrf52/pstorage_platform.h | 72 ---- nrf52/qstrdefsport.h | 0 26 files changed, 1708 deletions(-) delete mode 100644 nrf52/.gitignore delete mode 100644 nrf52/Makefile delete mode 100644 nrf52/README.md delete mode 100644 nrf52/boards/D52Q/README.md delete mode 100644 nrf52/boards/D52Q/build.mk delete mode 100644 nrf52/boards/D52Q/d52q_board.c delete mode 100644 nrf52/boards/D52Q/nrf52_board.h delete mode 100644 nrf52/boards/PCA10040/README.md delete mode 100644 nrf52/boards/PCA10040/build.mk delete mode 100644 nrf52/boards/PCA10040/nrf52_board.h delete mode 100644 nrf52/boards/PCA10040/pca10040_board.c delete mode 100644 nrf52/gcc_nrf52_s132.ld delete mode 100644 nrf52/main.c delete mode 100644 nrf52/mods/build.mk delete mode 100644 nrf52/mods/builtin.c delete mode 100644 nrf52/mp_functions.c delete mode 100644 nrf52/mpconfigport.h delete mode 100644 nrf52/mphalport.h delete mode 100644 nrf52/nordic/.gitignore delete mode 100644 nrf52/nordic/build.mk delete mode 100644 nrf52/nordic/gcc_startup_nrf52.S delete mode 100644 nrf52/nrf52_app_error.c delete mode 100644 nrf52/nrf52_ble.c delete mode 100644 nrf52/nrf52_ble.h delete mode 100644 nrf52/pstorage_platform.h delete mode 100644 nrf52/qstrdefsport.h diff --git a/nrf52/.gitignore b/nrf52/.gitignore deleted file mode 100644 index d16386367f..0000000000 --- a/nrf52/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build/ \ No newline at end of file diff --git a/nrf52/Makefile b/nrf52/Makefile deleted file mode 100644 index cd4251e1d4..0000000000 --- a/nrf52/Makefile +++ /dev/null @@ -1,141 +0,0 @@ -include ../py/mkenv.mk - -CROSS_COMPILE ?= arm-none-eabi- - -BTYPE ?= debug - -ifeq (${BTYPE}, release) -DEFINES += NDEBUG -CFLAGS += -Os -# CFLAGS += -flto -else -ifeq (${BTYPE}, debug) -DEBUG := 1 -DEFINES += DEBUG -CFLAGS += -Og -g -else -$(error Invalid BTYPE specified) -endif -endif - -BOARD ?= PCA10040 - -BUILD = build/${BOARD}/${BTYPE} - -LINKER_PATH = . -LINKER_SCRIPT = gcc_nrf52_s132.ld - -# don't set PROG as it's used by mkrules.mk -PROGRAM ?= ${BUILD}/firmware - -# qstr definitions (must come before including py.mk) -QSTR_DEFS = qstrdefsport.h - -# include py core make definitions -include ../py/py.mk - -ifeq ($(wildcard boards/${BOARD}/.),) -$(error Invalid BOARD specified) -else -# include board makefile (if any) --include boards/${BOARD}/build.mk -endif - -# include nordic makefile -include nordic/build.mk - -SRC_C += \ - main.c \ - mp_functions.c \ - nrf52_app_error.c \ - nrf52_ble.c \ - lib/mp-readline/readline.c \ - lib/utils/pyexec.c \ - lib/utils/stdout_helpers.c - -# XXX I simply copied gcc_startup_nrf52.s to .S so mkrules can compile it -OBJ += $(PY_O) $(addprefix ${BUILD}/, $(SRC_C:.c=.o)) - -INC += -I. -INC += -I.. -INC += -I${BUILD} -INC += -Iboards/${BOARD} -INC += -I../lib/mp-readline - -# transform all DEFINES entry in -DDEFINE c flags -CFLAGS += $(patsubst %,-D%,${DEFINES}) -CFLAGS += ${INC} -CFLAGS += -Wall -Werror -std=gnu99 -CFLAGS += -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -fsingle-precision-constant -CFLAGS += -ffunction-sections -fdata-sections -fno-strict-aliasing -CFLAGS += -fno-builtin --short-enums - -LDFLAGS += -Wl,-Map=${PROGRAM}.map -LDFLAGS += -mthumb -mabi=aapcs -L${LINKER_PATH} -T${LINKER_SCRIPT} -LDFLAGS += -mcpu=cortex-m4 -LDFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16 -LDFLAGS += -Wl,--gc-sections -LDFLAGS += --specs=nano.specs -lc -lnosys - -# mkenv doesn't set these -OBJDUMP = $(CROSS_COMPILE)objdump -GDB = $(CROSS_COMPILE)gdb - - -all: ${PROGRAM}.hex ${PROGRAM}.bin -.PHONY: all - -${PROGRAM}.elf: ${OBJ} - $(ECHO) "LINK $@" - ${Q}${CC} -o $@ ${CFLAGS} ${LDFLAGS} $^ ${LDLIBS} -ifndef DEBUG - ${Q}$(STRIP) $(STRIPFLAGS_EXTRA) $@ -endif - ${Q}$(SIZE) $@ - -%.hex: %.elf - ${Q}${OBJCOPY} -O ihex $< $@ - -%.bin: %.elf - ${Q}${OBJCOPY} -O binary $< $@ - -%.jlink: %.hex - ${OBJDUMP} -h $< | \ - awk '$$1 ~ /^[0-9]+$$/ {addr="0x"$$5; if (!min || addr < min) min = addr} END { printf "\ - loadbin %s,%s\n\ - sleep 100\n\ - r\n\ - g\n\ - exit\n", f, min}' f="$<" > $@ - -%-all.jlink: %.jlink ${SOFTDEV_HEX} - @[ -e "${SOFTDEV_HEX}" ] || echo "cannot find softdevice hex image '${SOFTDEV_HEX}'" >&2 - # w4 0x4001e504, 0x2 -> enable erase: CONFIG.WEN = EEN - # w4 0x4001e50c, 0x1 -> erase all: ERASEALL = 1 - printf "\ - device nrf52\n\ - halt\n\ - w4 0x4001e504, 0x2\n\ - w4 0x4001e50c, 0x1\n\ - sleep 100\n\ - r\n\ - loadbin %s,0\n" ${SOFTDEV_HEX} > $@ - cat $< >> $@ - -flash: ${PROGRAM}.hex ${PROGRAM}.jlink - JLinkExe -device nrf52 -if SWD ${PROGRAM}.jlink -.PHONY: flash - -flash-all: ${PROGRAM}.hex ${PROGRAM}-all.jlink - JLinkExe -device nrf52 -if SWD ${PROGRAM}-all.jlink -.PHONY: flash-all - -gdbserver: ${PROGRAM}.elf - JLinkGDBServer -device nrf52 -if SWD -.PHONY: gdbserver - -gdb: ${PROGRAM}.elf - ${GDB} ${PROGRAM}.elf -ex 'target remote :2331' -.PHONY: gdb - -include ../py/mkrules.mk diff --git a/nrf52/README.md b/nrf52/README.md deleted file mode 100644 index 8ff64ed02b..0000000000 --- a/nrf52/README.md +++ /dev/null @@ -1,46 +0,0 @@ -# nRF52 Port - -WIP - -## requirements - -- GNU make -- ARM GCC for embedded development -- JLink Segger command line tools -- Download and unzip the Nordic SDK 11 under `nordic/` - - -## quickstart - -Plug your board and type: - - $> make flash-all - - -## debugging - - $> make gdbserver - -in another terminal - - $> make gdb - -in yet another terminal (for the RTT messages) - - $> telnet 127.0.0.1 19021 - - -## TODO - -- BLE peripheral - - Advertisement - - Manage services/characteristics - - Notifications/Indications -- HAL - - UART - - TWI - - SPI - - ADC - - Flash - - GPIO - - I2S \ No newline at end of file diff --git a/nrf52/boards/D52Q/README.md b/nrf52/boards/D52Q/README.md deleted file mode 100644 index 9ede1e781e..0000000000 --- a/nrf52/boards/D52Q/README.md +++ /dev/null @@ -1,3 +0,0 @@ -# Dynasteam D52Q dev board - -(insert picture) \ No newline at end of file diff --git a/nrf52/boards/D52Q/build.mk b/nrf52/boards/D52Q/build.mk deleted file mode 100644 index 4e331ce75a..0000000000 --- a/nrf52/boards/D52Q/build.mk +++ /dev/null @@ -1,5 +0,0 @@ - -D52Q_SRC_C += \ - d52q_board.c - -OBJ += $(addprefix ${BUILD}/boards/D52Q/, $(D52Q_SRC_C:.c=.o)) diff --git a/nrf52/boards/D52Q/d52q_board.c b/nrf52/boards/D52Q/d52q_board.c deleted file mode 100644 index 438f09a0df..0000000000 --- a/nrf52/boards/D52Q/d52q_board.c +++ /dev/null @@ -1,7 +0,0 @@ -#include "nrf52_board.h" - - -void -nrf52_board_init(void) -{ -} diff --git a/nrf52/boards/D52Q/nrf52_board.h b/nrf52/boards/D52Q/nrf52_board.h deleted file mode 100644 index 8d20b72844..0000000000 --- a/nrf52/boards/D52Q/nrf52_board.h +++ /dev/null @@ -1,9 +0,0 @@ -#pragma once - -#include "nrf_sdm.h" - -// Low frequency clock source to be used by the SoftDevice -#define NRF_CLOCK_LFCLKSRC {.source = NRF_CLOCK_LF_SRC_XTAL, \ - .rc_ctiv = 0, \ - .rc_temp_ctiv = 0, \ - .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM} diff --git a/nrf52/boards/PCA10040/README.md b/nrf52/boards/PCA10040/README.md deleted file mode 100644 index e6bf1f8f51..0000000000 --- a/nrf52/boards/PCA10040/README.md +++ /dev/null @@ -1,3 +0,0 @@ -# Nordic nRF52 DK - -[Link](https://www.nordicsemi.com/eng/Products/Bluetooth-low-energy/nRF52-DK) \ No newline at end of file diff --git a/nrf52/boards/PCA10040/build.mk b/nrf52/boards/PCA10040/build.mk deleted file mode 100644 index b6b3acd79e..0000000000 --- a/nrf52/boards/PCA10040/build.mk +++ /dev/null @@ -1,7 +0,0 @@ - -PCA10040_SRC_C += \ - pca10040_board.c - -OBJ += $(addprefix ${BUILD}/boards/PCA10040/, $(PCA10040_SRC_C:.c=.o)) - -DEFINES += BOARD_PCA10040 diff --git a/nrf52/boards/PCA10040/nrf52_board.h b/nrf52/boards/PCA10040/nrf52_board.h deleted file mode 100644 index 8d20b72844..0000000000 --- a/nrf52/boards/PCA10040/nrf52_board.h +++ /dev/null @@ -1,9 +0,0 @@ -#pragma once - -#include "nrf_sdm.h" - -// Low frequency clock source to be used by the SoftDevice -#define NRF_CLOCK_LFCLKSRC {.source = NRF_CLOCK_LF_SRC_XTAL, \ - .rc_ctiv = 0, \ - .rc_temp_ctiv = 0, \ - .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM} diff --git a/nrf52/boards/PCA10040/pca10040_board.c b/nrf52/boards/PCA10040/pca10040_board.c deleted file mode 100644 index 438f09a0df..0000000000 --- a/nrf52/boards/PCA10040/pca10040_board.c +++ /dev/null @@ -1,7 +0,0 @@ -#include "nrf52_board.h" - - -void -nrf52_board_init(void) -{ -} diff --git a/nrf52/gcc_nrf52_s132.ld b/nrf52/gcc_nrf52_s132.ld deleted file mode 100644 index 02585fe969..0000000000 --- a/nrf52/gcc_nrf52_s132.ld +++ /dev/null @@ -1,23 +0,0 @@ -/* Linker script to configure memory regions. */ - -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x1c000, LENGTH = 0x64000 - RAM (rwx) : ORIGIN = 0x20002080, LENGTH = 0xdf80 -} - -SECTIONS -{ - .fs_data : - { - PROVIDE(__start_fs_data = .); - KEEP(*(.fs_data)) - PROVIDE(__stop_fs_data = .); - } > RAM -} INSERT AFTER .data; - -/* found in the nordic SDK components/toolchain/gcc */ -INCLUDE "nrf5x_common.ld" diff --git a/nrf52/main.c b/nrf52/main.c deleted file mode 100644 index 9bc4177767..0000000000 --- a/nrf52/main.c +++ /dev/null @@ -1,59 +0,0 @@ -#include "py/nlr.h" -#include "py/compile.h" -#include "py/runtime.h" -#include "py/repl.h" -#include "py/gc.h" -#include "lib/utils/pyexec.h" - -#include "nrf52_board.h" -#include "nrf52_ble.h" - -static char *stack_top; -static char heap[4 * 1024]; - -void nrf52_board_init(void); - -void -gc_collect(void) -{ - // WARNING: This gc_collect implementation doesn't try to get root - // pointers from CPU registers, and thus may function incorrectly. - void *dummy; - gc_collect_start(); - gc_collect_root(&dummy, ((mp_uint_t)stack_top - (mp_uint_t)&dummy) / sizeof(mp_uint_t)); - gc_collect_end(); - gc_dump_info(); -} - -int -main(int argc, char **argv) -{ - int stack_dummy; - stack_top = (char*)&stack_dummy; - - #if MICROPY_ENABLE_GC - gc_init(heap, heap + sizeof(heap)); - #endif - - nrf52_board_init(); - nrf52_ble_init(); - - mp_init(); - - #if MICROPY_REPL_EVENT_DRIVEN - pyexec_event_repl_init(); - for (;;) { - int c = mp_hal_stdin_rx_chr(); - if (pyexec_event_repl_process_char(c)) { - break; - } - } - #else - pyexec_friendly_repl(); - #endif - - mp_deinit(); - - NVIC_SystemReset(); - return 0; -} diff --git a/nrf52/mods/build.mk b/nrf52/mods/build.mk deleted file mode 100644 index 13b2d7acdf..0000000000 --- a/nrf52/mods/build.mk +++ /dev/null @@ -1,4 +0,0 @@ -MODS_SRC_C += \ - builtin.c - -OBJ += $(addprefix ${BUILD}/mods/, $(MODS_SRC_C:.c=.o)) diff --git a/nrf52/mods/builtin.c b/nrf52/mods/builtin.c deleted file mode 100644 index 0dfaff1a93..0000000000 --- a/nrf52/mods/builtin.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2013, 2014 Damien P. George - * Copyright (c) 2015 Daniel Campora - * Copyright (c) 2016 Daniel Tralamazza - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "lib/utils/pyhelp.h" -#include "py/runtime.h" -#include "extmod/vfs_fat_file.h" -#include "py/mphal.h" - -// MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, fatfs_builtin_open); - - -STATIC const char help_text[] = "Welcome to MicroPython!\n" - "For online help please visit http://micropython.org/help/.\n" - "For further help on a specific object, type help(obj)\n"; - -STATIC mp_obj_t pyb_help(uint n_args, const mp_obj_t *args) { - if (n_args == 0) { - // print a general help message - mp_hal_stdout_tx_str(help_text); - } - else { - // try to print something sensible about the given object - pyhelp_print_obj(args[0]); - } - return mp_const_none; -} -MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_builtin_help_obj, 0, 1, pyb_help); diff --git a/nrf52/mp_functions.c b/nrf52/mp_functions.c deleted file mode 100644 index 1c217809fe..0000000000 --- a/nrf52/mp_functions.c +++ /dev/null @@ -1,21 +0,0 @@ -// NOTE: the objective is to move these functions to their respective final implementations - -#include "py/obj.h" -#include "py/lexer.h" - -void nlr_jump_fail(void *val) { -} - - -mp_import_stat_t mp_import_stat(const char *path) { - return MP_IMPORT_STAT_NO_EXIST; -} - -mp_lexer_t *mp_lexer_new_from_file(const char *filename) { - return NULL; -} - -mp_obj_t mp_builtin_open(uint n_args, const mp_obj_t *args, mp_map_t *kwargs) { - return mp_const_none; -} -MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open); diff --git a/nrf52/mpconfigport.h b/nrf52/mpconfigport.h deleted file mode 100644 index 346876b7d9..0000000000 --- a/nrf52/mpconfigport.h +++ /dev/null @@ -1,95 +0,0 @@ -#include - -// options to control how Micro Python is built - -#define MICROPY_QSTR_BYTES_IN_HASH (1) -// #define MICROPY_QSTR_EXTRA_POOL mp_qstr_frozen_const_pool -#define MICROPY_ALLOC_PATH_MAX (256) -#define MICROPY_ALLOC_PARSE_CHUNK_INIT (16) -#define MICROPY_EMIT_X64 (0) -#define MICROPY_EMIT_THUMB (0) -#define MICROPY_EMIT_INLINE_THUMB (0) -#define MICROPY_COMP_MODULE_CONST (0) -#define MICROPY_COMP_CONST (0) -#define MICROPY_COMP_DOUBLE_TUPLE_ASSIGN (0) -#define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0) -#define MICROPY_MEM_STATS (0) -#define MICROPY_DEBUG_PRINTERS (0) -#define MICROPY_ENABLE_GC (1) -#define MICROPY_REPL_EVENT_DRIVEN (0) -#define MICROPY_HELPER_REPL (1) -#define MICROPY_HELPER_LEXER_UNIX (0) -#define MICROPY_ENABLE_SOURCE_LINE (0) -#define MICROPY_ENABLE_DOC_STRING (0) -#define MICROPY_ERROR_REPORTING (MICROPY_ERROR_REPORTING_TERSE) -#define MICROPY_BUILTIN_METHOD_CHECK_SELF_ARG (0) -#define MICROPY_PY_ASYNC_AWAIT (0) -#define MICROPY_PY_BUILTINS_BYTEARRAY (0) -#define MICROPY_PY_BUILTINS_MEMORYVIEW (0) -#define MICROPY_PY_BUILTINS_ENUMERATE (0) -#define MICROPY_PY_BUILTINS_FILTER (0) -#define MICROPY_PY_BUILTINS_FROZENSET (0) -#define MICROPY_PY_BUILTINS_REVERSED (0) -#define MICROPY_PY_BUILTINS_SET (0) -#define MICROPY_PY_BUILTINS_SLICE (0) -#define MICROPY_PY_BUILTINS_PROPERTY (0) -#define MICROPY_PY_BUILTINS_MIN_MAX (0) -#define MICROPY_PY___FILE__ (0) -#define MICROPY_PY_GC (0) -#define MICROPY_PY_ARRAY (0) -#define MICROPY_PY_ATTRTUPLE (0) -#define MICROPY_PY_COLLECTIONS (0) -#define MICROPY_PY_MATH (0) -#define MICROPY_PY_CMATH (0) -#define MICROPY_PY_IO (0) -#define MICROPY_PY_STRUCT (0) -#define MICROPY_PY_SYS (0) -#define MICROPY_MODULE_FROZEN_MPY (0) -#define MICROPY_CPYTHON_COMPAT (0) -#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_NONE) -#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_NONE) - -// type definitions for the specific machine - -#define BYTES_PER_WORD (4) - -#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1)) - -// This port is intended to be 32-bit, but unfortunately, int32_t for -// different targets may be defined in different ways - either as int -// or as long. This requires different printf formatting specifiers -// to print such value. So, we avoid int32_t and use int directly. -#define UINT_FMT "%u" -#define INT_FMT "%d" -typedef int mp_int_t; // must be pointer size -typedef unsigned mp_uint_t; // must be pointer size - -typedef void *machine_ptr_t; // must be of pointer size -typedef const void *machine_const_ptr_t; // must be of pointer size -typedef long mp_off_t; - -#define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len) - -// extra built in names to add to the global namespace -#define MICROPY_PORT_BUILTINS \ - { MP_OBJ_NEW_QSTR(MP_QSTR_open), (mp_obj_t)&mp_builtin_open_obj }, - -// We need to provide a declaration/definition of alloca() -#include - -#define MICROPY_HW_BOARD_NAME "minimal" -#define MICROPY_HW_MCU_NAME "NRF52832" - -#ifdef __linux__ -#define MICROPY_MIN_USE_STDOUT (1) -#endif - -#ifdef __thumb__ -#define MICROPY_MIN_USE_CORTEX_CPU (1) -#define MICROPY_MIN_USE_STM32_MCU (1) -#endif - -#define MP_STATE_PORT MP_STATE_VM - -#define MICROPY_PORT_ROOT_POINTERS \ - const char *readline_hist[8]; diff --git a/nrf52/mphalport.h b/nrf52/mphalport.h deleted file mode 100644 index 60d68bd2d6..0000000000 --- a/nrf52/mphalport.h +++ /dev/null @@ -1,2 +0,0 @@ -static inline mp_uint_t mp_hal_ticks_ms(void) { return 0; } -static inline void mp_hal_set_interrupt_char(char c) {} diff --git a/nrf52/nordic/.gitignore b/nrf52/nordic/.gitignore deleted file mode 100644 index 7d72dd27b9..0000000000 --- a/nrf52/nordic/.gitignore +++ /dev/null @@ -1,7 +0,0 @@ -# Ignore everything in this directory -* - -# Except -!.gitignore -!build.mk -!gcc_startup_nrf52.S \ No newline at end of file diff --git a/nrf52/nordic/build.mk b/nrf52/nordic/build.mk deleted file mode 100644 index 4c9a6a6268..0000000000 --- a/nrf52/nordic/build.mk +++ /dev/null @@ -1,105 +0,0 @@ -# this file's folder -SDK_DIR := $(abspath $(dir $(lastword ${MAKEFILE_LIST}))) - -# -D in CFLAGS -DEFINES += __HEAP_SIZE=0 -DEFINES += BLE_STACK_SUPPORT_REQD -DEFINES += CONFIG_GPIO_AS_PINRESET -DEFINES += NRF52 -DEFINES += NRF52_PAN_12 -DEFINES += NRF52_PAN_15 -DEFINES += NRF52_PAN_20 -DEFINES += NRF52_PAN_30 -DEFINES += NRF52_PAN_31 -DEFINES += NRF52_PAN_36 -DEFINES += NRF52_PAN_51 -DEFINES += NRF52_PAN_53 -DEFINES += NRF52_PAN_54 -DEFINES += NRF52_PAN_55 -DEFINES += NRF52_PAN_58 -DEFINES += NRF52_PAN_62 -DEFINES += NRF52_PAN_63 -DEFINES += NRF52_PAN_64 -DEFINES += S132 -DEFINES += SOFTDEVICE_PRESENT -DEFINES += SWI_DISABLE0 - -# nordic SDK C sources (relative path) -SDK_SRC_C += \ - components/ble/ble_advertising/ble_advertising.c \ - components/ble/ble_services/ble_nus/ble_nus.c \ - components/ble/common/ble_advdata.c \ - components/ble/common/ble_conn_params.c \ - components/ble/common/ble_conn_state.c \ - components/ble/common/ble_srv_common.c \ - components/ble/peer_manager/gatt_cache_manager.c \ - components/ble/peer_manager/gattc_cache_manager.c \ - components/ble/peer_manager/gatts_cache_manager.c \ - components/ble/peer_manager/id_manager.c \ - components/ble/peer_manager/peer_data.c \ - components/ble/peer_manager/peer_data_storage.c \ - components/ble/peer_manager/peer_database.c \ - components/ble/peer_manager/peer_id.c \ - components/ble/peer_manager/peer_manager.c \ - components/ble/peer_manager/pm_buffer.c \ - components/ble/peer_manager/pm_mutex.c \ - components/ble/peer_manager/security_dispatcher.c \ - components/ble/peer_manager/security_manager.c \ - components/drivers_nrf/delay/nrf_delay.c \ - components/drivers_nrf/pstorage/pstorage.c \ - components/libraries/fds/fds.c \ - components/libraries/fifo/app_fifo.c \ - components/libraries/fstorage/fstorage.c \ - components/libraries/timer/app_timer.c \ - components/libraries/util/app_util_platform.c \ - components/libraries/util/sdk_mapped_flags.c \ - components/softdevice/common/softdevice_handler/softdevice_handler.c \ - components/toolchain/system_nrf52.c - -# add segger RTT -ifeq (${BTYPE}, debug) -DEFINES += USE_RTT -SDK_SRC_C += \ - external/segger_rtt/RTT_Syscalls_GCC.c \ - external/segger_rtt/SEGGER_RTT.c \ - external/segger_rtt/SEGGER_RTT_printf.c -endif - -# # nordic SDK ASM sources (relative path) -# SDK_SRC_ASM += \ -# components/toolchain/gcc/gcc_startup_nrf52.s - -# include source folders (sort removes duplicates) -SDK_INC_DIRS += $(sort $(dir ${SDK_SRC_C})) -# ble.h -SDK_INC_DIRS += components/softdevice/s132/headers -# nrf52.h compiler_abstraction.h -SDK_INC_DIRS += components/device -# core_cm4.h -SDK_INC_DIRS += components/toolchain/CMSIS/Include -# section_vars.h -SDK_INC_DIRS += components/libraries/experimental_section_vars -# fstorage_config.h -SDK_INC_DIRS += components/libraries/fstorage/config -# nrf_drv_config.h -SDK_INC_DIRS += components/drivers_nrf/config -# app_util.h -SDK_INC_DIRS += components/libraries/util -# fds_config.h -SDK_INC_DIRS += components/libraries/fds/config - -# include full path -INC += $(patsubst %,-I${SDK_DIR}/%, ${SDK_INC_DIRS}) - -# object folder -NORDIC_BUILD = ${BUILD}/nordic - -OBJ += $(addprefix ${NORDIC_BUILD}/, $(SDK_SRC_C:.c=.o)) -# OBJ += $(addprefix ${NORDIC_BUILD}/, $(SDK_SRC_ASM:.s=.o)) -OBJ += ${NORDIC_BUILD}/gcc_startup_nrf52.o - -# linker script folder -LDFLAGS += -L${SDK_DIR}/components/toolchain/gcc - -# softdevice .hex file -SOFTDEV_HEX ?= $(lastword $(wildcard nordic/components/softdevice/s132/hex/s132*softdevice.hex)) diff --git a/nrf52/nordic/gcc_startup_nrf52.S b/nrf52/nordic/gcc_startup_nrf52.S deleted file mode 100644 index 995771c50a..0000000000 --- a/nrf52/nordic/gcc_startup_nrf52.S +++ /dev/null @@ -1,524 +0,0 @@ -/* Copyright (c) 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - .syntax unified - .arch armv7e-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 8192 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 8192 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler - .long NMI_Handler - .long HardFault_Handler - .long MemoryManagement_Handler - .long BusFault_Handler - .long UsageFault_Handler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long SVC_Handler - .long DebugMonitor_Handler - .long 0 /*Reserved */ - .long PendSV_Handler - .long SysTick_Handler - - /* External Interrupts */ - .long POWER_CLOCK_IRQHandler - .long RADIO_IRQHandler - .long UARTE0_UART0_IRQHandler - .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .long NFCT_IRQHandler - .long GPIOTE_IRQHandler - .long SAADC_IRQHandler - .long TIMER0_IRQHandler - .long TIMER1_IRQHandler - .long TIMER2_IRQHandler - .long RTC0_IRQHandler - .long TEMP_IRQHandler - .long RNG_IRQHandler - .long ECB_IRQHandler - .long CCM_AAR_IRQHandler - .long WDT_IRQHandler - .long RTC1_IRQHandler - .long QDEC_IRQHandler - .long COMP_LPCOMP_IRQHandler - .long SWI0_EGU0_IRQHandler - .long SWI1_EGU1_IRQHandler - .long SWI2_EGU2_IRQHandler - .long SWI3_EGU3_IRQHandler - .long SWI4_EGU4_IRQHandler - .long SWI5_EGU5_IRQHandler - .long TIMER3_IRQHandler - .long TIMER4_IRQHandler - .long PWM0_IRQHandler - .long PDM_IRQHandler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long MWU_IRQHandler - .long PWM1_IRQHandler - .long PWM2_IRQHandler - .long SPIM2_SPIS2_SPI2_IRQHandler - .long RTC2_IRQHandler - .long I2S_IRQHandler - .long FPU_IRQHandler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - 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Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - - subs r3, r2 - ble .L_loop1_done - -.L_loop1: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 - -.L_loop1_done: - -/* This part of work usually is done in C library startup code. Otherwise, - * define __STARTUP_CLEAR_BSS to enable it in this startup. This section - * clears the RAM where BSS data is located. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * All addresses must be aligned to 4 bytes boundary. - */ -#ifdef __STARTUP_CLEAR_BSS - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 - - subs r2, r1 - ble .L_loop3_done - -.L_loop3: - subs r2, #4 - str r0, [r1, r2] - bgt .L_loop3 - -.L_loop3_done: -#endif /* __STARTUP_CLEAR_BSS */ - -/* Execute SystemInit function. */ - bl SystemInit - -/* Call _start function provided by libraries. - * If those libraries are not accessible, define __START as your entry point. - */ -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler,.-Reset_Handler - - .section ".text" - - -/* Dummy Exception Handlers (infinite loops which can be modified) */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - b . - .size NMI_Handler, . - NMI_Handler - - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - b . - .size HardFault_Handler, . - HardFault_Handler - - - .weak MemoryManagement_Handler - .type MemoryManagement_Handler, %function -MemoryManagement_Handler: - b . - .size MemoryManagement_Handler, . - MemoryManagement_Handler - - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - b . - .size BusFault_Handler, . - BusFault_Handler - - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - b . - .size UsageFault_Handler, . - UsageFault_Handler - - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - - .weak DebugMonitor_Handler - .type DebugMonitor_Handler, %function -DebugMonitor_Handler: - b . - .size DebugMonitor_Handler, . - DebugMonitor_Handler - - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - b . - .size PendSV_Handler, . - PendSV_Handler - - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - b . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ POWER_CLOCK_IRQHandler - IRQ RADIO_IRQHandler - IRQ UARTE0_UART0_IRQHandler - IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - IRQ NFCT_IRQHandler - IRQ GPIOTE_IRQHandler - IRQ SAADC_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ RTC0_IRQHandler - IRQ TEMP_IRQHandler - IRQ RNG_IRQHandler - IRQ ECB_IRQHandler - IRQ CCM_AAR_IRQHandler - IRQ WDT_IRQHandler - IRQ RTC1_IRQHandler - IRQ QDEC_IRQHandler - IRQ COMP_LPCOMP_IRQHandler - IRQ SWI0_EGU0_IRQHandler - IRQ SWI1_EGU1_IRQHandler - IRQ SWI2_EGU2_IRQHandler - IRQ SWI3_EGU3_IRQHandler - IRQ SWI4_EGU4_IRQHandler - IRQ SWI5_EGU5_IRQHandler - IRQ TIMER3_IRQHandler - IRQ TIMER4_IRQHandler - IRQ PWM0_IRQHandler - IRQ PDM_IRQHandler - IRQ MWU_IRQHandler - IRQ PWM1_IRQHandler - IRQ PWM2_IRQHandler - IRQ SPIM2_SPIS2_SPI2_IRQHandler - IRQ RTC2_IRQHandler - IRQ I2S_IRQHandler - IRQ FPU_IRQHandler - - .end diff --git a/nrf52/nrf52_app_error.c b/nrf52/nrf52_app_error.c deleted file mode 100644 index 5775a3e3a3..0000000000 --- a/nrf52/nrf52_app_error.c +++ /dev/null @@ -1,19 +0,0 @@ -#include -#include "app_error.h" - - -void -#ifdef DEBUG -app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) -#else -app_error_handler_bare(ret_code_t error_code) -#endif -{ -#ifdef DEBUG - for (;;) { - /* FOREVER */ - } -#else - NVIC_SystemReset(); -#endif -} diff --git a/nrf52/nrf52_ble.c b/nrf52/nrf52_ble.c deleted file mode 100644 index 386e601f30..0000000000 --- a/nrf52/nrf52_ble.c +++ /dev/null @@ -1,481 +0,0 @@ -#include "nrf52_ble.h" -#include "nrf52_board.h" - -#include "app_error.h" -#include "app_fifo.h" -#include "app_timer.h" -#include "ble_advertising.h" -#include "ble_conn_params.h" -#include "ble_conn_state.h" -#include "ble_hci.h" -#include "ble_nus.h" -#include "ble_srv_common.h" -#include "fds.h" -#include "fds.h" -#include "fstorage.h" -#include "peer_manager.h" -#include "softdevice_handler.h" - - -#define CENTRAL_LINK_COUNT 0 /**< Number of central links used by the application. When changing this number remember to adjust the RAM settings*/ -#define PERIPHERAL_LINK_COUNT 1 /**< Number of peripheral links used by the application. When changing this number remember to adjust the RAM settings*/ - -#define DEVICE_NAME "micropython" - -#define MIN_CONN_INTERVAL MSEC_TO_UNITS(20, UNIT_1_25_MS) /**< Minimum acceptable connection interval (0.02 seconds). */ -#define MAX_CONN_INTERVAL MSEC_TO_UNITS(200, UNIT_1_25_MS) /**< Maximum acceptable connection interval (0.2 second). */ -#define SLAVE_LATENCY 0 /**< Slave latency. */ -#define CONN_SUP_TIMEOUT MSEC_TO_UNITS(3000, UNIT_10_MS) /**< Connection supervisory timeout (3 seconds). */ - -#define APP_ADV_INTERVAL MSEC_TO_UNITS(25, UNIT_0_625_MS) -#define APP_ADV_TIMEOUT_IN_SECONDS 180 - -#define APP_TIMER_PRESCALER 0 /**< Value of the RTC1 PRESCALER register. */ -#define APP_TIMER_OP_QUEUE_SIZE 4 /**< Size of timer operation queues. */ - -#define FIRST_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(5000, APP_TIMER_PRESCALER) /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (5 seconds). */ -#define NEXT_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(30000, APP_TIMER_PRESCALER) /**< Time between each call to sd_ble_gap_conn_param_update after the first call (30 seconds). */ -#define MAX_CONN_PARAMS_UPDATE_COUNT 3 - -#define SEC_PARAM_BOND 1 /**< Perform bonding. */ -#define SEC_PARAM_MITM 0 /**< Man In The Middle protection not required. */ -#define SEC_PARAM_LESC 0 /**< LE Secure Connections not enabled. */ -#define SEC_PARAM_KEYPRESS 0 /**< Keypress notifications not enabled. */ -#define SEC_PARAM_IO_CAPABILITIES BLE_GAP_IO_CAPS_NONE /**< No I/O capabilities. */ -#define SEC_PARAM_OOB 0 /**< Out Of Band data not available. */ -#define SEC_PARAM_MIN_KEY_SIZE 7 /**< Minimum encryption key size. */ -#define SEC_PARAM_MAX_KEY_SIZE 16 /**< Maximum encryption key size. */ - -#define NUS_RX_FIFO_BUFFER_SIZE 64 - -static ble_uuid_t m_adv_uuids[] = {{BLE_UUID_NUS_SERVICE, 0}}; /**< Universally unique service identifiers. */ - -static ble_nus_t m_nus; -static app_fifo_t m_nus_rx_fifo; -static uint8_t m_nus_rx_fifo_buffer[NUS_RX_FIFO_BUFFER_SIZE]; - - -static void -ble_evt_dispatch(ble_evt_t * p_ble_evt) -{ - ble_conn_state_on_ble_evt(p_ble_evt); - pm_on_ble_evt(p_ble_evt); - ble_conn_params_on_ble_evt(p_ble_evt); - ble_advertising_on_ble_evt(p_ble_evt); - ble_nus_on_ble_evt(&m_nus, p_ble_evt); -} - -static void -sys_evt_dispatch(uint32_t sys_evt) -{ - fs_sys_event_handler(sys_evt); - ble_advertising_on_sys_evt(sys_evt); -} - -static void -ble_stack_init(void) -{ - nrf_clock_lf_cfg_t clock_lf_cfg = NRF_CLOCK_LFCLKSRC; - - // Initialize the SoftDevice handler module. - SOFTDEVICE_HANDLER_INIT(&clock_lf_cfg, NULL); - - ble_enable_params_t ble_enable_params; - uint32_t err_code = softdevice_enable_get_default_config(CENTRAL_LINK_COUNT, - PERIPHERAL_LINK_COUNT, - &ble_enable_params); - APP_ERROR_CHECK(err_code); - - //Check the ram settings against the used number of links - CHECK_RAM_START_ADDR(CENTRAL_LINK_COUNT, PERIPHERAL_LINK_COUNT); - - // Enable BLE stack. - err_code = softdevice_enable(&ble_enable_params); - APP_ERROR_CHECK(err_code); - - // Register with the SoftDevice handler module for BLE events. - err_code = softdevice_ble_evt_handler_set(ble_evt_dispatch); - APP_ERROR_CHECK(err_code); - - // Register with the SoftDevice handler module for BLE events. - err_code = softdevice_sys_evt_handler_set(sys_evt_dispatch); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for the GAP initialization. - * - * @details This function sets up all the necessary GAP (Generic Access Profile) parameters of the - * device including the device name, appearance, and the preferred connection parameters. - */ -static void -gap_params_init(void) -{ - uint32_t err_code; - ble_gap_conn_params_t gap_conn_params; - ble_gap_conn_sec_mode_t sec_mode; - - BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); - - err_code = sd_ble_gap_device_name_set(&sec_mode, - (const uint8_t *)DEVICE_NAME, - strlen(DEVICE_NAME)); - APP_ERROR_CHECK(err_code); - - err_code = sd_ble_gap_appearance_set(BLE_APPEARANCE_UNKNOWN); - APP_ERROR_CHECK(err_code); - - memset(&gap_conn_params, 0, sizeof(gap_conn_params)); - - gap_conn_params.min_conn_interval = MIN_CONN_INTERVAL; - gap_conn_params.max_conn_interval = MAX_CONN_INTERVAL; - gap_conn_params.slave_latency = SLAVE_LATENCY; - gap_conn_params.conn_sup_timeout = CONN_SUP_TIMEOUT; - - err_code = sd_ble_gap_ppcp_set(&gap_conn_params); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for handling advertising events. - * - * @details This function will be called for advertising events which are passed to the application. - * - * @param[in] ble_adv_evt Advertising event. - */ -static void -on_adv_evt(ble_adv_evt_t ble_adv_evt) -{ - switch (ble_adv_evt) - { - case BLE_ADV_EVT_FAST: - break; - case BLE_ADV_EVT_IDLE: - break; - default: - break; - } -} - -/**@brief Function for initializing the Advertising functionality. - */ -static void -advertising_init(void) -{ - uint32_t err_code; - ble_advdata_t advdata; - - // Build advertising data struct to pass into @ref ble_advertising_init. - memset(&advdata, 0, sizeof(advdata)); - - advdata.name_type = BLE_ADVDATA_FULL_NAME; - advdata.include_appearance = true; - advdata.flags = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE; - advdata.uuids_complete.uuid_cnt = sizeof(m_adv_uuids) / sizeof(m_adv_uuids[0]); - advdata.uuids_complete.p_uuids = m_adv_uuids; - - ble_adv_modes_config_t options = {0}; - options.ble_adv_fast_enabled = BLE_ADV_FAST_ENABLED; - options.ble_adv_fast_interval = APP_ADV_INTERVAL; - options.ble_adv_fast_timeout = APP_ADV_TIMEOUT_IN_SECONDS; - - err_code = ble_advertising_init(&advdata, NULL, &options, on_adv_evt, NULL); - APP_ERROR_CHECK(err_code); -} - -static void -nus_data_handler(ble_nus_t * p_nus, uint8_t * p_data, uint16_t length) -{ - for (uint32_t i = 0; i < length; i++) { - // XXX - app_fifo_put(&m_nus_rx_fifo, p_data[i]); - } -} - -static void -services_init(void) -{ - uint32_t err_code; - ble_nus_init_t nus_init = {0}; - nus_init.data_handler = nus_data_handler; - err_code = ble_nus_init(&m_nus, &nus_init); - APP_ERROR_CHECK(err_code); - - m_adv_uuids[0].type = m_nus.uuid_type; - - err_code = app_fifo_init(&m_nus_rx_fifo, m_nus_rx_fifo_buffer, NUS_RX_FIFO_BUFFER_SIZE); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for handling a Connection Parameters error. - * - * @param[in] nrf_error Error code containing information about what went wrong. - */ -static void conn_params_error_handler(uint32_t nrf_error) -{ - APP_ERROR_HANDLER(nrf_error); -} - -/**@brief Function for initializing the Connection Parameters module. - */ -static void -conn_params_init(void) -{ - uint32_t err_code; - ble_conn_params_init_t cp_init; - - memset(&cp_init, 0, sizeof(cp_init)); - - cp_init.p_conn_params = NULL; - cp_init.first_conn_params_update_delay = FIRST_CONN_PARAMS_UPDATE_DELAY; - cp_init.next_conn_params_update_delay = NEXT_CONN_PARAMS_UPDATE_DELAY; - cp_init.max_conn_params_update_count = MAX_CONN_PARAMS_UPDATE_COUNT; - cp_init.start_on_notify_cccd_handle = BLE_GATT_HANDLE_INVALID; - cp_init.disconnect_on_fail = true; - cp_init.evt_handler = NULL; - cp_init.error_handler = conn_params_error_handler; - - err_code = ble_conn_params_init(&cp_init); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for starting advertising. - */ -static void -advertising_start(void) -{ - uint32_t err_code = ble_advertising_start(BLE_ADV_MODE_FAST); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for handling Peer Manager events. - * - * @param[in] p_evt Peer Manager event. - */ -static void -pm_evt_handler(pm_evt_t const * p_evt) -{ - ret_code_t err_code; - - switch(p_evt->evt_id) - { - case PM_EVT_BONDED_PEER_CONNECTED: - err_code = pm_peer_rank_highest(p_evt->peer_id); - if (err_code != NRF_ERROR_BUSY) - { - APP_ERROR_CHECK(err_code); - } - break;//PM_EVT_BONDED_PEER_CONNECTED - - case PM_EVT_CONN_SEC_START: - break;//PM_EVT_CONN_SEC_START - - case PM_EVT_CONN_SEC_SUCCEEDED: - { - NRF_LOG_PRINTF_DEBUG("Link secured. Role: %d. conn_handle: %d, Procedure: %d\r\n", - ble_conn_state_role(p_evt->conn_handle), - p_evt->conn_handle, - p_evt->params.conn_sec_succeeded.procedure); - err_code = pm_peer_rank_highest(p_evt->peer_id); - if (err_code != NRF_ERROR_BUSY) - { - APP_ERROR_CHECK(err_code); - } - } - break;//PM_EVT_CONN_SEC_SUCCEEDED - - case PM_EVT_CONN_SEC_FAILED: - { - /** In some cases, when securing fails, it can be restarted directly. Sometimes it can - * be restarted, but only after changing some Security Parameters. Sometimes, it cannot - * be restarted until the link is disconnected and reconnected. Sometimes it is - * impossible, to secure the link, or the peer device does not support it. How to - * handle this error is highly application dependent. */ - switch (p_evt->params.conn_sec_failed.error) - { - case PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING: - // Rebond if one party has lost its keys. - err_code = pm_conn_secure(p_evt->conn_handle, true); - if (err_code != NRF_ERROR_INVALID_STATE) - { - APP_ERROR_CHECK(err_code); - } - break;//PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING - - default: - break; - } - } - break;//PM_EVT_CONN_SEC_FAILED - - case PM_EVT_CONN_SEC_CONFIG_REQ: - { - // Reject pairing request from an already bonded peer. - pm_conn_sec_config_t conn_sec_config = {.allow_repairing = false}; - pm_conn_sec_config_reply(p_evt->conn_handle, &conn_sec_config); - } - break;//PM_EVT_CONN_SEC_CONFIG_REQ - - case PM_EVT_STORAGE_FULL: - { - // Run garbage collection on the flash. - err_code = fds_gc(); - if (err_code == FDS_ERR_BUSY || err_code == FDS_ERR_NO_SPACE_IN_QUEUES) - { - // Retry. - } - else - { - APP_ERROR_CHECK(err_code); - } - } - break;//PM_EVT_STORAGE_FULL - - case PM_EVT_ERROR_UNEXPECTED: - // Assert. - APP_ERROR_CHECK(p_evt->params.error_unexpected.error); - break;//PM_EVT_ERROR_UNEXPECTED - - case PM_EVT_PEER_DATA_UPDATE_SUCCEEDED: - break;//PM_EVT_PEER_DATA_UPDATE_SUCCEEDED - - case PM_EVT_PEER_DATA_UPDATE_FAILED: - // Assert. - APP_ERROR_CHECK_BOOL(false); - break;//PM_EVT_PEER_DATA_UPDATE_FAILED - - case PM_EVT_PEER_DELETE_SUCCEEDED: - break;//PM_EVT_PEER_DELETE_SUCCEEDED - - case PM_EVT_PEER_DELETE_FAILED: - // Assert. - APP_ERROR_CHECK(p_evt->params.peer_delete_failed.error); - break;//PM_EVT_PEER_DELETE_FAILED - - case PM_EVT_PEERS_DELETE_SUCCEEDED: - advertising_start(); - break;//PM_EVT_PEERS_DELETE_SUCCEEDED - - case PM_EVT_PEERS_DELETE_FAILED: - // Assert. - APP_ERROR_CHECK(p_evt->params.peers_delete_failed_evt.error); - break;//PM_EVT_PEERS_DELETE_FAILED - - case PM_EVT_LOCAL_DB_CACHE_APPLIED: - break;//PM_EVT_LOCAL_DB_CACHE_APPLIED - - case PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED: - // The local database has likely changed, send service changed indications. - pm_local_database_has_changed(); - break;//PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED - - case PM_EVT_SERVICE_CHANGED_IND_SENT: - break;//PM_EVT_SERVICE_CHANGED_IND_SENT - - case PM_EVT_SERVICE_CHANGED_IND_CONFIRMED: - break;//PM_EVT_SERVICE_CHANGED_IND_CONFIRMED - - default: - // No implementation needed. - break; - } -} - -static void -peer_manager_init(bool erase_bonds) -{ - ble_gap_sec_params_t sec_param; - ret_code_t err_code; - - err_code = pm_init(); - APP_ERROR_CHECK(err_code); - - if (erase_bonds) - { - err_code = pm_peers_delete(); - APP_ERROR_CHECK(err_code); - } - - memset(&sec_param, 0, sizeof(ble_gap_sec_params_t)); - - // Security parameters to be used for all security procedures. - sec_param.bond = SEC_PARAM_BOND; - sec_param.mitm = SEC_PARAM_MITM; - sec_param.lesc = SEC_PARAM_LESC; - sec_param.keypress = SEC_PARAM_KEYPRESS; - sec_param.io_caps = SEC_PARAM_IO_CAPABILITIES; - sec_param.oob = SEC_PARAM_OOB; - sec_param.min_key_size = SEC_PARAM_MIN_KEY_SIZE; - sec_param.max_key_size = SEC_PARAM_MAX_KEY_SIZE; - sec_param.kdist_own.enc = 1; - sec_param.kdist_own.id = 1; - sec_param.kdist_peer.enc = 1; - sec_param.kdist_peer.id = 1; - - err_code = pm_sec_params_set(&sec_param); - APP_ERROR_CHECK(err_code); - - err_code = pm_register(pm_evt_handler); - APP_ERROR_CHECK(err_code); -} - -static void -timers_init() -{ - APP_TIMER_INIT(APP_TIMER_PRESCALER, APP_TIMER_OP_QUEUE_SIZE, false); -} - -void -nrf52_ble_init(void) -{ - timers_init(); - ble_stack_init(); - peer_manager_init(false); - gap_params_init(); - services_init(); - advertising_init(); - conn_params_init(); - - advertising_start(); -} - -static void -power_manage() -{ - uint32_t err_code = sd_app_evt_wait(); - APP_ERROR_CHECK(err_code); -} - -// ########################### MP IO functions ########################### - -void -mp_hal_stdout_tx_strn(const char *str, size_t len) -{ - uint32_t err_code; - uint8_t *buf = (uint8_t *)str; - size_t send_len; - - while (len > 0) { - if (len >= BLE_NUS_MAX_DATA_LEN) - send_len = BLE_NUS_MAX_DATA_LEN; - else - send_len = len; - err_code = ble_nus_string_send(&m_nus, buf, send_len); - if (err_code == NRF_SUCCESS) { - len -= send_len; - buf += send_len; - } else if (err_code != NRF_ERROR_INVALID_STATE) { - APP_ERROR_CHECK(err_code); - } - } -} - -int -mp_hal_stdin_rx_chr() -{ - uint8_t byte; - for (;;) { - if (app_fifo_get(&m_nus_rx_fifo, &byte) == NRF_SUCCESS) { - return byte; - } - power_manage(); - } -} diff --git a/nrf52/nrf52_ble.h b/nrf52/nrf52_ble.h deleted file mode 100644 index 26f9d86400..0000000000 --- a/nrf52/nrf52_ble.h +++ /dev/null @@ -1,4 +0,0 @@ -#pragma once - - -void nrf52_ble_init(void); diff --git a/nrf52/pstorage_platform.h b/nrf52/pstorage_platform.h deleted file mode 100644 index 4de11876b8..0000000000 --- a/nrf52/pstorage_platform.h +++ /dev/null @@ -1,72 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - - /** @cond To make doxygen skip this file */ - -/** @file - * This header contains defines with respect persistent storage that are specific to - * persistent storage implementation and application use case. - */ -#ifndef PSTORAGE_PL_H__ -#define PSTORAGE_PL_H__ - -#include -#include "nrf.h" - -static __INLINE uint16_t pstorage_flash_page_size() -{ - return (uint16_t)NRF_FICR->CODEPAGESIZE; -} - -#define PSTORAGE_FLASH_PAGE_SIZE pstorage_flash_page_size() /**< Size of one flash page. */ -#define PSTORAGE_FLASH_EMPTY_MASK 0xFFFFFFFF /**< Bit mask that defines an empty address in flash. */ - -static __INLINE uint32_t pstorage_flash_page_end() -{ - uint32_t bootloader_addr = NRF_UICR->NRFFW[0]; - - return ((bootloader_addr != PSTORAGE_FLASH_EMPTY_MASK) ? - (bootloader_addr/ PSTORAGE_FLASH_PAGE_SIZE) : NRF_FICR->CODESIZE); -} - -#define PSTORAGE_FLASH_PAGE_END pstorage_flash_page_end() - -#define PSTORAGE_NUM_OF_PAGES 1 /**< Number of flash pages allocated for the pstorage module excluding the swap page, configurable based on system requirements. */ -#define PSTORAGE_MIN_BLOCK_SIZE 0x0010 /**< Minimum size of block that can be registered with the module. Should be configured based on system requirements, recommendation is not have this value to be at least size of word. */ - -#define PSTORAGE_DATA_START_ADDR ((PSTORAGE_FLASH_PAGE_END - PSTORAGE_NUM_OF_PAGES - 1) \ - * PSTORAGE_FLASH_PAGE_SIZE) /**< Start address for persistent data, configurable according to system requirements. */ -#define PSTORAGE_DATA_END_ADDR ((PSTORAGE_FLASH_PAGE_END - 1) * PSTORAGE_FLASH_PAGE_SIZE) /**< End address for persistent data, configurable according to system requirements. */ -#define PSTORAGE_SWAP_ADDR PSTORAGE_DATA_END_ADDR /**< Top-most page is used as swap area for clear and update. */ - -#define PSTORAGE_MAX_BLOCK_SIZE PSTORAGE_FLASH_PAGE_SIZE /**< Maximum size of block that can be registered with the module. Should be configured based on system requirements. And should be greater than or equal to the minimum size. */ -#define PSTORAGE_CMD_QUEUE_SIZE 10 /**< Maximum number of flash access commands that can be maintained by the module for all applications. Configurable. */ - - -/** Abstracts persistently memory block identifier. */ -typedef uint32_t pstorage_block_t; - -typedef struct -{ - uint32_t module_id; /**< Module ID.*/ - pstorage_block_t block_id; /**< Block ID.*/ -} pstorage_handle_t; - -typedef uint16_t pstorage_size_t; /** Size of length and offset fields. */ - -/**@brief Handles Flash Access Result Events. To be called in the system event dispatcher of the application. */ -void pstorage_sys_event_handler (uint32_t sys_evt); - -#endif // PSTORAGE_PL_H__ - -/** @} */ -/** @endcond */ diff --git a/nrf52/qstrdefsport.h b/nrf52/qstrdefsport.h deleted file mode 100644 index e69de29bb2..0000000000 From 44c9888511351d45a0d73f1f5236eff93418341d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 1 Mar 2017 00:05:04 +0100 Subject: [PATCH 435/809] nrf5/sdk: Removing SDK dependant BLE UART Service implementation The sdk_12.1.0 nrf52_ble.c implementation was dependent on SDK components. This has been replaced with the ble_uart.c implementation using a standalone bluetooth driver implementation without need of SDK components. Also, sdk.mk has been updated to not use a special linker script. --- nrf5/sdk/sdk_12.1.0/build.mk | 105 -- nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld | 40 - nrf5/sdk/sdk_12.1.0/nrf52_app_error.c | 19 - nrf5/sdk/sdk_12.1.0/nrf52_ble.c | 493 ----- nrf5/sdk/sdk_12.1.0/nrf52_ble.h | 4 - nrf5/sdk/sdk_12.1.0/nrf52_board.h | 9 - nrf5/sdk/sdk_12.1.0/sdk.mk | 2 - nrf5/sdk/sdk_12.1.0/sdk_config.h | 2299 ----------------------- 8 files changed, 2971 deletions(-) delete mode 100644 nrf5/sdk/sdk_12.1.0/build.mk delete mode 100644 nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld delete mode 100644 nrf5/sdk/sdk_12.1.0/nrf52_app_error.c delete mode 100644 nrf5/sdk/sdk_12.1.0/nrf52_ble.c delete mode 100644 nrf5/sdk/sdk_12.1.0/nrf52_ble.h delete mode 100644 nrf5/sdk/sdk_12.1.0/nrf52_board.h delete mode 100644 nrf5/sdk/sdk_12.1.0/sdk_config.h diff --git a/nrf5/sdk/sdk_12.1.0/build.mk b/nrf5/sdk/sdk_12.1.0/build.mk deleted file mode 100644 index 6529861e2b..0000000000 --- a/nrf5/sdk/sdk_12.1.0/build.mk +++ /dev/null @@ -1,105 +0,0 @@ -# this file's folder -SDK_DIR := $(SDK_ROOT) - -# -D in CFLAGS -DEFINES += __HEAP_SIZE=0 -DEFINES += BLE_STACK_SUPPORT_REQD -DEFINES += CONFIG_GPIO_AS_PINRESET -DEFINES += NRF52 -DEFINES += NRF52_PAN_12 -DEFINES += NRF52_PAN_15 -DEFINES += NRF52_PAN_20 -DEFINES += NRF52_PAN_30 -DEFINES += NRF52_PAN_31 -DEFINES += NRF52_PAN_36 -DEFINES += NRF52_PAN_51 -DEFINES += NRF52_PAN_53 -DEFINES += NRF52_PAN_54 -DEFINES += NRF52_PAN_55 -DEFINES += NRF52_PAN_58 -DEFINES += NRF52_PAN_62 -DEFINES += NRF52_PAN_63 -DEFINES += NRF52_PAN_64 -DEFINES += S132 -DEFINES += SOFTDEVICE_PRESENT -DEFINES += SWI_DISABLE0 -DEFINES += NRF_SD_BLE_API_VERSION=3 -DEFINES += PEER_MANAGER_ENABLED=1 -DEFINES += FDS_ENABLED=1 - -ifeq ($(SDK_COMPOENTS), 1) -# nordic SDK C sources (relative path) -SDK_SRC_C += \ - components/ble/ble_advertising/ble_advertising.c \ - components/ble/ble_services/ble_nus/ble_nus.c \ - components/ble/common/ble_advdata.c \ - components/ble/common/ble_conn_params.c \ - components/ble/common/ble_conn_state.c \ - components/ble/common/ble_srv_common.c \ - components/ble/peer_manager/gatt_cache_manager.c \ - components/ble/peer_manager/gatts_cache_manager.c \ - components/ble/peer_manager/id_manager.c \ - components/ble/peer_manager/peer_data.c \ - components/ble/peer_manager/peer_data_storage.c \ - components/ble/peer_manager/peer_database.c \ - components/ble/peer_manager/peer_id.c \ - components/ble/peer_manager/peer_manager.c \ - components/ble/peer_manager/pm_buffer.c \ - components/ble/peer_manager/pm_mutex.c \ - components/ble/peer_manager/security_dispatcher.c \ - components/ble/peer_manager/security_manager.c \ - components/libraries/fds/fds.c \ - components/libraries/fifo/app_fifo.c \ - components/libraries/fstorage/fstorage.c \ - components/libraries/timer/app_timer.c \ - components/libraries/util/app_util_platform.c \ - components/libraries/util/sdk_mapped_flags.c \ - components/softdevice/common/softdevice_handler/softdevice_handler.c \ - components/drivers_nrf/clock/nrf_drv_clock.c \ - components/libraries/util/app_error.c \ - components/libraries/util/app_error_weak.c \ - components/drivers_nrf/common/nrf_drv_common.c -endif - -# include source folders (sort removes duplicates) -SDK_INC_DIRS += $(sort $(dir $(SDK_SRC_C))) -#SDK_INC_DIRS += $(sort $(${SDK_ROOT} ${SDK_SRC_C})) -# ble.h -SDK_INC_DIRS += components/softdevice/s132/headers -# nrf52.h compiler_abstraction.h -SDK_INC_DIRS += components/device -# core_cm4.h -SDK_INC_DIRS += components/toolchain/CMSIS/Include -# section_vars.h -SDK_INC_DIRS += components/libraries/experimental_section_vars -# fstorage_config.h -SDK_INC_DIRS += components/libraries/fstorage/config -# nrf_drv_config.h -SDK_INC_DIRS += components/drivers_nrf/config -# app_util.h -SDK_INC_DIRS += components/libraries/util -# fds_config.h -SDK_INC_DIRS += components/libraries/fds/config -# nrf_log.h -SDK_INC_DIRS += components/libraries/log/ -# nrf_log_internal.h -SDK_INC_DIRS += components/libraries/log/src -# nrf_clock.h -SDK_INC_DIRS += components/drivers_nrf/hal -# nrf_drv_common.h -SDK_INC_DIRS += components/drivers_nrf/common -# nrf_delay.h -SDK_INC_DIRS += components/drivers_nrf/delay - -CFLAGS += $(patsubst %,-D%,${DEFINES}) - -# include full path -INC += $(patsubst %,-I${SDK_DIR}/%, ${SDK_INC_DIRS}) - -# additional SDK source files -SRC_C += $(addprefix ${SDK_ROOT}/, $(SDK_SRC_C)) - -# Wrappers -SRC_C += \ - $(SDK_MODULES_PATH)nrf52_ble.c \ - diff --git a/nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld b/nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld deleted file mode 100644 index 094a8c45ca..0000000000 --- a/nrf5/sdk/sdk_12.1.0/nrf52832_aa_s132.ld +++ /dev/null @@ -1,40 +0,0 @@ -/* - GNU linker script for NRF52 w/ s132 3.0.0 SoftDevice -*/ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */ - FLASH_ISR (rx) : ORIGIN = 0x0001f000, LENGTH = 0x001000 /* sector 0, 4 KiB */ - FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 /* 396 KiB */ - RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 57.89 KiB, give 8KiB headroom for softdevice */ -} - -/* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 8K; -_minimum_heap_size = 8K; - -/* top end of the stack */ - -/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ -_estack = ORIGIN(RAM) + LENGTH(RAM); - -/* RAM extents for the garbage collector */ -_ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x200069c0; /* tunable */ - -__data_start__ = ORIGIN(RAM); - -SECTIONS -{ - .fs_data : - { - PROVIDE(__start_fs_data = .); - KEEP(*(.fs_data)) - PROVIDE(__stop_fs_data = .); - } > RAM -} INSERT AFTER .data; - - -INCLUDE "boards/common.ld" diff --git a/nrf5/sdk/sdk_12.1.0/nrf52_app_error.c b/nrf5/sdk/sdk_12.1.0/nrf52_app_error.c deleted file mode 100644 index 5775a3e3a3..0000000000 --- a/nrf5/sdk/sdk_12.1.0/nrf52_app_error.c +++ /dev/null @@ -1,19 +0,0 @@ -#include -#include "app_error.h" - - -void -#ifdef DEBUG -app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) -#else -app_error_handler_bare(ret_code_t error_code) -#endif -{ -#ifdef DEBUG - for (;;) { - /* FOREVER */ - } -#else - NVIC_SystemReset(); -#endif -} diff --git a/nrf5/sdk/sdk_12.1.0/nrf52_ble.c b/nrf5/sdk/sdk_12.1.0/nrf52_ble.c deleted file mode 100644 index 7a47f704ee..0000000000 --- a/nrf5/sdk/sdk_12.1.0/nrf52_ble.c +++ /dev/null @@ -1,493 +0,0 @@ -#include "py/mpconfig.h" - -#if MICROPY_PY_BLE_NUS - -#include "nrf52_ble.h" -#include "nrf52_board.h" - -#include "sdk_config.h" -#include "app_error.h" -#include "app_fifo.h" -#include "app_timer.h" -#include "ble_advertising.h" -#include "ble_conn_params.h" -#include "ble_conn_state.h" -#include "ble_hci.h" -#include "ble_nus.h" -#include "ble_srv_common.h" -#include "fds.h" -#include "fstorage.h" -#include "peer_manager.h" -#include "softdevice_handler.h" - -#define CENTRAL_LINK_COUNT 0 /**< Number of central links used by the application. When changing this number remember to adjust the RAM settings*/ -#define PERIPHERAL_LINK_COUNT 1 /**< Number of peripheral links used by the application. When changing this number remember to adjust the RAM settings*/ - -#define DEVICE_NAME "micropython" - -#define MIN_CONN_INTERVAL MSEC_TO_UNITS(20, UNIT_1_25_MS) /**< Minimum acceptable connection interval (0.02 seconds). */ -#define MAX_CONN_INTERVAL MSEC_TO_UNITS(200, UNIT_1_25_MS) /**< Maximum acceptable connection interval (0.2 second). */ -#define SLAVE_LATENCY 0 /**< Slave latency. */ -#define CONN_SUP_TIMEOUT MSEC_TO_UNITS(3000, UNIT_10_MS) /**< Connection supervisory timeout (3 seconds). */ - -#define APP_ADV_INTERVAL MSEC_TO_UNITS(25, UNIT_0_625_MS) -#define APP_ADV_TIMEOUT_IN_SECONDS 180 - -#define APP_TIMER_PRESCALER 0 /**< Value of the RTC1 PRESCALER register. */ -#define APP_TIMER_OP_QUEUE_SIZE 4 /**< Size of timer operation queues. */ - -#define FIRST_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(5000, APP_TIMER_PRESCALER) /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (5 seconds). */ -#define NEXT_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(30000, APP_TIMER_PRESCALER) /**< Time between each call to sd_ble_gap_conn_param_update after the first call (30 seconds). */ -#define MAX_CONN_PARAMS_UPDATE_COUNT 3 - -#define SEC_PARAM_BOND 1 /**< Perform bonding. */ -#define SEC_PARAM_MITM 0 /**< Man In The Middle protection not required. */ -#define SEC_PARAM_LESC 0 /**< LE Secure Connections not enabled. */ -#define SEC_PARAM_KEYPRESS 0 /**< Keypress notifications not enabled. */ -#define SEC_PARAM_IO_CAPABILITIES BLE_GAP_IO_CAPS_NONE /**< No I/O capabilities. */ -#define SEC_PARAM_OOB 0 /**< Out Of Band data not available. */ -#define SEC_PARAM_MIN_KEY_SIZE 7 /**< Minimum encryption key size. */ -#define SEC_PARAM_MAX_KEY_SIZE 16 /**< Maximum encryption key size. */ - -#define NUS_RX_FIFO_BUFFER_SIZE 64 - -static ble_uuid_t m_adv_uuids[] = {{BLE_UUID_NUS_SERVICE, 0}}; /**< Universally unique service identifiers. */ - -static ble_nus_t m_nus; -static app_fifo_t m_nus_rx_fifo; -static uint8_t m_nus_rx_fifo_buffer[NUS_RX_FIFO_BUFFER_SIZE]; - - -static void -ble_evt_dispatch(ble_evt_t * p_ble_evt) -{ - ble_conn_state_on_ble_evt(p_ble_evt); - pm_on_ble_evt(p_ble_evt); - ble_conn_params_on_ble_evt(p_ble_evt); - ble_advertising_on_ble_evt(p_ble_evt); - ble_nus_on_ble_evt(&m_nus, p_ble_evt); -} - -static void -sys_evt_dispatch(uint32_t sys_evt) -{ - fs_sys_event_handler(sys_evt); - ble_advertising_on_sys_evt(sys_evt); -} - -static void -ble_stack_init(void) -{ - nrf_clock_lf_cfg_t clock_lf_cfg = NRF_CLOCK_LFCLKSRC; - - // Initialize the SoftDevice handler module. - SOFTDEVICE_HANDLER_INIT(&clock_lf_cfg, NULL); - - ble_enable_params_t ble_enable_params; - uint32_t err_code = softdevice_enable_get_default_config(CENTRAL_LINK_COUNT, - PERIPHERAL_LINK_COUNT, - &ble_enable_params); - APP_ERROR_CHECK(err_code); - - //Check the ram settings against the used number of links - CHECK_RAM_START_ADDR(CENTRAL_LINK_COUNT, PERIPHERAL_LINK_COUNT); - - // Enable BLE stack. - err_code = softdevice_enable(&ble_enable_params); - APP_ERROR_CHECK(err_code); - - // Register with the SoftDevice handler module for BLE events. - err_code = softdevice_ble_evt_handler_set(ble_evt_dispatch); - APP_ERROR_CHECK(err_code); - - // Register with the SoftDevice handler module for BLE events. - err_code = softdevice_sys_evt_handler_set(sys_evt_dispatch); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for the GAP initialization. - * - * @details This function sets up all the necessary GAP (Generic Access Profile) parameters of the - * device including the device name, appearance, and the preferred connection parameters. - */ -static void -gap_params_init(void) -{ - uint32_t err_code; - ble_gap_conn_params_t gap_conn_params; - ble_gap_conn_sec_mode_t sec_mode; - - BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); - - err_code = sd_ble_gap_device_name_set(&sec_mode, - (const uint8_t *)DEVICE_NAME, - strlen(DEVICE_NAME)); - APP_ERROR_CHECK(err_code); - - err_code = sd_ble_gap_appearance_set(BLE_APPEARANCE_UNKNOWN); - APP_ERROR_CHECK(err_code); - - memset(&gap_conn_params, 0, sizeof(gap_conn_params)); - - gap_conn_params.min_conn_interval = MIN_CONN_INTERVAL; - gap_conn_params.max_conn_interval = MAX_CONN_INTERVAL; - gap_conn_params.slave_latency = SLAVE_LATENCY; - gap_conn_params.conn_sup_timeout = CONN_SUP_TIMEOUT; - - err_code = sd_ble_gap_ppcp_set(&gap_conn_params); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for handling advertising events. - * - * @details This function will be called for advertising events which are passed to the application. - * - * @param[in] ble_adv_evt Advertising event. - */ -static void -on_adv_evt(ble_adv_evt_t ble_adv_evt) -{ - switch (ble_adv_evt) - { - case BLE_ADV_EVT_FAST: - break; - case BLE_ADV_EVT_IDLE: - break; - default: - break; - } -} - -/**@brief Function for initializing the Advertising functionality. - */ -static void -advertising_init(void) -{ - uint32_t err_code; - ble_advdata_t advdata; - - // Build advertising data struct to pass into @ref ble_advertising_init. - memset(&advdata, 0, sizeof(advdata)); - - advdata.name_type = BLE_ADVDATA_FULL_NAME; - advdata.include_appearance = true; - advdata.flags = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE; - advdata.uuids_complete.uuid_cnt = sizeof(m_adv_uuids) / sizeof(m_adv_uuids[0]); - advdata.uuids_complete.p_uuids = m_adv_uuids; - - ble_adv_modes_config_t options = {0}; - options.ble_adv_fast_enabled = true; - options.ble_adv_fast_interval = APP_ADV_INTERVAL; - options.ble_adv_fast_timeout = APP_ADV_TIMEOUT_IN_SECONDS; - - err_code = ble_advertising_init(&advdata, NULL, &options, on_adv_evt, NULL); - APP_ERROR_CHECK(err_code); -} - -static void -nus_data_handler(ble_nus_t * p_nus, uint8_t * p_data, uint16_t length) -{ - for (uint32_t i = 0; i < length; i++) { - // XXX - app_fifo_put(&m_nus_rx_fifo, p_data[i]); - } -} - -static void -services_init(void) -{ - uint32_t err_code; - ble_nus_init_t nus_init = {0}; - nus_init.data_handler = nus_data_handler; - err_code = ble_nus_init(&m_nus, &nus_init); - APP_ERROR_CHECK(err_code); - - m_adv_uuids[0].type = m_nus.uuid_type; - - err_code = app_fifo_init(&m_nus_rx_fifo, m_nus_rx_fifo_buffer, NUS_RX_FIFO_BUFFER_SIZE); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for handling a Connection Parameters error. - * - * @param[in] nrf_error Error code containing information about what went wrong. - */ -static void conn_params_error_handler(uint32_t nrf_error) -{ - APP_ERROR_HANDLER(nrf_error); -} - -/**@brief Function for initializing the Connection Parameters module. - */ -static void -conn_params_init(void) -{ - uint32_t err_code; - ble_conn_params_init_t cp_init; - - memset(&cp_init, 0, sizeof(cp_init)); - - cp_init.p_conn_params = NULL; - cp_init.first_conn_params_update_delay = FIRST_CONN_PARAMS_UPDATE_DELAY; - cp_init.next_conn_params_update_delay = NEXT_CONN_PARAMS_UPDATE_DELAY; - cp_init.max_conn_params_update_count = MAX_CONN_PARAMS_UPDATE_COUNT; - cp_init.start_on_notify_cccd_handle = BLE_GATT_HANDLE_INVALID; - cp_init.disconnect_on_fail = true; - cp_init.evt_handler = NULL; - cp_init.error_handler = conn_params_error_handler; - - err_code = ble_conn_params_init(&cp_init); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for starting advertising. - */ -static void -advertising_start(void) -{ - uint32_t err_code = ble_advertising_start(BLE_ADV_MODE_FAST); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for handling Peer Manager events. - * - * @param[in] p_evt Peer Manager event. - */ -static void -pm_evt_handler(pm_evt_t const * p_evt) -{ - ret_code_t err_code; - - switch(p_evt->evt_id) - { - case PM_EVT_BONDED_PEER_CONNECTED: - err_code = pm_peer_rank_highest(p_evt->peer_id); - if (err_code != NRF_ERROR_BUSY) - { - APP_ERROR_CHECK(err_code); - } - break;//PM_EVT_BONDED_PEER_CONNECTED - - case PM_EVT_CONN_SEC_START: - break;//PM_EVT_CONN_SEC_START - - case PM_EVT_CONN_SEC_SUCCEEDED: - { - /* - NRF_LOG_PRINTF_DEBUG("Link secured. Role: %d. conn_handle: %d, Procedure: %d\r\n", - ble_conn_state_role(p_evt->conn_handle), - p_evt->conn_handle, - p_evt->params.conn_sec_succeeded.procedure); - */ - err_code = pm_peer_rank_highest(p_evt->peer_id); - if (err_code != NRF_ERROR_BUSY) - { - APP_ERROR_CHECK(err_code); - } - } - break;//PM_EVT_CONN_SEC_SUCCEEDED - - case PM_EVT_CONN_SEC_FAILED: - { - /** In some cases, when securing fails, it can be restarted directly. Sometimes it can - * be restarted, but only after changing some Security Parameters. Sometimes, it cannot - * be restarted until the link is disconnected and reconnected. Sometimes it is - * impossible, to secure the link, or the peer device does not support it. How to - * handle this error is highly application dependent. */ - switch (p_evt->params.conn_sec_failed.error) - { - case PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING: - // Rebond if one party has lost its keys. - err_code = pm_conn_secure(p_evt->conn_handle, true); - if (err_code != NRF_ERROR_INVALID_STATE) - { - APP_ERROR_CHECK(err_code); - } - break;//PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING - - default: - break; - } - } - break;//PM_EVT_CONN_SEC_FAILED - - case PM_EVT_CONN_SEC_CONFIG_REQ: - { - // Reject pairing request from an already bonded peer. - pm_conn_sec_config_t conn_sec_config = {.allow_repairing = false}; - pm_conn_sec_config_reply(p_evt->conn_handle, &conn_sec_config); - } - break;//PM_EVT_CONN_SEC_CONFIG_REQ - - case PM_EVT_STORAGE_FULL: - { - // Run garbage collection on the flash. - err_code = fds_gc(); - if (err_code == FDS_ERR_BUSY || err_code == FDS_ERR_NO_SPACE_IN_QUEUES) - { - // Retry. - } - else - { - APP_ERROR_CHECK(err_code); - } - } - break;//PM_EVT_STORAGE_FULL - - case PM_EVT_ERROR_UNEXPECTED: - // Assert. - APP_ERROR_CHECK(p_evt->params.error_unexpected.error); - break;//PM_EVT_ERROR_UNEXPECTED - - case PM_EVT_PEER_DATA_UPDATE_SUCCEEDED: - break;//PM_EVT_PEER_DATA_UPDATE_SUCCEEDED - - case PM_EVT_PEER_DATA_UPDATE_FAILED: - // Assert. - APP_ERROR_CHECK_BOOL(false); - break;//PM_EVT_PEER_DATA_UPDATE_FAILED - - case PM_EVT_PEER_DELETE_SUCCEEDED: - break;//PM_EVT_PEER_DELETE_SUCCEEDED - - case PM_EVT_PEER_DELETE_FAILED: - // Assert. - APP_ERROR_CHECK(p_evt->params.peer_delete_failed.error); - break;//PM_EVT_PEER_DELETE_FAILED - - case PM_EVT_PEERS_DELETE_SUCCEEDED: - advertising_start(); - break;//PM_EVT_PEERS_DELETE_SUCCEEDED - - case PM_EVT_PEERS_DELETE_FAILED: - // Assert. - APP_ERROR_CHECK(p_evt->params.peers_delete_failed_evt.error); - break;//PM_EVT_PEERS_DELETE_FAILED - - case PM_EVT_LOCAL_DB_CACHE_APPLIED: - break;//PM_EVT_LOCAL_DB_CACHE_APPLIED - - case PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED: - // The local database has likely changed, send service changed indications. - pm_local_database_has_changed(); - break;//PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED - - case PM_EVT_SERVICE_CHANGED_IND_SENT: - break;//PM_EVT_SERVICE_CHANGED_IND_SENT - - case PM_EVT_SERVICE_CHANGED_IND_CONFIRMED: - break;//PM_EVT_SERVICE_CHANGED_IND_CONFIRMED - - default: - // No implementation needed. - break; - } -} - -static void -peer_manager_init(bool erase_bonds) -{ - ble_gap_sec_params_t sec_param; - ret_code_t err_code; - - err_code = pm_init(); - APP_ERROR_CHECK(err_code); - - if (erase_bonds) - { - err_code = pm_peers_delete(); - APP_ERROR_CHECK(err_code); - } - - memset(&sec_param, 0, sizeof(ble_gap_sec_params_t)); - - // Security parameters to be used for all security procedures. - sec_param.bond = SEC_PARAM_BOND; - sec_param.mitm = SEC_PARAM_MITM; - sec_param.lesc = SEC_PARAM_LESC; - sec_param.keypress = SEC_PARAM_KEYPRESS; - sec_param.io_caps = SEC_PARAM_IO_CAPABILITIES; - sec_param.oob = SEC_PARAM_OOB; - sec_param.min_key_size = SEC_PARAM_MIN_KEY_SIZE; - sec_param.max_key_size = SEC_PARAM_MAX_KEY_SIZE; - sec_param.kdist_own.enc = 1; - sec_param.kdist_own.id = 1; - sec_param.kdist_peer.enc = 1; - sec_param.kdist_peer.id = 1; - - err_code = pm_sec_params_set(&sec_param); - APP_ERROR_CHECK(err_code); - - err_code = pm_register(pm_evt_handler); - APP_ERROR_CHECK(err_code); -} - -static void -timers_init() -{ - APP_TIMER_INIT(APP_TIMER_PRESCALER, APP_TIMER_OP_QUEUE_SIZE, false); -} - -void -nrf52_ble_init(void) -{ - fds_init(); - fs_init(); - timers_init(); - ble_stack_init(); - ble_conn_state_init(); - peer_manager_init(false); - gap_params_init(); - services_init(); - advertising_init(); - conn_params_init(); - - (void)ble_advertising_start(BLE_ADV_MODE_FAST); - - -} - -static void -power_manage() -{ - uint32_t err_code = sd_app_evt_wait(); - APP_ERROR_CHECK(err_code); -} - -// ########################### MP IO functions ########################### - -void -mp_hal_stdout_tx_strn(const char *str, size_t len) -{ - uint32_t err_code; - uint8_t *buf = (uint8_t *)str; - size_t send_len; - - while (len > 0) { - if (len >= BLE_NUS_MAX_DATA_LEN) - send_len = BLE_NUS_MAX_DATA_LEN; - else - send_len = len; - err_code = ble_nus_string_send(&m_nus, buf, send_len); - if (err_code == NRF_SUCCESS) { - len -= send_len; - buf += send_len; - } else if (err_code != NRF_ERROR_INVALID_STATE) { - APP_ERROR_CHECK(err_code); - } - } -} - -int -mp_hal_stdin_rx_chr() -{ - uint8_t byte; - for (;;) { - if (app_fifo_get(&m_nus_rx_fifo, &byte) == NRF_SUCCESS) { - return byte; - } - power_manage(); - } -} - -#endif // MICROPY_PY_BLE_NUS diff --git a/nrf5/sdk/sdk_12.1.0/nrf52_ble.h b/nrf5/sdk/sdk_12.1.0/nrf52_ble.h deleted file mode 100644 index 26f9d86400..0000000000 --- a/nrf5/sdk/sdk_12.1.0/nrf52_ble.h +++ /dev/null @@ -1,4 +0,0 @@ -#pragma once - - -void nrf52_ble_init(void); diff --git a/nrf5/sdk/sdk_12.1.0/nrf52_board.h b/nrf5/sdk/sdk_12.1.0/nrf52_board.h deleted file mode 100644 index 8d20b72844..0000000000 --- a/nrf5/sdk/sdk_12.1.0/nrf52_board.h +++ /dev/null @@ -1,9 +0,0 @@ -#pragma once - -#include "nrf_sdm.h" - -// Low frequency clock source to be used by the SoftDevice -#define NRF_CLOCK_LFCLKSRC {.source = NRF_CLOCK_LF_SRC_XTAL, \ - .rc_ctiv = 0, \ - .rc_temp_ctiv = 0, \ - .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM} diff --git a/nrf5/sdk/sdk_12.1.0/sdk.mk b/nrf5/sdk/sdk_12.1.0/sdk.mk index 69c314a0fb..b8ba631642 100644 --- a/nrf5/sdk/sdk_12.1.0/sdk.mk +++ b/nrf5/sdk/sdk_12.1.0/sdk.mk @@ -12,6 +12,4 @@ SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s130/hex/ else ifeq ($(SD), s132) CFLAGS += -DBLUETOOTH_SD=132 SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s132/hex/s132_nrf52_3.0.0_softdevice.hex)) -# Update to local linker file, special linking has to be done -LD_FILE := $(SDK_MODULES_PATH)nrf52832_aa_s132.ld endif diff --git a/nrf5/sdk/sdk_12.1.0/sdk_config.h b/nrf5/sdk/sdk_12.1.0/sdk_config.h deleted file mode 100644 index fa78d17e3e..0000000000 --- a/nrf5/sdk/sdk_12.1.0/sdk_config.h +++ /dev/null @@ -1,2299 +0,0 @@ - - -#ifndef SDK_CONFIG_H -#define SDK_CONFIG_H -// <<< Use Configuration Wizard in Context Menu >>>\n -#ifdef USE_APP_CONFIG -#include "app_config.h" -#endif -// nRF_BLE - -//========================================================== -// BLE_ADVERTISING_ENABLED - ble_advertising - Advertising module - - -#ifndef BLE_ADVERTISING_ENABLED -#define BLE_ADVERTISING_ENABLED 1 -#endif - -// BLE_DTM_ENABLED - ble_dtm - Module for testing RF/PHY using DTM commands - - -#ifndef BLE_DTM_ENABLED -#define BLE_DTM_ENABLED 0 -#endif - -// BLE_RACP_ENABLED - ble_racp - Record Access Control Point library - - -#ifndef BLE_RACP_ENABLED -#define BLE_RACP_ENABLED 0 -#endif - -// NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write) - - -#ifndef NRF_BLE_QWR_ENABLED -#define NRF_BLE_QWR_ENABLED 0 -#endif - -// PEER_MANAGER_ENABLED - peer_manager - Peer Manager - - -#ifndef PEER_MANAGER_ENABLED -#define PEER_MANAGER_ENABLED 1 -#endif - -// -//========================================================== - -// nRF_BLE_Services - -//========================================================== -// BLE_ANCS_C_ENABLED - ble_ancs_c - Apple Notification Service Client - - -#ifndef BLE_ANCS_C_ENABLED -#define BLE_ANCS_C_ENABLED 0 -#endif - -// BLE_ANS_C_ENABLED - ble_ans_c - Alert Notification Service Client - - -#ifndef BLE_ANS_C_ENABLED -#define BLE_ANS_C_ENABLED 0 -#endif - -// BLE_BAS_C_ENABLED - ble_bas_c - Battery Service Client - - -#ifndef BLE_BAS_C_ENABLED -#define BLE_BAS_C_ENABLED 0 -#endif - -// BLE_BAS_ENABLED - ble_bas - Battery Service - - -#ifndef BLE_BAS_ENABLED -#define BLE_BAS_ENABLED 0 -#endif - -// BLE_CSCS_ENABLED - ble_cscs - Cycling Speed and Cadence Service - - -#ifndef BLE_CSCS_ENABLED -#define BLE_CSCS_ENABLED 0 -#endif - -// BLE_CTS_C_ENABLED - ble_cts_c - Current Time Service Client - - -#ifndef BLE_CTS_C_ENABLED -#define BLE_CTS_C_ENABLED 0 -#endif - -// BLE_DIS_ENABLED - ble_dis - Device Information Service - - -#ifndef BLE_DIS_ENABLED -#define BLE_DIS_ENABLED 0 -#endif - -// BLE_GLS_ENABLED - ble_gls - Glucose Service - - -#ifndef BLE_GLS_ENABLED -#define BLE_GLS_ENABLED 0 -#endif - -// BLE_HIDS_ENABLED - ble_hids - Human Interface Device Service - - -#ifndef BLE_HIDS_ENABLED -#define BLE_HIDS_ENABLED 0 -#endif - -// BLE_HRS_C_ENABLED - ble_hrs_c - Heart Rate Service Client - - -#ifndef BLE_HRS_C_ENABLED -#define BLE_HRS_C_ENABLED 0 -#endif - -// BLE_HRS_ENABLED - ble_hrs - Heart Rate Service - - -#ifndef BLE_HRS_ENABLED -#define BLE_HRS_ENABLED 0 -#endif - -// BLE_HTS_ENABLED - ble_hts - Health Thermometer Service - - -#ifndef BLE_HTS_ENABLED -#define BLE_HTS_ENABLED 0 -#endif - -// BLE_IAS_C_ENABLED - ble_ias_c - Immediate Alert Service Client - - -#ifndef BLE_IAS_C_ENABLED -#define BLE_IAS_C_ENABLED 0 -#endif - -// BLE_IAS_ENABLED - ble_ias - Immediate Alert Service - - -#ifndef BLE_IAS_ENABLED -#define BLE_IAS_ENABLED 0 -#endif - -// BLE_LBS_C_ENABLED - ble_lbs_c - Nordic LED Button Service Client - - -#ifndef BLE_LBS_C_ENABLED -#define BLE_LBS_C_ENABLED 0 -#endif - -// BLE_LBS_ENABLED - ble_lbs - LED Button Service - - -#ifndef BLE_LBS_ENABLED -#define BLE_LBS_ENABLED 0 -#endif - -// BLE_LLS_ENABLED - ble_lls - Link Loss Service - - -#ifndef BLE_LLS_ENABLED -#define BLE_LLS_ENABLED 0 -#endif - -// BLE_NUS_C_ENABLED - ble_nus_c - Nordic UART Central Service - - -#ifndef BLE_NUS_C_ENABLED -#define BLE_NUS_C_ENABLED 0 -#endif - -// BLE_NUS_ENABLED - ble_nus - Nordic UART Service - - -#ifndef BLE_NUS_ENABLED -#define BLE_NUS_ENABLED 1 -#endif - -// BLE_RSCS_C_ENABLED - ble_rscs_c - Running Speed and Cadence Client - - -#ifndef BLE_RSCS_C_ENABLED -#define BLE_RSCS_C_ENABLED 0 -#endif - -// BLE_RSCS_ENABLED - ble_rscs - Running Speed and Cadence Service - - -#ifndef BLE_RSCS_ENABLED -#define BLE_RSCS_ENABLED 0 -#endif - -// BLE_TPS_ENABLED - ble_tps - TX Power Service - - -#ifndef BLE_TPS_ENABLED -#define BLE_TPS_ENABLED 0 -#endif - -// -//========================================================== - -// nRF_Drivers - -//========================================================== -// ADC_ENABLED - nrf_drv_adc - Driver for ADC peripheral (nRF51) -//========================================================== -#ifndef ADC_ENABLED -#define ADC_ENABLED 0 -#endif -#if ADC_ENABLED -// ADC_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef ADC_CONFIG_IRQ_PRIORITY -#define ADC_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //ADC_ENABLED -// - -// CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver -//========================================================== -#ifndef CLOCK_ENABLED -#define CLOCK_ENABLED 1 -#endif -#if CLOCK_ENABLED -// CLOCK_CONFIG_XTAL_FREQ - HF XTAL Frequency - -// <0=> Default (64 MHz) - -#ifndef CLOCK_CONFIG_XTAL_FREQ -#define CLOCK_CONFIG_XTAL_FREQ 0 -#endif - -// CLOCK_CONFIG_LF_SRC - LF Clock Source - -// <0=> RC -// <1=> XTAL -// <2=> Synth - -#ifndef CLOCK_CONFIG_LF_SRC -#define CLOCK_CONFIG_LF_SRC 1 -#endif - -// CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef CLOCK_CONFIG_IRQ_PRIORITY -#define CLOCK_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //CLOCK_ENABLED -// - -// COMP_ENABLED - nrf_drv_comp - COMP peripheral driver -//========================================================== -#ifndef COMP_ENABLED -#define COMP_ENABLED 0 -#endif -#if COMP_ENABLED -// COMP_CONFIG_REF - Reference voltage - -// <0=> Internal 1.2V -// <1=> Internal 1.8V -// <2=> Internal 2.4V -// <4=> VDD -// <7=> ARef - -#ifndef COMP_CONFIG_REF -#define COMP_CONFIG_REF 1 -#endif - -// COMP_CONFIG_MAIN_MODE - Main mode - -// <0=> Single ended -// <1=> Differential - -#ifndef COMP_CONFIG_MAIN_MODE -#define COMP_CONFIG_MAIN_MODE 0 -#endif - -// COMP_CONFIG_SPEED_MODE - Speed mode - -// <0=> Low power -// <1=> Normal -// <2=> High speed - -#ifndef COMP_CONFIG_SPEED_MODE -#define COMP_CONFIG_SPEED_MODE 2 -#endif - -// COMP_CONFIG_HYST - Hystheresis - -// <0=> No -// <1=> 50mV - -#ifndef COMP_CONFIG_HYST -#define COMP_CONFIG_HYST 0 -#endif - -// COMP_CONFIG_ISOURCE - Current Source - -// <0=> Off -// <1=> 2.5 uA -// <2=> 5 uA -// <3=> 10 uA - -#ifndef COMP_CONFIG_ISOURCE -#define COMP_CONFIG_ISOURCE 0 -#endif - -// COMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef COMP_CONFIG_INPUT -#define COMP_CONFIG_INPUT 0 -#endif - -// COMP_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef COMP_CONFIG_IRQ_PRIORITY -#define COMP_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //COMP_ENABLED -// - -// EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver - - -#ifndef EGU_ENABLED -#define EGU_ENABLED 0 -#endif - -// GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver -//========================================================== -#ifndef GPIOTE_ENABLED -#define GPIOTE_ENABLED 1 -#endif -#if GPIOTE_ENABLED -// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4 -#endif - -// GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef GPIOTE_CONFIG_IRQ_PRIORITY -#define GPIOTE_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //GPIOTE_ENABLED -// - -// I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver -//========================================================== -#ifndef I2S_ENABLED -#define I2S_ENABLED 0 -#endif -#if I2S_ENABLED -// I2S_CONFIG_SCK_PIN - SCK pin <0-31> - - -#ifndef I2S_CONFIG_SCK_PIN -#define I2S_CONFIG_SCK_PIN 31 -#endif - -// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> - - -#ifndef I2S_CONFIG_LRCK_PIN -#define I2S_CONFIG_LRCK_PIN 30 -#endif - -// I2S_CONFIG_MCK_PIN - MCK pin -#ifndef I2S_CONFIG_MCK_PIN -#define I2S_CONFIG_MCK_PIN 255 -#endif - -// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> - - -#ifndef I2S_CONFIG_SDOUT_PIN -#define I2S_CONFIG_SDOUT_PIN 29 -#endif - -// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> - - -#ifndef I2S_CONFIG_SDIN_PIN -#define I2S_CONFIG_SDIN_PIN 28 -#endif - -// I2S_CONFIG_MASTER - Mode - -// <0=> Master -// <1=> Slave - -#ifndef I2S_CONFIG_MASTER -#define I2S_CONFIG_MASTER 0 -#endif - -// I2S_CONFIG_FORMAT - Format - -// <0=> I2S -// <1=> Aligned - -#ifndef I2S_CONFIG_FORMAT -#define I2S_CONFIG_FORMAT 0 -#endif - -// I2S_CONFIG_ALIGN - Alignment - -// <0=> Left -// <1=> Right - -#ifndef I2S_CONFIG_ALIGN -#define I2S_CONFIG_ALIGN 0 -#endif - -// I2S_CONFIG_SWIDTH - Sample width (bits) - -// <0=> 8 -// <1=> 16 -// <2=> 24 - -#ifndef I2S_CONFIG_SWIDTH -#define I2S_CONFIG_SWIDTH 1 -#endif - -// I2S_CONFIG_CHANNELS - Channels - -// <0=> Stereo -// <1=> Left -// <2=> Right - -#ifndef I2S_CONFIG_CHANNELS -#define I2S_CONFIG_CHANNELS 1 -#endif - -// I2S_CONFIG_MCK_SETUP - MCK behavior - -// <0=> Disabled -// <2147483648=> 32MHz/2 -// <1342177280=> 32MHz/3 -// <1073741824=> 32MHz/4 -// <805306368=> 32MHz/5 -// <671088640=> 32MHz/6 -// <536870912=> 32MHz/8 -// <402653184=> 32MHz/10 -// <369098752=> 32MHz/11 -// <285212672=> 32MHz/15 -// <268435456=> 32MHz/16 -// <201326592=> 32MHz/21 -// <184549376=> 32MHz/23 -// <142606336=> 32MHz/30 -// <138412032=> 32MHz/31 -// <134217728=> 32MHz/32 -// <100663296=> 32MHz/42 -// <68157440=> 32MHz/63 -// <34340864=> 32MHz/125 - -#ifndef I2S_CONFIG_MCK_SETUP -#define I2S_CONFIG_MCK_SETUP 536870912 -#endif - -// I2S_CONFIG_RATIO - MCK/LRCK ratio - -// <0=> 32x -// <1=> 48x -// <2=> 64x -// <3=> 96x -// <4=> 128x -// <5=> 192x -// <6=> 256x -// <7=> 384x -// <8=> 512x - -#ifndef I2S_CONFIG_RATIO -#define I2S_CONFIG_RATIO 2000 -#endif - -// I2S_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef I2S_CONFIG_IRQ_PRIORITY -#define I2S_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //I2S_ENABLED -// - -// LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver -//========================================================== -#ifndef LPCOMP_ENABLED -#define LPCOMP_ENABLED 0 -#endif -#if LPCOMP_ENABLED -// LPCOMP_CONFIG_REFERENCE - Reference voltage - -// <0=> Supply 1/8 -// <1=> Supply 2/8 -// <2=> Supply 3/8 -// <3=> Supply 4/8 -// <4=> Supply 5/8 -// <5=> Supply 6/8 -// <6=> Supply 7/8 -// <8=> Supply 1/16 (nRF52) -// <9=> Supply 3/16 (nRF52) -// <10=> Supply 5/16 (nRF52) -// <11=> Supply 7/16 (nRF52) -// <12=> Supply 9/16 (nRF52) -// <13=> Supply 11/16 (nRF52) -// <14=> Supply 13/16 (nRF52) -// <15=> Supply 15/16 (nRF52) -// <7=> External Ref 0 -// <65543=> External Ref 1 - -#ifndef LPCOMP_CONFIG_REFERENCE -#define LPCOMP_CONFIG_REFERENCE 3 -#endif - -// LPCOMP_CONFIG_DETECTION - Detection - -// <0=> Crossing -// <1=> Up -// <2=> Down - -#ifndef LPCOMP_CONFIG_DETECTION -#define LPCOMP_CONFIG_DETECTION 2 -#endif - -// LPCOMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef LPCOMP_CONFIG_INPUT -#define LPCOMP_CONFIG_INPUT 0 -#endif - -// LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef LPCOMP_CONFIG_IRQ_PRIORITY -#define LPCOMP_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //LPCOMP_ENABLED -// - -// PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver -//========================================================== -#ifndef PDM_ENABLED -#define PDM_ENABLED 0 -#endif -#if PDM_ENABLED -// PDM_CONFIG_MODE - Mode - -// <0=> Stereo -// <1=> Mono - -#ifndef PDM_CONFIG_MODE -#define PDM_CONFIG_MODE 1 -#endif - -// PDM_CONFIG_EDGE - Edge - -// <0=> Left falling -// <1=> Left rising - -#ifndef PDM_CONFIG_EDGE -#define PDM_CONFIG_EDGE 0 -#endif - -// PDM_CONFIG_CLOCK_FREQ - Clock frequency - -// <134217728=> 1000k -// <138412032=> 1032k (default) -// <142606336=> 1067k - -#ifndef PDM_CONFIG_CLOCK_FREQ -#define PDM_CONFIG_CLOCK_FREQ 138412032 -#endif - -// PDM_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef PDM_CONFIG_IRQ_PRIORITY -#define PDM_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //PDM_ENABLED -// - -// PERIPHERAL_RESOURCE_SHARING_ENABLED - nrf_drv_common - Peripheral drivers common module - - -#ifndef PERIPHERAL_RESOURCE_SHARING_ENABLED -#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0 -#endif - -// PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver - - -#ifndef PPI_ENABLED -#define PPI_ENABLED 0 -#endif - -// PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver -//========================================================== -#ifndef PWM_ENABLED -#define PWM_ENABLED 0 -#endif -#if PWM_ENABLED -// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN -#define PWM_DEFAULT_CONFIG_OUT0_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN -#define PWM_DEFAULT_CONFIG_OUT1_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN -#define PWM_DEFAULT_CONFIG_OUT2_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN -#define PWM_DEFAULT_CONFIG_OUT3_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 MHz - -#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK -#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4 -#endif - -// PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode - -// <0=> Up -// <1=> Up and Down - -#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE -#define PWM_DEFAULT_CONFIG_COUNT_MODE 0 -#endif - -// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value -#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE -#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000 -#endif - -// PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode - -// <0=> Common -// <1=> Grouped -// <2=> Individual -// <3=> Waveform - -#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE -#define PWM_DEFAULT_CONFIG_LOAD_MODE 0 -#endif - -// PWM_DEFAULT_CONFIG_STEP_MODE - Step mode - -// <0=> Auto -// <1=> Triggered - -#ifndef PWM_DEFAULT_CONFIG_STEP_MODE -#define PWM_DEFAULT_CONFIG_STEP_MODE 0 -#endif - -// PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 -#endif - -// PWM0_ENABLED - Enable PWM0 instance - - -#ifndef PWM0_ENABLED -#define PWM0_ENABLED 0 -#endif - -// PWM1_ENABLED - Enable PWM1 instance - - -#ifndef PWM1_ENABLED -#define PWM1_ENABLED 0 -#endif - -// PWM2_ENABLED - Enable PWM2 instance - - -#ifndef PWM2_ENABLED -#define PWM2_ENABLED 0 -#endif - -#endif //PWM_ENABLED -// - -// QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver -//========================================================== -#ifndef QDEC_ENABLED -#define QDEC_ENABLED 0 -#endif -#if QDEC_ENABLED -// QDEC_CONFIG_REPORTPER - Report period - -// <0=> 10 Samples -// <1=> 40 Samples -// <2=> 80 Samples -// <3=> 120 Samples -// <4=> 160 Samples -// <5=> 200 Samples -// <6=> 240 Samples -// <7=> 280 Samples - -#ifndef QDEC_CONFIG_REPORTPER -#define QDEC_CONFIG_REPORTPER 0 -#endif - -// QDEC_CONFIG_SAMPLEPER - Sample period - -// <0=> 128 us -// <1=> 256 us -// <2=> 512 us -// <3=> 1024 us -// <4=> 2048 us -// <5=> 4096 us -// <6=> 8192 us -// <7=> 16384 us - -#ifndef QDEC_CONFIG_SAMPLEPER -#define QDEC_CONFIG_SAMPLEPER 7 -#endif - -// QDEC_CONFIG_PIO_A - A pin <0-31> - - -#ifndef QDEC_CONFIG_PIO_A -#define QDEC_CONFIG_PIO_A 31 -#endif - -// QDEC_CONFIG_PIO_B - B pin <0-31> - - -#ifndef QDEC_CONFIG_PIO_B -#define QDEC_CONFIG_PIO_B 31 -#endif - -// QDEC_CONFIG_PIO_LED - LED pin <0-31> - - -#ifndef QDEC_CONFIG_PIO_LED -#define QDEC_CONFIG_PIO_LED 31 -#endif - -// QDEC_CONFIG_LEDPRE - LED pre -#ifndef QDEC_CONFIG_LEDPRE -#define QDEC_CONFIG_LEDPRE 511 -#endif - -// QDEC_CONFIG_LEDPOL - LED polarity - -// <0=> Active low -// <1=> Active high - -#ifndef QDEC_CONFIG_LEDPOL -#define QDEC_CONFIG_LEDPOL 1 -#endif - -// QDEC_CONFIG_DBFEN - Debouncing enable - - -#ifndef QDEC_CONFIG_DBFEN -#define QDEC_CONFIG_DBFEN 0 -#endif - -// QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable - - -#ifndef QDEC_CONFIG_SAMPLE_INTEN -#define QDEC_CONFIG_SAMPLE_INTEN 0 -#endif - -// QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef QDEC_CONFIG_IRQ_PRIORITY -#define QDEC_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //QDEC_ENABLED -// - -// RNG_ENABLED - nrf_drv_rng - RNG peripheral driver -//========================================================== -#ifndef RNG_ENABLED -#define RNG_ENABLED 0 -#endif -#if RNG_ENABLED -// RNG_CONFIG_ERROR_CORRECTION - Error correction - - -#ifndef RNG_CONFIG_ERROR_CORRECTION -#define RNG_CONFIG_ERROR_CORRECTION 0 -#endif - -// RNG_CONFIG_POOL_SIZE - Pool size -#ifndef RNG_CONFIG_POOL_SIZE -#define RNG_CONFIG_POOL_SIZE 8 -#endif - -// RNG_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef RNG_CONFIG_IRQ_PRIORITY -#define RNG_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //RNG_ENABLED -// - -// RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver -//========================================================== -#ifndef RTC_ENABLED -#define RTC_ENABLED 0 -#endif -#if RTC_ENABLED -// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> - - -#ifndef RTC_DEFAULT_CONFIG_FREQUENCY -#define RTC_DEFAULT_CONFIG_FREQUENCY 32768 -#endif - -// RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering - - -#ifndef RTC_DEFAULT_CONFIG_RELIABLE -#define RTC_DEFAULT_CONFIG_RELIABLE 0 -#endif - -// RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 -#endif - -// RTC0_ENABLED - Enable RTC0 instance - - -#ifndef RTC0_ENABLED -#define RTC0_ENABLED 0 -#endif - -// RTC1_ENABLED - Enable RTC1 instance - - -#ifndef RTC1_ENABLED -#define RTC1_ENABLED 0 -#endif - -// RTC2_ENABLED - Enable RTC2 instance - - -#ifndef RTC2_ENABLED -#define RTC2_ENABLED 0 -#endif - -// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt -#ifndef NRF_MAXIMUM_LATENCY_US -#define NRF_MAXIMUM_LATENCY_US 2000 -#endif - -#endif //RTC_ENABLED -// - -// SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver -//========================================================== -#ifndef SAADC_ENABLED -#define SAADC_ENABLED 0 -#endif -#if SAADC_ENABLED -// SAADC_CONFIG_RESOLUTION - Resolution - -// <0=> 8 bit -// <1=> 10 bit -// <2=> 12 bit -// <3=> 14 bit - -#ifndef SAADC_CONFIG_RESOLUTION -#define SAADC_CONFIG_RESOLUTION 1 -#endif - -// SAADC_CONFIG_OVERSAMPLE - Sample period - -// <0=> Disabled -// <1=> 2x -// <2=> 4x -// <3=> 8x -// <4=> 16x -// <5=> 32x -// <6=> 64x -// <7=> 128x -// <8=> 256x - -#ifndef SAADC_CONFIG_OVERSAMPLE -#define SAADC_CONFIG_OVERSAMPLE 0 -#endif - -// SAADC_CONFIG_LP_MODE - Enabling low power mode - - -#ifndef SAADC_CONFIG_LP_MODE -#define SAADC_CONFIG_LP_MODE 0 -#endif - -// SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef SAADC_CONFIG_IRQ_PRIORITY -#define SAADC_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //SAADC_ENABLED -// - -// SPIS_ENABLED - nrf_drv_spis - SPI Slave driver -//========================================================== -#ifndef SPIS_ENABLED -#define SPIS_ENABLED 0 -#endif -#if SPIS_ENABLED -// SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 -#endif - -// SPIS_DEFAULT_MODE - Mode - -// <0=> MODE_0 -// <1=> MODE_1 -// <2=> MODE_2 -// <3=> MODE_3 - -#ifndef SPIS_DEFAULT_MODE -#define SPIS_DEFAULT_MODE 0 -#endif - -// SPIS_DEFAULT_BIT_ORDER - SPIS default bit order - -// <0=> MSB first -// <1=> LSB first - -#ifndef SPIS_DEFAULT_BIT_ORDER -#define SPIS_DEFAULT_BIT_ORDER 0 -#endif - -// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> - - -#ifndef SPIS_DEFAULT_DEF -#define SPIS_DEFAULT_DEF 255 -#endif - -// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> - - -#ifndef SPIS_DEFAULT_ORC -#define SPIS_DEFAULT_ORC 255 -#endif - -// SPIS0_ENABLED - Enable SPIS0 instance - - -#ifndef SPIS0_ENABLED -#define SPIS0_ENABLED 0 -#endif - -// SPIS1_ENABLED - Enable SPIS1 instance - - -#ifndef SPIS1_ENABLED -#define SPIS1_ENABLED 0 -#endif - -// SPIS2_ENABLED - Enable SPIS2 instance - - -#ifndef SPIS2_ENABLED -#define SPIS2_ENABLED 0 -#endif - -#endif //SPIS_ENABLED -// - -// SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver -//========================================================== -#ifndef SPI_ENABLED -#define SPI_ENABLED 0 -#endif -#if SPI_ENABLED -// SPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef SPI_CONFIG_LOG_ENABLED -#define SPI_CONFIG_LOG_ENABLED 0 -#endif -#if SPI_CONFIG_LOG_ENABLED -// SPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef SPI_CONFIG_LOG_LEVEL -#define SPI_CONFIG_LOG_LEVEL 3 -#endif - -// SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPI_CONFIG_INFO_COLOR -#define SPI_CONFIG_INFO_COLOR 0 -#endif - -// SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPI_CONFIG_DEBUG_COLOR -#define SPI_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //SPI_CONFIG_LOG_ENABLED -// - -// SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY -#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 -#endif - -// SPI0_ENABLED - Enable SPI0 instance -//========================================================== -#ifndef SPI0_ENABLED -#define SPI0_ENABLED 0 -#endif -#if SPI0_ENABLED -// SPI0_USE_EASY_DMA - Use EasyDMA - - -#ifndef SPI0_USE_EASY_DMA -#define SPI0_USE_EASY_DMA 1 -#endif - -#endif //SPI0_ENABLED -// - -// SPI1_ENABLED - Enable SPI1 instance -//========================================================== -#ifndef SPI1_ENABLED -#define SPI1_ENABLED 0 -#endif -#if SPI1_ENABLED -// SPI1_USE_EASY_DMA - Use EasyDMA - - -#ifndef SPI1_USE_EASY_DMA -#define SPI1_USE_EASY_DMA 1 -#endif - -#endif //SPI1_ENABLED -// - -// SPI2_ENABLED - Enable SPI2 instance -//========================================================== -#ifndef SPI2_ENABLED -#define SPI2_ENABLED 0 -#endif -#if SPI2_ENABLED -// SPI2_USE_EASY_DMA - Use EasyDMA - - -#ifndef SPI2_USE_EASY_DMA -#define SPI2_USE_EASY_DMA 1 -#endif - -#endif //SPI2_ENABLED -// - -#endif //SPI_ENABLED -// - -// TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver -//========================================================== -#ifndef TIMER_ENABLED -#define TIMER_ENABLED 0 -#endif -#if TIMER_ENABLED -// TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz -// <8=> 62.5 kHz -// <9=> 31.25 kHz - -#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY -#define TIMER_DEFAULT_CONFIG_FREQUENCY 0 -#endif - -// TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation - -// <0=> Timer -// <1=> Counter - -#ifndef TIMER_DEFAULT_CONFIG_MODE -#define TIMER_DEFAULT_CONFIG_MODE 0 -#endif - -// TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width - -// <0=> 16 bit -// <1=> 8 bit -// <2=> 24 bit -// <3=> 32 bit - -#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH -#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 -#endif - -// TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6 -#endif - -// TIMER0_ENABLED - Enable TIMER0 instance - - -#ifndef TIMER0_ENABLED -#define TIMER0_ENABLED 0 -#endif - -// TIMER1_ENABLED - Enable TIMER1 instance - - -#ifndef TIMER1_ENABLED -#define TIMER1_ENABLED 0 -#endif - -// TIMER2_ENABLED - Enable TIMER2 instance - - -#ifndef TIMER2_ENABLED -#define TIMER2_ENABLED 0 -#endif - -// TIMER3_ENABLED - Enable TIMER3 instance - - -#ifndef TIMER3_ENABLED -#define TIMER3_ENABLED 0 -#endif - -// TIMER4_ENABLED - Enable TIMER4 instance - - -#ifndef TIMER4_ENABLED -#define TIMER4_ENABLED 0 -#endif - -#endif //TIMER_ENABLED -// - -// TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver -//========================================================== -#ifndef TWIS_ENABLED -#define TWIS_ENABLED 0 -#endif -#if TWIS_ENABLED -// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 -#ifndef TWIS_DEFAULT_CONFIG_ADDR0 -#define TWIS_DEFAULT_CONFIG_ADDR0 0 -#endif - -// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 -#ifndef TWIS_DEFAULT_CONFIG_ADDR1 -#define TWIS_DEFAULT_CONFIG_ADDR1 0 -#endif - -// TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL -#define TWIS_DEFAULT_CONFIG_SCL_PULL 0 -#endif - -// TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL -#define TWIS_DEFAULT_CONFIG_SDA_PULL 0 -#endif - -// TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 -#endif - -// TWIS0_ENABLED - Enable TWIS0 instance - - -#ifndef TWIS0_ENABLED -#define TWIS0_ENABLED 0 -#endif - -// TWIS1_ENABLED - Enable TWIS1 instance - - -#ifndef TWIS1_ENABLED -#define TWIS1_ENABLED 0 -#endif - -// TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once - - -// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. - -#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -// TWIS_NO_SYNC_MODE - Remove support for synchronous mode - - -// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. - -#ifndef TWIS_NO_SYNC_MODE -#define TWIS_NO_SYNC_MODE 0 -#endif - -#endif //TWIS_ENABLED -// - -// TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver -//========================================================== -#ifndef TWI_ENABLED -#define TWI_ENABLED 0 -#endif -#if TWI_ENABLED -// TWI_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k - -#ifndef TWI_DEFAULT_CONFIG_FREQUENCY -#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 -#endif - -// TWI_DEFAULT_CONFIG_CLR_BUS_INIT - Enables bus clearing procedure during init - - -#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT -#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 -#endif - -// TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - - -#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 -#endif - -// TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY -#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 -#endif - -// TWI0_ENABLED - Enable TWI0 instance -//========================================================== -#ifndef TWI0_ENABLED -#define TWI0_ENABLED 0 -#endif -#if TWI0_ENABLED -// TWI0_USE_EASY_DMA - Use EasyDMA (if present) - - -#ifndef TWI0_USE_EASY_DMA -#define TWI0_USE_EASY_DMA 0 -#endif - -#endif //TWI0_ENABLED -// - -// TWI1_ENABLED - Enable TWI1 instance -//========================================================== -#ifndef TWI1_ENABLED -#define TWI1_ENABLED 0 -#endif -#if TWI1_ENABLED -// TWI1_USE_EASY_DMA - Use EasyDMA (if present) - - -#ifndef TWI1_USE_EASY_DMA -#define TWI1_USE_EASY_DMA 0 -#endif - -#endif //TWI1_ENABLED -// - -#endif //TWI_ENABLED -// - -// UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver -//========================================================== -#ifndef UART_ENABLED -#define UART_ENABLED 1 -#endif -#if UART_ENABLED -// UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef UART_DEFAULT_CONFIG_HWFC -#define UART_DEFAULT_CONFIG_HWFC 0 -#endif - -// UART_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included - -#ifndef UART_DEFAULT_CONFIG_PARITY -#define UART_DEFAULT_CONFIG_PARITY 0 -#endif - -// UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 57600 baud - -#ifndef UART_DEFAULT_CONFIG_BAUDRATE -#define UART_DEFAULT_CONFIG_BAUDRATE 30801920 -#endif - -// UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY -#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6 -#endif - -// UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA - - -#ifndef UART0_CONFIG_USE_EASY_DMA -#define UART0_CONFIG_USE_EASY_DMA 1 -#endif - -// UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA - - -#ifndef UART_EASY_DMA_SUPPORT -#define UART_EASY_DMA_SUPPORT 1 -#endif - -// UART_LEGACY_SUPPORT - Driver supporting Legacy mode - - -#ifndef UART_LEGACY_SUPPORT -#define UART_LEGACY_SUPPORT 1 -#endif - -#endif //UART_ENABLED -// - -// WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver -//========================================================== -#ifndef WDT_ENABLED -#define WDT_ENABLED 0 -#endif -#if WDT_ENABLED -// WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode - -// <1=> Run in SLEEP, Pause in HALT -// <8=> Pause in SLEEP, Run in HALT -// <9=> Run in SLEEP and HALT -// <0=> Pause in SLEEP and HALT - -#ifndef WDT_CONFIG_BEHAVIOUR -#define WDT_CONFIG_BEHAVIOUR 1 -#endif - -// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> - - -#ifndef WDT_CONFIG_RELOAD_VALUE -#define WDT_CONFIG_RELOAD_VALUE 2000 -#endif - -// WDT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef WDT_CONFIG_IRQ_PRIORITY -#define WDT_CONFIG_IRQ_PRIORITY 6 -#endif - -#endif //WDT_ENABLED -// - -// -//========================================================== - -// nRF_Libraries - -//========================================================== -// APP_FIFO_ENABLED - app_fifo - Software FIFO implementation - - -#ifndef APP_FIFO_ENABLED -#define APP_FIFO_ENABLED 1 -#endif - -// APP_MAILBOX_ENABLED - app_mailbox - Thread safe mailbox - - -#ifndef APP_MAILBOX_ENABLED -#define APP_MAILBOX_ENABLED 0 -#endif - -// APP_PWM_ENABLED - app_pwm - PWM functionality - - -#ifndef APP_PWM_ENABLED -#define APP_PWM_ENABLED 0 -#endif - -// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler -//========================================================== -#ifndef APP_SCHEDULER_ENABLED -#define APP_SCHEDULER_ENABLED 0 -#endif -#if APP_SCHEDULER_ENABLED -// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature - - -#ifndef APP_SCHEDULER_WITH_PAUSE -#define APP_SCHEDULER_WITH_PAUSE 0 -#endif - -// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling - - -#ifndef APP_SCHEDULER_WITH_PROFILER -#define APP_SCHEDULER_WITH_PROFILER 0 -#endif - -#endif //APP_SCHEDULER_ENABLED -// - -// APP_TIMER_ENABLED - app_timer - Application timer functionality -//========================================================== -#ifndef APP_TIMER_ENABLED -#define APP_TIMER_ENABLED 1 -#endif -#if APP_TIMER_ENABLED -// APP_TIMER_WITH_PROFILER - Enable app_timer profiling - - -#ifndef APP_TIMER_WITH_PROFILER -#define APP_TIMER_WITH_PROFILER 0 -#endif - -// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on - - -// If option is enabled RTC is kept running even if there is no active timers. -// This option can be used when app_timer is used for timestamping. - -#ifndef APP_TIMER_KEEPS_RTC_ACTIVE -#define APP_TIMER_KEEPS_RTC_ACTIVE 0 -#endif - -#endif //APP_TIMER_ENABLED -// - -// APP_TWI_ENABLED - app_twi - TWI transaction manager - - -#ifndef APP_TWI_ENABLED -#define APP_TWI_ENABLED 0 -#endif - -// APP_UART_ENABLED - app_uart - UART driver -//========================================================== -#ifndef APP_UART_ENABLED -#define APP_UART_ENABLED 1 -#endif -#if APP_UART_ENABLED -// APP_UART_DRIVER_INSTANCE - UART instance used - -// <0=> 0 - -#ifndef APP_UART_DRIVER_INSTANCE -#define APP_UART_DRIVER_INSTANCE 0 -#endif - -#endif //APP_UART_ENABLED -// - -// BUTTON_ENABLED - app_button - buttons handling module - - -#ifndef BUTTON_ENABLED -#define BUTTON_ENABLED 1 -#endif - -// CRC16_ENABLED - crc16 - CRC16 calculation routines - - -#ifndef CRC16_ENABLED -#define CRC16_ENABLED 0 -#endif - -// CRC32_ENABLED - crc32 - CRC32 calculation routines - - -#ifndef CRC32_ENABLED -#define CRC32_ENABLED 0 -#endif - -// ECC_ENABLED - ecc - Elliptic Curve Cryptography Library - - -#ifndef ECC_ENABLED -#define ECC_ENABLED 0 -#endif - -// FDS_ENABLED - fds - Flash data storage module -//========================================================== -#ifndef FDS_ENABLED -#define FDS_ENABLED 1 -#endif -#if FDS_ENABLED -// FDS_OP_QUEUE_SIZE - Size of the internal queue. -#ifndef FDS_OP_QUEUE_SIZE -#define FDS_OP_QUEUE_SIZE 4 -#endif - -// FDS_CHUNK_QUEUE_SIZE - Determines how many @ref fds_record_chunk_t structures can be buffered at any time. -#ifndef FDS_CHUNK_QUEUE_SIZE -#define FDS_CHUNK_QUEUE_SIZE 8 -#endif - -// FDS_MAX_USERS - Maximum number of callbacks that can be registered. -#ifndef FDS_MAX_USERS -#define FDS_MAX_USERS 8 -#endif - -// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. -// One of the virtual pages is reserved by the system for garbage collection. -// Therefore, the minimum is two virtual pages: one page to store data and -// one page to be used by the system for garbage collection. The total amount -// of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES -// @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes. - -#ifndef FDS_VIRTUAL_PAGES -#define FDS_VIRTUAL_PAGES 3 -#endif - -// FDS_VIRTUAL_PAGE_SIZE - The size of a virtual page of flash memory, expressed in number of 4-byte words. - - -// By default, a virtual page is the same size as a physical page. -// The size of a virtual page must be a multiple of the size of a physical page. -// <1024=> 1024 -// <2048=> 2048 - -#ifndef FDS_VIRTUAL_PAGE_SIZE -#define FDS_VIRTUAL_PAGE_SIZE 1024 -#endif - -#endif //FDS_ENABLED -// - -// FSTORAGE_ENABLED - fstorage - Flash storage module -//========================================================== -#ifndef FSTORAGE_ENABLED -#define FSTORAGE_ENABLED 1 -#endif -#if FSTORAGE_ENABLED -// FS_QUEUE_SIZE - Configures the size of the internal queue. -// Increase this if there are many users, or if it is likely that many -// operation will be queued at once without waiting for the previous operations -// to complete. In general, increase the queue size if you frequently receive -// @ref FS_ERR_QUEUE_FULL errors when calling @ref fs_store or @ref fs_erase. - -#ifndef FS_QUEUE_SIZE -#define FS_QUEUE_SIZE 4 -#endif - -// FS_OP_MAX_RETRIES - Number attempts to execute an operation if the SoftDevice fails. -// Increase this value if events return the @ref FS_ERR_OPERATION_TIMEOUT -// error often. The SoftDevice may fail to schedule flash access due to high BLE activity. - -#ifndef FS_OP_MAX_RETRIES -#define FS_OP_MAX_RETRIES 3 -#endif - -// FS_MAX_WRITE_SIZE_WORDS - Maximum number of words to be written to flash in a single operation. -// Tweaking this value can increase the chances of the SoftDevice being -// able to fit flash operations in between radio activity. This value is bound by the -// maximum number of words which the SoftDevice can write to flash in a single call to -// @ref sd_flash_write, which is 256 words for nRF51 ICs and 1024 words for nRF52 ICs. - -#ifndef FS_MAX_WRITE_SIZE_WORDS -#define FS_MAX_WRITE_SIZE_WORDS 1024 -#endif - -#endif //FSTORAGE_ENABLED -// - -// HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release - - -#ifndef HARDFAULT_HANDLER_ENABLED -#define HARDFAULT_HANDLER_ENABLED 0 -#endif - -// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI -//========================================================== -#ifndef HCI_MEM_POOL_ENABLED -#define HCI_MEM_POOL_ENABLED 0 -#endif -#if HCI_MEM_POOL_ENABLED -// HCI_TX_BUF_SIZE - TX buffer size in bytes. -#ifndef HCI_TX_BUF_SIZE -#define HCI_TX_BUF_SIZE 600 -#endif - -// HCI_RX_BUF_SIZE - RX buffer size in bytes. -#ifndef HCI_RX_BUF_SIZE -#define HCI_RX_BUF_SIZE 600 -#endif - -// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. -#ifndef HCI_RX_BUF_QUEUE_SIZE -#define HCI_RX_BUF_QUEUE_SIZE 4 -#endif - -#endif //HCI_MEM_POOL_ENABLED -// - -// HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI -//========================================================== -#ifndef HCI_SLIP_ENABLED -#define HCI_SLIP_ENABLED 0 -#endif -#if HCI_SLIP_ENABLED -// HCI_UART_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 57600 baud - -#ifndef HCI_UART_BAUDRATE -#define HCI_UART_BAUDRATE 30801920 -#endif - -// HCI_UART_FLOW_CONTROL - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef HCI_UART_FLOW_CONTROL -#define HCI_UART_FLOW_CONTROL 0 -#endif - -// HCI_UART_RX_PIN - UART RX pin -#ifndef HCI_UART_RX_PIN -#define HCI_UART_RX_PIN 8 -#endif - -// HCI_UART_TX_PIN - UART TX pin -#ifndef HCI_UART_TX_PIN -#define HCI_UART_TX_PIN 6 -#endif - -// HCI_UART_RTS_PIN - UART RTS pin -#ifndef HCI_UART_RTS_PIN -#define HCI_UART_RTS_PIN 5 -#endif - -// HCI_UART_CTS_PIN - UART CTS pin -#ifndef HCI_UART_CTS_PIN -#define HCI_UART_CTS_PIN 7 -#endif - -#endif //HCI_SLIP_ENABLED -// - -// HCI_TRANSPORT_ENABLED - hci_transport - HCI transport -//========================================================== -#ifndef HCI_TRANSPORT_ENABLED -#define HCI_TRANSPORT_ENABLED 0 -#endif -#if HCI_TRANSPORT_ENABLED -// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. -#ifndef HCI_MAX_PACKET_SIZE_IN_BITS -#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 -#endif - -#endif //HCI_TRANSPORT_ENABLED -// - -// LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module - - -#ifndef LED_SOFTBLINK_ENABLED -#define LED_SOFTBLINK_ENABLED 0 -#endif - -// LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module - - -#ifndef LOW_POWER_PWM_ENABLED -#define LOW_POWER_PWM_ENABLED 0 -#endif - -// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator -//========================================================== -#ifndef MEM_MANAGER_ENABLED -#define MEM_MANAGER_ENABLED 0 -#endif -#if MEM_MANAGER_ENABLED -// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> - - -#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT -#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 -#endif - -// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. -// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE -#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 -#endif - -// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> - - -#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT -#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. -// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 -#endif - -// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> - - -#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT -#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. -// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE -#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 -#endif - -// MEM_MANAGER_ENABLE_LOGS - Enable debug trace in the module. - - -#ifndef MEM_MANAGER_ENABLE_LOGS -#define MEM_MANAGER_ENABLE_LOGS 0 -#endif - -// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. - - -#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK -#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 -#endif - -#endif //MEM_MANAGER_ENABLED -// - -// NRF_CSENSE_ENABLED - nrf_csense - nrf_csense module -//========================================================== -#ifndef NRF_CSENSE_ENABLED -#define NRF_CSENSE_ENABLED 0 -#endif -#if NRF_CSENSE_ENABLED -// NRF_CSENSE_PAD_HYSTERESIS - Minimal value of change to decide that pad was touched. -#ifndef NRF_CSENSE_PAD_HYSTERESIS -#define NRF_CSENSE_PAD_HYSTERESIS 15 -#endif - -// NRF_CSENSE_PAD_DEVIATION - Minimal value measured on pad to take its value while calculating step. -#ifndef NRF_CSENSE_PAD_DEVIATION -#define NRF_CSENSE_PAD_DEVIATION 70 -#endif - -// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on pad to take its value into account. -#ifndef NRF_CSENSE_MIN_PAD_VALUE -#define NRF_CSENSE_MIN_PAD_VALUE 20 -#endif - -// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. -#ifndef NRF_CSENSE_MAX_PADS_NUMBER -#define NRF_CSENSE_MAX_PADS_NUMBER 20 -#endif - -// NRF_CSENSE_MAX_VALUE - Maximum normalized value got from measurement. -#ifndef NRF_CSENSE_MAX_VALUE -#define NRF_CSENSE_MAX_VALUE 1000 -#endif - -// NRF_CSENSE_OUTPUT_PIN - Output pin used by lower module. -// This is only used when running on NRF51. - -#ifndef NRF_CSENSE_OUTPUT_PIN -#define NRF_CSENSE_OUTPUT_PIN 30 -#endif - -#endif //NRF_CSENSE_ENABLED -// - -// NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor module -//========================================================== -#ifndef NRF_DRV_CSENSE_ENABLED -#define NRF_DRV_CSENSE_ENABLED 0 -#endif -#if NRF_DRV_CSENSE_ENABLED -// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (except nRF51) -#ifndef TIMER0_FOR_CSENSE -#define TIMER0_FOR_CSENSE 1 -#endif - -// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (except nRF51) -#ifndef TIMER1_FOR_CSENSE -#define TIMER1_FOR_CSENSE 2 -#endif - -// MEASUREMENT_PERIOD - Single measurement period. -// Time of single measurement can be calculated as T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). I_SOURCE, VUP and VDOWN are values used to initialize COMP and C is capacitance of used pad. - -#ifndef MEASUREMENT_PERIOD -#define MEASUREMENT_PERIOD 20 -#endif - -#endif //NRF_DRV_CSENSE_ENABLED -// - -// RETARGET_ENABLED - retarget - Retargeting stdio functions - - -#ifndef RETARGET_ENABLED -#define RETARGET_ENABLED 1 -#endif - -// SLIP_ENABLED - slip - SLIP encoding decoding - - -#ifndef SLIP_ENABLED -#define SLIP_ENABLED 0 -#endif - -// -//========================================================== - -// nRF_Log - -//========================================================== -// NRF_LOG_ENABLED - nrf_log - Logging -//========================================================== -#ifndef NRF_LOG_ENABLED -#define NRF_LOG_ENABLED 0 -#endif -#if NRF_LOG_ENABLED -// NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string -//========================================================== -#ifndef NRF_LOG_USES_COLORS -#define NRF_LOG_USES_COLORS 0 -#endif -#if NRF_LOG_USES_COLORS -// NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LOG_COLOR_DEFAULT -#define NRF_LOG_COLOR_DEFAULT 0 -#endif - -// NRF_LOG_ERROR_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LOG_ERROR_COLOR -#define NRF_LOG_ERROR_COLOR 0 -#endif - -// NRF_LOG_WARNING_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LOG_WARNING_COLOR -#define NRF_LOG_WARNING_COLOR 0 -#endif - -#endif //NRF_LOG_USES_COLORS -// - -// NRF_LOG_DEFAULT_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_LOG_DEFAULT_LEVEL -#define NRF_LOG_DEFAULT_LEVEL 3 -#endif - -// NRF_LOG_DEFERRED - Enable deffered logger. - -// Log data is buffered and can be processed in idle. -//========================================================== -#ifndef NRF_LOG_DEFERRED -#define NRF_LOG_DEFERRED 1 -#endif -#if NRF_LOG_DEFERRED -// NRF_LOG_DEFERRED_BUFSIZE - Size of the buffer for logs in words. -// Must be power of 2 - -#ifndef NRF_LOG_DEFERRED_BUFSIZE -#define NRF_LOG_DEFERRED_BUFSIZE 256 -#endif - -#endif //NRF_LOG_DEFERRED -// - -// NRF_LOG_USES_TIMESTAMP - Enable timestamping - - -// Function for getting the timestamp is provided by the user - -#ifndef NRF_LOG_USES_TIMESTAMP -#define NRF_LOG_USES_TIMESTAMP 0 -#endif - -#endif //NRF_LOG_ENABLED -// - -// -//========================================================== - -// <<< end of configuration section >>> -#endif //SDK_CONFIG_H - From e60fa9b3e127f21e6fafd6e96e102de27fec645a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Mar 2017 21:25:51 +0100 Subject: [PATCH 436/809] nrf5/sdk: Fixing unaligned access issues for nrf51 (cortex-m0) in bluetooth le driver --- nrf5/sdk/ble_drv.c | 50 ++++++++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 19 deletions(-) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index 13eca28569..73c19554ef 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -286,8 +286,9 @@ bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj) { if (p_service_obj->p_uuid->type > BLE_UUID_TYPE_BLE) { ble_uuid_t uuid; - uuid.type = p_service_obj->p_uuid->uuid_vs_idx; - uuid.uuid = (uint16_t)(*(uint16_t *)&p_service_obj->p_uuid->value[0]); + uuid.type = p_service_obj->p_uuid->uuid_vs_idx; + uuid.uuid = p_service_obj->p_uuid->value[0]; + uuid.uuid += p_service_obj->p_uuid->value[1] << 8; if (sd_ble_gatts_service_add(p_service_obj->type, &uuid, @@ -296,11 +297,14 @@ bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj) { "Can not add Service.")); } } else if (p_service_obj->p_uuid->type == BLE_UUID_TYPE_BLE) { + printf("adding service\n"); ble_uuid_t uuid; - uuid.type = p_service_obj->p_uuid->type; - uuid.uuid = (uint16_t)(*(uint16_t *)&p_service_obj->p_uuid->value[0]); + uuid.type = p_service_obj->p_uuid->type; + uuid.uuid = p_service_obj->p_uuid->value[0]; + uuid.uuid += p_service_obj->p_uuid->value[1] << 8; + printf("adding service\n"); if (sd_ble_gatts_service_add(p_service_obj->type, &uuid, &p_service_obj->handle) != 0) { @@ -347,8 +351,9 @@ bool ble_drv_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj) { char_md.p_cccd_md = NULL; } - uuid.type = p_char_obj->p_uuid->type; - uuid.uuid = (uint16_t)(*(uint16_t *)&p_char_obj->p_uuid->value[0]); + uuid.type = p_char_obj->p_uuid->type; + uuid.uuid = p_char_obj->p_uuid->value[0]; + uuid.uuid += p_char_obj->p_uuid->value[1] << 8; memset(&attr_md, 0, sizeof(attr_md)); @@ -458,9 +463,9 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i]; ble_uuid_t uuid; - uuid.type = p_service->p_uuid->type; - uuid.uuid = (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]); - + uuid.type = p_service->p_uuid->type; + uuid.uuid = p_service->p_uuid->value[0]; + uuid.uuid += p_service->p_uuid->value[1] << 8; // calculate total size of uuids if (sd_ble_uuid_encode(&uuid, &encoded_size, NULL) != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, @@ -481,9 +486,10 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { uuid_total_size += encoded_size; // size of entry byte_pos += encoded_size; // relative to adv data packet - BLE_DRIVER_LOG("ADV: uuid size: %u, type: %u, uuid: %u, vs_idx: %u\n", + BLE_DRIVER_LOG("ADV: uuid size: %u, type: %u, uuid: %x%x, vs_idx: %u\n", encoded_size, p_service->p_uuid->type, - (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]), + p_service->p_uuid->value[1], + p_service->p_uuid->value[0], p_service->p_uuid->uuid_vs_idx); } @@ -506,8 +512,9 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i]; ble_uuid_t uuid; - uuid.type = p_service->p_uuid->uuid_vs_idx; - uuid.uuid = (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]); + uuid.type = p_service->p_uuid->uuid_vs_idx; + uuid.uuid = p_service->p_uuid->value[0]; + uuid.uuid += p_service->p_uuid->value[1] << 8; // calculate total size of uuids if (sd_ble_uuid_encode(&uuid, &encoded_size, NULL) != 0) { @@ -529,9 +536,10 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { uuid_total_size += encoded_size; // size of entry byte_pos += encoded_size; // relative to adv data packet - BLE_DRIVER_LOG("ADV: uuid size: %u, type: %u, uuid: %u, vs_idx: %u\n", + BLE_DRIVER_LOG("ADV: uuid size: %u, type: %x%x, uuid: %u, vs_idx: %u\n", encoded_size, p_service->p_uuid->type, - (uint16_t)(*(uint16_t *)&p_service->p_uuid->value[0]), + p_service->p_uuid->value[1], + p_service->p_uuid->value[0], p_service->p_uuid->uuid_vs_idx); } @@ -556,10 +564,14 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { m_adv_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS); // approx 8 ms m_adv_params.timeout = 0; // infinite advertisment - if (m_adv_in_progress && sd_ble_gap_adv_stop() != 0) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can not stop advertisment.")); +#if (BLUETOOTH_SD == 132) + if (m_adv_in_progress == true) { + if (sd_ble_gap_adv_stop() != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not stop advertisment.")); + } } +#endif m_adv_in_progress = false; uint32_t err_code = sd_ble_gap_adv_start(&m_adv_params); @@ -670,7 +682,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GATTS_EVT_WRITE: BLE_DRIVER_LOG("GATTS write\n"); - uint16_t handle = p_ble_evt->evt.gatts_evt.params.write.handle; + uint16_t handle = p_ble_evt->evt.gatts_evt.params.write.handle; uint16_t data_len = p_ble_evt->evt.gatts_evt.params.write.len; uint8_t * p_data = &p_ble_evt->evt.gatts_evt.params.write.data[0]; From 4efedb67b647d87a4421c84a763d8122224ab1d2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Mar 2017 22:43:06 +0100 Subject: [PATCH 437/809] nrf5/modules: Enable ubluepy constants for CONNECT and DISCONNECT for other bluetooth stacks than s132. --- nrf5/modules/ubluepy/ubluepy_constants.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_constants.c b/nrf5/modules/ubluepy/ubluepy_constants.c index 4670b62272..c9980b06bd 100644 --- a/nrf5/modules/ubluepy/ubluepy_constants.c +++ b/nrf5/modules/ubluepy/ubluepy_constants.c @@ -32,11 +32,9 @@ #include "modubluepy.h" STATIC const mp_map_elem_t ubluepy_constants_locals_dict_table[] = { -#if (BLUETOOTH_SD == 132) // GAP events { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_OBJ_NEW_SMALL_INT(16) }, { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_OBJ_NEW_SMALL_INT(17) }, -#endif { MP_OBJ_NEW_QSTR(MP_QSTR_UUID_CCCD), MP_OBJ_NEW_SMALL_INT(0x2902) }, }; From 22f66e274da9d7d35546a3087dfb5e2c06421b48 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 2 Mar 2017 22:48:04 +0100 Subject: [PATCH 438/809] nrf5/sdk: Updating bluetooth le driver to handle SEC PARAM REQUEST by replying that pairing is not supported. Moving initialization of adv and tx in progress state variables to stack enable function. --- nrf5/sdk/ble_drv.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index 73c19554ef..143c189b6b 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -71,8 +71,8 @@ if (ble_drv_stack_enabled() == 0) { \ (void)ble_drv_stack_enable(); \ } -static volatile bool m_adv_in_progress = false; -static volatile bool m_tx_in_progress = false; +static volatile bool m_adv_in_progress; +static volatile bool m_tx_in_progress; static ubluepy_gap_evt_callback_t ubluepy_gap_event_handler; static ubluepy_gatts_evt_callback_t ubluepy_gatts_event_handler; @@ -101,6 +101,9 @@ void softdevice_assert_handler(uint32_t id, uint32_t pc, uint32_t info) { } #endif uint32_t ble_drv_stack_enable(void) { + m_adv_in_progress = false; + m_tx_in_progress = false; + #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) memset(&nrf_nvic_state, 0, sizeof(nrf_nvic_state_t)); #endif @@ -665,6 +668,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { BLE_DRIVER_LOG("GAP CONNECT\n"); m_adv_in_progress = false; ubluepy_gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); + ble_gap_conn_params_t conn_params; (void)sd_ble_gap_ppcp_get(&conn_params); (void)sd_ble_gap_conn_param_update(p_ble_evt->evt.gap_evt.conn_handle, &conn_params); @@ -710,6 +714,14 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { m_tx_in_progress = false; break; + case BLE_GAP_EVT_SEC_PARAMS_REQUEST: + BLE_DRIVER_LOG("BLE EVT SEC PARAMS REQUEST\n"); + // pairing not supported + (void)sd_ble_gap_sec_params_reply(p_ble_evt->evt.gatts_evt.conn_handle, + BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP, + NULL, NULL); + break; + default: BLE_DRIVER_LOG(">>> unhandled evt: 0x" HEX2_FMT "\n", p_ble_evt->header.evt_id); break; From db3dd8bc8bab7c9d3279cbcb0b5a4e0170ccc8be Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 3 Mar 2017 00:04:13 +0100 Subject: [PATCH 439/809] nrf5/modules: Updating ubluepy peripheral to pass handle value to python event handler instead of data length. Data length can be derived from the bytearray structure. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index a0a196913b..f66861d7f1 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -53,7 +53,7 @@ STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn mp_obj_t args[3]; mp_uint_t num_of_args = 3; args[0] = MP_OBJ_NEW_SMALL_INT(event_id); - args[1] = MP_OBJ_NEW_SMALL_INT(length); + args[1] = MP_OBJ_NEW_SMALL_INT(conn_handle); if (data != NULL) { args[2] = mp_obj_new_bytearray_by_ref(length, data); } else { @@ -74,7 +74,7 @@ STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t at mp_obj_t args[3]; mp_uint_t num_of_args = 3; args[0] = MP_OBJ_NEW_SMALL_INT(event_id); - args[1] = MP_OBJ_NEW_SMALL_INT(length); + args[1] = MP_OBJ_NEW_SMALL_INT(attr_handle); if (data != NULL) { args[2] = mp_obj_new_bytearray_by_ref(length, data); } else { From df31508d6ffd48e8cfb562b756c4ecd1fdd6f403 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 3 Mar 2017 00:05:09 +0100 Subject: [PATCH 440/809] nrf5/modules: Updating example in ubluepy header to use handle instead of data length upon reception of an event. --- nrf5/modules/ubluepy/modubluepy.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index c9d924a8bf..2b1c6f62d3 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -40,8 +40,9 @@ DB setup: from ubluepy import Service, Characteristic, UUID, Peripheral, constants from pyb import LED -def event_handler(id, length, data): - print("BLE event:", id, "length:", length) +def event_handler(id, handle, data): + print("BLE event:", id, "handle:", handle) + print(data) if id == constants.EVT_GAP_CONNECTED: # connected From d057a936750f1b8c18312fbc104aa9853f8c7cf5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 3 Mar 2017 00:06:51 +0100 Subject: [PATCH 441/809] nrf5/sdk: Rename cccd_enable variable to m_cccd_enable in bluetooth le UART driver. Also made the variable volatile. --- nrf5/sdk/ble_uart.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/nrf5/sdk/ble_uart.c b/nrf5/sdk/ble_uart.c index 8d675f11f2..b3bad7c41f 100644 --- a/nrf5/sdk/ble_uart.c +++ b/nrf5/sdk/ble_uart.c @@ -74,7 +74,7 @@ static ubluepy_peripheral_obj_t ble_uart_peripheral = { .conn_handle = 0xFFFF, }; -static bool cccd_enabled; +static volatile bool m_cccd_enabled; ringBuffer_typedef(uint8_t, ringbuffer_t); @@ -138,7 +138,7 @@ STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t at if (event_id == 80) { // gatts write if (ble_uart_char_tx.cccd_handle == attr_handle) { - cccd_enabled = true; + m_cccd_enabled = true; } else if (ble_uart_char_rx.handle == attr_handle) { for (uint16_t i = 0; i < length; i++) { bufferWrite(mp_rx_ring_buffer, data[i]); @@ -177,7 +177,6 @@ void ble_uart_init0(void) { mp_obj_list_append(ble_uart_service.char_list, MP_OBJ_FROM_PTR(&ble_uart_char_rx)); // setup the peripheral - (void)ble_uart_peripheral; ble_uart_peripheral.service_list = mp_obj_new_list(0, NULL); mp_obj_list_append(ble_uart_peripheral.service_list, MP_OBJ_FROM_PTR(&ble_uart_service)); ble_uart_service.p_periph = &ble_uart_peripheral; @@ -206,7 +205,7 @@ void ble_uart_init0(void) { (void)device_name; (void)services; - cccd_enabled = false; + m_cccd_enabled = false; // initialize ring buffer m_rx_ring_buffer.size = sizeof(m_rx_ring_buffer_data) + 1; @@ -216,7 +215,7 @@ void ble_uart_init0(void) { (void)ble_drv_advertise_data(&adv_data); - while (cccd_enabled != true) { + while (m_cccd_enabled != true) { ; } } From 235c0edacb7274857bd1725dd7757ff18e55bf2f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 3 Mar 2017 00:11:42 +0100 Subject: [PATCH 442/809] nrf5/sdk: Updating ringbuffer.h to use volatile variables for start and end. --- nrf5/sdk/ringbuffer.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/sdk/ringbuffer.h b/nrf5/sdk/ringbuffer.h index 3f54a6200c..3438b5c9b5 100644 --- a/nrf5/sdk/ringbuffer.h +++ b/nrf5/sdk/ringbuffer.h @@ -67,8 +67,8 @@ #define ringBuffer_typedef(T, NAME) \ typedef struct { \ int size; \ - int start; \ - int end; \ + volatile int start; \ + volatile int end; \ T* elems; \ } NAME From 159202ad00bd73d5efb3888221d4ca7514f3e9ba Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 3 Mar 2017 00:36:25 +0100 Subject: [PATCH 443/809] lib/utils: Expose pyb_set_repl_info function public The patch enables the possibility to disable or initialize the repl info from outside of the module. Can also be used to initialize the repl_display_debugging_info in pyexec.c if not startup file is clearing .bss segment. --- lib/utils/pyexec.h | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/utils/pyexec.h b/lib/utils/pyexec.h index 0c7567e273..d7d2a85ab7 100644 --- a/lib/utils/pyexec.h +++ b/lib/utils/pyexec.h @@ -48,6 +48,7 @@ int pyexec_frozen_module(const char *name); void pyexec_event_repl_init(void); int pyexec_event_repl_process_char(int c); extern uint8_t pyexec_repl_active; +mp_obj_t pyb_set_repl_info(mp_obj_t o_value); MP_DECLARE_CONST_FUN_OBJ_1(pyb_set_repl_info_obj); From c300e3f196e5487833e36cfb6920cb8cbf70eb31 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 3 Mar 2017 00:40:44 +0100 Subject: [PATCH 444/809] nrf5: Initialize repl_display_debugging_info in pyexec.c for cortex-m0 targets. --- nrf5/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/main.c b/nrf5/main.c index d8f91c2336..3e81372af8 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -98,6 +98,8 @@ int main(int argc, char **argv) { mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script) mp_obj_list_init(mp_sys_argv, 0); + pyb_set_repl_info(MP_OBJ_NEW_SMALL_INT(0)); + readline_init0(); pin_init0(); From e95ec1a285a9a0eecdab0d454665bc390373448a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 3 Mar 2017 23:20:38 +0100 Subject: [PATCH 445/809] nrf5/sdk: Adding support for initializing the bluetooth stack using RC oscillator instead of crystal. If BLUETOOTH_LFCLK_RC is set in CFLAGS, this variant of softdevice enable will be activated. --- nrf5/sdk/ble_drv.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index 143c189b6b..ed0e400740 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -109,8 +109,13 @@ uint32_t ble_drv_stack_enable(void) { #endif #if (BLUETOOTH_SD == 100) || (BLUETOOTH_SD == 110) +#if BLUETOOTH_LFCLK_RC + uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_RC_250_PPM_4000MS_CALIBRATION, + softdevice_assert_handler); +#else uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, softdevice_assert_handler); +#endif // BLUETOOTH_LFCLK_RC #else nrf_clock_lf_cfg_t clock_config = { .source = NRF_CLOCK_LF_SRC_XTAL, From 2af06bd3fa7b2bd00a08ce10d1bde1058e12d402 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 3 Mar 2017 23:21:47 +0100 Subject: [PATCH 446/809] nrf5/boards: Adding BLUETOOTH_LFCLK_RC to CFLAGS in microbit s110 makefile. --- nrf5/boards/microbit/mpconfigboard_s110.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/boards/microbit/mpconfigboard_s110.mk b/nrf5/boards/microbit/mpconfigboard_s110.mk index 0cd554415f..fbe641cf86 100644 --- a/nrf5/boards/microbit/mpconfigboard_s110.mk +++ b/nrf5/boards/microbit/mpconfigboard_s110.mk @@ -3,3 +3,4 @@ MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 LD_FILE = boards/nrf51822_aa_s110.ld FLASHER = pyocd +CFLAGS += -DBLUETOOTH_LFCLK_RC From 1aeb74a426508a56a56efaa8a232b7a31bda12e3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 01:24:05 +0100 Subject: [PATCH 447/809] nrf51: Removing stack section from startup file as it got added to the final hex file. Thanks dhylands for helping out. --- nrf5/device/nrf51/startup_nrf51.s | 3 --- 1 file changed, 3 deletions(-) diff --git a/nrf5/device/nrf51/startup_nrf51.s b/nrf5/device/nrf51/startup_nrf51.s index b20f3745fa..9b6d541708 100644 --- a/nrf5/device/nrf51/startup_nrf51.s +++ b/nrf5/device/nrf51/startup_nrf51.s @@ -27,9 +27,6 @@ .syntax unified .arch armv6-m - .section .stack - .align 3 - .global __Vectors .global Default_Handler From ef6d583ec3b358c0ec925497395a97ef21dd54f7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 01:29:05 +0100 Subject: [PATCH 448/809] nrf5/boards: Updating nrf51822_aa_s110.ld to be more generic, leaving all RAM not used for stack, .bss and .data to the heap. --- nrf5/boards/nrf51822_aa_s110.ld | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/nrf5/boards/nrf51822_aa_s110.ld b/nrf5/boards/nrf51822_aa_s110.ld index e63b50aadc..aa5ff3f838 100644 --- a/nrf5/boards/nrf51822_aa_s110.ld +++ b/nrf5/boards/nrf51822_aa_s110.ld @@ -9,13 +9,13 @@ MEMORY FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */ FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */ FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 159 KiB */ - RAM (xrw) : ORIGIN = 0x20001000, LENGTH = 0x003000 /* 12 KiB */ + RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x002000 /* 8 KiB */ } /* produce a link error if there is not this amount of RAM for these sections */ _minimum_stack_size = 2K; -_minimum_heap_size = 8K; - +_minimum_heap_size = 1K; + /* top end of the stack */ /*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ @@ -23,6 +23,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20003000; /* tunable */ +_heap_end = 0x20003c00; /* tunable */ INCLUDE "boards/common.ld" From f2a7e198d285b9f18e343b00cebffcf337bc17fc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 01:36:06 +0100 Subject: [PATCH 449/809] nrf5/sdk: Updating low frequency clock calibration from 4 seconds to 250 ms for stack enable when BLUETOOTH_LFCLK_RC is enabled. --- nrf5/sdk/ble_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/sdk/ble_drv.c index ed0e400740..b66f163cf3 100644 --- a/nrf5/sdk/ble_drv.c +++ b/nrf5/sdk/ble_drv.c @@ -110,7 +110,7 @@ uint32_t ble_drv_stack_enable(void) { #if (BLUETOOTH_SD == 100) || (BLUETOOTH_SD == 110) #if BLUETOOTH_LFCLK_RC - uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_RC_250_PPM_4000MS_CALIBRATION, + uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_RC_250_PPM_250MS_CALIBRATION, softdevice_assert_handler); #else uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, From 80c9c2e3c0036b4dc21036ff460bf1b0ea0e4165 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 02:14:27 +0100 Subject: [PATCH 450/809] nrf5/boards: Adding support for SPI, I2C, ADC, and Temp in machine modules in micro:bit target. Also activating hal drivers for the peripherals. --- nrf5/boards/microbit/mpconfigboard.h | 15 ++++++++++++--- nrf5/boards/microbit/nrf51_hal_conf.h | 9 ++++++--- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index fd5fc7dfed..25816c993d 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -30,10 +30,13 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51" -#define MICROPY_PY_MACHINE_HW_SPI (0) +#define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_PWM (0) -#define MICROPY_PY_MACHINE_TIMER (0) -#define MICROPY_PY_MACHINE_RTC (0) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) +#define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_PY_USOCKET (0) #define MICROPY_PY_NETWORK (0) @@ -63,4 +66,10 @@ #define MICROPY_HW_UART1_TX (pin_A24) #define MICROPY_HW_UART1_HWFC (0) +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (pin_A13) +#define MICROPY_HW_SPI0_MOSI (pin_A15) +#define MICROPY_HW_SPI0_MISO (pin_A14) + #define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/microbit/nrf51_hal_conf.h b/nrf5/boards/microbit/nrf51_hal_conf.h index b24164aeb1..e83e2d346e 100644 --- a/nrf5/boards/microbit/nrf51_hal_conf.h +++ b/nrf5/boards/microbit/nrf51_hal_conf.h @@ -2,9 +2,12 @@ #define NRF51_HAL_CONF_H__ #define HAL_UART_MODULE_ENABLED -// #define HAL_SPI_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED -// #define HAL_RTC_MODULE_ENABLED -// #define HAL_TIMER_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ From 309ae12346c4e42d1e25fbef1d3309d2da8fadb2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 15:06:08 +0100 Subject: [PATCH 451/809] nrf5: Starting process of renaming files in sdk folder to facilitate renaming of the folder and make it more logical. Transition will be from sdk to bluetooth. --- nrf5/Makefile | 2 +- nrf5/mpconfigport.h | 2 +- nrf5/sdk/{sdk_common.mk => bluetooth_common.mk} | 0 nrf5/sdk/help_sd.h | 2 +- nrf5/sdk/iot_0.9.0/modnwble6lowpan.c | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) rename nrf5/sdk/{sdk_common.mk => bluetooth_common.mk} (100%) diff --git a/nrf5/Makefile b/nrf5/Makefile index f48660b413..cf71189da2 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -31,7 +31,7 @@ else include ../py/mkenv.mk include boards/$(BOARD)/mpconfigboard_$(SD_LOWER).mk - include sdk/sdk_common.mk + include sdk/bluetooth_common.mk endif # qstr definitions (must come before including py.mk) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 903bb6848f..f0596de52b 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -206,7 +206,7 @@ // if sdk is in use, import configuration #if BLUETOOTH_SD -#include "nrf5_sdk_conf.h" +#include "bluetooth_conf.h" #endif #ifndef MICROPY_PY_UBLUEPY diff --git a/nrf5/sdk/sdk_common.mk b/nrf5/sdk/bluetooth_common.mk similarity index 100% rename from nrf5/sdk/sdk_common.mk rename to nrf5/sdk/bluetooth_common.mk diff --git a/nrf5/sdk/help_sd.h b/nrf5/sdk/help_sd.h index f6d5ef6565..fa48d4a578 100644 --- a/nrf5/sdk/help_sd.h +++ b/nrf5/sdk/help_sd.h @@ -27,7 +27,7 @@ #ifndef HELP_SD_H__ #define HELP_SD_H__ -#include "nrf5_sdk_conf.h" +#include "bluetooth_conf.h" #if MICROPY_PY_BLE diff --git a/nrf5/sdk/iot_0.9.0/modnwble6lowpan.c b/nrf5/sdk/iot_0.9.0/modnwble6lowpan.c index 80f1b81e0a..f8b3be89f4 100644 --- a/nrf5/sdk/iot_0.9.0/modnwble6lowpan.c +++ b/nrf5/sdk/iot_0.9.0/modnwble6lowpan.c @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -#include "nrf5_sdk_conf.h" +#include "bluetooth_conf.h" #if MICROPY_PY_BLE_6LOWPAN From ec35861938899ec79a3ea77e2104ed8cb647e5cc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 17:19:29 +0100 Subject: [PATCH 452/809] nrf5: Renaming nrf5_sdk_conf.h to bluetooth_conf.h --- nrf5/sdk/{nrf5_sdk_conf.h => bluetooth_conf.h} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename nrf5/sdk/{nrf5_sdk_conf.h => bluetooth_conf.h} (100%) diff --git a/nrf5/sdk/nrf5_sdk_conf.h b/nrf5/sdk/bluetooth_conf.h similarity index 100% rename from nrf5/sdk/nrf5_sdk_conf.h rename to nrf5/sdk/bluetooth_conf.h From 5e89a27ba1b0d19ad8ce6a767edd4ccbbdaa2f55 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 17:52:20 +0100 Subject: [PATCH 453/809] nrf5: Merging sdk makefiles into bluetooth_common.mk. s1xx_iot is still left out of this refactoring. --- nrf5/sdk/bluetooth_common.mk | 31 +++++++++++++++++-------------- nrf5/sdk/sdk_10.0.0/sdk.mk | 17 ----------------- nrf5/sdk/sdk_12.1.0/sdk.mk | 15 --------------- 3 files changed, 17 insertions(+), 46 deletions(-) delete mode 100644 nrf5/sdk/sdk_10.0.0/sdk.mk delete mode 100644 nrf5/sdk/sdk_12.1.0/sdk.mk diff --git a/nrf5/sdk/bluetooth_common.mk b/nrf5/sdk/bluetooth_common.mk index e4609ba123..f85bc5b47b 100644 --- a/nrf5/sdk/bluetooth_common.mk +++ b/nrf5/sdk/bluetooth_common.mk @@ -1,25 +1,28 @@ -SDK_MODULES ?= +SOFTDEV_HEX_NAME ?= -ifeq ($(SD), s1xx) - SDK_MODULES = iot_0.9.0 -else ifeq ($(SD), s110) - SDK_MODULES = sdk_10.0.0 +ifeq ($(SD), s110) + INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers + CFLAGS += -DBLUETOOTH_SD_DEBUG=1 + CFLAGS += -DBLUETOOTH_SD=110 + SOFTDEV_HEX_NAME = s110_nrf51_8.0.0_softdevice.hex else ifeq ($(SD), s120) - SDK_MODULES = sdk_10.0.0 - $(error No supported BLE wrapper) + $(error No BLE wrapper available yet) else ifeq ($(SD), s130) - SDK_MODULES = sdk_10.0.0 + $(error No BLE wrapper available yet) else ifeq ($(SD), s132) - SDK_MODULES = sdk_12.1.0 - SDK_COMPONENTS = 0 + INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers + INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers/$(MCU_VARIANT) + CFLAGS += -DBLUETOOTH_SD_DEBUG=1 + CFLAGS += -DBLUETOOTH_SD=132 + SOFTDEV_HEX_NAME = s132_nrf52_3.0.0_softdevice.hex +#else ifeq ($(SD), s1xx) +# include sdk/iot_0.9.0/sdk.mk else - $(error No SDK configured for this SD) + $(error Incorrect softdevice set flag) endif -SDK_MODULES_PATH = sdk/$(SDK_MODULES)/ - -include $(SDK_MODULES_PATH)sdk.mk +SOFTDEV_HEX = $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/$(SD)/hex/$(SOFTDEV_HEX_NAME))) INC += -I./sdk diff --git a/nrf5/sdk/sdk_10.0.0/sdk.mk b/nrf5/sdk/sdk_10.0.0/sdk.mk deleted file mode 100644 index a5097eabc9..0000000000 --- a/nrf5/sdk/sdk_10.0.0/sdk.mk +++ /dev/null @@ -1,17 +0,0 @@ - -INC += -I./$(SDK_MODULES_PATH) - -# Nothing to build from SDK. -# include $(SDK_MODULES_PATH)build.mk - -INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 - -# softdevice .hex file -ifeq ($(SD), s110) -CFLAGS += -DBLUETOOTH_SD=110 -SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s110/hex/s110_nrf51_8.0.0_softdevice.hex)) -else ifeq ($(SD), s120) -CFLAGS += -DBLUETOOTH_SD=120 -SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s120/hex/s120_nrf51_2.1.0_softdevice.hex)) -endif \ No newline at end of file diff --git a/nrf5/sdk/sdk_12.1.0/sdk.mk b/nrf5/sdk/sdk_12.1.0/sdk.mk deleted file mode 100644 index b8ba631642..0000000000 --- a/nrf5/sdk/sdk_12.1.0/sdk.mk +++ /dev/null @@ -1,15 +0,0 @@ - -INC += -I./$(SDK_MODULES_PATH) - -INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers -INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers/$(MCU_VARIANT) -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 - -# softdevice .hex file -ifeq ($(SD), s130) -CFLAGS += -DBLUETOOTH_SD=130 -SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s130/hex/s130_nrf51_2.0.1_softdevice.hex)) -else ifeq ($(SD), s132) -CFLAGS += -DBLUETOOTH_SD=132 -SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s132/hex/s132_nrf52_3.0.0_softdevice.hex)) -endif From 9e36242259867aceff1a7e8a2c0fddf4823126b0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 17:54:15 +0100 Subject: [PATCH 454/809] nrf5: Renaming sdk folder to bluetooth. --- nrf5/{sdk => bluetooth}/ble_drv.c | 0 nrf5/{sdk => bluetooth}/ble_drv.h | 0 nrf5/{sdk => bluetooth}/ble_uart.c | 0 nrf5/{sdk => bluetooth}/ble_uart.h | 0 nrf5/{sdk => bluetooth}/bluetooth_common.mk | 0 nrf5/{sdk => bluetooth}/bluetooth_conf.h | 0 nrf5/{sdk => bluetooth}/help_sd.h | 0 nrf5/{sdk => bluetooth}/iot_0.9.0/build.mk | 0 nrf5/{sdk => bluetooth}/iot_0.9.0/modnwble6lowpan.c | 0 nrf5/{sdk => bluetooth}/iot_0.9.0/sdk.mk | 0 nrf5/{sdk => bluetooth}/iot_0.9.0/sdk_config.h | 0 nrf5/{sdk => bluetooth}/iot_0.9.0/sdkhelp.c | 0 nrf5/{sdk => bluetooth}/iot_0.9.0/sdkhelp.h | 0 nrf5/{sdk => bluetooth}/modble.c | 0 nrf5/{sdk => bluetooth}/ringbuffer.h | 0 15 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/{sdk => bluetooth}/ble_drv.c (100%) rename nrf5/{sdk => bluetooth}/ble_drv.h (100%) rename nrf5/{sdk => bluetooth}/ble_uart.c (100%) rename nrf5/{sdk => bluetooth}/ble_uart.h (100%) rename nrf5/{sdk => bluetooth}/bluetooth_common.mk (100%) rename nrf5/{sdk => bluetooth}/bluetooth_conf.h (100%) rename nrf5/{sdk => bluetooth}/help_sd.h (100%) rename nrf5/{sdk => bluetooth}/iot_0.9.0/build.mk (100%) rename nrf5/{sdk => bluetooth}/iot_0.9.0/modnwble6lowpan.c (100%) rename nrf5/{sdk => bluetooth}/iot_0.9.0/sdk.mk (100%) rename nrf5/{sdk => bluetooth}/iot_0.9.0/sdk_config.h (100%) rename nrf5/{sdk => bluetooth}/iot_0.9.0/sdkhelp.c (100%) rename nrf5/{sdk => bluetooth}/iot_0.9.0/sdkhelp.h (100%) rename nrf5/{sdk => bluetooth}/modble.c (100%) rename nrf5/{sdk => bluetooth}/ringbuffer.h (100%) diff --git a/nrf5/sdk/ble_drv.c b/nrf5/bluetooth/ble_drv.c similarity index 100% rename from nrf5/sdk/ble_drv.c rename to nrf5/bluetooth/ble_drv.c diff --git a/nrf5/sdk/ble_drv.h b/nrf5/bluetooth/ble_drv.h similarity index 100% rename from nrf5/sdk/ble_drv.h rename to nrf5/bluetooth/ble_drv.h diff --git a/nrf5/sdk/ble_uart.c b/nrf5/bluetooth/ble_uart.c similarity index 100% rename from nrf5/sdk/ble_uart.c rename to nrf5/bluetooth/ble_uart.c diff --git a/nrf5/sdk/ble_uart.h b/nrf5/bluetooth/ble_uart.h similarity index 100% rename from nrf5/sdk/ble_uart.h rename to nrf5/bluetooth/ble_uart.h diff --git a/nrf5/sdk/bluetooth_common.mk b/nrf5/bluetooth/bluetooth_common.mk similarity index 100% rename from nrf5/sdk/bluetooth_common.mk rename to nrf5/bluetooth/bluetooth_common.mk diff --git a/nrf5/sdk/bluetooth_conf.h b/nrf5/bluetooth/bluetooth_conf.h similarity index 100% rename from nrf5/sdk/bluetooth_conf.h rename to nrf5/bluetooth/bluetooth_conf.h diff --git a/nrf5/sdk/help_sd.h b/nrf5/bluetooth/help_sd.h similarity index 100% rename from nrf5/sdk/help_sd.h rename to nrf5/bluetooth/help_sd.h diff --git a/nrf5/sdk/iot_0.9.0/build.mk b/nrf5/bluetooth/iot_0.9.0/build.mk similarity index 100% rename from nrf5/sdk/iot_0.9.0/build.mk rename to nrf5/bluetooth/iot_0.9.0/build.mk diff --git a/nrf5/sdk/iot_0.9.0/modnwble6lowpan.c b/nrf5/bluetooth/iot_0.9.0/modnwble6lowpan.c similarity index 100% rename from nrf5/sdk/iot_0.9.0/modnwble6lowpan.c rename to nrf5/bluetooth/iot_0.9.0/modnwble6lowpan.c diff --git a/nrf5/sdk/iot_0.9.0/sdk.mk b/nrf5/bluetooth/iot_0.9.0/sdk.mk similarity index 100% rename from nrf5/sdk/iot_0.9.0/sdk.mk rename to nrf5/bluetooth/iot_0.9.0/sdk.mk diff --git a/nrf5/sdk/iot_0.9.0/sdk_config.h b/nrf5/bluetooth/iot_0.9.0/sdk_config.h similarity index 100% rename from nrf5/sdk/iot_0.9.0/sdk_config.h rename to nrf5/bluetooth/iot_0.9.0/sdk_config.h diff --git a/nrf5/sdk/iot_0.9.0/sdkhelp.c b/nrf5/bluetooth/iot_0.9.0/sdkhelp.c similarity index 100% rename from nrf5/sdk/iot_0.9.0/sdkhelp.c rename to nrf5/bluetooth/iot_0.9.0/sdkhelp.c diff --git a/nrf5/sdk/iot_0.9.0/sdkhelp.h b/nrf5/bluetooth/iot_0.9.0/sdkhelp.h similarity index 100% rename from nrf5/sdk/iot_0.9.0/sdkhelp.h rename to nrf5/bluetooth/iot_0.9.0/sdkhelp.h diff --git a/nrf5/sdk/modble.c b/nrf5/bluetooth/modble.c similarity index 100% rename from nrf5/sdk/modble.c rename to nrf5/bluetooth/modble.c diff --git a/nrf5/sdk/ringbuffer.h b/nrf5/bluetooth/ringbuffer.h similarity index 100% rename from nrf5/sdk/ringbuffer.h rename to nrf5/bluetooth/ringbuffer.h From 56d106507a37747780dce3706d4a2e7d8e56e9be Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 17:58:31 +0100 Subject: [PATCH 455/809] nrf5/bluetooth: Updating old references to 'sdk' to use the new folder name 'bluetooth' in makefiles. --- nrf5/Makefile | 2 +- nrf5/bluetooth/bluetooth_common.mk | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index cf71189da2..4c8387cc94 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -31,7 +31,7 @@ else include ../py/mkenv.mk include boards/$(BOARD)/mpconfigboard_$(SD_LOWER).mk - include sdk/bluetooth_common.mk + include bluetooth/bluetooth_common.mk endif # qstr definitions (must come before including py.mk) diff --git a/nrf5/bluetooth/bluetooth_common.mk b/nrf5/bluetooth/bluetooth_common.mk index f85bc5b47b..74a367d8e8 100644 --- a/nrf5/bluetooth/bluetooth_common.mk +++ b/nrf5/bluetooth/bluetooth_common.mk @@ -17,16 +17,16 @@ else ifeq ($(SD), s132) CFLAGS += -DBLUETOOTH_SD=132 SOFTDEV_HEX_NAME = s132_nrf52_3.0.0_softdevice.hex #else ifeq ($(SD), s1xx) -# include sdk/iot_0.9.0/sdk.mk +# include bluetooth/iot_0.9.0/sdk.mk else $(error Incorrect softdevice set flag) endif SOFTDEV_HEX = $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/$(SD)/hex/$(SOFTDEV_HEX_NAME))) -INC += -I./sdk +INC += -I./bluetooth SRC_C += \ - sdk/modble.c \ - sdk/ble_drv.c \ - sdk/ble_uart.c + bluetooth/modble.c \ + bluetooth/ble_drv.c \ + bluetooth/ble_uart.c From ab0d9756f15061ee48c9bfe6852687edb78c37b6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 18:05:51 +0100 Subject: [PATCH 456/809] nrf5/bluetooth: Updating header guard in bluetooth_conf.h to reflect new filename. --- nrf5/bluetooth/bluetooth_conf.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/bluetooth/bluetooth_conf.h b/nrf5/bluetooth/bluetooth_conf.h index beac291931..2e34c35106 100644 --- a/nrf5/bluetooth/bluetooth_conf.h +++ b/nrf5/bluetooth/bluetooth_conf.h @@ -1,5 +1,5 @@ -#ifndef NRF_SDK_CONF_H__ -#define NRF_SDK_CONF_H__ +#ifndef BLUETOOTH_CONF_H__ +#define BLUETOOTH_CONF_H__ // SD specific configurations. From 4a631a0d470498e1b8fde782cef9a637c5277b97 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 19:13:59 +0100 Subject: [PATCH 457/809] nrf5/boards: Renaming linker script for all nrf51 and nrf52 into more logical names. Updating all boards with new names. --- nrf5/boards/microbit/mpconfigboard.mk | 2 +- nrf5/boards/microbit/mpconfigboard_s110.mk | 3 ++- nrf5/boards/{nrf51822_aa.ld => nrf51x22_256k_16k.ld} | 0 .../boards/{nrf51822_aa_s110.ld => nrf51x22_256k_16k_s110.ld} | 0 nrf5/boards/{nrf51822_ac.ld => nrf51x22_256k_32k.ld} | 0 .../boards/{nrf51822_ac_s110.ld => nrf51x22_256k_32k_s110.ld} | 0 .../boards/{nrf51822_ac_s120.ld => nrf51x22_256k_32k_s120.ld} | 0 .../boards/{nrf51822_ac_s130.ld => nrf51x22_256k_32k_s130.ld} | 0 nrf5/boards/{nrf52832_aa.ld => nrf52832_512k_64k.ld} | 0 .../boards/{nrf52832_aa_s132.ld => nrf52832_512k_64k_s132.ld} | 0 .../boards/{nrf52832_aa_s1xx.ld => nrf52832_512k_64k_s1xx.ld} | 0 nrf5/boards/{nrf52840_aa.ld => nrf52840_1M_256k.ld} | 0 nrf5/boards/pca10000/mpconfigboard.mk | 3 +-- nrf5/boards/pca10000/mpconfigboard_s110.mk | 3 ++- nrf5/boards/pca10001/mpconfigboard.mk | 2 +- nrf5/boards/pca10001/mpconfigboard_s110.mk | 3 ++- nrf5/boards/pca10028/mpconfigboard.mk | 2 +- nrf5/boards/pca10028/mpconfigboard_s110.mk | 3 +-- nrf5/boards/pca10028/mpconfigboard_s120.mk | 2 +- nrf5/boards/pca10028/mpconfigboard_s130.mk | 3 +-- nrf5/boards/pca10031/mpconfigboard.mk | 2 +- nrf5/boards/pca10031/mpconfigboard_s110.mk | 4 ++-- nrf5/boards/pca10031/mpconfigboard_s120.mk | 4 ++-- nrf5/boards/pca10031/mpconfigboard_s130.mk | 4 ++-- nrf5/boards/pca10040/mpconfigboard.mk | 2 +- nrf5/boards/pca10040/mpconfigboard_s132.mk | 2 +- nrf5/boards/pca10040/mpconfigboard_s1xx.mk | 2 +- nrf5/boards/pca10056/mpconfigboard.mk | 2 +- 28 files changed, 24 insertions(+), 24 deletions(-) rename nrf5/boards/{nrf51822_aa.ld => nrf51x22_256k_16k.ld} (100%) rename nrf5/boards/{nrf51822_aa_s110.ld => nrf51x22_256k_16k_s110.ld} (100%) rename nrf5/boards/{nrf51822_ac.ld => nrf51x22_256k_32k.ld} (100%) rename nrf5/boards/{nrf51822_ac_s110.ld => nrf51x22_256k_32k_s110.ld} (100%) rename nrf5/boards/{nrf51822_ac_s120.ld => nrf51x22_256k_32k_s120.ld} (100%) rename nrf5/boards/{nrf51822_ac_s130.ld => nrf51x22_256k_32k_s130.ld} (100%) rename nrf5/boards/{nrf52832_aa.ld => nrf52832_512k_64k.ld} (100%) rename nrf5/boards/{nrf52832_aa_s132.ld => nrf52832_512k_64k_s132.ld} (100%) rename nrf5/boards/{nrf52832_aa_s1xx.ld => nrf52832_512k_64k_s1xx.ld} (100%) rename nrf5/boards/{nrf52840_aa.ld => nrf52840_1M_256k.ld} (100%) diff --git a/nrf5/boards/microbit/mpconfigboard.mk b/nrf5/boards/microbit/mpconfigboard.mk index f959edab50..dd63e22e5d 100644 --- a/nrf5/boards/microbit/mpconfigboard.mk +++ b/nrf5/boards/microbit/mpconfigboard.mk @@ -1,5 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld +LD_FILE = boards/nrf51x22_256k_16k.ld FLASHER = pyocd diff --git a/nrf5/boards/microbit/mpconfigboard_s110.mk b/nrf5/boards/microbit/mpconfigboard_s110.mk index fbe641cf86..20b6ca594d 100644 --- a/nrf5/boards/microbit/mpconfigboard_s110.mk +++ b/nrf5/boards/microbit/mpconfigboard_s110.mk @@ -1,6 +1,7 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51822_aa_s110.ld +LD_FILE = boards/nrf51x22_256k_16k_s110.ld FLASHER = pyocd + CFLAGS += -DBLUETOOTH_LFCLK_RC diff --git a/nrf5/boards/nrf51822_aa.ld b/nrf5/boards/nrf51x22_256k_16k.ld similarity index 100% rename from nrf5/boards/nrf51822_aa.ld rename to nrf5/boards/nrf51x22_256k_16k.ld diff --git a/nrf5/boards/nrf51822_aa_s110.ld b/nrf5/boards/nrf51x22_256k_16k_s110.ld similarity index 100% rename from nrf5/boards/nrf51822_aa_s110.ld rename to nrf5/boards/nrf51x22_256k_16k_s110.ld diff --git a/nrf5/boards/nrf51822_ac.ld b/nrf5/boards/nrf51x22_256k_32k.ld similarity index 100% rename from nrf5/boards/nrf51822_ac.ld rename to nrf5/boards/nrf51x22_256k_32k.ld diff --git a/nrf5/boards/nrf51822_ac_s110.ld b/nrf5/boards/nrf51x22_256k_32k_s110.ld similarity index 100% rename from nrf5/boards/nrf51822_ac_s110.ld rename to nrf5/boards/nrf51x22_256k_32k_s110.ld diff --git a/nrf5/boards/nrf51822_ac_s120.ld b/nrf5/boards/nrf51x22_256k_32k_s120.ld similarity index 100% rename from nrf5/boards/nrf51822_ac_s120.ld rename to nrf5/boards/nrf51x22_256k_32k_s120.ld diff --git a/nrf5/boards/nrf51822_ac_s130.ld b/nrf5/boards/nrf51x22_256k_32k_s130.ld similarity index 100% rename from nrf5/boards/nrf51822_ac_s130.ld rename to nrf5/boards/nrf51x22_256k_32k_s130.ld diff --git a/nrf5/boards/nrf52832_aa.ld b/nrf5/boards/nrf52832_512k_64k.ld similarity index 100% rename from nrf5/boards/nrf52832_aa.ld rename to nrf5/boards/nrf52832_512k_64k.ld diff --git a/nrf5/boards/nrf52832_aa_s132.ld b/nrf5/boards/nrf52832_512k_64k_s132.ld similarity index 100% rename from nrf5/boards/nrf52832_aa_s132.ld rename to nrf5/boards/nrf52832_512k_64k_s132.ld diff --git a/nrf5/boards/nrf52832_aa_s1xx.ld b/nrf5/boards/nrf52832_512k_64k_s1xx.ld similarity index 100% rename from nrf5/boards/nrf52832_aa_s1xx.ld rename to nrf5/boards/nrf52832_512k_64k_s1xx.ld diff --git a/nrf5/boards/nrf52840_aa.ld b/nrf5/boards/nrf52840_1M_256k.ld similarity index 100% rename from nrf5/boards/nrf52840_aa.ld rename to nrf5/boards/nrf52840_1M_256k.ld diff --git a/nrf5/boards/pca10000/mpconfigboard.mk b/nrf5/boards/pca10000/mpconfigboard.mk index 523653ede0..12087d6828 100644 --- a/nrf5/boards/pca10000/mpconfigboard.mk +++ b/nrf5/boards/pca10000/mpconfigboard.mk @@ -1,5 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld - +LD_FILE = boards/nrf51x22_256k_16k.ld diff --git a/nrf5/boards/pca10000/mpconfigboard_s110.mk b/nrf5/boards/pca10000/mpconfigboard_s110.mk index 5a3fa8e1c3..d96cab63b9 100644 --- a/nrf5/boards/pca10000/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10000/mpconfigboard_s110.mk @@ -1,3 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_aa_s110.ld +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/nrf51x22_256k_16k_s110.ld diff --git a/nrf5/boards/pca10001/mpconfigboard.mk b/nrf5/boards/pca10001/mpconfigboard.mk index 269fdc95af..12087d6828 100644 --- a/nrf5/boards/pca10001/mpconfigboard.mk +++ b/nrf5/boards/pca10001/mpconfigboard.mk @@ -1,4 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld +LD_FILE = boards/nrf51x22_256k_16k.ld diff --git a/nrf5/boards/pca10001/mpconfigboard_s110.mk b/nrf5/boards/pca10001/mpconfigboard_s110.mk index 5a3fa8e1c3..d96cab63b9 100644 --- a/nrf5/boards/pca10001/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10001/mpconfigboard_s110.mk @@ -1,3 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_aa_s110.ld +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/nrf51x22_256k_16k_s110.ld diff --git a/nrf5/boards/pca10028/mpconfigboard.mk b/nrf5/boards/pca10028/mpconfigboard.mk index 01b6bcf7e1..29e76d94a9 100644 --- a/nrf5/boards/pca10028/mpconfigboard.mk +++ b/nrf5/boards/pca10028/mpconfigboard.mk @@ -1,4 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/$(MCU_SUB_VARIANT)_ac.ld +LD_FILE = boards/nrf51x22_256k_32k.ld diff --git a/nrf5/boards/pca10028/mpconfigboard_s110.mk b/nrf5/boards/pca10028/mpconfigboard_s110.mk index ea7b9c3e9c..a0f6a39f34 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s110.mk @@ -1,5 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51822_ac_s110.ld - +LD_FILE = boards/nrf51x22_256k_32k_s110.ld diff --git a/nrf5/boards/pca10028/mpconfigboard_s120.mk b/nrf5/boards/pca10028/mpconfigboard_s120.mk index ad896186f0..10930317a1 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s120.mk @@ -1,4 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51822_ac_s120.ld +LD_FILE = boards/nrf51x22_256k_32k_s120.ld diff --git a/nrf5/boards/pca10028/mpconfigboard_s130.mk b/nrf5/boards/pca10028/mpconfigboard_s130.mk index 5e6e49268b..77b8add56d 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s130.mk @@ -1,5 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51822_ac_s130.ld - +LD_FILE = boards/nrf51x22_256k_32k_s130.ld diff --git a/nrf5/boards/pca10031/mpconfigboard.mk b/nrf5/boards/pca10031/mpconfigboard.mk index 01b6bcf7e1..29e76d94a9 100644 --- a/nrf5/boards/pca10031/mpconfigboard.mk +++ b/nrf5/boards/pca10031/mpconfigboard.mk @@ -1,4 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/$(MCU_SUB_VARIANT)_ac.ld +LD_FILE = boards/nrf51x22_256k_32k.ld diff --git a/nrf5/boards/pca10031/mpconfigboard_s110.mk b/nrf5/boards/pca10031/mpconfigboard_s110.mk index 54766bd429..a0f6a39f34 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s110.mk @@ -1,4 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_ac_s110.ld - +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/nrf51x22_256k_32k_s110.ld diff --git a/nrf5/boards/pca10031/mpconfigboard_s120.mk b/nrf5/boards/pca10031/mpconfigboard_s120.mk index dc1de98188..8422010a49 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s120.mk @@ -1,4 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_ac_s120.ld - +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/nrf51x22_256k_32k_s120.ld \ No newline at end of file diff --git a/nrf5/boards/pca10031/mpconfigboard_s130.mk b/nrf5/boards/pca10031/mpconfigboard_s130.mk index 3f55086b49..77b8add56d 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s130.mk @@ -1,4 +1,4 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 -LD_FILE = boards/nrf51822_ac_s130.ld - +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/nrf51x22_256k_32k_s130.ld diff --git a/nrf5/boards/pca10040/mpconfigboard.mk b/nrf5/boards/pca10040/mpconfigboard.mk index 62fce4c795..83dbb5ab42 100644 --- a/nrf5/boards/pca10040/mpconfigboard.mk +++ b/nrf5/boards/pca10040/mpconfigboard.mk @@ -1,6 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52832 -LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld +LD_FILE = boards/nrf52832_512k_64k.ld NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf5/boards/pca10040/mpconfigboard_s132.mk b/nrf5/boards/pca10040/mpconfigboard_s132.mk index c0bdd5b3ca..59e03bdb68 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s132.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s132.mk @@ -1,6 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52832 -LD_FILE = boards/nrf52832_aa_s132.ld +LD_FILE = boards/nrf52832_512k_64k_s132.ld NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk index 5bfeca122c..1467d01f2c 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk @@ -1,6 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52832 -LD_FILE = boards/nrf52832_aa_s1xx.ld +LD_FILE = boards/nrf52832_512k_64k_s1xx.ld NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf5/boards/pca10056/mpconfigboard.mk b/nrf5/boards/pca10056/mpconfigboard.mk index 15a88ed091..76661243a6 100644 --- a/nrf5/boards/pca10056/mpconfigboard.mk +++ b/nrf5/boards/pca10056/mpconfigboard.mk @@ -1,6 +1,6 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52840 -LD_FILE = boards/$(MCU_SUB_VARIANT)_aa.ld +LD_FILE = boards/nrf52840_1M_256k.ld NRF_DEFINES += -DNRF52840_XXAA From 2c61b7f596c570ffd8e79229a09422459f5706bb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 21:42:36 +0100 Subject: [PATCH 458/809] nrf5/hal: Adding untested implementation of twi read. Lacking sensors to test with :) --- nrf5/hal/hal_twi.c | 31 ++++++++++++++++++++++++++++++- nrf5/hal/hal_twi.h | 3 ++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/nrf5/hal/hal_twi.c b/nrf5/hal/hal_twi.c index 9da0cd6d0a..551595111b 100644 --- a/nrf5/hal/hal_twi.c +++ b/nrf5/hal/hal_twi.c @@ -93,8 +93,37 @@ void hal_twi_master_tx(NRF_TWI_Type * p_instance, void hal_twi_master_rx(NRF_TWI_Type * p_instance, uint8_t addr, uint16_t transfer_size, - const uint8_t * rx_data) { + uint8_t * rx_data, + bool stop) { + uint16_t number_of_rxd_bytes = 0; + + p_instance->ADDRESS = addr; + + p_instance->EVENTS_RXDREADY = 0; + + p_instance->TASKS_STARTRX = 1; + + while (number_of_rxd_bytes < transfer_size) { + // wait for the transaction complete + while (p_instance->EVENTS_RXDREADY == 0) { + ; + } + + rx_data[number_of_rxd_bytes] = p_instance->RXD; + p_instance->EVENTS_RXDREADY = 0; + + number_of_rxd_bytes++; + } + + if (stop) { + p_instance->EVENTS_STOPPED = 0; + p_instance->TASKS_STOP = 1; + + while (p_instance->EVENTS_STOPPED == 0) { + ; + } + } } void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) { diff --git a/nrf5/hal/hal_twi.h b/nrf5/hal/hal_twi.h index 8332992ba0..d7a189e985 100644 --- a/nrf5/hal/hal_twi.h +++ b/nrf5/hal/hal_twi.h @@ -108,7 +108,8 @@ void hal_twi_master_tx(NRF_TWI_Type * p_instance, void hal_twi_master_rx(NRF_TWI_Type * p_instance, uint8_t addr, uint16_t transfer_size, - const uint8_t * rx_data); + uint8_t * rx_data, + bool stop); void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init); From ee5884bfe934721c22d7bc092c196d7b9ad11d06 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 4 Mar 2017 21:44:05 +0100 Subject: [PATCH 459/809] nrf5/modules: Updating readfrom function in machine i2c module to use the new hal function which has been implemented. --- nrf5/modules/machine/i2c.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/machine/i2c.c b/nrf5/modules/machine/i2c.c index 539fb5a748..75e7528551 100644 --- a/nrf5/modules/machine/i2c.c +++ b/nrf5/modules/machine/i2c.c @@ -131,7 +131,10 @@ mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, siz #include int machine_hard_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t *dest, size_t len, bool stop) { - printf("machine_hard_i2c_readfrom called\n"); + machine_hard_i2c_obj_t *self = (machine_hard_i2c_obj_t *)self_in; + + hal_twi_master_rx(self->i2c->instance, addr, len, dest, stop); + return 0; } From 048915309463a264d271e137300e81ae6550455e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Mar 2017 22:37:07 +0100 Subject: [PATCH 460/809] nrf5/hal: Renaming uart hal function to use hal_uart prefix. --- nrf5/hal/hal_uart.c | 14 +++++++------- nrf5/hal/hal_uart.h | 10 +++++----- nrf5/hal/hal_uarte.c | 20 ++++++++++---------- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/nrf5/hal/hal_uart.c b/nrf5/hal/hal_uart.c index c2fa9085a0..cda9ba60a1 100644 --- a/nrf5/hal/hal_uart.c +++ b/nrf5/hal/hal_uart.c @@ -60,7 +60,7 @@ uint32_t hal_uart_baudrate_lookup[] = { UART_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud. }; -void nrf_uart_char_write(uint8_t ch) { +void hal_uart_char_write(uint8_t ch) { UART_BASE->TXD = (uint8_t)ch; while (UART_BASE->EVENTS_TXDRDY != 1) { // Blocking wait. @@ -70,7 +70,7 @@ void nrf_uart_char_write(uint8_t ch) { UART_BASE->EVENTS_TXDRDY = 0; } -uint8_t nrf_uart_char_read(void) { +uint8_t hal_uart_char_read(void) { while (UART_BASE->EVENTS_RXDRDY != 1) { // Wait for RXD data. } @@ -79,27 +79,27 @@ uint8_t nrf_uart_char_read(void) { return (uint8_t)UART_BASE->RXD; } -void nrf_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { +void hal_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { int i = 0; uint8_t ch = p_buffer[i++]; while (i < num_of_bytes) { - nrf_uart_char_write(ch); + hal_uart_char_write(ch); ch = p_buffer[i++]; } cb(); } -void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { +void hal_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { int i = 0; while (i < num_of_bytes) { - uint8_t ch = nrf_uart_char_read(); + uint8_t ch = hal_uart_char_read(); p_buffer[i] = ch; i++; } cb(); } -void nrf_uart_init(hal_uart_init_t const * p_uart_init) { +void hal_uart_init(hal_uart_init_t const * p_uart_init) { hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); diff --git a/nrf5/hal/hal_uart.h b/nrf5/hal/hal_uart.h index 48c39ca1b2..bc7a945d27 100644 --- a/nrf5/hal/hal_uart.h +++ b/nrf5/hal/hal_uart.h @@ -122,14 +122,14 @@ typedef struct { typedef void (*uart_complete_cb)(void); -void nrf_uart_init(hal_uart_init_t const * p_uart_init); +void hal_uart_init(hal_uart_init_t const * p_uart_init); -void nrf_uart_char_write(uint8_t ch); +void hal_uart_char_write(uint8_t ch); -uint8_t nrf_uart_char_read(void); +uint8_t hal_uart_char_read(void); -void nrf_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb); +void hal_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb); -void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb); +void hal_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb); #endif // UART_H__ diff --git a/nrf5/hal/hal_uarte.c b/nrf5/hal/hal_uarte.c index cde143502c..bb421bec20 100644 --- a/nrf5/hal/hal_uarte.c +++ b/nrf5/hal/hal_uarte.c @@ -68,21 +68,21 @@ static const uint32_t hal_uart_baudrate_lookup[] = { UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud. }; -__STATIC_INLINE void nrf_uart_irq_clear(void) { +__STATIC_INLINE void hal_uart_irq_clear(void) { NVIC_ClearPendingIRQ(UART_IRQ_NUM); } -__STATIC_INLINE void nrf_uart_irq_enable(uint8_t priority) { +__STATIC_INLINE void hal_uart_irq_enable(uint8_t priority) { NVIC_SetPriority(UART_IRQ_NUM, priority); - nrf_uart_irq_clear(); + hal_uart_irq_clear(); NVIC_EnableIRQ(UART_IRQ_NUM); } void nrf_sendchar(int ch) { - nrf_uart_char_write(ch); + hal_uart_char_write(ch); } -void nrf_uart_init(hal_uart_init_t const * p_uart_init) { +void hal_uart_init(hal_uart_init_t const * p_uart_init) { hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_pin_set(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin); hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); @@ -121,7 +121,7 @@ void nrf_uart_init(hal_uart_init_t const * p_uart_init) { #endif } - nrf_uart_irq_enable(p_uart_init->irq_priority); + hal_uart_irq_enable(p_uart_init->irq_priority); UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); @@ -132,7 +132,7 @@ void nrf_uart_init(hal_uart_init_t const * p_uart_init) { UARTE_BASE->EVENTS_ENDRX = 0; } -void nrf_uart_char_write(uint8_t ch) { +void hal_uart_char_write(uint8_t ch) { static volatile uint8_t m_tx_buf[TX_BUF_SIZE]; (void)m_tx_buf; @@ -153,7 +153,7 @@ void nrf_uart_char_write(uint8_t ch) { UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); } -uint8_t nrf_uart_char_read(void) { +uint8_t hal_uart_char_read(void) { static volatile uint8_t m_rx_buf[RX_BUF_SIZE]; UARTE_BASE->INTENCLR = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); @@ -173,7 +173,7 @@ uint8_t nrf_uart_char_read(void) { return (uint8_t)m_rx_buf[0]; } -void nrf_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { +void hal_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { dma_write_cb = cb; UARTE_BASE->TXD.PTR = (uint32_t)p_buffer; @@ -189,7 +189,7 @@ void nrf_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_compl } -void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { +void hal_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { dma_read_cb = cb; UARTE_BASE->RXD.PTR = (uint32_t)(p_buffer); From 9ddd62e73e16cecf9a1a3627603bfd7400d449e1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 5 Mar 2017 22:37:52 +0100 Subject: [PATCH 461/809] nrf5/modules: Updating machine uart module to use new hal uart interface name. --- nrf5/modules/machine/uart.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/machine/uart.c b/nrf5/modules/machine/uart.c index 6001ba44bf..37a2c5af9c 100644 --- a/nrf5/modules/machine/uart.c +++ b/nrf5/modules/machine/uart.c @@ -111,11 +111,11 @@ STATIC bool uart_rx_wait(pyb_uart_obj_t *self, uint32_t timeout) { } int uart_rx_char(pyb_uart_obj_t *self) { - return (int)nrf_uart_char_read(); + return (int)hal_uart_char_read(); } STATIC void uart_tx_char(pyb_uart_obj_t * self, int c) { - nrf_uart_char_write((char)c); + hal_uart_char_write((char)c); } @@ -225,7 +225,7 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, con uart_init.cts_pin = &MICROPY_HW_UART1_CTS; #endif - nrf_uart_init(&uart_init); + hal_uart_init(&uart_init); return mp_const_none; } From 852aaba58bf2c67080663c697e47d18f59bd664a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 00:50:00 +0100 Subject: [PATCH 462/809] nrf5/hal: Adding hal_irq.h which defines a set of static inline functions to do nvic irq operations. --- nrf5/hal/hal_irq.h | 51 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 nrf5/hal/hal_irq.h diff --git a/nrf5/hal/hal_irq.h b/nrf5/hal/hal_irq.h new file mode 100644 index 0000000000..f834e33598 --- /dev/null +++ b/nrf5/hal/hal_irq.h @@ -0,0 +1,51 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_IRQ_H__ +#define HAL_IRQ_H__ + +#include + +#include "nrf.h" + +static inline void hal_irq_clear(uint32_t irq_num) { + NVIC_ClearPendingIRQ(irq_num); +} + +static inline void hal_irq_enable(uint32_t irq_num) { + hal_irq_clear(irq_num); + NVIC_EnableIRQ(irq_num); +} + +static inline void hal_irq_disable(uint32_t irq_num) { + NVIC_DisableIRQ(irq_num); +} + +static inline void hal_irq_priority(uint32_t irq_num, uint8_t priority) { + NVIC_SetPriority(irq_num, priority); +} + +#endif // HAL_IRQ_H__ From ff7541599aff54aa80ac3e88a3e9374a1973de28 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 00:53:21 +0100 Subject: [PATCH 463/809] nrf5/hal: Updating hal RTC implementation. --- nrf5/hal/hal_rtc.c | 74 +++++++++++++++++++++++++++++++++++++++++++++- nrf5/hal/hal_rtc.h | 21 +++++++++---- 2 files changed, 89 insertions(+), 6 deletions(-) diff --git a/nrf5/hal/hal_rtc.c b/nrf5/hal/hal_rtc.c index 9f3bef48cd..519de3eac1 100644 --- a/nrf5/hal/hal_rtc.c +++ b/nrf5/hal/hal_rtc.c @@ -26,11 +26,83 @@ #include "mphalport.h" #include "hal_rtc.h" +#include "hal_irq.h" #ifdef HAL_RTC_MODULE_ENABLED -void hal_rtc_init(NRF_RTC_Type * p_instance, hal_rtc_init_t const * p_rtc_init) { +static hal_rtc_app_callback m_callback; + +void hal_rtc_callback_set(hal_rtc_app_callback callback) { + m_callback = callback; } +void hal_rtc_init(hal_rtc_conf_t const * p_rtc_conf) { + p_rtc_conf->p_instance->PRESCALER = (32768 / p_rtc_conf->frequency) - 1; // approx correct. + hal_irq_priority(p_rtc_conf->irq_num, p_rtc_conf->irq_priority); +} + +void hal_rtc_start(hal_rtc_conf_t const * p_rtc_conf, uint16_t period) { + p_rtc_conf->p_instance->CC[0] = period; + p_rtc_conf->p_instance->EVTENSET = RTC_EVTEN_COMPARE0_Msk; + p_rtc_conf->p_instance->INTENSET = RTC_INTENSET_COMPARE0_Msk; + + hal_irq_clear(p_rtc_conf->irq_num); + hal_irq_enable(p_rtc_conf->irq_num); + + p_rtc_conf->p_instance->TASKS_START = 1; +} + +void hal_rtc_stop(hal_rtc_conf_t const * p_rtc_conf) { + p_rtc_conf->p_instance->TASKS_STOP = 1; + + p_rtc_conf->p_instance->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; + p_rtc_conf->p_instance->INTENCLR = RTC_INTENSET_COMPARE0_Msk; + + hal_irq_disable(p_rtc_conf->irq_num); +} + +void RTC0_IRQHandler(void) +{ + // clear all events + NRF_RTC0->EVENTS_COMPARE[0] = 0; + NRF_RTC0->EVENTS_COMPARE[1] = 0; + NRF_RTC0->EVENTS_COMPARE[2] = 0; + NRF_RTC0->EVENTS_COMPARE[3] = 0; + NRF_RTC0->EVENTS_TICK = 0; + NRF_RTC0->EVENTS_OVRFLW = 0; + + m_callback(NRF_RTC0); +} + +void RTC1_IRQHandler(void) +{ + // clear all events + NRF_RTC1->EVENTS_COMPARE[0] = 0; + NRF_RTC1->EVENTS_COMPARE[1] = 0; + NRF_RTC1->EVENTS_COMPARE[2] = 0; + NRF_RTC1->EVENTS_COMPARE[3] = 0; + NRF_RTC1->EVENTS_TICK = 0; + NRF_RTC1->EVENTS_OVRFLW = 0; + + m_callback(NRF_RTC1); +} + +#if NRF52 + +void RTC2_IRQHandler(void) +{ + // clear all events + NRF_RTC2->EVENTS_COMPARE[0] = 0; + NRF_RTC2->EVENTS_COMPARE[1] = 0; + NRF_RTC2->EVENTS_COMPARE[2] = 0; + NRF_RTC2->EVENTS_COMPARE[3] = 0; + NRF_RTC2->EVENTS_TICK = 0; + NRF_RTC2->EVENTS_OVRFLW = 0; + + m_callback(NRF_RTC2); +} + +#endif // NRF52 + #endif // HAL_RTC_MODULE_ENABLED diff --git a/nrf5/hal/hal_rtc.h b/nrf5/hal/hal_rtc.h index 4c4e9d1194..16ef2f7ed2 100644 --- a/nrf5/hal/hal_rtc.h +++ b/nrf5/hal/hal_rtc.h @@ -49,22 +49,33 @@ #error "Device not supported." #endif +typedef void (*hal_rtc_app_callback)(NRF_RTC_Type * p_instance); + /** * @brief RTC Configuration Structure definition */ typedef struct { -} hal_rtc_init_t; + NRF_RTC_Type * p_instance; /* RTC registers base address */ + uint32_t irq_num; /* RTC IRQ num */ + uint32_t irq_priority; /* RTC IRQ priority */ + uint16_t frequency; /* RTC frequency in Hz */ +} hal_rtc_conf_t; /** * @brief RTC handle Structure definition */ typedef struct __RTC_HandleTypeDef { - NRF_RTC_Type *instance; /* RTC registers base address */ - hal_rtc_init_t init; /* RTC initialization parameters */ - uint8_t id; /* RTC instance id */ + uint8_t id; /* RTC instance id */ + hal_rtc_conf_t config; /* RTC config */ } RTC_HandleTypeDef; -void hal_rtc_init(NRF_RTC_Type * p_instance, hal_rtc_init_t const * p_rtc_init); +void hal_rtc_callback_set(hal_rtc_app_callback callback); + +void hal_rtc_init(hal_rtc_conf_t const * p_rtc_config); + +void hal_rtc_start(hal_rtc_conf_t const * p_rtc_conf, uint16_t period); + +void hal_rtc_stop(hal_rtc_conf_t const * p_rtc_conf); #endif // HAL_RTC_H__ From 7144696e1747498db15acf60fe0a7b9143de2202 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 00:56:18 +0100 Subject: [PATCH 464/809] nrf5/modules: Updating rtc module. Not working yet. Updated to align with new hal_rtc interface. Added start and stop methods. Allowing callback function set from init. This should be moved to start function, not set in main. --- nrf5/modules/machine/rtc.c | 105 +++++++++++++++++++++++++++++++------ 1 file changed, 89 insertions(+), 16 deletions(-) diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index 9a4913d88d..172cd2ac98 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -38,22 +38,44 @@ typedef struct _machine_rtc_obj_t { mp_obj_base_t base; RTC_HandleTypeDef *rtc; + mp_obj_t callback; } machine_rtc_obj_t; -RTC_HandleTypeDef RTCHandle0 = {.instance = NULL, .id = 0}; -RTC_HandleTypeDef RTCHandle1 = {.instance = NULL, .id = 1}; +RTC_HandleTypeDef RTCHandle0 = {.config.p_instance = NULL, .id = 0}; +RTC_HandleTypeDef RTCHandle1 = {.config.p_instance = NULL, .id = 1}; STATIC const machine_rtc_obj_t machine_rtc_obj[] = { {{&machine_rtc_type}, &RTCHandle0}, {{&machine_rtc_type}, &RTCHandle1}, }; +STATIC void hal_interrupt_handle(NRF_RTC_Type * p_instance) { + if (p_instance == RTC0) { + const machine_rtc_obj_t *self = &machine_rtc_obj[0]; + mp_call_function_0(self->callback); + } else if (p_instance == RTC1) { + const machine_rtc_obj_t *self = &machine_rtc_obj[1]; + mp_call_function_0(self->callback); + } +#if NRF52 + else if (p_instance == RTC2) { + const machine_rtc_obj_t *self = &machine_rtc_obj[2]; + mp_call_function_0(self->callback); + } +#endif +} + void rtc_init0(void) { + + hal_rtc_callback_set(hal_interrupt_handle); + // reset the RTC handles memset(&RTCHandle0, 0, sizeof(RTC_HandleTypeDef)); - RTCHandle0.instance = RTC0; + RTCHandle0.config.p_instance = RTC0; + RTCHandle0.config.irq_num = RTC0_IRQ_NUM; memset(&RTCHandle1, 0, sizeof(RTC_HandleTypeDef)); - RTCHandle1.instance = RTC1; + RTCHandle1.config.p_instance = RTC1; + RTCHandle1.config.irq_num = RTC1_IRQ_NUM; } STATIC int rtc_find(mp_obj_t id) { @@ -75,43 +97,94 @@ STATIC void rtc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) /******************************************************************************/ /* MicroPython bindings for machine API */ -// for make_new -enum { - ARG_NEW_id, -}; - STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { - { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_frequency, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_callback, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, }; // parse args mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { + if (args[0].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { // index -1 does not exist return mp_const_none; // TODO: raise exception } // get static peripheral object - int rtc_id = rtc_find(args[ARG_NEW_id].u_obj); - const machine_rtc_obj_t *self = &machine_rtc_obj[rtc_id]; + int rtc_id = rtc_find(args[0].u_obj); - hal_rtc_init(self->rtc->instance, &self->rtc->init); + // unconst machine object in order to set a callback. + machine_rtc_obj_t * self = (machine_rtc_obj_t *)&machine_rtc_obj[rtc_id]; + + mp_obj_t freq_obj = args[1].u_obj; + + if (freq_obj != mp_const_none && MP_OBJ_IS_INT(freq_obj)) { + self->rtc->config.frequency = mp_obj_get_int(freq_obj); + } else { + // raise exception + } + + if (args[2].u_obj != mp_const_none) { + self->callback = args[2].u_obj; + } + + // hardcode priority to 3, to make sure it is less than any bluetooth stack. + +#if (BLUETOOTH_SD == 100) + self->rtc->config.irq_priority = 3; +#else + self->rtc->config.irq_priority = 6; +#endif + + hal_rtc_init(&self->rtc->config); return MP_OBJ_FROM_PTR(self); } +/// \method start(period) +/// Start the RTC timer. Timeout occurs after number of periods +/// in the configured frequency has been reached. +/// +STATIC mp_obj_t machine_rtc_start(mp_obj_t self_in, mp_obj_t period_in) { + machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in); + mp_int_t period = mp_obj_get_int(period_in); + + hal_rtc_start(&self->rtc->config, period); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_rtc_start_obj, machine_rtc_start); + +/// \method stop() +/// Stop the RTC timer. +/// +STATIC mp_obj_t machine_rtc_stop(mp_obj_t self_in) { + machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in); + + hal_rtc_stop(&self->rtc->config); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_stop_obj, machine_rtc_stop); + + +STATIC const mp_map_elem_t machine_rtc_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_start), (mp_obj_t)(&machine_rtc_start_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)(&machine_rtc_stop_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(machine_rtc_locals_dict, machine_rtc_locals_dict_table); + const mp_obj_type_t machine_rtc_type = { { &mp_type_type }, .name = MP_QSTR_RTC, .print = rtc_print, .make_new = machine_rtc_make_new, -#if 0 .locals_dict = (mp_obj_t)&machine_rtc_locals_dict -#endif }; #endif // MICROPY_PY_MACHINE_RTC From 1ef7c732e86fff7960cc0d685680b7e327f7bac6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 00:56:58 +0100 Subject: [PATCH 465/809] nrf5/modules: Added RTC into the machine module globals dict. --- nrf5/modules/machine/modmachine.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 9fc28f95e5..4c1890d632 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -49,7 +49,9 @@ #if MICROPY_PY_MACHINE_TEMP #include "temp.h" #endif - +#if MICROPY_PY_MACHINE_RTC +#include "rtc.h" +#endif #define PYB_RESET_HARD (0) #define PYB_RESET_WDT (1) @@ -181,6 +183,9 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { #if MICROPY_PY_MACHINE_ADC { MP_OBJ_NEW_QSTR(MP_QSTR_ADC), (mp_obj_t)&machine_adc_type }, #endif +#if MICROPY_PY_MACHINE_RTC + { MP_OBJ_NEW_QSTR(MP_QSTR_RTC), (mp_obj_t)&machine_rtc_type }, +#endif #if MICROPY_PY_MACHINE_PWM { MP_OBJ_NEW_QSTR(MP_QSTR_PWM), (mp_obj_t)&machine_hard_pwm_type }, #endif From 49b1607bedb7fa473b2cd2ead93e62f8c0f74988 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 00:57:33 +0100 Subject: [PATCH 466/809] nrf5: Updating main.c to initialize the rtc module if enabled. --- nrf5/main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/main.c b/nrf5/main.c index 3e81372af8..e5b0f51705 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -48,6 +48,7 @@ #include "pin.h" #include "spi.h" #include "i2c.h" +#include "rtc.h" #if MICROPY_PY_MACHINE_PWM #include "pwm.h" #endif @@ -116,6 +117,10 @@ int main(int argc, char **argv) { pwm_init0(); #endif +#if MICROPY_PY_MACHINE_RTC + rtc_init0(); +#endif + #if MICROPY_PY_MACHINE_TIMER timer_init0(); #endif From 7000e0a2a0dc3ac2ee874a15654d1debd556355d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 01:13:19 +0100 Subject: [PATCH 467/809] nrf5/modules: Moving irq priority settings in RTC object to rtc_init0 when initializing the hardware instances. Also modifying comments a bit. Adding simple example in comment above make_new function on how the object is intended to work. --- nrf5/modules/machine/rtc.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index 172cd2ac98..7ccf599b83 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -73,9 +73,19 @@ void rtc_init0(void) { memset(&RTCHandle0, 0, sizeof(RTC_HandleTypeDef)); RTCHandle0.config.p_instance = RTC0; RTCHandle0.config.irq_num = RTC0_IRQ_NUM; +#if (BLUETOOTH_SD == 100) + RTCHandle0.config.irq_priority = 3; +#else + RTCHandle0.config.irq_priority = 6; +#endif memset(&RTCHandle1, 0, sizeof(RTC_HandleTypeDef)); RTCHandle1.config.p_instance = RTC1; RTCHandle1.config.irq_num = RTC1_IRQ_NUM; +#if (BLUETOOTH_SD == 100) + RTCHandle1.config.irq_priority = 3; +#else + RTCHandle1.config.irq_priority = 6; +#endif } STATIC int rtc_find(mp_obj_t id) { @@ -97,6 +107,14 @@ STATIC void rtc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) /******************************************************************************/ /* MicroPython bindings for machine API */ +/* +from machine import RTC +def cb(): + print("Callback") +r = RTC(0, 8, cb) +r.start(16) +*/ + STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, @@ -132,14 +150,6 @@ STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, s self->callback = args[2].u_obj; } - // hardcode priority to 3, to make sure it is less than any bluetooth stack. - -#if (BLUETOOTH_SD == 100) - self->rtc->config.irq_priority = 3; -#else - self->rtc->config.irq_priority = 6; -#endif - hal_rtc_init(&self->rtc->config); return MP_OBJ_FROM_PTR(self); From 87e16164882eb990498da604594d11f4eb3fdf27 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 20:06:47 +0100 Subject: [PATCH 468/809] nrf5/hal: Adding initialization of LFCLK if not already enabled in hal_rtc. --- nrf5/hal/hal_rtc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/nrf5/hal/hal_rtc.c b/nrf5/hal/hal_rtc.c index 519de3eac1..bf10dfc8dc 100644 --- a/nrf5/hal/hal_rtc.c +++ b/nrf5/hal/hal_rtc.c @@ -39,6 +39,13 @@ void hal_rtc_callback_set(hal_rtc_app_callback callback) { void hal_rtc_init(hal_rtc_conf_t const * p_rtc_conf) { p_rtc_conf->p_instance->PRESCALER = (32768 / p_rtc_conf->frequency) - 1; // approx correct. hal_irq_priority(p_rtc_conf->irq_num, p_rtc_conf->irq_priority); + + // start LFCLK if not already started + if (NRF_CLOCK->LFCLKSTAT == 0) { + NRF_CLOCK->TASKS_LFCLKSTART = 1; + while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0); + NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; + } } void hal_rtc_start(hal_rtc_conf_t const * p_rtc_conf, uint16_t period) { From f50a56dbb58f2089fc75ab3a4f5f83e1395bdc21 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 20:09:04 +0100 Subject: [PATCH 469/809] nrf5/modules: Updating rtc module with non-const machine object list in order to allow setting callback function in constructor. --- nrf5/modules/machine/rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index 7ccf599b83..de27d213f9 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -44,7 +44,7 @@ typedef struct _machine_rtc_obj_t { RTC_HandleTypeDef RTCHandle0 = {.config.p_instance = NULL, .id = 0}; RTC_HandleTypeDef RTCHandle1 = {.config.p_instance = NULL, .id = 1}; -STATIC const machine_rtc_obj_t machine_rtc_obj[] = { +STATIC machine_rtc_obj_t machine_rtc_obj[] = { {{&machine_rtc_type}, &RTCHandle0}, {{&machine_rtc_type}, &RTCHandle1}, }; From c301cca2a4e2b4efe2d47a52929de15b02beb598 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 20:51:59 +0100 Subject: [PATCH 470/809] nrf5/hal: hal_rtc update. Adding current counter value to period value before setting it in the compare register. --- nrf5/hal/hal_rtc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/nrf5/hal/hal_rtc.c b/nrf5/hal/hal_rtc.c index bf10dfc8dc..d539d78c48 100644 --- a/nrf5/hal/hal_rtc.c +++ b/nrf5/hal/hal_rtc.c @@ -49,7 +49,10 @@ void hal_rtc_init(hal_rtc_conf_t const * p_rtc_conf) { } void hal_rtc_start(hal_rtc_conf_t const * p_rtc_conf, uint16_t period) { - p_rtc_conf->p_instance->CC[0] = period; + uint32_t counter = p_rtc_conf->p_instance->COUNTER; + + p_rtc_conf->p_instance->CC[0] = counter + period; + p_rtc_conf->p_instance->EVTENSET = RTC_EVTEN_COMPARE0_Msk; p_rtc_conf->p_instance->INTENSET = RTC_INTENSET_COMPARE0_Msk; @@ -60,12 +63,12 @@ void hal_rtc_start(hal_rtc_conf_t const * p_rtc_conf, uint16_t period) { } void hal_rtc_stop(hal_rtc_conf_t const * p_rtc_conf) { - p_rtc_conf->p_instance->TASKS_STOP = 1; - p_rtc_conf->p_instance->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; p_rtc_conf->p_instance->INTENCLR = RTC_INTENSET_COMPARE0_Msk; hal_irq_disable(p_rtc_conf->irq_num); + + p_rtc_conf->p_instance->TASKS_STOP = 1; } void RTC0_IRQHandler(void) From 3debb43e833a13dd746986fc5471454b8c59214b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 21:33:29 +0100 Subject: [PATCH 471/809] nrf5/modules: Adding support for periodic RTC callback. --- nrf5/modules/machine/rtc.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index de27d213f9..c9d6204d77 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -39,6 +39,8 @@ typedef struct _machine_rtc_obj_t { mp_obj_base_t base; RTC_HandleTypeDef *rtc; mp_obj_t callback; + mp_int_t period; + mp_int_t type; } machine_rtc_obj_t; RTC_HandleTypeDef RTCHandle0 = {.config.p_instance = NULL, .id = 0}; @@ -53,6 +55,11 @@ STATIC void hal_interrupt_handle(NRF_RTC_Type * p_instance) { if (p_instance == RTC0) { const machine_rtc_obj_t *self = &machine_rtc_obj[0]; mp_call_function_0(self->callback); + + hal_rtc_stop(&self->rtc->config); + if (self->type == 1) { + hal_rtc_start(&self->rtc->config, self->period); + } } else if (p_instance == RTC1) { const machine_rtc_obj_t *self = &machine_rtc_obj[1]; mp_call_function_0(self->callback); @@ -111,7 +118,7 @@ STATIC void rtc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) from machine import RTC def cb(): print("Callback") -r = RTC(0, 8, cb) +r = RTC(0, 8, cb, type=RTC.PERIODIC) r.start(16) */ @@ -120,6 +127,7 @@ STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, s { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_frequency, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_callback, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_type, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, }; // parse args @@ -150,6 +158,8 @@ STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, s self->callback = args[2].u_obj; } + self->type = args[3].u_int; + hal_rtc_init(&self->rtc->config); return MP_OBJ_FROM_PTR(self); @@ -163,6 +173,8 @@ STATIC mp_obj_t machine_rtc_start(mp_obj_t self_in, mp_obj_t period_in) { machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in); mp_int_t period = mp_obj_get_int(period_in); + self->period = mp_obj_get_int(period_in); + hal_rtc_start(&self->rtc->config, period); return mp_const_none; @@ -185,6 +197,10 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_stop_obj, machine_rtc_stop); STATIC const mp_map_elem_t machine_rtc_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_start), (mp_obj_t)(&machine_rtc_start_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)(&machine_rtc_stop_obj) }, + + // constants + { MP_OBJ_NEW_QSTR(MP_QSTR_ONESHOT), MP_OBJ_NEW_SMALL_INT(0) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PERIODIC), MP_OBJ_NEW_SMALL_INT(1) }, }; STATIC MP_DEFINE_CONST_DICT(machine_rtc_locals_dict, machine_rtc_locals_dict_table); From 7c50cd26a2225158a7229af1c23e21999fe0dd9c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 22:59:43 +0100 Subject: [PATCH 472/809] nrf5/modules: Updating RTC kwarg from type to mode to set ONESHOT or PERIODIC mode. --- nrf5/modules/machine/rtc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index c9d6204d77..4a9c4977be 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -40,7 +40,7 @@ typedef struct _machine_rtc_obj_t { RTC_HandleTypeDef *rtc; mp_obj_t callback; mp_int_t period; - mp_int_t type; + mp_int_t mode; } machine_rtc_obj_t; RTC_HandleTypeDef RTCHandle0 = {.config.p_instance = NULL, .id = 0}; @@ -57,7 +57,7 @@ STATIC void hal_interrupt_handle(NRF_RTC_Type * p_instance) { mp_call_function_0(self->callback); hal_rtc_stop(&self->rtc->config); - if (self->type == 1) { + if (self->mode == 1) { hal_rtc_start(&self->rtc->config, self->period); } } else if (p_instance == RTC1) { @@ -118,7 +118,7 @@ STATIC void rtc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) from machine import RTC def cb(): print("Callback") -r = RTC(0, 8, cb, type=RTC.PERIODIC) +r = RTC(0, 8, cb, mode=RTC.PERIODIC) r.start(16) */ @@ -127,7 +127,7 @@ STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, s { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_frequency, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_callback, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, - { MP_QSTR_type, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, }; // parse args @@ -158,7 +158,7 @@ STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, s self->callback = args[2].u_obj; } - self->type = args[3].u_int; + self->mode = args[3].u_int; hal_rtc_init(&self->rtc->config); From 5acba015ef391f66c8699b7fb187cc8db0c8bd0a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 23:05:03 +0100 Subject: [PATCH 473/809] nrf5/modules/rtc: Adding support for stopping and restarting rtc (if periodic) for all the instances of RTC. --- nrf5/modules/machine/rtc.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index 4a9c4977be..d7559ae8c2 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -52,24 +52,27 @@ STATIC machine_rtc_obj_t machine_rtc_obj[] = { }; STATIC void hal_interrupt_handle(NRF_RTC_Type * p_instance) { + const machine_rtc_obj_t * self = NULL; if (p_instance == RTC0) { - const machine_rtc_obj_t *self = &machine_rtc_obj[0]; + self = &machine_rtc_obj[0]; mp_call_function_0(self->callback); - - hal_rtc_stop(&self->rtc->config); - if (self->mode == 1) { - hal_rtc_start(&self->rtc->config, self->period); - } } else if (p_instance == RTC1) { - const machine_rtc_obj_t *self = &machine_rtc_obj[1]; + self = &machine_rtc_obj[1]; mp_call_function_0(self->callback); } #if NRF52 else if (p_instance == RTC2) { - const machine_rtc_obj_t *self = &machine_rtc_obj[2]; + self = &machine_rtc_obj[2]; mp_call_function_0(self->callback); } #endif + + if (self != NULL) { + hal_rtc_stop(&self->rtc->config); + if (self->mode == 1) { + hal_rtc_start(&self->rtc->config, self->period); + } + } } void rtc_init0(void) { From 4afa41ac368f84c0578cafa858ddc781ab453446 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 23:30:56 +0100 Subject: [PATCH 474/809] nrf5/modules/machine: Adding enable_irq() and disable_irq() method to the machine module. No implementation yet for the case where bluetooth stack is used. --- nrf5/modules/machine/modmachine.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 4c1890d632..07f5b74533 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -162,11 +162,34 @@ STATIC mp_obj_t machine_reset_cause(void) { } STATIC MP_DEFINE_CONST_FUN_OBJ_0(machine_reset_cause_obj, machine_reset_cause); +STATIC mp_obj_t machine_enable_irq(void) { +#ifndef BLUETOOTH_SD + __enable_irq(); +#else + +#endif + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_enable_irq_obj, machine_enable_irq); + +// Resets the pyboard in a manner similar to pushing the external RESET button. +STATIC mp_obj_t machine_disable_irq(void) { +#ifndef BLUETOOTH_SD + __disable_irq(); +#else + +#endif + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_disable_irq_obj, machine_disable_irq); + STATIC const mp_map_elem_t machine_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_umachine) }, { MP_OBJ_NEW_QSTR(MP_QSTR_info), (mp_obj_t)&machine_info_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_reset), (mp_obj_t)&machine_reset_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_soft_reset), (mp_obj_t)&machine_soft_reset_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_enable_irq), (mp_obj_t)&machine_enable_irq_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_disable_irq), (mp_obj_t)&machine_disable_irq_obj }, #if MICROPY_HW_ENABLE_RNG { MP_OBJ_NEW_QSTR(MP_QSTR_rng), (mp_obj_t)&pyb_rng_get_obj }, #endif From 4e1b9aca79e50886788a5adca38fa2da9c01bb55 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 23:35:32 +0100 Subject: [PATCH 475/809] nrf5/modules/machine: Adding __WFE() on machine.sleep() --- nrf5/modules/machine/modmachine.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 07f5b74533..276b248081 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -148,6 +148,7 @@ STATIC mp_obj_t machine_soft_reset(void) { MP_DEFINE_CONST_FUN_OBJ_0(machine_soft_reset_obj, machine_soft_reset); STATIC mp_obj_t machine_sleep(void) { + __WFE(); return mp_const_none; } MP_DEFINE_CONST_FUN_OBJ_0(machine_sleep_obj, machine_sleep); From 2e1335b05166c65e049349a76e930a98683137a3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 6 Mar 2017 23:36:36 +0100 Subject: [PATCH 476/809] nrf5/modules/machine: Adding __WFI() on machine.deepsleep() --- nrf5/modules/machine/modmachine.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 276b248081..c847a4fc60 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -154,6 +154,7 @@ STATIC mp_obj_t machine_sleep(void) { MP_DEFINE_CONST_FUN_OBJ_0(machine_sleep_obj, machine_sleep); STATIC mp_obj_t machine_deepsleep(void) { + __WFI(); return mp_const_none; } MP_DEFINE_CONST_FUN_OBJ_0(machine_deepsleep_obj, machine_deepsleep); From 5f705adae06d4925351fe716f956d0fc922e53cf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 7 Mar 2017 17:41:46 +0100 Subject: [PATCH 477/809] nrf5/boards: Adding more heap memory to the nrf51 256k/32k s110 linker script. Leaving 2k for stack. --- nrf5/boards/nrf51x22_256k_32k_s110.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/nrf51x22_256k_32k_s110.ld b/nrf5/boards/nrf51x22_256k_32k_s110.ld index ec1aff397d..adee5b4bc9 100644 --- a/nrf5/boards/nrf51x22_256k_32k_s110.ld +++ b/nrf5/boards/nrf51x22_256k_32k_s110.ld @@ -14,7 +14,7 @@ MEMORY /* produce a link error if there is not this amount of RAM for these sections */ _minimum_stack_size = 2K; -_minimum_heap_size = 4K; +_minimum_heap_size = 1K; /* top end of the stack */ @@ -23,6 +23,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20003000; /* tunable */ +_heap_end = 0x20005000; /* tunable */ INCLUDE "boards/common.ld" From 9d2a2d227c2a6782391bb5e2300e8bc0ae6e5a6f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 7 Mar 2017 17:53:10 +0100 Subject: [PATCH 478/809] nrf5: Updated after merge with master. Updating nlr_jump_fail to call __fatal_error in order to provide a non-returning function call. --- nrf5/main.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/nrf5/main.c b/nrf5/main.c index e5b0f51705..8d0219a467 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -233,14 +233,16 @@ void HardFault_Handler(void) #endif } - -void nlr_jump_fail(void *val) { -} - void NORETURN __fatal_error(const char *msg) { while (1); } +void nlr_jump_fail(void *val) { + printf("FATAL: uncaught exception %p\n", val); + mp_obj_print_exception(&mp_plat_print, (mp_obj_t)val); + __fatal_error(""); +} + void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) { printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line); __fatal_error("Assertion failed"); From 9689aae45b0bf39a7a00e3d7d0a1c63220c1e5cd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 7 Mar 2017 18:01:13 +0100 Subject: [PATCH 479/809] nrf5/boards: Disable all display modules in pca10028 board config. --- nrf5/boards/pca10028/mpconfigboard.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index e69de00951..df1cad5ace 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -30,10 +30,10 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" -#define MICROPY_PY_DISPLAY (1) +#define MICROPY_PY_DISPLAY (0) #define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) #define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) -#define MICROPY_PY_DISPLAY_LCD_SSD1289 (1) +#define MICROPY_PY_DISPLAY_LCD_SSD1289 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) From 5f9b070f6d80e170ba02e79c570055d78acf4c97 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 7 Mar 2017 18:04:54 +0100 Subject: [PATCH 480/809] nrf5: Disable machine PWM module by default if board does not define it. --- nrf5/mpconfigport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index f0596de52b..8dd4266eba 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -128,7 +128,7 @@ #endif #ifndef MICROPY_PY_MACHINE_PWM -#define MICROPY_PY_MACHINE_PWM (1) +#define MICROPY_PY_MACHINE_PWM (0) #endif #ifndef MICROPY_PY_MACHINE_TIMER From 3b2ca64738c9db0583c9b0c93056441d30d6746f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 7 Mar 2017 18:05:38 +0100 Subject: [PATCH 481/809] nrf5/boards: Remove define of machine PWM module configuration in nrf51 targets, as the device does not have a HW PWM peripheral. --- nrf5/boards/microbit/mpconfigboard.h | 1 - nrf5/boards/pca10000/mpconfigboard.h | 1 - nrf5/boards/pca10028/mpconfigboard.h | 1 - nrf5/boards/pca10031/mpconfigboard.h | 1 - 4 files changed, 4 deletions(-) diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index 25816c993d..485a3f5acc 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -31,7 +31,6 @@ #define MICROPY_PY_SYS_PLATFORM "nrf51" #define MICROPY_PY_MACHINE_HW_SPI (1) -#define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_MACHINE_I2C (1) diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf5/boards/pca10000/mpconfigboard.h index 9646ced77c..a734e512ed 100644 --- a/nrf5/boards/pca10000/mpconfigboard.h +++ b/nrf5/boards/pca10000/mpconfigboard.h @@ -31,7 +31,6 @@ #define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" #define MICROPY_PY_MACHINE_HW_SPI (0) -#define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_HW_HAS_SWITCH (0) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index df1cad5ace..ae8c9e8352 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -38,7 +38,6 @@ #define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) #define MICROPY_PY_MACHINE_HW_SPI (1) -#define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_MACHINE_I2C (1) diff --git a/nrf5/boards/pca10031/mpconfigboard.h b/nrf5/boards/pca10031/mpconfigboard.h index 43c0693f7f..8baef4335e 100644 --- a/nrf5/boards/pca10031/mpconfigboard.h +++ b/nrf5/boards/pca10031/mpconfigboard.h @@ -30,7 +30,6 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" -#define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_HW_HAS_SWITCH (0) From 99f5ecdfad43580cf2e30da5cd33e2d0e8f7ab17 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 7 Mar 2017 23:15:59 +0100 Subject: [PATCH 482/809] nrf5/bluetooth: Moving bluetooth_conf.h to port root folder to make it more exposed. --- nrf5/{bluetooth => }/bluetooth_conf.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename nrf5/{bluetooth => }/bluetooth_conf.h (100%) diff --git a/nrf5/bluetooth/bluetooth_conf.h b/nrf5/bluetooth_conf.h similarity index 100% rename from nrf5/bluetooth/bluetooth_conf.h rename to nrf5/bluetooth_conf.h From f8d1ea80aeef4c3a35f8673c5d63f98e0a9629b0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 7 Mar 2017 23:18:03 +0100 Subject: [PATCH 483/809] nrf5/modules: Updating uart object to allow baudrate configuration. --- nrf5/modules/machine/uart.c | 56 +++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/machine/uart.c b/nrf5/modules/machine/uart.c index 37a2c5af9c..83a584cfff 100644 --- a/nrf5/modules/machine/uart.c +++ b/nrf5/modules/machine/uart.c @@ -170,7 +170,7 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, con // set the UART configuration values memset(&self->uart, 0, sizeof(self->uart)); - UART_InitTypeDef *init = &self->uart.init; + UART_InitTypeDef * init = &self->uart.init; // baudrate init->baud_rate = args[0].u_int; @@ -210,13 +210,65 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, con .flow_control = false, #endif .use_parity = false, - .baud_rate = HAL_UART_BAUD_115K2, #if (BLUETOOTH_SD == 100) .irq_priority = 3 #else .irq_priority = 6 #endif }; + + switch (init->baud_rate) { + case 1200: + uart_init.baud_rate = HAL_UART_BAUD_1K2; + break; + case 2400: + uart_init.baud_rate = HAL_UART_BAUD_2K4; + break; + case 4800: + uart_init.baud_rate = HAL_UART_BAUD_4K8; + break; + case 9600: + uart_init.baud_rate = HAL_UART_BAUD_9K6; + break; + case 14400: + uart_init.baud_rate = HAL_UART_BAUD_14K4; + break; + case 19200: + uart_init.baud_rate = HAL_UART_BAUD_19K2; + break; + case 28800: + uart_init.baud_rate = HAL_UART_BAUD_28K8; + break; + case 38400: + uart_init.baud_rate = HAL_UART_BAUD_38K4; + break; + case 57600: + uart_init.baud_rate = HAL_UART_BAUD_57K6; + break; + case 76800: + uart_init.baud_rate = HAL_UART_BAUD_76K8; + break; + case 115200: + uart_init.baud_rate = HAL_UART_BAUD_115K2; + break; + case 230400: + uart_init.baud_rate = HAL_UART_BAUD_230K4; + break; + case 250000: + uart_init.baud_rate = HAL_UART_BAUD_250K0; + break; + case 500000: + uart_init.baud_rate = HAL_UART_BAUD_500K0; + break; + case 1000000: + uart_init.baud_rate = HAL_UART_BAUD_1M0; + break; + default: + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "UART baudrate not supported, %ul", init->baud_rate)); + break; + } + uart_init.rx_pin = &MICROPY_HW_UART1_RX; uart_init.tx_pin = &MICROPY_HW_UART1_TX; From 611b829138a0e02f47c26e7a3d7adce344e0e9ba Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 10 Mar 2017 22:21:19 +0100 Subject: [PATCH 484/809] nrf5/uart: Refactoring UART module and HAL driver Facilitating for adding second HW uart. Moving pyb_uart into machine_uart. Adding return error codes from hal_uart functions, if the hardware detects an error. --- nrf5/hal/hal_uart.c | 81 +++++---- nrf5/hal/hal_uart.h | 106 ++++++------ nrf5/hal/hal_uarte.c | 181 +++++++------------- nrf5/main.c | 4 +- nrf5/modules/machine/uart.c | 326 +++++++++++++++--------------------- nrf5/modules/machine/uart.h | 12 +- nrf5/modules/pyb/modpyb.c | 2 +- nrf5/modules/uos/moduos.c | 2 +- nrf5/mpconfigport.h | 4 +- 9 files changed, 300 insertions(+), 418 deletions(-) diff --git a/nrf5/hal/hal_uart.c b/nrf5/hal/hal_uart.c index cda9ba60a1..13d549e103 100644 --- a/nrf5/hal/hal_uart.c +++ b/nrf5/hal/hal_uart.c @@ -33,14 +33,6 @@ #ifdef HAL_UART_MODULE_ENABLED -#ifdef NRF51 -#define UART_BASE ((NRF_UART_Type *) NRF_UART0_BASE) -#define UART_IRQ_NUM UART0_IRQn -#else -#define UART_BASE ((NRF_UART_Type *) NRF_UART0_BASE) -#define UART_IRQ_NUM UARTE0_UART0_IRQn -#endif - uint32_t hal_uart_baudrate_lookup[] = { UART_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud. UART_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud. @@ -60,80 +52,95 @@ uint32_t hal_uart_baudrate_lookup[] = { UART_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud. }; -void hal_uart_char_write(uint8_t ch) { - UART_BASE->TXD = (uint8_t)ch; - while (UART_BASE->EVENTS_TXDRDY != 1) { +hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch) { + p_instance->ERRORSRC = 0; + p_instance->TXD = (uint8_t)ch; + while (p_instance->EVENTS_TXDRDY != 1) { // Blocking wait. } // Clear the TX flag. - UART_BASE->EVENTS_TXDRDY = 0; + p_instance->EVENTS_TXDRDY = 0; + + return p_instance->ERRORSRC; } -uint8_t hal_uart_char_read(void) { - while (UART_BASE->EVENTS_RXDRDY != 1) { +hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch) { + p_instance->ERRORSRC = 0; + while (p_instance->EVENTS_RXDRDY != 1) { // Wait for RXD data. } - UART_BASE->EVENTS_RXDRDY = 0; - return (uint8_t)UART_BASE->RXD; + p_instance->EVENTS_RXDRDY = 0; + *ch = p_instance->RXD; + + return p_instance->ERRORSRC; } -void hal_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { +hal_uart_error_t hal_uart_buffer_write(NRF_UART_Type * p_instance, uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { int i = 0; + hal_uart_error_t err = 0; uint8_t ch = p_buffer[i++]; while (i < num_of_bytes) { - hal_uart_char_write(ch); + err = hal_uart_char_write(p_instance, ch); + if (err) { + return err; + } ch = p_buffer[i++]; } cb(); + return err; } -void hal_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { +hal_uart_error_t hal_uart_buffer_read(NRF_UART_Type * p_instance, uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { int i = 0; + hal_uart_error_t err = 0; while (i < num_of_bytes) { - uint8_t ch = hal_uart_char_read(); - p_buffer[i] = ch; + hal_uart_error_t err = hal_uart_char_read(p_instance, &p_buffer[i]); + if (err) { + return err; + } i++; } cb(); + return err; } -void hal_uart_init(hal_uart_init_t const * p_uart_init) { +void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init) { hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_pin_clear(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin); - UART_BASE->PSELTXD = p_uart_init->tx_pin->pin; - UART_BASE->PSELRXD = p_uart_init->rx_pin->pin; + p_instance->PSELTXD = p_uart_init->tx_pin->pin; + p_instance->PSELRXD = p_uart_init->rx_pin->pin; #if NRF52840_XXAA - UART_BASE->PSELTXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos); - UART_BASE->PSELRXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos); + p_instance->PSELTXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos); + p_instance->PSELRXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos); #endif if (p_uart_init->flow_control) { hal_gpio_cfg_pin(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_uart_init->cts_pin->port, p_uart_init->cts_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); - UART_BASE->PSELCTS = p_uart_init->cts_pin->pin; - UART_BASE->PSELRTS = p_uart_init->rts_pin->pin; + p_instance->PSELCTS = p_uart_init->cts_pin->pin; + p_instance->PSELRTS = p_uart_init->rts_pin->pin; #if NRF52840_XXAA - UART_BASE->PSELCTS |= (p_uart_init->cts_pin->port << UARTE_PSEL_CTS_PORT_Pos); - UART_BASE->PSELRTS |= (p_uart_init->rts_pin->port << UARTE_PSEL_RTS_PORT_Pos); + p_instance->PSELCTS |= (p_uart_init->cts_pin->port << UARTE_PSEL_CTS_PORT_Pos); + p_instance->PSELRTS |= (p_uart_init->rts_pin->port << UARTE_PSEL_RTS_PORT_Pos); #endif - UART_BASE->CONFIG = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos); + p_instance->CONFIG = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos); } - UART_BASE->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]); - UART_BASE->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos); - UART_BASE->EVENTS_TXDRDY = 0; - UART_BASE->EVENTS_RXDRDY = 0; - UART_BASE->TASKS_STARTTX = 1; - UART_BASE->TASKS_STARTRX = 1; + p_instance->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]); + p_instance->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos); + p_instance->EVENTS_TXDRDY = 0; + p_instance->EVENTS_RXDRDY = 0; + p_instance->TASKS_STARTTX = 1; + p_instance->TASKS_STARTRX = 1; } #endif // HAL_UART_MODULE_ENABLED diff --git a/nrf5/hal/hal_uart.h b/nrf5/hal/hal_uart.h index bc7a945d27..3f39f117c3 100644 --- a/nrf5/hal/hal_uart.h +++ b/nrf5/hal/hal_uart.h @@ -33,42 +33,49 @@ #include "nrf.h" #if NRF51 - -#define UART_HWCONTROL_NONE ((uint32_t)UART_CONFIG_HWFC_Disabled << UART_CONFIG_HWFC_Pos) -#define UART_HWCONTROL_RTS_CTS ((uint32_t)(UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos) -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + #define UART_HWCONTROL_NONE ((uint32_t)UART_CONFIG_HWFC_Disabled << UART_CONFIG_HWFC_Pos) + #define UART_HWCONTROL_RTS_CTS ((uint32_t)(UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos) + #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ (((CONTROL) == UART_HWCONTROL_NONE) || \ ((CONTROL) == UART_HWCONTROL_RTS_CTS)) + #define UART_BASE_POINTERS (const uint32_t[]){NRF_UART0_BASE} + #define UART_IRQ_VALUES (const uint32_t[]){UART0_IRQn} #elif NRF52 - -#define UART_HWCONTROL_NONE ((uint32_t)UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos) -#define UART_HWCONTROL_RTS_CTS ((uint32_t)(UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos) -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + #define UART_HWCONTROL_NONE ((uint32_t)UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos) + #define UART_HWCONTROL_RTS_CTS ((uint32_t)(UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos) + #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ (((CONTROL) == UART_HWCONTROL_NONE) || \ ((CONTROL) == UART_HWCONTROL_RTS_CTS)) + #ifdef HAL_UART_MODULE_ENABLED + #define UART_BASE_POINTERS (const uint32_t[]){NRF_UART0_BASE} + #define UART_IRQ_VALUES (const uint32_t[]){UARTE0_UART0_IRQn} + #else // HAL_UARTE_MODULE_ENABLED + #ifdef NRF52832_XXAA + #define UART_BASE_POINTERS (const uint32_t[]){NRF_UARTE0_BASE} + #define UART_IRQ_VALUES (const uint32_t[]){UARTE0_UART0_IRQn} + #elif NRF52840_XXAA + #define UART_BASE_POINTERS (const uint32_t[]){NRF_UARTE0_BASE, \ + NRF_UARTE1_BASE} + #define UART_IRQ_VALUES (const uint32_t[]){UARTE0_UART0_IRQn, \ + UARTE1_IRQn} + #endif // HAL_UARTE_MODULE_ENABLED + #endif #else #error "Device not supported." #endif -typedef enum { - HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_UART_STATE_ERROR = 0x04 /*!< Error */ -} HAL_UART_StateTypeDef; + +#define UART_BASE(x) ((NRF_UART_Type *)UART_BASE_POINTERS[x]) +#define UART_IRQ_NUM(x) (UART_IRQ_VALUES[x]) typedef enum { - HAL_UART_ERROR_NONE = 0x00, /*!< No error */ - HAL_UART_ERROR_ORE = 0x01, /*!< Overrun error. A start bit is received while the previous data still lies in RXD. (Previous data is lost.) */ - HAL_UART_ERROR_PE = 0x02, /*!< Parity error. A character with bad parity is received, if HW parity check is enabled. */ - HAL_UART_ERROR_FE = 0x04, /*!< Frame error. A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ - HAL_UART_ERROR_BE = 0x08, /*!< Break error. The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit.). */ -} HAL_UART_ErrorTypeDef; + HAL_UART_ERROR_NONE = 0x00, /*!< No error */ + HAL_UART_ERROR_ORE = 0x01, /*!< Overrun error. A start bit is received while the previous data still lies in RXD. (Previous data is lost.) */ + HAL_UART_ERROR_PE = 0x02, /*!< Parity error. A character with bad parity is received, if HW parity check is enabled. */ + HAL_UART_ERROR_FE = 0x04, /*!< Frame error. A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ + HAL_UART_ERROR_BE = 0x08, /*!< Break error. The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit.). */ +} hal_uart_error_t; typedef enum { HAL_UART_BAUD_1K2 = 0, /**< 1200 baud */ @@ -89,47 +96,30 @@ typedef enum { } hal_uart_baudrate_t; typedef struct { - uint32_t baud_rate; - uint32_t flow_control; -} UART_InitTypeDef; + uint8_t id; /* UART instance id */ + const pin_obj_t * rx_pin; /* RX pin. */ + const pin_obj_t * tx_pin; /* TX pin. */ + const pin_obj_t * rts_pin; /* RTS pin, only used if flow control is enabled. */ + const pin_obj_t * cts_pin; /* CTS pin, only used if flow control is enabled. */ + bool flow_control; /* Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ + bool use_parity; /* Even parity if TRUE, no parity if FALSE. */ + uint32_t baud_rate; /* Baud rate configuration. */ + uint32_t irq_priority; /* UARTE IRQ priority. */ + uint32_t irq_num; +} hal_uart_init_t; typedef struct { - NRF_UART_Type *instance; /* UART registers base address */ - UART_InitTypeDef init; /* UART communication parameters */ - uint8_t *p_tx_buff; /* Pointer to UART Tx transfer Buffer */ - uint16_t tx_xfer_size; /* UART Tx Transfer size */ - uint16_t tx_xfer_count; /* UART Tx Transfer Counter */ - uint8_t *p_rx_buff; /* Pointer to UART Rx transfer Buffer */ - uint16_t rx_xfer_size; /* UART Rx Transfer size */ - uint16_t rx_xfer_count; /* UART Rx Transfer Counter */ - __IO HAL_UART_StateTypeDef state; /* UART communication state */ - __IO HAL_UART_ErrorTypeDef error_code; /* UART Error code */ - + NRF_UART_Type * p_instance; /* UART registers base address */ + hal_uart_init_t init; /* UART communication parameters */ } UART_HandleTypeDef; -typedef struct { - const pin_obj_t * rx_pin; /**< RX pin. */ - const pin_obj_t * tx_pin; /**< TX pin. */ - const pin_obj_t * rts_pin; /**< RTS pin, only used if flow control is enabled. */ - const pin_obj_t * cts_pin; /**< CTS pin, only used if flow control is enabled. */ - bool flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ - bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ - uint32_t baud_rate; /**< Baud rate configuration. */ - uint32_t irq_priority; /**< UARTE IRQ priority. */ -} hal_uart_init_t; - - typedef void (*uart_complete_cb)(void); -void hal_uart_init(hal_uart_init_t const * p_uart_init); +void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init); -void hal_uart_char_write(uint8_t ch); +hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch); -uint8_t hal_uart_char_read(void); +hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch); -void hal_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb); - -void hal_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb); - -#endif // UART_H__ +#endif // HAL_UART_H__ diff --git a/nrf5/hal/hal_uarte.c b/nrf5/hal/hal_uarte.c index bb421bec20..6393c136d1 100644 --- a/nrf5/hal/hal_uarte.c +++ b/nrf5/hal/hal_uarte.c @@ -29,26 +29,22 @@ #include "mphalport.h" #include "hal_uart.h" +#include "hal_irq.h" #ifdef HAL_UARTE_MODULE_ENABLED #include "nrf.h" -#if NRF52 - -#define UARTE_BASE ((NRF_UARTE_Type *) NRF_UARTE0_BASE) -#define UART_IRQ_NUM UARTE0_UART0_IRQn - -#else +#ifndef NRF52 #error "Device not supported." #endif +#define UART_BASE(x) ((NRF_UART_Type *)UART_BASE_POINTERS[x]) +#define UART_IRQ_NUM(x) (UART_IRQ_VALUES[x]) + #define TX_BUF_SIZE 1 #define RX_BUF_SIZE 1 -static uart_complete_cb dma_read_cb = NULL; -static uart_complete_cb dma_write_cb = NULL; - static const uint32_t hal_uart_baudrate_lookup[] = { UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud. UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud. @@ -68,26 +64,19 @@ static const uint32_t hal_uart_baudrate_lookup[] = { UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud. }; -__STATIC_INLINE void hal_uart_irq_clear(void) { - NVIC_ClearPendingIRQ(UART_IRQ_NUM); +void nrf_sendchar(NRF_UART_Type * p_instance, int ch) { + hal_uart_char_write(p_instance, ch); } -__STATIC_INLINE void hal_uart_irq_enable(uint8_t priority) { - NVIC_SetPriority(UART_IRQ_NUM, priority); - hal_uart_irq_clear(); - NVIC_EnableIRQ(UART_IRQ_NUM); -} +void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init) { -void nrf_sendchar(int ch) { - hal_uart_char_write(ch); -} + NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance; -void hal_uart_init(hal_uart_init_t const * p_uart_init) { hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_pin_set(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin); hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED); - UARTE_BASE->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]); + uarte_instance->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]); uint32_t hwfc = (p_uart_init->flow_control) ? (UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos) @@ -97,14 +86,14 @@ void hal_uart_init(hal_uart_init_t const * p_uart_init) { ? (UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos) : (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos); - UARTE_BASE->CONFIG = (uint32_t)hwfc | (uint32_t)parity; + uarte_instance->CONFIG = (uint32_t)hwfc | (uint32_t)parity; - UARTE_BASE->PSEL.RXD = p_uart_init->rx_pin->pin; - UARTE_BASE->PSEL.TXD = p_uart_init->tx_pin->pin; + uarte_instance->PSEL.RXD = p_uart_init->rx_pin->pin; + uarte_instance->PSEL.TXD = p_uart_init->tx_pin->pin; #if NRF52840_XXAA - UARTE_BASE->PSEL.RXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos); - UARTE_BASE->PSEL.TXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos); + uarte_instance->PSEL.RXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos); + uarte_instance->PSEL.TXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos); #endif if (hwfc) { @@ -112,132 +101,80 @@ void hal_uart_init(hal_uart_init_t const * p_uart_init) { hal_gpio_cfg_pin(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); hal_gpio_pin_set(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin); - UARTE_BASE->PSEL.RTS = p_uart_init->rts_pin->pin; - UARTE_BASE->PSEL.CTS = p_uart_init->cts_pin->pin; + uarte_instance->PSEL.RTS = p_uart_init->rts_pin->pin; + uarte_instance->PSEL.CTS = p_uart_init->cts_pin->pin; #if NRF52840_XXAA - UARTE_BASE->PSEL.RTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_RTS_PORT_Pos); - UARTE_BASE->PSEL.CTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_CTS_PORT_Pos); + uarte_instance->PSEL.RTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_RTS_PORT_Pos); + uarte_instance->PSEL.CTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_CTS_PORT_Pos); #endif } - hal_uart_irq_enable(p_uart_init->irq_priority); + hal_irq_priority(p_uart_init->irq_num, p_uart_init->irq_priority); + hal_irq_enable(p_uart_init->irq_num); - UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); - UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); + uarte_instance->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); + uarte_instance->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); - UARTE_BASE->ENABLE = (UARTE_ENABLE_ENABLE_Enabled << UARTE_ENABLE_ENABLE_Pos); + uarte_instance->ENABLE = (UARTE_ENABLE_ENABLE_Enabled << UARTE_ENABLE_ENABLE_Pos); - UARTE_BASE->EVENTS_ENDTX = 0; - UARTE_BASE->EVENTS_ENDRX = 0; + uarte_instance->EVENTS_ENDTX = 0; + uarte_instance->EVENTS_ENDRX = 0; } -void hal_uart_char_write(uint8_t ch) { +hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch) { + + NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance; + + uarte_instance->ERRORSRC = 0; + + static volatile uint8_t m_tx_buf[TX_BUF_SIZE]; (void)m_tx_buf; - UARTE_BASE->INTENCLR = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); + uarte_instance->INTENCLR = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); m_tx_buf[0] = ch; - UARTE_BASE->TXD.PTR = (uint32_t)((uint8_t *)m_tx_buf); - UARTE_BASE->TXD.MAXCNT = (uint32_t)sizeof(m_tx_buf); + uarte_instance->TXD.PTR = (uint32_t)((uint8_t *)m_tx_buf); + uarte_instance->TXD.MAXCNT = (uint32_t)sizeof(m_tx_buf); - UARTE_BASE->TASKS_STARTTX = 1; + uarte_instance->TASKS_STARTTX = 1; - while((0 == UARTE_BASE->EVENTS_ENDTX)); + while((0 == uarte_instance->EVENTS_ENDTX)); - UARTE_BASE->EVENTS_ENDTX = 0; - UARTE_BASE->TASKS_STOPTX = 1; + uarte_instance->EVENTS_ENDTX = 0; + uarte_instance->TASKS_STOPTX = 1; - UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); + uarte_instance->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); + + return uarte_instance->ERRORSRC; } -uint8_t hal_uart_char_read(void) { +hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch) { + + NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance; + + uarte_instance->ERRORSRC = 0; + static volatile uint8_t m_rx_buf[RX_BUF_SIZE]; - UARTE_BASE->INTENCLR = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); + uarte_instance->INTENCLR = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); - UARTE_BASE->RXD.PTR = (uint32_t)((uint8_t *)m_rx_buf); - UARTE_BASE->RXD.MAXCNT = (uint32_t)sizeof(m_rx_buf); + uarte_instance->RXD.PTR = (uint32_t)((uint8_t *)m_rx_buf); + uarte_instance->RXD.MAXCNT = (uint32_t)sizeof(m_rx_buf); - UARTE_BASE->TASKS_STARTRX = 1; + uarte_instance->TASKS_STARTRX = 1; - while ((0 == UARTE_BASE->EVENTS_ENDRX)); + while ((0 == uarte_instance->EVENTS_ENDRX)); - UARTE_BASE->EVENTS_ENDRX = 0; - UARTE_BASE->TASKS_STOPRX = 1; + uarte_instance->EVENTS_ENDRX = 0; + uarte_instance->TASKS_STOPRX = 1; - UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); + uarte_instance->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); + *ch = (uint8_t)m_rx_buf[0]; - return (uint8_t)m_rx_buf[0]; -} - -void hal_uart_buffer_write(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { - dma_write_cb = cb; - - UARTE_BASE->TXD.PTR = (uint32_t)p_buffer; - UARTE_BASE->TXD.MAXCNT = num_of_bytes; - UARTE_BASE->TASKS_STARTTX = 1; - - while((0 == UARTE_BASE->EVENTS_ENDTX)); - - UARTE_BASE->EVENTS_ENDTX = 0; - UARTE_BASE->TASKS_STOPTX = 1; - - UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos); - -} - -void hal_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) { - dma_read_cb = cb; - - UARTE_BASE->RXD.PTR = (uint32_t)(p_buffer); - UARTE_BASE->RXD.MAXCNT = num_of_bytes; - UARTE_BASE->TASKS_STARTRX = 1; - - while ((0 == UARTE_BASE->EVENTS_ENDRX)); - - UARTE_BASE->EVENTS_ENDRX = 0; - UARTE_BASE->TASKS_STOPRX = 1; - - UARTE_BASE->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos); - -} - -static void dma_read_complete(void) { - UARTE_BASE->TASKS_STOPRX = 1; - - if (dma_read_cb != NULL) { - uart_complete_cb temp_cb = dma_read_cb; - dma_read_cb = NULL; - temp_cb(); - } -} - -static void dma_write_complete(void) { - UARTE_BASE->TASKS_STOPTX = 1; - - if (dma_write_cb != NULL) { - uart_complete_cb temp_cb = dma_write_cb; - dma_write_cb = NULL; - temp_cb(); - } -} - -void UARTE0_UART0_IRQHandler(void) { - if ((UARTE_BASE->EVENTS_ENDRX) - && (UARTE_BASE->INTEN & UARTE_INTENSET_ENDRX_Msk)) { - - UARTE_BASE->EVENTS_ENDRX = 0; - dma_read_complete(); - - } else if ((UARTE_BASE->EVENTS_ENDTX) - && (UARTE_BASE->INTEN & UARTE_INTENSET_ENDTX_Msk)) { - - UARTE_BASE->EVENTS_ENDTX = 0; - dma_write_complete(); - } + return uarte_instance->ERRORSRC; } #endif // HAL_UARTE_MODULE_ENABLED diff --git a/nrf5/main.c b/nrf5/main.c index 8d0219a467..9412cabbff 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -135,10 +135,10 @@ int main(int argc, char **argv) { #if (MICROPY_PY_BLE_NUS == 0) { mp_obj_t args[2] = { - MP_OBJ_NEW_SMALL_INT(PYB_UART_1), + MP_OBJ_NEW_SMALL_INT(0), MP_OBJ_NEW_SMALL_INT(115200), }; - MP_STATE_PORT(pyb_stdio_uart) = pyb_uart_type.make_new((mp_obj_t)&pyb_uart_type, MP_ARRAY_SIZE(args), 0, args); + MP_STATE_PORT(pyb_stdio_uart) = machine_hard_uart_type.make_new((mp_obj_t)&machine_hard_uart_type, MP_ARRAY_SIZE(args), 0, args); } #endif diff --git a/nrf5/modules/machine/uart.c b/nrf5/modules/machine/uart.c index 83a584cfff..5714b8b4c5 100644 --- a/nrf5/modules/machine/uart.c +++ b/nrf5/modules/machine/uart.c @@ -46,86 +46,86 @@ #define CHAR_WIDTH_8BIT (0) #define CHAR_WIDTH_9BIT (1) -struct _pyb_uart_obj_t { +typedef struct _machine_hard_uart_obj_t { mp_obj_base_t base; - UART_HandleTypeDef uart; - IRQn_Type irqn; - pyb_uart_t uart_id : 8; - bool is_enabled : 1; + UART_HandleTypeDef * uart; byte char_width; // 0 for 7,8 bit chars, 1 for 9 bit chars - uint16_t char_mask; // 0x7f for 7 bit, 0xff for 8 bit, 0x1ff for 9 bit - uint16_t timeout; // timeout waiting for first char - uint16_t timeout_char; // timeout waiting between chars - uint16_t read_buf_len; // len in chars; buf can hold len-1 chars - volatile uint16_t read_buf_head; // indexes first empty slot - uint16_t read_buf_tail; // indexes first full slot (not full if equals head) - byte *read_buf; // byte or uint16_t, depending on char size +} machine_hard_uart_obj_t; + +UART_HandleTypeDef UARTHandle0 = {.p_instance = NULL, .init.id = 0}; +#if NRF52840_XXAA +UART_HandleTypeDef UARTHandle1 = {.p_instance = NULL, .init.id = 1}; +#endif + +STATIC machine_hard_uart_obj_t machine_hard_uart_obj[] = { + {{&machine_hard_uart_type}, &UARTHandle0}, +#if NRF52840_XXAA + {{&machine_hard_uart_type}, &UARTHandle1}, +#endif }; -STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in); - void uart_init0(void) { + // reset the UART handles + memset(&UARTHandle0, 0, sizeof(UART_HandleTypeDef)); + UARTHandle0.p_instance = UART_BASE(0); +#if NRF52840_XXAA + memset(&UARTHandle1, 0, sizeof(UART_HandleTypeDef)); + UARTHandle0.p_instance = UART_BASE(1); +#endif +#if 0 for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) { MP_STATE_PORT(pyb_uart_obj_all)[i] = NULL; } +#endif } -// unregister all interrupt sources -void uart_deinit(void) { - for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) { - pyb_uart_obj_t *uart_obj = MP_STATE_PORT(pyb_uart_obj_all)[i]; - if (uart_obj != NULL) { - pyb_uart_deinit(uart_obj); - } +STATIC int uart_find(mp_obj_t id) { + // given an integer id + int uart_id = mp_obj_get_int(id); + if (uart_id >= 0 && uart_id <= MP_ARRAY_SIZE(machine_hard_uart_obj) + && machine_hard_uart_obj[uart_id].uart != NULL) { + return uart_id; } -} - -/// \method deinit() -/// Turn off the UART bus. -STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in) { - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_deinit_obj, pyb_uart_deinit); - -//// assumes Init parameters have been set up correctly -STATIC bool uart_init2(pyb_uart_obj_t * uart_obj) { - uart_obj->is_enabled = true; - - return true; + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "UART(%d) does not exist", uart_id)); } void uart_irq_handler(mp_uint_t uart_id) { } -bool uart_rx_any(pyb_uart_obj_t *uart_obj) { - // TODO: uart will block for now. - return true; +bool uart_rx_any(machine_hard_uart_obj_t *uart_obj) { + // TODO: uart will block for now. + return true; } +#if 0 // Waits at most timeout milliseconds for at least 1 char to become ready for // reading (from buf or for direct reading). // Returns true if something available, false if not. -STATIC bool uart_rx_wait(pyb_uart_obj_t *self, uint32_t timeout) { - return false; +STATIC bool uart_rx_wait(machine_hard_uart_obj_t * self, uint32_t timeout) { + return false; +} +#endif + +int uart_rx_char(machine_hard_uart_obj_t * self) { + uint8_t ch; + hal_uart_char_read(self->uart->p_instance, &ch); + return (int)ch; } -int uart_rx_char(pyb_uart_obj_t *self) { - return (int)hal_uart_char_read(); -} - -STATIC void uart_tx_char(pyb_uart_obj_t * self, int c) { - hal_uart_char_write((char)c); +STATIC hal_uart_error_t uart_tx_char(machine_hard_uart_obj_t * self, int c) { + return hal_uart_char_write(self->uart->p_instance, (char)c); } -void uart_tx_strn(pyb_uart_obj_t *uart_obj, const char *str, uint len) { +void uart_tx_strn(machine_hard_uart_obj_t *uart_obj, const char *str, uint len) { for (const char *top = str + len; str < top; str++) { uart_tx_char(uart_obj, *str); } } -void uart_tx_strn_cooked(pyb_uart_obj_t *uart_obj, const char *str, uint len) { +void uart_tx_strn_cooked(machine_hard_uart_obj_t *uart_obj, const char *str, uint len) { for (const char *top = str + len; str < top; str++) { if (*str == '\n') { uart_tx_char(uart_obj, '\r'); @@ -140,10 +140,12 @@ void uart_tx_strn_cooked(pyb_uart_obj_t *uart_obj, const char *str, uint len) { STATIC void pyb_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { } + + /// \method init(baudrate, bits=8, parity=None, stop=1, *, timeout=1000, timeout_char=0, read_buf_len=64) /// /// Initialise the UART bus with the given parameters: -/// +/// - `id`is bus id. /// - `baudrate` is the clock rate. /// - `bits` is the number of bits per byte, 7, 8 or 9. /// - `parity` is the parity, `None`, 0 (even) or 1 (odd). @@ -151,41 +153,40 @@ STATIC void pyb_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_k /// - `timeout` is the timeout in milliseconds to wait for the first character. /// - `timeout_char` is the timeout in milliseconds to wait between characters. /// - `read_buf_len` is the character length of the read buffer (0 to disable). -STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { +STATIC mp_obj_t machine_hard_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { + { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ }, { MP_QSTR_baudrate, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 9600} }, { MP_QSTR_bits, MP_ARG_INT, {.u_int = 8} }, { MP_QSTR_parity, MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_stop, MP_ARG_INT, {.u_int = 1} }, - { MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UART_HWCONTROL_NONE} }, + { MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} }, { MP_QSTR_timeout_char, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, { MP_QSTR_read_buf_len, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 64} }, }; - // parse args mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; - mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - // set the UART configuration values - memset(&self->uart, 0, sizeof(self->uart)); - UART_InitTypeDef * init = &self->uart.init; + // get static peripheral object + int uart_id = uart_find(args[0].u_obj); + machine_hard_uart_obj_t * self = &machine_hard_uart_obj[uart_id]; - // baudrate - init->baud_rate = args[0].u_int; + hal_uart_init_t * init = &self->uart->init; // flow control - init->flow_control = args[4].u_int; - + init->flow_control = args[5].u_int; +#if 0 // init UART (if it fails, it's because the port doesn't exist) if (!uart_init2(self)) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%d) does not exist", self->uart_id)); } // set timeouts - self->timeout = args[5].u_int; - self->timeout_char = args[6].u_int; + self->timeout = args[6].u_int; + self->timeout_char = args[7].u_int; // setup the read buffer m_del(byte, self->read_buf, self->read_buf_len << self->char_width); @@ -193,75 +194,75 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, con self->read_buf_head = 0; self->read_buf_tail = 0; - if (args[7].u_int <= 0) { + if (args[8].u_int <= 0) { // no read buffer self->read_buf_len = 0; self->read_buf = NULL; } else { // read buffer using interrupts - self->read_buf_len = args[7].u_int; - self->read_buf = m_new(byte, args[7].u_int << self->char_width); + self->read_buf_len = args[8].u_int; + self->read_buf = m_new(byte, args[8].u_int << self->char_width); } - hal_uart_init_t uart_init = { -#if MICROPY_HW_UART1_HWFC - .flow_control = true, -#else - .flow_control = false, -#endif - .use_parity = false, -#if (BLUETOOTH_SD == 100) - .irq_priority = 3 -#else - .irq_priority = 6 -#endif - }; +#endif // 0 - switch (init->baud_rate) { +#if MICROPY_HW_UART1_HWFC + init->flow_control = true; +#else + init->flow_control = false; +#endif + init->use_parity = false; +#if (BLUETOOTH_SD == 100) + init->irq_priority = 3; +#else + init->irq_priority = 6; +#endif + + switch (args[1].u_int) { case 1200: - uart_init.baud_rate = HAL_UART_BAUD_1K2; + init->baud_rate = HAL_UART_BAUD_1K2; break; case 2400: - uart_init.baud_rate = HAL_UART_BAUD_2K4; + init->baud_rate = HAL_UART_BAUD_2K4; break; case 4800: - uart_init.baud_rate = HAL_UART_BAUD_4K8; + init->baud_rate = HAL_UART_BAUD_4K8; break; case 9600: - uart_init.baud_rate = HAL_UART_BAUD_9K6; + init->baud_rate = HAL_UART_BAUD_9K6; break; case 14400: - uart_init.baud_rate = HAL_UART_BAUD_14K4; + init->baud_rate = HAL_UART_BAUD_14K4; break; case 19200: - uart_init.baud_rate = HAL_UART_BAUD_19K2; + init->baud_rate = HAL_UART_BAUD_19K2; break; case 28800: - uart_init.baud_rate = HAL_UART_BAUD_28K8; + init->baud_rate = HAL_UART_BAUD_28K8; break; case 38400: - uart_init.baud_rate = HAL_UART_BAUD_38K4; + init->baud_rate = HAL_UART_BAUD_38K4; break; case 57600: - uart_init.baud_rate = HAL_UART_BAUD_57K6; + init->baud_rate = HAL_UART_BAUD_57K6; break; case 76800: - uart_init.baud_rate = HAL_UART_BAUD_76K8; + init->baud_rate = HAL_UART_BAUD_76K8; break; case 115200: - uart_init.baud_rate = HAL_UART_BAUD_115K2; + init->baud_rate = HAL_UART_BAUD_115K2; break; case 230400: - uart_init.baud_rate = HAL_UART_BAUD_230K4; + init->baud_rate = HAL_UART_BAUD_230K4; break; case 250000: - uart_init.baud_rate = HAL_UART_BAUD_250K0; + init->baud_rate = HAL_UART_BAUD_250K0; break; case 500000: - uart_init.baud_rate = HAL_UART_BAUD_500K0; + init->baud_rate = HAL_UART_BAUD_500K0; break; case 1000000: - uart_init.baud_rate = HAL_UART_BAUD_1M0; + init->baud_rate = HAL_UART_BAUD_1M0; break; default: nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, @@ -269,72 +270,23 @@ STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, con break; } - uart_init.rx_pin = &MICROPY_HW_UART1_RX; - uart_init.tx_pin = &MICROPY_HW_UART1_TX; + init->rx_pin = &MICROPY_HW_UART1_RX; + init->tx_pin = &MICROPY_HW_UART1_TX; #if MICROPY_HW_UART1_HWFC - uart_init.rts_pin = &MICROPY_HW_UART1_RTS; - uart_init.cts_pin = &MICROPY_HW_UART1_CTS; + init->rts_pin = &MICROPY_HW_UART1_RTS; + init->cts_pin = &MICROPY_HW_UART1_CTS; #endif - hal_uart_init(&uart_init); + hal_uart_init(self->uart->p_instance, init); - return mp_const_none; + return MP_OBJ_FROM_PTR(self); } -/// \classmethod \constructor(bus, ...) -/// -/// Construct a UART object. -STATIC mp_obj_t pyb_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { - // check arguments - mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true); - - // work out port - int uart_id = 0; - - if (MP_OBJ_IS_STR(args[0])) { - const char *port = mp_obj_str_get_str(args[0]); - if (0) { - - } else if (strcmp(port, "COM1") == 0) { - uart_id = PYB_UART_1; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%s) does not exist", port)); - } - } else { - uart_id = mp_obj_get_int(args[0]); - if (uart_id < 1 || uart_id > MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all))) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%d) does not exist", uart_id)); - } - } - - pyb_uart_obj_t *self; - if (MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1] == NULL) { - // create new UART object - self = m_new0(pyb_uart_obj_t, 1); - self->base.type = &pyb_uart_type; - self->uart_id = uart_id; - MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1] = self; - } else { - // reference existing UART object - self = MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1]; - } - - if (n_args > 1 || n_kw > 0) { - // start the peripheral - mp_map_t kw_args; - mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); - pyb_uart_init_helper(self, n_args - 1, args + 1, &kw_args); - } - - return self; -} - - /// \method any() /// Return `True` if any characters waiting, else `False`. STATIC mp_obj_t pyb_uart_any(mp_obj_t self_in) { - pyb_uart_obj_t *self = self_in; + machine_hard_uart_obj_t *self = self_in; if (uart_rx_any(self)) { return mp_const_true; } else { @@ -346,56 +298,53 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_any_obj, pyb_uart_any); /// \method writechar(char) /// Write a single character on the bus. `char` is an integer to write. /// Return value: `None`. -STATIC mp_obj_t pyb_uart_writechar(mp_obj_t self_in, mp_obj_t char_in) { - pyb_uart_obj_t *self = self_in; +STATIC mp_obj_t machine_hard_uart_writechar(mp_obj_t self_in, mp_obj_t char_in) { + machine_hard_uart_obj_t *self = self_in; // get the character to write (might be 9 bits) uint16_t data = mp_obj_get_int(char_in); + hal_uart_error_t err = 0; for (int i = 0; i < 2; i++) { - uart_tx_char(self, (int)(&data)[i]); + err = uart_tx_char(self, (int)(&data)[i]); } - self->uart.instance->TASKS_STOPTX = 0; + HAL_StatusTypeDef status = self->uart->p_instance->EVENTS_ERROR; - HAL_StatusTypeDef status = self->uart.instance->EVENTS_ERROR; - - if (status != HAL_OK) { + if (err != HAL_UART_ERROR_NONE) { mp_hal_raise(status); } return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_uart_writechar_obj, pyb_uart_writechar); +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_hard_uart_writechar_obj, machine_hard_uart_writechar); /// \method readchar() /// Receive a single character on the bus. /// Return value: The character read, as an integer. Returns -1 on timeout. -STATIC mp_obj_t pyb_uart_readchar(mp_obj_t self_in) { - pyb_uart_obj_t *self = self_in; - +STATIC mp_obj_t machine_hard_uart_readchar(mp_obj_t self_in) { + machine_hard_uart_obj_t *self = self_in; +#if 0 if (uart_rx_wait(self, self->timeout)) { +#endif return MP_OBJ_NEW_SMALL_INT(uart_rx_char(self)); +#if 0 } else { // return -1 on timeout return MP_OBJ_NEW_SMALL_INT(-1); } +#endif } -STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_readchar_obj, pyb_uart_readchar); +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_hard_uart_readchar_obj, machine_hard_uart_readchar); // uart.sendbreak() -STATIC mp_obj_t pyb_uart_sendbreak(mp_obj_t self_in) { +STATIC mp_obj_t machine_hard_uart_sendbreak(mp_obj_t self_in) { return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_sendbreak_obj, pyb_uart_sendbreak); +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_hard_uart_sendbreak_obj, machine_hard_uart_sendbreak); STATIC const mp_map_elem_t pyb_uart_locals_dict_table[] = { // instance methods - - //{ MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&pyb_uart_init_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_deinit), (mp_obj_t)&pyb_uart_deinit_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_any), (mp_obj_t)&pyb_uart_any_obj }, - /// \method read([nbytes]) { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&mp_stream_read_obj }, /// \method readline() @@ -403,9 +352,9 @@ STATIC const mp_map_elem_t pyb_uart_locals_dict_table[] = { /// \method readinto(buf[, nbytes]) { MP_OBJ_NEW_QSTR(MP_QSTR_readinto), (mp_obj_t)&mp_stream_readinto_obj }, /// \method writechar(buf) - { MP_OBJ_NEW_QSTR(MP_QSTR_writechar), (mp_obj_t)&pyb_uart_writechar_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readchar), (mp_obj_t)&pyb_uart_readchar_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_sendbreak), (mp_obj_t)&pyb_uart_sendbreak_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_writechar), (mp_obj_t)&machine_hard_uart_writechar_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_readchar), (mp_obj_t)&machine_hard_uart_readchar_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_sendbreak), (mp_obj_t)&machine_hard_uart_sendbreak_obj }, // class constants /* @@ -416,8 +365,8 @@ STATIC const mp_map_elem_t pyb_uart_locals_dict_table[] = { STATIC MP_DEFINE_CONST_DICT(pyb_uart_locals_dict, pyb_uart_locals_dict_table); -STATIC mp_uint_t pyb_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) { - pyb_uart_obj_t *self = self_in; +STATIC mp_uint_t machine_hard_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) { + machine_hard_uart_obj_t *self = self_in; byte *buf = buf_in; // check that size is a multiple of character width @@ -439,7 +388,7 @@ STATIC mp_uint_t pyb_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, i for (;;) { int data = uart_rx_char(self); - *buf++ = data; + *buf++ = data; if (--size == 0) { // return number of bytes read @@ -448,8 +397,8 @@ STATIC mp_uint_t pyb_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, i } } -STATIC mp_uint_t pyb_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) { - pyb_uart_obj_t *self = self_in; +STATIC mp_uint_t machine_hard_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) { + machine_hard_uart_obj_t *self = self_in; const byte *buf = buf_in; // check that size is a multiple of character width @@ -458,39 +407,38 @@ STATIC mp_uint_t pyb_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t return MP_STREAM_ERROR; } + hal_uart_error_t err = 0; for (int i = 0; i < size; i++) { - uart_tx_char(self, (int)((uint8_t *)buf)[i]); + err = uart_tx_char(self, (int)((uint8_t *)buf)[i]); } - HAL_StatusTypeDef status = self->uart.instance->EVENTS_ERROR; - - if (status == HAL_OK) { + if (err == HAL_UART_ERROR_NONE) { // return number of bytes written return size; } else { - *errcode = mp_hal_status_to_errno_table[status]; + *errcode = mp_hal_status_to_errno_table[err]; return MP_STREAM_ERROR; } } -STATIC mp_uint_t pyb_uart_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) { - pyb_uart_obj_t *self = self_in; +STATIC mp_uint_t machine_hard_uart_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) { + machine_hard_uart_obj_t *self = self_in; (void)self; return MP_STREAM_ERROR; } STATIC const mp_stream_p_t uart_stream_p = { - .read = pyb_uart_read, - .write = pyb_uart_write, - .ioctl = pyb_uart_ioctl, + .read = machine_hard_uart_read, + .write = machine_hard_uart_write, + .ioctl = machine_hard_uart_ioctl, .is_text = false, }; -const mp_obj_type_t pyb_uart_type = { +const mp_obj_type_t machine_hard_uart_type = { { &mp_type_type }, .name = MP_QSTR_UART, .print = pyb_uart_print, - .make_new = pyb_uart_make_new, + .make_new = machine_hard_uart_make_new, .getiter = mp_identity_getiter, .iternext = mp_stream_unbuffered_iter, .protocol = &uart_stream_p, diff --git a/nrf5/modules/machine/uart.h b/nrf5/modules/machine/uart.h index 26b79c949f..e05744dba8 100644 --- a/nrf5/modules/machine/uart.h +++ b/nrf5/modules/machine/uart.h @@ -33,16 +33,16 @@ typedef enum { PYB_UART_1 = 1, } pyb_uart_t; -typedef struct _pyb_uart_obj_t pyb_uart_obj_t; -extern const mp_obj_type_t pyb_uart_type; +typedef struct _machine_hard_uart_obj_t machine_hard_uart_obj_t; +extern const mp_obj_type_t machine_hard_uart_type; void uart_init0(void); void uart_deinit(void); void uart_irq_handler(mp_uint_t uart_id); -bool uart_rx_any(pyb_uart_obj_t *uart_obj); -int uart_rx_char(pyb_uart_obj_t *uart_obj); -void uart_tx_strn(pyb_uart_obj_t *uart_obj, const char *str, uint len); -void uart_tx_strn_cooked(pyb_uart_obj_t *uart_obj, const char *str, uint len); +bool uart_rx_any(machine_hard_uart_obj_t * uart_obj); +int uart_rx_char(machine_hard_uart_obj_t * uart_obj); +void uart_tx_strn(machine_hard_uart_obj_t * uart_obj, const char *str, uint len); +void uart_tx_strn_cooked(machine_hard_uart_obj_t *uart_obj, const char *str, uint len); #endif diff --git a/nrf5/modules/pyb/modpyb.c b/nrf5/modules/pyb/modpyb.c index b436c2468c..1a5848f869 100644 --- a/nrf5/modules/pyb/modpyb.c +++ b/nrf5/modules/pyb/modpyb.c @@ -37,7 +37,7 @@ STATIC const mp_map_elem_t pyb_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_pyb) }, { MP_OBJ_NEW_QSTR(MP_QSTR_LED), (mp_obj_t)&pyb_led_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_repl_info), (mp_obj_t)&pyb_set_repl_info_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&pyb_uart_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&machine_hard_uart_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_Pin), (mp_obj_t)&pin_type }, /* { MP_OBJ_NEW_QSTR(MP_QSTR_main), (mp_obj_t)&pyb_main_obj }*/ }; diff --git a/nrf5/modules/uos/moduos.c b/nrf5/modules/uos/moduos.c index 35bc3f0e64..0f814a9c55 100644 --- a/nrf5/modules/uos/moduos.c +++ b/nrf5/modules/uos/moduos.c @@ -118,7 +118,7 @@ STATIC mp_obj_t os_dupterm(mp_uint_t n_args, const mp_obj_t *args) { } else { if (args[0] == mp_const_none) { MP_STATE_PORT(pyb_stdio_uart) = NULL; - } else if (mp_obj_get_type(args[0]) == &pyb_uart_type) { + } else if (mp_obj_get_type(args[0]) == &machine_hard_uart_type) { MP_STATE_PORT(pyb_stdio_uart) = args[0]; } else { nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "need a UART object")); diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 8dd4266eba..de50aa57e5 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -341,10 +341,10 @@ extern const struct _mp_obj_module_t ble_module; struct _pyb_timer_obj_t *pyb_timer_obj_all[14]; \ \ /* stdio is repeated on this UART object if it's not null */ \ - struct _pyb_uart_obj_t *pyb_stdio_uart; \ + struct _machine_hard_uart_obj_t *pyb_stdio_uart; \ \ /* pointers to all UART objects (if they have been created) */ \ - struct _pyb_uart_obj_t *pyb_uart_obj_all[1]; \ + struct _machine_hard_uart_obj_t *pyb_uart_obj_all[1]; \ \ /* list of registered NICs */ \ mp_obj_list_t mod_network_nic_list; \ From 1aecf560da9df6d0246020cb122ac6f8df8bdcfb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 10 Mar 2017 22:48:43 +0100 Subject: [PATCH 485/809] nrf5/uart: Moving UART from pyb to machine module. --- nrf5/modules/machine/modmachine.c | 2 ++ nrf5/modules/pyb/modpyb.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index c847a4fc60..8f78a12606 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -38,6 +38,7 @@ #include "lib/oofatfs/diskio.h" #include "gccollect.h" #include "pin.h" +#include "uart.h" #include "spi.h" #include "i2c.h" #if MICROPY_PY_MACHINE_PWM @@ -199,6 +200,7 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_deepsleep), (mp_obj_t)&machine_deepsleep_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_reset_cause), (mp_obj_t)&machine_reset_cause_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_Pin), (mp_obj_t)&pin_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&machine_hard_uart_type }, #if MICROPY_PY_MACHINE_HW_SPI { MP_OBJ_NEW_QSTR(MP_QSTR_SPI), (mp_obj_t)&machine_hard_spi_type }, #endif diff --git a/nrf5/modules/pyb/modpyb.c b/nrf5/modules/pyb/modpyb.c index 1a5848f869..8d09944a25 100644 --- a/nrf5/modules/pyb/modpyb.c +++ b/nrf5/modules/pyb/modpyb.c @@ -28,7 +28,6 @@ #include "lib/utils/pyexec.h" #include "py/runtime.h" #include "py/obj.h" -#include "uart.h" #include "led.h" #include "nrf.h" // TODO: figure out where to put this import #include "pin.h" @@ -37,7 +36,6 @@ STATIC const mp_map_elem_t pyb_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_pyb) }, { MP_OBJ_NEW_QSTR(MP_QSTR_LED), (mp_obj_t)&pyb_led_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_repl_info), (mp_obj_t)&pyb_set_repl_info_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&machine_hard_uart_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_Pin), (mp_obj_t)&pin_type }, /* { MP_OBJ_NEW_QSTR(MP_QSTR_main), (mp_obj_t)&pyb_main_obj }*/ }; From 91652882a96900bc37a1da05c1ac41e34940eb79 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 12:34:11 +0100 Subject: [PATCH 486/809] nrf5/modules/ubluepy: Adding templates for central role Scanner and ScanEntry objects. --- nrf5/modules/ubluepy/ubluepy_scan_entry.c | 47 +++++++++++++++++++++++ nrf5/modules/ubluepy/ubluepy_scanner.c | 47 +++++++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 nrf5/modules/ubluepy/ubluepy_scan_entry.c create mode 100644 nrf5/modules/ubluepy/ubluepy_scanner.c diff --git a/nrf5/modules/ubluepy/ubluepy_scan_entry.c b/nrf5/modules/ubluepy/ubluepy_scan_entry.c new file mode 100644 index 0000000000..48328e1921 --- /dev/null +++ b/nrf5/modules/ubluepy/ubluepy_scan_entry.c @@ -0,0 +1,47 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "py/obj.h" +#include "py/runtime.h" +#include "py/objstr.h" +#include "py/objlist.h" + +#if MICROPY_PY_UBLUEPY_CENTRAL + +#include "ble_drv.h" + +const mp_obj_type_t ubluepy_scan_entry_type = { + { &mp_type_type }, + .name = MP_QSTR_ScanEntry, +#if 0 + .print = ubluepy_scan_entry_print, + .make_new = ubluepy_scan_entry_make_new, + .locals_dict = (mp_obj_t)&ubluepy_scan_entry_locals_dict +#endif +}; + +#endif // MICROPY_PY_UBLUEPY_CENTRAL diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c new file mode 100644 index 0000000000..f1280b8311 --- /dev/null +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -0,0 +1,47 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "py/obj.h" +#include "py/runtime.h" +#include "py/objstr.h" +#include "py/objlist.h" + +#if MICROPY_PY_UBLUEPY_CENTRAL + +#include "ble_drv.h" + +const mp_obj_type_t ubluepy_scanner_type = { + { &mp_type_type }, + .name = MP_QSTR_Scanner, +#if 0 + .print = ubluepy_scanner_print, + .make_new = ubluepy_scanner_make_new, + .locals_dict = (mp_obj_t)&ubluepy_scanner_locals_dict +#endif +}; + +#endif // MICROPY_PY_UBLUEPY_CENTRAL From 11c40892ac83bea0c7288c36c225e04470c95ae3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 14:20:41 +0100 Subject: [PATCH 487/809] nrf5/modules/ubluepy: Adding template object typedefs for scanner and scan entry, and extern definition for scanner and scan_entry object type in modubluepy.h --- nrf5/modules/ubluepy/modubluepy.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 2b1c6f62d3..c5f8440e60 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -77,6 +77,8 @@ extern const mp_obj_type_t ubluepy_uuid_type; extern const mp_obj_type_t ubluepy_service_type; extern const mp_obj_type_t ubluepy_characteristic_type; extern const mp_obj_type_t ubluepy_peripheral_type; +extern const mp_obj_type_t ubluepy_scanner_type; +extern const mp_obj_type_t ubluepy_scan_entry_type; typedef enum { UBLUEPY_UUID_16_BIT = 1, @@ -143,6 +145,14 @@ typedef struct _ubluepy_advertise_data_t { uint8_t num_of_services; } ubluepy_advertise_data_t; +typedef struct _ubluepy_scanner_obj_t { + mp_obj_base_t base; +} ubluepy_scanner_obj_t; + +typedef struct _ubluepy_scan_entry_obj_t { + mp_obj_base_t base; +} ubluepy_scan_entry_obj_t; + typedef enum _ubluepy_prop_t { UBLUEPY_PROP_BROADCAST = 0x01, UBLUEPY_PROP_READ = 0x02, From 2f9fda1367602f338f0119931acd30f83485bbfe Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 14:21:27 +0100 Subject: [PATCH 488/809] nrf5: Adding ubluepy_scanner.c and ubluepy_scan_entry.c to Makefile source list. --- nrf5/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 4c8387cc94..976c5d7a2e 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -176,6 +176,8 @@ DRIVERS_SRC_C += $(addprefix modules/,\ ubluepy/ubluepy_delegate.c \ ubluepy/ubluepy_constants.c \ ubluepy/ubluepy_descriptor.c \ + ubluepy/ubluepy_scanner.c \ + ubluepy/ubluepy_scan_entry.c \ ) #ifeq ($(SD), ) From 90e88b2c4386ee1a4cf7e866a72c2726459d4f56 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 14:24:12 +0100 Subject: [PATCH 489/809] nrf5/bluetooth: Adding new configuration flag for s132 bluetooth stack, to enable/disable ubluepy central. Disabled by default. --- nrf5/bluetooth_conf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/bluetooth_conf.h b/nrf5/bluetooth_conf.h index 2e34c35106..e2bff0cbc0 100644 --- a/nrf5/bluetooth_conf.h +++ b/nrf5/bluetooth_conf.h @@ -23,6 +23,7 @@ #define MICROPY_PY_BLE_NUS (0) #define MICROPY_PY_UBLUEPY (1) #define MICROPY_PY_UBLUEPY_PERIPHERAL (1) +#define MICROPY_PY_UBLUEPY_CENTRAL (0) #else #error "SD not supported" From 242b40e917c353fea8d5136e8fc4ca7edc092d82 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 14:25:49 +0100 Subject: [PATCH 490/809] nrf5/modules/ubluepy: Activate Scanner and ScanEntry objects if MICROPY_PY_UBLUPY_CENTRAL is set. --- nrf5/modules/ubluepy/modubluepy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.c b/nrf5/modules/ubluepy/modubluepy.c index ea1b93c6ca..6835e9ef7c 100644 --- a/nrf5/modules/ubluepy/modubluepy.c +++ b/nrf5/modules/ubluepy/modubluepy.c @@ -34,19 +34,19 @@ extern const mp_obj_type_t ubluepy_uuid_type; extern const mp_obj_type_t ubluepy_characteristic_type; extern const mp_obj_type_t ubluepy_delegate_type; extern const mp_obj_type_t ubluepy_constants_type; +extern const mp_obj_type_t ubluepy_scanner_type; +extern const mp_obj_type_t ubluepy_scan_entry_type; STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy) }, #if MICROPY_PY_UBLUEPY_PERIPHERAL { MP_OBJ_NEW_QSTR(MP_QSTR_Peripheral), (mp_obj_t)&ubluepy_peripheral_type }, #endif -#if MICROPY_PY_UBLUEPY_CENTRAL +#if 0 // MICROPY_PY_UBLUEPY_CENTRAL { MP_OBJ_NEW_QSTR(MP_QSTR_Central), (mp_obj_t)&ubluepy_central_type }, #endif -#if MICROPY_PY_UBLUEPY_SCANNER - { MP_OBJ_NEW_QSTR(MP_QSTR_Scanner), (mp_obj_t)&ubluepy_scanner_type }, -#endif #if MICROPY_PY_UBLUEPY_CENTRAL + { MP_OBJ_NEW_QSTR(MP_QSTR_Scanner), (mp_obj_t)&ubluepy_scanner_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_ScanEntry), (mp_obj_t)&ubluepy_scan_entry_type }, #endif { MP_OBJ_NEW_QSTR(MP_QSTR_DefaultDelegate), (mp_obj_t)&ubluepy_delegate_type }, From 851705fc3a3713a9554138405d57987bccec3d92 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 14:27:09 +0100 Subject: [PATCH 491/809] nrf5/modules/ubluepy: Disable all functions central related functions in the Peripheral object for now, even if MICROPY_PY_UBLUEPY_CENTRAL is enabled. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index f66861d7f1..c6282cbb27 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -247,7 +247,7 @@ STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_setNotificationHandler), (mp_obj_t)(&ubluepy_peripheral_set_notif_handler_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_setConnectionHandler), (mp_obj_t)(&ubluepy_peripheral_set_conn_handler_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, -#if MICROPY_PY_UBLUEPY_CENTRAL +#if 0 // MICROPY_PY_UBLUEPY_CENTRAL { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getServiceByUUID), (mp_obj_t)(&ubluepy_peripheral_get_service_by_uuid_obj) }, From 7ea966d844741fd158a3b705e98a9ce3348e4a61 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 14:28:11 +0100 Subject: [PATCH 492/809] nrf5/modules/ubluepy: Adding print function to Scanner object. --- nrf5/modules/ubluepy/ubluepy_scanner.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index f1280b8311..5d56b3b779 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -34,11 +34,17 @@ #include "ble_drv.h" +STATIC void ubluepy_scanner_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + ubluepy_scanner_obj_t * self = (ubluepy_scanner_obj_t *)o; + (void)self; + mp_printf(print, "Scanner"); +} + const mp_obj_type_t ubluepy_scanner_type = { { &mp_type_type }, .name = MP_QSTR_Scanner, -#if 0 .print = ubluepy_scanner_print, +#if 0 .make_new = ubluepy_scanner_make_new, .locals_dict = (mp_obj_t)&ubluepy_scanner_locals_dict #endif From ee5ecac7cc3706587cd85db41d4fecf0a8213bd5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 14:40:56 +0100 Subject: [PATCH 493/809] nrf5/modules/ubluepy: Adding constructor function to scanner object. --- nrf5/modules/ubluepy/ubluepy_scanner.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index 5d56b3b779..849390376b 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -40,12 +40,29 @@ STATIC void ubluepy_scanner_print(const mp_print_t *print, mp_obj_t o, mp_print_ mp_printf(print, "Scanner"); } +STATIC mp_obj_t ubluepy_scanner_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + static const mp_arg_t allowed_args[] = { + + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + ubluepy_scanner_obj_t * s = m_new_obj(ubluepy_scanner_obj_t); + s->base.type = type; + +// s->scan_list = mp_obj_new_list(0, NULL); + + return MP_OBJ_FROM_PTR(s); +} + const mp_obj_type_t ubluepy_scanner_type = { { &mp_type_type }, .name = MP_QSTR_Scanner, .print = ubluepy_scanner_print, -#if 0 .make_new = ubluepy_scanner_make_new, +#if 0 .locals_dict = (mp_obj_t)&ubluepy_scanner_locals_dict #endif }; From 471d6a05da2cd794e6d09256fea71142ab781e5e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 19:50:38 +0100 Subject: [PATCH 494/809] nrf5/bluetooth: Adding empty scan_start and scan_stop function to the bluetooth driver. --- nrf5/bluetooth/ble_drv.c | 8 ++++++++ nrf5/bluetooth/ble_drv.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index b66f163cf3..32660cbdc9 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -661,6 +661,14 @@ void ble_drv_gatts_event_handler_set(mp_obj_t obj, ubluepy_gatts_evt_callback_t ubluepy_gatts_event_handler = evt_handler; } +void ble_drv_scan_start(void) { + +} + +void ble_drv_scan_stop(void) { + +} + static void ble_evt_handler(ble_evt_t * p_ble_evt) { // S132 event ranges. // Common 0x01 -> 0x0F diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 9fc80215ed..8e19293c72 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -60,4 +60,8 @@ void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uin void ble_drv_attr_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); +void ble_drv_scan_start(void); + +void ble_drv_scan_stop(void); + #endif // BLUETOOTH_LE_DRIVER_H__ From 89095f861f7502a2897b6ed31133ae8ea7103723 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 19:52:12 +0100 Subject: [PATCH 495/809] nrf5/modules/ubluepy: Adding scan method to the Scanner object. Adding locals dict table. --- nrf5/modules/ubluepy/ubluepy_scanner.c | 33 ++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index 849390376b..3bb0cbecdc 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -33,6 +33,7 @@ #if MICROPY_PY_UBLUEPY_CENTRAL #include "ble_drv.h" +#include "hal_time.h" STATIC void ubluepy_scanner_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_scanner_obj_t * self = (ubluepy_scanner_obj_t *)o; @@ -57,14 +58,42 @@ STATIC mp_obj_t ubluepy_scanner_make_new(const mp_obj_type_t *type, size_t n_arg return MP_OBJ_FROM_PTR(s); } +/// \method scan(timeout) +/// Scan for devices. Timeout is in milliseconds and will set the duration +/// of the scanning. +/// +STATIC mp_obj_t scanner_scan(mp_obj_t self_in, mp_obj_t timeout_in) { + ubluepy_scanner_obj_t * self = MP_OBJ_TO_PTR(self_in); + mp_int_t timeout = mp_obj_get_int(timeout_in); + + // start + ble_drv_scan_start(); + + // sleep + mp_hal_delay_ms(timeout); + + // stop + ble_drv_scan_stop(); + + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_scanner_scan_obj, scanner_scan); + +STATIC const mp_map_elem_t ubluepy_scanner_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_scan), (mp_obj_t)(&ubluepy_scanner_scan_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_scanner_locals_dict, ubluepy_scanner_locals_dict_table); + + const mp_obj_type_t ubluepy_scanner_type = { { &mp_type_type }, .name = MP_QSTR_Scanner, .print = ubluepy_scanner_print, .make_new = ubluepy_scanner_make_new, -#if 0 .locals_dict = (mp_obj_t)&ubluepy_scanner_locals_dict -#endif }; #endif // MICROPY_PY_UBLUEPY_CENTRAL From 739bf3a740f6cb948ed0ff0846da3b5dab1083f1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 20:18:37 +0100 Subject: [PATCH 496/809] nrf5/bluetooth: Adding some implementation to scan_start function. --- nrf5/bluetooth/ble_drv.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 32660cbdc9..d25920026f 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -36,7 +36,7 @@ #include "ble.h" // sd_ble_uuid_encode -#define BLE_DRIVER_VERBOSE 0 +#define BLE_DRIVER_VERBOSE 1 #if BLE_DRIVER_VERBOSE #define BLE_DRIVER_LOG printf #else @@ -661,14 +661,31 @@ void ble_drv_gatts_event_handler_set(mp_obj_t obj, ubluepy_gatts_evt_callback_t ubluepy_gatts_event_handler = evt_handler; } -void ble_drv_scan_start(void) { +#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) +void ble_drv_scan_start(void) { + ble_gap_scan_params_t scan_params; + scan_params.active = 1; + scan_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS); + scan_params.window = MSEC_TO_UNITS(100, UNIT_0_625_MS); + scan_params.timeout = 0; // Infinite + +#if (BLUETOOTH_SD == 130) + scan_params.selective = 0, + scan_params.p_whitelist = NULL, +#else + scan_params.use_whitelist = 0, +#endif + + sd_ble_gap_scan_start(&scan_params); } void ble_drv_scan_stop(void) { - + sd_ble_gap_scan_stop(); } +#endif + static void ble_evt_handler(ble_evt_t * p_ble_evt) { // S132 event ranges. // Common 0x01 -> 0x0F @@ -735,6 +752,12 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { NULL, NULL); break; +#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) + case BLE_GAP_EVT_ADV_REPORT: + BLE_DRIVER_LOG("BLE EVT ADV REPORT\n"); + break; +#endif + default: BLE_DRIVER_LOG(">>> unhandled evt: 0x" HEX2_FMT "\n", p_ble_evt->header.evt_id); break; From caf242a5aeaf0a0ad0b8d8207bbfca2c765e2289 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 20:20:15 +0100 Subject: [PATCH 497/809] nrf5/bluetooth: Correcting indention. --- nrf5/bluetooth/ble_drv.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index d25920026f..5792b69f12 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -745,17 +745,17 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { break; case BLE_GAP_EVT_SEC_PARAMS_REQUEST: - BLE_DRIVER_LOG("BLE EVT SEC PARAMS REQUEST\n"); - // pairing not supported - (void)sd_ble_gap_sec_params_reply(p_ble_evt->evt.gatts_evt.conn_handle, - BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP, - NULL, NULL); - break; + BLE_DRIVER_LOG("BLE EVT SEC PARAMS REQUEST\n"); + // pairing not supported + (void)sd_ble_gap_sec_params_reply(p_ble_evt->evt.gatts_evt.conn_handle, + BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP, + NULL, NULL); + break; #if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) case BLE_GAP_EVT_ADV_REPORT: - BLE_DRIVER_LOG("BLE EVT ADV REPORT\n"); - break; + BLE_DRIVER_LOG("BLE EVT ADV REPORT\n"); + break; #endif default: From 9aa3df795526933bd1b27a1cc81fd25913f8817e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 22:45:02 +0100 Subject: [PATCH 498/809] nrf5: Removing ubluepy scanner and scan entry from Makefile source list until nrf52 central issues has been resolved. --- nrf5/Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 976c5d7a2e..4c8387cc94 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -176,8 +176,6 @@ DRIVERS_SRC_C += $(addprefix modules/,\ ubluepy/ubluepy_delegate.c \ ubluepy/ubluepy_constants.c \ ubluepy/ubluepy_descriptor.c \ - ubluepy/ubluepy_scanner.c \ - ubluepy/ubluepy_scan_entry.c \ ) #ifeq ($(SD), ) From 5580ac82002b3918311fc1d2e15fc1fdb8369f00 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 22:46:40 +0100 Subject: [PATCH 499/809] nrf5/bluetooth: Adding more implementation in scan start function. However, commented out for time beeing, as there is some memory issues when activating central. --- nrf5/bluetooth/ble_drv.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 5792b69f12..7ee2037b18 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -36,7 +36,7 @@ #include "ble.h" // sd_ble_uuid_encode -#define BLE_DRIVER_VERBOSE 1 +#define BLE_DRIVER_VERBOSE 0 #if BLE_DRIVER_VERBOSE #define BLE_DRIVER_LOG printf #else @@ -664,6 +664,9 @@ void ble_drv_gatts_event_handler_set(mp_obj_t obj, ubluepy_gatts_evt_callback_t #if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) void ble_drv_scan_start(void) { +#if 0 + SD_TEST_OR_ENABLE(); + ble_gap_scan_params_t scan_params; scan_params.active = 1; scan_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS); @@ -671,13 +674,18 @@ void ble_drv_scan_start(void) { scan_params.timeout = 0; // Infinite #if (BLUETOOTH_SD == 130) - scan_params.selective = 0, - scan_params.p_whitelist = NULL, + scan_params.selective = 0; + scan_params.p_whitelist = NULL; #else - scan_params.use_whitelist = 0, + scan_params.use_whitelist = 0; #endif - sd_ble_gap_scan_start(&scan_params); + uint32_t err_code; + if ((err_code = sd_ble_gap_scan_start(&scan_params)) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not start scanning. status: 0x" HEX2_FMT, (uint16_t)err_code)); + } +#endif // 0 } void ble_drv_scan_stop(void) { From a01a3734f81c2cbc1bebe517c8a17929248c07f6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 23:20:44 +0100 Subject: [PATCH 500/809] nrf5/boards: Adjust heap end after increased .data usage in nrf52832 s132 linker script. --- nrf5/boards/nrf52832_512k_64k_s132.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/nrf52832_512k_64k_s132.ld b/nrf5/boards/nrf52832_512k_64k_s132.ld index 629ed12c9c..65c108192b 100644 --- a/nrf5/boards/nrf52832_512k_64k_s132.ld +++ b/nrf5/boards/nrf52832_512k_64k_s132.ld @@ -22,6 +22,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20005000; /* tunable */ +_heap_end = 0x20006000; /* tunable */ INCLUDE "boards/common.ld" From 6ea3f3c69baa6d8d2143c2b289233daaa572f563 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 23:23:37 +0100 Subject: [PATCH 501/809] nrf5/bluetooth: Enable implementation in scan start function in the bluetooth stack driver. --- nrf5/bluetooth/ble_drv.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 7ee2037b18..31e5c2d40c 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -36,7 +36,7 @@ #include "ble.h" // sd_ble_uuid_encode -#define BLE_DRIVER_VERBOSE 0 +#define BLE_DRIVER_VERBOSE 1 #if BLE_DRIVER_VERBOSE #define BLE_DRIVER_LOG printf #else @@ -664,7 +664,6 @@ void ble_drv_gatts_event_handler_set(mp_obj_t obj, ubluepy_gatts_evt_callback_t #if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) void ble_drv_scan_start(void) { -#if 0 SD_TEST_OR_ENABLE(); ble_gap_scan_params_t scan_params; @@ -685,7 +684,6 @@ void ble_drv_scan_start(void) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not start scanning. status: 0x" HEX2_FMT, (uint16_t)err_code)); } -#endif // 0 } void ble_drv_scan_stop(void) { From c8127ef33728852bb8a06aad3ca06cc024965071 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 23:24:20 +0100 Subject: [PATCH 502/809] nrf5: Add back ublupy scanner and scan entry source files in Makefile. --- nrf5/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 4c8387cc94..976c5d7a2e 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -176,6 +176,8 @@ DRIVERS_SRC_C += $(addprefix modules/,\ ubluepy/ubluepy_delegate.c \ ubluepy/ubluepy_constants.c \ ubluepy/ubluepy_descriptor.c \ + ubluepy/ubluepy_scanner.c \ + ubluepy/ubluepy_scan_entry.c \ ) #ifeq ($(SD), ) From 51c739f64a83bc88ac06d18ce3c546dc6b3023cd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 12 Mar 2017 23:32:33 +0100 Subject: [PATCH 503/809] nrf5/bluetooth: Turn off bluetooth printf logging. --- nrf5/bluetooth/ble_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 31e5c2d40c..c70a384053 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -36,7 +36,7 @@ #include "ble.h" // sd_ble_uuid_encode -#define BLE_DRIVER_VERBOSE 1 +#define BLE_DRIVER_VERBOSE 0 #if BLE_DRIVER_VERBOSE #define BLE_DRIVER_LOG printf #else From 5fc6a9d9a248121a1de14b5f290a3cccd288707e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 13 Mar 2017 17:56:39 +0100 Subject: [PATCH 504/809] nrf5/modules/machine: Cleaning up uart a bit more. Removing unused any() method, and aligning print and local dict names to use machine_uart prefix. --- nrf5/modules/machine/uart.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/nrf5/modules/machine/uart.c b/nrf5/modules/machine/uart.c index 5714b8b4c5..e8533e455b 100644 --- a/nrf5/modules/machine/uart.c +++ b/nrf5/modules/machine/uart.c @@ -137,7 +137,7 @@ void uart_tx_strn_cooked(machine_hard_uart_obj_t *uart_obj, const char *str, uin /******************************************************************************/ /* Micro Python bindings */ -STATIC void pyb_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { +STATIC void machine_hard_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { } @@ -283,18 +283,6 @@ STATIC mp_obj_t machine_hard_uart_make_new(const mp_obj_type_t *type, size_t n_a return MP_OBJ_FROM_PTR(self); } -/// \method any() -/// Return `True` if any characters waiting, else `False`. -STATIC mp_obj_t pyb_uart_any(mp_obj_t self_in) { - machine_hard_uart_obj_t *self = self_in; - if (uart_rx_any(self)) { - return mp_const_true; - } else { - return mp_const_false; - } -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_any_obj, pyb_uart_any); - /// \method writechar(char) /// Write a single character on the bus. `char` is an integer to write. /// Return value: `None`. @@ -343,7 +331,7 @@ STATIC mp_obj_t machine_hard_uart_sendbreak(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_hard_uart_sendbreak_obj, machine_hard_uart_sendbreak); -STATIC const mp_map_elem_t pyb_uart_locals_dict_table[] = { +STATIC const mp_map_elem_t machine_hard_uart_locals_dict_table[] = { // instance methods /// \method read([nbytes]) { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&mp_stream_read_obj }, @@ -363,7 +351,7 @@ STATIC const mp_map_elem_t pyb_uart_locals_dict_table[] = { */ }; -STATIC MP_DEFINE_CONST_DICT(pyb_uart_locals_dict, pyb_uart_locals_dict_table); +STATIC MP_DEFINE_CONST_DICT(machine_hard_uart_locals_dict, machine_hard_uart_locals_dict_table); STATIC mp_uint_t machine_hard_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) { machine_hard_uart_obj_t *self = self_in; @@ -437,11 +425,11 @@ STATIC const mp_stream_p_t uart_stream_p = { const mp_obj_type_t machine_hard_uart_type = { { &mp_type_type }, .name = MP_QSTR_UART, - .print = pyb_uart_print, + .print = machine_hard_uart_print, .make_new = machine_hard_uart_make_new, .getiter = mp_identity_getiter, .iternext = mp_stream_unbuffered_iter, .protocol = &uart_stream_p, - .locals_dict = (mp_obj_t)&pyb_uart_locals_dict, + .locals_dict = (mp_obj_t)&machine_hard_uart_locals_dict, }; From ada69c40c6d574dd978416acabb9183c1c672b22 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 07:57:20 +0100 Subject: [PATCH 505/809] nrf5/modules/ubluepy: Adding adv_reports member to scanner object, to hold the result of scan. --- nrf5/modules/ubluepy/modubluepy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index c5f8440e60..d31188d6fd 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -147,6 +147,7 @@ typedef struct _ubluepy_advertise_data_t { typedef struct _ubluepy_scanner_obj_t { mp_obj_base_t base; + mp_obj_t adv_reports; } ubluepy_scanner_obj_t; typedef struct _ubluepy_scan_entry_obj_t { @@ -170,5 +171,6 @@ typedef enum _ubluepy_attr_t { typedef void (*ubluepy_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); typedef void (*ubluepy_gatts_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); +typedef void (*ubluepy_adv_evt_callback_t)(mp_obj_t self, uint16_t event_id, ble_drv_adv_data_t * data); #endif // UBLUEPY_H__ From 6fc806b313277f807f338a19077418bc918b4de2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 07:59:29 +0100 Subject: [PATCH 506/809] nrf5/bluetooth: adding adv report data structure to pass to ubluepy upon adv report event. Adding new api for setting callack where to handle advertisment events in ubluepy. --- nrf5/bluetooth/ble_drv.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 8e19293c72..c764b21a69 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -32,6 +32,14 @@ #include "modubluepy.h" +typedef struct { + uint8_t * p_peer_addr; + bool is_scan_resp; + int8_t rssi; + uint8_t data_len; + uint8_t * p_data; +} ble_drv_adv_data_t; + uint32_t ble_drv_stack_enable(void); void ble_drv_stack_disable(void); @@ -64,4 +72,6 @@ void ble_drv_scan_start(void); void ble_drv_scan_stop(void); +void ble_drv_adv_report_handler_set(mp_obj_t obj, ubluepy_adv_evt_callback_t evt_handler); + #endif // BLUETOOTH_LE_DRIVER_H__ From 9b0d893b4d4eb19a67736322cd826e11c218fee7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 08:04:24 +0100 Subject: [PATCH 507/809] nrf5/bluetooth: Adding handling of advertisment reports in bluetooth driver and issue callback to ubluepy. A bit ugly implmentation and has to be re-worked. --- nrf5/bluetooth/ble_drv.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index c70a384053..55fc4662b3 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -74,11 +74,13 @@ if (ble_drv_stack_enabled() == 0) { \ static volatile bool m_adv_in_progress; static volatile bool m_tx_in_progress; -static ubluepy_gap_evt_callback_t ubluepy_gap_event_handler; -static ubluepy_gatts_evt_callback_t ubluepy_gatts_event_handler; +static ubluepy_gap_evt_callback_t ubluepy_gap_event_handler; +static ubluepy_adv_evt_callback_t ubluepy_adv_event_handler; +static ubluepy_gatts_evt_callback_t ubluepy_gatts_event_handler; -static mp_obj_t mp_gap_observer; -static mp_obj_t mp_gatts_observer; +static mp_obj_t mp_gap_observer; +static mp_obj_t mp_adv_observer; +static mp_obj_t mp_gatts_observer; #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -661,6 +663,11 @@ void ble_drv_gatts_event_handler_set(mp_obj_t obj, ubluepy_gatts_evt_callback_t ubluepy_gatts_event_handler = evt_handler; } +void ble_drv_adv_report_handler_set(mp_obj_t obj, ubluepy_adv_evt_callback_t evt_handler) { + mp_adv_observer = obj; + ubluepy_adv_event_handler = evt_handler; +} + #if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) void ble_drv_scan_start(void) { @@ -761,6 +768,18 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { #if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) case BLE_GAP_EVT_ADV_REPORT: BLE_DRIVER_LOG("BLE EVT ADV REPORT\n"); + ble_drv_adv_data_t adv_data = { + .p_peer_addr = p_ble_evt->evt.gap_evt.params.adv_report.peer_addr.addr, + .is_scan_resp = p_ble_evt->evt.gap_evt.params.adv_report.scan_rsp, + .rssi = p_ble_evt->evt.gap_evt.params.adv_report.rssi, + .data_len = p_ble_evt->evt.gap_evt.params.adv_report.dlen, + .p_data = p_ble_evt->evt.gap_evt.params.adv_report.data + }; + + // TODO: Fix unsafe callback to possible undefined callback... + ubluepy_adv_event_handler(mp_adv_observer, + p_ble_evt->header.evt_id, + &adv_data); break; #endif From e028eda0bc599248d2d2bddebecc76cfbd457bda Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 08:05:54 +0100 Subject: [PATCH 508/809] nrf5/modules/ubluepy: Extracting advertisment reports and adding some data to list before returning it in scan() method. --- nrf5/modules/ubluepy/ubluepy_scanner.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index 3bb0cbecdc..8b3545bb57 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -35,6 +35,14 @@ #include "ble_drv.h" #include "hal_time.h" +STATIC void adv_event_handler(mp_obj_t self_in, uint16_t event_id, ble_drv_adv_data_t * data) { + ubluepy_scanner_obj_t *self = MP_OBJ_TO_PTR(self_in); + + mp_obj_list_append(self->adv_reports, MP_OBJ_NEW_SMALL_INT(event_id)); // TODO: Swap out with ScanEntry + + (void)self; +} + STATIC void ubluepy_scanner_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_scanner_obj_t * self = (ubluepy_scanner_obj_t *)o; (void)self; @@ -53,7 +61,7 @@ STATIC mp_obj_t ubluepy_scanner_make_new(const mp_obj_type_t *type, size_t n_arg ubluepy_scanner_obj_t * s = m_new_obj(ubluepy_scanner_obj_t); s->base.type = type; -// s->scan_list = mp_obj_new_list(0, NULL); + s->adv_reports = mp_obj_new_list(0, NULL); return MP_OBJ_FROM_PTR(s); } @@ -66,6 +74,8 @@ STATIC mp_obj_t scanner_scan(mp_obj_t self_in, mp_obj_t timeout_in) { ubluepy_scanner_obj_t * self = MP_OBJ_TO_PTR(self_in); mp_int_t timeout = mp_obj_get_int(timeout_in); + ble_drv_adv_report_handler_set(MP_OBJ_FROM_PTR(self), adv_event_handler); + // start ble_drv_scan_start(); @@ -75,9 +85,7 @@ STATIC mp_obj_t scanner_scan(mp_obj_t self_in, mp_obj_t timeout_in) { // stop ble_drv_scan_stop(); - (void)self; - - return mp_const_none; + return self->adv_reports; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_scanner_scan_obj, scanner_scan); From c066344a149a76c7e2f1d66b467653ebb3179884 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 08:13:32 +0100 Subject: [PATCH 509/809] nrf5/bluetooth: Moving callback definitions to bluetooth driver header. Refactoring bluetooth driver, setting new names on callback functions and updating api to use new callback function name prefix. --- nrf5/bluetooth/ble_drv.c | 28 ++++++++++++++-------------- nrf5/bluetooth/ble_drv.h | 10 +++++++--- nrf5/modules/ubluepy/modubluepy.h | 4 ---- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 55fc4662b3..43aa4fc452 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -74,9 +74,9 @@ if (ble_drv_stack_enabled() == 0) { \ static volatile bool m_adv_in_progress; static volatile bool m_tx_in_progress; -static ubluepy_gap_evt_callback_t ubluepy_gap_event_handler; -static ubluepy_adv_evt_callback_t ubluepy_adv_event_handler; -static ubluepy_gatts_evt_callback_t ubluepy_gatts_event_handler; +static ble_drv_gap_evt_callback_t gap_event_handler; +static ble_drv_adv_evt_callback_t adv_event_handler; +static ble_drv_gatts_evt_callback_t gatts_event_handler; static mp_obj_t mp_gap_observer; static mp_obj_t mp_adv_observer; @@ -653,19 +653,19 @@ void ble_drv_attr_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, ui } } -void ble_drv_gap_event_handler_set(mp_obj_t obj, ubluepy_gap_evt_callback_t evt_handler) { +void ble_drv_gap_event_handler_set(mp_obj_t obj, ble_drv_gap_evt_callback_t evt_handler) { mp_gap_observer = obj; - ubluepy_gap_event_handler = evt_handler; + gap_event_handler = evt_handler; } -void ble_drv_gatts_event_handler_set(mp_obj_t obj, ubluepy_gatts_evt_callback_t evt_handler) { +void ble_drv_gatts_event_handler_set(mp_obj_t obj, ble_drv_gatts_evt_callback_t evt_handler) { mp_gatts_observer = obj; - ubluepy_gatts_event_handler = evt_handler; + gatts_event_handler = evt_handler; } -void ble_drv_adv_report_handler_set(mp_obj_t obj, ubluepy_adv_evt_callback_t evt_handler) { +void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt_handler) { mp_adv_observer = obj; - ubluepy_adv_event_handler = evt_handler; + adv_event_handler = evt_handler; } #if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) @@ -710,7 +710,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GAP_EVT_CONNECTED: BLE_DRIVER_LOG("GAP CONNECT\n"); m_adv_in_progress = false; - ubluepy_gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); + gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); ble_gap_conn_params_t conn_params; (void)sd_ble_gap_ppcp_get(&conn_params); @@ -719,11 +719,11 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GAP_EVT_DISCONNECTED: BLE_DRIVER_LOG("GAP DISCONNECT\n"); - ubluepy_gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); + gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); break; case BLE_GATTS_EVT_HVC: - ubluepy_gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gatts_evt.params.hvc.handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); + gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gatts_evt.params.hvc.handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL); break; case BLE_GATTS_EVT_WRITE: @@ -733,7 +733,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { uint16_t data_len = p_ble_evt->evt.gatts_evt.params.write.len; uint8_t * p_data = &p_ble_evt->evt.gatts_evt.params.write.data[0]; - ubluepy_gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, handle, data_len, p_data); + gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, handle, data_len, p_data); break; case BLE_GAP_EVT_CONN_PARAM_UPDATE: @@ -777,7 +777,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { }; // TODO: Fix unsafe callback to possible undefined callback... - ubluepy_adv_event_handler(mp_adv_observer, + adv_event_handler(mp_adv_observer, p_ble_evt->header.evt_id, &adv_data); break; diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index c764b21a69..37b3a86a58 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -40,6 +40,10 @@ typedef struct { uint8_t * p_data; } ble_drv_adv_data_t; +typedef void (*ble_drv_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); +typedef void (*ble_drv_gatts_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); +typedef void (*ble_drv_adv_evt_callback_t)(mp_obj_t self, uint16_t event_id, ble_drv_adv_data_t * data); + uint32_t ble_drv_stack_enable(void); void ble_drv_stack_disable(void); @@ -58,9 +62,9 @@ bool ble_drv_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj); bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params); -void ble_drv_gap_event_handler_set(mp_obj_t obs, ubluepy_gap_evt_callback_t evt_handler); +void ble_drv_gap_event_handler_set(mp_obj_t obs, ble_drv_gap_evt_callback_t evt_handler); -void ble_drv_gatts_event_handler_set(mp_obj_t obj, ubluepy_gatts_evt_callback_t evt_handler); +void ble_drv_gatts_event_handler_set(mp_obj_t obj, ble_drv_gatts_evt_callback_t evt_handler); void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); @@ -72,6 +76,6 @@ void ble_drv_scan_start(void); void ble_drv_scan_stop(void); -void ble_drv_adv_report_handler_set(mp_obj_t obj, ubluepy_adv_evt_callback_t evt_handler); +void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt_handler); #endif // BLUETOOTH_LE_DRIVER_H__ diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index d31188d6fd..724cc48552 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -169,8 +169,4 @@ typedef enum _ubluepy_attr_t { UBLUEPY_ATTR_SCCD = 0x02, } ubluepy_attr_t; -typedef void (*ubluepy_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); -typedef void (*ubluepy_gatts_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); -typedef void (*ubluepy_adv_evt_callback_t)(mp_obj_t self, uint16_t event_id, ble_drv_adv_data_t * data); - #endif // UBLUEPY_H__ From 4a97cfe3ea8464f3487592eed2b76872b7879860 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 08:20:16 +0100 Subject: [PATCH 510/809] nrf5/modules/ubluepy: Populating ubluepy_scan_entry_obj_t with members that are interesting to keep for the ScanEntry object. --- nrf5/modules/ubluepy/modubluepy.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 724cc48552..83c02682b7 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -152,6 +152,11 @@ typedef struct _ubluepy_scanner_obj_t { typedef struct _ubluepy_scan_entry_obj_t { mp_obj_base_t base; + uint8_t addr[6]; + uint8_t addr_type; + bool connectable; + uint8_t rssi; + mp_obj_t data; } ubluepy_scan_entry_obj_t; typedef enum _ubluepy_prop_t { From 9a20d9ca91b721733d5e3496ee8b63aa79fb11bf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 21:27:29 +0100 Subject: [PATCH 511/809] nrf5/modules/ubluepy: Adding print function to scan_entry object. --- nrf5/modules/ubluepy/ubluepy_scan_entry.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scan_entry.c b/nrf5/modules/ubluepy/ubluepy_scan_entry.c index 48328e1921..f614d4f049 100644 --- a/nrf5/modules/ubluepy/ubluepy_scan_entry.c +++ b/nrf5/modules/ubluepy/ubluepy_scan_entry.c @@ -34,11 +34,17 @@ #include "ble_drv.h" +STATIC void ubluepy_scan_entry_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + ubluepy_scan_entry_obj_t * self = (ubluepy_scan_entry_obj_t *)o; + (void)self; + mp_printf(print, "ScanEntry"); +} + const mp_obj_type_t ubluepy_scan_entry_type = { { &mp_type_type }, .name = MP_QSTR_ScanEntry, -#if 0 .print = ubluepy_scan_entry_print, +#if 0 .make_new = ubluepy_scan_entry_make_new, .locals_dict = (mp_obj_t)&ubluepy_scan_entry_locals_dict #endif From a44439011507249cf69e9efb44acbaec06f9f4b8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 21:28:42 +0100 Subject: [PATCH 512/809] nrf5/modules/ubluepy: Create new adv report list for each individual scan. Create a new ScanEntry object instance on each advertisment event recieved and append this to the current adv_report list. --- nrf5/modules/ubluepy/ubluepy_scanner.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index 8b3545bb57..393d1f1f00 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -38,7 +38,10 @@ STATIC void adv_event_handler(mp_obj_t self_in, uint16_t event_id, ble_drv_adv_data_t * data) { ubluepy_scanner_obj_t *self = MP_OBJ_TO_PTR(self_in); - mp_obj_list_append(self->adv_reports, MP_OBJ_NEW_SMALL_INT(event_id)); // TODO: Swap out with ScanEntry + ubluepy_scan_entry_obj_t * item = m_new_obj(ubluepy_scan_entry_obj_t); + item->base.type = &ubluepy_scan_entry_type; + + mp_obj_list_append(self->adv_reports, item); (void)self; } @@ -61,8 +64,6 @@ STATIC mp_obj_t ubluepy_scanner_make_new(const mp_obj_type_t *type, size_t n_arg ubluepy_scanner_obj_t * s = m_new_obj(ubluepy_scanner_obj_t); s->base.type = type; - s->adv_reports = mp_obj_new_list(0, NULL); - return MP_OBJ_FROM_PTR(s); } @@ -74,6 +75,8 @@ STATIC mp_obj_t scanner_scan(mp_obj_t self_in, mp_obj_t timeout_in) { ubluepy_scanner_obj_t * self = MP_OBJ_TO_PTR(self_in); mp_int_t timeout = mp_obj_get_int(timeout_in); + self->adv_reports = mp_obj_new_list(0, NULL); + ble_drv_adv_report_handler_set(MP_OBJ_FROM_PTR(self), adv_event_handler); // start From 08883c619a676eb6a1019df7ed8b8864f6546cc0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 22:12:33 +0100 Subject: [PATCH 513/809] nrf5/modules/ubluepy: Extending print of ScanEntry object to also include the bluetooth le address. --- nrf5/modules/ubluepy/ubluepy_scan_entry.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scan_entry.c b/nrf5/modules/ubluepy/ubluepy_scan_entry.c index f614d4f049..c6b957de3b 100644 --- a/nrf5/modules/ubluepy/ubluepy_scan_entry.c +++ b/nrf5/modules/ubluepy/ubluepy_scan_entry.c @@ -37,7 +37,10 @@ STATIC void ubluepy_scan_entry_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_scan_entry_obj_t * self = (ubluepy_scan_entry_obj_t *)o; (void)self; - mp_printf(print, "ScanEntry"); + mp_printf(print, "ScanEntry(addr: "HEX2_FMT":"HEX2_FMT":"HEX2_FMT":" \ + HEX2_FMT":"HEX2_FMT":"HEX2_FMT")", + self->addr[0], self->addr[1], self->addr[2], + self->addr[3], self->addr[4], self->addr[5]); } const mp_obj_type_t ubluepy_scan_entry_type = { From 445b45ee13d541295785436eee5ce2e532af8009 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 22:14:05 +0100 Subject: [PATCH 514/809] nrf5/modules/ubluepy: Swapping address bytes when copying bluetooth address over to ScanEntry object during advertisment scan report event. --- nrf5/modules/ubluepy/ubluepy_scanner.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index 393d1f1f00..0d80bf81b7 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -41,9 +41,14 @@ STATIC void adv_event_handler(mp_obj_t self_in, uint16_t event_id, ble_drv_adv_d ubluepy_scan_entry_obj_t * item = m_new_obj(ubluepy_scan_entry_obj_t); item->base.type = &ubluepy_scan_entry_type; - mp_obj_list_append(self->adv_reports, item); + item->addr[0] = data->p_peer_addr[5]; + item->addr[1] = data->p_peer_addr[4]; + item->addr[2] = data->p_peer_addr[3]; + item->addr[3] = data->p_peer_addr[2]; + item->addr[4] = data->p_peer_addr[1]; + item->addr[5] = data->p_peer_addr[0]; - (void)self; + mp_obj_list_append(self->adv_reports, item); } STATIC void ubluepy_scanner_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { From cbfba08ae77f3688a412e19277263af19765745b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 23:12:24 +0100 Subject: [PATCH 515/809] nrf5/bluetooth: Adding address type to bluetooth stack driver advertisment structure, and fill the member when advertisment report is received. --- nrf5/bluetooth/ble_drv.c | 3 ++- nrf5/bluetooth/ble_drv.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 43aa4fc452..bdfb346572 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -773,7 +773,8 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { .is_scan_resp = p_ble_evt->evt.gap_evt.params.adv_report.scan_rsp, .rssi = p_ble_evt->evt.gap_evt.params.adv_report.rssi, .data_len = p_ble_evt->evt.gap_evt.params.adv_report.dlen, - .p_data = p_ble_evt->evt.gap_evt.params.adv_report.data + .p_data = p_ble_evt->evt.gap_evt.params.adv_report.data, + .type = p_ble_evt->evt.gap_evt.params.adv_report.type }; // TODO: Fix unsafe callback to possible undefined callback... diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 37b3a86a58..a7d831911a 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -38,6 +38,7 @@ typedef struct { int8_t rssi; uint8_t data_len; uint8_t * p_data; + uint8_t type; } ble_drv_adv_data_t; typedef void (*ble_drv_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); From 609a174f8df7fe8e71876ebd550c73ede090e3c6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 23:13:13 +0100 Subject: [PATCH 516/809] nrf5/modules/ubluepy: Copy address type and rssi to the ScanEntry object upon reception of an advertisment report callback. --- nrf5/modules/ubluepy/ubluepy_scanner.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index 0d80bf81b7..e9faf2fe14 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -48,6 +48,9 @@ STATIC void adv_event_handler(mp_obj_t self_in, uint16_t event_id, ble_drv_adv_d item->addr[4] = data->p_peer_addr[1]; item->addr[5] = data->p_peer_addr[0]; + item->addr_type = data->type; + item->rssi = data->rssi; + mp_obj_list_append(self->adv_reports, item); } From 442e46f4be82459e9c659787c7322d7cb574b3f2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 23:14:31 +0100 Subject: [PATCH 517/809] nrf5/modules/ubluepy: Adding attribute to ScanEntry object for getting address (returning bytearray), type (returning int) and rssi (returning int). --- nrf5/modules/ubluepy/ubluepy_scan_entry.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scan_entry.c b/nrf5/modules/ubluepy/ubluepy_scan_entry.c index c6b957de3b..1149006934 100644 --- a/nrf5/modules/ubluepy/ubluepy_scan_entry.c +++ b/nrf5/modules/ubluepy/ubluepy_scan_entry.c @@ -43,14 +43,32 @@ STATIC void ubluepy_scan_entry_print(const mp_print_t *print, mp_obj_t o, mp_pri self->addr[3], self->addr[4], self->addr[5]); } +STATIC void ubluepy_scan_entry_attr(mp_obj_t self_in, qstr attr, mp_obj_t *dest) { + if (dest[0] != MP_OBJ_NULL) { + // not load attribute + return; + } + ubluepy_scan_entry_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (attr == MP_QSTR_addr) { + dest[0] = mp_obj_new_bytearray_by_ref(6, self->addr); + } else if (attr == MP_QSTR_addr_type) { + dest[0] = mp_obj_new_int(self->addr_type); + } else if (attr == MP_QSTR_rssi) { + dest[0] = mp_obj_new_int(self->rssi); + } + +} + + const mp_obj_type_t ubluepy_scan_entry_type = { { &mp_type_type }, .name = MP_QSTR_ScanEntry, .print = ubluepy_scan_entry_print, #if 0 .make_new = ubluepy_scan_entry_make_new, - .locals_dict = (mp_obj_t)&ubluepy_scan_entry_locals_dict + .locals_dict = (mp_obj_t)&ubluepy_scan_entry_locals_dict, #endif + .attr = ubluepy_scan_entry_attr }; #endif // MICROPY_PY_UBLUEPY_CENTRAL From 34689722991cb76fda85766a46975e74222c14d3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 14 Mar 2017 23:18:51 +0100 Subject: [PATCH 518/809] nrf5/modules/ubluepy: Correcting rssi member in scan_entry object to be int instead of uint. --- nrf5/modules/ubluepy/modubluepy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 83c02682b7..d9d2abfbc9 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -155,7 +155,7 @@ typedef struct _ubluepy_scan_entry_obj_t { uint8_t addr[6]; uint8_t addr_type; bool connectable; - uint8_t rssi; + int8_t rssi; mp_obj_t data; } ubluepy_scan_entry_obj_t; From 327754a953a87cd0efb6c0749025189faa5a7111 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 16 Mar 2017 22:46:26 +0100 Subject: [PATCH 519/809] nrf5/bluetooth: capture address type in addition to advertisment type in bluetooth advertisment reports. --- nrf5/bluetooth/ble_drv.c | 5 +++-- nrf5/bluetooth/ble_drv.h | 3 ++- nrf5/modules/ubluepy/ubluepy_scanner.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index bdfb346572..071fd8d9ae 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -36,7 +36,7 @@ #include "ble.h" // sd_ble_uuid_encode -#define BLE_DRIVER_VERBOSE 0 +#define BLE_DRIVER_VERBOSE 1 #if BLE_DRIVER_VERBOSE #define BLE_DRIVER_LOG printf #else @@ -770,11 +770,12 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { BLE_DRIVER_LOG("BLE EVT ADV REPORT\n"); ble_drv_adv_data_t adv_data = { .p_peer_addr = p_ble_evt->evt.gap_evt.params.adv_report.peer_addr.addr, + .addr_type = p_ble_evt->evt.gap_evt.params.adv_report.peer_addr.addr_type, .is_scan_resp = p_ble_evt->evt.gap_evt.params.adv_report.scan_rsp, .rssi = p_ble_evt->evt.gap_evt.params.adv_report.rssi, .data_len = p_ble_evt->evt.gap_evt.params.adv_report.dlen, .p_data = p_ble_evt->evt.gap_evt.params.adv_report.data, - .type = p_ble_evt->evt.gap_evt.params.adv_report.type + .adv_type = p_ble_evt->evt.gap_evt.params.adv_report.type }; // TODO: Fix unsafe callback to possible undefined callback... diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index a7d831911a..cf70fe1e34 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -34,11 +34,12 @@ typedef struct { uint8_t * p_peer_addr; + uint8_t addr_type; bool is_scan_resp; int8_t rssi; uint8_t data_len; uint8_t * p_data; - uint8_t type; + uint8_t adv_type; } ble_drv_adv_data_t; typedef void (*ble_drv_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index e9faf2fe14..39e25b9edc 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -48,7 +48,7 @@ STATIC void adv_event_handler(mp_obj_t self_in, uint16_t event_id, ble_drv_adv_d item->addr[4] = data->p_peer_addr[1]; item->addr[5] = data->p_peer_addr[0]; - item->addr_type = data->type; + item->addr_type = data->addr_type; item->rssi = data->rssi; mp_obj_list_append(self->adv_reports, item); From 8a884de7b9fdfde909127b74f8c02fd6c315adda Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 22 Mar 2017 23:18:41 +0100 Subject: [PATCH 520/809] nrf5/modules/ubluepy: Return BLE peer address as string instead of bytearray. Updated struct in modubluepy.h to use a mp_obj_t to hold a string instead of a fixed 6-byte array. Stripped down ScanEntry print out to only contain class name, peer address available through addr attribute. --- nrf5/modules/ubluepy/modubluepy.h | 2 +- nrf5/modules/ubluepy/ubluepy_scan_entry.c | 7 ++----- nrf5/modules/ubluepy/ubluepy_scanner.c | 17 +++++++++++------ 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index d9d2abfbc9..a14110ef41 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -152,7 +152,7 @@ typedef struct _ubluepy_scanner_obj_t { typedef struct _ubluepy_scan_entry_obj_t { mp_obj_base_t base; - uint8_t addr[6]; + mp_obj_t addr; uint8_t addr_type; bool connectable; int8_t rssi; diff --git a/nrf5/modules/ubluepy/ubluepy_scan_entry.c b/nrf5/modules/ubluepy/ubluepy_scan_entry.c index 1149006934..b7d54523d6 100644 --- a/nrf5/modules/ubluepy/ubluepy_scan_entry.c +++ b/nrf5/modules/ubluepy/ubluepy_scan_entry.c @@ -37,10 +37,7 @@ STATIC void ubluepy_scan_entry_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_scan_entry_obj_t * self = (ubluepy_scan_entry_obj_t *)o; (void)self; - mp_printf(print, "ScanEntry(addr: "HEX2_FMT":"HEX2_FMT":"HEX2_FMT":" \ - HEX2_FMT":"HEX2_FMT":"HEX2_FMT")", - self->addr[0], self->addr[1], self->addr[2], - self->addr[3], self->addr[4], self->addr[5]); + mp_printf(print, "ScanEntry"); } STATIC void ubluepy_scan_entry_attr(mp_obj_t self_in, qstr attr, mp_obj_t *dest) { @@ -50,7 +47,7 @@ STATIC void ubluepy_scan_entry_attr(mp_obj_t self_in, qstr attr, mp_obj_t *dest) } ubluepy_scan_entry_obj_t *self = MP_OBJ_TO_PTR(self_in); if (attr == MP_QSTR_addr) { - dest[0] = mp_obj_new_bytearray_by_ref(6, self->addr); + dest[0] = self->addr; } else if (attr == MP_QSTR_addr_type) { dest[0] = mp_obj_new_int(self->addr_type); } else if (attr == MP_QSTR_rssi) { diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index 39e25b9edc..112b075625 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -41,12 +41,17 @@ STATIC void adv_event_handler(mp_obj_t self_in, uint16_t event_id, ble_drv_adv_d ubluepy_scan_entry_obj_t * item = m_new_obj(ubluepy_scan_entry_obj_t); item->base.type = &ubluepy_scan_entry_type; - item->addr[0] = data->p_peer_addr[5]; - item->addr[1] = data->p_peer_addr[4]; - item->addr[2] = data->p_peer_addr[3]; - item->addr[3] = data->p_peer_addr[2]; - item->addr[4] = data->p_peer_addr[1]; - item->addr[5] = data->p_peer_addr[0]; + vstr_t vstr; + vstr_init(&vstr, 17); + + vstr_printf(&vstr, ""HEX2_FMT":"HEX2_FMT":"HEX2_FMT":" \ + HEX2_FMT":"HEX2_FMT":"HEX2_FMT"", + data->p_peer_addr[5], data->p_peer_addr[4], data->p_peer_addr[3], + data->p_peer_addr[2], data->p_peer_addr[1], data->p_peer_addr[0]); + + item->addr = mp_obj_new_str(vstr.buf, vstr.len, false); + + vstr_clear(&vstr); item->addr_type = data->addr_type; item->rssi = data->rssi; From f38b0ba037c0893c5c5be7c678af4b3b752c8681 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 23 Mar 2017 21:03:40 +0100 Subject: [PATCH 521/809] nrf5/bluetooth: Adding function for connecting to a device (in central role). Not yet tested. --- nrf5/bluetooth/ble_drv.c | 32 ++++++++++++++++++++++++++++++++ nrf5/bluetooth/ble_drv.h | 2 ++ 2 files changed, 34 insertions(+) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 071fd8d9ae..3ba51569fe 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -697,6 +697,38 @@ void ble_drv_scan_stop(void) { sd_ble_gap_scan_stop(); } +void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) { + SD_TEST_OR_ENABLE(); + + ble_gap_scan_params_t scan_params; + scan_params.active = 1; + scan_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS); + scan_params.window = MSEC_TO_UNITS(100, UNIT_0_625_MS); + scan_params.timeout = 0; // Infinite + +#if (BLUETOOTH_SD == 130) + scan_params.selective = 0; + scan_params.p_whitelist = NULL; +#else + scan_params.use_whitelist = 0; +#endif + + ble_gap_addr_t addr; + memset(&addr, 0, sizeof(addr)); + + addr.addr_type = addr_type; + memcpy(addr.addr, p_addr, 6); + + ble_gap_conn_params_t conn_params; + (void)sd_ble_gap_ppcp_get(&conn_params); + + uint32_t err_code; + if ((err_code = sd_ble_gap_connect(&addr, &scan_params, &conn_params)) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not connect. status: 0x" HEX2_FMT, (uint16_t)err_code)); + } +} + #endif static void ble_evt_handler(ble_evt_t * p_ble_evt) { diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index cf70fe1e34..c466bea3d9 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -80,4 +80,6 @@ void ble_drv_scan_stop(void); void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt_handler); +void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type); + #endif // BLUETOOTH_LE_DRIVER_H__ From 098e64b1228d62682cb9d4e4085ba46192a1bceb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 25 Mar 2017 17:39:44 +0100 Subject: [PATCH 522/809] nrf5/modules/ubluepy: Adding locals dict to Scan Entry introducing function to retreive Scan Data. Not working as expected together with .attr. It looks like locals dict functions are treated to be attributes and cannot be resolved. --- nrf5/modules/ubluepy/ubluepy_scan_entry.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scan_entry.c b/nrf5/modules/ubluepy/ubluepy_scan_entry.c index b7d54523d6..d197df4051 100644 --- a/nrf5/modules/ubluepy/ubluepy_scan_entry.c +++ b/nrf5/modules/ubluepy/ubluepy_scan_entry.c @@ -56,15 +56,29 @@ STATIC void ubluepy_scan_entry_attr(mp_obj_t self_in, qstr attr, mp_obj_t *dest) } +/// \method getScanData() +/// Return list of the scan data tupples. +/// +STATIC mp_obj_t scan_entry_get_scan_data(mp_obj_t self_in, mp_obj_t type_in) { + ubluepy_scan_entry_obj_t * self = MP_OBJ_TO_PTR(self_in); + (void)self; + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_scan_entry_get_scan_data_obj, scan_entry_get_scan_data); + +STATIC const mp_map_elem_t ubluepy_scan_entry_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_getScanData), (mp_obj_t)(&ubluepy_scan_entry_get_scan_data_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_scan_entry_locals_dict, ubluepy_scan_entry_locals_dict_table); + const mp_obj_type_t ubluepy_scan_entry_type = { { &mp_type_type }, .name = MP_QSTR_ScanEntry, .print = ubluepy_scan_entry_print, -#if 0 - .make_new = ubluepy_scan_entry_make_new, .locals_dict = (mp_obj_t)&ubluepy_scan_entry_locals_dict, -#endif .attr = ubluepy_scan_entry_attr }; From 4d147beedbb4e6d9e2e12eec6ebd78b2edd7f78d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 25 Mar 2017 17:51:52 +0100 Subject: [PATCH 523/809] nrf5/modules/ubluepy: Adding template function for central connect() in peripheral object. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index c6282cbb27..9d481def94 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -242,13 +242,26 @@ STATIC mp_obj_t peripheral_get_services(mp_obj_t self_in) { STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_get_services_obj, peripheral_get_services); +/// \method connect(device_address) +/// Connect to device peripheral with the given device address. +/// +STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { + ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); + + (void)self; + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_connect_obj, peripheral_connect); + + STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_setNotificationHandler), (mp_obj_t)(&ubluepy_peripheral_set_notif_handler_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_setConnectionHandler), (mp_obj_t)(&ubluepy_peripheral_set_conn_handler_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, -#if 0 // MICROPY_PY_UBLUEPY_CENTRAL +#if MICROPY_PY_UBLUEPY_CENTRAL { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, +#if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getServiceByUUID), (mp_obj_t)(&ubluepy_peripheral_get_service_by_uuid_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_peripheral_get_chars_obj) }, @@ -256,7 +269,8 @@ STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_waitForNotifications), (mp_obj_t)(&ubluepy_peripheral_wait_for_notif_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, -#endif +#endif // 0 +#endif // MICROPY_PY_UBLUEPY_CENTRAL #if MICROPY_PY_UBLUEPY_PERIPHERAL { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, From bcf4631e0afd53b99a5f7345338605913630cc8c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Mar 2017 20:43:43 +0200 Subject: [PATCH 524/809] nrf5/bluetooth: Updating connect function in the bluetooth driver to do a successful connect to a peripheral device. --- nrf5/bluetooth/ble_drv.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 3ba51569fe..414abdcd70 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -704,7 +704,7 @@ void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) { scan_params.active = 1; scan_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS); scan_params.window = MSEC_TO_UNITS(100, UNIT_0_625_MS); - scan_params.timeout = 0; // Infinite + scan_params.timeout = 0; // infinite #if (BLUETOOTH_SD == 130) scan_params.selective = 0; @@ -719,8 +719,20 @@ void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) { addr.addr_type = addr_type; memcpy(addr.addr, p_addr, 6); + BLE_DRIVER_LOG("GAP CONNECTING: "HEX2_FMT":"HEX2_FMT":"HEX2_FMT":"HEX2_FMT":"HEX2_FMT":"HEX2_FMT", type: %d\n", + addr.addr[0], addr.addr[1], addr.addr[2], addr.addr[3], addr.addr[4], addr.addr[5], addr.addr_type); + ble_gap_conn_params_t conn_params; - (void)sd_ble_gap_ppcp_get(&conn_params); + +// (void)sd_ble_gap_ppcp_get(&conn_params); + + // set connection parameters + memset(&conn_params, 0, sizeof(conn_params)); + + conn_params.min_conn_interval = BLE_MIN_CONN_INTERVAL; + conn_params.max_conn_interval = BLE_MAX_CONN_INTERVAL; + conn_params.slave_latency = BLE_SLAVE_LATENCY; + conn_params.conn_sup_timeout = BLE_CONN_SUP_TIMEOUT; uint32_t err_code; if ((err_code = sd_ble_gap_connect(&addr, &scan_params, &conn_params)) != 0) { From c230bc021af0bd25bb82d1dedf6fc05057742bb5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Mar 2017 20:45:21 +0200 Subject: [PATCH 525/809] nrf5/modules/ubluepy: Update connect method to parse dev_addr parameter and pass it to the bluetooth driver, going through a allocated heap buffer. Adding call to the bluetooth driver to issue a connect. Hardcoding address type for now. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 9d481def94..a86215c0c7 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -249,6 +249,32 @@ STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); (void)self; + + if (MP_OBJ_IS_STR(dev_addr)) { + GET_STR_DATA_LEN(dev_addr, str_data, str_len); + if (str_len == 17) { // Example "11:22:33:aa:bb:cc" + + uint8_t * p_addr = m_new(uint8_t, 6); + + p_addr[0] = unichar_xdigit_value(str_data[16]); + p_addr[0] += unichar_xdigit_value(str_data[15]) << 4; + p_addr[1] = unichar_xdigit_value(str_data[13]); + p_addr[1] += unichar_xdigit_value(str_data[12]) << 4; + p_addr[2] = unichar_xdigit_value(str_data[10]); + p_addr[2] += unichar_xdigit_value(str_data[9]) << 4; + p_addr[3] = unichar_xdigit_value(str_data[7]); + p_addr[3] += unichar_xdigit_value(str_data[6]) << 4; + p_addr[4] = unichar_xdigit_value(str_data[4]); + p_addr[4] += unichar_xdigit_value(str_data[3]) << 4; + p_addr[5] = unichar_xdigit_value(str_data[1]); + p_addr[5] += unichar_xdigit_value(str_data[0]) << 4; + + ble_drv_connect(p_addr, 1); + + m_del(uint8_t, p_addr, 6); + } + } + return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_connect_obj, peripheral_connect); From fb983c7692902a3f75bf6f6f02bc9fa3a5e34609 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Mar 2017 20:46:23 +0200 Subject: [PATCH 526/809] nrf5/boards: Inrease heap size in the nrf52832 w/s132 bluetooth stack linker script. --- nrf5/boards/nrf52832_512k_64k_s132.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/nrf52832_512k_64k_s132.ld b/nrf5/boards/nrf52832_512k_64k_s132.ld index 65c108192b..159c159b2c 100644 --- a/nrf5/boards/nrf52832_512k_64k_s132.ld +++ b/nrf5/boards/nrf52832_512k_64k_s132.ld @@ -22,6 +22,6 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x20006000; /* tunable */ +_heap_end = 0x20007000; /* tunable */ INCLUDE "boards/common.ld" From cd2149a47f282df6fc20b136551cb728a45cc220 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Mar 2017 21:02:25 +0200 Subject: [PATCH 527/809] nrf5/bluetooth: Updating bluetooth le driver to handle GAP conn param update request. Also updating minor syntax in previous switch case. --- nrf5/bluetooth/ble_drv.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 414abdcd70..b71b9f69bc 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -824,8 +824,15 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { // TODO: Fix unsafe callback to possible undefined callback... adv_event_handler(mp_adv_observer, - p_ble_evt->header.evt_id, - &adv_data); + p_ble_evt->header.evt_id, + &adv_data); + break; + + case BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST: + BLE_DRIVER_LOG("BLE EVT CONN PARAM UPDATE REQUEST\n"); + + (void)sd_ble_gap_conn_param_update(p_ble_evt->evt.gap_evt.conn_handle, + &p_ble_evt->evt.gap_evt.params.conn_param_update_request.conn_params); break; #endif From 2f2e67e9bd433549ae98c27f4847f623344ba8a1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Mar 2017 21:05:06 +0200 Subject: [PATCH 528/809] nrf5/bluetooth: Fixing some smaller tab errors in the bluetooth driver. --- nrf5/bluetooth/ble_drv.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index b71b9f69bc..688c83c3ae 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -607,8 +607,8 @@ void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint handle, &gatts_value); if (err_code != 0) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can not read attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not read attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); } } @@ -641,9 +641,9 @@ void ble_drv_attr_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, ui hvx_params.p_len = &hvx_len; hvx_params.p_data = p_data; - while (m_tx_in_progress) { - ; - } + while (m_tx_in_progress) { + ; + } m_tx_in_progress = true; uint32_t err_code; From 49cce723a9c0ebfb485ad203ee3090dc27cd4c0d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Mar 2017 21:06:17 +0200 Subject: [PATCH 529/809] nrf5/bluetooth: Turning off debug logging in bluetooth driver, which does not work well with bluetooth REPL mode. --- nrf5/bluetooth/ble_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 688c83c3ae..f73191d5f6 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -36,7 +36,7 @@ #include "ble.h" // sd_ble_uuid_encode -#define BLE_DRIVER_VERBOSE 1 +#define BLE_DRIVER_VERBOSE 0 #if BLE_DRIVER_VERBOSE #define BLE_DRIVER_LOG printf #else From 025f07dbabd6ff26b865d632013df40f7f8f6b0e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Mar 2017 22:51:10 +0200 Subject: [PATCH 530/809] nrf5/bluetooth: Adding intermediate gattc callback function type in bluetooth driver. --- nrf5/bluetooth/ble_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index c466bea3d9..4fa6f43d1a 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -44,6 +44,7 @@ typedef struct { typedef void (*ble_drv_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); typedef void (*ble_drv_gatts_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); +typedef void (*ble_drv_gattc_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); typedef void (*ble_drv_adv_evt_callback_t)(mp_obj_t self, uint16_t event_id, ble_drv_adv_data_t * data); uint32_t ble_drv_stack_enable(void); From 0914b3419338d86e199a33210ee21632c1b631b3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Mar 2017 22:57:07 +0200 Subject: [PATCH 531/809] nrf5/bluetooth: Adding function to register gattc event handler (central). --- nrf5/bluetooth/ble_drv.c | 7 +++++++ nrf5/bluetooth/ble_drv.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index f73191d5f6..33e85bbdbe 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -77,10 +77,12 @@ static volatile bool m_tx_in_progress; static ble_drv_gap_evt_callback_t gap_event_handler; static ble_drv_adv_evt_callback_t adv_event_handler; static ble_drv_gatts_evt_callback_t gatts_event_handler; +static ble_drv_gattc_evt_callback_t gattc_event_handler; static mp_obj_t mp_gap_observer; static mp_obj_t mp_adv_observer; static mp_obj_t mp_gatts_observer; +static mp_obj_t mp_gattc_observer; #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -663,6 +665,11 @@ void ble_drv_gatts_event_handler_set(mp_obj_t obj, ble_drv_gatts_evt_callback_t gatts_event_handler = evt_handler; } +void ble_drv_gattc_event_handler_set(mp_obj_t obj, ble_drv_gattc_evt_callback_t evt_handler) { + mp_gattc_observer = obj; + gattc_event_handler = evt_handler; +} + void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt_handler) { mp_adv_observer = obj; adv_event_handler = evt_handler; diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 4fa6f43d1a..ee8a8304c3 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -69,6 +69,8 @@ void ble_drv_gap_event_handler_set(mp_obj_t obs, ble_drv_gap_evt_callback_t evt_ void ble_drv_gatts_event_handler_set(mp_obj_t obj, ble_drv_gatts_evt_callback_t evt_handler); +void ble_drv_gattc_event_handler_set(mp_obj_t obj, ble_drv_gattc_evt_callback_t evt_handler); + void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); From 06af64a78a59c654cd8d2484fa1cc3e52fbea83e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 26 Mar 2017 22:59:30 +0200 Subject: [PATCH 532/809] nrf5/bluetooth: Adding template functions for service discovery in bluetooth driver. --- nrf5/bluetooth/ble_drv.c | 12 ++++++++++++ nrf5/bluetooth/ble_drv.h | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 33e85bbdbe..a3c3e04759 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -748,6 +748,18 @@ void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) { } } +void ble_drv_discover_services(void) { + +} + +void ble_drv_discover_characteristic(void) { + +} + +void ble_drv_discover_descriptors(void) { + +} + #endif static void ble_evt_handler(ble_evt_t * p_ble_evt) { diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index ee8a8304c3..d1b494fc3a 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -85,4 +85,10 @@ void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type); +void ble_drv_discover_services(void); + +void ble_drv_discover_characteristic(void); + +void ble_drv_discover_descriptors(void); + #endif // BLUETOOTH_LE_DRIVER_H__ From 61b825d75e13ca951aa7e8f04386cc5f5bd829d2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 28 Mar 2017 21:20:20 +0200 Subject: [PATCH 533/809] nrf5/bluetooth: Adding function parameters and return type to service and characteristic discovery template functions. --- nrf5/bluetooth/ble_drv.c | 8 ++++---- nrf5/bluetooth/ble_drv.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index a3c3e04759..452cba5935 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -748,12 +748,12 @@ void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) { } } -void ble_drv_discover_services(void) { - +bool ble_drv_discover_services(ubluepy_service_obj_t * p_service_obj) { + return false; } -void ble_drv_discover_characteristic(void) { - +bool ble_drv_discover_characteristic(ubluepy_characteristic_obj_t * p_char_obj) { + return false; } void ble_drv_discover_descriptors(void) { diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index d1b494fc3a..e6ff59bf44 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -85,9 +85,9 @@ void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type); -void ble_drv_discover_services(void); +bool ble_drv_discover_services(ubluepy_service_obj_t * p_service_obj); -void ble_drv_discover_characteristic(void); +bool ble_drv_discover_characteristic(ubluepy_characteristic_obj_t * p_char_obj); void ble_drv_discover_descriptors(void); From 8966c68b924b994103d42561f514f74dff182b50 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 28 Mar 2017 23:37:19 +0200 Subject: [PATCH 534/809] nrf5/bluetooth: Adding implementation to the discover service function. Adding handler for gatt client primary service discovery response events, and passing this to the ubluepy upon reception. --- nrf5/bluetooth/ble_drv.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 452cba5935..9414e929ac 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -749,6 +749,15 @@ void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) { } bool ble_drv_discover_services(ubluepy_service_obj_t * p_service_obj) { + BLE_DRIVER_LOG("Discover primary services. Conn handle: 0x" HEX2_FMT "\n", + p_service_obj->p_periph->conn_handle); + + uint32_t err_code; + err_code = sd_ble_gattc_primary_services_discover(p_service_obj->p_periph->conn_handle, + 0x0001, + NULL); + + (void)err_code; return false; } @@ -853,6 +862,12 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { (void)sd_ble_gap_conn_param_update(p_ble_evt->evt.gap_evt.conn_handle, &p_ble_evt->evt.gap_evt.params.conn_param_update_request.conn_params); break; + + case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: + BLE_DRIVER_LOG("BLE EVT PRIMARY SERVICE DISCOVERY RESPONSE\n"); + gattc_event_handler(mp_gattc_observer, p_ble_evt->header.evt_id, 0, 0, NULL); + break; + #endif default: From a139d5e8f77169fe05ccecfaaa4228d1d372a3cf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 28 Mar 2017 23:40:28 +0200 Subject: [PATCH 535/809] nrf5/modules/ubluepy: Adding some work in progress on service discovery. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index a86215c0c7..8f9b77f91e 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -87,6 +87,17 @@ STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t at } +#if MICROPY_PY_UBLUEPY_CENTRAL + +static volatile bool m_disc_evt_received; + +STATIC void gattc_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + (void)self; + m_disc_evt_received = true; +} +#endif + STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { enum { ARG_NEW_DEVICE_ADDR, @@ -107,6 +118,9 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(s), gap_event_handler); ble_drv_gatts_event_handler_set(MP_OBJ_FROM_PTR(s), gatts_event_handler); +#if MICROPY_PY_UBLUEPY_CENTRAL + ble_drv_gattc_event_handler_set(MP_OBJ_FROM_PTR(s), gattc_event_handler); +#endif s->delegate = mp_const_none; s->conn_handler = mp_const_none; @@ -275,6 +289,34 @@ STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { } } + // block until connected + while (self->conn_handle == 0xFFFF) { + ; + } + + ubluepy_service_obj_t * p_service; + bool retval; + do { + // create an initial service + p_service = m_new_obj(ubluepy_service_obj_t); + p_service->base.type = &ubluepy_service_type; + + // assign peripheral reference to the service object + p_service->p_periph = self; + + // assign an empty uuid object to the service object + // TODO + + // Do service discovery + m_disc_evt_received = false; + + retval = ble_drv_discover_services(p_service); + + while (m_disc_evt_received != true) { + ; + } + } while (m_disc_evt_received && retval == true); + return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_connect_obj, peripheral_connect); From 5b778790ae392058fda88aa1e0fc88ac8cb7a819 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 29 Mar 2017 23:34:33 +0200 Subject: [PATCH 536/809] nrf5/bluetooth: Updating bluetooth driver to do service discovery, doing callbacks to ubluepy upon each individual primary service discovered. Using intermediate structure defined by the driver, to abstract bluetooth stack specific data in ubluepy. --- nrf5/bluetooth/ble_drv.c | 38 +++++++++++++++++++++++++++++--------- nrf5/bluetooth/ble_drv.h | 10 +++++++++- 2 files changed, 38 insertions(+), 10 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 9414e929ac..a5d4e3639d 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -74,15 +74,17 @@ if (ble_drv_stack_enabled() == 0) { \ static volatile bool m_adv_in_progress; static volatile bool m_tx_in_progress; -static ble_drv_gap_evt_callback_t gap_event_handler; -static ble_drv_adv_evt_callback_t adv_event_handler; -static ble_drv_gatts_evt_callback_t gatts_event_handler; -static ble_drv_gattc_evt_callback_t gattc_event_handler; +static ble_drv_gap_evt_callback_t gap_event_handler; +static ble_drv_adv_evt_callback_t adv_event_handler; +static ble_drv_gatts_evt_callback_t gatts_event_handler; +static ble_drv_gattc_evt_callback_t gattc_event_handler; +static ble_drv_disc_add_service_callback_t disc_add_service_handler; static mp_obj_t mp_gap_observer; static mp_obj_t mp_adv_observer; static mp_obj_t mp_gatts_observer; static mp_obj_t mp_gattc_observer; +static mp_obj_t mp_gattc_disc_observer; #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -748,17 +750,20 @@ void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) { } } -bool ble_drv_discover_services(ubluepy_service_obj_t * p_service_obj) { +bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, ble_drv_disc_add_service_callback_t cb) { BLE_DRIVER_LOG("Discover primary services. Conn handle: 0x" HEX2_FMT "\n", - p_service_obj->p_periph->conn_handle); + conn_handle); + + mp_gattc_disc_observer = obj; + disc_add_service_handler = cb; uint32_t err_code; - err_code = sd_ble_gattc_primary_services_discover(p_service_obj->p_periph->conn_handle, + err_code = sd_ble_gattc_primary_services_discover(conn_handle, 0x0001, NULL); (void)err_code; - return false; + return true; } bool ble_drv_discover_characteristic(ubluepy_characteristic_obj_t * p_char_obj) { @@ -865,7 +870,22 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: BLE_DRIVER_LOG("BLE EVT PRIMARY SERVICE DISCOVERY RESPONSE\n"); - gattc_event_handler(mp_gattc_observer, p_ble_evt->header.evt_id, 0, 0, NULL); + + + + + for (uint16_t i = 0; i < p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count; i++) { + ble_gattc_service_t * p_service = &p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.services[i]; + + ble_drv_service_data_t service; + service.uuid_type = p_service->uuid.type; + service.uuid = p_service->uuid.uuid; + service.start_handle = p_service->handle_range.start_handle; + service.end_handle = p_service->handle_range.end_handle; + + disc_add_service_handler(mp_gattc_disc_observer, &service); + } + break; #endif diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index e6ff59bf44..26f16bdf1c 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -42,10 +42,18 @@ typedef struct { uint8_t adv_type; } ble_drv_adv_data_t; +typedef struct { + uint16_t uuid; + uint8_t uuid_type; + uint16_t start_handle; + uint16_t end_handle; +} ble_drv_service_data_t; + typedef void (*ble_drv_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); typedef void (*ble_drv_gatts_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); typedef void (*ble_drv_gattc_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); typedef void (*ble_drv_adv_evt_callback_t)(mp_obj_t self, uint16_t event_id, ble_drv_adv_data_t * data); +typedef void (*ble_drv_disc_add_service_callback_t)(mp_obj_t self, ble_drv_service_data_t * p_service_data); uint32_t ble_drv_stack_enable(void); @@ -85,7 +93,7 @@ void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type); -bool ble_drv_discover_services(ubluepy_service_obj_t * p_service_obj); +bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, ble_drv_disc_add_service_callback_t cb); bool ble_drv_discover_characteristic(ubluepy_characteristic_obj_t * p_char_obj); From 75148ee6ca266d12f2dfba9e03736a50e08972dc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 29 Mar 2017 23:37:32 +0200 Subject: [PATCH 537/809] nrf5/modules/ubluepy: Updating ubluepy peripheral object to new bluetooth driver API. Starting to populate service objects and uuid objects. Also adding the service to the peripheral object throught the regular static function for adding services. Handle value for the primary service is assuming that it is the first element in the handle range; start_handle reported by the service discovery. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 42 +++++++++++------------ 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 8f9b77f91e..0f1b37e251 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -256,6 +256,25 @@ STATIC mp_obj_t peripheral_get_services(mp_obj_t self_in) { STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_get_services_obj, peripheral_get_services); +void static disc_add_service(mp_obj_t self, ble_drv_service_data_t * p_service_data) { + ubluepy_service_obj_t * p_service = m_new_obj(ubluepy_service_obj_t); + p_service->base.type = &ubluepy_service_type; + + ubluepy_uuid_obj_t * p_uuid = m_new_obj(ubluepy_uuid_obj_t); + p_uuid->base.type = &ubluepy_uuid_type; + + p_service->p_uuid = p_uuid; + + p_uuid->type = p_service_data->uuid_type; + p_uuid->value[0] = p_service_data->uuid & 0xFF; + p_uuid->value[1] = p_service_data->uuid >> 8; + + p_service->handle = p_service_data->start_handle; + + peripheral_add_service(self, MP_OBJ_FROM_PTR(p_service)); +} + + /// \method connect(device_address) /// Connect to device peripheral with the given device address. /// @@ -294,28 +313,7 @@ STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { ; } - ubluepy_service_obj_t * p_service; - bool retval; - do { - // create an initial service - p_service = m_new_obj(ubluepy_service_obj_t); - p_service->base.type = &ubluepy_service_type; - - // assign peripheral reference to the service object - p_service->p_periph = self; - - // assign an empty uuid object to the service object - // TODO - - // Do service discovery - m_disc_evt_received = false; - - retval = ble_drv_discover_services(p_service); - - while (m_disc_evt_received != true) { - ; - } - } while (m_disc_evt_received && retval == true); + (void)ble_drv_discover_services(self, self->conn_handle, disc_add_service); return mp_const_none; } From 2200c4c084e8ed7ba1e33f8a8e715eb0a58fe674 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 30 Mar 2017 22:41:19 +0200 Subject: [PATCH 538/809] nrf5/bluetooth: Adding support for central characteristic service discovery. Updating primary service discovery to block until all services has been created in the peripheral object before returning from the bluetooth driver. This pattern is also applied to the characteristic discovery. --- nrf5/bluetooth/ble_drv.c | 82 +++++++++++++++++++++++++++++++++++----- nrf5/bluetooth/ble_drv.h | 16 +++++++- 2 files changed, 88 insertions(+), 10 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index a5d4e3639d..e6b71c90de 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -79,12 +79,14 @@ static ble_drv_adv_evt_callback_t adv_event_handler; static ble_drv_gatts_evt_callback_t gatts_event_handler; static ble_drv_gattc_evt_callback_t gattc_event_handler; static ble_drv_disc_add_service_callback_t disc_add_service_handler; +static ble_drv_disc_add_char_callback_t disc_add_char_handler; static mp_obj_t mp_gap_observer; static mp_obj_t mp_adv_observer; static mp_obj_t mp_gatts_observer; static mp_obj_t mp_gattc_observer; -static mp_obj_t mp_gattc_disc_observer; +static mp_obj_t mp_gattc_disc_service_observer; +static mp_obj_t mp_gattc_disc_char_observer; #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -754,20 +756,52 @@ bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, ble_drv_disc_ BLE_DRIVER_LOG("Discover primary services. Conn handle: 0x" HEX2_FMT "\n", conn_handle); - mp_gattc_disc_observer = obj; + mp_gattc_disc_service_observer = obj; disc_add_service_handler = cb; uint32_t err_code; err_code = sd_ble_gattc_primary_services_discover(conn_handle, 0x0001, NULL); + if (err_code != 0) { + return false; + } + + // busy loop until last service has been iterated + while (disc_add_service_handler != NULL) { + ; + } - (void)err_code; return true; } -bool ble_drv_discover_characteristic(ubluepy_characteristic_obj_t * p_char_obj) { - return false; +bool ble_drv_discover_characteristic(mp_obj_t obj, + uint16_t conn_handle, + uint16_t start_handle, + uint16_t end_handle, + ble_drv_disc_add_char_callback_t cb) { + BLE_DRIVER_LOG("Discover characteristicts. Conn handle: 0x" HEX2_FMT "\n", + conn_handle); + + mp_gattc_disc_char_observer = obj; + disc_add_char_handler = cb; + + ble_gattc_handle_range_t handle_range; + handle_range.start_handle = start_handle; + handle_range.end_handle = end_handle; + + uint32_t err_code; + err_code = sd_ble_gattc_characteristics_discover(conn_handle, &handle_range); + if (err_code != 0) { + return false; + } + + // busy loop until last service has been iterated + while (disc_add_char_handler != NULL) { + ; + } + + return true; } void ble_drv_discover_descriptors(void) { @@ -871,9 +905,6 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: BLE_DRIVER_LOG("BLE EVT PRIMARY SERVICE DISCOVERY RESPONSE\n"); - - - for (uint16_t i = 0; i < p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count; i++) { ble_gattc_service_t * p_service = &p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.services[i]; @@ -883,9 +914,42 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { service.start_handle = p_service->handle_range.start_handle; service.end_handle = p_service->handle_range.end_handle; - disc_add_service_handler(mp_gattc_disc_observer, &service); + disc_add_service_handler(mp_gattc_disc_service_observer, &service); } + // mark end of service discovery + disc_add_service_handler = NULL; + + break; + + case BLE_GATTC_EVT_CHAR_DISC_RSP: + BLE_DRIVER_LOG("BLE EVT CHAR DISCOVERY RESPONSE\n"); + + for (uint16_t i = 0; i < p_ble_evt->evt.gattc_evt.params.char_disc_rsp.count; i++) { + ble_gattc_char_t * p_char = &p_ble_evt->evt.gattc_evt.params.char_disc_rsp.chars[i]; + + ble_drv_char_data_t char_data; + char_data.uuid_type = p_char->uuid.type; + char_data.uuid = p_char->uuid.uuid; + char_data.decl_handle = p_char->handle_decl; + char_data.value_handle = p_char->handle_value; + + char_data.props |= (p_char->char_props.broadcast) ? UBLUEPY_PROP_BROADCAST : 0; + char_data.props |= (p_char->char_props.read) ? UBLUEPY_PROP_READ : 0; + char_data.props |= (p_char->char_props.write_wo_resp) ? UBLUEPY_PROP_WRITE_WO_RESP : 0; + char_data.props |= (p_char->char_props.write) ? UBLUEPY_PROP_WRITE : 0; + char_data.props |= (p_char->char_props.notify) ? UBLUEPY_PROP_NOTIFY : 0; + char_data.props |= (p_char->char_props.indicate) ? UBLUEPY_PROP_INDICATE : 0; + #if 0 + char_data.props |= (p_char->char_props.auth_signed_wr) ? UBLUEPY_PROP_NOTIFY : 0; + #endif + + disc_add_char_handler(mp_gattc_disc_char_observer, &char_data); + } + + // mark end of characteristic discovery + disc_add_char_handler = NULL; + break; #endif diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 26f16bdf1c..7e004eb1be 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -49,11 +49,21 @@ typedef struct { uint16_t end_handle; } ble_drv_service_data_t; +typedef struct { + uint16_t uuid; + uint8_t uuid_type; + uint8_t props; + uint16_t decl_handle; + uint16_t value_handle; +} ble_drv_char_data_t; + typedef void (*ble_drv_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data); typedef void (*ble_drv_gatts_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); typedef void (*ble_drv_gattc_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data); typedef void (*ble_drv_adv_evt_callback_t)(mp_obj_t self, uint16_t event_id, ble_drv_adv_data_t * data); typedef void (*ble_drv_disc_add_service_callback_t)(mp_obj_t self, ble_drv_service_data_t * p_service_data); +typedef void (*ble_drv_disc_add_char_callback_t)(mp_obj_t self, ble_drv_char_data_t * p_desc_data); + uint32_t ble_drv_stack_enable(void); @@ -95,7 +105,11 @@ void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type); bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, ble_drv_disc_add_service_callback_t cb); -bool ble_drv_discover_characteristic(ubluepy_characteristic_obj_t * p_char_obj); +bool ble_drv_discover_characteristic(mp_obj_t obj, + uint16_t conn_handle, + uint16_t start_handle, + uint16_t end_handle, + ble_drv_disc_add_char_callback_t cb); void ble_drv_discover_descriptors(void); From 31a71517abe5b7625bcd254855a95f56186e7997 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 30 Mar 2017 22:42:08 +0200 Subject: [PATCH 539/809] nrf5/modules/ubluepy: Adding start and end handle to service object. --- nrf5/modules/ubluepy/modubluepy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index a14110ef41..fd44f3a524 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -113,6 +113,8 @@ typedef struct _ubluepy_service_obj_t { ubluepy_uuid_obj_t * p_uuid; ubluepy_peripheral_obj_t * p_periph; mp_obj_t char_list; + uint16_t start_handle; + uint16_t end_handle; } ubluepy_service_obj_t; typedef struct _ubluepy_characteristic_obj_t { From bd2981681fdd239731de1e7a49ddc035aaf10890 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 30 Mar 2017 22:46:45 +0200 Subject: [PATCH 540/809] nrf5/modules/ubluepy: Updating peripheral object to handle characteristic discovery (central mode). --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 61 +++++++++++++++++++++-- 1 file changed, 56 insertions(+), 5 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 0f1b37e251..1bf94ceb95 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -37,7 +37,8 @@ STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { ubluepy_peripheral_obj_t * self = (ubluepy_peripheral_obj_t *)o; (void)self; - mp_printf(print, "Peripheral"); + mp_printf(print, "Peripheral(conn_handle: " HEX2_FMT ")", + self->conn_handle); } STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data) { @@ -269,11 +270,40 @@ void static disc_add_service(mp_obj_t self, ble_drv_service_data_t * p_service_d p_uuid->value[0] = p_service_data->uuid & 0xFF; p_uuid->value[1] = p_service_data->uuid >> 8; - p_service->handle = p_service_data->start_handle; + p_service->handle = p_service_data->start_handle; + p_service->start_handle = p_service_data->start_handle; + p_service->end_handle = p_service_data->end_handle; + + p_service->char_list = mp_obj_new_list(0, NULL); peripheral_add_service(self, MP_OBJ_FROM_PTR(p_service)); } +void static disc_add_char(mp_obj_t service_in, ble_drv_char_data_t * p_desc_data) { + ubluepy_service_obj_t * p_service = MP_OBJ_TO_PTR(service_in); + ubluepy_characteristic_obj_t * p_char = m_new_obj(ubluepy_characteristic_obj_t); + p_char->base.type = &ubluepy_characteristic_type; + + ubluepy_uuid_obj_t * p_uuid = m_new_obj(ubluepy_uuid_obj_t); + p_uuid->base.type = &ubluepy_uuid_type; + + p_char->p_uuid = p_uuid; + + p_uuid->type = p_desc_data->uuid_type; + p_uuid->value[0] = p_desc_data->uuid & 0xFF; + p_uuid->value[1] = p_desc_data->uuid >> 8; + + // add characteristic specific data from discovery + p_char->props = p_desc_data->props; + p_char->handle = p_desc_data->value_handle; + + // equivalent to ubluepy_service.c - service_add_characteristic() + // except the registration of the characteristic towards the bluetooth stack + p_char->service_handle = p_service->handle; + p_char->p_service = p_service; + + mp_obj_list_append(p_service->char_list, MP_OBJ_FROM_PTR(p_char)); +} /// \method connect(device_address) /// Connect to device peripheral with the given device address. @@ -281,8 +311,6 @@ void static disc_add_service(mp_obj_t self, ble_drv_service_data_t * p_service_d STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); - (void)self; - if (MP_OBJ_IS_STR(dev_addr)) { GET_STR_DATA_LEN(dev_addr, str_data, str_len); if (str_len == 17) { // Example "11:22:33:aa:bb:cc" @@ -313,7 +341,30 @@ STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { ; } - (void)ble_drv_discover_services(self, self->conn_handle, disc_add_service); + bool retval = ble_drv_discover_services(self, self->conn_handle, disc_add_service); + if (retval != true) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Error during service discovery")); + } + + // For each service perform a characteristic discovery + mp_obj_t * services = NULL; + mp_uint_t num_services; + mp_obj_get_array(self->service_list, &num_services, &services); + + for (uint16_t s = 0; s < num_services; s++) { + ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)services[s]; + + bool retval = ble_drv_discover_characteristic(p_service, + self->conn_handle, + p_service->start_handle, + p_service->end_handle, + disc_add_char); + if (retval != true) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Error during characteristic discovery")); + } + } return mp_const_none; } From ebb7925a169e05f489126b8e3ff6bd82474e28c2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 30 Mar 2017 22:53:25 +0200 Subject: [PATCH 541/809] nrf5/modules/ubluepy: Tab-fix --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 1bf94ceb95..a0d30c51b1 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -280,7 +280,7 @@ void static disc_add_service(mp_obj_t self, ble_drv_service_data_t * p_service_d } void static disc_add_char(mp_obj_t service_in, ble_drv_char_data_t * p_desc_data) { - ubluepy_service_obj_t * p_service = MP_OBJ_TO_PTR(service_in); + ubluepy_service_obj_t * p_service = MP_OBJ_TO_PTR(service_in); ubluepy_characteristic_obj_t * p_char = m_new_obj(ubluepy_characteristic_obj_t); p_char->base.type = &ubluepy_characteristic_type; From 93b76a66d379da13fdf24395272834672f2c2673 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 30 Mar 2017 23:18:49 +0200 Subject: [PATCH 542/809] nrf5/bluetooth: Adding event handling cases for gatt client read, write and hvx events. --- nrf5/bluetooth/ble_drv.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index e6b71c90de..b61b506466 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -952,6 +952,17 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { break; + case BLE_GATTC_EVT_READ_RSP: + BLE_DRIVER_LOG("BLE EVT READ RESPONSE\n"); + break; + + case BLE_GATTC_EVT_WRITE_RSP: + BLE_DRIVER_LOG("BLE EVT WRITE RESPONSE\n"); + break; + + case BLE_GATTC_EVT_HVX: + BLE_DRIVER_LOG("BLE EVT HVX RESPONSE\n"); + break; #endif default: From d24809a2aa53ef06aec360566f4e7f2f6344fa1a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 30 Mar 2017 23:38:01 +0200 Subject: [PATCH 543/809] nrf5/bluetooth: Adding new api for reading attribute as gatt client. Renaming old ble_drv_attr_read function to ble_drv_attr_s_read to indicate the server role. --- nrf5/bluetooth/ble_drv.c | 12 +++++++++++- nrf5/bluetooth/ble_drv.h | 4 +++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index b61b506466..20b6284490 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -601,7 +601,7 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { return true; } -void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { +void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { ble_gatts_value_t gatts_value; memset(&gatts_value, 0, sizeof(gatts_value)); @@ -619,6 +619,16 @@ void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint } +void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { + uint32_t err_code = sd_ble_gattc_read(conn_handle, + handle, + 0); + if (err_code != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not read attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); + } +} + void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { ble_gatts_value_t gatts_value; memset(&gatts_value, 0, sizeof(gatts_value)); diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 7e004eb1be..471b476bfb 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -89,7 +89,9 @@ void ble_drv_gatts_event_handler_set(mp_obj_t obj, ble_drv_gatts_evt_callback_t void ble_drv_gattc_event_handler_set(mp_obj_t obj, ble_drv_gattc_evt_callback_t evt_handler); -void ble_drv_attr_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); +void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); + +void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); From 7c6f041b8c1fb6a642923fb45033631ab6040951 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 30 Mar 2017 23:39:45 +0200 Subject: [PATCH 544/809] nrf5/modules/ubluepy: Adding dummy function call to ble_drv_attr_c_read. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index 313ac8ec4b..c1cfdd415d 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -86,8 +86,10 @@ STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_ /// STATIC mp_obj_t char_read(mp_obj_t self_in) { ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); - (void)self; - // ble_drv_characteristic_read(); + ble_drv_attr_c_read(self->p_service->p_periph->conn_handle, + self->handle, + 0, + NULL); return mp_const_none; } From f9a351d5279d9bd2180573c57ed8898ea2603fff Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 31 Mar 2017 21:51:57 +0200 Subject: [PATCH 545/809] nrf5/modules/ubluepy: Adding binVal() function to the ubluepy UUID object. For now returning the uint16_t value of the UUID as a small integer. --- nrf5/modules/ubluepy/ubluepy_uuid.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index 2bb6894e34..d5627bd2e1 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -139,12 +139,25 @@ STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, return MP_OBJ_FROM_PTR(s); } +/// \method binVal() +/// Get binary value of the 16 or 128 bit UUID. Returned as bytearray type. +/// +STATIC mp_obj_t uuid_bin_val(mp_obj_t self_in) { + ubluepy_uuid_obj_t * self = MP_OBJ_TO_PTR(self_in); + + // TODO: Extend the uint16 byte value to 16 byte if 128-bit, + // also encapsulate it in a bytearray. For now, return + // the uint16_t field of the UUID. + return MP_OBJ_NEW_SMALL_INT(self->value[0] | self->value[1] << 8); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_uuid_bin_val_obj, uuid_bin_val); + STATIC const mp_map_elem_t ubluepy_uuid_locals_dict_table[] = { #if 0 { MP_OBJ_NEW_QSTR(MP_QSTR_getCommonName), (mp_obj_t)(&ubluepy_uuid_get_common_name_obj) }, +#endif // Properties { MP_OBJ_NEW_QSTR(MP_QSTR_binVal), (mp_obj_t)(&ubluepy_uuid_bin_val_obj) }, -#endif }; STATIC MP_DEFINE_CONST_DICT(ubluepy_uuid_locals_dict, ubluepy_uuid_locals_dict_table); From bb7130a813bfad6c0c4e413bf1e74e4fa6618b4f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 31 Mar 2017 21:52:59 +0200 Subject: [PATCH 546/809] nrf5/modules/ubluepy: Adding uuid() function to service object to return UUID instance of the service. --- nrf5/modules/ubluepy/ubluepy_service.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 6400492cc3..6523d22da5 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -151,6 +151,15 @@ STATIC mp_obj_t service_get_characteristic(mp_obj_t self_in, mp_obj_t uuid) { } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_service_get_char_obj, service_get_characteristic); +/// \method uuid() +/// Get UUID instance of the Service. +/// +STATIC mp_obj_t service_uuid(mp_obj_t self_in) { + ubluepy_service_obj_t * self = MP_OBJ_TO_PTR(self_in); + return MP_OBJ_FROM_PTR(self->p_uuid); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_service_get_uuid_obj, service_uuid); + STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristic), (mp_obj_t)(&ubluepy_service_get_char_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_service_add_char_obj) }, @@ -158,8 +167,8 @@ STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { #if 0 // Properties { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_service_get_peripheral_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_service_get_uuid_obj) }, #endif + { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_service_get_uuid_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_PRIMARY), MP_OBJ_NEW_SMALL_INT(UBLUEPY_SERVICE_PRIMARY) }, { MP_OBJ_NEW_QSTR(MP_QSTR_SECONDARY), MP_OBJ_NEW_SMALL_INT(UBLUEPY_SERVICE_SECONDARY) }, }; From c88358d84b26a7c3113bd92e56b3791c0610154f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 1 Apr 2017 16:34:26 +0200 Subject: [PATCH 547/809] nrf5/bluetooth: Updating bluetooth driver to support GATT client read of a characteristic value. Data passed to caller in interrupt context, and copy has to be performed. The function call is itself blocking. --- nrf5/bluetooth/ble_drv.c | 24 ++++++++++++++++++++++-- nrf5/bluetooth/ble_drv.h | 4 ++-- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 20b6284490..71eb09bd3a 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -80,6 +80,7 @@ static ble_drv_gatts_evt_callback_t gatts_event_handler; static ble_drv_gattc_evt_callback_t gattc_event_handler; static ble_drv_disc_add_service_callback_t disc_add_service_handler; static ble_drv_disc_add_char_callback_t disc_add_char_handler; +static ble_drv_gattc_char_data_callback_t gattc_char_data_handle; static mp_obj_t mp_gap_observer; static mp_obj_t mp_adv_observer; @@ -87,6 +88,7 @@ static mp_obj_t mp_gatts_observer; static mp_obj_t mp_gattc_observer; static mp_obj_t mp_gattc_disc_service_observer; static mp_obj_t mp_gattc_disc_char_observer; +static mp_obj_t mp_gattc_char_data_observer; #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -619,7 +621,11 @@ void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, ui } -void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { +void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, ble_drv_gattc_char_data_callback_t cb) { + + mp_gattc_char_data_observer = obj; + gattc_char_data_handle = cb; + uint32_t err_code = sd_ble_gattc_read(conn_handle, handle, 0); @@ -627,6 +633,10 @@ void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, uint16_t len, ui nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not read attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); } + + while (gattc_char_data_handle != NULL) { + ; + } } void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { @@ -963,7 +973,17 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { break; case BLE_GATTC_EVT_READ_RSP: - BLE_DRIVER_LOG("BLE EVT READ RESPONSE\n"); + BLE_DRIVER_LOG("BLE EVT READ RESPONSE, offset: 0x"HEX2_FMT", length: 0x"HEX2_FMT"\n", + p_ble_evt->evt.gattc_evt.params.read_rsp.offset, + p_ble_evt->evt.gattc_evt.params.read_rsp.len); + + gattc_char_data_handle(mp_gattc_char_data_observer, + p_ble_evt->evt.gattc_evt.params.read_rsp.len, + p_ble_evt->evt.gattc_evt.params.read_rsp.data); + + // mark end of read + gattc_char_data_handle = NULL; + break; case BLE_GATTC_EVT_WRITE_RSP: diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 471b476bfb..9671ab695b 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -63,7 +63,7 @@ typedef void (*ble_drv_gattc_evt_callback_t)(mp_obj_t self, uint16_t event_id, u typedef void (*ble_drv_adv_evt_callback_t)(mp_obj_t self, uint16_t event_id, ble_drv_adv_data_t * data); typedef void (*ble_drv_disc_add_service_callback_t)(mp_obj_t self, ble_drv_service_data_t * p_service_data); typedef void (*ble_drv_disc_add_char_callback_t)(mp_obj_t self, ble_drv_char_data_t * p_desc_data); - +typedef void (*ble_drv_gattc_char_data_callback_t)(mp_obj_t self, uint16_t length, uint8_t * p_data); uint32_t ble_drv_stack_enable(void); @@ -91,7 +91,7 @@ void ble_drv_gattc_event_handler_set(mp_obj_t obj, ble_drv_gattc_evt_callback_t void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); -void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); +void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, ble_drv_gattc_char_data_callback_t cb); void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); From 5a7ab4686c06f070c8bc4f861727f29b6013b43d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 1 Apr 2017 16:36:15 +0200 Subject: [PATCH 548/809] nrf5/modules/ubluepy: Adding value data member to the characteristic object. This can hold the value data when gatt client perform a read and value has to be transferred between interrupt and main thread. --- nrf5/modules/ubluepy/modubluepy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index fd44f3a524..60fb49b993 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -128,6 +128,7 @@ typedef struct _ubluepy_characteristic_obj_t { uint8_t props; uint8_t attrs; ubluepy_service_obj_t * p_service; + mp_obj_t value_data; } ubluepy_characteristic_obj_t; typedef struct _ubluepy_descriptor_obj_t { From 276073b494fede2fe235bed981753ce8c2d5672e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 1 Apr 2017 16:39:51 +0200 Subject: [PATCH 549/809] nrf5/modules/ubluepy: Adding callback function to handle read response if gatt client has issued a read request. Also adding method for returning the uuid instance from the object. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 31 ++++++++++++++++--- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index c1cfdd415d..f8e7a29eef 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -78,20 +78,31 @@ STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_ // clear pointer to service s->p_service = NULL; + // clear pointer to char value data + s->value_data = NULL; + return MP_OBJ_FROM_PTR(s); } +void char_data_callback(mp_obj_t self_in, uint16_t length, uint8_t * p_data) { + ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); + self->value_data = mp_obj_new_bytearray(length, p_data); +} + /// \method read() /// Read Characteristic value. /// STATIC mp_obj_t char_read(mp_obj_t self_in) { ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); + + // TODO: free any previous allocation of value_data + ble_drv_attr_c_read(self->p_service->p_periph->conn_handle, self->handle, - 0, - NULL); + self_in, + char_data_callback); - return mp_const_none; + return self->value_data; } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_read_obj, char_read); @@ -130,6 +141,16 @@ STATIC mp_obj_t char_properties(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_get_properties_obj, char_properties); +/// \method uuid() +/// Get UUID instance of the characteristic. +/// +STATIC mp_obj_t char_uuid(mp_obj_t self_in) { + ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); + return MP_OBJ_FROM_PTR(self->p_uuid); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_get_uuid_obj, char_uuid); + + STATIC const mp_map_elem_t ubluepy_characteristic_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)(&ubluepy_characteristic_read_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_write), (mp_obj_t)(&ubluepy_characteristic_write_obj) }, @@ -140,9 +161,9 @@ STATIC const mp_map_elem_t ubluepy_characteristic_locals_dict_table[] = { // Properties { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_characteristic_get_peripheral_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_characteristic_get_uuid_obj) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_properties), (mp_obj_t)(&ubluepy_characteristic_get_properties_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_characteristic_get_uuid_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_properties), (mp_obj_t)(&ubluepy_characteristic_get_properties_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_BROADCAST), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_BROADCAST) }, { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_READ), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_READ) }, From 706bc97c929f23205a0b9a145445d898afa664ed Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 1 Apr 2017 22:32:55 +0200 Subject: [PATCH 550/809] nrf5/modules/ubluepy: Upon advertisment event, also store the advertisment data. --- nrf5/modules/ubluepy/ubluepy_scanner.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index 112b075625..6946fbb5c8 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -55,6 +55,7 @@ STATIC void adv_event_handler(mp_obj_t self_in, uint16_t event_id, ble_drv_adv_d item->addr_type = data->addr_type; item->rssi = data->rssi; + item->data = mp_obj_new_bytearray(data->data_len, data->p_data); mp_obj_list_append(self->adv_reports, item); } From 0887b95bb97be84d2f16f17af97188d8125f9f85 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 1 Apr 2017 22:34:44 +0200 Subject: [PATCH 551/809] nrf5/modules/ubluepy: Expose ubluepy constant objects as externs in modubluepy.h to be able to get access to the local dict tables in order to do a reverse lookup on value to resolve QSTR from external modules in c. --- nrf5/modules/ubluepy/modubluepy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 60fb49b993..b98d39f99b 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -79,6 +79,8 @@ extern const mp_obj_type_t ubluepy_characteristic_type; extern const mp_obj_type_t ubluepy_peripheral_type; extern const mp_obj_type_t ubluepy_scanner_type; extern const mp_obj_type_t ubluepy_scan_entry_type; +extern const mp_obj_type_t ubluepy_constants_type; +extern const mp_obj_type_t ubluepy_constants_ad_types_type; typedef enum { UBLUEPY_UUID_16_BIT = 1, From bb196a2b091fab7a42032086b3bd15f4ae18e3b8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 1 Apr 2017 22:37:39 +0200 Subject: [PATCH 552/809] nrf5/modules/ubluepy: Adding ad_types constants in new object. Linking in ad_types object into the ubluepy.constants local dict. --- nrf5/modules/ubluepy/ubluepy_constants.c | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_constants.c b/nrf5/modules/ubluepy/ubluepy_constants.c index c9980b06bd..6b808905b3 100644 --- a/nrf5/modules/ubluepy/ubluepy_constants.c +++ b/nrf5/modules/ubluepy/ubluepy_constants.c @@ -31,11 +31,57 @@ #include "modubluepy.h" +STATIC const mp_map_elem_t ubluepy_constants_ad_types_locals_dict_table[] = { + // GAP AD Types + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_FLAGS), MP_OBJ_NEW_SMALL_INT(0x01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE), MP_OBJ_NEW_SMALL_INT(0x02) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE), MP_OBJ_NEW_SMALL_INT(0x03) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE), MP_OBJ_NEW_SMALL_INT(0x04) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE), MP_OBJ_NEW_SMALL_INT(0x05) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE), MP_OBJ_NEW_SMALL_INT(0x06) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE), MP_OBJ_NEW_SMALL_INT(0x07) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SHORT_LOCAL_NAME), MP_OBJ_NEW_SMALL_INT(0x08) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_COMPLETE_LOCAL_NAME), MP_OBJ_NEW_SMALL_INT(0x09) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_TX_POWER_LEVEL), MP_OBJ_NEW_SMALL_INT(0x0A) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_CLASS_OF_DEVICE), MP_OBJ_NEW_SMALL_INT(0x0D) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_HASH_C), MP_OBJ_NEW_SMALL_INT(0x0E) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R), MP_OBJ_NEW_SMALL_INT(0x0F) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SECURITY_MANAGER_TK_VALUE), MP_OBJ_NEW_SMALL_INT(0x10) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS), MP_OBJ_NEW_SMALL_INT(0x11) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE), MP_OBJ_NEW_SMALL_INT(0x12) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT), MP_OBJ_NEW_SMALL_INT(0x14) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT), MP_OBJ_NEW_SMALL_INT(0x15) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA), MP_OBJ_NEW_SMALL_INT(0x16) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_PUBLIC_TARGET_ADDRESS), MP_OBJ_NEW_SMALL_INT(0x17) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_RANDOM_TARGET_ADDRESS), MP_OBJ_NEW_SMALL_INT(0x18) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_APPEARANCE), MP_OBJ_NEW_SMALL_INT(0x19) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_ADVERTISING_INTERVAL), MP_OBJ_NEW_SMALL_INT(0x1A) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS), MP_OBJ_NEW_SMALL_INT(0x1B) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_LE_ROLE), MP_OBJ_NEW_SMALL_INT(0x1C) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_HASH_C256), MP_OBJ_NEW_SMALL_INT(0x1D) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256), MP_OBJ_NEW_SMALL_INT(0x1E) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA_32BIT_UUID), MP_OBJ_NEW_SMALL_INT(0x20) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA_128BIT_UUID), MP_OBJ_NEW_SMALL_INT(0x21) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_URI), MP_OBJ_NEW_SMALL_INT(0x24) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_3D_INFORMATION_DATA), MP_OBJ_NEW_SMALL_INT(0x3D) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_MANUFACTURER_SPECIFIC_DATA), MP_OBJ_NEW_SMALL_INT(0xFF) }, +}; + +STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_ad_types_locals_dict, ubluepy_constants_ad_types_locals_dict_table); + +const mp_obj_type_t ubluepy_constants_ad_types_type = { + { &mp_type_type }, + .name = MP_QSTR_ad_types, + .locals_dict = (mp_obj_t)&ubluepy_constants_ad_types_locals_dict +}; + STATIC const mp_map_elem_t ubluepy_constants_locals_dict_table[] = { // GAP events { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_OBJ_NEW_SMALL_INT(16) }, { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_OBJ_NEW_SMALL_INT(17) }, { MP_OBJ_NEW_QSTR(MP_QSTR_UUID_CCCD), MP_OBJ_NEW_SMALL_INT(0x2902) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_ad_types), (mp_obj_t)(&ubluepy_constants_ad_types_type) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_locals_dict, ubluepy_constants_locals_dict_table); From 33b1028b50628ac85b58b2b73f318d18904d50d8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 1 Apr 2017 22:43:54 +0200 Subject: [PATCH 553/809] nrf5/modules/ubluepy: Turn all attributes (addr, addr_type and rssi) to method calls instead of using common .attr callback. Adding getScanData implementation, which parses the advertisment data and returns a list of tuples containing (ad_type, desc, value). Description is generated by peeking into the ad_types local dicts map table, and do a reverse lookup on the value to find the QSTR. --- nrf5/modules/ubluepy/ubluepy_scan_entry.c | 103 +++++++++++++++++----- 1 file changed, 82 insertions(+), 21 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_scan_entry.c b/nrf5/modules/ubluepy/ubluepy_scan_entry.c index d197df4051..bf7d704607 100644 --- a/nrf5/modules/ubluepy/ubluepy_scan_entry.c +++ b/nrf5/modules/ubluepy/ubluepy_scan_entry.c @@ -29,6 +29,9 @@ #include "py/runtime.h" #include "py/objstr.h" #include "py/objlist.h" +#include "py/objarray.h" +#include "py/objtuple.h" +#include "py/qstr.h" #if MICROPY_PY_UBLUEPY_CENTRAL @@ -40,46 +43,104 @@ STATIC void ubluepy_scan_entry_print(const mp_print_t *print, mp_obj_t o, mp_pri mp_printf(print, "ScanEntry"); } -STATIC void ubluepy_scan_entry_attr(mp_obj_t self_in, qstr attr, mp_obj_t *dest) { - if (dest[0] != MP_OBJ_NULL) { - // not load attribute - return; - } +/// \method addr() +/// Return address as text string. +/// +STATIC mp_obj_t scan_entry_get_addr(mp_obj_t self_in) { ubluepy_scan_entry_obj_t *self = MP_OBJ_TO_PTR(self_in); - if (attr == MP_QSTR_addr) { - dest[0] = self->addr; - } else if (attr == MP_QSTR_addr_type) { - dest[0] = mp_obj_new_int(self->addr_type); - } else if (attr == MP_QSTR_rssi) { - dest[0] = mp_obj_new_int(self->rssi); - } - + return self->addr; } +STATIC MP_DEFINE_CONST_FUN_OBJ_1(bluepy_scan_entry_get_addr_obj, scan_entry_get_addr); + +/// \method addr_type() +/// Return address type value. +/// +STATIC mp_obj_t scan_entry_get_addr_type(mp_obj_t self_in) { + ubluepy_scan_entry_obj_t *self = MP_OBJ_TO_PTR(self_in); + return mp_obj_new_int(self->addr_type); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(bluepy_scan_entry_get_addr_type_obj, scan_entry_get_addr_type); + +/// \method rssi() +/// Return RSSI value. +/// +STATIC mp_obj_t scan_entry_get_rssi(mp_obj_t self_in) { + ubluepy_scan_entry_obj_t *self = MP_OBJ_TO_PTR(self_in); + return mp_obj_new_int(self->rssi); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(bluepy_scan_entry_get_rssi_obj, scan_entry_get_rssi); /// \method getScanData() -/// Return list of the scan data tupples. +/// Return list of the scan data tupples (ad_type, description, value) /// -STATIC mp_obj_t scan_entry_get_scan_data(mp_obj_t self_in, mp_obj_t type_in) { +STATIC mp_obj_t scan_entry_get_scan_data(mp_obj_t self_in) { ubluepy_scan_entry_obj_t * self = MP_OBJ_TO_PTR(self_in); - (void)self; - return mp_const_none; + mp_obj_t retval_list = mp_obj_new_list(0, NULL); + + // TODO: check if self->data is set + mp_obj_array_t * data = MP_OBJ_TO_PTR(self->data); + + uint16_t byte_index = 0; + + while (byte_index < data->len) { + mp_obj_tuple_t *t = MP_OBJ_TO_PTR(mp_obj_new_tuple(3, NULL)); + + uint8_t adv_item_len = ((uint8_t * )data->items)[byte_index]; + uint8_t adv_item_type = ((uint8_t * )data->items)[byte_index + 1]; + + mp_obj_t description = mp_const_none; + + mp_map_t *constant_map = mp_obj_dict_get_map(ubluepy_constants_ad_types_type.locals_dict); + mp_map_elem_t *ad_types_table = MP_OBJ_TO_PTR(constant_map->table); + + uint16_t num_of_elements = constant_map->used; + + for (uint16_t i = 0; i < num_of_elements; i++) { + mp_map_elem_t element = (mp_map_elem_t)*ad_types_table; + ad_types_table++; + uint16_t element_value = mp_obj_get_int(element.value); + + if (adv_item_type == element_value) { + qstr key_qstr = MP_OBJ_QSTR_VALUE(element.key); + const char * text = qstr_str(key_qstr); + size_t len = qstr_len(key_qstr); + + vstr_t vstr; + vstr_init(&vstr, len); + vstr_printf(&vstr, "%s", text); + description = mp_obj_new_str(vstr.buf, vstr.len, false); + vstr_clear(&vstr); + } + } + + t->items[0] = MP_OBJ_NEW_SMALL_INT(adv_item_type); + t->items[1] = description; + t->items[2] = mp_obj_new_bytearray(adv_item_len - 1, + &((uint8_t * )data->items)[byte_index + 2]); + mp_obj_list_append(retval_list, MP_OBJ_FROM_PTR(t)); + + byte_index += adv_item_len + 1; + } + + return retval_list; } -STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_scan_entry_get_scan_data_obj, scan_entry_get_scan_data); +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_scan_entry_get_scan_data_obj, scan_entry_get_scan_data); STATIC const mp_map_elem_t ubluepy_scan_entry_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_addr), (mp_obj_t)(&bluepy_scan_entry_get_addr_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_addr_type), (mp_obj_t)(&bluepy_scan_entry_get_addr_type_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_rssi), (mp_obj_t)(&bluepy_scan_entry_get_rssi_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_getScanData), (mp_obj_t)(&ubluepy_scan_entry_get_scan_data_obj) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_scan_entry_locals_dict, ubluepy_scan_entry_locals_dict_table); - const mp_obj_type_t ubluepy_scan_entry_type = { { &mp_type_type }, .name = MP_QSTR_ScanEntry, .print = ubluepy_scan_entry_print, - .locals_dict = (mp_obj_t)&ubluepy_scan_entry_locals_dict, - .attr = ubluepy_scan_entry_attr + .locals_dict = (mp_obj_t)&ubluepy_scan_entry_locals_dict }; #endif // MICROPY_PY_UBLUEPY_CENTRAL From 9568e07159d584ff22046e5926342cd7ebaed071 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 1 Apr 2017 22:45:11 +0200 Subject: [PATCH 554/809] nrf5/examples: Adding example on how to use the ubluepy Scanner object in order to scan for a device name and find the address of the device. This can subsequently be used to perform a Central role connect() using the Peripheral object. --- nrf5/examples/ubluepy_scan.py | 38 +++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 nrf5/examples/ubluepy_scan.py diff --git a/nrf5/examples/ubluepy_scan.py b/nrf5/examples/ubluepy_scan.py new file mode 100644 index 0000000000..c3a054d587 --- /dev/null +++ b/nrf5/examples/ubluepy_scan.py @@ -0,0 +1,38 @@ +from ubluepy import Scanner + +def bytes_to_str(bytes): + string = "" + for b in bytes: + string += chr(b) + return string + +def get_device_names(scan_entries): + dev_names = [] + for e in scan_entries: + scan = e.getScanData() + if scan: + for s in scan: + if s[0] == 9: + dev_names.append((e, bytes_to_str(s[2]))) + return dev_names + +def find_device_by_name(name): + s = Scanner() + scan_res = s.scan(100) + + device_names = get_device_names(scan_res) + for dev in device_names: + if name == dev[1]: + return dev[0] + +# >>> res = find_device_by_name("micr") +# >>> if res: +# ... print("address:", res.addr()) +# ... print("address type:", res.addr_type()) +# ... print("rssi:", res.rssi()) +# ... +# ... +# ... +# address: c2:73:61:89:24:45 +# address type: 1 +# rssi: -26 From 460f6dee507f8ac23f6cdfd4b8b41fcbd511b043 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 1 Apr 2017 22:50:37 +0200 Subject: [PATCH 555/809] nrf5/examples: Updating ubluepy scan example to use constant value from ubluepy instead of hardcoded value. --- nrf5/examples/ubluepy_scan.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/examples/ubluepy_scan.py b/nrf5/examples/ubluepy_scan.py index c3a054d587..ab11661cca 100644 --- a/nrf5/examples/ubluepy_scan.py +++ b/nrf5/examples/ubluepy_scan.py @@ -1,4 +1,4 @@ -from ubluepy import Scanner +from ubluepy import Scanner, constants def bytes_to_str(bytes): string = "" @@ -12,7 +12,7 @@ def get_device_names(scan_entries): scan = e.getScanData() if scan: for s in scan: - if s[0] == 9: + if s[0] == constants.ad_types.AD_TYPE_COMPLETE_LOCAL_NAME: dev_names.append((e, bytes_to_str(s[2]))) return dev_names From 84e5b828ea642203e965075d7c414b7064a76f4f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 00:30:16 +0200 Subject: [PATCH 556/809] nrf5/bluetooth: Moving central code inside central bluetooth stack defines to make peripheral only code compile again. --- nrf5/bluetooth/ble_drv.c | 49 +++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 71eb09bd3a..0fb63f5e7c 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -75,20 +75,26 @@ static volatile bool m_adv_in_progress; static volatile bool m_tx_in_progress; static ble_drv_gap_evt_callback_t gap_event_handler; -static ble_drv_adv_evt_callback_t adv_event_handler; static ble_drv_gatts_evt_callback_t gatts_event_handler; + +#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) +static ble_drv_adv_evt_callback_t adv_event_handler; static ble_drv_gattc_evt_callback_t gattc_event_handler; static ble_drv_disc_add_service_callback_t disc_add_service_handler; static ble_drv_disc_add_char_callback_t disc_add_char_handler; static ble_drv_gattc_char_data_callback_t gattc_char_data_handle; +#endif static mp_obj_t mp_gap_observer; -static mp_obj_t mp_adv_observer; static mp_obj_t mp_gatts_observer; + +#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) +static mp_obj_t mp_adv_observer; static mp_obj_t mp_gattc_observer; static mp_obj_t mp_gattc_disc_service_observer; static mp_obj_t mp_gattc_disc_char_observer; static mp_obj_t mp_gattc_char_data_observer; +#endif #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" @@ -621,24 +627,6 @@ void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, ui } -void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, ble_drv_gattc_char_data_callback_t cb) { - - mp_gattc_char_data_observer = obj; - gattc_char_data_handle = cb; - - uint32_t err_code = sd_ble_gattc_read(conn_handle, - handle, - 0); - if (err_code != 0) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can not read attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); - } - - while (gattc_char_data_handle != NULL) { - ; - } -} - void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { ble_gatts_value_t gatts_value; memset(&gatts_value, 0, sizeof(gatts_value)); @@ -689,6 +677,8 @@ void ble_drv_gatts_event_handler_set(mp_obj_t obj, ble_drv_gatts_evt_callback_t gatts_event_handler = evt_handler; } +#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) + void ble_drv_gattc_event_handler_set(mp_obj_t obj, ble_drv_gattc_evt_callback_t evt_handler) { mp_gattc_observer = obj; gattc_event_handler = evt_handler; @@ -699,7 +689,24 @@ void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt adv_event_handler = evt_handler; } -#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) + +void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, ble_drv_gattc_char_data_callback_t cb) { + + mp_gattc_char_data_observer = obj; + gattc_char_data_handle = cb; + + uint32_t err_code = sd_ble_gattc_read(conn_handle, + handle, + 0); + if (err_code != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not read attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); + } + + while (gattc_char_data_handle != NULL) { + ; + } +} void ble_drv_scan_start(void) { SD_TEST_OR_ENABLE(); From 5f645b6c8ea27b041e5b259fac2a86b3b7647eaa Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 00:31:28 +0200 Subject: [PATCH 557/809] nrf5/modules/ubluepy: Adding compile guard for UBLUEPY_CENTRAL around the char_read() call to ble_drv_attr_c_read(). --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index f8e7a29eef..1a68e070b0 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -95,6 +95,7 @@ void char_data_callback(mp_obj_t self_in, uint16_t length, uint8_t * p_data) { STATIC mp_obj_t char_read(mp_obj_t self_in) { ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); +#if MICROPY_PY_UBLUEPY_CENTRAL // TODO: free any previous allocation of value_data ble_drv_attr_c_read(self->p_service->p_periph->conn_handle, @@ -103,6 +104,10 @@ STATIC mp_obj_t char_read(mp_obj_t self_in) { char_data_callback); return self->value_data; +#else + (void)self; + return mp_const_none; +#endif } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_read_obj, char_read); From 52c07e7cb235e6fec2c2b86aedc22ca09bada002 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 15:45:02 +0200 Subject: [PATCH 558/809] nrf5/bluetooth: Cleaning up stack enable function, to not set device name twice. Also, adding support for setting custom advertisment data. --- nrf5/bluetooth/ble_drv.c | 49 ++++++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 0fb63f5e7c..3ea065710f 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -189,16 +189,11 @@ uint32_t ble_drv_stack_enable(void) { const char device_name[] = "micr"; - err_code = sd_ble_gap_device_name_set(&sec_mode, - (const uint8_t *)device_name, - strlen(device_name)); - - if (sd_ble_gap_device_name_set(&sec_mode, - (const uint8_t *)device_name, - strlen(device_name)) != 0) { - - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Cannot set GAP parameters.")); + if ((err_code = sd_ble_gap_device_name_set(&sec_mode, + (const uint8_t *)device_name, + strlen(device_name))) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Cannot apply GAP parameters.")); } // set connection parameters @@ -447,13 +442,16 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { byte_pos += p_adv_params->device_name_len; } - // set flags, default to disc mode - adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + BLE_AD_TYPE_FLAGS_DATA_SIZE); - byte_pos += BLE_ADV_LENGTH_FIELD_SIZE; - adv_data[byte_pos] = BLE_GAP_AD_TYPE_FLAGS; - byte_pos += BLE_AD_TYPE_FLAGS_DATA_SIZE; - adv_data[byte_pos] = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE; - byte_pos += 1; + // Add FLAGS only if manually controlled data has not been used. + if (p_adv_params->data_len == 0) { + // set flags, default to disc mode + adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + BLE_AD_TYPE_FLAGS_DATA_SIZE); + byte_pos += BLE_ADV_LENGTH_FIELD_SIZE; + adv_data[byte_pos] = BLE_GAP_AD_TYPE_FLAGS; + byte_pos += BLE_AD_TYPE_FLAGS_DATA_SIZE; + adv_data[byte_pos] = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE; + byte_pos += 1; + } if (p_adv_params->num_of_services > 0) { @@ -571,10 +569,21 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { } } + if ((p_adv_params->data_len > 0) && (p_adv_params->p_data != NULL)) { + if (p_adv_params->data_len + byte_pos > BLE_GAP_ADV_MAX_SIZE) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not fit data into the advertisment packet.")); + } + + memcpy(adv_data, p_adv_params->p_data, p_adv_params->data_len); + byte_pos += p_adv_params->data_len; + } + // scan response data not set - if (sd_ble_gap_adv_data_set(adv_data, byte_pos, NULL, 0) != 0) { + uint32_t err_code; + if ((err_code = sd_ble_gap_adv_data_set(adv_data, byte_pos, NULL, 0)) != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can not apply advertisment data.")); + "Can not apply advertisment data. status: 0x" HEX2_FMT, (uint16_t)err_code)); } BLE_DRIVER_LOG("Set Adv data size: " UINT_FMT "\n", byte_pos); @@ -598,7 +607,7 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { #endif m_adv_in_progress = false; - uint32_t err_code = sd_ble_gap_adv_start(&m_adv_params); + err_code = sd_ble_gap_adv_start(&m_adv_params); if (err_code != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not start advertisment. status: 0x" HEX2_FMT, (uint16_t)err_code)); From 58238a43b3aed2ab5e8cc40a0dc6e84cd90119d2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 15:48:32 +0200 Subject: [PATCH 559/809] nrf5/modules/ubluepy: Adding new members to the ublupy advertisment parameters, to hold custom data payload if set. --- nrf5/modules/ubluepy/modubluepy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index b98d39f99b..42a1ae9408 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -148,6 +148,8 @@ typedef struct _ubluepy_advertise_data_t { uint8_t device_name_len; mp_obj_t * p_services; uint8_t num_of_services; + uint8_t * p_data; + uint8_t data_len; } ubluepy_advertise_data_t; typedef struct _ubluepy_scanner_obj_t { From f7fbf55a455aca1b4ef48c70a113893dcfc54efc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 15:50:07 +0200 Subject: [PATCH 560/809] nrf5/modules/ubluepy: Open up Peripheral advertise method to pass custom data to the bluetooth driver. Allowing method to allow kwargs only if no args is set. To support setting data kwarg only. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index a0d30c51b1..48748f75fc 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -210,14 +210,20 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, } if (data_obj != mp_const_none) { + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(data_obj, &bufinfo, MP_BUFFER_READ); + if (bufinfo.len > 0) { + adv_data.p_data = bufinfo.buf; + adv_data.data_len = bufinfo.len; + } } (void)ble_drv_advertise_data(&adv_data); return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_KW(ubluepy_peripheral_advertise_obj, 1, peripheral_advertise); +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(ubluepy_peripheral_advertise_obj, 0, peripheral_advertise); /// \method disconnect() /// disconnect connection. From c8097eb470a4d57d57c7830afd7078bfb5e1246e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 15:51:00 +0200 Subject: [PATCH 561/809] nrf5/examples: Adding python eddystone example using ubluepy api. --- nrf5/examples/ubluepy_eddystone.py | 58 ++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 nrf5/examples/ubluepy_eddystone.py diff --git a/nrf5/examples/ubluepy_eddystone.py b/nrf5/examples/ubluepy_eddystone.py new file mode 100644 index 0000000000..c004e6c70f --- /dev/null +++ b/nrf5/examples/ubluepy_eddystone.py @@ -0,0 +1,58 @@ +from ubluepy import Peripheral, constants + +BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE = const(0x02) +BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED = const(0x04) + +BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE = const(BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) + +EDDYSTONE_FRAME_TYPE_URL = const(0x10) +EDDYSTONE_URL_PREFIX_HTTP_WWW = const(0x00) # "http://www". +EDDYSTONE_URL_SUFFIX_DOT_COM = const(0x01) # ".com" + +def string_to_binarray(text): + b = bytearray([]) + for c in text: + b.append(ord(c)) + return b + +def gen_ad_type_content(ad_type, data): + b = bytearray(1) + b.append(ad_type) + b.extend(data) + b[0] = len(b) - 1 + return b + +def generate_eddystone_adv_packet(url): + # flags + disc_mode = bytearray([BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE]) + packet_flags = gen_ad_type_content(constants.ad_types.AD_TYPE_FLAGS, disc_mode) + + # 16-bit uuid + uuid = bytearray([0xAA, 0xFE]) + packet_uuid16 = gen_ad_type_content(constants.ad_types.AD_TYPE_16BIT_SERVICE_UUID_COMPLETE, uuid) + + # eddystone data + rssi = 0xEE # -18 dB, approx signal strength at 0m. + eddystone_data = bytearray([]) + eddystone_data.append(EDDYSTONE_FRAME_TYPE_URL) + eddystone_data.append(rssi) + eddystone_data.append(EDDYSTONE_URL_PREFIX_HTTP_WWW) + eddystone_data.extend(string_to_binarray(url)) + eddystone_data.append(EDDYSTONE_URL_SUFFIX_DOT_COM) + + # service data + service_data = uuid + eddystone_data + packet_service_data = gen_ad_type_content(constants.ad_types.AD_TYPE_SERVICE_DATA, service_data) + + # generate advertisment packet + packet = bytearray([]) + packet.extend(packet_flags) + packet.extend(packet_uuid16) + packet.extend(packet_service_data) + + return packet + +def start(): + adv_packet = generate_eddystone_adv_packet("micropython") + p = Peripheral() + p.advertise(data=adv_packet) \ No newline at end of file From c7f0069aacc68bf6b0f65d35f09d1e2f5b54bcdb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 16:14:48 +0200 Subject: [PATCH 562/809] nrf5/bluetooth: Removing advertise from ble module. Removing help text as well. --- nrf5/bluetooth/help_sd.h | 1 - nrf5/bluetooth/modble.c | 9 --------- 2 files changed, 10 deletions(-) diff --git a/nrf5/bluetooth/help_sd.h b/nrf5/bluetooth/help_sd.h index fa48d4a578..a3d49c5295 100644 --- a/nrf5/bluetooth/help_sd.h +++ b/nrf5/bluetooth/help_sd.h @@ -36,7 +36,6 @@ "available:\n" \ " ble.enable() -- enable softdevice\n" \ " ble.disable() -- disable softdevice\n" \ -" ble.advertise() -- Start advertising Eddystone beacon\n" \ "\n" #else diff --git a/nrf5/bluetooth/modble.c b/nrf5/bluetooth/modble.c index 358ef70830..abf05a25e5 100644 --- a/nrf5/bluetooth/modble.c +++ b/nrf5/bluetooth/modble.c @@ -67,18 +67,10 @@ mp_obj_t ble_obj_address_print(void) { return mp_const_none; } -/// \method advertise() -/// Bluetooth Low Energy advertise. -mp_obj_t ble_obj_advertise(void) { - ble_drv_advertise(); - return mp_const_none; -} - STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_enable_obj, ble_obj_enable); STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_disable_obj, ble_obj_disable); STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_enabled_obj, ble_obj_enabled); STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_address_print_obj, ble_obj_address_print); -STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_advertise_obj, ble_obj_advertise); STATIC const mp_map_elem_t ble_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ble) }, @@ -86,7 +78,6 @@ STATIC const mp_map_elem_t ble_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_disable), (mp_obj_t)&ble_obj_disable_obj}, { MP_OBJ_NEW_QSTR(MP_QSTR_enabled), (mp_obj_t)&ble_obj_enabled_obj}, { MP_OBJ_NEW_QSTR(MP_QSTR_address_print), (mp_obj_t)&ble_obj_address_print_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)&ble_obj_advertise_obj}, }; From e3773e899f7096401e4392d8f88cbc235bab15bf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 16:17:39 +0200 Subject: [PATCH 563/809] nrf5/bluetooth: Updating help text for ble module to also list up enabled() function which queries the bluetooth stack on whether it is enabled or not. --- nrf5/bluetooth/help_sd.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nrf5/bluetooth/help_sd.h b/nrf5/bluetooth/help_sd.h index a3d49c5295..b854fda060 100644 --- a/nrf5/bluetooth/help_sd.h +++ b/nrf5/bluetooth/help_sd.h @@ -34,8 +34,9 @@ #define HELP_TEXT_SD \ "If compiled with SD= the additional commands are\n" \ "available:\n" \ -" ble.enable() -- enable softdevice\n" \ -" ble.disable() -- disable softdevice\n" \ +" ble.enable() -- enable bluetooth stack\n" \ +" ble.disable() -- disable bluetooth stack\n" \ +" ble.enabled() -- check whether bluetooth stack is enabled\n" \ "\n" #else From 1402574b7d9bd33339df3ca43acdcfeef079e905 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 16:39:14 +0200 Subject: [PATCH 564/809] nrf5/bluetooth: Adding new structure which can hold local address. Updating api prototype for ble_drv_address_get with a address structure by reference. --- nrf5/bluetooth/ble_drv.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 9671ab695b..a717cf564c 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -32,6 +32,11 @@ #include "modubluepy.h" +typedef struct { + uint8_t addr[6]; + uint8_t addr_type; +} ble_drv_addr_t; + typedef struct { uint8_t * p_peer_addr; uint8_t addr_type; @@ -71,7 +76,7 @@ void ble_drv_stack_disable(void); uint8_t ble_drv_stack_enabled(void); -void ble_drv_address_get(void); +void ble_drv_address_get(ble_drv_addr_t * p_addr); void ble_drv_advertise(void); From 7e52da7ccb6214f8b53cc5c5c2f3faeb42441ff6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 16:41:08 +0200 Subject: [PATCH 565/809] nrf5/bluetooth: Update ble_drv_address_get to new api which pass in a address struct to fill by reference. Updating implementation to copy the address data. Also ensuring that the bluetooth stack has been enabled before fetching the address from the bluetooth stack. --- nrf5/bluetooth/ble_drv.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 3ea065710f..490c2b600c 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -227,13 +227,21 @@ uint8_t ble_drv_stack_enabled(void) { return is_enabled; } -void ble_drv_address_get(void) { +void ble_drv_address_get(ble_drv_addr_t * p_addr) { + SD_TEST_OR_ENABLE(); + ble_gap_addr_t local_ble_addr; #if (BLUETOOTH_SD != 132) uint32_t err_code = sd_ble_gap_address_get(&local_ble_addr); #else uint32_t err_code = sd_ble_gap_addr_get(&local_ble_addr); #endif + + if (err_code != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not query for the device address.")); + } + BLE_DRIVER_LOG("ble address, type: " HEX2_FMT ", " \ "address: " HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT ":" \ HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT "\n", \ @@ -241,7 +249,8 @@ void ble_drv_address_get(void) { local_ble_addr.addr[5], local_ble_addr.addr[4], local_ble_addr.addr[3], \ local_ble_addr.addr[2], local_ble_addr.addr[1], local_ble_addr.addr[0]); - (void)err_code; + p_addr->addr_type = local_ble_addr.addr_type; + memcpy(p_addr->addr, local_ble_addr.addr, 6); } void ble_drv_advertise(void) { From 6fcb0a40e9d8317554015fee5e6a19044f7f3e89 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 16:43:16 +0200 Subject: [PATCH 566/809] nrf5/bluetooth: Renaming the ble module method address_print() to address(), as it will now return a string of the resolved local address. Updating the function to create a string out the local address and return this. --- nrf5/bluetooth/modble.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/nrf5/bluetooth/modble.c b/nrf5/bluetooth/modble.c index abf05a25e5..565b88bebd 100644 --- a/nrf5/bluetooth/modble.c +++ b/nrf5/bluetooth/modble.c @@ -60,24 +60,38 @@ mp_obj_t ble_obj_enabled(void) { return MP_OBJ_NEW_SMALL_INT(enabled); } -/// \method address_print() -/// Print device address. -mp_obj_t ble_obj_address_print(void) { - ble_drv_address_get(); - return mp_const_none; +/// \method address() +/// Return device address as text string. +mp_obj_t ble_obj_address(void) { + ble_drv_addr_t local_addr; + ble_drv_address_get(&local_addr); + + vstr_t vstr; + vstr_init(&vstr, 17); + + vstr_printf(&vstr, ""HEX2_FMT":"HEX2_FMT":"HEX2_FMT":" \ + HEX2_FMT":"HEX2_FMT":"HEX2_FMT"", + local_addr.addr[5], local_addr.addr[4], local_addr.addr[3], + local_addr.addr[2], local_addr.addr[1], local_addr.addr[0]); + + mp_obj_t mac_str = mp_obj_new_str(vstr.buf, vstr.len, false); + + vstr_clear(&vstr); + + return mac_str; } STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_enable_obj, ble_obj_enable); STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_disable_obj, ble_obj_disable); STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_enabled_obj, ble_obj_enabled); -STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_address_print_obj, ble_obj_address_print); +STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_address_obj, ble_obj_address); STATIC const mp_map_elem_t ble_module_globals_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ble) }, { MP_OBJ_NEW_QSTR(MP_QSTR_enable), (mp_obj_t)&ble_obj_enable_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_disable), (mp_obj_t)&ble_obj_disable_obj}, { MP_OBJ_NEW_QSTR(MP_QSTR_enabled), (mp_obj_t)&ble_obj_enabled_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_address_print), (mp_obj_t)&ble_obj_address_print_obj}, + { MP_OBJ_NEW_QSTR(MP_QSTR_address), (mp_obj_t)&ble_obj_address_obj}, }; From e5fc082366c2c8486ea5ded61564b60afd090dcf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 16:44:37 +0200 Subject: [PATCH 567/809] nrf5/help: Updating ble module help description to also include the address method. --- nrf5/bluetooth/help_sd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/bluetooth/help_sd.h b/nrf5/bluetooth/help_sd.h index b854fda060..2dde1a9e91 100644 --- a/nrf5/bluetooth/help_sd.h +++ b/nrf5/bluetooth/help_sd.h @@ -37,6 +37,7 @@ " ble.enable() -- enable bluetooth stack\n" \ " ble.disable() -- disable bluetooth stack\n" \ " ble.enabled() -- check whether bluetooth stack is enabled\n" \ +" ble.address() -- return device address as text string\n" \ "\n" #else From ce6221ef61b33780e21b202be352c840e1c3848e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 16:55:47 +0200 Subject: [PATCH 568/809] nrf5/bluetooth: Removing legacy advertise function in the bluetooth driver, which only did a hardcoded eddystone beacone advertisment. --- nrf5/bluetooth/ble_drv.c | 52 ---------------------------------------- nrf5/bluetooth/ble_drv.h | 2 -- 2 files changed, 54 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 490c2b600c..f71ef09a51 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -43,14 +43,6 @@ #define BLE_DRIVER_LOG(...) #endif -#define EDDYSTONE_UUID 0xFEAA // UUID for Eddystone beacons, Big Endian. - -// URL Frame Type, fixed at 0x10. -// RSSI, 0xEE = -18 dB is the approximate signal strength at 0 m. -// URL prefix, 0x00 = "http://www". -// URL -// URL suffix, 0x01 = ".com" -#define EDDYSTONE_DATA 0x10, 0xEE, 0x00, 'm', 'i', 'c', 'r', 'o', 'p', 'y', 't', 'h', 'o', 'n', 0x01 #define BLE_ADV_LENGTH_FIELD_SIZE 1 #define BLE_ADV_AD_TYPE_FIELD_SIZE 1 #define BLE_AD_TYPE_FLAGS_DATA_SIZE 1 @@ -253,50 +245,6 @@ void ble_drv_address_get(ble_drv_addr_t * p_addr) { memcpy(p_addr->addr, local_ble_addr.addr, 6); } -void ble_drv_advertise(void) { - ble_uuid_t adv_uuids[] = {{.uuid = EDDYSTONE_UUID, .type = BLE_UUID_TYPE_BLE}}; - uint8_t encoded_size; - uint8_t uuid_encoded[2]; - uint32_t err_code = sd_ble_uuid_encode(&adv_uuids[0], &encoded_size, uuid_encoded); - (void)err_code; - - BLE_DRIVER_LOG("Encoded UUID size: " UINT_FMT ": result: " HEX2_FMT "\n", encoded_size, (uint16_t)err_code); - BLE_DRIVER_LOG("Encoded UUID: " HEX2_FMT " " HEX2_FMT "\n", uuid_encoded[0], uuid_encoded[1]); - - uint8_t eddystone_data[] = {EDDYSTONE_DATA}; // Temp buffer to calculate the size. - - uint8_t adv_data[] = { - (uint8_t)(BLE_ADV_AD_TYPE_FIELD_SIZE + BLE_AD_TYPE_FLAGS_DATA_SIZE), - BLE_GAP_AD_TYPE_FLAGS, - BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE, - 3, - BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE, - uuid_encoded[0], uuid_encoded[1], - (uint8_t)(BLE_ADV_AD_TYPE_FIELD_SIZE + sizeof(eddystone_data) + 2), - BLE_GAP_AD_TYPE_SERVICE_DATA, - uuid_encoded[0], uuid_encoded[1], - EDDYSTONE_DATA - }; - - // Scan response data not set. - err_code = sd_ble_gap_adv_data_set(adv_data, sizeof(adv_data), NULL, 0); - BLE_DRIVER_LOG("Set Adv data status: " UINT_FMT ", size: " UINT_FMT "\n", (uint16_t)err_code, sizeof(adv_data)); - - ble_gap_adv_params_t m_adv_params; - - // Initialize advertising params. - memset(&m_adv_params, 0, sizeof(m_adv_params)); - m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_NONCONN_IND; - m_adv_params.p_peer_addr = NULL; // Undirected advertisement. - m_adv_params.fp = BLE_GAP_ADV_FP_ANY; - m_adv_params.interval = NON_CONNECTABLE_ADV_INTERVAL; - m_adv_params.timeout = APP_CFG_NON_CONN_ADV_TIMEOUT; - - err_code = sd_ble_gap_adv_start(&m_adv_params); - - BLE_DRIVER_LOG("Advertisment start status: " UINT_FMT "\n", (uint16_t)err_code); -} - bool ble_drv_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx) { SD_TEST_OR_ENABLE(); diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index a717cf564c..40c38576ba 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -78,8 +78,6 @@ uint8_t ble_drv_stack_enabled(void); void ble_drv_address_get(ble_drv_addr_t * p_addr); -void ble_drv_advertise(void); - bool ble_drv_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx); bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj); From 0559be4ffc74ae0b8a28837d4155cfbcb2588860 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 2 Apr 2017 18:34:56 +0200 Subject: [PATCH 569/809] nrf5/bluetooth: Adding possibility to configure whether advertisment should be connectable or not. --- nrf5/bluetooth/ble_drv.c | 6 +++++- nrf5/bluetooth/ble_uart.c | 2 ++ nrf5/examples/ubluepy_eddystone.py | 2 +- nrf5/modules/ubluepy/modubluepy.h | 1 + nrf5/modules/ubluepy/ubluepy_peripheral.c | 11 +++++++++-- 5 files changed, 18 insertions(+), 4 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index f71ef09a51..45b07f18ca 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -548,7 +548,11 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { // initialize advertising params memset(&m_adv_params, 0, sizeof(m_adv_params)); - m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND; + if (p_adv_params->connectable) { + m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND; + } else { + m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_NONCONN_IND; + } m_adv_params.p_peer_addr = NULL; // undirected advertisement m_adv_params.fp = BLE_GAP_ADV_FP_ANY; m_adv_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS); // approx 8 ms diff --git a/nrf5/bluetooth/ble_uart.c b/nrf5/bluetooth/ble_uart.c index b3bad7c41f..f9a88fbccc 100644 --- a/nrf5/bluetooth/ble_uart.c +++ b/nrf5/bluetooth/ble_uart.c @@ -213,6 +213,8 @@ void ble_uart_init0(void) { m_rx_ring_buffer.end = 0; m_rx_ring_buffer.elems = m_rx_ring_buffer_data; + adv_data.connectable = true; + (void)ble_drv_advertise_data(&adv_data); while (m_cccd_enabled != true) { diff --git a/nrf5/examples/ubluepy_eddystone.py b/nrf5/examples/ubluepy_eddystone.py index c004e6c70f..c8abd5aea6 100644 --- a/nrf5/examples/ubluepy_eddystone.py +++ b/nrf5/examples/ubluepy_eddystone.py @@ -55,4 +55,4 @@ def generate_eddystone_adv_packet(url): def start(): adv_packet = generate_eddystone_adv_packet("micropython") p = Peripheral() - p.advertise(data=adv_packet) \ No newline at end of file + p.advertise(data=adv_packet, connectable=False) \ No newline at end of file diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 42a1ae9408..1560fa0467 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -150,6 +150,7 @@ typedef struct _ubluepy_advertise_data_t { uint8_t num_of_services; uint8_t * p_data; uint8_t data_len; + bool connectable; } ubluepy_advertise_data_t; typedef struct _ubluepy_scanner_obj_t { diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 48748f75fc..5670933289 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -169,14 +169,15 @@ STATIC mp_obj_t peripheral_set_conn_handler(mp_obj_t self_in, mp_obj_t func) { } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_set_conn_handler_obj, peripheral_set_conn_handler); -/// \method advertise(device_name, [service=[service1, service2, ...]], [data=bytearray]) -/// Start advertising. +/// \method advertise(device_name, [service=[service1, service2, ...]], [data=bytearray], [connectable=True]) +/// Start advertising. Connectable advertisment type by default. /// STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { static const mp_arg_t allowed_args[] = { { MP_QSTR_device_name, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_services, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_data, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_connectable, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, }; // parse args @@ -187,6 +188,7 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, mp_obj_t device_name_obj = args[0].u_obj; mp_obj_t service_obj = args[1].u_obj; mp_obj_t data_obj = args[2].u_obj; + mp_obj_t connectable_obj = args[3].u_obj; ubluepy_advertise_data_t adv_data; memset(&adv_data, 0, sizeof(ubluepy_advertise_data_t)); @@ -219,6 +221,11 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, } } + adv_data.connectable = true; + if (connectable_obj != mp_const_none && !(mp_obj_is_true(connectable_obj))) { + adv_data.connectable = false; + } + (void)ble_drv_advertise_data(&adv_data); return mp_const_none; From 46c21ff6ba76e114e0b7bb2bb5c6806336c9fe01 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 4 Apr 2017 20:24:43 +0200 Subject: [PATCH 570/809] nrf5/modules/ubluepy: Adding support for starting advertisment from BLE UART REPL, by delaying registration of gatt/gatts and gattc handlers until needed in advertise or connect. If non connectable advertisment is selected, handlers in peripheral new is not anymore overriding the other peripheral instances which has set the callbacks. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 5670933289..d038b3a960 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -117,12 +117,6 @@ STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_ ubluepy_peripheral_obj_t *s = m_new_obj(ubluepy_peripheral_obj_t); s->base.type = type; - ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(s), gap_event_handler); - ble_drv_gatts_event_handler_set(MP_OBJ_FROM_PTR(s), gatts_event_handler); -#if MICROPY_PY_UBLUEPY_CENTRAL - ble_drv_gattc_event_handler_set(MP_OBJ_FROM_PTR(s), gattc_event_handler); -#endif - s->delegate = mp_const_none; s->conn_handler = mp_const_none; s->notif_handler = mp_const_none; @@ -180,6 +174,8 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, { MP_QSTR_connectable, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, }; + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + // parse args mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); @@ -224,6 +220,9 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, adv_data.connectable = true; if (connectable_obj != mp_const_none && !(mp_obj_is_true(connectable_obj))) { adv_data.connectable = false; + } else { + ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(self), gap_event_handler); + ble_drv_gatts_event_handler_set(MP_OBJ_FROM_PTR(self), gatts_event_handler); } (void)ble_drv_advertise_data(&adv_data); @@ -269,6 +268,7 @@ STATIC mp_obj_t peripheral_get_services(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_get_services_obj, peripheral_get_services); +#if MICROPY_PY_UBLUEPY_CENTRAL void static disc_add_service(mp_obj_t self, ble_drv_service_data_t * p_service_data) { ubluepy_service_obj_t * p_service = m_new_obj(ubluepy_service_obj_t); @@ -354,6 +354,8 @@ STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { ; } + ble_drv_gattc_event_handler_set(MP_OBJ_FROM_PTR(s), gattc_event_handler); + bool retval = ble_drv_discover_services(self, self->conn_handle, disc_add_service); if (retval != true) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, @@ -383,6 +385,7 @@ STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_connect_obj, peripheral_connect); +#endif STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, From 31feea45114fe1a881271001bb58fede65efe360 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 4 Apr 2017 21:22:49 +0200 Subject: [PATCH 571/809] nrf5/bluetooth: Adding function to stop advertisment if onging --- nrf5/bluetooth/ble_drv.c | 22 +++++++++++++--------- nrf5/bluetooth/ble_drv.h | 2 ++ 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 45b07f18ca..89daf06e1a 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -553,21 +553,14 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { } else { m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_NONCONN_IND; } + m_adv_params.p_peer_addr = NULL; // undirected advertisement m_adv_params.fp = BLE_GAP_ADV_FP_ANY; m_adv_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS); // approx 8 ms m_adv_params.timeout = 0; // infinite advertisment -#if (BLUETOOTH_SD == 132) - if (m_adv_in_progress == true) { - if (sd_ble_gap_adv_stop() != 0) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Can not stop advertisment.")); - } - } -#endif + ble_drv_advertise_stop(); - m_adv_in_progress = false; err_code = sd_ble_gap_adv_start(&m_adv_params); if (err_code != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, @@ -579,6 +572,17 @@ bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) { return true; } +void ble_drv_advertise_stop(void) { + if (m_adv_in_progress == true) { + uint32_t err_code; + if ((err_code = sd_ble_gap_adv_stop()) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not stop advertisment. status: 0x" HEX2_FMT, (uint16_t)err_code)); + } + } + m_adv_in_progress = false; +} + void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { ble_gatts_value_t gatts_value; memset(&gatts_value, 0, sizeof(gatts_value)); diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 40c38576ba..4ebc249023 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -86,6 +86,8 @@ bool ble_drv_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj); bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params); +void ble_drv_advertise_stop(void); + void ble_drv_gap_event_handler_set(mp_obj_t obs, ble_drv_gap_evt_callback_t evt_handler); void ble_drv_gatts_event_handler_set(mp_obj_t obj, ble_drv_gatts_evt_callback_t evt_handler); From 587c6277c421f210e9d08ba2d2712388312ac5fb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 4 Apr 2017 21:25:28 +0200 Subject: [PATCH 572/809] nrf5/modules/ubluepy: Adding method Peripheral object to stop any ongoing advertisment. Adding compile guard to only include advertise and advertise_stop if peripheral role is compiled in. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index d038b3a960..3d434ad882 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -163,6 +163,8 @@ STATIC mp_obj_t peripheral_set_conn_handler(mp_obj_t self_in, mp_obj_t func) { } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_set_conn_handler_obj, peripheral_set_conn_handler); +#if MICROPY_PY_UBLUEPY_PERIPHERAL + /// \method advertise(device_name, [service=[service1, service2, ...]], [data=bytearray], [connectable=True]) /// Start advertising. Connectable advertisment type by default. /// @@ -231,6 +233,22 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, } STATIC MP_DEFINE_CONST_FUN_OBJ_KW(ubluepy_peripheral_advertise_obj, 0, peripheral_advertise); +/// \method advertise_stop() +/// Stop advertisment if any onging advertisment. +/// +STATIC mp_obj_t peripheral_advertise_stop(mp_obj_t self_in) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in); + + (void)self; + + ble_drv_advertise_stop(); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_advertise_stop_obj, peripheral_advertise_stop); + +#endif // MICROPY_PY_UBLUEPY_PERIPHERAL + /// \method disconnect() /// disconnect connection. /// @@ -406,6 +424,7 @@ STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { #endif // MICROPY_PY_UBLUEPY_CENTRAL #if MICROPY_PY_UBLUEPY_PERIPHERAL { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_advertise_stop), (mp_obj_t)(&ubluepy_peripheral_advertise_stop_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, { MP_OBJ_NEW_QSTR(MP_QSTR_addService), (mp_obj_t)(&ubluepy_peripheral_add_service_obj) }, #if 0 From a4173c467fd8106df30ae03361fb663021c9c244 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 4 Apr 2017 22:31:17 +0200 Subject: [PATCH 573/809] nrf5/bluetooth: Adding webbluetooth REPL template. Alternating advertisment of eddystone URL and UART BLE service every 500 ms. Adding new config parameter to bluetooth_conf.h to enable webbluetooth repl. Has to be configured in combination with BLE_NUS. Eddystone URL not pointing to a valid WebBluetooth application at the moment, but rather to micropython.org as a placeholder for now. --- nrf5/bluetooth/ble_uart.c | 64 ++++++++++++++++++++++++++++++--------- nrf5/bluetooth/ble_uart.h | 4 ++- nrf5/bluetooth_conf.h | 2 ++ nrf5/main.c | 3 ++ 4 files changed, 58 insertions(+), 15 deletions(-) diff --git a/nrf5/bluetooth/ble_uart.c b/nrf5/bluetooth/ble_uart.c index f9a88fbccc..f5614849a2 100644 --- a/nrf5/bluetooth/ble_uart.c +++ b/nrf5/bluetooth/ble_uart.c @@ -31,6 +31,10 @@ #if MICROPY_PY_BLE_NUS +#if BLUETOOTH_WEBBLUETOOTH_REPL +#include "hal_time.h" +#endif // BLUETOOTH_WEBBLUETOOTH_REPL + static ubluepy_uuid_obj_t uuid_obj_service = { .base.type = &ubluepy_uuid_type, .type = UBLUEPY_UUID_128_BIT, @@ -75,6 +79,7 @@ static ubluepy_peripheral_obj_t ble_uart_peripheral = { }; static volatile bool m_cccd_enabled; +static volatile bool m_connected; ringBuffer_typedef(uint8_t, ringbuffer_t); @@ -82,6 +87,11 @@ static ringbuffer_t m_rx_ring_buffer; static ringbuffer_t * mp_rx_ring_buffer = &m_rx_ring_buffer; static uint8_t m_rx_ring_buffer_data[128]; +static ubluepy_advertise_data_t m_adv_data_uart_service; + +#if BLUETOOTH_WEBBLUETOOTH_REPL +static ubluepy_advertise_data_t m_adv_data_eddystone_url; +#endif // BLUETOOTH_WEBBLUETOOTH_REPL int mp_hal_stdin_rx_chr(void) { while (isBufferEmpty(mp_rx_ring_buffer)) { @@ -127,8 +137,10 @@ STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn if (event_id == 16) { // connect event self->conn_handle = conn_handle; + m_connected = true; } else if (event_id == 17) { // disconnect event self->conn_handle = 0xFFFF; // invalid connection handle + m_connected = false; } } @@ -195,15 +207,21 @@ void ble_uart_init0(void) { mp_uint_t num_services; mp_obj_get_array(service_list, &num_services, &services); - ubluepy_advertise_data_t adv_data = { - .p_services = services, - .num_of_services = num_services, - .p_device_name = (uint8_t *)device_name, - .device_name_len = strlen(device_name) - }; + m_adv_data_uart_service.p_services = services; + m_adv_data_uart_service.num_of_services = num_services; + m_adv_data_uart_service.p_device_name = (uint8_t *)device_name; + m_adv_data_uart_service.device_name_len = strlen(device_name); + m_adv_data_uart_service.connectable = true; - (void)device_name; - (void)services; +#if BLUETOOTH_WEBBLUETOOTH_REPL + static uint8_t eddystone_url_data[26] = {0x2, 0x1, 0x6, + 0x3, 0x3, 0xaa, 0xfe, + 18, 0x16, 0xaa, 0xfe, 0x10, 0xee, 0x0, 'm', 'i', 'c', 'r', 'o', 'p', 'y', 't', 'h', 'o', 'n', 0x1}; + // eddystone url adv data + m_adv_data_eddystone_url.p_data = eddystone_url_data; + m_adv_data_eddystone_url.data_len = sizeof(eddystone_url_data); + m_adv_data_eddystone_url.connectable = false; +#endif m_cccd_enabled = false; @@ -213,15 +231,33 @@ void ble_uart_init0(void) { m_rx_ring_buffer.end = 0; m_rx_ring_buffer.elems = m_rx_ring_buffer_data; - adv_data.connectable = true; + m_connected = false; - (void)ble_drv_advertise_data(&adv_data); - - while (m_cccd_enabled != true) { - ; - } + ble_uart_advertise(); } +void ble_uart_advertise(void) { +#if BLUETOOTH_WEBBLUETOOTH_REPL + while (!m_connected) { + (void)ble_drv_advertise_data(&m_adv_data_uart_service); + mp_hal_delay_ms(500); + (void)ble_drv_advertise_data(&m_adv_data_eddystone_url); + mp_hal_delay_ms(500); + } + + ble_drv_advertise_stop(); +#else + (void)ble_drv_advertise_data(&m_adv_data_uart_service); +#endif // BLUETOOTH_WEBBLUETOOTH_REPL +} + +bool ble_uart_connected(void) { + return (m_connected); +} + +bool ble_uart_enabled(void) { + return (m_cccd_enabled); +} #endif // MICROPY_PY_BLE_NUS diff --git a/nrf5/bluetooth/ble_uart.h b/nrf5/bluetooth/ble_uart.h index 6d341cf5bf..e84e5ed0fa 100644 --- a/nrf5/bluetooth/ble_uart.h +++ b/nrf5/bluetooth/ble_uart.h @@ -31,5 +31,7 @@ #include "ble_drv.h" void ble_uart_init0(void); - +void ble_uart_advertise(void); +bool ble_uart_connected(void); +bool ble_uart_enabled(void); #endif // BLUETOOTH_LE_UART_H__ diff --git a/nrf5/bluetooth_conf.h b/nrf5/bluetooth_conf.h index e2bff0cbc0..5e62c97961 100644 --- a/nrf5/bluetooth_conf.h +++ b/nrf5/bluetooth_conf.h @@ -14,6 +14,7 @@ #define MICROPY_PY_BLE (1) #define MICROPY_PY_BLE_NUS (0) +#define BLUETOOTH_WEBBLUETOOTH_REPL (0) #define MICROPY_PY_UBLUEPY (1) #define MICROPY_PY_UBLUEPY_PERIPHERAL (1) @@ -21,6 +22,7 @@ #define MICROPY_PY_BLE (1) #define MICROPY_PY_BLE_NUS (0) +#define BLUETOOTH_WEBBLUETOOTH_REPL (0) #define MICROPY_PY_UBLUEPY (1) #define MICROPY_PY_UBLUEPY_PERIPHERAL (1) #define MICROPY_PY_UBLUEPY_CENTRAL (0) diff --git a/nrf5/main.c b/nrf5/main.c index 9412cabbff..0440dacd0d 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -197,6 +197,9 @@ int main(int argc, char **argv) { #if MICROPY_PY_BLE_NUS ble_uart_init0(); + while (!ble_uart_enabled()) { + ; + } #endif for (;;) { From b92b55bdd0ff12fa5c83f7157ff8a10ec8ea582d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 15:36:34 +0200 Subject: [PATCH 574/809] nrf5/bluetooth: Updating Eddystone URL to point to https://goo.gl/x46FES which hosts the MicroPython WebBluetooth application which will be able to connect to the Bluetooth LE UART service of the device and create the REPL. --- nrf5/bluetooth/ble_uart.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/bluetooth/ble_uart.c b/nrf5/bluetooth/ble_uart.c index f5614849a2..4b53268afa 100644 --- a/nrf5/bluetooth/ble_uart.c +++ b/nrf5/bluetooth/ble_uart.c @@ -214,9 +214,9 @@ void ble_uart_init0(void) { m_adv_data_uart_service.connectable = true; #if BLUETOOTH_WEBBLUETOOTH_REPL - static uint8_t eddystone_url_data[26] = {0x2, 0x1, 0x6, + static uint8_t eddystone_url_data[27] = {0x2, 0x1, 0x6, 0x3, 0x3, 0xaa, 0xfe, - 18, 0x16, 0xaa, 0xfe, 0x10, 0xee, 0x0, 'm', 'i', 'c', 'r', 'o', 'p', 'y', 't', 'h', 'o', 'n', 0x1}; + 19, 0x16, 0xaa, 0xfe, 0x10, 0xee, 0x3, 'g', 'o', 'o', '.', 'g', 'l', '/', 'x', '4', '6', 'F', 'E', 'S'}; // eddystone url adv data m_adv_data_eddystone_url.p_data = eddystone_url_data; m_adv_data_eddystone_url.data_len = sizeof(eddystone_url_data); From 5d06aa32609959115b496ac0e596438bfdbda038 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 15:52:21 +0200 Subject: [PATCH 575/809] nrf5/bluetooth: Add some comment on the destination of the eddystone short-url. --- nrf5/bluetooth/ble_uart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/bluetooth/ble_uart.c b/nrf5/bluetooth/ble_uart.c index 4b53268afa..7789da2f3a 100644 --- a/nrf5/bluetooth/ble_uart.c +++ b/nrf5/bluetooth/ble_uart.c @@ -214,6 +214,7 @@ void ble_uart_init0(void) { m_adv_data_uart_service.connectable = true; #if BLUETOOTH_WEBBLUETOOTH_REPL + // for now point eddystone URL to https://goo.gl/x46FES => https://glennrub.github.io/webbluetooth/micropython/repl/ static uint8_t eddystone_url_data[27] = {0x2, 0x1, 0x6, 0x3, 0x3, 0xaa, 0xfe, 19, 0x16, 0xaa, 0xfe, 0x10, 0xee, 0x3, 'g', 'o', 'o', '.', 'g', 'l', '/', 'x', '4', '6', 'F', 'E', 'S'}; From a026d3475f4d0d06a1d32496fa7f52194eaf18dc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 17:48:48 +0200 Subject: [PATCH 576/809] nrf5/modules/usocket: Updating import of netutils.h after upmerge with upstream master. --- nrf5/modules/usocket/modusocket.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/usocket/modusocket.c b/nrf5/modules/usocket/modusocket.c index 4c49788793..6afbbf95f9 100644 --- a/nrf5/modules/usocket/modusocket.c +++ b/nrf5/modules/usocket/modusocket.c @@ -32,7 +32,7 @@ #include "py/objlist.h" #include "py/runtime.h" #include "py/mperrno.h" -#include "netutils.h" +#include "lib/netutils/netutils.h" #include "modnetwork.h" #if MICROPY_PY_USOCKET From 4dd86178bc7981ca8b8cf4548c61733125f0ff1a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 18:25:15 +0200 Subject: [PATCH 577/809] nrf5: Removing custom display, framebuffer and graphics module to make branch contain core components instead of playground modules. --- nrf5/Makefile | 15 - nrf5/boards/pca10028/mpconfigboard.h | 7 - nrf5/boards/pca10040/mpconfigboard.h | 6 - nrf5/boards/pca10056/mpconfigboard.h | 8 - nrf5/examples/epaper.py | 451 --------------- nrf5/examples/game2048.py | 338 ------------ .../modules/display/epaper_sld00200p_driver.c | 447 --------------- .../modules/display/epaper_sld00200p_driver.h | 65 --- nrf5/modules/display/epaper_sld00200p_obj.c | 493 ----------------- nrf5/modules/display/epaper_sld00200p_obj.h | 35 -- nrf5/modules/display/framebuffer.c | 116 ---- nrf5/modules/display/framebuffer.h | 97 ---- nrf5/modules/display/lcd_ili9341_driver.c | 254 --------- nrf5/modules/display/lcd_ili9341_driver.h | 41 -- nrf5/modules/display/lcd_ili9341_obj.c | 357 ------------ nrf5/modules/display/lcd_ili9341_obj.h | 35 -- nrf5/modules/display/lcd_ls0xxb7dxxx_driver.c | 119 ---- nrf5/modules/display/lcd_ls0xxb7dxxx_driver.h | 47 -- nrf5/modules/display/lcd_ls0xxb7dxxx_obj.c | 392 ------------- nrf5/modules/display/lcd_ls0xxb7dxxx_obj.h | 35 -- nrf5/modules/display/lcd_ssd1289_driver.c | 225 -------- nrf5/modules/display/lcd_ssd1289_driver.h | 52 -- nrf5/modules/display/lcd_ssd1289_obj.c | 516 ------------------ nrf5/modules/display/lcd_ssd1289_obj.h | 35 -- nrf5/modules/display/moddisplay.c | 68 --- nrf5/modules/display/moddisplay.h | 46 -- nrf5/modules/display/oled_ssd1305_driver.c | 207 ------- nrf5/modules/display/oled_ssd1305_driver.h | 41 -- nrf5/modules/display/oled_ssd1305_obj.c | 372 ------------- nrf5/modules/display/oled_ssd1305_obj.h | 35 -- nrf5/modules/display/oled_ssd1306_driver.c | 208 ------- nrf5/modules/display/oled_ssd1306_driver.h | 41 -- nrf5/modules/display/oled_ssd1306_obj.c | 370 ------------- nrf5/modules/display/oled_ssd1306_obj.h | 35 -- nrf5/modules/display/rgb16.h | 33 -- nrf5/modules/graphic/draw.c | 189 ------- nrf5/modules/graphic/draw.h | 26 - nrf5/mpconfigport.h | 81 --- 38 files changed, 5938 deletions(-) delete mode 100644 nrf5/examples/epaper.py delete mode 100644 nrf5/examples/game2048.py delete mode 100644 nrf5/modules/display/epaper_sld00200p_driver.c delete mode 100644 nrf5/modules/display/epaper_sld00200p_driver.h delete mode 100644 nrf5/modules/display/epaper_sld00200p_obj.c delete mode 100644 nrf5/modules/display/epaper_sld00200p_obj.h delete mode 100644 nrf5/modules/display/framebuffer.c delete mode 100644 nrf5/modules/display/framebuffer.h delete mode 100644 nrf5/modules/display/lcd_ili9341_driver.c delete mode 100644 nrf5/modules/display/lcd_ili9341_driver.h delete mode 100644 nrf5/modules/display/lcd_ili9341_obj.c delete mode 100644 nrf5/modules/display/lcd_ili9341_obj.h delete mode 100644 nrf5/modules/display/lcd_ls0xxb7dxxx_driver.c delete mode 100644 nrf5/modules/display/lcd_ls0xxb7dxxx_driver.h delete mode 100644 nrf5/modules/display/lcd_ls0xxb7dxxx_obj.c delete mode 100644 nrf5/modules/display/lcd_ls0xxb7dxxx_obj.h delete mode 100644 nrf5/modules/display/lcd_ssd1289_driver.c delete mode 100644 nrf5/modules/display/lcd_ssd1289_driver.h delete mode 100644 nrf5/modules/display/lcd_ssd1289_obj.c delete mode 100644 nrf5/modules/display/lcd_ssd1289_obj.h delete mode 100644 nrf5/modules/display/moddisplay.c delete mode 100644 nrf5/modules/display/moddisplay.h delete mode 100644 nrf5/modules/display/oled_ssd1305_driver.c delete mode 100644 nrf5/modules/display/oled_ssd1305_driver.h delete mode 100644 nrf5/modules/display/oled_ssd1305_obj.c delete mode 100644 nrf5/modules/display/oled_ssd1305_obj.h delete mode 100644 nrf5/modules/display/oled_ssd1306_driver.c delete mode 100644 nrf5/modules/display/oled_ssd1306_driver.h delete mode 100644 nrf5/modules/display/oled_ssd1306_obj.c delete mode 100644 nrf5/modules/display/oled_ssd1306_obj.h delete mode 100644 nrf5/modules/display/rgb16.h delete mode 100644 nrf5/modules/graphic/draw.c delete mode 100644 nrf5/modules/graphic/draw.h diff --git a/nrf5/Makefile b/nrf5/Makefile index 976c5d7a2e..511fe4c465 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -137,21 +137,6 @@ SRC_C += \ fatfs_port.c \ DRIVERS_SRC_C += $(addprefix modules/,\ - display/moddisplay.c \ - display/epaper_sld00200p_obj.c \ - display/epaper_sld00200p_driver.c \ - display/lcd_ili9341_obj.c \ - display/lcd_ili9341_driver.c \ - display/lcd_ls0xxb7dxxx_obj.c \ - display/lcd_ls0xxb7dxxx_driver.c \ - display/lcd_ssd1289_obj.c \ - display/lcd_ssd1289_driver.c \ - display/oled_ssd1305_obj.c \ - display/oled_ssd1305_driver.c \ - display/oled_ssd1306_obj.c \ - display/oled_ssd1306_driver.c \ - display/framebuffer.c \ - graphic/draw.c \ machine/modmachine.c \ machine/uart.c \ machine/spi.c \ diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index ae8c9e8352..8dc210c413 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -30,13 +30,6 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" -#define MICROPY_PY_DISPLAY (0) -#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) -#define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) -#define MICROPY_PY_DISPLAY_LCD_SSD1289 (0) -#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) - #define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 12f0cb5d35..50b3da7fc3 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -38,12 +38,6 @@ #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) -#define MICROPY_PY_DISPLAY (1) -#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) -#define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) -#define MICROPY_PY_DISPLAY_LCD_SSD1289 (1) -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) - #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index a4673057f5..f111e737d6 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -36,14 +36,6 @@ #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) -#define MICROPY_PY_DISPLAY (1) -#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (1) -#define MICROPY_PY_DISPLAY_LCD_ILI9341 (1) -#define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (1) -#define MICROPY_PY_DISPLAY_LCD_SSD1289 (1) -#define MICROPY_PY_DISPLAY_OLED_SSD1305 (1) -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (1) - #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/examples/epaper.py b/nrf5/examples/epaper.py deleted file mode 100644 index 743ae2e0cb..0000000000 --- a/nrf5/examples/epaper.py +++ /dev/null @@ -1,451 +0,0 @@ -# This file is part of the Micro Python project, http://micropython.org/ -# -# The MIT License (MIT) -# -# Copyright (c) 2017 Glenn Ruben Bakke -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -# THE SOFTWARE. - -""" -E-paper EM027AS011. - -Pin layout on pca10040 (nrf52): - -EPAPER_PANEL_ON 13 (Arduino D2) -EPAPER_BORDER 14 (Arduino D3) -EPAPER_PWM 16 (Arduino D5) -EPAPER_RESET 17 (Arduino D6) -EPAPER_BUSY 18 (Arduino D7) -EPAPER_DISCHARGE 19 (Arduino D8) -EPAPER_TEMP_SENSOR 03 (Arduino A0) -EPAPER_CS 22 (Arduino D10) -EPAPER_DIN 23 (Arduino D11) -EPAPER_DOUT 24 (Arduino D12) -EPAPER_CLK 25 (Arduino D13) - -Example usage on pca10040: - -from epaper import Epaper - -epd = Epaper() -epd.fill(0) -epd.text("Hello World!", 50, 50) -epd.show() - -epd.refresh() -epd.refresh() -""" - -import os -import time -import lcd_mono_fb - -from machine import SPI, Pin, PWM - -EPD_STATE_COMP = const(0x1) -EPD_STATE_WHITE = const(0x2) -EPD_STATE_INV = const(0x3) -EPD_STATE_NORM = const(0x4) - -class Epaper: - def __init__(self, width=264, height=176, vertical=False): - - self.width = width - self.height = height - self.vertical = vertical - self.framebuf = lcd_mono_fb.MonoFB(self.line_update, self.width, self.height, True) - - self.reset = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) - self.panel_on = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) - self.discharge = Pin("A19", mode=Pin.OUT, pull=Pin.PULL_UP) - self.border = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) - self.busy = Pin("A18", mode=Pin.IN, pull=Pin.PULL_DISABLED) - self.cs = Pin("A22", mode=Pin.OUT, pull=Pin.PULL_UP) - - self.reset.low() - self.panel_on.low() - self.discharge.low() - self.border.low() - - self.pwm = PWM(0, Pin("A16", mode=Pin.OUT), freq=PWM.FREQ_250KHZ, duty=50, period=2) - - # Min baudrate 4M, max 12M - self.spi = SPI(0, baudrate=80000000) - # self.spi.init(baudrate=8000000, phase=0, polarity=0) - - def line_update(self, o, line, new_bytes, old_bytes): - if new_bytes: - self._update_line(line, old_bytes, EPD_STATE_COMP) - self._update_line(line, old_bytes, EPD_STATE_WHITE) - self._update_line(line, new_bytes, EPD_STATE_INV) - self._update_line(line, new_bytes, EPD_STATE_NORM) - else: - self._update_line(line, old_bytes, EPD_STATE_NORM) - - def clear(self): - line_count = self.height; - for i in range(0, line_count): - self._update_line(i, None, EPD_STATE_COMP, 0xFF) - - time.sleep_ms(500) - - for i in range(0, line_count): - self._update_line(i, None, EPD_STATE_WHITE, 0xAA) - - time.sleep_ms(500) - - for i in range(0, line_count): - self._update_line(i, None, EPD_STATE_INV, 0xFF) - - time.sleep_ms(500) - - for i in range(0, line_count): - self._update_line(i, None, EPD_STATE_NORM, 0xAA) - - time.sleep_ms(500) - - def init_display(self): - - self.pwm.init() # start the pwm - - print("sleep") - time.sleep_ms(5) - print("wakeup") - self.panel_on.high() - time.sleep_ms(10) - - self.reset.high() - self.border.high() - self.cs.high() - - time.sleep_ms(5) - - self.reset.low() - - time.sleep_ms(5) - - self.reset.high() - - time.sleep_ms(5) - print("Wait for busy") - self.wait_for_busy_release() - - time.sleep_us(10) - # channel select - self.write_data(bytearray([0x70, 0x01])) - time.sleep_us(10) - - # CS - self.write_data(bytearray([0x72, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xfe, 0x00, 0x00])) - - # DC/DC frequency - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x06])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0xff])) - - # high power mode osc - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x07])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x9d])) - - # disable ADC - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x08])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x00])) - - # Vcom level - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x09])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0xd0, 0x00])) - - # gate and source voltage levels - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x04])) - - # GS - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x00])) - - time.sleep_ms(5) - - # driver latch on - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x03])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x01])) - - # driver latch off - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x03])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x00])) - - time.sleep_ms(5) - - # charge pump positive voltage on - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x05])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x01])) - - # final delay before PWM off - time.sleep_us(30) - - # stop PWM - self.pwm.deinit() - - # charge pump negative voltage on - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x05])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x03])) - - time.sleep_us(30) - - # Vcom driver on - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x05])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x0f])) - - time.sleep_ms(30); - - # output enable to disable - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x02])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x24])) - - def wait_for_busy_release(self): - # wait for COG to become ready - while (self.busy.value() == 1): - pass - - def _update_line(self, line, data, state, fixed=None): - time.sleep_us(10) - - self.write_data(bytearray([0x70, 0x04])) - time.sleep_us(10) - - # gate source - self.write_data(bytearray([0x72, 0x00])) - time.sleep_us(10) - - self.write_data(bytearray([0x70, 0x0a])) - time.sleep_us(10) - - self.cs.low() - - self.write_data_wait(bytearray([0x72])) - - bytes_per_line = self.width // 8; - - # even pixels - if data: - for i in range(bytes_per_line - 1, -1, -1): - - pixels = data[i] & 0xaa; - - if state == EPD_STATE_COMP: - # B -> W, W -> B (current image) - pixels = 0xaa | ((pixels ^ 0xaa) >> 1) - - elif state == EPD_STATE_WHITE: - # B -> N, W -> W (current image) - pixels = 0x55 + ((pixels ^ 0xaa) >> 1) - - elif state == EPD_STATE_INV: - # B -> N, W -> B (new image) - pixels = 0x55 | (pixels ^ 0xaa) - - elif state == EPD_STATE_NORM: - # B -> B, W -> W (new image) - pixels = 0xaa | (pixels >> 1) - - self.write_data_wait(bytearray([pixels])); - else: - self.write_data_wait(bytearray([fixed] * bytes_per_line)); - - bytes_per_scan = 176 // 4; - # scan line - for i in range(0, bytes_per_scan): - if (line // 4 == i): - self.write_data_wait(bytearray([0xc0 >> (2 * (line & 0x03))])) - else: - self.write_data_wait(bytearray([0x00])) - - # odd pixels - if data: - for i in range (0, bytes_per_line): - pixels = data[i] & 0x55 - - if state == EPD_STATE_COMP: - pixels = 0xaa | (pixels ^ 0x55) - - elif state == EPD_STATE_WHITE: - pixels = 0x55 + (pixels ^ 0x55) - - elif state == EPD_STATE_INV: - pixels = 0x55 | ((pixels ^ 0x55) << 1) - - elif state == EPD_STATE_NORM: - pixels = 0xaa | pixels - - p1 = (pixels >> 6) & 0x03; - p2 = (pixels >> 4) & 0x03; - p3 = (pixels >> 2) & 0x03; - p4 = (pixels >> 0) & 0x03; - - pixels = (p1 << 0) | (p2 << 2) | (p3 << 4) | (p4 << 6); - - self.write_data_wait(bytearray([pixels])) - else: - self.write_data_wait(bytearray([fixed] * bytes_per_line)) - - # Complete line - self.write_data_wait(bytearray([0x00])) - - self.cs.high() - - time.sleep_us(10) - - - self.write_data(bytearray([0x70, 0x02])) - time.sleep_us(10) - - self.write_data(bytearray([0x72, 0x2f])) - - def deinit_display(self): - # all display sizes - self._update_line(0x7fff, None, EPD_STATE_NORM, 0x55) - time.sleep_ms(25) - self.border.low() - time.sleep_ms(250) - self.border.high() - - # latch reset turn on - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x03])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x01])) - - # output enable off - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x02])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x05])) - - # Vcom power off - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x05])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x0e])) - - # power off negative charge pump - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x05])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x02])) - - # discharge - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x04])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x0c])) - time.sleep_us(120) - - # all charge pumps off - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x05])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x00])) - - # turn of osc - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x07])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x0d])) - - # discharge internal - 1 - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x04])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x50])) - time.sleep_us(40) - - # discharge internal - 2 - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x04])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0xA0])) - time.sleep_us(40) - - # discharge internal - 3 - time.sleep_us(10) - self.write_data(bytearray([0x70, 0x04])) - time.sleep_us(10) - self.write_data(bytearray([0x72, 0x00])) - - # turn of power and all signals - time.sleep_ms(10) - self.reset.low() - self.panel_on.low() - self.border.low() - - # discharge pulse - self.discharge.high() - time.sleep_us(250) - self.discharge.low() - - self.cs.high() - - def show(self): - self.init_display() - self.framebuf.show() - self.deinit_display() - - def refresh(self): - self.init_display() - self.framebuf.refresh() - self.deinit_display() - - def fill(self, col): - self.framebuf.fill(col) - - def pixel(self, x, y, col): - self.framebuf.pixel(x, y, col) - - def scroll(self, dx, dy): - self.framebuf.scroll(dx, dy) - - def text(self, string, x, y, col=1): - self.framebuf.text(string, x, y, col) - - def write_data_wait(self, buf): - self.spi.write(buf) - self.wait_for_busy_release() - - def write_data(self, buf): - self.cs.low() - self.spi.write(buf) - self.cs.high() diff --git a/nrf5/examples/game2048.py b/nrf5/examples/game2048.py deleted file mode 100644 index 3d321d92c5..0000000000 --- a/nrf5/examples/game2048.py +++ /dev/null @@ -1,338 +0,0 @@ -# This file is part of the Micro Python project, http://micropython.org/ -# -# The MIT License (MIT) -# -# Copyright (c) 2017 Glenn Ruben Bakke -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -# THE SOFTWARE. - -''' -Usage: - -from game2048 import Game -g = Game() -g.start() - -''' - -from machine import ADC -from machine import Pin, SPI -from display import SSD1305 -import draw -import time - -font_128 = [ - " x xx xx", - " xx x x x x", - "x x x x x", - " x x xx", - " x x x x", - " x x x x", - " xxx xxxx xx" -] - -font_256 = [ - " xx xxxx xx", - "x x x x x", - " x xxx x ", - " x x xxxx", - " x x x x", - "x x x x", - "xxxx xxx xx" -] - -font_512 = [ - "xxxx x xx", - "x xx x x", - "xxx x x x", - " x x x", - " x x x", - " x x x", - "xxx xxx xxxx" -] - -font_1024 = [ - " xx x x x x", - "x x x x x x x x", - " x x x x x x", - " x x x x xxx", - " x x x x x", - " x x x x x", - " x x xxx x" -] - -DIR_UP = const(0x1) -DIR_DOWN = const(0x2) -DIR_LEFT = const(0x3) -DIR_RIGHT = const(0x4) -DIR_CENTER = const(0x5) - -class Game: - def __init__(self): - -# # setup harware for nrf51822 / pca10028 -# cs = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) -# reset = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) -# dc = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) -# spi = SPI(0, baudrate=8000000) -# self.screen = SSD1305(128, 64, spi, cs, dc, reset) -# self.x_adc = ADC(2) -# self.y_adc = ADC(3) -# self.adc_threshold = 205 - - # setup harware for nrf52840 / pca10056 - cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) - reset = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) - dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) - spi = SPI(0, baudrate=8000000) - self.screen = SSD1305(128, 64, spi, cs, dc, reset) - self.x_adc = ADC(1) - self.y_adc = ADC(2) - self.adc_threshold = 130 - - # game setup - self.grid = [[0, 0, 0, 0], [0, 0, 0, 0], [0, 0, 0, 0], [0, 0, 0, 0]] - self._rand = 1337 - self.not_game_over = True - self.score = 0 - - - def move(self, dir): - if (dir == DIR_UP): - # float up - for col in range(0, 4): - for row1 in range(1, 5): - for row0 in range(1, row1): - if self.grid[col][row0 - 1] == 0: - if self.grid[col][row0]: - self.grid[col][row0 - 1] = self.grid[col][row0] - self.grid[col][row0] = 0 - # collapse - for col in range(0, 4): - for row0 in range(0, 3): - if self.grid[col][row0] == self.grid[col][row0 + 1]: - self.grid[col][row0] += self.grid[col][row0] - self.score += self.grid[col][row0] - self.grid[col][row0 + 1] = 0 - # float up - for col in range(0, 4): - for row1 in range(1, 5): - for row0 in range(1, row1): - if self.grid[col][row0 - 1] == 0: - if self.grid[col][row0]: - self.grid[col][row0 - 1] = self.grid[col][row0] - self.grid[col][row0] = 0 - elif (dir == DIR_DOWN): - # float down - for col in range(0, 4): - for row1 in range(1, 5): - for row0 in range(row1, 4): - if self.grid[col][row0] == 0: - if self.grid[col][row0 - 1]: - self.grid[col][row0] = self.grid[col][row0 - 1] - self.grid[col][row0 - 1] = 0 - # collapse - for col in range(0, 4): - for row0 in range(1, 4): - if self.grid[col][row0] == self.grid[col][row0 - 1]: - self.grid[col][row0] += self.grid[col][row0] - self.score += self.grid[col][row0] - self.grid[col][row0 - 1] = 0 - # float down - for col in range(0, 4): - for row1 in range(1, 5): - for row0 in range(row1, 4): - if self.grid[col][row0] == 0: - if self.grid[col][row0 - 1]: - self.grid[col][row0] = self.grid[col][row0 - 1] - self.grid[col][row0 - 1] = 0 - elif (dir == DIR_LEFT): - # float left - for row in range(0, 4): - for col1 in range(1, 5): - for col0 in range(1, col1): - if self.grid[col0 - 1][row] == 0: - if self.grid[col0][row]: - self.grid[col0 - 1][row] = self.grid[col0][row] - self.grid[col0][row] = 0 - # collapse - for row in range(0, 4): - for col0 in range(0, 3): - if self.grid[col0][row] == self.grid[col0 + 1][row]: - self.grid[col0][row] += self.grid[col0][row] - self.score += self.grid[col0][row] - self.grid[col0 + 1][row] = 0 - # float left - for row in range(0, 4): - for col1 in range(1, 5): - for col0 in range(1, col1): - if self.grid[col0 - 1][row] == 0: - if self.grid[col0][row]: - self.grid[col0 - 1][row] = self.grid[col0][row] - self.grid[col0][row] = 0 - elif (dir == DIR_RIGHT): - # float right - for row in range(0, 4): - for col1 in range(1, 5): - for col0 in range(col1, 4): - if self.grid[col0][row] == 0: - if self.grid[col0 - 1][row]: - self.grid[col0][row] = self.grid[col0 - 1][row] - self.grid[col0 - 1][row] = 0 - # collapse - for row in range(0, 4): - for col0 in range(1, 4): - if self.grid[col0][row] == self.grid[col0 - 1][row]: - self.grid[col0][row] += self.grid[col0][row] - self.score += self.grid[col0][row] - self.grid[col0 - 1][row] = 0 - # float right - for row in range(0, 4): - for col1 in range(1, 5): - for col0 in range(col1, 4): - if self.grid[col0][row] == 0: - if self.grid[col0 - 1][row]: - self.grid[col0][row] = self.grid[col0 - 1][row] - self.grid[col0 - 1][row] = 0 - def set_val(self, x, y, val): - self.grid[x][y] = val - def get_val(self, x, y): - return self.grid[x][y] - def draw_high_number(self, font, x, y): - for rel_y, line in enumerate(font): - for rel_x in range(0, len(line)): - if (line[rel_x] == 'x'): - self.screen.pixel(x + rel_x, y + rel_y, 1) - def draw_tile(self, x, y): - val = self.get_val(x, y) - if val != 0: - x0 = x * 16 - y0 = y * 16 - if (val < 16): - draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) - draw.text(self.screen, str(val), x0 + 4, y0 + 4, 1) - elif val == 16: - draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) - draw.text(self.screen, "1", x0 + 1, y0 + 4, 1) - draw.text(self.screen, "6", x0 + 7, y0 + 4, 1) - elif val == 32: - draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) - draw.text(self.screen, "3", x0 + 1, y0 + 4, 1) - draw.text(self.screen, "2", x0 + 7, y0 + 4, 1) - elif val == 64: - draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) - draw.text(self.screen, "6", x0 + 1, y0 + 4, 1) - draw.text(self.screen, "4", x0 + 7, y0 + 4, 1) - elif val == 128: - draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) - self.draw_high_number(font_128, x0 + 1, y0 + 4) - elif val == 256: - draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) - self.draw_high_number(font_256, x0 + 1, y0 + 4) - elif val == 512: - draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) - self.draw_high_number(font_512, x0 + 1, y0 + 4) - elif val == 1024: - draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) - self.draw_high_number(font_1024, x0 + 1, y0 + 4) - elif val == 2048: - draw.rectangle(self.screen, x0, y0, x0 + 15, y0 + 15, 1) - self.draw_high_number(font_2048, x0 + 1, y0 + 4) - def read_stick_x(self): - return self.x_adc.value() - def read_stick_y(self): - return self.y_adc.value() - def wait_for_move(self): - x_val = self.read_stick_x() - y_val = self.read_stick_y() - if x_val > self.adc_threshold + 15: - return DIR_RIGHT - elif x_val < self.adc_threshold - 15: - return DIR_LEFT - if y_val > self.adc_threshold + 15: - return DIR_UP - elif y_val < self.adc_threshold - 15: - return DIR_DOWN - return DIR_CENTER - def get_free_tiles(self): - list = [] - for x in range(0, 4): - for y in range(0, 4): - if self.get_val(x, y) == 0: - list.append((x, y)) - return list - def draw_all_tiles(self): - for x in range(0, 4): - for y in range(0, 4): - self.draw_tile(x, y) - def rand(self, mod=0): - self._rand = ((214013*self._rand+2531011)>>16)&0x7FFF - if mod: - return self._rand % mod - else: - return self._rand - def add_random_tile(self): - free_tiles = self.get_free_tiles() - if free_tiles: - x,y = free_tiles[self.rand(len(free_tiles))] - new_val = 2 << self.rand(2) - self.set_val(x, y, new_val) - return True - else: - return False - def draw_score(self): - draw.text(self.screen, "Score:", 70, 10, 1) - draw.text(self.screen, str(self.score), 70, 20, 1) - def clear_grid(self): - # Because the the double array does not initialize correctly - # in micropython, we do an explicit clear - for i in range(0, 4): - for j in range(0, 4): - self.grid[i][j] = 0 - def start(self): - self.screen.fill(0) - draw.text(self.screen, "Touch the stick", 10, 20, 1) - draw.text(self.screen, " to start the", 10, 30, 1) - draw.text(self.screen, " game! =)", 10, 40, 1) - self.screen.show() - in_center = False - x_move = True - y_move = True - wait_for_center = False - self.clear_grid() - while self.not_game_over: - move_dir = self.wait_for_move() - if move_dir != DIR_CENTER and wait_for_center == False: - self.move(move_dir) - self.screen.fill(0) - res = self.add_random_tile() - if not res: - self.not_game_over = False - else: - self.draw_all_tiles() - self.draw_score() - self.screen.show() - wait_for_center = True - if move_dir == DIR_CENTER: - wait_for_center = False - self.screen.fill(0) - draw.text(self.screen, "Game Over!", 10, 20, 1) - draw.text(self.screen, "Score:", 10, 30, 1) - draw.text(self.screen, str(self.score), 10, 40, 1) - self.screen.show() \ No newline at end of file diff --git a/nrf5/modules/display/epaper_sld00200p_driver.c b/nrf5/modules/display/epaper_sld00200p_driver.c deleted file mode 100644 index 30ce590ce5..0000000000 --- a/nrf5/modules/display/epaper_sld00200p_driver.c +++ /dev/null @@ -1,447 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "epaper_sld00200p_driver.h" - -#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P - -#include "py/mphal.h" - -#include "epaper_sld00200p_driver.h" -#include "hal_spi.h" -#include "hal_time.h" - -#define BYTE_ARRAY(...) ((uint8_t[]){ __VA_ARGS__}) -#define DATA_WRITE(...) (data_write_buffer(BYTE_ARRAY(__VA_ARGS__), sizeof(BYTE_ARRAY(__VA_ARGS__)))) - -static NRF_SPI_Type * mp_spi_instance; -static NRF_PWM_Type * mp_pwm_instance; -static pin_obj_t * mp_pin_cs; -static pin_obj_t * mp_pin_panel_on; -static pin_obj_t * mp_pin_border; -static pin_obj_t * mp_pin_busy; -static pin_obj_t * mp_pin_reset; -static pin_obj_t * mp_pin_discharge; - -#if 0 -static pin_obj_t * mp_pin_temp_sensor; -#endif - -static void wait_for_busy_release(void) { - while (mp_hal_pin_read(mp_pin_busy) == 1) { - ; - } -} - -static void data_write_buffer(uint8_t * p_bytes, uint16_t num_of_bytes) { - mp_hal_pin_low(mp_pin_cs); - - hal_spi_master_tx_rx(mp_spi_instance, num_of_bytes, p_bytes, NULL); - - mp_hal_pin_high(mp_pin_cs); -} - -static void raw_write(uint8_t value) -{ - hal_spi_master_tx_rx(mp_spi_instance, 1, &value, NULL); -} - -void driver_sld00200p_init(NRF_SPI_Type * p_spi_instance, - NRF_PWM_Type * p_pwm_instance, - pin_obj_t * p_pin_cs, - pin_obj_t * p_pin_panel_on, - pin_obj_t * p_pin_border, - pin_obj_t * p_pin_busy, - pin_obj_t * p_pin_reset, - pin_obj_t * p_pin_discharge) { - - mp_spi_instance = p_spi_instance; - mp_pwm_instance = p_pwm_instance; - mp_pin_cs = p_pin_cs; - mp_pin_panel_on = p_pin_panel_on; - mp_pin_border = p_pin_border; - mp_pin_busy = p_pin_busy; - mp_pin_reset = p_pin_reset; - mp_pin_discharge = p_pin_discharge; - - driver_sld00200p_reinit(); -} - -void driver_sld00200p_reinit(void) { - mp_hal_pin_low(mp_pin_reset); - mp_hal_pin_low(mp_pin_panel_on); - mp_hal_pin_low(mp_pin_discharge); - mp_hal_pin_low(mp_pin_border); - - // start the pwm - hal_pwm_start(mp_pwm_instance); - - mp_hal_delay_ms(5); - - mp_hal_pin_high(mp_pin_panel_on); - - mp_hal_delay_ms(10); - - mp_hal_pin_high(mp_pin_reset); - mp_hal_pin_high(mp_pin_border); - mp_hal_pin_high(mp_pin_cs); - - // make reset square wave - mp_hal_delay_ms(5); - mp_hal_pin_low(mp_pin_reset); - mp_hal_delay_ms(5); - mp_hal_pin_high(mp_pin_reset); - mp_hal_delay_ms(5); - - wait_for_busy_release(); - - // channel select - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x01); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xfe, 0x00, 0x00); - - // DC/DC frequency - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x06); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xfe, 0x00, 0x00); - - // high power mode osc - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x07); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x9d); - - // disable ADC - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x08); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x00); - - // Vcom level - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x09); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0xd0, 0x00); - - // gate and source voltage levels - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x04); - - // GS - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x00); - - mp_hal_delay_ms(5); - - // driver latch on - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x03); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x01); - - // driver latch off - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x03); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x00); - - mp_hal_delay_ms(5); - - // charge pump positive voltage on - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x05); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x01); - - // final delay before PWM off - mp_hal_delay_us(30); - - // stop the pwm - hal_pwm_stop(mp_pwm_instance); - - // charge pump negative voltage on - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x05); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x03); - - mp_hal_delay_us(30); - - // Vcom driver on - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x05); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x0f); - - mp_hal_delay_ms(30); - - // output enable to disable - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x02); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x24); -} - -static void epaper_sld00200p_line(uint16_t line, const uint8_t * data, uint8_t fixed_value, epd_stage_t stage) -{ - mp_hal_delay_ms(10); - - DATA_WRITE(0x70, 0x04); - wait_for_busy_release(); - - // gate source - DATA_WRITE(0x72, 0x00); - wait_for_busy_release(); - - DATA_WRITE(0x70, 0x0a); - wait_for_busy_release(); - - mp_hal_pin_low(mp_pin_cs); - raw_write(0x72); - wait_for_busy_release(); - - uint16_t bytes_per_line = 264 / 8; - - // even pixels - for (uint16_t i = bytes_per_line; i > 0; --i) { - if (data != NULL) { - uint8_t pixels = data[i - 1] & 0xaa; - - switch (stage) { - case EPD_COMP: - // B -> W, W -> B (current image) - pixels = 0xaa | ((pixels ^ 0xaa) >> 1); - break; - - case EPD_WHITE: - // B -> N, W -> W (current image) - pixels = 0x55 + ((pixels ^ 0xaa) >> 1); - break; - - case EPD_INV: - // B -> N, W -> B (new image) - pixels = 0x55 | (pixels ^ 0xaa); - break; - - case EPD_NORM: - // B -> B, W -> W (new image) - pixels = 0xaa | (pixels >> 1); - break; - - default: - break; - } - - raw_write(pixels); - wait_for_busy_release(); - } else { - raw_write(fixed_value); - wait_for_busy_release(); - } - } - - uint16_t bytes_per_scan = 176 / 4; - // scan line - for (uint16_t i = 0; i < bytes_per_scan; i++) { - if (line / 4 == i) { - raw_write(0xc0 >> (2 * (line & 0x03))); - wait_for_busy_release(); - } else { - raw_write(0x00); - wait_for_busy_release(); - } - } - - // odd pixels - for (uint16_t i = 0; i < bytes_per_line; i++) { - if (data != NULL) { - uint8_t pixels; - pixels = data[i] & 0x55; - - switch (stage) { - case EPD_COMP: - pixels = 0xaa | (pixels ^ 0x55); - break; - - case EPD_WHITE: - pixels = 0x55 + (pixels ^ 0x55); - break; - - case EPD_INV: - pixels = 0x55 | ((pixels ^ 0x55) << 1); - break; - - case EPD_NORM: - pixels = 0xaa | pixels; - break; - - default: - break; - } - - uint8_t p1 = (pixels >> 6) & 0x03; - uint8_t p2 = (pixels >> 4) & 0x03; - uint8_t p3 = (pixels >> 2) & 0x03; - uint8_t p4 = (pixels >> 0) & 0x03; - pixels = (p1 << 0) | (p2 << 2) | (p3 << 4) | (p4 << 6); - - raw_write(pixels); - wait_for_busy_release(); - } else { - raw_write(fixed_value); - wait_for_busy_release(); - } - } - - // Complete line - raw_write(0x00); - wait_for_busy_release(); - - mp_hal_pin_high(mp_pin_cs); - wait_for_busy_release(); - - DATA_WRITE(0x70, 0x02); - wait_for_busy_release(); - - DATA_WRITE(0x72, 0x2f); -} - -void driver_sld00200p_deinit(void) { - epaper_sld00200p_line(0x7fffu, 0, 0x55, EPD_NORM); - mp_hal_delay_ms(25); - mp_hal_pin_low(mp_pin_border); - mp_hal_delay_ms(250); - mp_hal_pin_high(mp_pin_border); - - // latch reset turn on - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x03); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x01); - - // output enable off - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x02); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x05); - - // Vcom power off - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x05); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x0e); - - // power off negative charge pump - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x05); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x02); - - // discharge - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x04); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x0c); - mp_hal_delay_us(120); - - // all charge pumps off - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x05); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x00); - - // turn of osc - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x07); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x0d); - - // discharge internal - 1 - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x04); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x50); - mp_hal_delay_us(40); - - // discharge internal - 2 - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x04); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0xA0); - mp_hal_delay_us(40); - - // discharge internal - 3 - mp_hal_delay_us(10); - DATA_WRITE(0x70, 0x04); - mp_hal_delay_us(10); - DATA_WRITE(0x72, 0x00); - - // turn of power and all signals - mp_hal_delay_ms(10); - mp_hal_pin_low(mp_pin_reset); - mp_hal_pin_low(mp_pin_panel_on); - mp_hal_pin_low(mp_pin_border); - - // discharge pulse - mp_hal_pin_high(mp_pin_discharge); - mp_hal_delay_us(250); - mp_hal_pin_low(mp_pin_discharge); - mp_hal_pin_high(mp_pin_cs); -} - -void driver_sld00200p_clear(uint16_t color) { - uint16_t line_count = 176; - for (uint16_t i = 0; i < line_count; i++) { - epaper_sld00200p_line(i, NULL, 0xFF, EPD_COMP); - } - mp_hal_delay_ms(100); - - for (uint16_t i = 0; i < line_count; i++) { - epaper_sld00200p_line(i, NULL, 0xAA, EPD_WHITE); - } - mp_hal_delay_ms(100); - - for (uint16_t i = 0; i < line_count; i++) { - epaper_sld00200p_line(i, NULL, 0xFF, EPD_INV); - } - mp_hal_delay_ms(100); - - for (uint16_t i = 0; i < line_count; i++) { - epaper_sld00200p_line(i, NULL, 0xAA, EPD_NORM); - } - mp_hal_delay_ms(100); -} - -void driver_sld00200p_update_line(uint16_t line, framebuffer_byte_t * p_bytes, framebuffer_byte_t * p_old, uint16_t len) { - epaper_sld00200p_line(line, (uint8_t *)p_old, 0x00, EPD_COMP); - epaper_sld00200p_line(line, (uint8_t *)p_old, 0xAA, EPD_WHITE); - epaper_sld00200p_line(line, (uint8_t *)p_bytes, 0xAA, EPD_INV); - epaper_sld00200p_line(line, (uint8_t *)p_bytes, 0xFF, EPD_NORM); -} - -#endif diff --git a/nrf5/modules/display/epaper_sld00200p_driver.h b/nrf5/modules/display/epaper_sld00200p_driver.h deleted file mode 100644 index 81470d0abc..0000000000 --- a/nrf5/modules/display/epaper_sld00200p_driver.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef EPAPER_SLD00200P_DRIVER_H__ -#define EPAPER_SLD00200P_DRIVER_H__ - -#if NRF52 // TODO: For now only supported by NRF52 targets, as PWM soft-pwm is not present for nrf51 yet. - -#include "py/mphal.h" - -#include "hal_spi.h" -#include "hal_pwm.h" -#include "framebuffer.h" - -typedef enum -{ - EPD_COMP, - EPD_WHITE, - EPD_INV, - EPD_NORM -} epd_stage_t; - -void driver_sld00200p_init(NRF_SPI_Type * p_spi_instance, - NRF_PWM_Type * p_pwm_instance, - pin_obj_t * p_pin_cs, - pin_obj_t * p_pin_panel_on, - pin_obj_t * p_pin_border, - pin_obj_t * p_pin_busy, - pin_obj_t * p_pin_reset, - pin_obj_t * p_pin_discharge); - -void driver_sld00200p_reinit(void); - -void driver_sld00200p_deinit(void); - -void driver_sld00200p_clear(uint16_t color); - -void driver_sld00200p_update_line(uint16_t line, framebuffer_byte_t * p_bytes, framebuffer_byte_t * p_bytes_old, uint16_t len); - -#endif // NRF52 - -#endif // EPAPER_SLD00200P_DRIVER_H__ diff --git a/nrf5/modules/display/epaper_sld00200p_obj.c b/nrf5/modules/display/epaper_sld00200p_obj.c deleted file mode 100644 index df2d5d6d98..0000000000 --- a/nrf5/modules/display/epaper_sld00200p_obj.c +++ /dev/null @@ -1,493 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" -#include "py/runtime.h" -#include "py/mphal.h" -#include "genhdr/pins.h" - -#include "epaper_sld00200p_driver.h" - -// For now PWM is only enabled for nrf52 targets. -#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P && NRF52 - -/// \moduleref epaper -/// \class sld00200p - SLD00200P E-paper shield. - -#include "pin.h" -#include "spi.h" -#include "pwm.h" -#include "hal_spi.h" -#include "hal_pwm.h" -#include "moddisplay.h" -#include "framebuffer.h" - -typedef struct _epaper_sld00200p_obj_t { - mp_obj_base_t base; - display_draw_callbacks_t draw_callbacks; - framebuffer_t * framebuffer; - machine_hard_spi_obj_t *spi; - machine_hard_pwm_obj_t *pwm; - pin_obj_t * pin_cs; - pin_obj_t * pin_panel_on; - pin_obj_t * pin_border; - pin_obj_t * pin_busy; - pin_obj_t * pin_reset; - pin_obj_t * pin_discharge; -#if 0 - pin_obj_t * pin_temp_sensor; -#endif -} epaper_sld00200p_obj_t; - -#define EPAPER_SLD00200P_COLOR_BLACK 0 -#define EPAPER_SLD00200P_COLOR_WHITE 1 - -static void set_pixel(void * p_display, - uint16_t x, - uint16_t y, - uint16_t color) { - epaper_sld00200p_obj_t *self = (epaper_sld00200p_obj_t *)p_display; - - if (color == EPAPER_SLD00200P_COLOR_BLACK) { - framebuffer_pixel_clear(self->framebuffer, x, y); - } else { - framebuffer_pixel_set(self->framebuffer, x, y); - } -} - -/// \method __str__() -/// Return a string describing the SLD00200P object. -STATIC void epaper_sld00200_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - epaper_sld00200p_obj_t *self = o; - - mp_printf(print, "SLD00200(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin->port, - self->spi->pyb->spi->init.mosi_pin->pin, - self->spi->pyb->spi->init.miso_pin->port, - self->spi->pyb->spi->init.miso_pin->pin, - self->spi->pyb->spi->init.clk_pin->port, - self->spi->pyb->spi->init.clk_pin->pin); - - mp_printf(print, " PWM(pwm_pin=%u),\n", - self->pwm->pyb->pwm->init.pwm_pin); - - mp_printf(print, " cs=(port=%u, pin=%u), panel_on=(port=%u, pin=%u),\n", - self->pin_cs->port, - self->pin_cs->pin, - self->pin_panel_on->port, - self->pin_panel_on->pin); - - mp_printf(print, " border=(port=%u, pin=%u), busy=(port=%u, pin=%u),\n", - self->pin_border->port, - self->pin_border->pin, - self->pin_busy->port, - self->pin_busy->pin); - - mp_printf(print, " reset=(port=%u, pin=%u), discharge=(port=%u, pin=%u),\n", - self->pin_reset->port, - self->pin_reset->pin, - self->pin_discharge->port, - self->pin_discharge->pin); - - mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", - self->framebuffer->screen_width, - self->framebuffer->screen_height, - self->framebuffer->line_orientation, - self->framebuffer->fb_stride, - self->framebuffer->fb_dirty_stride); -} - -// for make_new -enum { - ARG_NEW_WIDTH, - ARG_NEW_HEIGHT, - ARG_NEW_SPI, - ARG_NEW_PWM, - ARG_NEW_CS, - ARG_NEW_PANEL_ON, - ARG_NEW_BORDER, - ARG_NEW_BUSY, - ARG_NEW_RESET, - ARG_NEW_DISCHARGE, - ARG_NEW_TEMP_SENSOR, -}; - -/* -from machine import Pin, SPI, PWM -from display import SLD00200P -import draw -reset = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) -panel_on = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) -discharge = Pin("A19", mode=Pin.OUT, pull=Pin.PULL_UP) -border = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) -busy = Pin("A18", mode=Pin.IN, pull=Pin.PULL_DISABLED) -cs = Pin("A22", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -pwm = PWM(0, Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP), freq=PWM.FREQ_250KHZ, duty=50, period=2) -d = SLD00200P(264, 176, spi, pwm, cs, panel_on, border, busy, reset, discharge) -draw.text(d, "Hello World!", 32, 32) -d.show() - -Example for nrf52840 / pca10056: - -from machine import Pin, SPI, PWM -from display import SLD00200P -import draw -reset = Pin("B7", mode=Pin.OUT, pull=Pin.PULL_UP) -panel_on = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) -discharge = Pin("B9", mode=Pin.OUT, pull=Pin.PULL_UP) -border = Pin("B4", mode=Pin.OUT, pull=Pin.PULL_UP) -busy = Pin("B8", mode=Pin.IN, pull=Pin.PULL_DISABLED) -cs = Pin("B12", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -pwm = PWM(0, Pin("B6", mode=Pin.OUT, pull=Pin.PULL_UP), freq=PWM.FREQ_250KHZ, duty=50, period=2) -d = SLD00200P(264, 176, spi, pwm, cs, panel_on, border, busy, reset, discharge) -draw.text(d, "Hello World!", 32, 32) -d.show() - -*/ -STATIC mp_obj_t epaper_sld00200p_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - static const mp_arg_t allowed_args[] = { - { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_PWM, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_PANEL_ON, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_BORDER, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_BUSY, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_DISCHARGE, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, -#if 0 - { ARG_NEW_TEMP_SENSOR, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, -#endif - }; - - // parse args - mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; - mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - - epaper_sld00200p_obj_t *s = m_new_obj_with_finaliser(epaper_sld00200p_obj_t); - s->base.type = type; - s->draw_callbacks.pixel_set = set_pixel; - - mp_int_t width; - mp_int_t height; - - if (args[ARG_NEW_WIDTH].u_int > 0) { - width = args[ARG_NEW_WIDTH].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display width not set")); - } - - if (args[ARG_NEW_HEIGHT].u_int > 0) { - height = args[ARG_NEW_HEIGHT].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display height not set")); - } - - if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { - s->spi = args[ARG_NEW_SPI].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display SPI not set")); - } - - if (args[ARG_NEW_PWM].u_obj != MP_OBJ_NULL) { - s->pwm = args[ARG_NEW_PWM].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display PWM not set")); - } - - if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { - s->pin_cs = args[ARG_NEW_CS].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display CS Pin not set")); - } - - if (args[ARG_NEW_PANEL_ON].u_obj != MP_OBJ_NULL) { - s->pin_panel_on = args[ARG_NEW_PANEL_ON].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Panel-on Pin not set")); - } - - if (args[ARG_NEW_BORDER].u_obj != MP_OBJ_NULL) { - s->pin_border = args[ARG_NEW_BORDER].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Border Pin not set")); - } - - if (args[ARG_NEW_BUSY].u_obj != MP_OBJ_NULL) { - s->pin_busy = args[ARG_NEW_BUSY].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Busy Pin not set")); - } - - if (args[ARG_NEW_RESET].u_obj != MP_OBJ_NULL) { - s->pin_reset = args[ARG_NEW_RESET].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Reset Pin not set")); - } - - if (args[ARG_NEW_DISCHARGE].u_obj != MP_OBJ_NULL) { - s->pin_discharge = args[ARG_NEW_DISCHARGE].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Reset Pin not set")); - } - -#if 0 - if (args[ARG_NEW_TEMP_SENSOR].u_obj != MP_OBJ_NULL) { - s->pin_temp_sensor = args[ARG_NEW_TEMP_SENSOR].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Busy Pin not set)")); - } -#endif - - framebuffer_init_t init_conf = { - .width = width, - .height = height, - .line_orientation = FRAMEBUFFER_LINE_DIR_HORIZONTAL, - .double_buffer = false - }; - - s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); - - framebuffer_init(s->framebuffer, &init_conf); - - driver_sld00200p_init(s->spi->pyb->spi->instance, - s->pwm->pyb->pwm->instance, - s->pin_cs, - s->pin_panel_on, - s->pin_border, - s->pin_busy, - s->pin_reset, - s->pin_discharge); - - // Default to white background - driver_sld00200p_clear(0x00); - - framebuffer_clear(s->framebuffer); - - driver_sld00200p_deinit(); - - return MP_OBJ_FROM_PTR(s); -} - -// text - -/// \method fill(color) -/// Fill framebuffer with the color defined as argument. -STATIC mp_obj_t epaper_sld00200p_fill(mp_obj_t self_in, mp_obj_t color) { - epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(self_in); - - if (color == MP_OBJ_NEW_SMALL_INT(EPAPER_SLD00200P_COLOR_BLACK)) { - framebuffer_clear(self->framebuffer); - } else { - framebuffer_fill(self->framebuffer); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(epaper_sld00200p_fill_obj, epaper_sld00200p_fill); - -static void render(framebuffer_t * p_framebuffer, bool refresh) { - for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { - if (p_framebuffer->fb_dirty[i].byte != 0 || refresh) { - for (uint16_t b = 0; b < 8; b++) { - if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1) || refresh) { - uint16_t line_num = (i * 8) + b; - driver_sld00200p_update_line(line_num, - &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], - &p_framebuffer->fb_old[line_num * p_framebuffer->fb_stride], - p_framebuffer->fb_stride); - } - } - - if (refresh == false) { - p_framebuffer->fb_dirty[i].byte = 0x00; - } - } - } -} - -/// \method show([num_of_refresh]) -/// Display content in framebuffer. -/// -/// - With no argument, no refresh is done. -/// - With `num_of_refresh` given, the lines touched by previous update -/// will be refreshed the given number of times. If no lines have been -/// touched, no update will be performed. To force a refresh, call the -/// refresh() method explicitly. -STATIC mp_obj_t epaper_sld00200p_show(size_t n_args, const mp_obj_t *args) { - epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); - - mp_int_t num_of_refresh = 0; - - if (n_args > 1) { - num_of_refresh = mp_obj_get_int(args[1]); - } - driver_sld00200p_reinit(); - - render(self->framebuffer, false); - framebuffer_flip(self->framebuffer); - - if (num_of_refresh > 0) { - while (num_of_refresh > 0) { - render(self->framebuffer, true); - num_of_refresh--; - } - } - - driver_sld00200p_deinit(); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_show_obj, 1, 2, epaper_sld00200p_show); - -/// \method refresh([num_of_refresh]) -/// Refresh content in framebuffer. -/// -/// - With no argument, 1 refresh will be done. -/// - With `num_of_refresh` given, The whole framebuffer will be considered -/// dirty and will be refreshed the given number of times. -STATIC mp_obj_t epaper_sld00200p_refresh(size_t n_args, const mp_obj_t *args) { - epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); - - mp_int_t num_of_refresh = 0; - - if (n_args > 1) { - num_of_refresh = mp_obj_get_int(args[1]); - } - - driver_sld00200p_reinit(); - - if (num_of_refresh > 0) { - while (num_of_refresh > 0) { - render(self->framebuffer, true); - num_of_refresh--; - } - } else { - // default to one refresh - render(self->framebuffer, true); - } - - driver_sld00200p_deinit(); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_refresh_obj, 1, 2, epaper_sld00200p_refresh); - -/// \method pixel(x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color of the pixel in framebuffer will be returend. -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t epaper_sld00200p_pixel(size_t n_args, const mp_obj_t *args) { - epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); - mp_int_t x = mp_obj_get_int(args[1]); - mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color = mp_obj_get_int(args[3]); - - set_pixel(self, x, y, color); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_pixel_obj, 3, 4, epaper_sld00200p_pixel); - -/// \method pixel(text, x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color will be the opposite of background (fill color). -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t epaper_sld00200p_text(size_t n_args, const mp_obj_t *args) { - epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(args[0]); - const char *str = mp_obj_str_get_str(args[1]); - mp_int_t x = mp_obj_get_int(args[2]); - mp_int_t y = mp_obj_get_int(args[3]); - mp_int_t color; - if (n_args >= 4) { - color = mp_obj_get_int(args[3]); - } - -// display_print_string(self->framebuffer, x, y, str); - - (void)x; - (void)y; - (void)self; - (void)str; - (void)color; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(epaper_sld00200p_text_obj, 4, 5, epaper_sld00200p_text); - - -STATIC mp_obj_t epaper_sld00200p_del(mp_obj_t self_in) { - epaper_sld00200p_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(epaper_sld00200p_del_obj, epaper_sld00200p_del); - -STATIC const mp_rom_map_elem_t epaper_sld00200p_locals_dict_table[] = { - { MP_ROM_QSTR(MP_QSTR___del__), MP_ROM_PTR(&epaper_sld00200p_del_obj) }, - { MP_ROM_QSTR(MP_QSTR_fill), MP_ROM_PTR(&epaper_sld00200p_fill_obj) }, - { MP_ROM_QSTR(MP_QSTR_show), MP_ROM_PTR(&epaper_sld00200p_show_obj) }, - { MP_ROM_QSTR(MP_QSTR_refresh), MP_ROM_PTR(&epaper_sld00200p_refresh_obj) }, - { MP_ROM_QSTR(MP_QSTR_text), MP_ROM_PTR(&epaper_sld00200p_text_obj) }, - { MP_ROM_QSTR(MP_QSTR_pixel), MP_ROM_PTR(&epaper_sld00200p_pixel_obj) }, -#if 0 - { MP_ROM_QSTR(MP_QSTR_bitmap), MP_ROM_PTR(&epaper_sld00200p_bitmap_obj) }, -#endif - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(EPAPER_SLD00200P_COLOR_BLACK) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(EPAPER_SLD00200P_COLOR_WHITE) }, - -}; - -STATIC MP_DEFINE_CONST_DICT(epaper_sld00200p_locals_dict, epaper_sld00200p_locals_dict_table); - - -const mp_obj_type_t epaper_sld00200p_type = { - { &mp_type_type }, - .name = MP_QSTR_SLD00200P, - .print = epaper_sld00200_print, - .make_new = epaper_sld00200p_make_new, - .locals_dict = (mp_obj_t)&epaper_sld00200p_locals_dict -}; - -#endif // MICROPY_PY_DISPLAY_EPAPER_SLD00200P diff --git a/nrf5/modules/display/epaper_sld00200p_obj.h b/nrf5/modules/display/epaper_sld00200p_obj.h deleted file mode 100644 index f6a3fa8ed9..0000000000 --- a/nrf5/modules/display/epaper_sld00200p_obj.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef EPAPER_SLD00200P_H__ -#define EPAPER_SLD00200P_H__ - -#include - -extern const mp_obj_type_t epaper_sld00200p_type; - -#endif // EPAPER_SLD00200P_H__ - diff --git a/nrf5/modules/display/framebuffer.c b/nrf5/modules/display/framebuffer.c deleted file mode 100644 index 988c7715ec..0000000000 --- a/nrf5/modules/display/framebuffer.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include -#include "py/obj.h" -#include "framebuffer.h" - -#if MICROPY_PY_DISPLAY_FRAMEBUFFER - -void framebuffer_init(framebuffer_t * p_fb, framebuffer_init_t * p_init_conf) { - uint16_t width = p_init_conf->width; - uint16_t height = p_init_conf->height; - - if (p_init_conf->line_orientation == FRAMEBUFFER_LINE_DIR_HORIZONTAL) { - uint16_t dirty_row_stride = height / 8; - p_fb->fb_dirty = m_new(framebuffer_byte_t, dirty_row_stride); - p_fb->fb_dirty_stride = dirty_row_stride; - p_fb->fb_stride = width / 8; - } else { // FRAMEBUFFER_LINE_DIR_VERTICAL - uint16_t dirty_column_stride = width / 8; - p_fb->fb_dirty = m_new(framebuffer_byte_t, dirty_column_stride); - p_fb->fb_dirty_stride = dirty_column_stride; - p_fb->fb_stride = height / 8; - } - - p_fb->fb_new = m_new(framebuffer_byte_t, (width * height / 8)); - - if (p_init_conf->double_buffer) { - p_fb->fb_old = m_new(framebuffer_byte_t, (width * height / 8)); - } - p_fb->line_orientation = p_init_conf->line_orientation; - p_fb->screen_width = width; - p_fb->screen_height = height; -} - - -void framebuffer_flip(framebuffer_t * p_fb) { - if (p_fb->fb_double) { - framebuffer_byte_t * old = p_fb->fb_old; - p_fb->fb_old = p_fb->fb_new; - p_fb->fb_new = old; - } -} - -void framebuffer_pixel_set(framebuffer_t * p_fb, uint16_t x, uint16_t y) { - if (p_fb->line_orientation == FRAMEBUFFER_LINE_DIR_HORIZONTAL) { - uint16_t col = (x / 8); - uint16_t row = y; - uint8_t bit_pos = x % 8; - - p_fb->fb_new[row * (p_fb->fb_stride) + col].byte |= (1 << bit_pos); - p_fb->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); - } else { - uint16_t col = x; - uint16_t row = (y / 8); - uint8_t bit_pos = y % 8; - - p_fb->fb_new[col * (p_fb->fb_stride) + row].byte |= (1 << bit_pos); - p_fb->fb_dirty[x / 8].byte |= (uint8_t)(0x1 << x % 8); - } -} - -void framebuffer_pixel_clear(framebuffer_t * p_fb, uint16_t x, uint16_t y) { - if (p_fb->line_orientation == FRAMEBUFFER_LINE_DIR_HORIZONTAL) { - uint16_t col = (x / 8); - uint16_t row = y; - uint8_t bit_pos = x % 8; - - p_fb->fb_new[row * (p_fb->fb_stride) + col].byte &= ~(1 << bit_pos); - p_fb->fb_dirty[y / 8].byte |= (uint8_t)(0x1 << y % 8); - } else { - uint16_t col = x; - uint16_t row = (y / 8); - uint8_t bit_pos = y % 8; - - p_fb->fb_new[col * (p_fb->fb_stride) + row].byte &= ~(1 << bit_pos); - p_fb->fb_dirty[x / 8].byte |= (uint8_t)(0x1 << x % 8); - } -} - -void framebuffer_clear(framebuffer_t * p_fb) { - memset(p_fb->fb_new, 0x00, p_fb->screen_width * p_fb->screen_height / 8); - memset(p_fb->fb_dirty, 0xFF, p_fb->fb_dirty_stride); -} - -void framebuffer_fill(framebuffer_t * p_fb) { - memset(p_fb->fb_new, 0xFF, p_fb->screen_width * p_fb->screen_height / 8); - memset(p_fb->fb_dirty, 0xFF, p_fb->fb_dirty_stride); -} - -#endif // MICROPY_PY_DISPLAY_FRAMEBUFFER diff --git a/nrf5/modules/display/framebuffer.h b/nrf5/modules/display/framebuffer.h deleted file mode 100644 index 1c9ad05b7c..0000000000 --- a/nrf5/modules/display/framebuffer.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef DISPLAY_FRAMEBUFFER_H__ -#define DISPLAY_FRAMEBUFFER_H__ - -#include -#include - -typedef struct { - uint8_t bit0 : 1; - uint8_t bit1 : 1; - uint8_t bit2 : 1; - uint8_t bit3 : 1; - uint8_t bit4 : 1; - uint8_t bit5 : 1; - uint8_t bit6 : 1; - uint8_t bit7 : 1; -} bits_le_t; - -typedef struct { - uint8_t bit7 : 1; - uint8_t bit6 : 1; - uint8_t bit5 : 1; - uint8_t bit4 : 1; - uint8_t bit3 : 1; - uint8_t bit2 : 1; - uint8_t bit1 : 1; - uint8_t bit0 : 1; -} bits_be_t; - -typedef struct { - union { - uint8_t byte; - bits_le_t bits_le; - bits_be_t bits_be; - }; -} framebuffer_byte_t; - -typedef enum { - FRAMEBUFFER_LINE_DIR_HORIZONTAL, - FRAMEBUFFER_LINE_DIR_VERTICAL -} framebuffer_line_orientation_t; - -typedef struct { - framebuffer_byte_t * fb_new; - framebuffer_byte_t * fb_old; - uint16_t fb_stride; - bool fb_double; - framebuffer_byte_t * fb_dirty; - uint16_t fb_dirty_stride; - uint16_t fb_orientation; - uint16_t screen_height; - uint16_t screen_width; - framebuffer_line_orientation_t line_orientation; -} framebuffer_t; - -typedef struct { - uint16_t width; - uint16_t height; - framebuffer_line_orientation_t line_orientation; - bool double_buffer; -} framebuffer_init_t; - -void framebuffer_init(framebuffer_t * p_fb, framebuffer_init_t * p_init_conf); -void framebuffer_deinit(framebuffer_t * p_fb); - -void framebuffer_flip(framebuffer_t * p_fb); -void framebuffer_pixel_set(framebuffer_t * p_fb, uint16_t x, uint16_t y); -void framebuffer_pixel_clear(framebuffer_t * p_fb, uint16_t x, uint16_t y); -void framebuffer_clear(framebuffer_t * p_fb); -void framebuffer_fill(framebuffer_t * p_fb); - -#endif // DISPLAY_FRAMEBUFFER_H__ diff --git a/nrf5/modules/display/lcd_ili9341_driver.c b/nrf5/modules/display/lcd_ili9341_driver.c deleted file mode 100644 index b6c4b2f7f2..0000000000 --- a/nrf5/modules/display/lcd_ili9341_driver.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/mphal.h" - -#include "lcd_ili9341_driver.h" -#include "hal_spi.h" -#include "hal_time.h" - -#if MICROPY_PY_DISPLAY_LCD_ILI9341 - -static pin_obj_t * mp_cs_pin; -static pin_obj_t * mp_dc_pin; -static NRF_SPI_Type * mp_instance; - - -static void raw_write(uint8_t value) -{ - hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); -} - -static void cmd_write(uint8_t value) -{ - mp_hal_pin_low(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); - - mp_hal_pin_high(mp_cs_pin); -} - -static void data_write(uint8_t value) -{ - mp_hal_pin_high(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); - - mp_hal_pin_high(mp_cs_pin); -} - -void driver_ili9341_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_obj_t * p_dc_pin) -{ - mp_instance = p_instance; - mp_cs_pin = p_cs_pin; - mp_dc_pin = p_dc_pin; -#if 0 - mp_hal_pin_high(enable_pin); - mp_hal_pin_high(backlight_pin); -#endif - - mp_hal_pin_high(mp_cs_pin); - mp_hal_pin_high(mp_dc_pin); - - // Read driver id - - mp_hal_delay_ms(1000); - - cmd_write(0x01); - - mp_hal_delay_ms(500); - - cmd_write(0xCF); - data_write(0x00); - data_write(0x8B); - data_write(0X30); - - cmd_write(0xED); - data_write(0x67); - data_write(0x03); - data_write(0X12); - data_write(0X81); - - cmd_write(0xE8); - data_write(0x85); - data_write(0x10); - data_write(0x7A); - - cmd_write(0xCB); - data_write(0x39); - data_write(0x2C); - data_write(0x00); - data_write(0x34); - data_write(0x02); - - cmd_write(0xF7); - data_write(0x20); - - cmd_write(0xEA); - data_write(0x00); - data_write(0x00); - - cmd_write(0xC0); /* Power control */ - data_write(0x1B); /* VRH[5:0] */ - - cmd_write(0xC1); /* Power control */ - data_write(0x10); /* SAP[2:0];BT[3:0] */ - - cmd_write(0xC5); /* VCM control */ - data_write(0x3F); - data_write(0x3C); - - cmd_write(0xC7); /* VCM control2 */ - data_write(0XB7); - - cmd_write(0x36); /* Memory Access Control */ - data_write(0x08); - - cmd_write(0x3A); - data_write(0x55); - - cmd_write(0xB1); - data_write(0x00); - data_write(0x1B); - - cmd_write(0xB6); /* Display Function Control */ - data_write(0x0A); - data_write(0xA2); - - cmd_write(0xF2); /* 3Gamma Function Disable */ - data_write(0x00); - - cmd_write(0x26); /* Gamma curve selected */ - data_write(0x01); - - cmd_write(0xE0); /* Set Gamma */ - data_write(0x0F); - data_write(0x2A); - data_write(0x28); - data_write(0x08); - data_write(0x0E); - data_write(0x08); - data_write(0x54); - data_write(0XA9); - data_write(0x43); - data_write(0x0A); - data_write(0x0F); - data_write(0x00); - data_write(0x00); - data_write(0x00); - data_write(0x00); - - cmd_write(0XE1); /* Set Gamma */ - data_write(0x00); - data_write(0x15); - data_write(0x17); - data_write(0x07); - data_write(0x11); - data_write(0x06); - data_write(0x2B); - data_write(0x56); - data_write(0x3C); - data_write(0x05); - data_write(0x10); - data_write(0x0F); - data_write(0x3F); - data_write(0x3F); - data_write(0x0F); - - cmd_write(0x11); /* Exit Sleep */ - - mp_hal_delay_ms(120); - - cmd_write(0x29); /* Display on */ -} - -static void set_col(uint16_t start_col, uint16_t end_col) -{ - cmd_write(0x2A); /* Column Command address */ - data_write(start_col >> 8); - data_write(start_col & 0xFF ); - data_write(end_col >> 8); - data_write(end_col & 0xFF); -} - -static void set_page(uint16_t start_page, uint16_t end_page) -{ - cmd_write(0x2B); /* Column Command address */ - data_write(start_page >> 8); - data_write(start_page & 0xFF); - data_write(end_page >> 8); - data_write(end_page & 0xFF); -} - -void driver_ili9341_clear(uint16_t color) -{ - set_col(0, 239); - set_page(0, 319); - - cmd_write(0x2c); // start writing to the display ram - - mp_hal_pin_high(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - for(uint16_t i = 0; i < 38400; i++) - { - raw_write(color >> 8); - raw_write(color & 0xFF); - raw_write(color >> 8); - raw_write(color & 0xFF); - } - - mp_hal_pin_high(mp_cs_pin); -} - -void driver_ili9341_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { - set_col(0, 239); - set_page(line, line); - - cmd_write(0x2c); - - mp_hal_pin_high(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - for (uint16_t i = 0; i < len; i++) { - uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; - for (uint8_t pixel_pos = 0; pixel_pos < 8; pixel_pos++) { - if (((byte >> pixel_pos) & 0x1) == 0x0) { - data_write(0x00); - data_write(0x00); - } else { - data_write(0xFF); - data_write(0xFF); - } - } - } - - mp_hal_pin_high(mp_cs_pin); -} - -#endif diff --git a/nrf5/modules/display/lcd_ili9341_driver.h b/nrf5/modules/display/lcd_ili9341_driver.h deleted file mode 100644 index aa01ecfaa4..0000000000 --- a/nrf5/modules/display/lcd_ili9341_driver.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef LCD_ILI9341_DRIVER_H__ -#define LCD_ILI9341_DRIVER_H__ - -#include "py/mphal.h" - -#include "hal_spi.h" -#include "framebuffer.h" - -void driver_ili9341_init(NRF_SPI_Type * p_instance, pin_obj_t * cs_pin, pin_obj_t * dc_pin); - -void driver_ili9341_clear(uint16_t color); - -void driver_ili9341_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); - -#endif // LCD_ILI9341_DRIVER_H__ diff --git a/nrf5/modules/display/lcd_ili9341_obj.c b/nrf5/modules/display/lcd_ili9341_obj.c deleted file mode 100644 index 968b3bf858..0000000000 --- a/nrf5/modules/display/lcd_ili9341_obj.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "py/obj.h" -#include "py/runtime.h" -#include "py/mphal.h" -#include "genhdr/pins.h" - -#include "lcd_ili9341_driver.h" -// For now PWM is only enabled for nrf52 targets. -#if MICROPY_PY_DISPLAY_LCD_ILI9341 - -/// \moduleref display -/// \class ILI9341 - ILI9341 TFT LCD display driver. - -#include "moddisplay.h" -#include "framebuffer.h" -#include "pin.h" -#include "spi.h" - -typedef struct _lcd_ili9341_obj_t { - mp_obj_base_t base; - display_draw_callbacks_t draw_callbacks; - framebuffer_t * framebuffer; - machine_hard_spi_obj_t *spi; - pin_obj_t * pin_cs; - pin_obj_t * pin_dc; -} lcd_ili9341_obj_t; - -#define LCD_ILI9341_COLOR_BLACK 0 -#define LCD_ILI9341_COLOR_WHITE 1 - -static void set_pixel(void * p_display, - uint16_t x, - uint16_t y, - uint16_t color) { - lcd_ili9341_obj_t *self = (lcd_ili9341_obj_t *)p_display; - - if (color == LCD_ILI9341_COLOR_BLACK) { - framebuffer_pixel_clear(self->framebuffer, x, y); - } else { - framebuffer_pixel_set(self->framebuffer, x, y); - } -} - -/// \method __str__() -/// Return a string describing the ILI9341 object. -STATIC void lcd_ili9341_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - lcd_ili9341_obj_t *self = o; - - mp_printf(print, "ILI9341(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin->port, - self->spi->pyb->spi->init.mosi_pin->pin, - self->spi->pyb->spi->init.miso_pin->port, - self->spi->pyb->spi->init.miso_pin->pin, - self->spi->pyb->spi->init.clk_pin->port, - self->spi->pyb->spi->init.clk_pin->pin); - - mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u),\n", - self->pin_cs->port, - self->pin_cs->pin, - self->pin_dc->port, - self->pin_dc->pin); - - mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", - self->framebuffer->screen_width, - self->framebuffer->screen_height, - self->framebuffer->line_orientation, - self->framebuffer->fb_stride, - self->framebuffer->fb_dirty_stride); -} - -// for make_new -enum { - ARG_NEW_WIDTH, - ARG_NEW_HEIGHT, - ARG_NEW_SPI, - ARG_NEW_CS, - ARG_NEW_DC, -}; - -/* - -Example for nrf51822 / pca10028: - -from machine import Pin, SPI -from display import ILI9341 -cs = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) -dc = Pin("A18", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -d = ILI9341(240, 320, spi, cs, dc) -d.text("Hello World!", 32, 32) -d.show() - -Example for nrf52832 / pca10040: - -from machine import Pin, SPI -from display import ILI9341 -cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) -dc = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -d = ILI9341(240, 320, spi, cs, dc) -d.text("Hello World!", 32, 32) -d.show() - -Example for nrf52840 / pca10056: - -from machine import Pin, SPI -from display import ILI9341 -cs = Pin("B6", mode=Pin.OUT, pull=Pin.PULL_UP) -dc = Pin("B7", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -d = ILI9341(240, 320, spi, cs, dc) -d.text("Hello World!", 32, 32) -d.show() - -*/ -STATIC mp_obj_t lcd_ili9341_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - static const mp_arg_t allowed_args[] = { - { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_DC, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - }; - - // parse args - mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; - mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - - lcd_ili9341_obj_t *s = m_new_obj_with_finaliser(lcd_ili9341_obj_t); - s->base.type = type; - s->draw_callbacks.pixel_set = set_pixel; - - mp_int_t width; - mp_int_t height; - - if (args[ARG_NEW_WIDTH].u_int > 0) { - width = args[ARG_NEW_WIDTH].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display width not set")); - } - - if (args[ARG_NEW_HEIGHT].u_int > 0) { - height = args[ARG_NEW_HEIGHT].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display height not set")); - } - - if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { - s->spi = args[ARG_NEW_SPI].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display SPI not set")); - } - - if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { - s->pin_cs = args[ARG_NEW_CS].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display CS Pin not set")); - } - - if (args[ARG_NEW_DC].u_obj != MP_OBJ_NULL) { - s->pin_dc = args[ARG_NEW_DC].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display DC Pin not set")); - } - - framebuffer_init_t init_conf = { - .width = width, - .height = height, - .line_orientation = FRAMEBUFFER_LINE_DIR_HORIZONTAL, - .double_buffer = false - }; - - s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); - - framebuffer_init(s->framebuffer, &init_conf); - - driver_ili9341_init(s->spi->pyb->spi->instance, s->pin_cs, s->pin_dc); - // Default to white background - driver_ili9341_clear(0x0000); - - framebuffer_clear(s->framebuffer); - - return MP_OBJ_FROM_PTR(s); -} - -// text - -/// \method fill(color) -/// Fill framebuffer with the color defined as argument. -STATIC mp_obj_t lcd_ili9341_fill(mp_obj_t self_in, mp_obj_t color) { - lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(self_in); - - if (color == MP_OBJ_NEW_SMALL_INT(LCD_ILI9341_COLOR_BLACK)) { - framebuffer_clear(self->framebuffer); - } else { - framebuffer_fill(self->framebuffer); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_ili9341_fill_obj, lcd_ili9341_fill); - -static void render(framebuffer_t * p_framebuffer) { - for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { - if (p_framebuffer->fb_dirty[i].byte != 0) { - for (uint16_t b = 0; b < 8; b++) { - if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { - uint16_t line_num = (i * 8) + b; - driver_ili9341_update_line(line_num, - &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], - p_framebuffer->fb_stride); - } - } - - p_framebuffer->fb_dirty[i].byte = 0x00; - } - } -} - -/// \method show() -/// Display content in framebuffer. -STATIC mp_obj_t lcd_ili9341_show(size_t n_args, const mp_obj_t *args) { - lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(args[0]); - - render(self->framebuffer); - framebuffer_flip(self->framebuffer); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ili9341_show_obj, 1, 2, lcd_ili9341_show); - -/// \method refresh([num_of_refresh]) -/// Refresh content in framebuffer. -/// -/// - With no argument, 1 refresh will be done. -/// - With `num_of_refresh` given, The whole framebuffer will be considered -/// dirty and will be refreshed the given number of times. -STATIC mp_obj_t lcd_ili9341_refresh(mp_obj_t self_in) { - lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ili9341_refresh_obj, lcd_ili9341_refresh); - -/// \method pixel(x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color of the pixel in framebuffer will be returend. -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t lcd_ili9341_pixel(size_t n_args, const mp_obj_t *args) { - lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(args[0]); - mp_int_t x = mp_obj_get_int(args[1]); - mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color = mp_obj_get_int(args[3]); - - set_pixel(self, x, y, color); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ili9341_pixel_obj, 3, 4, lcd_ili9341_pixel); - -/// \method pixel(text, x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color will be the opposite of background (fill color). -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t lcd_ili9341_text(size_t n_args, const mp_obj_t *args) { - lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(args[0]); - const char *str = mp_obj_str_get_str(args[1]); - mp_int_t x = mp_obj_get_int(args[2]); - mp_int_t y = mp_obj_get_int(args[3]); - mp_int_t color; - if (n_args >= 4) { - color = mp_obj_get_int(args[3]); - } - - // display_print_string(self->framebuffer, x, y, str); - - (void)x; - (void)y; - (void)self; - (void)str; - (void)color; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ili9341_text_obj, 4, 5, lcd_ili9341_text); - -STATIC mp_obj_t lcd_ili9341_del(mp_obj_t self_in) { - lcd_ili9341_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ili9341_del_obj, lcd_ili9341_del); - -STATIC const mp_map_elem_t lcd_ili9341_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&lcd_ili9341_del_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&lcd_ili9341_fill_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&lcd_ili9341_show_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&lcd_ili9341_text_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&lcd_ili9341_pixel_obj) }, -#if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&lcd_ili9341_bitmap_obj) }, -#endif - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_ILI9341_COLOR_BLACK) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_ILI9341_COLOR_WHITE) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, -}; - -STATIC MP_DEFINE_CONST_DICT(lcd_ili9341_locals_dict, lcd_ili9341_locals_dict_table); - -const mp_obj_type_t lcd_ili9341_type = { - { &mp_type_type }, - .name = MP_QSTR_ILI9341, - .print = lcd_ili9341_print, - .make_new = lcd_ili9341_make_new, - .locals_dict = (mp_obj_t)&lcd_ili9341_locals_dict -}; - -#endif // MICROPY_PY_DISPLAY_LCD_ILI9341 diff --git a/nrf5/modules/display/lcd_ili9341_obj.h b/nrf5/modules/display/lcd_ili9341_obj.h deleted file mode 100644 index 097b7eb698..0000000000 --- a/nrf5/modules/display/lcd_ili9341_obj.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef LCD_ILI9341_H__ -#define LCD_ILI9341_H__ - -#include - -extern const mp_obj_type_t lcd_ili9341_type; - -#endif // LCD_ILI9341_H__ - diff --git a/nrf5/modules/display/lcd_ls0xxb7dxxx_driver.c b/nrf5/modules/display/lcd_ls0xxb7dxxx_driver.c deleted file mode 100644 index 686a626682..0000000000 --- a/nrf5/modules/display/lcd_ls0xxb7dxxx_driver.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "py/mphal.h" - -#include "lcd_ls0xxb7dxxx_driver.h" -#include "hal_spi.h" -#include "hal_time.h" - -#include "framebuffer.h" - -#if MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX - -static pin_obj_t * mp_cs_pin; -static pin_obj_t * mp_disp_pin; -static pin_obj_t * mp_extcomin_pin; -static pin_obj_t * mp_extmode_pin; -static pin_obj_t * mp_power_control_pin; -static pin_obj_t * mp_power_charge_pin; -static NRF_SPI_Type * mp_instance; - - -static void raw_write(uint8_t value) -{ - hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); -} - -void driver_ls0xxb7dxxx_init(NRF_SPI_Type * p_instance, - pin_obj_t * p_cs_pin, - pin_obj_t * p_disp_pin, - pin_obj_t * p_ext_com_in_pin, - pin_obj_t * p_ext_mode_pin, - pin_obj_t * p_power_control_pin, - pin_obj_t * p_power_charge_pin) { - mp_instance = p_instance; - mp_cs_pin = p_cs_pin; - mp_disp_pin = p_disp_pin; - mp_extcomin_pin = p_ext_com_in_pin; - mp_extmode_pin = p_ext_mode_pin; - mp_power_control_pin = p_power_control_pin; - mp_power_charge_pin = p_power_charge_pin; - - mp_hal_pin_high(mp_extcomin_pin); - mp_hal_pin_low(mp_disp_pin); - mp_hal_pin_low(mp_cs_pin); - mp_hal_pin_low(mp_extmode_pin); - mp_hal_pin_low(mp_power_charge_pin); - mp_hal_pin_low(mp_power_control_pin); - - // power on display - mp_hal_pin_high(mp_power_charge_pin); - mp_hal_pin_high(mp_power_control_pin); - - // display on - mp_hal_pin_high(mp_disp_pin); - - mp_hal_pin_low(mp_extcomin_pin); - -} - -void driver_ls0xxb7dxxx_clear(uint16_t color) -{ - mp_hal_pin_high(mp_cs_pin); - raw_write(0x04); // clear command - raw_write(0x00); - mp_hal_pin_low(mp_cs_pin); -} - -void driver_ls0xxb7dxxx_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { - // update single line - 0x01 <50bytes data> 0x00 0x00 - // update multi line - 0x01 <50bytes data> 0x00 [ <50bytes data> 0x00] 0x00 - - mp_hal_pin_high(mp_cs_pin); - - mp_hal_delay_us(3); - - raw_write(0x01); - - raw_write(line); - for (uint8_t i = 0; i < 50; i++) - { - uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; - raw_write(~byte); - } - raw_write(0x00); - - raw_write(0x00); - - mp_hal_delay_us(1); - - mp_hal_pin_low(mp_cs_pin); -} - -#endif diff --git a/nrf5/modules/display/lcd_ls0xxb7dxxx_driver.h b/nrf5/modules/display/lcd_ls0xxb7dxxx_driver.h deleted file mode 100644 index 380fba0b23..0000000000 --- a/nrf5/modules/display/lcd_ls0xxb7dxxx_driver.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef LCD_LS0XXB7DXXX_DRIVER_H__ -#define LCD_LS0XXB7DXXX_DRIVER_H__ - -#include "py/mphal.h" - -#include "hal_spi.h" -#include "framebuffer.h" - -void driver_ls0xxb7dxxx_init(NRF_SPI_Type * p_instance, - pin_obj_t * p_cs_pin, - pin_obj_t * p_disp_pin, - pin_obj_t * p_ext_com_in_pin, - pin_obj_t * p_ext_mode_pin, - pin_obj_t * p_power_control_pin, - pin_obj_t * p_power_charge_pin); - -void driver_ls0xxb7dxxx_clear(uint16_t color); - -void driver_ls0xxb7dxxx_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); - -#endif // LCD_LS0XXB7DXXX_DRIVER_H__ diff --git a/nrf5/modules/display/lcd_ls0xxb7dxxx_obj.c b/nrf5/modules/display/lcd_ls0xxb7dxxx_obj.c deleted file mode 100644 index afbc1f6203..0000000000 --- a/nrf5/modules/display/lcd_ls0xxb7dxxx_obj.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" -#include "py/runtime.h" -#include "py/mphal.h" -#include "genhdr/pins.h" - -#include "lcd_ls0xxb7dxxx_driver.h" - -#if MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX - -/// \moduleref display -/// \class LS0XXB7DXXX - LS0XXB7DXXX TFT LCD display driver. - -#include "moddisplay.h" -#include "framebuffer.h" -#include "pin.h" -#include "spi.h" - -typedef struct _lcd_ls0xxb7dxxx_obj_t { - mp_obj_base_t base; - display_draw_callbacks_t draw_callbacks; - framebuffer_t * framebuffer; - machine_hard_spi_obj_t *spi; - pin_obj_t * pin_cs; - pin_obj_t * pin_disp; - pin_obj_t * pin_extcomin; - pin_obj_t * pin_extmode; - pin_obj_t * pin_power_control; - pin_obj_t * pin_power_charge; -} lcd_ls0xxb7dxxx_obj_t; - -#define LCD_LS0XXB7DXXX_COLOR_BLACK 0 -#define LCD_LS0XXB7DXXX_COLOR_WHITE 1 - -static void set_pixel(void * p_display, - uint16_t x, - uint16_t y, - uint16_t color) { - lcd_ls0xxb7dxxx_obj_t *self = (lcd_ls0xxb7dxxx_obj_t *)p_display; - - if (color == LCD_LS0XXB7DXXX_COLOR_BLACK) { - framebuffer_pixel_set(self->framebuffer, x, y); - } else { - framebuffer_pixel_clear(self->framebuffer, x, y); - } -} - -/// \method __str__() -/// Return a string describing the LS0XXB7DXXX object. -STATIC void lcd_ls0xxb7dxxx_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - lcd_ls0xxb7dxxx_obj_t *self = o; - - mp_printf(print, "LS0XXB7DXXX(SPI(mosi=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin->port, - self->spi->pyb->spi->init.mosi_pin->pin, - self->spi->pyb->spi->init.clk_pin->port, - self->spi->pyb->spi->init.clk_pin->pin); - - mp_printf(print, " cs=(port=%u, pin=%u), disp=(port=%u, pin=%u), extcomin=(port=%u, pin=%u),\n", - self->pin_cs->port, - self->pin_cs->pin, - self->pin_disp->port, - self->pin_disp->pin, - self->pin_extcomin->port, - self->pin_extcomin->pin); - mp_printf(print, " extmode=(port=%u, pin=%u), power_control=(port=%u, pin=%u), power_charge=(port=%u, pin=%u),\n", - self->pin_extmode->port, - self->pin_extmode->pin, - self->pin_power_control->port, - self->pin_power_control->pin, - self->pin_power_charge->port, - self->pin_power_charge->pin); - - mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", - self->framebuffer->screen_width, - self->framebuffer->screen_height, - self->framebuffer->line_orientation, - self->framebuffer->fb_stride, - self->framebuffer->fb_dirty_stride); -} - -// for make_new -enum { - ARG_NEW_WIDTH, - ARG_NEW_HEIGHT, - ARG_NEW_SPI, - ARG_NEW_CS, - ARG_NEW_DISP, - ARG_NEW_EXTCOMIN, - ARG_NEW_EXTMODE, - ARG_NEW_POWER_CONTROL, - ARG_NEW_POWER_CHARGE -}; - -/* - -Example for nrf52840 / pca10056: - -from machine import Pin, SPI -from display import LS0XXB7DXXX -import draw -cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) -disp = Pin("B4", mode=Pin.OUT, pull=Pin.PULL_UP) -extcomin = Pin("A28", mode=Pin.OUT, pull=Pin.PULL_UP) -extmode = Pin("B5", mode=Pin.OUT, pull=Pin.PULL_UP) -power_control = Pin("A29", mode=Pin.OUT, pull=Pin.PULL_UP) -power_charge = Pin("A30", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=2000000, firstbit=SPI.LSB) -d = LS0XXB7DXXX(400, 240, spi, cs, disp, extcomin, extmode, power_control, power_charge) -draw.text(d, "Hello World!", 32, 32) -d.show() - -*/ -STATIC mp_obj_t lcd_ls0xxb7dxxx_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - static const mp_arg_t allowed_args[] = { - { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_DISP, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_EXTCOMIN, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_EXTMODE, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_POWER_CONTROL, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_POWER_CHARGE, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - }; - - // parse args - mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; - mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - - lcd_ls0xxb7dxxx_obj_t *s = m_new_obj_with_finaliser(lcd_ls0xxb7dxxx_obj_t); - s->base.type = type; - s->draw_callbacks.pixel_set = set_pixel; - - mp_int_t width; - mp_int_t height; - - if (args[ARG_NEW_WIDTH].u_int > 0) { - width = args[ARG_NEW_WIDTH].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display width not set")); - } - - if (args[ARG_NEW_HEIGHT].u_int > 0) { - height = args[ARG_NEW_HEIGHT].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display height not set")); - } - - if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { - s->spi = args[ARG_NEW_SPI].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display SPI not set")); - } - - if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { - s->pin_cs = args[ARG_NEW_CS].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display CS Pin not set")); - } - - if (args[ARG_NEW_DISP].u_obj != MP_OBJ_NULL) { - s->pin_disp = args[ARG_NEW_DISP].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Disp Pin not set")); - } - - if (args[ARG_NEW_EXTCOMIN].u_obj != MP_OBJ_NULL) { - s->pin_extcomin = args[ARG_NEW_EXTCOMIN].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display ExtComIn Pin not set")); - } - - if (args[ARG_NEW_EXTMODE].u_obj != MP_OBJ_NULL) { - s->pin_extmode = args[ARG_NEW_EXTMODE].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display ExtMode Pin not set")); - } - - if (args[ARG_NEW_POWER_CONTROL].u_obj != MP_OBJ_NULL) { - s->pin_power_control = args[ARG_NEW_POWER_CONTROL].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display PowerControl Pin not set")); - } - - if (args[ARG_NEW_POWER_CHARGE].u_obj != MP_OBJ_NULL) { - s->pin_power_charge = args[ARG_NEW_POWER_CHARGE].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display PowerCharge Pin not set")); - } - - framebuffer_init_t init_conf = { - .width = width, - .height = height, - .line_orientation = FRAMEBUFFER_LINE_DIR_HORIZONTAL, - .double_buffer = false - }; - - s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); - - framebuffer_init(s->framebuffer, &init_conf); - - driver_ls0xxb7dxxx_init(s->spi->pyb->spi->instance, - s->pin_cs, - s->pin_disp, - s->pin_extcomin, - s->pin_extmode, - s->pin_power_control, - s->pin_power_charge); - - // Default to black background - driver_ls0xxb7dxxx_clear(0x00); - - framebuffer_clear(s->framebuffer); - - return MP_OBJ_FROM_PTR(s); -} - -// text - -/// \method fill(color) -/// Fill framebuffer with the color defined as argument. -STATIC mp_obj_t lcd_ls0xxb7dxxx_fill(mp_obj_t self_in, mp_obj_t color) { - lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(self_in); - - if (color == MP_OBJ_NEW_SMALL_INT(LCD_LS0XXB7DXXX_COLOR_BLACK)) { - framebuffer_fill(self->framebuffer); - } else { - framebuffer_clear(self->framebuffer); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_ls0xxb7dxxx_fill_obj, lcd_ls0xxb7dxxx_fill); - -static void render(framebuffer_t * p_framebuffer) { - for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { - if (p_framebuffer->fb_dirty[i].byte != 0) { - for (uint16_t b = 0; b < 8; b++) { - if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { - uint16_t line_num = (i * 8) + b; - driver_ls0xxb7dxxx_update_line(line_num, - &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], - p_framebuffer->fb_stride); - } - } - - p_framebuffer->fb_dirty[i].byte = 0x00; - } - } -} - -/// \method show() -/// Display content in framebuffer. -STATIC mp_obj_t lcd_ls0xxb7dxxx_show(size_t n_args, const mp_obj_t *args) { - lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(args[0]); - - render(self->framebuffer); - framebuffer_flip(self->framebuffer); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ls0xxb7dxxx_show_obj, 1, 2, lcd_ls0xxb7dxxx_show); - -/// \method refresh([num_of_refresh]) -/// Refresh content in framebuffer. -/// -/// - With no argument, 1 refresh will be done. -/// - With `num_of_refresh` given, The whole framebuffer will be considered -/// dirty and will be refreshed the given number of times. -STATIC mp_obj_t lcd_ls0xxb7dxxx_refresh(mp_obj_t self_in) { - lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ls0xxb7dxxx_refresh_obj, lcd_ls0xxb7dxxx_refresh); - -/// \method pixel(x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color of the pixel in framebuffer will be returend. -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t lcd_ls0xxb7dxxx_pixel(size_t n_args, const mp_obj_t *args) { - lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(args[0]); - mp_int_t x = mp_obj_get_int(args[1]); - mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color = mp_obj_get_int(args[3]); - - set_pixel(self, x, y, color); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ls0xxb7dxxx_pixel_obj, 4, 4, lcd_ls0xxb7dxxx_pixel); - -/// \method pixel(text, x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color will be the opposite of background (fill color). -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t lcd_ls0xxb7dxxx_text(size_t n_args, const mp_obj_t *args) { - lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(args[0]); - const char *str = mp_obj_str_get_str(args[1]); - mp_int_t x = mp_obj_get_int(args[2]); - mp_int_t y = mp_obj_get_int(args[3]); - mp_int_t color; - if (n_args >= 4) { - color = mp_obj_get_int(args[3]); - } - - //display_print_string(self->framebuffer, x, y, str); - - (void)x; - (void)y; - (void)self; - (void)str; - (void)color; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ls0xxb7dxxx_text_obj, 4, 5, lcd_ls0xxb7dxxx_text); - -STATIC mp_obj_t lcd_ls0xxb7dxxx_del(mp_obj_t self_in) { - lcd_ls0xxb7dxxx_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ls0xxb7dxxx_del_obj, lcd_ls0xxb7dxxx_del); - -STATIC const mp_map_elem_t lcd_ls0xxb7dxxx_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&lcd_ls0xxb7dxxx_del_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&lcd_ls0xxb7dxxx_fill_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&lcd_ls0xxb7dxxx_show_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&lcd_ls0xxb7dxxx_text_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&lcd_ls0xxb7dxxx_pixel_obj) }, -#if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&lcd_ls0xxb7dxxx_bitmap_obj) }, -#endif - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_LS0XXB7DXXX_COLOR_BLACK) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_LS0XXB7DXXX_COLOR_WHITE) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, -}; - -STATIC MP_DEFINE_CONST_DICT(lcd_ls0xxb7dxxx_locals_dict, lcd_ls0xxb7dxxx_locals_dict_table); - -const mp_obj_type_t lcd_ls0xxb7dxxx_type = { - { &mp_type_type }, - .name = MP_QSTR_LS0XXB7DXXX, - .print = lcd_ls0xxb7dxxx_print, - .make_new = lcd_ls0xxb7dxxx_make_new, - .locals_dict = (mp_obj_t)&lcd_ls0xxb7dxxx_locals_dict -}; - -#endif // MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX diff --git a/nrf5/modules/display/lcd_ls0xxb7dxxx_obj.h b/nrf5/modules/display/lcd_ls0xxb7dxxx_obj.h deleted file mode 100644 index a1f2b3f833..0000000000 --- a/nrf5/modules/display/lcd_ls0xxb7dxxx_obj.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef LCD_LS0XXB7DXXX_H__ -#define LCD_LS0XXB7DXXX_H__ - -#include - -extern const mp_obj_type_t lcd_ls0xxb7dxxx_type; - -#endif // LCD_LS0XXB7DXXX_H__ - diff --git a/nrf5/modules/display/lcd_ssd1289_driver.c b/nrf5/modules/display/lcd_ssd1289_driver.c deleted file mode 100644 index db2bae8030..0000000000 --- a/nrf5/modules/display/lcd_ssd1289_driver.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "py/mphal.h" - -#include "lcd_ssd1289_driver.h" -#include "hal_time.h" - -#include "framebuffer.h" - -#if MICROPY_PY_DISPLAY_LCD_SSD1289 - -static pin_obj_t * mp_cs_pin; -static pin_obj_t * mp_rs_pin; -static pin_obj_t * mp_wr_pin; -static pin_obj_t * mp_reset_pin; -static pin_obj_t * mp_d0_pin; -static pin_obj_t * mp_d1_pin; -static pin_obj_t * mp_d2_pin; -static pin_obj_t * mp_d3_pin; -static pin_obj_t * mp_d4_pin; -static pin_obj_t * mp_d5_pin; -static pin_obj_t * mp_d6_pin; -static pin_obj_t * mp_d7_pin; - -static void data_port_write(uint8_t byte) { - mp_hal_pin_write(mp_d0_pin, (byte >> 0) & 0x1); - mp_hal_pin_write(mp_d1_pin, (byte >> 1) & 0x1); - mp_hal_pin_write(mp_d2_pin, (byte >> 2) & 0x1); - mp_hal_pin_write(mp_d3_pin, (byte >> 3) & 0x1); - mp_hal_pin_write(mp_d4_pin, (byte >> 4) & 0x1); - mp_hal_pin_write(mp_d5_pin, (byte >> 5) & 0x1); - mp_hal_pin_write(mp_d6_pin, (byte >> 6) & 0x1); - mp_hal_pin_write(mp_d7_pin, (byte >> 7) & 0x1); - mp_hal_pin_low(mp_wr_pin); - mp_hal_delay_us(20); - mp_hal_pin_high(mp_wr_pin); -} - -static void cmd_write(uint8_t cmd) { - mp_hal_pin_low(mp_rs_pin); - mp_hal_delay_us(20); - data_port_write(0x00); - mp_hal_delay_us(20); - data_port_write(cmd); -} - -static void data_write(uint16_t value) { - mp_hal_pin_high(mp_rs_pin); - - uint8_t high_byte = (uint8_t)(value >> 8); - uint8_t low_byte = (uint8_t)(value & 0xFF); - mp_hal_delay_us(20); - data_port_write(high_byte); - mp_hal_delay_us(20); - data_port_write(low_byte); -} - -#define LCD_WRITE(a, b) { \ - cmd_write(a); \ - data_write(b); } - -void driver_ssd1289_init(pin_obj_t * p_cs_pin, - pin_obj_t * p_rs_pin, - pin_obj_t * p_wr_pin, - pin_obj_t * p_reset_pin, - pin_obj_t * p_d0_pin, - pin_obj_t * p_d1_pin, - pin_obj_t * p_d2_pin, - pin_obj_t * p_d3_pin, - pin_obj_t * p_d4_pin, - pin_obj_t * p_d5_pin, - pin_obj_t * p_d6_pin, - pin_obj_t * p_d7_pin) { - - mp_cs_pin = p_cs_pin; - mp_rs_pin = p_rs_pin; - mp_wr_pin = p_wr_pin; - mp_reset_pin = p_reset_pin; - mp_d0_pin = p_d0_pin; - mp_d1_pin = p_d1_pin; - mp_d2_pin = p_d2_pin; - mp_d3_pin = p_d3_pin; - mp_d4_pin = p_d4_pin; - mp_d5_pin = p_d5_pin; - mp_d6_pin = p_d6_pin; - mp_d7_pin = p_d7_pin; - - mp_hal_pin_low(mp_d0_pin); - mp_hal_pin_low(mp_d1_pin); - mp_hal_pin_low(mp_d2_pin); - mp_hal_pin_low(mp_d3_pin); - mp_hal_pin_low(mp_d4_pin); - mp_hal_pin_low(mp_d5_pin); - mp_hal_pin_low(mp_d6_pin); - mp_hal_pin_low(mp_d7_pin); - - mp_hal_pin_low(mp_rs_pin); - mp_hal_pin_low(mp_wr_pin); - - mp_hal_pin_low(mp_cs_pin); - - mp_hal_pin_high(mp_reset_pin); - mp_hal_delay_ms(20); - mp_hal_pin_high(mp_reset_pin); - - LCD_WRITE(0x00,0x0001); - LCD_WRITE(0x03,0xA8A4); - LCD_WRITE(0x0C,0x0000); - LCD_WRITE(0x0D,0x080C); - LCD_WRITE(0x0E,0x2B00); - LCD_WRITE(0x1E,0x00B7); - LCD_WRITE(0x01,0x2B3F); - LCD_WRITE(0x02,0x0600); - LCD_WRITE(0x10,0x0000); - LCD_WRITE(0x11,0x6070); - LCD_WRITE(0x05,0x0000); - LCD_WRITE(0x06,0x0000); - LCD_WRITE(0x16,0xEF1C); - LCD_WRITE(0x17,0x0003); - LCD_WRITE(0x07,0x0233); - LCD_WRITE(0x0B,0x0000); - LCD_WRITE(0x0F,0x0000); - LCD_WRITE(0x41,0x0000); - LCD_WRITE(0x42,0x0000); - LCD_WRITE(0x48,0x0000); - LCD_WRITE(0x49,0x013F); - LCD_WRITE(0x4A,0x0000); - LCD_WRITE(0x4B,0x0000); - LCD_WRITE(0x44,0xEF00); - LCD_WRITE(0x45,0x0000); - LCD_WRITE(0x46,0x013F); - LCD_WRITE(0x30,0x0707); - LCD_WRITE(0x31,0x0204); - LCD_WRITE(0x32,0x0204); - LCD_WRITE(0x33,0x0502); - LCD_WRITE(0x34,0x0507); - LCD_WRITE(0x35,0x0204); - LCD_WRITE(0x36,0x0204); - LCD_WRITE(0x37,0x0502); - LCD_WRITE(0x3A,0x0302); - LCD_WRITE(0x3B,0x0302); - LCD_WRITE(0x23,0x0000); - LCD_WRITE(0x24,0x0000); - LCD_WRITE(0x25,0x8000); - LCD_WRITE(0x4f,0x0000); - LCD_WRITE(0x4e,0x0000); - cmd_write(0x22); - - mp_hal_pin_high(mp_cs_pin); -} - -static void set_xy(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) { - LCD_WRITE(0x44, (y1 << 8) + y0); - LCD_WRITE(0x45, 319 - x1); - LCD_WRITE(0x46, 319 - x0); - LCD_WRITE(0x4e, y0); - LCD_WRITE(0x4f, 319 - x1); - cmd_write(0x22); -} - -void driver_ssd1289_clear(uint16_t color) { - uint16_t x; - uint16_t y; - uint16_t lcd_x_size = 240; - uint16_t lcd_y_size = 320; - - mp_hal_pin_low(mp_cs_pin); - - set_xy(0, 0, lcd_y_size - 1, lcd_x_size - 1); - - for (x = 0; x < lcd_x_size; x++) { - for (y = 0; y < lcd_y_size; y++) { - data_write(color); - } - } - - mp_hal_pin_high(mp_cs_pin); -} - -void driver_ssd1289_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { - set_xy(0, line, 319, line); - - mp_hal_pin_low(mp_cs_pin); - - for (uint8_t i = 0; i < len; i++) { - uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; - for (uint8_t pixel_pos = 0; pixel_pos < 8; pixel_pos++) { - if (((byte >> pixel_pos) & 0x1) == 0x0) { - data_write(0x0000); - } else { - data_write(0xFFFF); - } - } - } - - mp_hal_pin_high(mp_cs_pin); -} - -#endif // MICROPY_PY_DISPLAY_LCD_SSD1289 diff --git a/nrf5/modules/display/lcd_ssd1289_driver.h b/nrf5/modules/display/lcd_ssd1289_driver.h deleted file mode 100644 index 58b36618d8..0000000000 --- a/nrf5/modules/display/lcd_ssd1289_driver.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef LCD_SSD1289_DRIVER_H__ -#define LCD_SSD1289_DRIVER_H__ - -#include "py/mphal.h" - -#include "framebuffer.h" - -void driver_ssd1289_init(pin_obj_t * p_cs_pin, - pin_obj_t * p_rs_pin, - pin_obj_t * p_wr_pin, - pin_obj_t * p_reset_pin, - pin_obj_t * p_d0_pin, - pin_obj_t * p_d1_pin, - pin_obj_t * p_d2_pin, - pin_obj_t * p_d3_pin, - pin_obj_t * p_d4_pin, - pin_obj_t * p_d5_pin, - pin_obj_t * p_d6_pin, - pin_obj_t * p_d7_pin); - - -void driver_ssd1289_clear(uint16_t color); - -void driver_ssd1289_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); - -#endif // LCD_SSD1289_DRIVER_H__ diff --git a/nrf5/modules/display/lcd_ssd1289_obj.c b/nrf5/modules/display/lcd_ssd1289_obj.c deleted file mode 100644 index 24382ab6f3..0000000000 --- a/nrf5/modules/display/lcd_ssd1289_obj.c +++ /dev/null @@ -1,516 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" -#include "py/runtime.h" -#include "py/mphal.h" -#include "genhdr/pins.h" - -#include "lcd_ssd1289_driver.h" - -#if MICROPY_PY_DISPLAY_LCD_SSD1289 - -/// \moduleref display -/// \class SSD1289 - SSD1289 TFT LCD display driver. - -#include "moddisplay.h" -#include "framebuffer.h" -#include "pin.h" - -typedef struct _lcd_ssd1289_obj_t { - mp_obj_base_t base; - display_draw_callbacks_t draw_callbacks; - framebuffer_t * framebuffer; - pin_obj_t * pin_cs; - pin_obj_t * pin_rs; - pin_obj_t * pin_wr; - pin_obj_t * pin_reset; - pin_obj_t * pin_d0; - pin_obj_t * pin_d1; - pin_obj_t * pin_d2; - pin_obj_t * pin_d3; - pin_obj_t * pin_d4; - pin_obj_t * pin_d5; - pin_obj_t * pin_d6; - pin_obj_t * pin_d7; -} lcd_ssd1289_obj_t; - -#define LCD_SSD1289_COLOR_BLACK 0 -#define LCD_SSD1289_COLOR_WHITE 1 - -static void set_pixel(void * p_display, - uint16_t x, - uint16_t y, - uint16_t color) { - lcd_ssd1289_obj_t *self = (lcd_ssd1289_obj_t *)p_display; - - if (color == LCD_SSD1289_COLOR_BLACK) { - framebuffer_pixel_clear(self->framebuffer, x, y); - } else { - framebuffer_pixel_set(self->framebuffer, x, y); - } -} - -/// \method __str__() -/// Return a string describing the SSD1289 object. -STATIC void lcd_ssd1289_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - lcd_ssd1289_obj_t *self = o; - - mp_printf(print, "SSD1289(cs=(port=%u, pin=%u), rs=(port=%u, pin=%u),\n", - self->pin_cs->port, - self->pin_cs->pin, - self->pin_rs->port, - self->pin_rs->pin); - - mp_printf(print, " wr=(port=%u, pin=%u), reset=(port=%u, pin=%u),\n", - self->pin_wr->port, - self->pin_wr->pin, - self->pin_reset->port, - self->pin_reset->pin); - - mp_printf(print, " d0=(port=%u, pin=%u), d1=(port=%u, pin=%u),\n", - self->pin_d0->port, - self->pin_d0->pin, - self->pin_d1->port, - self->pin_d1->pin); - - mp_printf(print, " d2=(port=%u, pin=%u), d3=(port=%u, pin=%u),\n", - self->pin_d2->port, - self->pin_d2->pin, - self->pin_d3->port, - self->pin_d3->pin); - - mp_printf(print, " d4=(port=%u, pin=%u), d5=(port=%u, pin=%u),\n", - self->pin_d4->port, - self->pin_d4->pin, - self->pin_d5->port, - self->pin_d5->pin); - - mp_printf(print, " d6=(port=%u, pin=%u), d7=(port=%u, pin=%u),\n", - self->pin_d6->port, - self->pin_d6->pin, - self->pin_d7->port, - self->pin_d7->pin); - - - mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", - self->framebuffer->screen_width, - self->framebuffer->screen_height, - self->framebuffer->line_orientation, - self->framebuffer->fb_stride, - self->framebuffer->fb_dirty_stride); -} - -// for make_new -enum { - ARG_NEW_WIDTH, - ARG_NEW_HEIGHT, - ARG_NEW_CS, - ARG_NEW_RS, - ARG_NEW_WR, - ARG_NEW_RESET, - ARG_NEW_D0, - ARG_NEW_D1, - ARG_NEW_D2, - ARG_NEW_D3, - ARG_NEW_D4, - ARG_NEW_D5, - ARG_NEW_D6, - ARG_NEW_D7, - -}; - -/* - -Example for nrf51822 / pca10028: - -from machine import Pin -from display import SSD1289 -import draw -cs = Pin("A1", mode=Pin.OUT, pull=Pin.PULL_UP) -rs = Pin("A2", mode=Pin.OUT, pull=Pin.PULL_UP) -wr = Pin("A3", mode=Pin.OUT, pull=Pin.PULL_UP) -reset = Pin("A4", mode=Pin.OUT, pull=Pin.PULL_UP) - -d0 = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) -d1 = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) -d2 = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) -d3 = Pin("A15", mode=Pin.OUT, pull=Pin.PULL_UP) -d4 = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) -d5 = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) -d6 = Pin("A18", mode=Pin.OUT, pull=Pin.PULL_UP) -d7 = Pin("A19", mode=Pin.OUT, pull=Pin.PULL_UP) - -d = SSD1289(320, 240, cs, rs, wr, reset, d0, d1, d2, d3, d4, d5, d6, d7) -draw.text(d, "Hello World!", 32, 32) -d.show() - -Example for nrf52832 / pca10040: - -from machine import Pin -from display import SSD1289 -import draw -cs = Pin("A3", mode=Pin.OUT, pull=Pin.PULL_UP) -rs = Pin("A4", mode=Pin.OUT, pull=Pin.PULL_UP) -wr = Pin("A28", mode=Pin.OUT, pull=Pin.PULL_UP) -reset = Pin("A29", mode=Pin.OUT, pull=Pin.PULL_UP) - -d0 = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) -d1 = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) -d2 = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) -d3 = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) -d4 = Pin("A15", mode=Pin.OUT, pull=Pin.PULL_UP) -d5 = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) -d6 = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) -d7 = Pin("A18", mode=Pin.OUT, pull=Pin.PULL_UP) - -d = SSD1289(240, 320, cs, rs, wr, reset, d0, d1, d2, d3, d4, d5, d6, d7) -draw.text(d, "Hello World!", 32, 32) -d.show() - -Example for nrf52840 / pca10056: - -from machine import Pin -from display import SSD1289 -import draw -cs = Pin("A3", mode=Pin.OUT, pull=Pin.PULL_UP) -rs = Pin("A4", mode=Pin.OUT, pull=Pin.PULL_UP) -wr = Pin("A28", mode=Pin.OUT, pull=Pin.PULL_UP) -reset = Pin("A29", mode=Pin.OUT, pull=Pin.PULL_UP) - -d0 = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) -d1 = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) -d2 = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) -d3 = Pin("B4", mode=Pin.OUT, pull=Pin.PULL_UP) -d4 = Pin("B5", mode=Pin.OUT, pull=Pin.PULL_UP) -d5 = Pin("B6", mode=Pin.OUT, pull=Pin.PULL_UP) -d6 = Pin("B7", mode=Pin.OUT, pull=Pin.PULL_UP) -d7 = Pin("B8", mode=Pin.OUT, pull=Pin.PULL_UP) - -d = SSD1289(320, 240, cs, rs, wr, reset, d0, d1, d2, d3, d4, d5, d6, d7) -draw.text(d, "Hello World!", 32, 32) -d.show() - -*/ -STATIC mp_obj_t lcd_ssd1289_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - static const mp_arg_t allowed_args[] = { - { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_RS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_WR, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_D0, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_D1, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_D2, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_D3, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_D4, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_D5, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_D6, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_D7, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - }; - - // parse args - mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; - mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - - lcd_ssd1289_obj_t *s = m_new_obj_with_finaliser(lcd_ssd1289_obj_t); - s->base.type = type; - s->draw_callbacks.pixel_set = set_pixel; - - mp_int_t width; - mp_int_t height; - - if (args[ARG_NEW_WIDTH].u_int > 0) { - width = args[ARG_NEW_WIDTH].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display width not set")); - } - - if (args[ARG_NEW_HEIGHT].u_int > 0) { - height = args[ARG_NEW_HEIGHT].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display height not set")); - } - - if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { - s->pin_cs = args[ARG_NEW_CS].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display CS Pin not set")); - } - - if (args[ARG_NEW_RS].u_obj != MP_OBJ_NULL) { - s->pin_rs = args[ARG_NEW_RS].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display RS Pin not set")); - } - - if (args[ARG_NEW_WR].u_obj != MP_OBJ_NULL) { - s->pin_wr = args[ARG_NEW_WR].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display WR Pin not set")); - } - - if (args[ARG_NEW_RESET].u_obj != MP_OBJ_NULL) { - s->pin_reset = args[ARG_NEW_RESET].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Reset Pin not set")); - } - - if (args[ARG_NEW_D0].u_obj != MP_OBJ_NULL) { - s->pin_d0 = args[ARG_NEW_D0].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Data 0 Pin not set")); - } - - if (args[ARG_NEW_D1].u_obj != MP_OBJ_NULL) { - s->pin_d1 = args[ARG_NEW_D1].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Data 1 Pin not set")); - } - - if (args[ARG_NEW_D2].u_obj != MP_OBJ_NULL) { - s->pin_d2 = args[ARG_NEW_D2].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Data 2 Pin not set")); - } - - if (args[ARG_NEW_D3].u_obj != MP_OBJ_NULL) { - s->pin_d3 = args[ARG_NEW_D3].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Data 3 Pin not set")); - } - - if (args[ARG_NEW_D4].u_obj != MP_OBJ_NULL) { - s->pin_d4 = args[ARG_NEW_D4].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Data 4 Pin not set")); - } - - if (args[ARG_NEW_D5].u_obj != MP_OBJ_NULL) { - s->pin_d5 = args[ARG_NEW_D5].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Data 5 Pin not set")); - } - - if (args[ARG_NEW_D6].u_obj != MP_OBJ_NULL) { - s->pin_d6 = args[ARG_NEW_D6].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Data 6 Pin not set")); - } - - if (args[ARG_NEW_D7].u_obj != MP_OBJ_NULL) { - s->pin_d7 = args[ARG_NEW_D7].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Data 7 Pin not set")); - } - - framebuffer_init_t init_conf = { - .width = width, - .height = height, - .line_orientation = FRAMEBUFFER_LINE_DIR_HORIZONTAL, - .double_buffer = false - }; - - s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); - - framebuffer_init(s->framebuffer, &init_conf); - - driver_ssd1289_init(s->pin_cs, - s->pin_rs, - s->pin_wr, - s->pin_reset, - s->pin_d0, - s->pin_d1, - s->pin_d2, - s->pin_d3, - s->pin_d4, - s->pin_d5, - s->pin_d6, - s->pin_d7); - - // Default to black background - driver_ssd1289_clear(0x00FF); - - framebuffer_clear(s->framebuffer); - - return MP_OBJ_FROM_PTR(s); -} - -// text - -/// \method fill(color) -/// Fill framebuffer with the color defined as argument. -STATIC mp_obj_t lcd_ssd1289_fill(mp_obj_t self_in, mp_obj_t color) { - lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(self_in); - - if (color == MP_OBJ_NEW_SMALL_INT(LCD_SSD1289_COLOR_BLACK)) { - framebuffer_clear(self->framebuffer); - } else { - framebuffer_fill(self->framebuffer); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(lcd_ssd1289_fill_obj, lcd_ssd1289_fill); - -static void render(framebuffer_t * p_framebuffer) { - for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { - if (p_framebuffer->fb_dirty[i].byte != 0) { - for (uint16_t b = 0; b < 8; b++) { - if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { - uint16_t line_num = (i * 8) + b; - driver_ssd1289_update_line(line_num, - &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], - p_framebuffer->fb_stride); - } - } - - p_framebuffer->fb_dirty[i].byte = 0x00; - } - } -} - -/// \method show() -/// Display content in framebuffer. -STATIC mp_obj_t lcd_ssd1289_show(size_t n_args, const mp_obj_t *args) { - lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(args[0]); - - render(self->framebuffer); - framebuffer_flip(self->framebuffer); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ssd1289_show_obj, 1, 2, lcd_ssd1289_show); - -/// \method refresh([num_of_refresh]) -/// Refresh content in framebuffer. -/// -/// - With no argument, 1 refresh will be done. -/// - With `num_of_refresh` given, The whole framebuffer will be considered -/// dirty and will be refreshed the given number of times. -STATIC mp_obj_t lcd_ssd1289_refresh(mp_obj_t self_in) { - lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ssd1289_refresh_obj, lcd_ssd1289_refresh); - -/// \method pixel(x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color of the pixel in framebuffer will be returend. -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t lcd_ssd1289_pixel(size_t n_args, const mp_obj_t *args) { - lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(args[0]); - mp_int_t x = mp_obj_get_int(args[1]); - mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color = mp_obj_get_int(args[3]); - - set_pixel(self, x, y, color); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ssd1289_pixel_obj, 4, 4, lcd_ssd1289_pixel); - -/// \method pixel(text, x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color will be the opposite of background (fill color). -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t lcd_ssd1289_text(size_t n_args, const mp_obj_t *args) { - lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(args[0]); - const char *str = mp_obj_str_get_str(args[1]); - mp_int_t x = mp_obj_get_int(args[2]); - mp_int_t y = mp_obj_get_int(args[3]); - mp_int_t color; - if (n_args >= 4) { - color = mp_obj_get_int(args[3]); - } - - //display_print_string(self->framebuffer, x, y, str); - - (void)x; - (void)y; - (void)self; - (void)str; - (void)color; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lcd_ssd1289_text_obj, 4, 5, lcd_ssd1289_text); - -STATIC mp_obj_t lcd_ssd1289_del(mp_obj_t self_in) { - lcd_ssd1289_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(lcd_ssd1289_del_obj, lcd_ssd1289_del); - -STATIC const mp_map_elem_t lcd_ssd1289_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&lcd_ssd1289_del_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&lcd_ssd1289_fill_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&lcd_ssd1289_show_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&lcd_ssd1289_text_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&lcd_ssd1289_pixel_obj) }, -#if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&lcd_ssd1289_bitmap_obj) }, -#endif - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(LCD_SSD1289_COLOR_BLACK) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(LCD_SSD1289_COLOR_WHITE) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, -}; - -STATIC MP_DEFINE_CONST_DICT(lcd_ssd1289_locals_dict, lcd_ssd1289_locals_dict_table); - -const mp_obj_type_t lcd_ssd1289_type = { - { &mp_type_type }, - .name = MP_QSTR_SSD1289, - .print = lcd_ssd1289_print, - .make_new = lcd_ssd1289_make_new, - .locals_dict = (mp_obj_t)&lcd_ssd1289_locals_dict -}; - -#endif // MICROPY_PY_DISPLAY_LCD_SSD1289 diff --git a/nrf5/modules/display/lcd_ssd1289_obj.h b/nrf5/modules/display/lcd_ssd1289_obj.h deleted file mode 100644 index 7105c110cc..0000000000 --- a/nrf5/modules/display/lcd_ssd1289_obj.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef LCD_SSD1289_H__ -#define LCD_SSD1289_H__ - -#include - -extern const mp_obj_type_t lcd_ssd1289_type; - -#endif // LCD_SSD1289_H__ - diff --git a/nrf5/modules/display/moddisplay.c b/nrf5/modules/display/moddisplay.c deleted file mode 100644 index ca4db0b454..0000000000 --- a/nrf5/modules/display/moddisplay.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" - -#if MICROPY_PY_DISPLAY - -#include "epaper_sld00200p_obj.h" -#include "lcd_ili9341_obj.h" -#include "lcd_ls0xxb7dxxx_obj.h" -#include "lcd_ssd1289_obj.h" -#include "oled_ssd1305_obj.h" -#include "oled_ssd1306_obj.h" - -STATIC const mp_map_elem_t mp_module_display_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_display) }, -#if MICROPY_PY_DISPLAY_EPAPER_SLD00200P - { MP_OBJ_NEW_QSTR(MP_QSTR_SLD00200P), (mp_obj_t)&epaper_sld00200p_type }, -#endif -#if MICROPY_PY_DISPLAY_LCD_ILI9341 - { MP_OBJ_NEW_QSTR(MP_QSTR_ILI9341), (mp_obj_t)&lcd_ili9341_type }, -#endif -#if MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX - { MP_OBJ_NEW_QSTR(MP_QSTR_LS0XXB7DXXX), (mp_obj_t)&lcd_ls0xxb7dxxx_type }, -#endif -#if MICROPY_PY_DISPLAY_LCD_SSD1289 - { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1289), (mp_obj_t)&lcd_ssd1289_type }, -#endif -#if MICROPY_PY_DISPLAY_OLED_SSD1305 - { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1305), (mp_obj_t)&oled_ssd1305_type }, -#endif -#if MICROPY_PY_DISPLAY_OLED_SSD1306 - { MP_OBJ_NEW_QSTR(MP_QSTR_SSD1306), (mp_obj_t)&oled_ssd1306_type }, -#endif -}; - - -STATIC MP_DEFINE_CONST_DICT(mp_module_display_globals, mp_module_display_globals_table); - -const mp_obj_module_t mp_module_display = { - .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_display_globals, -}; - -#endif // MICROPY_PY_DISPLAY diff --git a/nrf5/modules/display/moddisplay.h b/nrf5/modules/display/moddisplay.h deleted file mode 100644 index 82ff595027..0000000000 --- a/nrf5/modules/display/moddisplay.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef MODDISPLAY_H__ -#define MODDISPLAY_H__ - -typedef struct _display_t display_t; - -typedef void (*pixel_set_callback_t)(void * p_display, - uint16_t x, - uint16_t y, - uint16_t color); - -typedef struct _display_draw_callbacks_t { - pixel_set_callback_t pixel_set; -} display_draw_callbacks_t; - -typedef struct _display_t { - mp_obj_base_t base; - display_draw_callbacks_t draw_callbacks; -} display_t; - -#endif // MODDISPLAY_H__ diff --git a/nrf5/modules/display/oled_ssd1305_driver.c b/nrf5/modules/display/oled_ssd1305_driver.c deleted file mode 100644 index 95fc8f26c5..0000000000 --- a/nrf5/modules/display/oled_ssd1305_driver.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "py/mphal.h" - -#include "oled_ssd1305_driver.h" -#include "hal_spi.h" -#include "hal_time.h" - -#include "framebuffer.h" - -#if MICROPY_PY_DISPLAY_OLED_SSD1305 - -static pin_obj_t * mp_cs_pin; -static pin_obj_t * mp_dc_pin; -static pin_obj_t * mp_reset_pin; -static NRF_SPI_Type * mp_instance; - - -static void raw_write(uint8_t value) -{ - hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); - -} - -static void cmd_write(uint8_t value) -{ - mp_hal_pin_low(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); - - mp_hal_pin_high(mp_cs_pin); -} - -#define SET_CONTRAST (0x81) -#define SET_ENTIRE_ON (0xa4) -#define SET_NORM_INV (0xa6) -#define SET_DISP (0xae) -#define SET_MEM_ADDR (0x20) -#define SET_COL_ADDR (0x21) -#define SET_PAGE_ADDR (0x22) -#define SET_DISP_START_LINE (0x40) -#define SET_SEG_REMAP (0xa0) -#define SET_MUX_RATIO (0xa8) -#define SET_COM_OUT_DIR (0xc0) -#define SET_DISP_OFFSET (0xd3) -#define SET_COM_PIN_CFG (0xda) -#define SET_DISP_CLK_DIV (0xd5) -#define SET_PRECHARGE (0xd9) -#define SET_VCOM_DESEL (0xdb) -#define SET_CHARGE_PUMP (0x8d) - -void driver_ssd1305_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_obj_t * p_dc_pin, pin_obj_t * p_reset_pin) -{ - mp_instance = p_instance; - mp_cs_pin = p_cs_pin; - mp_dc_pin = p_dc_pin; - mp_reset_pin = p_reset_pin; - - mp_hal_pin_high(mp_cs_pin); - mp_hal_pin_high(mp_dc_pin); - mp_hal_pin_high(mp_reset_pin); - - // power on display - mp_hal_pin_high(mp_reset_pin); - mp_hal_delay_ms(1); - mp_hal_pin_low(mp_reset_pin); - mp_hal_delay_ms(10); - mp_hal_pin_high(mp_reset_pin); - - // Turn off - cmd_write(SET_DISP | 0x00); // off - - // address setting - cmd_write(SET_MEM_ADDR); - cmd_write(0x00); // horizontal - - // resolution and layout - cmd_write(SET_DISP_START_LINE | 0x00); - cmd_write(SET_SEG_REMAP | 0x00); // column addr 127 mapped to SEG0 - cmd_write(SET_MUX_RATIO); - - uint16_t height = 64; // TODO: configurable - cmd_write(height - 1); // height - 1 - cmd_write(SET_COM_OUT_DIR | 0x08); // scan from COM[N] to COM0 - cmd_write(SET_DISP_OFFSET); - cmd_write(0x00); - cmd_write(SET_COM_PIN_CFG); - if (height == 32) { - cmd_write(0x02); - } else { - cmd_write(0x12); - } - // timing and driving scheme - cmd_write(SET_DISP_CLK_DIV); - cmd_write(0x80); - cmd_write(SET_PRECHARGE); - bool external_vcc = false; - if (external_vcc == true) { - cmd_write(0x22); - } else { - cmd_write(0xf1); - } - cmd_write(SET_VCOM_DESEL); - cmd_write(0x30); // 0.83*Vcc - // display - cmd_write(SET_CONTRAST); - cmd_write(0xff); // maximum - cmd_write(SET_ENTIRE_ON); // output follows RAM contents - cmd_write(SET_NORM_INV); // not inverted - // charge pump - cmd_write(SET_CHARGE_PUMP); - if (external_vcc == true) { - cmd_write(0x10); - } else { - cmd_write(0x14); - } - // on - cmd_write(SET_DISP | 0x01); -} - -static void set_col(uint16_t start_col, uint16_t end_col) -{ - cmd_write(SET_COL_ADDR); // column command address - cmd_write(start_col & 0xFF ); - cmd_write(end_col & 0xFF); -} - -static void set_page(uint16_t start_page, uint16_t end_page) -{ - cmd_write(SET_PAGE_ADDR); // page command address - cmd_write(start_page & 0xFF); - cmd_write(end_page & 0xFF); -} - -void driver_ssd1305_clear(uint16_t color) -{ - uint16_t width = 128; - uint16_t height = 64; - - uint16_t x0 = 0; - uint16_t x1 = width - 1; - uint16_t y0 = 0; - uint16_t y1 = height -1; - - if (width == 64) { - // displays with width of 64 pixels are shifted by 32 - x0 += 32; - x1 += 32; - } - - uint16_t num_of_pages = height / 8; - set_col(x0, x1); - set_page(y0, y1); - - mp_hal_pin_high(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - for (uint16_t i = 0; i < (width * num_of_pages); i++) { - raw_write(color); - } - - mp_hal_pin_high(mp_cs_pin); -} - -void driver_ssd1305_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { - set_col(line, line); - set_page(0, 63); - - mp_hal_pin_high(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - for (uint8_t i = 0; i < len; i++) { - uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; - raw_write(byte); - } - - mp_hal_pin_high(mp_cs_pin); -} - -#endif diff --git a/nrf5/modules/display/oled_ssd1305_driver.h b/nrf5/modules/display/oled_ssd1305_driver.h deleted file mode 100644 index 5a030b7a87..0000000000 --- a/nrf5/modules/display/oled_ssd1305_driver.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef OLED_SSD1305_DRIVER_H__ -#define OLED_SSD1305_DRIVER_H__ - -#include "py/mphal.h" - -#include "hal_spi.h" -#include "framebuffer.h" - -void driver_ssd1305_init(NRF_SPI_Type * p_instance, pin_obj_t * cs_pin, pin_obj_t * dc_pin, pin_obj_t * reset_pin); - -void driver_ssd1305_clear(uint16_t color); - -void driver_ssd1305_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); - -#endif // OLED_SSD1305_DRIVER_H__ diff --git a/nrf5/modules/display/oled_ssd1305_obj.c b/nrf5/modules/display/oled_ssd1305_obj.c deleted file mode 100644 index 6b83a53550..0000000000 --- a/nrf5/modules/display/oled_ssd1305_obj.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" -#include "py/runtime.h" -#include "py/mphal.h" -#include "genhdr/pins.h" - -#include "oled_ssd1305_driver.h" - -#if MICROPY_PY_DISPLAY_OLED_SSD1305 - -/// \moduleref display -/// \class SSD1305 - SSD1305 TFT LCD display driver. - -#include "moddisplay.h" -#include "framebuffer.h" -#include "pin.h" -#include "spi.h" - -typedef struct _oled_ssd1305_obj_t { - mp_obj_base_t base; - display_draw_callbacks_t draw_callbacks; - framebuffer_t * framebuffer; - machine_hard_spi_obj_t *spi; - pin_obj_t * pin_cs; - pin_obj_t * pin_dc; - pin_obj_t * pin_reset; -} oled_ssd1305_obj_t; - -#define OLED_SSD1305_COLOR_BLACK 0 -#define OLED_SSD1305_COLOR_WHITE 1 - -static void set_pixel(void * p_display, - uint16_t x, - uint16_t y, - uint16_t color) { - oled_ssd1305_obj_t *self = (oled_ssd1305_obj_t *)p_display; - - if (color == OLED_SSD1305_COLOR_BLACK) { - framebuffer_pixel_clear(self->framebuffer, x, y); - } else { - framebuffer_pixel_set(self->framebuffer, x, y); - } -} - -/// \method __str__() -/// Return a string describing the SSD1305 object. -STATIC void oled_ssd1305_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - oled_ssd1305_obj_t *self = o; - - mp_printf(print, "SSD1305(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin->port, - self->spi->pyb->spi->init.mosi_pin->pin, - self->spi->pyb->spi->init.miso_pin->port, - self->spi->pyb->spi->init.miso_pin->pin, - self->spi->pyb->spi->init.clk_pin->port, - self->spi->pyb->spi->init.clk_pin->pin); - - mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u), reset=(port=%u, pin=%u),\n", - self->pin_cs->port, - self->pin_cs->pin, - self->pin_dc->port, - self->pin_dc->pin, - self->pin_reset->port, - self->pin_reset->pin); - - mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", - self->framebuffer->screen_width, - self->framebuffer->screen_height, - self->framebuffer->line_orientation, - self->framebuffer->fb_stride, - self->framebuffer->fb_dirty_stride); -} - -// for make_new -enum { - ARG_NEW_WIDTH, - ARG_NEW_HEIGHT, - ARG_NEW_SPI, - ARG_NEW_CS, - ARG_NEW_DC, - ARG_NEW_RESET -}; - -/* - -Example for nrf51822 / pca10028: - -from machine import Pin, SPI -from display import SSD1305 -cs = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) -reset = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) -dc = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -d = SSD1305(128, 64, spi, cs, dc, reset) -draw.text(d, "Hello World!", 32, 32) -d.show() - -Example for nrf52832 / pca10040: - -from machine import Pin, SPI -from display import SSD1305 -import draw -cs = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) -reset = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) -dc = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -d = SSD1305(128, 64, spi, cs, dc, reset) -draw.text(d, "Hello World!", 32, 32) -d.show() - -Example for nrf52840 / pca10056: - -from machine import Pin, SPI -from display import SSD1305 -import draw -cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) -reset = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) -dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -d = SSD1305(128, 64, spi, cs, dc, reset) -draw.text(d, "Hello World!", 32, 32) -d.show() - -*/ -STATIC mp_obj_t oled_ssd1305_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - static const mp_arg_t allowed_args[] = { - { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_DC, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - }; - - // parse args - mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; - mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - - oled_ssd1305_obj_t *s = m_new_obj_with_finaliser(oled_ssd1305_obj_t); - s->base.type = type; - s->draw_callbacks.pixel_set = set_pixel; - - mp_int_t width; - mp_int_t height; - - if (args[ARG_NEW_WIDTH].u_int > 0) { - width = args[ARG_NEW_WIDTH].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display width not set")); - } - - if (args[ARG_NEW_HEIGHT].u_int > 0) { - height = args[ARG_NEW_HEIGHT].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display height not set")); - } - - if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { - s->spi = args[ARG_NEW_SPI].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display SPI not set")); - } - - if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { - s->pin_cs = args[ARG_NEW_CS].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display CS Pin not set")); - } - - if (args[ARG_NEW_DC].u_obj != MP_OBJ_NULL) { - s->pin_dc = args[ARG_NEW_DC].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display DC Pin not set")); - } - - if (args[ARG_NEW_RESET].u_obj != MP_OBJ_NULL) { - s->pin_reset = args[ARG_NEW_RESET].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Reset Pin not set")); - } - - framebuffer_init_t init_conf = { - .width = width, - .height = height, - .line_orientation = FRAMEBUFFER_LINE_DIR_VERTICAL, - .double_buffer = false - }; - - s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); - - framebuffer_init(s->framebuffer, &init_conf); - - driver_ssd1305_init(s->spi->pyb->spi->instance, s->pin_cs, s->pin_dc, s->pin_reset); - // Default to black background - driver_ssd1305_clear(0); - - framebuffer_clear(s->framebuffer); - - return MP_OBJ_FROM_PTR(s); -} - -// text - -/// \method fill(color) -/// Fill framebuffer with the color defined as argument. -STATIC mp_obj_t oled_ssd1305_fill(mp_obj_t self_in, mp_obj_t color) { - oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(self_in); - - if (color == MP_OBJ_NEW_SMALL_INT(OLED_SSD1305_COLOR_BLACK)) { - framebuffer_clear(self->framebuffer); - } else { - framebuffer_fill(self->framebuffer); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(oled_ssd1305_fill_obj, oled_ssd1305_fill); - -static void render(framebuffer_t * p_framebuffer) { - for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { - if (p_framebuffer->fb_dirty[i].byte != 0) { - for (uint16_t b = 0; b < 8; b++) { - if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { - uint16_t line_num = (i * 8) + b; - driver_ssd1305_update_line(line_num, - &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], - p_framebuffer->fb_stride); - } - } - - p_framebuffer->fb_dirty[i].byte = 0x00; - } - } -} - -/// \method show() -/// Display content in framebuffer. -STATIC mp_obj_t oled_ssd1305_show(size_t n_args, const mp_obj_t *args) { - oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(args[0]); - - render(self->framebuffer); - framebuffer_flip(self->framebuffer); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1305_show_obj, 1, 2, oled_ssd1305_show); - -/// \method refresh([num_of_refresh]) -/// Refresh content in framebuffer. -/// -/// - With no argument, 1 refresh will be done. -/// - With `num_of_refresh` given, The whole framebuffer will be considered -/// dirty and will be refreshed the given number of times. -STATIC mp_obj_t oled_ssd1305_refresh(mp_obj_t self_in) { - oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(oled_ssd1305_refresh_obj, oled_ssd1305_refresh); - -/// \method pixel(x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color of the pixel in framebuffer will be returend. -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t oled_ssd1305_pixel(size_t n_args, const mp_obj_t *args) { - oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(args[0]); - mp_int_t x = mp_obj_get_int(args[1]); - mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color = mp_obj_get_int(args[3]); - - set_pixel(self, x, y, color); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1305_pixel_obj, 4, 4, oled_ssd1305_pixel); - -/// \method pixel(text, x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color will be the opposite of background (fill color). -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t oled_ssd1305_text(size_t n_args, const mp_obj_t *args) { - oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(args[0]); - const char *str = mp_obj_str_get_str(args[1]); - mp_int_t x = mp_obj_get_int(args[2]); - mp_int_t y = mp_obj_get_int(args[3]); - mp_int_t color; - if (n_args >= 4) { - color = mp_obj_get_int(args[3]); - } - - //display_print_string(self->framebuffer, x, y, str); - - (void)x; - (void)y; - (void)self; - (void)str; - (void)color; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1305_text_obj, 4, 5, oled_ssd1305_text); - -STATIC mp_obj_t oled_ssd1305_del(mp_obj_t self_in) { - oled_ssd1305_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(oled_ssd1305_del_obj, oled_ssd1305_del); - -STATIC const mp_map_elem_t oled_ssd1305_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&oled_ssd1305_del_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&oled_ssd1305_fill_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&oled_ssd1305_show_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&oled_ssd1305_text_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&oled_ssd1305_pixel_obj) }, -#if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&oled_ssd1305_bitmap_obj) }, -#endif - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(OLED_SSD1305_COLOR_BLACK) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(OLED_SSD1305_COLOR_WHITE) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, -}; - -STATIC MP_DEFINE_CONST_DICT(oled_ssd1305_locals_dict, oled_ssd1305_locals_dict_table); - -const mp_obj_type_t oled_ssd1305_type = { - { &mp_type_type }, - .name = MP_QSTR_SSD1305, - .print = oled_ssd1305_print, - .make_new = oled_ssd1305_make_new, - .locals_dict = (mp_obj_t)&oled_ssd1305_locals_dict -}; - -#endif // MICROPY_PY_DISPLAY_OLED_SSD1305 diff --git a/nrf5/modules/display/oled_ssd1305_obj.h b/nrf5/modules/display/oled_ssd1305_obj.h deleted file mode 100644 index 23a9f935db..0000000000 --- a/nrf5/modules/display/oled_ssd1305_obj.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef OLED_SSD1305_H__ -#define OLED_SSD1305_H__ - -#include - -extern const mp_obj_type_t oled_ssd1305_type; - -#endif // OLED_SSD1305_H__ - diff --git a/nrf5/modules/display/oled_ssd1306_driver.c b/nrf5/modules/display/oled_ssd1306_driver.c deleted file mode 100644 index 7083a66927..0000000000 --- a/nrf5/modules/display/oled_ssd1306_driver.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "py/mphal.h" - -#include "oled_ssd1306_driver.h" -#include "hal_spi.h" -#include "hal_time.h" - -#include "framebuffer.h" - -#if MICROPY_PY_DISPLAY_OLED_SSD1306 - -static pin_obj_t * mp_cs_pin; -static pin_obj_t * mp_dc_pin; -static pin_obj_t * mp_reset_pin; -static NRF_SPI_Type * mp_instance; - - -static void raw_write(uint8_t value) -{ - hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); - -} - -static void cmd_write(uint8_t value) -{ - mp_hal_pin_low(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - hal_spi_master_tx_rx(mp_instance, 1, &value, NULL); - - mp_hal_pin_high(mp_cs_pin); -} - -#define SET_CONTRAST (0x81) -#define SET_ENTIRE_ON (0xa4) -#define SET_NORM_INV (0xa6) -#define SET_DISP (0xae) -#define SET_MEM_ADDR (0x20) -#define SET_COL_ADDR (0x21) -#define SET_PAGE_ADDR (0x22) -#define SET_DISP_START_LINE (0x40) -#define SET_SEG_REMAP (0xa0) -#define SET_MUX_RATIO (0xa8) -#define SET_COM_OUT_DIR (0xc0) -#define SET_DISP_OFFSET (0xd3) -#define SET_COM_PIN_CFG (0xda) -#define SET_DISP_CLK_DIV (0xd5) -#define SET_PRECHARGE (0xd9) -#define SET_VCOM_DESEL (0xdb) -#define SET_CHARGE_PUMP (0x8d) - -void driver_ssd1306_init(NRF_SPI_Type * p_instance, pin_obj_t * p_cs_pin, pin_obj_t * p_dc_pin, pin_obj_t * p_reset_pin) -{ - mp_instance = p_instance; - mp_cs_pin = p_cs_pin; - mp_dc_pin = p_dc_pin; - mp_reset_pin = p_reset_pin; - - mp_hal_pin_high(mp_cs_pin); - mp_hal_pin_high(mp_dc_pin); - mp_hal_pin_high(mp_reset_pin); - - // power on display - mp_hal_pin_high(mp_reset_pin); - mp_hal_delay_ms(1); - mp_hal_pin_low(mp_reset_pin); - mp_hal_delay_ms(10); - mp_hal_pin_high(mp_reset_pin); - - // Turn off - cmd_write(SET_DISP | 0x00); // off - - // address setting - cmd_write(SET_MEM_ADDR); - cmd_write(0x00); // horizontal - - // resolution and layout - cmd_write(SET_DISP_START_LINE | 0x00); - cmd_write(SET_SEG_REMAP | 0x01); // column addr 127 mapped to SEG0 - cmd_write(SET_MUX_RATIO); - - uint16_t height = 64; // TODO: configurable - cmd_write(height - 1); // height - 1 - cmd_write(SET_COM_OUT_DIR | 0x08); // scan from COM[N] to COM0 - cmd_write(SET_DISP_OFFSET); - cmd_write(0x00); - cmd_write(SET_COM_PIN_CFG); - if (height == 32) { - cmd_write(0x02); - } else { - cmd_write(0x12); - } - // timing and driving scheme - cmd_write(SET_DISP_CLK_DIV); - cmd_write(0x80); - cmd_write(SET_PRECHARGE); - bool external_vcc = false; - if (external_vcc == true) { - cmd_write(0x22); - } else { - cmd_write(0xf1); - } - cmd_write(SET_VCOM_DESEL); - cmd_write(0x30); // 0.83*Vcc - // display - cmd_write(SET_CONTRAST); - cmd_write(0xff); // maximum - cmd_write(SET_ENTIRE_ON); // output follows RAM contents - cmd_write(SET_NORM_INV); // not inverted - // charge pump - cmd_write(SET_CHARGE_PUMP); - if (external_vcc == true) { - cmd_write(0x10); - } else { - cmd_write(0x14); - } - // on - cmd_write(SET_DISP | 0x01); - -} - -static void set_col(uint16_t start_col, uint16_t end_col) -{ - cmd_write(SET_COL_ADDR); // column command address - cmd_write(start_col & 0xFF ); - cmd_write(end_col & 0xFF); -} - -static void set_page(uint16_t start_page, uint16_t end_page) -{ - cmd_write(SET_PAGE_ADDR); // page command address - cmd_write(start_page & 0xFF); - cmd_write(end_page & 0xFF); -} - -void driver_ssd1306_clear(uint16_t color) -{ - uint16_t width = 128; - uint16_t height = 64; - - uint16_t x0 = 0; - uint16_t x1 = width - 1; - uint16_t y0 = 0; - uint16_t y1 = height -1; - - if (width == 64) { - // displays with width of 64 pixels are shifted by 32 - x0 += 32; - x1 += 32; - } - - uint16_t num_of_pages = height / 8; - set_col(x0, x1); - set_page(y0, y1); - - mp_hal_pin_high(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - for (uint16_t i = 0; i < (width * num_of_pages); i++) { - raw_write(color); - } - - mp_hal_pin_high(mp_cs_pin); -} - -void driver_ssd1306_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len) { - set_col(line, line); - set_page(0, 63); - - mp_hal_pin_high(mp_dc_pin); - mp_hal_pin_low(mp_cs_pin); - - for (uint8_t i = 0; i < len; i++) { - uint8_t byte = (uint8_t)((uint8_t *)p_bytes)[i]; - raw_write(byte); - } - - mp_hal_pin_high(mp_cs_pin); -} - -#endif diff --git a/nrf5/modules/display/oled_ssd1306_driver.h b/nrf5/modules/display/oled_ssd1306_driver.h deleted file mode 100644 index c9b33ab02d..0000000000 --- a/nrf5/modules/display/oled_ssd1306_driver.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef OLED_SSD1306_DRIVER_H__ -#define OLED_SSD1306_DRIVER_H__ - -#include "py/mphal.h" - -#include "hal_spi.h" -#include "framebuffer.h" - -void driver_ssd1306_init(NRF_SPI_Type * p_instance, pin_obj_t * cs_pin, pin_obj_t * dc_pin, pin_obj_t * reset_pin); - -void driver_ssd1306_clear(uint16_t color); - -void driver_ssd1306_update_line(uint16_t line, framebuffer_byte_t * p_bytes, uint16_t len); - -#endif // OLED_SSD1306_DRIVER_H__ diff --git a/nrf5/modules/display/oled_ssd1306_obj.c b/nrf5/modules/display/oled_ssd1306_obj.c deleted file mode 100644 index 55e5094996..0000000000 --- a/nrf5/modules/display/oled_ssd1306_obj.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" -#include "py/runtime.h" -#include "py/mphal.h" -#include "genhdr/pins.h" - -#include "oled_ssd1306_driver.h" - -#if MICROPY_PY_DISPLAY_OLED_SSD1306 - -/// \moduleref display -/// \class SSD1306 - SSD1306 TFT LCD display driver. - -#include "moddisplay.h" -#include "framebuffer.h" -#include "pin.h" -#include "spi.h" - -typedef struct _oled_ssd1306_obj_t { - mp_obj_base_t base; - display_draw_callbacks_t draw_callbacks; - framebuffer_t * framebuffer; - machine_hard_spi_obj_t *spi; - pin_obj_t * pin_cs; - pin_obj_t * pin_dc; - pin_obj_t * pin_reset; -} oled_ssd1306_obj_t; - -#define OLED_SSD1306_COLOR_BLACK 0 -#define OLED_SSD1306_COLOR_WHITE 1 - -static void set_pixel(void * p_display, - uint16_t x, - uint16_t y, - uint16_t color) { - oled_ssd1306_obj_t *self = (oled_ssd1306_obj_t *)p_display; - - if (color == OLED_SSD1306_COLOR_BLACK) { - framebuffer_pixel_clear(self->framebuffer, x, y); - } else { - framebuffer_pixel_set(self->framebuffer, x, y); - } -} - -/// \method __str__() -/// Return a string describing the SSD1306 object. -STATIC void oled_ssd1306_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { - oled_ssd1306_obj_t *self = o; - - mp_printf(print, "SSD1306(SPI(mosi=(port=%u, pin=%u), miso=(port=%u, pin=%u), clk=(port=%u, pin=%u)),\n", - self->spi->pyb->spi->init.mosi_pin->port, - self->spi->pyb->spi->init.mosi_pin->pin, - self->spi->pyb->spi->init.miso_pin->port, - self->spi->pyb->spi->init.miso_pin->pin, - self->spi->pyb->spi->init.clk_pin->port, - self->spi->pyb->spi->init.clk_pin->pin); - - mp_printf(print, " cs=(port=%u, pin=%u), dc=(port=%u, pin=%u), reset=(port=%u, pin=%u),\n", - self->pin_cs->port, - self->pin_cs->pin, - self->pin_dc->port, - self->pin_dc->pin, - self->pin_reset->port, - self->pin_reset->pin); - - mp_printf(print, " FB(width=%u, height=%u, dir=%u, fb_stride=%u, fb_dirty_stride=%u))\n", - self->framebuffer->screen_width, - self->framebuffer->screen_height, - self->framebuffer->line_orientation, - self->framebuffer->fb_stride, - self->framebuffer->fb_dirty_stride); -} - -// for make_new -enum { - ARG_NEW_WIDTH, - ARG_NEW_HEIGHT, - ARG_NEW_SPI, - ARG_NEW_CS, - ARG_NEW_DC, - ARG_NEW_RESET -}; - -/* - -Example for nrf51822 / pca10028: - -from machine import Pin, SPI -from display import SSD1306 -cs = Pin("A14", mode=Pin.OUT, pull=Pin.PULL_UP) -reset = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) -dc = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -d = SSD1306(128, 64, spi, cs, dc, reset) -d.text("Hello World!", 32, 32) -d.show() - -Example for nrf52832 / pca10040: - -from machine import Pin, SPI -from display import SSD1306 -cs = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) -reset = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) -dc = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -d = SSD1306(128, 64, spi, cs, dc, reset) -d.text("Hello World!", 32, 32) -d.show() - -Example for nrf52840 / pca10056: - -from machine import Pin, SPI -from display import SSD1306 -cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) -reset = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) -dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) -spi = SPI(0, baudrate=8000000) -d = SSD1306(128, 64, spi, cs, dc, reset) -d.text("Hello World!", 32, 32) -d.show() - -*/ -STATIC mp_obj_t oled_ssd1306_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - static const mp_arg_t allowed_args[] = { - { ARG_NEW_WIDTH, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_HEIGHT, MP_ARG_REQUIRED | MP_ARG_INT }, - { ARG_NEW_SPI, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_CS, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_DC, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { ARG_NEW_RESET, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - }; - - // parse args - mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; - mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - - oled_ssd1306_obj_t *s = m_new_obj_with_finaliser(oled_ssd1306_obj_t); - s->base.type = type; - s->draw_callbacks.pixel_set = set_pixel; - - mp_int_t width; - mp_int_t height; - - if (args[ARG_NEW_WIDTH].u_int > 0) { - width = args[ARG_NEW_WIDTH].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display width not set")); - } - - if (args[ARG_NEW_HEIGHT].u_int > 0) { - height = args[ARG_NEW_HEIGHT].u_int; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display height not set")); - } - - if (args[ARG_NEW_SPI].u_obj != MP_OBJ_NULL) { - s->spi = args[ARG_NEW_SPI].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display SPI not set")); - } - - if (args[ARG_NEW_CS].u_obj != MP_OBJ_NULL) { - s->pin_cs = args[ARG_NEW_CS].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display CS Pin not set")); - } - - if (args[ARG_NEW_DC].u_obj != MP_OBJ_NULL) { - s->pin_dc = args[ARG_NEW_DC].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display DC Pin not set")); - } - - if (args[ARG_NEW_RESET].u_obj != MP_OBJ_NULL) { - s->pin_reset = args[ARG_NEW_RESET].u_obj; - } else { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, - "Display Reset Pin not set")); - } - - framebuffer_init_t init_conf = { - .width = width, - .height = height, - .line_orientation = FRAMEBUFFER_LINE_DIR_VERTICAL, - .double_buffer = false - }; - - s->framebuffer = m_new(framebuffer_t, sizeof(framebuffer_t)); - - framebuffer_init(s->framebuffer, &init_conf); - - driver_ssd1306_init(s->spi->pyb->spi->instance, s->pin_cs, s->pin_dc, s->pin_reset); - // Default to black background - driver_ssd1306_clear(0); - - framebuffer_clear(s->framebuffer); - - return MP_OBJ_FROM_PTR(s); -} - -// text - -/// \method fill(color) -/// Fill framebuffer with the color defined as argument. -STATIC mp_obj_t oled_ssd1306_fill(mp_obj_t self_in, mp_obj_t color) { - oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(self_in); - - if (color == MP_OBJ_NEW_SMALL_INT(OLED_SSD1306_COLOR_BLACK)) { - framebuffer_clear(self->framebuffer); - } else { - framebuffer_fill(self->framebuffer); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(oled_ssd1306_fill_obj, oled_ssd1306_fill); - -static void render(framebuffer_t * p_framebuffer) { - for (uint16_t i = 0; i < p_framebuffer->fb_dirty_stride; i++) { - if (p_framebuffer->fb_dirty[i].byte != 0) { - for (uint16_t b = 0; b < 8; b++) { - if ((((p_framebuffer->fb_dirty[i].byte >> b) & 0x01) == 1)) { - uint16_t line_num = (i * 8) + b; - driver_ssd1306_update_line(line_num, - &p_framebuffer->fb_new[line_num * p_framebuffer->fb_stride], - p_framebuffer->fb_stride); - } - } - - p_framebuffer->fb_dirty[i].byte = 0x00; - } - } -} - -/// \method show() -/// Display content in framebuffer. -STATIC mp_obj_t oled_ssd1306_show(size_t n_args, const mp_obj_t *args) { - oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(args[0]); - - render(self->framebuffer); - framebuffer_flip(self->framebuffer); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1306_show_obj, 1, 2, oled_ssd1306_show); - -/// \method refresh([num_of_refresh]) -/// Refresh content in framebuffer. -/// -/// - With no argument, 1 refresh will be done. -/// - With `num_of_refresh` given, The whole framebuffer will be considered -/// dirty and will be refreshed the given number of times. -STATIC mp_obj_t oled_ssd1306_refresh(mp_obj_t self_in) { - oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(oled_ssd1306_refresh_obj, oled_ssd1306_refresh); - -/// \method pixel(x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color of the pixel in framebuffer will be returend. -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t oled_ssd1306_pixel(size_t n_args, const mp_obj_t *args) { - oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(args[0]); - mp_int_t x = mp_obj_get_int(args[1]); - mp_int_t y = mp_obj_get_int(args[2]); - mp_int_t color = mp_obj_get_int(args[3]); - - set_pixel(self, x, y, color); - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1306_pixel_obj, 4, 4, oled_ssd1306_pixel); - -/// \method pixel(text, x, y, [color]) -/// Write one pixel in framebuffer. -/// -/// - With no argument, the color will be the opposite of background (fill color). -/// - With `color` given, sets the pixel to the color given. -STATIC mp_obj_t oled_ssd1306_text(size_t n_args, const mp_obj_t *args) { - oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(args[0]); - const char *str = mp_obj_str_get_str(args[1]); - mp_int_t x = mp_obj_get_int(args[2]); - mp_int_t y = mp_obj_get_int(args[3]); - mp_int_t color; - if (n_args >= 4) { - color = mp_obj_get_int(args[3]); - } - - //display_print_string(self->framebuffer, x, y, str); - - (void)x; - (void)y; - (void)self; - (void)str; - (void)color; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(oled_ssd1306_text_obj, 4, 5, oled_ssd1306_text); - -STATIC mp_obj_t oled_ssd1306_del(mp_obj_t self_in) { - oled_ssd1306_obj_t *self = MP_OBJ_TO_PTR(self_in); - - (void)self; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(oled_ssd1306_del_obj, oled_ssd1306_del); - -STATIC const mp_map_elem_t oled_ssd1306_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)(&oled_ssd1306_del_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_fill), (mp_obj_t)(&oled_ssd1306_fill_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_show), (mp_obj_t)(&oled_ssd1306_show_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)(&oled_ssd1306_text_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_pixel), (mp_obj_t)(&oled_ssd1306_pixel_obj) }, -#if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_bitmap), (mp_obj_t)(&oled_ssd1306_bitmap_obj) }, -#endif - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_BLACK), MP_OBJ_NEW_SMALL_INT(OLED_SSD1306_COLOR_BLACK) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_COLOR_WHITE), MP_OBJ_NEW_SMALL_INT(OLED_SSD1306_COLOR_WHITE) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_VERTICAL), MP_OBJ_NEW_SMALL_INT(0) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_HORIZONTAL), MP_OBJ_NEW_SMALL_INT(1) }, -}; - -STATIC MP_DEFINE_CONST_DICT(oled_ssd1306_locals_dict, oled_ssd1306_locals_dict_table); - -const mp_obj_type_t oled_ssd1306_type = { - { &mp_type_type }, - .name = MP_QSTR_SSD1306, - .print = oled_ssd1306_print, - .make_new = oled_ssd1306_make_new, - .locals_dict = (mp_obj_t)&oled_ssd1306_locals_dict -}; - -#endif // MICROPY_PY_DISPLAY_OLED_SSD1306 diff --git a/nrf5/modules/display/oled_ssd1306_obj.h b/nrf5/modules/display/oled_ssd1306_obj.h deleted file mode 100644 index 37a00b1a88..0000000000 --- a/nrf5/modules/display/oled_ssd1306_obj.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef OLED_SSD1306_H__ -#define OLED_SSD1306_H__ - -#include - -extern const mp_obj_type_t oled_ssd1306_type; - -#endif // OLED_SSD1306_H__ - diff --git a/nrf5/modules/display/rgb16.h b/nrf5/modules/display/rgb16.h deleted file mode 100644 index 96977d4123..0000000000 --- a/nrf5/modules/display/rgb16.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef RGB16_H__ -#define RGB16_H__ - -#define RGB16(rrrrr32, gggggg64, bbbbb32) \ -(((rrrrr32 & 248) | gggggg64 >> 5) << 8) + ((gggggg64 & 28) << 3 | bbbbb32 >> 3) - -#endif // RGB16_H__ diff --git a/nrf5/modules/graphic/draw.c b/nrf5/modules/graphic/draw.c deleted file mode 100644 index 3dfb60a5b6..0000000000 --- a/nrf5/modules/graphic/draw.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "py/nlr.h" -#include "py/runtime.h" -#include "py/mphal.h" - -#include "moddisplay.h" -#include "font_petme128_8x8.h" - -#if MICROPY_PY_DISPLAY_GRAPHICS - -/// \method circle(display, radius, x, y, color, [fill]) -/// Draw a circle in the display framebuffer. -STATIC mp_obj_t draw_circle(mp_uint_t n_args, const mp_obj_t *args) { - display_t * screen = MP_OBJ_TO_PTR(args[0]); - - mp_uint_t radius = mp_obj_get_int(args[1]); - mp_uint_t xc = mp_obj_get_int(args[2]); - mp_uint_t yc = mp_obj_get_int(args[3]); - mp_uint_t color = mp_obj_get_int(args[4]); - - pixel_set_callback_t pixel_set_cb = screen->draw_callbacks.pixel_set; - - // algorithm borrowed from: - // http://stackoverflow.com/a/35541416 - - uint16_t y = radius; - uint16_t x = 0; - int d = 3 - 2 * radius; - - while (x <= y) { - for (uint16_t hor = 0; hor < x + 1; hor++) { - pixel_set_cb(screen, xc+hor, yc+y, color); - pixel_set_cb(screen, xc-hor, yc+y, color); - pixel_set_cb(screen, xc+hor, yc-y, color); - pixel_set_cb(screen, xc-hor, yc-y, color); - pixel_set_cb(screen, xc+x, yc+hor, color); - pixel_set_cb(screen, xc-x, yc+hor, color); - pixel_set_cb(screen, xc+x, yc-hor, color); - pixel_set_cb(screen, xc-x, yc-hor, color); - pixel_set_cb(screen, xc+hor, yc+x, color); - pixel_set_cb(screen, xc-hor, yc+x, color); - pixel_set_cb(screen, xc+hor, yc-x, color); - pixel_set_cb(screen, xc-hor, yc-x, color); - pixel_set_cb(screen, xc+y, yc+hor, color); - pixel_set_cb(screen, xc-y, yc+hor, color); - pixel_set_cb(screen, xc+y, yc-hor, color); - pixel_set_cb(screen, xc-y, yc-hor, color); - } - - if (d < 0) { - d = d + 4 * x + 6; - } else { - d = d + 4 * (x-y) + 10; - y = y - 1; - } - - x = x + 1; - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(graphics_draw_circle_obj, 5, 6, draw_circle); - -STATIC void graphics_draw_char(display_t * screen, uint16_t x, uint16_t y, char ch, uint16_t color, uint8_t font_size) { - - pixel_set_callback_t pixel_set_cb = screen->draw_callbacks.pixel_set; - - uint16_t col = x; - for (uint8_t i = 0; i < 8; i++) { - uint16_t current_col = col + (i * font_size); - - for (uint8_t y_pos = 0; y_pos < 8; y_pos++) { - if ((((uint8_t)font_petme128_8x8[((ch - 32) * 8) + i]) >> y_pos) & 0x01) { - for (uint8_t s_w = 0; s_w < font_size; s_w++) { - for (uint8_t s_h = 0; s_h < font_size; s_h++) { - - uint16_t pix_x = current_col + s_w; - uint16_t pix_y = y + (y_pos * font_size) + s_h; - - pixel_set_cb(screen, pix_x, pix_y, color); - } - } - } else { - for (uint8_t s_w = 0; s_w < font_size; s_w++) { - for (uint8_t s_h = 0; s_h < font_size; s_h++) { - uint16_t pix_x = current_col + s_w; - uint16_t pix_y = y + (y_pos * font_size) + s_h; - - pixel_set_cb(screen, pix_x, pix_y, !color); - } - } - } - } - } -} - -STATIC mp_obj_t graphics_draw_text(size_t n_args, const mp_obj_t *args) { - display_t * screen = MP_OBJ_TO_PTR(args[0]); - - const char *str = mp_obj_str_get_str(args[1]); - mp_int_t x = mp_obj_get_int(args[2]); - mp_int_t y = mp_obj_get_int(args[3]); - mp_int_t color = 0; - if (n_args >= 4) { - color = mp_obj_get_int(args[4]); - } - - uint8_t font_size = 1; - - uint16_t str_len = strlen(str); - for (uint16_t i = 0; i < str_len; i++) { - graphics_draw_char(screen, x + (i * 8 * font_size), y, str[i], color, font_size); - } - - (void)color; - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(graphics_draw_text_obj, 4, 5, graphics_draw_text); - -/// \method rectangle(display, x0, y0, x1, y1, color, [fill]) -STATIC mp_obj_t draw_rectangle(mp_uint_t n_args, const mp_obj_t *args) { - display_t * screen = MP_OBJ_TO_PTR(args[0]); - mp_uint_t x0 = mp_obj_get_int(args[1]); - mp_uint_t y0 = mp_obj_get_int(args[2]); - mp_uint_t x1 = mp_obj_get_int(args[3]); - mp_uint_t y1 = mp_obj_get_int(args[4]); - mp_uint_t color = mp_obj_get_int(args[5]); - - pixel_set_callback_t pixel_set_cb = screen->draw_callbacks.pixel_set; - - // horizontals - for (mp_uint_t hpos = x0; hpos <= x1; hpos++) { - pixel_set_cb(screen, hpos, y0, color); - pixel_set_cb(screen, hpos, y1, color); - } - // verticals - for (mp_uint_t vpos = y0; vpos <= y1; vpos++) { - pixel_set_cb(screen, x0, vpos, color); - pixel_set_cb(screen, x1, vpos, color); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(graphics_draw_rectangle_obj, 6, 7, draw_rectangle); - - -STATIC const mp_map_elem_t graphics_globals_dict_table[] = { - // class methods - { MP_OBJ_NEW_QSTR(MP_QSTR_circle), (mp_obj_t)&graphics_draw_circle_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_text), (mp_obj_t)&graphics_draw_text_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_rectangle), (mp_obj_t)&graphics_draw_rectangle_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(graphics_globals_dict, graphics_globals_dict_table); - -const mp_obj_module_t graphics_module = { - .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&graphics_globals_dict, -}; - -#endif // MICROPY_PY_DISPLAY_GRAPHICS diff --git a/nrf5/modules/graphic/draw.h b/nrf5/modules/graphic/draw.h deleted file mode 100644 index 79419c6862..0000000000 --- a/nrf5/modules/graphic/draw.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2017 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index de50aa57e5..05b3f583cc 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -147,60 +147,6 @@ #define MICROPY_PY_NETWORK (1) #endif - - -#ifndef MICROPY_PY_DISPLAY - -#define MICROPY_PY_DISPLAY (0) -#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) -#define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) -#define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (0) -#define MICROPY_PY_DISPLAY_LCD_SSD1289 (0) -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) -#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) -#define MICROPY_PY_DISPLAY_FRAMEBUFFER (0) -#define MICROPY_PY_DISPLAY_GRAPHICS (0) - -#elif MICROPY_PY_DISPLAY - -// Default to include Monochrome Framebuffer -// if display module is selected. -#ifndef MICROPY_PY_DISPLAY_FRAMEBUFFER -#define MICROPY_PY_DISPLAY_FRAMEBUFFER (1) -#endif - -// Default to include graphics library if -// display modue is selected. -#ifndef MICROPY_PY_DISPLAY_GRAPHICS -#define MICROPY_PY_DISPLAY_GRAPHICS (1) -#endif - -#ifndef MICROPY_PY_DISPLAY_EPAPER_SLD00200P -#define MICROPY_PY_DISPLAY_EPAPER_SLD00200P (0) -#endif - -#ifndef MICROPY_PY_DISPLAY_LCD_ILI9341 -#define MICROPY_PY_DISPLAY_LCD_ILI9341 (0) -#endif - -#ifndef MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX -#define MICROPY_PY_DISPLAY_LCD_LS0XXB7DXXX (0) -#endif - -#ifndef MICROPY_PY_DISPLAY_LCD_SSD1289 -#define MICROPY_PY_DISPLAY_LCD_SSD1289 (0) -#endif - -#ifndef MICROPY_PY_DISPLAY_OLED_SSD1305 -#define MICROPY_PY_DISPLAY_OLED_SSD1305 (0) -#endif - -#ifndef MICROPY_PY_DISPLAY_OLED_SSD1306 -#define MICROPY_PY_DISPLAY_OLED_SSD1306 (0) -#endif - -#endif // MICROPY_PY_DISPLAY - #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) #define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0) @@ -240,9 +186,6 @@ extern const struct _mp_obj_module_t mp_module_utime; extern const struct _mp_obj_module_t mp_module_uos; extern const struct _mp_obj_module_t mp_module_usocket; extern const struct _mp_obj_module_t mp_module_network; -extern const struct _mp_obj_module_t mp_module_lcd_mono_fb; -extern const struct _mp_obj_module_t mp_module_display; -extern const struct _mp_obj_module_t graphics_module; extern const struct _mp_obj_module_t mp_module_ubluepy; #if MICROPY_PY_USOCKET @@ -259,24 +202,6 @@ extern const struct _mp_obj_module_t mp_module_ubluepy; #define NETWORK_BUILTIN_MODULE #endif -#if MICROPY_PY_LCD_MONO_FB -#define LCD_MONO_FB_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_lcd_mono_fb), (mp_obj_t)&mp_module_lcd_mono_fb }, -#else -#define LCD_MONO_FB_MODULE -#endif - -#if MICROPY_PY_DISPLAY -#define DISPLAY_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_display), (mp_obj_t)&mp_module_display }, -#else -#define DISPLAY_MODULE -#endif - -#if MICROPY_PY_DISPLAY_GRAPHICS -#define GRAPHICS_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_draw), (mp_obj_t)&graphics_module }, -#else -#define GRAPHICS_MODULE -#endif - #if MICROPY_PY_UBLUEPY #define UBLUEPY_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy), (mp_obj_t)&mp_module_ubluepy }, #else @@ -295,9 +220,6 @@ extern const struct _mp_obj_module_t ble_module; { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ SOCKET_BUILTIN_MODULE \ NETWORK_BUILTIN_MODULE \ - LCD_MONO_FB_MODULE \ - DISPLAY_MODULE \ - GRAPHICS_MODULE \ UBLUEPY_MODULE \ @@ -308,9 +230,6 @@ extern const struct _mp_obj_module_t ble_module; { MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ - LCD_MONO_FB_MODULE \ - DISPLAY_MODULE \ - GRAPHICS_MODULE \ #endif // BLUETOOTH_SD From d7cfae3639b681b1a25db1bec104e04cad07b508 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 18:53:58 +0200 Subject: [PATCH 578/809] nrf5/usocket: Removing network modules related to Bluetooth 6lowpan implementation as it depends on SDK libraries for now. Will be moved to seperate working branch. --- nrf5/Makefile | 3 - nrf5/bluetooth/bluetooth_common.mk | 2 - nrf5/bluetooth/iot_0.9.0/build.mk | 118 ----- nrf5/bluetooth/iot_0.9.0/modnwble6lowpan.c | 217 ---------- nrf5/bluetooth/iot_0.9.0/sdk.mk | 12 - nrf5/bluetooth/iot_0.9.0/sdk_config.h | 46 -- nrf5/bluetooth/iot_0.9.0/sdkhelp.c | 256 ----------- nrf5/bluetooth/iot_0.9.0/sdkhelp.h | 27 -- nrf5/bluetooth_conf.h | 13 +- nrf5/boards/microbit/mpconfigboard.h | 3 - nrf5/boards/nrf52832_512k_64k_s1xx.ld | 27 -- nrf5/boards/pca10028/mpconfigboard.h | 3 - nrf5/boards/pca10040/mpconfigboard_s1xx.mk | 6 - nrf5/main.c | 5 - nrf5/modules/network/modnetwork.c | 97 ----- nrf5/modules/network/modnetwork.h | 81 ---- nrf5/modules/usocket/modusocket.c | 480 --------------------- nrf5/mpconfigport.h | 27 -- 18 files changed, 1 insertion(+), 1422 deletions(-) delete mode 100644 nrf5/bluetooth/iot_0.9.0/build.mk delete mode 100644 nrf5/bluetooth/iot_0.9.0/modnwble6lowpan.c delete mode 100644 nrf5/bluetooth/iot_0.9.0/sdk.mk delete mode 100644 nrf5/bluetooth/iot_0.9.0/sdk_config.h delete mode 100644 nrf5/bluetooth/iot_0.9.0/sdkhelp.c delete mode 100644 nrf5/bluetooth/iot_0.9.0/sdkhelp.h delete mode 100644 nrf5/boards/nrf52832_512k_64k_s1xx.ld delete mode 100644 nrf5/boards/pca10040/mpconfigboard_s1xx.mk delete mode 100644 nrf5/modules/network/modnetwork.c delete mode 100644 nrf5/modules/network/modnetwork.h delete mode 100644 nrf5/modules/usocket/modusocket.c diff --git a/nrf5/Makefile b/nrf5/Makefile index 511fe4c465..409a6c4c80 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -62,7 +62,6 @@ INC += -I./hal INC += -I./hal/$(MCU_VARIANT) INC += -I./modules/display INC += -I./modules/machine -INC += -I./modules/network INC += -I./modules/ubluepy INC += -I../lib/mp-readline @@ -148,8 +147,6 @@ DRIVERS_SRC_C += $(addprefix modules/,\ machine/pwm.c \ machine/led.c \ machine/temp.c \ - usocket/modusocket.c \ - network/modnetwork.c \ uos/moduos.c \ utime/modutime.c \ pyb/modpyb.c \ diff --git a/nrf5/bluetooth/bluetooth_common.mk b/nrf5/bluetooth/bluetooth_common.mk index 74a367d8e8..21aa9bafbe 100644 --- a/nrf5/bluetooth/bluetooth_common.mk +++ b/nrf5/bluetooth/bluetooth_common.mk @@ -16,8 +16,6 @@ else ifeq ($(SD), s132) CFLAGS += -DBLUETOOTH_SD_DEBUG=1 CFLAGS += -DBLUETOOTH_SD=132 SOFTDEV_HEX_NAME = s132_nrf52_3.0.0_softdevice.hex -#else ifeq ($(SD), s1xx) -# include bluetooth/iot_0.9.0/sdk.mk else $(error Incorrect softdevice set flag) endif diff --git a/nrf5/bluetooth/iot_0.9.0/build.mk b/nrf5/bluetooth/iot_0.9.0/build.mk deleted file mode 100644 index 763aa5a424..0000000000 --- a/nrf5/bluetooth/iot_0.9.0/build.mk +++ /dev/null @@ -1,118 +0,0 @@ -# this file's folder -SDK_DIR := $(SDK_ROOT) - -# -D in CFLAGS -DEFINES += __HEAP_SIZE=0 -DEFINES += BLE_STACK_SUPPORT_REQD -DEFINES += CONFIG_GPIO_AS_PINRESET -DEFINES += NRF52 -DEFINES += NRF52_PAN_12 -DEFINES += NRF52_PAN_15 -DEFINES += NRF52_PAN_20 -DEFINES += NRF52_PAN_30 -DEFINES += NRF52_PAN_31 -DEFINES += NRF52_PAN_36 -DEFINES += NRF52_PAN_51 -DEFINES += NRF52_PAN_53 -DEFINES += NRF52_PAN_54 -DEFINES += NRF52_PAN_55 -DEFINES += NRF52_PAN_58 -DEFINES += NRF52_PAN_62 -DEFINES += NRF52_PAN_63 -DEFINES += NRF52_PAN_64 -DEFINES += s1xx -DEFINES += SOFTDEVICE_PRESENT -DEFINES += SWI_DISABLE0 -DEFINES += NRF_SD_BLE_API_VERSION=3 -DEFINES += PEER_MANAGER_ENABLED=1 -DEFINES += FDS_ENABLED=1 -DEFINES += LWIP_DEBUG=0 - -# nordic SDK C sources (relative path) -SDK_SRC_C += \ - components/ble/common/ble_advdata.c \ - components/ble/common/ble_conn_params.c \ - components/ble/common/ble_srv_common.c \ - components/libraries/fifo/app_fifo.c \ - components/libraries/timer/app_timer.c \ - components/libraries/util/app_util_platform.c \ - components/softdevice/common/softdevice_handler/softdevice_handler.c \ - components/drivers_nrf/clock/nrf_drv_clock.c \ - components/libraries/util/app_error.c \ - components/drivers_nrf/common/nrf_drv_common.c \ - components/libraries/mem_manager/mem_manager.c \ - components/libraries/trace/app_trace.c \ - components/iot/context_manager/iot_context_manager.c \ - components/iot/iot_timer/iot_timer.c \ - external/lwip/src/core/def.c \ - external/lwip/src/core/dhcp.c \ - external/lwip/src/core/ipv6/dhcp6.c \ - external/lwip/src/core/dns.c \ - external/lwip/src/core/ipv4/icmp.c \ - external/lwip/src/core/ipv6/icmp6.c \ - external/lwip/src/core/ipv6/inet6.c \ - external/lwip/src/core/inet_chksum.c \ - external/lwip/src/core/init.c \ - external/lwip/src/core/ipv4/ip4.c \ - external/lwip/src/core/ipv4/ip4_addr.c \ - external/lwip/src/core/ipv6/ip6.c \ - external/lwip/src/core/ipv6/ip6_addr.c \ - external/lwip/src/core/memp.c \ - external/lwip/src/core/ipv6/mld6.c \ - external/lwip/src/core/ipv6/nd6.c \ - external/lwip/src/core/netif.c \ - external/lwip/src/port/nrf_platform_port.c \ - external/lwip/src/core/pbuf.c \ - external/lwip/src/core/raw.c \ - external/lwip/src/core/sys.c \ - external/lwip/src/core/tcp.c \ - external/lwip/src/core/tcp_in.c \ - external/lwip/src/core/tcp_out.c \ - external/lwip/src/core/timers.c \ - external/lwip/src/core/udp.c \ - -# include source folders (sort removes duplicates) -SDK_INC_DIRS += $(sort $(dir $(SDK_SRC_C))) -# nrf_drv_config.h -SDK_INC_DIRS += components/drivers_nrf/config -# app_util.h -SDK_INC_DIRS += components/libraries/util -# nrf_log.h -SDK_INC_DIRS += components/libraries/log/ -# nrf_log_internal.h -SDK_INC_DIRS += components/libraries/log/src -# nrf_clock.h -SDK_INC_DIRS += components/drivers_nrf/hal -# nrf_drv_common.h -SDK_INC_DIRS += components/drivers_nrf/common -# nrf_delay.h -SDK_INC_DIRS += components/drivers_nrf/delay -# ble_6lowpan.h -SDK_INC_DIRS += components/iot/ble_6lowpan -# ble_ipsp.h -SDK_INC_DIRS += components/iot/ble_ipsp -# iot_defines.h -SDK_INC_DIRS += components/iot/common -# SDK lwip includes -SDK_INC_DIRS += external/lwip/src/port/arch -SDK_INC_DIRS += external/lwip/src/include -SDK_INC_DIRS += external/lwip/src/include/netif -SDK_INC_DIRS += external/lwip/src/port -SDK_INC_DIRS += external/lwip/src/include/lwip - -LIBS += $(SDK_ROOT)/components/iot/ble_6lowpan/lib/ble_6lowpan.a - -CFLAGS += $(patsubst %,-D%,${DEFINES}) - -# include full path -INC += $(patsubst %,-I${SDK_DIR}/%, ${SDK_INC_DIRS}) - -# additional SDK source files -SRC_C += $(addprefix ${SDK_ROOT}/, $(SDK_SRC_C)) - -# Wrappers -SRC_C += \ - $(SDK_MODULES_PATH)sdkhelp.c \ - $(SDK_MODULES_PATH)modnwble6lowpan.c \ - - diff --git a/nrf5/bluetooth/iot_0.9.0/modnwble6lowpan.c b/nrf5/bluetooth/iot_0.9.0/modnwble6lowpan.c deleted file mode 100644 index f8b3be89f4..0000000000 --- a/nrf5/bluetooth/iot_0.9.0/modnwble6lowpan.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2016 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "bluetooth_conf.h" - -#if MICROPY_PY_BLE_6LOWPAN - -#include "lwip/ip6_addr.h" -#include "lwip/udp.h" - -#ifdef MAX -#undef MAX -#endif - -#ifdef MIN -#undef MIN -#endif - -#include -#include -#include - -#include "py/nlr.h" -#include "py/objlist.h" -#include "py/runtime.h" -#include "py/mperrno.h" -#include "py/mphal.h" -#include "netutils.h" -#include "modnetwork.h" -#include "pin.h" -#include "genhdr/pins.h" -#include "lwip/ip6_addr.h" -#include "lwip/udp.h" - -/// \moduleref network - -typedef struct _ble_6lowpan_obj_t { - mp_obj_base_t base; -} ble_6lowpan_obj_t; - -STATIC ble_6lowpan_obj_t ble_6lowpan_obj; - - - -STATIC int ble_6lowpan_gethostbyname(mp_obj_t nic, const char *name, mp_uint_t len, uint8_t *out_ip) { - return MP_ENOENT; -} - -STATIC int ble_6lowpan_socket_socket(mod_network_socket_obj_t *socket, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -STATIC void ble_6lowpan_socket_close(mod_network_socket_obj_t *socket) { -} - -STATIC int ble_6lowpan_socket_bind(mod_network_socket_obj_t *socket, byte *ip, mp_uint_t port, int *_errno) { - err_t err; - socket->p_socket = udp_new_ip6(); - if (socket->p_socket) { - - - err = udp_bind_ip6(socket->p_socket, ip, port); - if (err != ERR_OK) { - *_errno = err; - udp_remove(socket->p_socket); - } - } - - return 0; -} - -STATIC int ble_6lowpan_socket_listen(mod_network_socket_obj_t *socket, mp_int_t backlog, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -STATIC int ble_6lowpan_socket_accept(mod_network_socket_obj_t *socket, mod_network_socket_obj_t *socket2, byte *ip, mp_uint_t *port, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -STATIC int ble_6lowpan_socket_connect(mod_network_socket_obj_t *socket, byte *ip, mp_uint_t port, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -STATIC mp_uint_t ble_6lowpan_socket_send(mod_network_socket_obj_t *socket, const byte *buf, mp_uint_t len, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -STATIC mp_uint_t ble_6lowpan_socket_recv(mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -#include "netutils/netutils.h" - -STATIC mp_uint_t ble_6lowpan_socket_sendto(mod_network_socket_obj_t *socket, const byte *buf, mp_uint_t len, byte *ip, mp_uint_t port, int *_errno) { - - struct pbuf * lwip_buffer = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM); - memcpy(lwip_buffer->payload, buf, len); - - printf("Sendto\n"); - - err_t err = udp_sendto_ip6(socket->p_socket, - lwip_buffer, - ip, - port); - - printf("dest: %02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x\n", - ip[0], ip[1], ip[2], ip[3], - ip[4], ip[5], ip[6], ip[7], - ip[8], ip[9], ip[10], ip[11], - ip[12], ip[13], ip[14], ip[15]); - - printf("port: %x\n", port); - printf("len: %d\n", len); - - if (err != ERR_OK) { - *_errno = err; - } - - return 0; -} - -STATIC mp_uint_t ble_6lowpan_socket_recvfrom(mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, byte *ip, mp_uint_t *port, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -STATIC int ble_6lowpan_socket_setsockopt(mod_network_socket_obj_t *socket, mp_uint_t level, mp_uint_t opt, const void *optval, mp_uint_t optlen, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -STATIC int ble_6lowpan_socket_settimeout(mod_network_socket_obj_t *socket, mp_uint_t timeout_ms, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -STATIC int ble_6lowpan_socket_ioctl(mod_network_socket_obj_t *socket, mp_uint_t request, mp_uint_t arg, int *_errno) { - *_errno = MP_EINVAL; - return -1; -} - -#include "sdkhelp.h" - -/******************************************************************************/ -// Micro Python bindings - -/// \classmethod \constructor -/// Create and return a BLE 6LoWPAN object. -STATIC mp_obj_t ble_6lowpan_make_new(const mp_obj_type_t *type, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) { - // check arguments - //mp_arg_check_num(n_args, n_kw, 0, 0, false); - - // init the BLE 6lowpan object - ble_6lowpan_obj.base.type = (mp_obj_type_t*)&mod_network_nic_type_ble_6lowpan; - - // blocking call to wait for connection with peer. - transport_init(); - - // regiser NIC with network module - mod_network_register_nic(&ble_6lowpan_obj); - - // return BLE 6LoWPAN object - return &ble_6lowpan_obj; -} - -const mod_network_nic_type_t mod_network_nic_type_ble_6lowpan = { - .base = { - { &mp_type_type }, - .name = MP_QSTR_BLE6LOWPAN, - .make_new = ble_6lowpan_make_new, - }, - .gethostbyname = ble_6lowpan_gethostbyname, - .socket = ble_6lowpan_socket_socket, - .close = ble_6lowpan_socket_close, - .bind = ble_6lowpan_socket_bind, - .listen = ble_6lowpan_socket_listen, - .accept = ble_6lowpan_socket_accept, - .connect = ble_6lowpan_socket_connect, - .send = ble_6lowpan_socket_send, - .recv = ble_6lowpan_socket_recv, - .sendto = ble_6lowpan_socket_sendto, - .recvfrom = ble_6lowpan_socket_recvfrom, - .setsockopt = ble_6lowpan_socket_setsockopt, - .settimeout = ble_6lowpan_socket_settimeout, - .ioctl = ble_6lowpan_socket_ioctl, -}; - -#endif diff --git a/nrf5/bluetooth/iot_0.9.0/sdk.mk b/nrf5/bluetooth/iot_0.9.0/sdk.mk deleted file mode 100644 index 26544f2fc7..0000000000 --- a/nrf5/bluetooth/iot_0.9.0/sdk.mk +++ /dev/null @@ -1,12 +0,0 @@ - -INC += -I./$(SDK_MODULES_PATH) - -include $(SDK_MODULES_PATH)build.mk - -INC += -I$(SDK_ROOT)components/softdevice/s1xx_iot/headers -INC += -I$(SDK_ROOT)components/softdevice/s1xx_iot/headers/nrf52 -CFLAGS += -DBLUETOOTH_SD=100 -CFLAGS += -DBLUETOOTH_SD_DEBUG=1 - -# softdevice .hex file -SOFTDEV_HEX ?= $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/s1xx_iot/s1xx*softdevice.hex)) diff --git a/nrf5/bluetooth/iot_0.9.0/sdk_config.h b/nrf5/bluetooth/iot_0.9.0/sdk_config.h deleted file mode 100644 index fa851f540f..0000000000 --- a/nrf5/bluetooth/iot_0.9.0/sdk_config.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2016 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef SDK_CONFIG_H__ -#define SDK_CONFIG_H__ - -#define MEMORY_MANAGER_SMALL_BLOCK_COUNT (8) -#define MEMORY_MANAGER_SMALL_BLOCK_SIZE (128) -#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT (4) -#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE (256) -#define MEMORY_MANAGER_LARGE_BLOCK_COUNT (3) -#define MEMORY_MANAGER_LARGE_BLOCK_SIZE (1024) -#define MEM_MANAGER_ENABLE_LOGS (0) -#define MEM_MANAGER_DISABLE_API_PARAM_CHECK (0) -#define IOT_CONTEXT_MANAGER_ENABLE_LOGS (0) -#define IOT_CONTEXT_MANAGER_DISABLE_API_PARAM_CHECK (0) -#define IOT_CONTEXT_MANAGER_MAX_CONTEXTS (16) -#define IOT_CONTEXT_MANAGER_MAX_TABLES (1) -#define NRF_LWIP_DRIVER_ENABLE_LOGS (0) -#define IOT_TIMER_RESOLUTION_IN_MS (100) -#define IOT_TIMER_DISABLE_API_PARAM_CHECK (0) - -#endif // SDK_CONFIG_H__ diff --git a/nrf5/bluetooth/iot_0.9.0/sdkhelp.c b/nrf5/bluetooth/iot_0.9.0/sdkhelp.c deleted file mode 100644 index f3b1bf7991..0000000000 --- a/nrf5/bluetooth/iot_0.9.0/sdkhelp.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2016 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "softdevice_handler.h" -#include "app_trace.h" -#include "app_timer_appsh.h" -#include "ble_advdata.h" -#include "ble_srv_common.h" -#include "ble_ipsp.h" -#include "ble_6lowpan.h" -#include "mem_manager.h" -#include "app_trace.h" -#include "lwip/init.h" -#include "lwip/inet6.h" -#include "lwip/ip6.h" -#include "lwip/ip6_addr.h" -#include "lwip/netif.h" -#include "lwip/timers.h" -#include "nrf_platform_port.h" -#include "app_util_platform.h" -#include "ble_gap.h" -#include "sdkhelp.h" -#include "mpconfigport.h" -#include "app_timer_appsh.h" -#include "iot_timer.h" - -#include "iot_defines.h" - -eui64_t eui64_local_iid; - -bool m_interface_up = false; - -void nrf_driver_interface_up(void) -{ - // sys_check_timeouts(); - m_interface_up = true; -} - -void nrf_driver_interface_down(void) -{ - m_interface_up = false; -} - -#define DEVICE_NAME "MPY_IPv6" -#define APP_ADV_TIMEOUT (0) // disable timeout -#define APP_ADV_ADV_INTERVAL MSEC_TO_UNITS(333, UNIT_0_625_MS) -#define IOT_TIMER_RESOLUTION_IN_MS 100 -#define LWIP_SYS_TICK_MS 100 -#define APP_TIMER_PRESCALER 31 // Value of the RTC1 PRESCALER register. */ -#define APP_TIMER_MAX_TIMERS 1 -#define APP_TIMER_OP_QUEUE_SIZE 5 - -APP_TIMER_DEF(m_iot_timer_tick_src_id); - -static ble_gap_adv_params_t m_adv_params; -static ble_gap_addr_t m_local_ble_addr; - -static void app_lwip_time_tick(iot_timer_time_in_ms_t wall_clock_value) -{ - sys_check_timeouts(); -} - -static void iot_timer_init(void) -{ - uint32_t err_code; - - static const iot_timer_client_t list_of_clients[] = - { - {app_lwip_time_tick, LWIP_SYS_TICK_MS} - }; - - // The list of IoT Timer clients is declared as a constant. - static const iot_timer_clients_list_t iot_timer_clients = - { - (sizeof(list_of_clients) / sizeof(iot_timer_client_t)), - &(list_of_clients[0]), - }; - - // Passing the list of clients to the IoT Timer module. - err_code = iot_timer_client_list_set(&iot_timer_clients); - APP_ERROR_CHECK(err_code); - - // Starting the app timer instance that is the tick source for the IoT Timer. - err_code = app_timer_start(m_iot_timer_tick_src_id, \ - APP_TIMER_TICKS(IOT_TIMER_RESOLUTION_IN_MS, APP_TIMER_PRESCALER), \ - NULL); - APP_ERROR_CHECK(err_code); -} - -static void iot_timer_tick_callback(void * p_context) -{ - UNUSED_VARIABLE(p_context); - uint32_t err_code = iot_timer_update(); - APP_ERROR_CHECK(err_code); -} - -static void timers_init(void) -{ - uint32_t err_code; - - // Initialize timer module, making it use the scheduler - APP_TIMER_APPSH_INIT(APP_TIMER_PRESCALER, APP_TIMER_OP_QUEUE_SIZE, false); - - // Create a sys timer. - err_code = app_timer_create(&m_iot_timer_tick_src_id, - APP_TIMER_MODE_REPEATED, - iot_timer_tick_callback); - APP_ERROR_CHECK(err_code); -} - -static void on_ble_evt(ble_evt_t * p_ble_evt) -{ - switch (p_ble_evt->header.evt_id) - { - case BLE_GAP_EVT_CONNECTED: - break; - case BLE_GAP_EVT_DISCONNECTED: - sd_ble_gap_adv_start(&m_adv_params); - break; - default: - break; - } -} - -static void ble_evt_dispatch(ble_evt_t * p_ble_evt) -{ - ble_ipsp_evt_handler(p_ble_evt); - on_ble_evt(p_ble_evt); -} - -void transport_init(void) { - - // if interface is already up, return - if (m_interface_up) { - return; - } - - uint32_t err_code; - - timers_init(); - - // Initialize the SoftDevice handler module. - SOFTDEVICE_HANDLER_INIT(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, false); - printf("Softdevice init done\n"); - - // Enable BLE stack. - ble_enable_params_t ble_enable_params; - memset(&ble_enable_params, 0x00, sizeof(ble_enable_params)); - ble_enable_params.gatts_enable_params.attr_tab_size = BLE_GATTS_ATTR_TAB_SIZE_DEFAULT; - ble_enable_params.gatts_enable_params.service_changed = false; - err_code = sd_ble_enable(&ble_enable_params); - printf("Softdevice enable:" UINT_FMT "\n", (uint16_t)err_code); - - // Register with the SoftDevice handler module for BLE events. - err_code = softdevice_ble_evt_handler_set(ble_evt_dispatch); - printf("Softdevice evt handler set:" UINT_FMT "\n", (uint16_t)err_code); - APP_ERROR_CHECK(err_code); - - ble_advdata_t advdata; - uint8_t flags = BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED; - ble_gap_conn_sec_mode_t sec_mode; - - BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); - - err_code = sd_ble_gap_device_name_set(&sec_mode, - (const uint8_t *)DEVICE_NAME, - strlen(DEVICE_NAME)); - printf("Device name set:" UINT_FMT "\n", (uint16_t)err_code); - APP_ERROR_CHECK(err_code); - - err_code = sd_ble_gap_address_get(&m_local_ble_addr); - APP_ERROR_CHECK(err_code); - printf("GAP address get:" UINT_FMT "\n", (uint16_t)err_code); - - m_local_ble_addr.addr[5] = 0x00; - m_local_ble_addr.addr_type = BLE_GAP_ADDR_TYPE_PUBLIC; - - err_code = sd_ble_gap_address_set(BLE_GAP_ADDR_CYCLE_MODE_NONE, &m_local_ble_addr); - APP_ERROR_CHECK(err_code); - printf("GAP address set:" UINT_FMT "\n", (uint16_t)err_code); - IPV6_EUI64_CREATE_FROM_EUI48(eui64_local_iid.identifier, - m_local_ble_addr.addr, - m_local_ble_addr.addr_type); - - ble_uuid_t adv_uuids[] = - { - {BLE_UUID_IPSP_SERVICE, BLE_UUID_TYPE_BLE} - }; - - // build and set advertising data - memset(&advdata, 0, sizeof(advdata)); - - advdata.name_type = BLE_ADVDATA_FULL_NAME; - advdata.flags = flags; - advdata.uuids_complete.uuid_cnt = sizeof(adv_uuids) / sizeof(adv_uuids[0]); - advdata.uuids_complete.p_uuids = adv_uuids; - - err_code = ble_advdata_set(&advdata, NULL); - APP_ERROR_CHECK(err_code); - printf("Adv data set:" UINT_FMT "\n", (uint16_t)err_code); - // initialize advertising parameters (used when starting advertising) - memset(&m_adv_params, 0, sizeof(m_adv_params)); - - m_adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND; - m_adv_params.p_peer_addr = NULL; // undirected advertisement - m_adv_params.fp = BLE_GAP_ADV_FP_ANY; - m_adv_params.interval = APP_ADV_ADV_INTERVAL; - m_adv_params.timeout = APP_ADV_TIMEOUT; - - // initialize memory manager - err_code = nrf_mem_init(); - APP_ERROR_CHECK(err_code); - printf("mem init:" UINT_FMT "\n", (uint16_t)err_code); - // initialize lwip stack driver - err_code = nrf_driver_init(); - APP_ERROR_CHECK(err_code); - printf("driver init:" UINT_FMT "\n", (uint16_t)err_code); - // initialize lwip stack - lwip_init(); - printf("lwip init:" UINT_FMT "\n", (uint16_t)err_code); - - iot_timer_init(); - - printf("Starting adv:" UINT_FMT "\n", (uint16_t)err_code); - err_code = sd_ble_gap_adv_start(&m_adv_params); - - while (!m_interface_up) { - ; - } -} - diff --git a/nrf5/bluetooth/iot_0.9.0/sdkhelp.h b/nrf5/bluetooth/iot_0.9.0/sdkhelp.h deleted file mode 100644 index c3e8a122fb..0000000000 --- a/nrf5/bluetooth/iot_0.9.0/sdkhelp.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2016 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -void transport_init(void); diff --git a/nrf5/bluetooth_conf.h b/nrf5/bluetooth_conf.h index 5e62c97961..701cc13a6d 100644 --- a/nrf5/bluetooth_conf.h +++ b/nrf5/bluetooth_conf.h @@ -3,14 +3,7 @@ // SD specific configurations. -#if (BLUETOOTH_SD == 100) - -#define MICROPY_PY_BLE (1) -#define MICROPY_PY_BLE_6LOWPAN (1) -#define MICROPY_PY_USOCKET (1) -#define MICROPY_PY_NETWORK (1) - -#elif (BLUETOOTH_SD == 110) +#if (BLUETOOTH_SD == 110) #define MICROPY_PY_BLE (1) #define MICROPY_PY_BLE_NUS (0) @@ -33,10 +26,6 @@ // Default defines. -#ifndef MICROPY_PY_BLE_6LOWPAN -#define MICROPY_PY_BLE_6LOWPAN (0) -#endif - #ifndef MICROPY_PY_BLE #define MICROPY_PY_BLE (0) #endif diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index 485a3f5acc..f5bfdba88a 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -37,9 +37,6 @@ #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) -#define MICROPY_PY_USOCKET (0) -#define MICROPY_PY_NETWORK (0) - #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/nrf52832_512k_64k_s1xx.ld b/nrf5/boards/nrf52832_512k_64k_s1xx.ld deleted file mode 100644 index 2e2dc7cce6..0000000000 --- a/nrf5/boards/nrf52832_512k_64k_s1xx.ld +++ /dev/null @@ -1,27 +0,0 @@ -/* - GNU linker script for NRF52 w/ s1xx prototype3 softdevice (IPv6) -*/ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x0001F000, LENGTH = 0x061000 /* entire flash, 512 KiB */ - FLASH_ISR (rx) : ORIGIN = 0x0001F000, LENGTH = 0x000400 /* sector 0, 4 KiB */ - FLASH_TEXT (rx) : ORIGIN = 0x0001F400, LENGTH = 0x060c00 /* 396 KiB */ - RAM (xrw) : ORIGIN = 0x20002800, LENGTH = 0x00D800 /* 54 KiB */ -} - -/* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 8K; -_minimum_heap_size = 28K; - -/* top end of the stack */ - -/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ -_estack = ORIGIN(RAM) + LENGTH(RAM); - -/* RAM extents for the garbage collector */ -_ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x2000a800; /* tunable */ - -INCLUDE "boards/common.ld" diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index 8dc210c413..cd04f9b4eb 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -37,9 +37,6 @@ #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) -#define MICROPY_PY_USOCKET (0) -#define MICROPY_PY_NETWORK (0) - #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk b/nrf5/boards/pca10040/mpconfigboard_s1xx.mk deleted file mode 100644 index 1467d01f2c..0000000000 --- a/nrf5/boards/pca10040/mpconfigboard_s1xx.mk +++ /dev/null @@ -1,6 +0,0 @@ -MCU_SERIES = m4 -MCU_VARIANT = nrf52 -MCU_SUB_VARIANT = nrf52832 -LD_FILE = boards/nrf52832_512k_64k_s1xx.ld - -NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf5/main.c b/nrf5/main.c index 0440dacd0d..24651d3e02 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -41,7 +41,6 @@ #include "readline.h" #include "gccollect.h" #include "modmachine.h" -#include "modnetwork.h" #include "led.h" #include "uart.h" #include "nrf.h" @@ -175,10 +174,6 @@ int main(int argc, char **argv) { } #endif -#if MICROPY_PY_NETWORK - mod_network_init(); -#endif - #if MICROPY_HW_LED_TRICOLOR do_str("import pyb\r\n" \ "pyb.LED(1).on()", diff --git a/nrf5/modules/network/modnetwork.c b/nrf5/modules/network/modnetwork.c deleted file mode 100644 index f47df0db4e..0000000000 --- a/nrf5/modules/network/modnetwork.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2014 Damien P. George - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "py/nlr.h" -#include "py/objlist.h" -#include "py/runtime.h" -#include "modnetwork.h" - -#if MICROPY_PY_NETWORK - -/// \module network - network configuration -/// -/// This module provides network drivers and routing configuration. - -void mod_network_init(void) { - mp_obj_list_init(&MP_STATE_PORT(mod_network_nic_list), 0); -} - -void mod_network_register_nic(mp_obj_t nic) { - for (mp_uint_t i = 0; i < MP_STATE_PORT(mod_network_nic_list).len; i++) { - if (MP_STATE_PORT(mod_network_nic_list).items[i] == nic) { - // nic already registered - return; - } - } - // nic not registered so add to list - mp_obj_list_append(&MP_STATE_PORT(mod_network_nic_list), nic); -} - -mp_obj_t mod_network_find_nic(const uint8_t *ip) { - // find a NIC that is suited to given IP address - for (mp_uint_t i = 0; i < MP_STATE_PORT(mod_network_nic_list).len; i++) { - mp_obj_t nic = MP_STATE_PORT(mod_network_nic_list).items[i]; - // TODO check IP suitability here - //mod_network_nic_type_t *nic_type = (mod_network_nic_type_t*)mp_obj_get_type(nic); - return nic; - } - - nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "no available NIC")); -} - -STATIC mp_obj_t network_route(void) { - return &MP_STATE_PORT(mod_network_nic_list); -} -STATIC MP_DEFINE_CONST_FUN_OBJ_0(network_route_obj, network_route); - -STATIC const mp_map_elem_t mp_module_network_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_network) }, - - #if MICROPY_PY_WIZNET5K - { MP_OBJ_NEW_QSTR(MP_QSTR_WIZNET5K), (mp_obj_t)&mod_network_nic_type_wiznet5k }, - #endif - #if MICROPY_PY_CC3K - { MP_OBJ_NEW_QSTR(MP_QSTR_CC3K), (mp_obj_t)&mod_network_nic_type_cc3k }, - #endif - #if MICROPY_PY_BLE_6LOWPAN - { MP_OBJ_NEW_QSTR(MP_QSTR_ble_6lowpan), (mp_obj_t)&mod_network_nic_type_ble_6lowpan }, - #endif - - { MP_OBJ_NEW_QSTR(MP_QSTR_route), (mp_obj_t)&network_route_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(mp_module_network_globals, mp_module_network_globals_table); - -const mp_obj_module_t mp_module_network = { - .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_network_globals, -}; - -#endif // MICROPY_PY_NETWORK diff --git a/nrf5/modules/network/modnetwork.h b/nrf5/modules/network/modnetwork.h deleted file mode 100644 index 73f8b628fc..0000000000 --- a/nrf5/modules/network/modnetwork.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2013, 2014 Damien P. George - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#define MOD_NETWORK_IPADDR_BUF_SIZE (16) - -#define MOD_NETWORK_AF_INET (2) -#define MOD_NETWORK_AF_INET6 (10) - -#define MOD_NETWORK_SOCK_STREAM (1) -#define MOD_NETWORK_SOCK_DGRAM (2) -#define MOD_NETWORK_SOCK_RAW (3) - -struct _mod_network_socket_obj_t; - -typedef struct _mod_network_nic_type_t { - mp_obj_type_t base; - - // API for non-socket operations - int (*gethostbyname)(mp_obj_t nic, const char *name, mp_uint_t len, uint8_t *ip_out); - - // API for socket operations; return -1 on error - int (*socket)(struct _mod_network_socket_obj_t *socket, int *_errno); - void (*close)(struct _mod_network_socket_obj_t *socket); - int (*bind)(struct _mod_network_socket_obj_t *socket, byte *ip, mp_uint_t port, int *_errno); - int (*listen)(struct _mod_network_socket_obj_t *socket, mp_int_t backlog, int *_errno); - int (*accept)(struct _mod_network_socket_obj_t *socket, struct _mod_network_socket_obj_t *socket2, byte *ip, mp_uint_t *port, int *_errno); - int (*connect)(struct _mod_network_socket_obj_t *socket, byte *ip, mp_uint_t port, int *_errno); - mp_uint_t (*send)(struct _mod_network_socket_obj_t *socket, const byte *buf, mp_uint_t len, int *_errno); - mp_uint_t (*recv)(struct _mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, int *_errno); - mp_uint_t (*sendto)(struct _mod_network_socket_obj_t *socket, const byte *buf, mp_uint_t len, byte *ip, mp_uint_t port, int *_errno); - mp_uint_t (*recvfrom)(struct _mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, byte *ip, mp_uint_t *port, int *_errno); - int (*setsockopt)(struct _mod_network_socket_obj_t *socket, mp_uint_t level, mp_uint_t opt, const void *optval, mp_uint_t optlen, int *_errno); - int (*settimeout)(struct _mod_network_socket_obj_t *socket, mp_uint_t timeout_ms, int *_errno); - int (*ioctl)(struct _mod_network_socket_obj_t *socket, mp_uint_t request, mp_uint_t arg, int *_errno); -} mod_network_nic_type_t; - -typedef struct _mod_network_socket_obj_t { - mp_obj_base_t base; - mp_obj_t nic; - mod_network_nic_type_t *nic_type; - union { - struct { - uint8_t domain; - uint8_t type; - int8_t fileno; - } u_param; - mp_uint_t u_state; - }; - struct udp_pcb * p_socket; -} mod_network_socket_obj_t; - -extern const mod_network_nic_type_t mod_network_nic_type_wiznet5k; -extern const mod_network_nic_type_t mod_network_nic_type_cc3k; -extern const mod_network_nic_type_t mod_network_nic_type_ble_6lowpan; - -void mod_network_init(void); -void mod_network_register_nic(mp_obj_t nic); -mp_obj_t mod_network_find_nic(const uint8_t *ip); diff --git a/nrf5/modules/usocket/modusocket.c b/nrf5/modules/usocket/modusocket.c deleted file mode 100644 index 6afbbf95f9..0000000000 --- a/nrf5/modules/usocket/modusocket.c +++ /dev/null @@ -1,480 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2014 Damien P. George - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "py/nlr.h" -#include "py/objtuple.h" -#include "py/objlist.h" -#include "py/runtime.h" -#include "py/mperrno.h" -#include "lib/netutils/netutils.h" -#include "modnetwork.h" - -#if MICROPY_PY_USOCKET - -/******************************************************************************/ -// socket class - -STATIC const mp_obj_type_t socket_type; - -// constructor socket(family=AF_INET, type=SOCK_STREAM, proto=0, fileno=None) -STATIC mp_obj_t socket_make_new(const mp_obj_type_t *type, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) { - mp_arg_check_num(n_args, n_kw, 0, 4, false); - - // create socket object (not bound to any NIC yet) - mod_network_socket_obj_t *s = m_new_obj_with_finaliser(mod_network_socket_obj_t); - s->base.type = (mp_obj_t)&socket_type; - s->nic = MP_OBJ_NULL; - s->nic_type = NULL; - s->u_param.domain = MOD_NETWORK_AF_INET; - s->u_param.type = MOD_NETWORK_SOCK_STREAM; - s->u_param.fileno = -1; - if (n_args >= 1) { - s->u_param.domain = mp_obj_get_int(args[0]); - if (n_args >= 2) { - s->u_param.type = mp_obj_get_int(args[1]); - if (n_args >= 4) { - s->u_param.fileno = mp_obj_get_int(args[3]); - } - } - } - - return s; -} - -STATIC void socket_select_nic(mod_network_socket_obj_t *self, const byte *ip) { - if (self->nic == MP_OBJ_NULL) { - // select NIC based on IP - self->nic = mod_network_find_nic(ip); - self->nic_type = (mod_network_nic_type_t*)mp_obj_get_type(self->nic); - - // call the NIC to open the socket - int _errno; - if (self->nic_type->socket(self, &_errno) != 0) { - mp_raise_OSError(_errno); - } - } -} -// method socket.close() -STATIC mp_obj_t socket_close(mp_obj_t self_in) { - mod_network_socket_obj_t *self = self_in; - if (self->nic != MP_OBJ_NULL) { - self->nic_type->close(self); - self->nic = MP_OBJ_NULL; - } - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(socket_close_obj, socket_close); - -#include - -// method socket.bind(address) -STATIC mp_obj_t socket_bind(mp_obj_t self_in, mp_obj_t addr_in) { - mod_network_socket_obj_t *self = self_in; - - // get address - uint8_t ip[MOD_NETWORK_IPADDR_BUF_SIZE]; - - mp_uint_t port; - if (self->u_param.domain == MOD_NETWORK_AF_INET) { - port = netutils_parse_inet_addr(addr_in, ip, NETUTILS_BIG); - } else { - port = netutils_parse_inet6_addr(addr_in, ip, NETUTILS_BIG); - } - - // check if we need to select a NIC - socket_select_nic(self, ip); - - // call the NIC to bind the socket - int _errno; - if (self->nic_type->bind(self, ip, port, &_errno) != 0) { - mp_raise_OSError(_errno); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_bind_obj, socket_bind); - -// method socket.listen(backlog) -STATIC mp_obj_t socket_listen(mp_obj_t self_in, mp_obj_t backlog) { - mod_network_socket_obj_t *self = self_in; - - if (self->nic == MP_OBJ_NULL) { - // not connected - // TODO I think we can listen even if not bound... - mp_raise_OSError(MP_ENOTCONN); - } - - int _errno; - if (self->nic_type->listen(self, mp_obj_get_int(backlog), &_errno) != 0) { - mp_raise_OSError(_errno); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_listen_obj, socket_listen); - -// method socket.accept() -STATIC mp_obj_t socket_accept(mp_obj_t self_in) { - mod_network_socket_obj_t *self = self_in; - - // create new socket object - // starts with empty NIC so that finaliser doesn't run close() method if accept() fails - mod_network_socket_obj_t *socket2 = m_new_obj_with_finaliser(mod_network_socket_obj_t); - socket2->base.type = (mp_obj_t)&socket_type; - socket2->nic = MP_OBJ_NULL; - socket2->nic_type = NULL; - - // accept incoming connection - uint8_t ip[MOD_NETWORK_IPADDR_BUF_SIZE]; - mp_uint_t port; - int _errno; - if (self->nic_type->accept(self, socket2, ip, &port, &_errno) != 0) { - mp_raise_OSError(_errno); - } - - // new socket has valid state, so set the NIC to the same as parent - socket2->nic = self->nic; - socket2->nic_type = self->nic_type; - - // make the return value - mp_obj_tuple_t *client = mp_obj_new_tuple(2, NULL); - client->items[0] = socket2; - - if (self->u_param.domain == MOD_NETWORK_AF_INET) { - client->items[1] = netutils_format_inet_addr(ip, port, NETUTILS_BIG); - } else { - client->items[1] = netutils_format_inet6_addr(ip, port, NETUTILS_BIG); - } - - return client; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_1(socket_accept_obj, socket_accept); - -// method socket.connect(address) -STATIC mp_obj_t socket_connect(mp_obj_t self_in, mp_obj_t addr_in) { - mod_network_socket_obj_t *self = self_in; - - // get address - uint8_t ip[MOD_NETWORK_IPADDR_BUF_SIZE]; - - mp_uint_t port; - if (self->u_param.domain == MOD_NETWORK_AF_INET) { - port = netutils_parse_inet_addr(addr_in, ip, NETUTILS_BIG); - } else { - port = netutils_parse_inet6_addr(addr_in, ip, NETUTILS_BIG); - } - // check if we need to select a NIC - socket_select_nic(self, ip); - - // call the NIC to connect the socket - int _errno; - if (self->nic_type->connect(self, ip, port, &_errno) != 0) { - mp_raise_OSError(_errno); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_connect_obj, socket_connect); - -// method socket.send(bytes) -STATIC mp_obj_t socket_send(mp_obj_t self_in, mp_obj_t buf_in) { - mod_network_socket_obj_t *self = self_in; - if (self->nic == MP_OBJ_NULL) { - // not connected - mp_raise_OSError(MP_EPIPE); - } - mp_buffer_info_t bufinfo; - mp_get_buffer_raise(buf_in, &bufinfo, MP_BUFFER_READ); - int _errno; - mp_uint_t ret = self->nic_type->send(self, bufinfo.buf, bufinfo.len, &_errno); - if (ret == -1) { - mp_raise_OSError(_errno); - } - return mp_obj_new_int_from_uint(ret); -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_send_obj, socket_send); - -// method socket.recv(bufsize) -STATIC mp_obj_t socket_recv(mp_obj_t self_in, mp_obj_t len_in) { - mod_network_socket_obj_t *self = self_in; - if (self->nic == MP_OBJ_NULL) { - // not connected - mp_raise_OSError(MP_ENOTCONN); - } - mp_int_t len = mp_obj_get_int(len_in); - vstr_t vstr; - vstr_init_len(&vstr, len); - int _errno; - mp_uint_t ret = self->nic_type->recv(self, (byte*)vstr.buf, len, &_errno); - if (ret == -1) { - mp_raise_OSError(_errno); - } - if (ret == 0) { - return mp_const_empty_bytes; - } - vstr.len = ret; - return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr); -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_recv_obj, socket_recv); - -// method socket.sendto(bytes, address) -STATIC mp_obj_t socket_sendto(mp_obj_t self_in, mp_obj_t data_in, mp_obj_t addr_in) { - mod_network_socket_obj_t *self = self_in; - - // get the data - mp_buffer_info_t bufinfo; - mp_get_buffer_raise(data_in, &bufinfo, MP_BUFFER_READ); - - // get address - uint8_t ip[MOD_NETWORK_IPADDR_BUF_SIZE]; - mp_uint_t port; - if (self->u_param.domain == MOD_NETWORK_AF_INET) { - port = netutils_parse_inet_addr(addr_in, ip, NETUTILS_BIG); - } else { - port = netutils_parse_inet6_addr(addr_in, ip, NETUTILS_BIG); - } - - // check if we need to select a NIC - socket_select_nic(self, ip); - - // call the NIC to sendto - int _errno; - mp_int_t ret = self->nic_type->sendto(self, bufinfo.buf, bufinfo.len, ip, port, &_errno); - if (ret == -1) { - mp_raise_OSError(_errno); - } - - return mp_obj_new_int(ret); -} -STATIC MP_DEFINE_CONST_FUN_OBJ_3(socket_sendto_obj, socket_sendto); - -// method socket.recvfrom(bufsize) -STATIC mp_obj_t socket_recvfrom(mp_obj_t self_in, mp_obj_t len_in) { - mod_network_socket_obj_t *self = self_in; - if (self->nic == MP_OBJ_NULL) { - // not connected - mp_raise_OSError(MP_ENOTCONN); - } - vstr_t vstr; - vstr_init_len(&vstr, mp_obj_get_int(len_in)); - byte ip[4]; - mp_uint_t port; - int _errno; - mp_int_t ret = self->nic_type->recvfrom(self, (byte*)vstr.buf, vstr.len, ip, &port, &_errno); - if (ret == -1) { - mp_raise_OSError(_errno); - } - mp_obj_t tuple[2]; - if (ret == 0) { - tuple[0] = mp_const_empty_bytes; - } else { - vstr.len = ret; - tuple[0] = mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr); - } - - if (self->u_param.domain == MOD_NETWORK_AF_INET) { - tuple[1] = netutils_format_inet_addr(ip, port, NETUTILS_BIG); - } else { - tuple[1] = netutils_format_inet6_addr(ip, port, NETUTILS_BIG); - } - return mp_obj_new_tuple(2, tuple); -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_recvfrom_obj, socket_recvfrom); - -// method socket.setsockopt(level, optname, value) -STATIC mp_obj_t socket_setsockopt(mp_uint_t n_args, const mp_obj_t *args) { - mod_network_socket_obj_t *self = args[0]; - - mp_int_t level = mp_obj_get_int(args[1]); - mp_int_t opt = mp_obj_get_int(args[2]); - - const void *optval; - mp_uint_t optlen; - mp_int_t val; - if (mp_obj_is_integer(args[3])) { - val = mp_obj_get_int_truncated(args[3]); - optval = &val; - optlen = sizeof(val); - } else { - mp_buffer_info_t bufinfo; - mp_get_buffer_raise(args[3], &bufinfo, MP_BUFFER_READ); - optval = bufinfo.buf; - optlen = bufinfo.len; - } - - int _errno; - if (self->nic_type->setsockopt(self, level, opt, optval, optlen, &_errno) != 0) { - mp_raise_OSError(_errno); - } - - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(socket_setsockopt_obj, 4, 4, socket_setsockopt); - -// method socket.settimeout(value) -// timeout=0 means non-blocking -// timeout=None means blocking -// otherwise, timeout is in seconds -STATIC mp_obj_t socket_settimeout(mp_obj_t self_in, mp_obj_t timeout_in) { - mod_network_socket_obj_t *self = self_in; - if (self->nic == MP_OBJ_NULL) { - // not connected - mp_raise_OSError(MP_ENOTCONN); - } - mp_uint_t timeout; - if (timeout_in == mp_const_none) { - timeout = -1; - } else { - #if MICROPY_PY_BUILTINS_FLOAT - timeout = 1000 * mp_obj_get_float(timeout_in); - #else - timeout = 1000 * mp_obj_get_int(timeout_in); - #endif - } - int _errno; - if (self->nic_type->settimeout(self, timeout, &_errno) != 0) { - mp_raise_OSError(_errno); - } - return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_settimeout_obj, socket_settimeout); - -// method socket.setblocking(flag) -STATIC mp_obj_t socket_setblocking(mp_obj_t self_in, mp_obj_t blocking) { - if (mp_obj_is_true(blocking)) { - return socket_settimeout(self_in, mp_const_none); - } else { - return socket_settimeout(self_in, MP_OBJ_NEW_SMALL_INT(0)); - } -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_setblocking_obj, socket_setblocking); - -STATIC const mp_map_elem_t socket_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)&socket_close_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_close), (mp_obj_t)&socket_close_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_bind), (mp_obj_t)&socket_bind_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_listen), (mp_obj_t)&socket_listen_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_accept), (mp_obj_t)&socket_accept_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)&socket_connect_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_send), (mp_obj_t)&socket_send_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_recv), (mp_obj_t)&socket_recv_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_sendto), (mp_obj_t)&socket_sendto_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_recvfrom), (mp_obj_t)&socket_recvfrom_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setsockopt), (mp_obj_t)&socket_setsockopt_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_settimeout), (mp_obj_t)&socket_settimeout_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setblocking), (mp_obj_t)&socket_setblocking_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(socket_locals_dict, socket_locals_dict_table); - -mp_uint_t socket_ioctl(mp_obj_t self_in, mp_uint_t request, mp_uint_t arg, int *errcode) { - mod_network_socket_obj_t *self = self_in; - return self->nic_type->ioctl(self, request, arg, errcode); -} - -STATIC const mp_stream_p_t socket_stream_p = { - .ioctl = socket_ioctl, - .is_text = false, -}; - -STATIC const mp_obj_type_t socket_type = { - { &mp_type_type }, - .name = MP_QSTR_socket, - .make_new = socket_make_new, - .protocol = &socket_stream_p, - .locals_dict = (mp_obj_t)&socket_locals_dict, -}; - -/******************************************************************************/ -// usocket module - -// function usocket.getaddrinfo(host, port) -STATIC mp_obj_t mod_usocket_getaddrinfo(mp_obj_t host_in, mp_obj_t port_in) { - mp_uint_t hlen; - const char *host = mp_obj_str_get_data(host_in, &hlen); - mp_int_t port = mp_obj_get_int(port_in); - - // find a NIC that can do a name lookup - for (mp_uint_t i = 0; i < MP_STATE_PORT(mod_network_nic_list).len; i++) { - mp_obj_t nic = MP_STATE_PORT(mod_network_nic_list).items[i]; - mod_network_nic_type_t *nic_type = (mod_network_nic_type_t*)mp_obj_get_type(nic); - if (nic_type->gethostbyname != NULL) { - uint8_t out_ip[MOD_NETWORK_IPADDR_BUF_SIZE]; - int ret = nic_type->gethostbyname(nic, host, hlen, out_ip); - if (ret != 0) { - // TODO CPython raises: socket.gaierror: [Errno -2] Name or service not known - mp_raise_OSError(ret); - } - mp_obj_tuple_t *tuple = mp_obj_new_tuple(5, NULL); - tuple->items[0] = MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_AF_INET); - tuple->items[1] = MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_SOCK_STREAM); - tuple->items[2] = MP_OBJ_NEW_SMALL_INT(0); - tuple->items[3] = MP_OBJ_NEW_QSTR(MP_QSTR_); - tuple->items[4] = netutils_format_inet_addr(out_ip, port, NETUTILS_BIG); - return mp_obj_new_list(1, (mp_obj_t*)&tuple); - } - } - - nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "no available NIC")); -} -STATIC MP_DEFINE_CONST_FUN_OBJ_2(mod_usocket_getaddrinfo_obj, mod_usocket_getaddrinfo); - -STATIC const mp_map_elem_t mp_module_usocket_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_usocket) }, - - { MP_OBJ_NEW_QSTR(MP_QSTR_socket), (mp_obj_t)&socket_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getaddrinfo), (mp_obj_t)&mod_usocket_getaddrinfo_obj }, - - // class constants - { MP_OBJ_NEW_QSTR(MP_QSTR_AF_INET), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_AF_INET) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AF_INET6), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_AF_INET6) }, - - { MP_OBJ_NEW_QSTR(MP_QSTR_SOCK_STREAM), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_SOCK_STREAM) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_SOCK_DGRAM), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_SOCK_DGRAM) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_SOCK_RAW), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_SOCK_RAW) }, - - /* - { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_IP), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_IP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_ICMP), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_ICMP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_IPV4), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_IPV4) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_TCP), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_TCP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_UDP), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_UDP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_IPV6), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_IPV6) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_RAW), MP_OBJ_NEW_SMALL_INT(MOD_NETWORK_IPPROTO_RAW) }, - */ -}; - -STATIC MP_DEFINE_CONST_DICT(mp_module_usocket_globals, mp_module_usocket_globals_table); - -const mp_obj_module_t mp_module_usocket = { - .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_usocket_globals, -}; - -#endif // MICROPY_PY_USOCKET diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 05b3f583cc..98e41ca972 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -139,14 +139,6 @@ #define MICROPY_PY_MACHINE_RTC (0) #endif -#ifndef MICROPY_PY_USOCKET -#define MICROPY_PY_USOCKET (1) -#endif - -#ifndef MICROPY_PY_NETWORK -#define MICROPY_PY_NETWORK (1) -#endif - #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) #define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0) @@ -184,24 +176,8 @@ extern const struct _mp_obj_module_t pyb_module; extern const struct _mp_obj_module_t machine_module; extern const struct _mp_obj_module_t mp_module_utime; extern const struct _mp_obj_module_t mp_module_uos; -extern const struct _mp_obj_module_t mp_module_usocket; -extern const struct _mp_obj_module_t mp_module_network; extern const struct _mp_obj_module_t mp_module_ubluepy; -#if MICROPY_PY_USOCKET -#define SOCKET_BUILTIN_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_usocket), (mp_obj_t)&mp_module_usocket }, -#define SOCKET_BUILTIN_MODULE_WEAK_LINKS { MP_OBJ_NEW_QSTR(MP_QSTR_socket), (mp_obj_t)&mp_module_usocket }, -#else -#define SOCKET_BUILTIN_MODULE -#define SOCKET_BUILTIN_MODULE_WEAK_LINKS -#endif - -#if MICROPY_PY_NETWORK -#define NETWORK_BUILTIN_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_network), (mp_obj_t)&mp_module_network }, -#else -#define NETWORK_BUILTIN_MODULE -#endif - #if MICROPY_PY_UBLUEPY #define UBLUEPY_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy), (mp_obj_t)&mp_module_ubluepy }, #else @@ -218,8 +194,6 @@ extern const struct _mp_obj_module_t ble_module; { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&mp_module_utime }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ - SOCKET_BUILTIN_MODULE \ - NETWORK_BUILTIN_MODULE \ UBLUEPY_MODULE \ @@ -236,7 +210,6 @@ extern const struct _mp_obj_module_t ble_module; #define MICROPY_PORT_BUILTIN_MODULE_WEAK_LINKS \ { MP_OBJ_NEW_QSTR(MP_QSTR_os), (mp_obj_t)&mp_module_uos }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&mp_module_utime }, \ - SOCKET_BUILTIN_MODULE_WEAK_LINKS \ // extra built in names to add to the global namespace #define MICROPY_PORT_BUILTINS \ From 35f9c8f37fe9c9071ff2bb2d5ea43a8a9ce9257b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 18:55:53 +0200 Subject: [PATCH 579/809] nrf5: Removing leftover reference to deleted display module. --- nrf5/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 409a6c4c80..72fd1e5213 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -60,7 +60,6 @@ INC += -I./device INC += -I./device/$(MCU_VARIANT) INC += -I./hal INC += -I./hal/$(MCU_VARIANT) -INC += -I./modules/display INC += -I./modules/machine INC += -I./modules/ubluepy INC += -I../lib/mp-readline From 800a3991825fb3c3bf2e548e94a292ca22c4e497 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 18:58:05 +0200 Subject: [PATCH 580/809] Revert "lib/netutils: Adding some basic parsing and formating of ipv6 address strings. Only working with full length ipv6 strings. Short forms not supported at the moment (for example FE80::1, needs to be expressed as FE80:0000:0000:0000:0000:0000:0000:0001)." This reverts commit 4344d41b36488a8a86b5e45c0edaec1ad1fd910a. --- lib/netutils/netutils.c | 85 ----------------------------------------- lib/netutils/netutils.h | 15 -------- 2 files changed, 100 deletions(-) diff --git a/lib/netutils/netutils.c b/lib/netutils/netutils.c index f6718bf3e5..a2ea31cf38 100644 --- a/lib/netutils/netutils.c +++ b/lib/netutils/netutils.c @@ -5,7 +5,6 @@ * * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2015 Daniel Campora - * Copyright (c) 2016 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,7 +28,6 @@ #include #include #include -#include #include "py/obj.h" #include "py/nlr.h" @@ -95,86 +93,3 @@ mp_uint_t netutils_parse_inet_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_e netutils_parse_ipv4_addr(addr_items[0], out_ip, endian); return mp_obj_get_int(addr_items[1]); } - - -// Takes an array with a raw IPv6 address and returns something like '2001:db8::abcd:ef01:2345'. -mp_obj_t netutils_format_ipv6_addr(uint8_t *ip, netutils_endian_t endian) { - char ip_str[40]; - mp_uint_t ip_len; - if (endian == NETUTILS_LITTLE) { - ip_len = snprintf(ip_str, 40, "%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x", - ip[15], ip[14], ip[13], ip[12], - ip[11], ip[10], ip[9], ip[8], - ip[7], ip[6], ip[5], ip[4], - ip[3], ip[2], ip[1], ip[0]); - } else { - ip_len = snprintf(ip_str, 40, "%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x", - ip[0], ip[1], ip[2], ip[3], - ip[4], ip[5], ip[6], ip[7], - ip[8], ip[9], ip[10], ip[11], - ip[12], ip[13], ip[14], ip[15]); - } - return mp_obj_new_str(ip_str, ip_len, false); -} - -// Takes an array with a raw IP address, and a port, and returns a net-address -// tuple such as ('2001:db8::abcd:ef01:2345', 8080). -mp_obj_t netutils_format_inet6_addr(uint8_t *ip, mp_uint_t port, netutils_endian_t endian) { - mp_obj_t tuple[2] = { - tuple[0] = netutils_format_ipv6_addr(ip, endian), - tuple[1] = mp_obj_new_int(port), - }; - return mp_obj_new_tuple(2, tuple); -} - -void netutils_parse_ipv6_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian) { - mp_uint_t addr_len; - const char *addr_str = mp_obj_str_get_data(addr_in, &addr_len); - if (addr_len == 0) { - // special case of no address given - memset(out_ip, 0, NETUTILS_IPV6ADDR_BUFSIZE); - return; - } - - const char *s = addr_str; - const char *s_top = addr_str + addr_len; - - for (uint8_t i = 0; i <= NETUTILS_IPV6ADDR_BUFSIZE; i += 2) { - uint16_t val = 0; - for (; s < s_top && *s != ':'; s++) { - if ((*s >= 'a' && *s <= 'f')) { - val = val * 16 + (*s - 'a' + 10); - } else if (*s >= 'A' && *s <= 'F') { - val = val * 16 + (*s - 'A' + 10); - } else { - val = val * 16 + (*s - '0'); - } - } - -// if (endian == NETUTILS_LITTLE) { -// // not supported -// } else - { - out_ip[i] = (val >> 8); - out_ip[i + 1] = (val & 0xFF); - } - - if (s == s_top) { - return; - } else if (s < s_top && *s == ':') { - s++; - } else { - nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "invalid arguments")); - } - } -} - -// Takes an address of the form ('2001:db8::abcd:ef01:2345', 8080), returns the port and -// puts IP in out_ip (which must take at least IPADDR_BUF_SIZE bytes). -mp_uint_t netutils_parse_inet6_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian) { - mp_obj_t *addr_items; - mp_obj_get_array_fixed_n(addr_in, 2, &addr_items); - netutils_parse_ipv6_addr(addr_items[0], out_ip, endian); - return mp_obj_get_int(addr_items[1]); - -} diff --git a/lib/netutils/netutils.h b/lib/netutils/netutils.h index 78ffffc551..45e0216402 100644 --- a/lib/netutils/netutils.h +++ b/lib/netutils/netutils.h @@ -5,7 +5,6 @@ * * Copyright (c) 2013, 2014 Damien P. George * Copyright (c) 2015 Daniel Campora - * Copyrigth (c) 2016 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,7 +28,6 @@ #define __MICROPY_INCLUDED_LIB_NETUTILS_H__ #define NETUTILS_IPV4ADDR_BUFSIZE 4 -#define NETUTILS_IPV6ADDR_BUFSIZE 16 typedef enum _netutils_endian_t { NETUTILS_LITTLE, @@ -49,17 +47,4 @@ void netutils_parse_ipv4_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian // puts IP in out_ip (which must take at least IPADDR_BUF_SIZE bytes). mp_uint_t netutils_parse_inet_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian); -// Takes an array with a raw IPv6 address and returns something like '2001:db8::abcd:ef01:2345'. -mp_obj_t netutils_format_ipv6_addr(uint8_t *ip, netutils_endian_t endian); - -// Takes an array with a raw IP address, and a port, and returns a net-address -// tuple such as ('2001:db8::abcd:ef01:2345', 8080). -mp_obj_t netutils_format_inet6_addr(uint8_t *ip, mp_uint_t port, netutils_endian_t endian); - -void netutils_parse_ipv6_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian); - -// Takes an address of the form ('2001:db8::abcd:ef01:2345', 8080), returns the port and -// puts IP in out_ip (which must take at least IPADDR_BUF_SIZE bytes). -mp_uint_t netutils_parse_inet6_addr(mp_obj_t addr_in, uint8_t *out_ip, netutils_endian_t endian); - #endif // __MICROPY_INCLUDED_LIB_NETUTILS_H__ From 3b15d33809399cf6efc299bfe53ead0db7deaa3a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 21:39:15 +0200 Subject: [PATCH 581/809] nrf5/hal: Moving hal_gpio functions, types and defines from mphalport.h to a new hal_gpio.h. --- nrf5/hal/hal_gpio.h | 91 +++++++++++++++++++++++++++++++++++++++++++++ nrf5/mphalport.h | 86 ++---------------------------------------- 2 files changed, 95 insertions(+), 82 deletions(-) create mode 100644 nrf5/hal/hal_gpio.h diff --git a/nrf5/hal/hal_gpio.h b/nrf5/hal/hal_gpio.h new file mode 100644 index 0000000000..ca5c8a5028 --- /dev/null +++ b/nrf5/hal/hal_gpio.h @@ -0,0 +1,91 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_GPIO_H__ +#define HAL_GPIO_H__ + +#if NRF51 + #define POINTERS (const uint32_t[]){NRF_GPIO_BASE} +#endif + +#if NRF52 + #ifdef NRF52832_XXAA + #define POINTERS (const uint32_t[]){NRF_P0_BASE} + #endif + + #ifdef NRF52840_XXAA + #define POINTERS (const uint32_t[]){NRF_P0_BASE, NRF_P1_BASE} + #endif +#endif + +#define GPIO_BASE(x) ((NRF_GPIO_Type *)POINTERS[x]) + +#define hal_gpio_pin_high(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTSET = (p)->pin_mask) +#define hal_gpio_pin_low(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask) +#define hal_gpio_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1) + +typedef enum { + HAL_GPIO_PULL_DISABLED = (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos), + HAL_GPIO_PULL_DOWN = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos), + HAL_GPIO_PULL_UP = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) +} hal_gpio_pull_t; + +typedef enum { + HAL_GPIO_MODE_OUTPUT = (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos), + HAL_GPIO_MODE_INPUT = (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos), +} hal_gpio_mode_t; + +static inline void hal_gpio_cfg_pin(uint8_t port, uint32_t pin_number, hal_gpio_mode_t mode, hal_gpio_pull_t pull) { + GPIO_BASE(port)->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | pull + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | mode; +} + +static inline void hal_gpio_out_set(uint8_t port, uint32_t pin_mask) { + GPIO_BASE(port)->OUTSET = pin_mask; +} + +static inline void hal_gpio_pin_set(uint8_t port, uint32_t pin) { + GPIO_BASE(port)->OUTSET = (1 << pin); +} + +static inline void hal_gpio_pin_clear(uint8_t port, uint32_t pin) { + GPIO_BASE(port)->OUTCLR = (1 << pin); +} + +static inline void hal_gpio_pin_toggle(uint8_t port, uint32_t pin) { + uint32_t pin_mask = (1 << pin); + + if (GPIO_BASE(port)->OUT ^ pin_mask) { + GPIO_BASE(port)->OUTSET = pin_mask; + } else { + GPIO_BASE(port)->OUTCLR = pin_mask; + } +} + +#endif // HAL_GPIO_H__ diff --git a/nrf5/mphalport.h b/nrf5/mphalport.h index ae3f65b5bb..bda223cea3 100644 --- a/nrf5/mphalport.h +++ b/nrf5/mphalport.h @@ -30,6 +30,7 @@ #include "py/mpconfig.h" #include NRF5_HAL_H #include "pin.h" +#include "hal_gpio.h" typedef enum { @@ -39,85 +40,6 @@ typedef enum HAL_TIMEOUT = 0x03 } HAL_StatusTypeDef; - -#if NRF51 - #define POINTERS (const uint32_t[]){NRF_GPIO_BASE} -#endif - -#if NRF52 - #ifdef NRF52832_XXAA - #define POINTERS (const uint32_t[]){NRF_P0_BASE} - #endif - - #ifdef NRF52840_XXAA - #define POINTERS (const uint32_t[]){NRF_P0_BASE, NRF_P1_BASE} - #endif -#endif - -#define GPIO_BASE(x) ((NRF_GPIO_Type *)POINTERS[x]) - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode_define */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull_define */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed_define */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_Alternat_function_selection */ -} GPIO_InitTypeDef; - -typedef enum { - HAL_GPIO_PULL_DISABLED = (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos), - HAL_GPIO_PULL_DOWN = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos), - HAL_GPIO_PULL_UP = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) -} hal_gpio_pull_t; - -typedef enum { - HAL_GPIO_MODE_OUTPUT = (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos), - HAL_GPIO_MODE_INPUT = (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos), -} hal_gpio_mode_t; - -static inline void hal_gpio_cfg_pin(uint8_t port, uint32_t pin_number, hal_gpio_mode_t mode, hal_gpio_pull_t pull) { - GPIO_BASE(port)->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | pull - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | mode; -} - -static inline void hal_gpio_out_set(uint8_t port, uint32_t pin_mask) { - GPIO_BASE(port)->OUTSET = pin_mask; -} - -static inline void hal_gpio_pin_set(uint8_t port, uint32_t pin) { - GPIO_BASE(port)->OUTSET = (1 << pin); -} - -static inline void hal_gpio_pin_clear(uint8_t port, uint32_t pin) { - GPIO_BASE(port)->OUTCLR = (1 << pin); -} - -static inline void hal_gpio_pin_toggle(uint8_t port, uint32_t pin) { - uint32_t pin_mask = (1 << pin); - - if (GPIO_BASE(port)->OUT ^ pin_mask) { - GPIO_BASE(port)->OUTSET = pin_mask; - } else { - GPIO_BASE(port)->OUTCLR = pin_mask; - } -} - static inline uint32_t hal_tick_fake(void) { return 0; } @@ -134,9 +56,9 @@ void mp_hal_stdout_tx_str(const char *str); #define mp_hal_pin_obj_t const pin_obj_t* #define mp_hal_get_pin_obj(o) pin_find(o) -#define mp_hal_pin_high(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTSET = (p)->pin_mask) -#define mp_hal_pin_low(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask) -#define mp_hal_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1) +#define mp_hal_pin_high(p) hal_gpio_pin_high(p) +#define mp_hal_pin_low(p) hal_gpio_pin_low(p) +#define mp_hal_pin_read(p) hal_gpio_pin_read(p) #define mp_hal_pin_write(p, v) do { if (v) { mp_hal_pin_high(p); } else { mp_hal_pin_low(p); } } while (0) #define mp_hal_pin_od_low(p) mp_hal_pin_low(p) #define mp_hal_pin_od_high(p) mp_hal_pin_high(p) From 07edf4f26d089725618e7ad416da3739b0fea6f0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 21:49:02 +0200 Subject: [PATCH 582/809] nrf5/hal/gpio: Adding new enumeration for input polarity change events. --- nrf5/hal/hal_gpio.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/nrf5/hal/hal_gpio.h b/nrf5/hal/hal_gpio.h index ca5c8a5028..e9e94efd43 100644 --- a/nrf5/hal/hal_gpio.h +++ b/nrf5/hal/hal_gpio.h @@ -47,6 +47,12 @@ #define hal_gpio_pin_low(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask) #define hal_gpio_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1) +typedef enum { + HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH = GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos, + HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos, + HAL_GPIO_POLARITY_EVENT_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos +} hal_gpio_polarity_event_t; + typedef enum { HAL_GPIO_PULL_DISABLED = (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos), HAL_GPIO_PULL_DOWN = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos), From 32083a94430d22860f2f37b997cb9a4b0d967fae Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 21:50:11 +0200 Subject: [PATCH 583/809] nrf5/modules/machine: Adding new constants to pin object for polarity change triggers using the enumerated values in hal_gpio.h. --- nrf5/modules/machine/pin.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/modules/machine/pin.c b/nrf5/modules/machine/pin.c index b1690c7b5f..bfa06ddfcc 100644 --- a/nrf5/modules/machine/pin.c +++ b/nrf5/modules/machine/pin.c @@ -516,6 +516,11 @@ STATIC const mp_map_elem_t pin_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_UP), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_UP) }, { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DOWN), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_DOWN) }, + // IRQ triggers, can be or'd together + { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_RISING), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_FALLING), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_TOGGLE), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_POLARITY_EVENT_TOGGLE) }, + /* // legacy class constants { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_PP), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) }, From 64461056896ceb59b780b949455d01012b5cbe6d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 21:52:57 +0200 Subject: [PATCH 584/809] nrf5/modules/machine: Removing toggle event trigger as that will be a combination of the rising and falling together. --- nrf5/modules/machine/pin.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/modules/machine/pin.c b/nrf5/modules/machine/pin.c index bfa06ddfcc..d2676a52c2 100644 --- a/nrf5/modules/machine/pin.c +++ b/nrf5/modules/machine/pin.c @@ -519,8 +519,6 @@ STATIC const mp_map_elem_t pin_locals_dict_table[] = { // IRQ triggers, can be or'd together { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_RISING), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH) }, { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_FALLING), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_TOGGLE), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_POLARITY_EVENT_TOGGLE) }, - /* // legacy class constants { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_PP), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) }, From 8c45aca8d2eaba6a3d10ca2b0bed8db249848df5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 21:54:09 +0200 Subject: [PATCH 585/809] nrf5/hal/gpio: Removing toggle event from the enumeration as that will be a combination of the rising and falling together. --- nrf5/hal/hal_gpio.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/nrf5/hal/hal_gpio.h b/nrf5/hal/hal_gpio.h index e9e94efd43..e6eb09cc75 100644 --- a/nrf5/hal/hal_gpio.h +++ b/nrf5/hal/hal_gpio.h @@ -49,8 +49,7 @@ typedef enum { HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH = GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos, - HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos, - HAL_GPIO_POLARITY_EVENT_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos + HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos } hal_gpio_polarity_event_t; typedef enum { From 435bc5a3d4aeecf9864c1cb3e42be10c82ccaea1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 21:56:28 +0200 Subject: [PATCH 586/809] nrf5/hal/gpio: Updating hal_gpio.h with some tab-fixes in order to make the file a bit consistent in style. --- nrf5/hal/hal_gpio.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/nrf5/hal/hal_gpio.h b/nrf5/hal/hal_gpio.h index e6eb09cc75..00438598fc 100644 --- a/nrf5/hal/hal_gpio.h +++ b/nrf5/hal/hal_gpio.h @@ -43,9 +43,9 @@ #define GPIO_BASE(x) ((NRF_GPIO_Type *)POINTERS[x]) -#define hal_gpio_pin_high(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTSET = (p)->pin_mask) -#define hal_gpio_pin_low(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask) -#define hal_gpio_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1) +#define hal_gpio_pin_high(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTSET = (p)->pin_mask) +#define hal_gpio_pin_low(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask) +#define hal_gpio_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1) typedef enum { HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH = GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos, @@ -54,13 +54,13 @@ typedef enum { typedef enum { HAL_GPIO_PULL_DISABLED = (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos), - HAL_GPIO_PULL_DOWN = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos), - HAL_GPIO_PULL_UP = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) + HAL_GPIO_PULL_DOWN = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos), + HAL_GPIO_PULL_UP = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) } hal_gpio_pull_t; typedef enum { HAL_GPIO_MODE_OUTPUT = (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos), - HAL_GPIO_MODE_INPUT = (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos), + HAL_GPIO_MODE_INPUT = (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos), } hal_gpio_mode_t; static inline void hal_gpio_cfg_pin(uint8_t port, uint32_t pin_number, hal_gpio_mode_t mode, hal_gpio_pull_t pull) { From a93d462dfd4a0a94e5e772a3329651d628df0634 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 23:02:37 +0200 Subject: [PATCH 587/809] nrf5/hal/gpio: Reintroducing gpio polarity toggle event to be able to reference the short form of adding high_to_low and low_to_high together. --- nrf5/hal/hal_gpio.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_gpio.h b/nrf5/hal/hal_gpio.h index 00438598fc..bc2b1f24e2 100644 --- a/nrf5/hal/hal_gpio.h +++ b/nrf5/hal/hal_gpio.h @@ -49,7 +49,8 @@ typedef enum { HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH = GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos, - HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos + HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos, + HAL_GPIO_POLARITY_EVENT_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos } hal_gpio_polarity_event_t; typedef enum { From 2c90d94dc74332e42681e72181c1428d41ac294f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 23:16:07 +0200 Subject: [PATCH 588/809] nrf5/modules/machine: Adding pin irq type and basic functions and structures. --- nrf5/modules/machine/pin.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/nrf5/modules/machine/pin.c b/nrf5/modules/machine/pin.c index d2676a52c2..9cc94ad1c5 100644 --- a/nrf5/modules/machine/pin.c +++ b/nrf5/modules/machine/pin.c @@ -613,3 +613,39 @@ const mp_obj_type_t pin_af_type = { .print = pin_af_obj_print, .locals_dict = (mp_obj_t)&pin_af_locals_dict, }; + +/******************************************************************************/ +// Pin IRQ object + +typedef struct _pin_irq_obj_t { + mp_obj_base_t base; + pin_obj_t pin; +} pin_irq_obj_t; + +STATIC const mp_obj_type_t pin_irq_type; + +STATIC mp_obj_t pin_irq_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_obj_t *args) { + pin_irq_obj_t *self = self_in; + (void)self; + return mp_const_none; +} + +STATIC mp_obj_t pin_irq_trigger(size_t n_args, const mp_obj_t *args) { + pin_irq_obj_t *self = args[0]; + (void)self; + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_irq_trigger_obj, 1, 2, pin_irq_trigger); + +STATIC const mp_rom_map_elem_t pin_irq_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_trigger), MP_ROM_PTR(&pin_irq_trigger_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(pin_irq_locals_dict, pin_irq_locals_dict_table); + +STATIC const mp_obj_type_t pin_irq_type = { + { &mp_type_type }, + .name = MP_QSTR_IRQ, + .call = pin_irq_call, + .locals_dict = (mp_obj_dict_t*)&pin_irq_locals_dict, +}; From 320b9ecde769b97623760b33167ff77be7dadfae Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 23:18:00 +0200 Subject: [PATCH 589/809] nrf5/modules/machine: Adding placeholder for irq method to pin object class. --- nrf5/modules/machine/pin.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/nrf5/modules/machine/pin.c b/nrf5/modules/machine/pin.c index 9cc94ad1c5..ed30c98c2a 100644 --- a/nrf5/modules/machine/pin.c +++ b/nrf5/modules/machine/pin.c @@ -478,6 +478,24 @@ STATIC mp_obj_t pin_af(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_obj, pin_af); +STATIC mp_obj_t pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_handler, MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_trigger, MP_ARG_INT, {.u_int = HAL_GPIO_POLARITY_EVENT_TOGGLE} }, + { MP_QSTR_wake, MP_ARG_BOOL, {.u_bool = false} }, + }; + pin_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + (void)self; + + // return the irq object + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pin_irq_obj, 1, pin_irq); + + STATIC const mp_map_elem_t pin_locals_dict_table[] = { // instance methods { MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&pin_init_obj }, @@ -493,6 +511,7 @@ STATIC const mp_map_elem_t pin_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_mode), (mp_obj_t)&pin_mode_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_pull), (mp_obj_t)&pin_pull_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_af), (mp_obj_t)&pin_af_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_irq), (mp_obj_t)&pin_irq_obj }, // class methods { MP_OBJ_NEW_QSTR(MP_QSTR_mapper), (mp_obj_t)&pin_mapper_obj }, From c7c2285ab9e0e520b2affe4fc1e4714280e5fc42 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 23:19:26 +0200 Subject: [PATCH 590/809] nrf5/modules/machine: Style fix in pin object, indention. --- nrf5/modules/machine/pin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/machine/pin.c b/nrf5/modules/machine/pin.c index ed30c98c2a..56aa32b395 100644 --- a/nrf5/modules/machine/pin.c +++ b/nrf5/modules/machine/pin.c @@ -511,7 +511,7 @@ STATIC const mp_map_elem_t pin_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_mode), (mp_obj_t)&pin_mode_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_pull), (mp_obj_t)&pin_pull_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_af), (mp_obj_t)&pin_af_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_irq), (mp_obj_t)&pin_irq_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_irq), (mp_obj_t)&pin_irq_obj }, // class methods { MP_OBJ_NEW_QSTR(MP_QSTR_mapper), (mp_obj_t)&pin_mapper_obj }, From f8c0a51f5ee1e6402e5ebc0e2a61779c3fb84520 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 9 Apr 2017 23:47:44 +0200 Subject: [PATCH 591/809] nrf5/hal/gpio: Adding missing include. --- nrf5/hal/hal_gpio.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/hal/hal_gpio.h b/nrf5/hal/hal_gpio.h index bc2b1f24e2..fadeaee3a0 100644 --- a/nrf5/hal/hal_gpio.h +++ b/nrf5/hal/hal_gpio.h @@ -27,6 +27,8 @@ #ifndef HAL_GPIO_H__ #define HAL_GPIO_H__ +#include "nrf.h" + #if NRF51 #define POINTERS (const uint32_t[]){NRF_GPIO_BASE} #endif From adf316afaa182b80bf5aa59ad98622bcca62bd34 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 11 Apr 2017 13:53:37 +0200 Subject: [PATCH 592/809] nrf5/hal/gpio: Adding some new structures and functions to register irq channels to gpio's using GPIOTE peripheral --- nrf5/hal/hal_gpio.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/nrf5/hal/hal_gpio.h b/nrf5/hal/hal_gpio.h index fadeaee3a0..2cc73a5fe9 100644 --- a/nrf5/hal/hal_gpio.h +++ b/nrf5/hal/hal_gpio.h @@ -96,4 +96,31 @@ static inline void hal_gpio_pin_toggle(uint8_t port, uint32_t pin) { } } +typedef enum { + HAL_GPIO_EVENT_CHANNEL_0 = 0, + HAL_GPIO_EVENT_CHANNEL_1, + HAL_GPIO_EVENT_CHANNEL_2, + HAL_GPIO_EVENT_CHANNEL_3, +#if NRF52 + HAL_GPIO_EVENT_CHANNEL_4, + HAL_GPIO_EVENT_CHANNEL_5, + HAL_GPIO_EVENT_CHANNEL_6, + HAL_GPIO_EVENT_CHANNEL_7 +#endif +} hal_gpio_event_channel_t; + +typedef struct { + hal_gpio_event_channel_t channel; + hal_gpio_polarity_event_t event; + uint32_t pin; + uint8_t port; + uint8_t init_level; +} hal_gpio_event_config_t; + +typedef void (*hal_gpio_event_callback_t)(hal_gpio_event_channel_t channel); + +void hal_gpio_register_callback(hal_gpio_event_callback_t cb); + +void hal_gpio_event_config(hal_gpio_event_config_t const * p_config); + #endif // HAL_GPIO_H__ From fb53bdf07c6cd0c83c6d68a21b12a4bdb455fa39 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 11 Apr 2017 13:55:01 +0200 Subject: [PATCH 593/809] nrf5: Moving initialization of pin til after uart has been initialized for debugging purposes. This will make it possible to use uart to print out debug data when adding gpio irq handlers. --- nrf5/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/main.c b/nrf5/main.c index 24651d3e02..c89afbb8e5 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -102,8 +102,6 @@ int main(int argc, char **argv) { readline_init0(); - pin_init0(); - #if MICROPY_PY_MACHINE_HW_SPI spi_init0(); #endif @@ -141,6 +139,8 @@ int main(int argc, char **argv) { } #endif +pin_init0(); + #if MICROPY_HW_HAS_SDCARD // if an SD card is present then mount it on /sd/ if (sdcard_is_present()) { From 81aaf6e90667af7561efca30bdee3707e2b65d12 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 11 Apr 2017 13:57:44 +0200 Subject: [PATCH 594/809] nrf5/hal/gpio: Adding initial gpiote implementation to handle IRQ on polarity change on a gpio. --- nrf5/hal/hal_gpio.c | 117 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 nrf5/hal/hal_gpio.c diff --git a/nrf5/hal/hal_gpio.c b/nrf5/hal/hal_gpio.c new file mode 100644 index 0000000000..c36ed9905e --- /dev/null +++ b/nrf5/hal/hal_gpio.c @@ -0,0 +1,117 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hal_gpio.h" +#include "mphalport.h" +#include "hal_irq.h" + +#define GPIOTE_IRQ_NUM GPIOTE_IRQn +#define GPIOTE_BASE ((NRF_GPIOTE_Type *)NRF_GPIOTE_BASE) +#define HAL_GPIOTE_Type NRF_GPIOTE_Type + +static hal_gpio_event_callback_t m_callback; + +void hal_gpio_register_callback(hal_gpio_event_callback_t cb) { + m_callback = cb; + +#if 0 + hal_gpio_event_config_t config; + config.channel = HAL_GPIO_EVENT_CHANNEL_0; + config.event = HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW; + config.init_level = 1; + config.pin = 13; + config.port = 0; + + // start LFCLK if not already started + if (NRF_CLOCK->LFCLKSTAT == 0) { + NRF_CLOCK->TASKS_LFCLKSTART = 1; + while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0); + NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; + } + + hal_irq_enable(GPIOTE_IRQ_NUM); + hal_irq_priority(GPIOTE_IRQ_NUM, 3); + + hal_gpio_event_config(&config); +#endif +} + +void hal_gpio_event_config(hal_gpio_event_config_t const * p_config) { +#if 0 + hal_gpio_cfg_pin(p_config->port, p_config->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_UP); + + uint8_t channel = (uint8_t)p_config->channel; + GPIOTE_BASE->CONFIG[channel] = \ + GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos \ + | p_config->pin << GPIOTE_CONFIG_PSEL_Pos \ + | p_config->event \ + | p_config->init_level << GPIOTE_CONFIG_OUTINIT_Pos; + + GPIOTE_BASE->INTENSET = 1 << channel; + GPIOTE_BASE->EVENTS_IN[channel] = 0; +#endif +} + +#if 0 + +void GPIOTE_IRQHandler(void) { + if (GPIOTE_BASE->EVENTS_IN[0]) { + GPIOTE_BASE->EVENTS_IN[0] = 0; + m_callback(HAL_GPIO_EVENT_CHANNEL_0); + } + if (GPIOTE_BASE->EVENTS_IN[1]) { + GPIOTE_BASE->EVENTS_IN[1] = 0; + m_callback(HAL_GPIO_EVENT_CHANNEL_1); + } + if (GPIOTE_BASE->EVENTS_IN[2]) { + GPIOTE_BASE->EVENTS_IN[2] = 0; + m_callback(HAL_GPIO_EVENT_CHANNEL_2); + } + if (GPIOTE_BASE->EVENTS_IN[3]) { + GPIOTE_BASE->EVENTS_IN[3] = 0; + m_callback(HAL_GPIO_EVENT_CHANNEL_3); + } +#if NRF52 + if (GPIOTE_BASE->EVENTS_IN[4]) { + GPIOTE_BASE->EVENTS_IN[4] = 0; + m_callback(HAL_GPIO_EVENT_CHANNEL_4); + } + if (GPIOTE_BASE->EVENTS_IN[5]) { + GPIOTE_BASE->EVENTS_IN[5] = 0; + m_callback(HAL_GPIO_EVENT_CHANNEL_5); + } + if (GPIOTE_BASE->EVENTS_IN[6]) { + GPIOTE_BASE->EVENTS_IN[6] = 0; + m_callback(HAL_GPIO_EVENT_CHANNEL_6); + } + if (GPIOTE_BASE->EVENTS_IN[7]) { + GPIOTE_BASE->EVENTS_IN[7] = 0; + m_callback(HAL_GPIO_EVENT_CHANNEL_7); + } +#endif +} + +#endif // if 0 From 1e79bdf0b424fdc67851d0503a099e63cbfb3e53 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 11 Apr 2017 13:58:58 +0200 Subject: [PATCH 595/809] nrf5/modules/machine: Updating Pin module to register a IRQ callback upon GPIO polarity change events. --- nrf5/modules/machine/pin.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/nrf5/modules/machine/pin.c b/nrf5/modules/machine/pin.c index 56aa32b395..18d86d6e44 100644 --- a/nrf5/modules/machine/pin.c +++ b/nrf5/modules/machine/pin.c @@ -95,10 +95,15 @@ // Pin class variables STATIC bool pin_class_debug; +// Forward declare function +void gpio_irq_event_callback(hal_gpio_event_channel_t channel); + void pin_init0(void) { MP_STATE_PORT(pin_class_mapper) = mp_const_none; MP_STATE_PORT(pin_class_map_dict) = mp_const_none; pin_class_debug = false; + + hal_gpio_register_callback(gpio_irq_event_callback); } // C API used to convert a user-supplied pin name into an ordinal pin number. @@ -636,6 +641,10 @@ const mp_obj_type_t pin_af_type = { /******************************************************************************/ // Pin IRQ object +void gpio_irq_event_callback(hal_gpio_event_channel_t channel) { + // printf("### gpio irq received on channel %d\n", (uint16_t)channel); +} + typedef struct _pin_irq_obj_t { mp_obj_base_t base; pin_obj_t pin; From 2d7f39855be1d5259c073d14ef180b5171534fb9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 11 Apr 2017 13:59:54 +0200 Subject: [PATCH 596/809] nrf5: Adding hal_gpio.c to Makefile's source list. --- nrf5/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 72fd1e5213..9f4b9f33ed 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -118,6 +118,7 @@ SRC_HAL = $(addprefix hal/,\ hal_adc.c \ hal_adce.c \ hal_temp.c \ + hal_gpio.c \ ) ifeq ($(MCU_VARIANT), nrf52) From 4d56f2a76dc230afeeb41f2f7f8df1f7e6672657 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 18 Apr 2017 20:53:55 +0200 Subject: [PATCH 597/809] nrf5/hal/pwm: Adding more configuration options to the PWM peripheral wrapper. Possibility to set pulse with manually, and also mode. The mode indicates whether duty cycle is low and then goes high, or if it is high and then go low. Added new type to describe the two modes. --- nrf5/hal/hal_pwm.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/nrf5/hal/hal_pwm.h b/nrf5/hal/hal_pwm.h index 6837ad4a54..5097763aa4 100644 --- a/nrf5/hal/hal_pwm.h +++ b/nrf5/hal/hal_pwm.h @@ -65,11 +65,22 @@ typedef enum { HAL_PWM_FREQ_125khz } hal_pwm_freq_t; +/** + * @brief PWM mode type definition + */ +typedef enum { + HAL_PWM_MODE_LOW_HIGH = 0, + HAL_PWM_MODE_HIGH_LOW +} hal_pwm_mode_t; + + typedef struct { uint8_t pwm_pin; hal_pwm_freq_t freq; uint8_t duty; + uint16_t pulse_width; uint16_t period; + hal_pwm_mode_t mode; } hal_pwm_init_t; /** From d0d350da16f26dbac104218b4e02ebb9f9cb1205 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 18 Apr 2017 20:56:19 +0200 Subject: [PATCH 598/809] nrf5/hal/pwm: Updating PWM implementation to support manually set duty cycle period. Pulse width has precidence over duty cycle percentage. Also adding support for the two configurable modes, high to low, and low to high, duty cycles. --- nrf5/hal/hal_pwm.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/nrf5/hal/hal_pwm.c b/nrf5/hal/hal_pwm.c index d1c947f796..a0e69f469f 100644 --- a/nrf5/hal/hal_pwm.c +++ b/nrf5/hal/hal_pwm.c @@ -50,10 +50,20 @@ static const uint32_t hal_pwm_frequency_lookup[] = { void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init) { g_pwm_period = p_pwm_init->period; - uint16_t duty_cycle = ((g_pwm_period * p_pwm_init->duty)/100); + uint16_t pulse_width = ((g_pwm_period * p_pwm_init->duty)/100); + + if (p_pwm_init->pulse_width > 0) { + pulse_width = p_pwm_init->pulse_width; + } + + if (p_pwm_init->mode == HAL_PWM_MODE_HIGH_LOW) { + g_pwm_seq[0] = g_pwm_period - pulse_width; + g_pwm_seq[1] = g_pwm_period - pulse_width; + } else { + g_pwm_seq[0] = pulse_width; + g_pwm_seq[1] = pulse_width; + } - g_pwm_seq[0] = duty_cycle; - g_pwm_seq[1] = duty_cycle; g_pwm_seq[2] = 0; g_pwm_seq[3] = 0; From 071e551b791fdb158467700a9ff57c06f72586ea Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 18 Apr 2017 21:00:52 +0200 Subject: [PATCH 599/809] nrf5/modules/machine: Updating PWM module with two new kwargs parameters. One for setting pulse with more fine grained. This value should not exceed the period value. Also, adding support for setting PWM mode, whether it is LOW duty cycle or HIGH duty cycle. By default, high to low is set (this could be changed). --- nrf5/modules/machine/pwm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/nrf5/modules/machine/pwm.c b/nrf5/modules/machine/pwm.c index 2f646d2f11..4b6f1a858d 100644 --- a/nrf5/modules/machine/pwm.c +++ b/nrf5/modules/machine/pwm.c @@ -111,6 +111,8 @@ enum { ARG_NEW_freq, ARG_NEW_period, ARG_NEW_duty, + ARG_NEW_pulse_width, + ARG_NEW_mode }; // for init @@ -137,6 +139,8 @@ STATIC mp_obj_t machine_pwm_make_new(const mp_obj_type_t *type, size_t n_args, s { MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_period, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_duty, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_pulse_width, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, }; // parse args @@ -217,6 +221,7 @@ STATIC const mp_rom_map_elem_t machine_pwm_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_freq), MP_ROM_PTR(&mp_machine_pwm_freq_obj) }, { MP_ROM_QSTR(MP_QSTR_period), MP_ROM_PTR(&mp_machine_pwm_period_obj) }, { MP_ROM_QSTR(MP_QSTR_duty), MP_ROM_PTR(&mp_machine_pwm_duty_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_16MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_16Mhz) }, { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_8MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_8Mhz) }, { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_4MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_4Mhz) }, @@ -225,6 +230,9 @@ STATIC const mp_rom_map_elem_t machine_pwm_locals_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_500KHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_500khz) }, { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_250KHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_250khz) }, { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_125KHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_125khz) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_MODE_LOW_HIGH), MP_OBJ_NEW_SMALL_INT(HAL_PWM_MODE_LOW_HIGH) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_MODE_HIGH_LOW), MP_OBJ_NEW_SMALL_INT(HAL_PWM_MODE_HIGH_LOW) }, }; STATIC MP_DEFINE_CONST_DICT(machine_pwm_locals_dict, machine_pwm_locals_dict_table); @@ -272,6 +280,18 @@ STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args) { self->pyb->pwm->init.duty = 50; // 50% by default. } + if (args[ARG_NEW_pulse_width].u_obj != MP_OBJ_NULL) { + self->pyb->pwm->init.pulse_width = mp_obj_get_int(args[ARG_NEW_pulse_width].u_obj); + } else { + self->pyb->pwm->init.pulse_width = 0; + } + + if (args[ARG_NEW_mode].u_obj != MP_OBJ_NULL) { + self->pyb->pwm->init.mode = mp_obj_get_int(args[ARG_NEW_mode].u_obj); + } else { + self->pyb->pwm->init.mode = HAL_PWM_MODE_HIGH_LOW; + } + hal_pwm_init(self->pyb->pwm->instance, &self->pyb->pwm->init); return MP_OBJ_FROM_PTR(self); From aa32dcd0fd7b52345ac0e356c32508c357cc0a05 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 18 Apr 2017 21:03:14 +0200 Subject: [PATCH 600/809] nrf5/examples: Adding example to show how to use current PWM module to control servo motors. --- nrf5/examples/servo.py | 50 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 nrf5/examples/servo.py diff --git a/nrf5/examples/servo.py b/nrf5/examples/servo.py new file mode 100644 index 0000000000..221ced7111 --- /dev/null +++ b/nrf5/examples/servo.py @@ -0,0 +1,50 @@ +# This file is part of the Micro Python project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2017 Glenn Ruben Bakke +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE + +import time +from machine import PWM, Pin + +class Servo(): + def __init__(self, pin_name=""): + if pin_name: + self.pin = Pin(pin_name, mode=Pin.OUT, pull=Pin.PULL_DOWN) + else: + self.pin = Pin("A22", mode=Pin.OUT, pull=Pin.PULL_DOWN) + def left(self): + p = PWM(0, self.pin, freq=PWM.FREQ_125KHZ, pulse_width=105, period=2500, mode=PWM.MODE_HIGH_LOW) + p.init() + time.sleep_ms(200) + p.deinit() + + def center(self): + p = PWM(0, self.pin, freq=PWM.FREQ_125KHZ, pulse_width=188, period=2500, mode=PWM.MODE_HIGH_LOW) + p.init() + time.sleep_ms(200) + p.deinit() + + def right(self): + p = PWM(0, self.pin, freq=PWM.FREQ_125KHZ, pulse_width=275, period=2500, mode=PWM.MODE_HIGH_LOW) + p.init() + time.sleep_ms(200) + p.deinit() From f6f8097f77fb84d9c9a03f5ab491e29541790ccf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 20 Apr 2017 23:54:10 +0200 Subject: [PATCH 601/809] nrf5/bluetooth: Adding bash script to automate download of bluetooth le stacks --- nrf5/bluetooth/download_ble_stack.sh | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100755 nrf5/bluetooth/download_ble_stack.sh diff --git a/nrf5/bluetooth/download_ble_stack.sh b/nrf5/bluetooth/download_ble_stack.sh new file mode 100755 index 0000000000..83e964df3a --- /dev/null +++ b/nrf5/bluetooth/download_ble_stack.sh @@ -0,0 +1,38 @@ +#!/bin/bash + +function download_s110_nrf51 +{ + echo "### Downloading nrf51_s110 ###" + wget https://developer.nordicsemi.com/nRF5_SDK/nRF51_SDK_v10.x.x/nRF51_SDK_10.0.0_dc26b5e.zip + unzip nRF51_SDK_10.0.0_dc26b5e.zip components/softdevice/s110/* + mv components s110_nrf51 + rm nRF51_SDK_10.0.0_dc26b5e.zip +} + +function download_s132_nrf52 +{ + echo "### Downloading nrf52_s132 ###" + wget https://developer.nordicsemi.com/nRF5_SDK/nRF5_SDK_v12.x.x/nRF5_SDK_12.1.0_0d23e2a.zip + unzip nRF5_SDK_12.1.0_0d23e2a.zip components/softdevice/s132/* + mv components s132_nrf52 + rm nRF5_SDK_12.1.0_0d23e2a.zip +} + +cd bluetooth + +if [ $# -eq 0 ]; then + echo "No Bluetooth LE stack defined, downloading all." + download_s110_nrf51 + download_s132_nrf52 +else + case $1 in + "s110_nrf51" ) + download_s110_nrf51 ;; + "s132_nrf52" ) + download_s132_nrf52 ;; + esac +fi + +cd .. + +exit 0 From 7501ecec8ed5fd3c6e7fddb6a01f9d0d905163c6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 21 Apr 2017 18:23:48 +0200 Subject: [PATCH 602/809] nrf5/bluetooth: Updating Bluetooth LE stack download script. --- nrf5/bluetooth/download_ble_stack.sh | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/nrf5/bluetooth/download_ble_stack.sh b/nrf5/bluetooth/download_ble_stack.sh index 83e964df3a..584b8682ad 100755 --- a/nrf5/bluetooth/download_ble_stack.sh +++ b/nrf5/bluetooth/download_ble_stack.sh @@ -2,7 +2,12 @@ function download_s110_nrf51 { - echo "### Downloading nrf51_s110 ###" + echo "" + echo "##############################" + echo "### Downloading s110_nrf51 ###" + echo "##############################" + echo "" + wget https://developer.nordicsemi.com/nRF5_SDK/nRF51_SDK_v10.x.x/nRF51_SDK_10.0.0_dc26b5e.zip unzip nRF51_SDK_10.0.0_dc26b5e.zip components/softdevice/s110/* mv components s110_nrf51 @@ -11,15 +16,18 @@ function download_s110_nrf51 function download_s132_nrf52 { - echo "### Downloading nrf52_s132 ###" + echo "" + echo "##############################" + echo "### Downloading s132_nrf52 ###" + echo "##############################" + echo "" + wget https://developer.nordicsemi.com/nRF5_SDK/nRF5_SDK_v12.x.x/nRF5_SDK_12.1.0_0d23e2a.zip unzip nRF5_SDK_12.1.0_0d23e2a.zip components/softdevice/s132/* mv components s132_nrf52 rm nRF5_SDK_12.1.0_0d23e2a.zip } -cd bluetooth - if [ $# -eq 0 ]; then echo "No Bluetooth LE stack defined, downloading all." download_s110_nrf51 @@ -33,6 +41,4 @@ else esac fi -cd .. - exit 0 From 10b7f3ef83a0168092848d50f34a616ab27f7447 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 21 Apr 2017 18:46:32 +0200 Subject: [PATCH 603/809] nrf5/bluetooth: Including bluetooth stack version in folder name after download to be able to detect if stack has been updated. --- nrf5/bluetooth/download_ble_stack.sh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/nrf5/bluetooth/download_ble_stack.sh b/nrf5/bluetooth/download_ble_stack.sh index 584b8682ad..0ee433c709 100755 --- a/nrf5/bluetooth/download_ble_stack.sh +++ b/nrf5/bluetooth/download_ble_stack.sh @@ -3,28 +3,28 @@ function download_s110_nrf51 { echo "" - echo "##############################" - echo "### Downloading s110_nrf51 ###" - echo "##############################" + echo "####################################" + echo "### Downloading s110_nrf51_8.0.0 ###" + echo "####################################" echo "" wget https://developer.nordicsemi.com/nRF5_SDK/nRF51_SDK_v10.x.x/nRF51_SDK_10.0.0_dc26b5e.zip unzip nRF51_SDK_10.0.0_dc26b5e.zip components/softdevice/s110/* - mv components s110_nrf51 + mv components s110_nrf51_8.0.0 rm nRF51_SDK_10.0.0_dc26b5e.zip } function download_s132_nrf52 { echo "" - echo "##############################" - echo "### Downloading s132_nrf52 ###" - echo "##############################" + echo "####################################" + echo "### Downloading s132_nrf52_3.0.0 ###" + echo "####################################" echo "" wget https://developer.nordicsemi.com/nRF5_SDK/nRF5_SDK_v12.x.x/nRF5_SDK_12.1.0_0d23e2a.zip unzip nRF5_SDK_12.1.0_0d23e2a.zip components/softdevice/s132/* - mv components s132_nrf52 + mv components s132_nrf52_3.0.0 rm nRF5_SDK_12.1.0_0d23e2a.zip } From a76ff755e36c2a84ac3a33cfbda08614dfea7b01 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 21 Apr 2017 18:55:59 +0200 Subject: [PATCH 604/809] nrf5/bluetooth: Adding back SOFTDEV_HEX as flash tools in main Makefile uses this to locate hex file. --- nrf5/bluetooth/bluetooth_common.mk | 39 +++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/nrf5/bluetooth/bluetooth_common.mk b/nrf5/bluetooth/bluetooth_common.mk index 21aa9bafbe..db31093e00 100644 --- a/nrf5/bluetooth/bluetooth_common.mk +++ b/nrf5/bluetooth/bluetooth_common.mk @@ -1,26 +1,53 @@ SOFTDEV_HEX_NAME ?= +SOFTDEV_HEX_PATH ?= ifeq ($(SD), s110) - INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers + SOFTDEV_VERSION = 8.0.0 + INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/headers CFLAGS += -DBLUETOOTH_SD_DEBUG=1 CFLAGS += -DBLUETOOTH_SD=110 - SOFTDEV_HEX_NAME = s110_nrf51_8.0.0_softdevice.hex + SOFTDEV_HEX_NAME = $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_softdevice.hex + SOFTDEV_HEX_PATH = bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/hex + else ifeq ($(SD), s120) $(error No BLE wrapper available yet) else ifeq ($(SD), s130) $(error No BLE wrapper available yet) else ifeq ($(SD), s132) - INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers - INC += -I$(SDK_ROOT)components/softdevice/$(SD)/headers/$(MCU_VARIANT) + SOFTDEV_VERSION=3.0.0 + INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/headers + INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/headers/$(MCU_VARIANT) CFLAGS += -DBLUETOOTH_SD_DEBUG=1 CFLAGS += -DBLUETOOTH_SD=132 - SOFTDEV_HEX_NAME = s132_nrf52_3.0.0_softdevice.hex + SOFTDEV_HEX_NAME = $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_softdevice.hex + SOFTDEV_HEX_PATH = bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/hex else $(error Incorrect softdevice set flag) endif -SOFTDEV_HEX = $(lastword $(wildcard $(SDK_ROOT)/components/softdevice/$(SD)/hex/$(SOFTDEV_HEX_NAME))) +define STACK_MISSING_ERROR + + +###### ERROR: Bluetooth LE Stack not found ############ +# # +# The build target requires a Bluetooth LE stack. # +# $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION) Bluetooth LE stack not found. # +# # +# Please run the download script: # +# # +# bluetooth/download_ble_stack.sh # +# # +####################################################### + +endef + + +SOFTDEV_HEX = $(SOFTDEV_HEX_PATH)/$(SOFTDEV_HEX_NAME) + +ifeq ($(shell test ! -e $(SOFTDEV_HEX) && echo -n no),no) + $(error $(STACK_MISSING_ERROR)) +endif INC += -I./bluetooth From f6e612f7d7f476b7ed7b217e60c90413fecbf8ae Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 21 Apr 2017 18:58:57 +0200 Subject: [PATCH 605/809] nrf5: Removing SDK_ROOT parameter to Makefile. Bluetooth stacks should be downloaded using the download_ble_stack.sh. The script should be run inside the bluetooth folder to work properly. --- nrf5/Makefile | 8 -------- 1 file changed, 8 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 9f4b9f33ed..84b149c665 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -5,13 +5,6 @@ ifeq ($(wildcard boards/$(BOARD)/.),) $(error Invalid BOARD specified) endif -check_defined = \ - $(strip $(foreach 1,$1, \ - $(call __check_defined,$1,$(strip $(value 2))))) -__check_defined = \ - $(if $(value $1),, \ - $(error Undefined $1$(if $2, ($2)))) - # If SoftDevice is selected, try to use that one. SD ?= SD_LOWER = $(shell echo $(SD) | tr '[:upper:]' '[:lower:]') @@ -25,7 +18,6 @@ ifeq ($(SD), ) include ../py/mkenv.mk include boards/$(BOARD)/mpconfigboard.mk else - $(call check_defined, SDK_ROOT, path to SDK containing softdevice) # If the build directory is not given, make it reflect the board name. BUILD ?= build-$(BOARD)-$(SD_LOWER) include ../py/mkenv.mk From ca43f42b78f86aa1186156426197c66f302045f1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 23 Apr 2017 18:35:31 +0200 Subject: [PATCH 606/809] nrf5/bluetooth: Fixing bug found when testing microbit. Newly introduced advertisment data pointer was not cleared on nrf51 targets. Explicit set to NULL as no additional advertisment data is set. Raises a question on why the nrf51 static variable was not zero initialized. To be checked up. --- nrf5/bluetooth/ble_uart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/bluetooth/ble_uart.c b/nrf5/bluetooth/ble_uart.c index 7789da2f3a..bb5292bf5d 100644 --- a/nrf5/bluetooth/ble_uart.c +++ b/nrf5/bluetooth/ble_uart.c @@ -212,6 +212,7 @@ void ble_uart_init0(void) { m_adv_data_uart_service.p_device_name = (uint8_t *)device_name; m_adv_data_uart_service.device_name_len = strlen(device_name); m_adv_data_uart_service.connectable = true; + m_adv_data_uart_service.p_data = NULL; #if BLUETOOTH_WEBBLUETOOTH_REPL // for now point eddystone URL to https://goo.gl/x46FES => https://glennrub.github.io/webbluetooth/micropython/repl/ From 3f965329524a158a8533c422454081edbed17a0f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 21:46:28 +0200 Subject: [PATCH 607/809] nrf5/bluetooth: Switch over to downloaded bluetooth stacks from nordicsemi.com instead of getting them through the SDK's. This will facilitate download of s132 v2.0.0 later. --- nrf5/bluetooth/bluetooth_common.mk | 10 +++++----- nrf5/bluetooth/download_ble_stack.sh | 23 +++++++++++++++-------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/nrf5/bluetooth/bluetooth_common.mk b/nrf5/bluetooth/bluetooth_common.mk index db31093e00..06e311f3cd 100644 --- a/nrf5/bluetooth/bluetooth_common.mk +++ b/nrf5/bluetooth/bluetooth_common.mk @@ -4,11 +4,11 @@ SOFTDEV_HEX_PATH ?= ifeq ($(SD), s110) SOFTDEV_VERSION = 8.0.0 - INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/headers + INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include CFLAGS += -DBLUETOOTH_SD_DEBUG=1 CFLAGS += -DBLUETOOTH_SD=110 SOFTDEV_HEX_NAME = $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_softdevice.hex - SOFTDEV_HEX_PATH = bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/hex + SOFTDEV_HEX_PATH = bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION) else ifeq ($(SD), s120) $(error No BLE wrapper available yet) @@ -16,12 +16,12 @@ else ifeq ($(SD), s130) $(error No BLE wrapper available yet) else ifeq ($(SD), s132) SOFTDEV_VERSION=3.0.0 - INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/headers - INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/headers/$(MCU_VARIANT) + INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include + INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include/$(MCU_VARIANT) CFLAGS += -DBLUETOOTH_SD_DEBUG=1 CFLAGS += -DBLUETOOTH_SD=132 SOFTDEV_HEX_NAME = $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_softdevice.hex - SOFTDEV_HEX_PATH = bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/softdevice/$(SD)/hex + SOFTDEV_HEX_PATH = bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION) else $(error Incorrect softdevice set flag) endif diff --git a/nrf5/bluetooth/download_ble_stack.sh b/nrf5/bluetooth/download_ble_stack.sh index 0ee433c709..84c9377432 100755 --- a/nrf5/bluetooth/download_ble_stack.sh +++ b/nrf5/bluetooth/download_ble_stack.sh @@ -8,10 +8,13 @@ function download_s110_nrf51 echo "####################################" echo "" - wget https://developer.nordicsemi.com/nRF5_SDK/nRF51_SDK_v10.x.x/nRF51_SDK_10.0.0_dc26b5e.zip - unzip nRF51_SDK_10.0.0_dc26b5e.zip components/softdevice/s110/* - mv components s110_nrf51_8.0.0 - rm nRF51_SDK_10.0.0_dc26b5e.zip + mkdir s110_nrf51_8.0.0 + cd s110_nrf51_8.0.0 + wget https://www.nordicsemi.com/eng/nordic/download_resource/45846/3/78153065/80234 + mv 80234 temp.zip + unzip temp.zip + rm temp.zip + cd - } function download_s132_nrf52 @@ -22,10 +25,14 @@ function download_s132_nrf52 echo "####################################" echo "" - wget https://developer.nordicsemi.com/nRF5_SDK/nRF5_SDK_v12.x.x/nRF5_SDK_12.1.0_0d23e2a.zip - unzip nRF5_SDK_12.1.0_0d23e2a.zip components/softdevice/s132/* - mv components s132_nrf52_3.0.0 - rm nRF5_SDK_12.1.0_0d23e2a.zip + mkdir s132_nrf52_3.0.0 + cd s132_nrf52_3.0.0 + + wget https://www.nordicsemi.com/eng/nordic/download_resource/56261/6/26298825/108144 + mv 108144 temp.zip + unzip temp.zip + rm temp.zip + cd - } if [ $# -eq 0 ]; then From 39d3d7bb280ab62ce7ab8e97ed4058e741f11366 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 21:56:28 +0200 Subject: [PATCH 608/809] nrf5/bluetooth: Add support for downloading s132_2.0.1 bluetooth stack. --- nrf5/bluetooth/download_ble_stack.sh | 43 +++++++++++++++++++++------- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git a/nrf5/bluetooth/download_ble_stack.sh b/nrf5/bluetooth/download_ble_stack.sh index 84c9377432..e142b9f410 100755 --- a/nrf5/bluetooth/download_ble_stack.sh +++ b/nrf5/bluetooth/download_ble_stack.sh @@ -1,6 +1,6 @@ #!/bin/bash -function download_s110_nrf51 +function download_s110_nrf51_8_0_0 { echo "" echo "####################################" @@ -8,16 +8,34 @@ function download_s110_nrf51 echo "####################################" echo "" - mkdir s110_nrf51_8.0.0 + mkdir -p s110_nrf51_8.0.0 cd s110_nrf51_8.0.0 wget https://www.nordicsemi.com/eng/nordic/download_resource/45846/3/78153065/80234 mv 80234 temp.zip - unzip temp.zip + unzip -u temp.zip rm temp.zip cd - } -function download_s132_nrf52 +function download_s132_nrf52_2_0_1 +{ + echo "" + echo "####################################" + echo "### Downloading s132_nrf52_2.0.1 ###" + echo "####################################" + echo "" + + mkdir -p s132_nrf52_2.0.1 + cd s132_nrf52_2.0.1 + + wget https://www.nordicsemi.com/eng/nordic/download_resource/51479/6/84640562/95151 + mv 95151 temp.zip + unzip -u temp.zip + rm temp.zip + cd - +} + +function download_s132_nrf52_3_0_0 { echo "" echo "####################################" @@ -25,26 +43,29 @@ function download_s132_nrf52 echo "####################################" echo "" - mkdir s132_nrf52_3.0.0 + mkdir -p s132_nrf52_3.0.0 cd s132_nrf52_3.0.0 wget https://www.nordicsemi.com/eng/nordic/download_resource/56261/6/26298825/108144 mv 108144 temp.zip - unzip temp.zip + unzip -u temp.zip rm temp.zip cd - } if [ $# -eq 0 ]; then echo "No Bluetooth LE stack defined, downloading all." - download_s110_nrf51 - download_s132_nrf52 + download_s110_nrf51_8_0_0 + download_s132_nrf52_2_0_1 + download_s132_nrf52_3_0_0 else case $1 in "s110_nrf51" ) - download_s110_nrf51 ;; - "s132_nrf52" ) - download_s132_nrf52 ;; + download_s110_nrf51_8_0_0 ;; + "s132_nrf52_2_0_1" ) + download_s132_nrf52_2_0_1 ;; + "s132_nrf52_3_0_0" ) + download_s132_nrf52_3_0_0 ;; esac fi From 582db669b6bcf4230c0cdd82af883f9bb6932cc9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 22:02:41 +0200 Subject: [PATCH 609/809] nrf5/boards: Renaming linker script for nrf52832 using bluetooth stack such that it also holds the version number of the stack. Updating linkerscript using the target linker script. --- ...52832_512k_64k_s132.ld => nrf52832_512k_64k_s132_3.0.0.ld} | 0 nrf5/boards/pca10040/mpconfigboard_s132.mk | 4 +++- 2 files changed, 3 insertions(+), 1 deletion(-) rename nrf5/boards/{nrf52832_512k_64k_s132.ld => nrf52832_512k_64k_s132_3.0.0.ld} (100%) diff --git a/nrf5/boards/nrf52832_512k_64k_s132.ld b/nrf5/boards/nrf52832_512k_64k_s132_3.0.0.ld similarity index 100% rename from nrf5/boards/nrf52832_512k_64k_s132.ld rename to nrf5/boards/nrf52832_512k_64k_s132_3.0.0.ld diff --git a/nrf5/boards/pca10040/mpconfigboard_s132.mk b/nrf5/boards/pca10040/mpconfigboard_s132.mk index 59e03bdb68..3e29e9f087 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s132.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s132.mk @@ -1,6 +1,8 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52832 -LD_FILE = boards/nrf52832_512k_64k_s132.ld +SOFTDEV_VERSION=3.0.0 + +LD_FILE = boards/nrf52832_512k_64k_s132_$(SOFTDEV_VERSION).ld NRF_DEFINES += -DNRF52832_XXAA From bccfc7262d3791e486687f9d5aa00d2ce734c714 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 22:18:46 +0200 Subject: [PATCH 610/809] nrf5/boards: adding some spaces in s132 makefile for pca10040. --- nrf5/boards/pca10040/mpconfigboard_s132.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/pca10040/mpconfigboard_s132.mk b/nrf5/boards/pca10040/mpconfigboard_s132.mk index 3e29e9f087..42d37d38d4 100644 --- a/nrf5/boards/pca10040/mpconfigboard_s132.mk +++ b/nrf5/boards/pca10040/mpconfigboard_s132.mk @@ -1,7 +1,7 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52832 -SOFTDEV_VERSION=3.0.0 +SOFTDEV_VERSION = 3.0.0 LD_FILE = boards/nrf52832_512k_64k_s132_$(SOFTDEV_VERSION).ld From f4fd45bef33460b5183f4beb58d9558f6e74f54d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 22:22:09 +0200 Subject: [PATCH 611/809] nrf5/boards: Renaming bluetooth stack linker scripts to reflect version of the stack. --- ...{nrf51x22_256k_16k_s110.ld => nrf51x22_256k_16k_s110_8.0.0.ld} | 0 ...{nrf51x22_256k_32k_s110.ld => nrf51x22_256k_32k_s110_8.0.0.ld} | 0 ...{nrf51x22_256k_32k_s120.ld => nrf51x22_256k_32k_s120_2.1.0.ld} | 0 ...{nrf51x22_256k_32k_s130.ld => nrf51x22_256k_32k_s130_2.0.1.ld} | 0 4 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/boards/{nrf51x22_256k_16k_s110.ld => nrf51x22_256k_16k_s110_8.0.0.ld} (100%) rename nrf5/boards/{nrf51x22_256k_32k_s110.ld => nrf51x22_256k_32k_s110_8.0.0.ld} (100%) rename nrf5/boards/{nrf51x22_256k_32k_s120.ld => nrf51x22_256k_32k_s120_2.1.0.ld} (100%) rename nrf5/boards/{nrf51x22_256k_32k_s130.ld => nrf51x22_256k_32k_s130_2.0.1.ld} (100%) diff --git a/nrf5/boards/nrf51x22_256k_16k_s110.ld b/nrf5/boards/nrf51x22_256k_16k_s110_8.0.0.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_16k_s110.ld rename to nrf5/boards/nrf51x22_256k_16k_s110_8.0.0.ld diff --git a/nrf5/boards/nrf51x22_256k_32k_s110.ld b/nrf5/boards/nrf51x22_256k_32k_s110_8.0.0.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_32k_s110.ld rename to nrf5/boards/nrf51x22_256k_32k_s110_8.0.0.ld diff --git a/nrf5/boards/nrf51x22_256k_32k_s120.ld b/nrf5/boards/nrf51x22_256k_32k_s120_2.1.0.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_32k_s120.ld rename to nrf5/boards/nrf51x22_256k_32k_s120_2.1.0.ld diff --git a/nrf5/boards/nrf51x22_256k_32k_s130.ld b/nrf5/boards/nrf51x22_256k_32k_s130_2.0.1.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_32k_s130.ld rename to nrf5/boards/nrf51x22_256k_32k_s130_2.0.1.ld From 3c8323aff488387b9eceb8fefb18fc13dd50086b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 22:28:08 +0200 Subject: [PATCH 612/809] nrf5/boards: Updating makefiles using bluetooth stack to use updated linker script file names. --- nrf5/boards/microbit/mpconfigboard_s110.mk | 3 ++- nrf5/boards/pca10000/mpconfigboard_s110.mk | 3 ++- nrf5/boards/pca10001/mpconfigboard_s110.mk | 3 ++- nrf5/boards/pca10028/mpconfigboard_s110.mk | 3 ++- nrf5/boards/pca10028/mpconfigboard_s120.mk | 3 ++- nrf5/boards/pca10028/mpconfigboard_s130.mk | 3 ++- nrf5/boards/pca10031/mpconfigboard_s110.mk | 3 ++- nrf5/boards/pca10031/mpconfigboard_s120.mk | 3 ++- nrf5/boards/pca10031/mpconfigboard_s130.mk | 3 ++- 9 files changed, 18 insertions(+), 9 deletions(-) diff --git a/nrf5/boards/microbit/mpconfigboard_s110.mk b/nrf5/boards/microbit/mpconfigboard_s110.mk index 20b6ca594d..d638b06095 100644 --- a/nrf5/boards/microbit/mpconfigboard_s110.mk +++ b/nrf5/boards/microbit/mpconfigboard_s110.mk @@ -1,7 +1,8 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51x22_256k_16k_s110.ld +SOFTDEV_VERSION = 8.0.0 +LD_FILE = boards/nrf51x22_256k_16k_s110_$(SOFTDEV_VERSION).ld FLASHER = pyocd CFLAGS += -DBLUETOOTH_LFCLK_RC diff --git a/nrf5/boards/pca10000/mpconfigboard_s110.mk b/nrf5/boards/pca10000/mpconfigboard_s110.mk index d96cab63b9..5cd9966f9c 100644 --- a/nrf5/boards/pca10000/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10000/mpconfigboard_s110.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51x22_256k_16k_s110.ld +SOFTDEV_VERSION = 8.0.0 +LD_FILE = boards/nrf51x22_256k_16k_s110_$(SOFTDEV_VERSION).ld diff --git a/nrf5/boards/pca10001/mpconfigboard_s110.mk b/nrf5/boards/pca10001/mpconfigboard_s110.mk index d96cab63b9..5cd9966f9c 100644 --- a/nrf5/boards/pca10001/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10001/mpconfigboard_s110.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51x22_256k_16k_s110.ld +SOFTDEV_VERSION = 8.0.0 +LD_FILE = boards/nrf51x22_256k_16k_s110_$(SOFTDEV_VERSION).ld diff --git a/nrf5/boards/pca10028/mpconfigboard_s110.mk b/nrf5/boards/pca10028/mpconfigboard_s110.mk index a0f6a39f34..6afc1466f4 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s110.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51x22_256k_32k_s110.ld +SOFTDEV_VERSION = 8.0.0 +LD_FILE = boards/nrf51x22_256k_32k_s110_$(SOFTDEV_VERSION).ld diff --git a/nrf5/boards/pca10028/mpconfigboard_s120.mk b/nrf5/boards/pca10028/mpconfigboard_s120.mk index 10930317a1..97843f8f71 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s120.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51x22_256k_32k_s120.ld +SOFTDEV_VERSION = 2.1.0 +LD_FILE = boards/nrf51x22_256k_32k_s120_$(SOFTDEV_VERSION).ld diff --git a/nrf5/boards/pca10028/mpconfigboard_s130.mk b/nrf5/boards/pca10028/mpconfigboard_s130.mk index 77b8add56d..908549afdc 100644 --- a/nrf5/boards/pca10028/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10028/mpconfigboard_s130.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51x22_256k_32k_s130.ld +SOFTDEV_VERSION = 2.0.1 +LD_FILE = boards/nrf51x22_256k_32k_s130_$(SOFTDEV_VERSION).ld diff --git a/nrf5/boards/pca10031/mpconfigboard_s110.mk b/nrf5/boards/pca10031/mpconfigboard_s110.mk index a0f6a39f34..6afc1466f4 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s110.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s110.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51x22_256k_32k_s110.ld +SOFTDEV_VERSION = 8.0.0 +LD_FILE = boards/nrf51x22_256k_32k_s110_$(SOFTDEV_VERSION).ld diff --git a/nrf5/boards/pca10031/mpconfigboard_s120.mk b/nrf5/boards/pca10031/mpconfigboard_s120.mk index 8422010a49..97843f8f71 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s120.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s120.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51x22_256k_32k_s120.ld \ No newline at end of file +SOFTDEV_VERSION = 2.1.0 +LD_FILE = boards/nrf51x22_256k_32k_s120_$(SOFTDEV_VERSION).ld diff --git a/nrf5/boards/pca10031/mpconfigboard_s130.mk b/nrf5/boards/pca10031/mpconfigboard_s130.mk index 77b8add56d..908549afdc 100644 --- a/nrf5/boards/pca10031/mpconfigboard_s130.mk +++ b/nrf5/boards/pca10031/mpconfigboard_s130.mk @@ -1,4 +1,5 @@ MCU_SERIES = m0 MCU_VARIANT = nrf51 MCU_SUB_VARIANT = nrf51822 -LD_FILE = boards/nrf51x22_256k_32k_s130.ld +SOFTDEV_VERSION = 2.0.1 +LD_FILE = boards/nrf51x22_256k_32k_s130_$(SOFTDEV_VERSION).ld From 9abd38a3f2c54e14d51592821c6c9f37274dd4f7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 22:29:48 +0200 Subject: [PATCH 613/809] nrf5/bluetooth: Remove hardcoded softdevice version as this now comes as parameter from board makefile. --- nrf5/bluetooth/bluetooth_common.mk | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/bluetooth/bluetooth_common.mk b/nrf5/bluetooth/bluetooth_common.mk index 06e311f3cd..94ed916414 100644 --- a/nrf5/bluetooth/bluetooth_common.mk +++ b/nrf5/bluetooth/bluetooth_common.mk @@ -3,7 +3,6 @@ SOFTDEV_HEX_NAME ?= SOFTDEV_HEX_PATH ?= ifeq ($(SD), s110) - SOFTDEV_VERSION = 8.0.0 INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include CFLAGS += -DBLUETOOTH_SD_DEBUG=1 CFLAGS += -DBLUETOOTH_SD=110 @@ -15,7 +14,6 @@ else ifeq ($(SD), s120) else ifeq ($(SD), s130) $(error No BLE wrapper available yet) else ifeq ($(SD), s132) - SOFTDEV_VERSION=3.0.0 INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include/$(MCU_VARIANT) CFLAGS += -DBLUETOOTH_SD_DEBUG=1 From 2adad5f2a61c59e62238d12d8eb5b9f4a24bab9b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 23:03:54 +0200 Subject: [PATCH 614/809] nrf5/bluetooth: Add new compiler flag to signal API variants of the s132 bluetooth le stack. The version is derived from the major number of the stack name. --- nrf5/bluetooth/bluetooth_common.mk | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/nrf5/bluetooth/bluetooth_common.mk b/nrf5/bluetooth/bluetooth_common.mk index 94ed916414..f06190bee9 100644 --- a/nrf5/bluetooth/bluetooth_common.mk +++ b/nrf5/bluetooth/bluetooth_common.mk @@ -18,6 +18,13 @@ else ifeq ($(SD), s132) INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include/$(MCU_VARIANT) CFLAGS += -DBLUETOOTH_SD_DEBUG=1 CFLAGS += -DBLUETOOTH_SD=132 + +ifeq ($(SOFTDEV_VERSION), 2.0.1) + CFLAGS += -DBLE_API_VERSION=2 +else ifeq ($(SOFTDEV_vERSION), 3.0.0) + CFLAGS += -DBLE_API_VERSION=3 +endif + SOFTDEV_HEX_NAME = $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_softdevice.hex SOFTDEV_HEX_PATH = bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION) else From f68fb8499debc5260a2a79e9253f4873ae1edbba Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 23:05:08 +0200 Subject: [PATCH 615/809] nrf5/bluetooth: Updating bluetooth le driver to compile with s132 v.2.0.1 stack. --- nrf5/bluetooth/ble_drv.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 89daf06e1a..45338c42df 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -223,10 +223,10 @@ void ble_drv_address_get(ble_drv_addr_t * p_addr) { SD_TEST_OR_ENABLE(); ble_gap_addr_t local_ble_addr; -#if (BLUETOOTH_SD != 132) - uint32_t err_code = sd_ble_gap_address_get(&local_ble_addr); -#else +#if (BLUETOOTH_SD == 132 && BLE_API_VERSION == 3) uint32_t err_code = sd_ble_gap_addr_get(&local_ble_addr); +#else + uint32_t err_code = sd_ble_gap_address_get(&local_ble_addr); #endif if (err_code != 0) { @@ -694,7 +694,7 @@ void ble_drv_scan_start(void) { #if (BLUETOOTH_SD == 130) scan_params.selective = 0; scan_params.p_whitelist = NULL; -#else +#elif (BLUETOOTH_SD == 132 && BLE_API_VERSION == 3) scan_params.use_whitelist = 0; #endif @@ -721,7 +721,7 @@ void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) { #if (BLUETOOTH_SD == 130) scan_params.selective = 0; scan_params.p_whitelist = NULL; -#else +#elif (BLUETOOTH_SD == 132 && BLE_API_VERSION == 3) scan_params.use_whitelist = 0; #endif @@ -857,7 +857,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { (void)sd_ble_gatts_sys_attr_set(p_ble_evt->evt.gatts_evt.conn_handle, NULL, 0, 0); break; -#if (BLUETOOTH_SD == 132) +#if (BLUETOOTH_SD == 132 && BLE_API_VERSION == 3) case BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST: BLE_DRIVER_LOG("GATTS EVT EXCHANGE MTU REQUEST\n"); (void)sd_ble_gatts_exchange_mtu_reply(p_ble_evt->evt.gatts_evt.conn_handle, 23); // MAX MTU size From 44fc96c8a9f6985ba37cc0273b3f9a6dbebc53ce Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 23:14:04 +0200 Subject: [PATCH 616/809] nrf5/bluetooth: Correcting typo in test where s132 API version is settled. --- nrf5/bluetooth/bluetooth_common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/bluetooth/bluetooth_common.mk b/nrf5/bluetooth/bluetooth_common.mk index f06190bee9..0c1b8fabf2 100644 --- a/nrf5/bluetooth/bluetooth_common.mk +++ b/nrf5/bluetooth/bluetooth_common.mk @@ -21,7 +21,7 @@ else ifeq ($(SD), s132) ifeq ($(SOFTDEV_VERSION), 2.0.1) CFLAGS += -DBLE_API_VERSION=2 -else ifeq ($(SOFTDEV_vERSION), 3.0.0) +else ifeq ($(SOFTDEV_VERSION), 3.0.0) CFLAGS += -DBLE_API_VERSION=3 endif From 0ba9c62940a1a65f6673531dfe25a5dc0a992c03 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 23:25:09 +0200 Subject: [PATCH 617/809] nrf5/boards: Adding template board makefiles and configs for bluefruit nrf52 feather. Copied from pca10040 target board. Linker script reference updated to use s132 v2.0.1. Non-BLE enable build disabled for now. Board configuration for leds, uart etc has not been updated yet from pca10040 layout. --- nrf5/boards/bluefruit_feather/mpconfigboard.h | 78 +++++++++++++++++++ .../boards/bluefruit_feather/mpconfigboard.mk | 13 ++++ .../bluefruit_feather/mpconfigboard_s132.mk | 8 ++ .../boards/bluefruit_feather/nrf52_hal_conf.h | 17 ++++ nrf5/boards/bluefruit_feather/pins.csv | 30 +++++++ 5 files changed, 146 insertions(+) create mode 100644 nrf5/boards/bluefruit_feather/mpconfigboard.h create mode 100644 nrf5/boards/bluefruit_feather/mpconfigboard.mk create mode 100644 nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk create mode 100644 nrf5/boards/bluefruit_feather/nrf52_hal_conf.h create mode 100644 nrf5/boards/bluefruit_feather/pins.csv diff --git a/nrf5/boards/bluefruit_feather/mpconfigboard.h b/nrf5/boards/bluefruit_feather/mpconfigboard.h new file mode 100644 index 0000000000..50b3da7fc3 --- /dev/null +++ b/nrf5/boards/bluefruit_feather/mpconfigboard.h @@ -0,0 +1,78 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define PCA10040 + +#define MICROPY_HW_BOARD_NAME "PCA10040" +#define MICROPY_HW_MCU_NAME "NRF52832" +#define MICROPY_PY_SYS_PLATFORM "nrf52-DK" + +#define MICROPY_PY_MACHINE_PWM (1) +#define MICROPY_PY_MACHINE_HW_SPI (1) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) +#define MICROPY_PY_MACHINE_TEMP (1) + +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_PULLUP (1) + +#define MICROPY_HW_LED1 (17) // LED1 +#define MICROPY_HW_LED2 (18) // LED2 +#define MICROPY_HW_LED3 (19) // LED3 +#define MICROPY_HW_LED4 (20) // LED4 + +// UART config +#define MICROPY_HW_UART1_RX (pin_A8) +#define MICROPY_HW_UART1_TX (pin_A6) +#define MICROPY_HW_UART1_CTS (pin_A7) +#define MICROPY_HW_UART1_RTS (pin_A5) +#define MICROPY_HW_UART1_HWFC (1) + +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (pin_A25) // (Arduino D13) +#define MICROPY_HW_SPI0_MOSI (pin_A23) // (Arduino D11) +#define MICROPY_HW_SPI0_MISO (pin_A24) // (Arduino D12) + +#define MICROPY_HW_PWM0_NAME "PWM0" +#define MICROPY_HW_PWM1_NAME "PWM1" +#define MICROPY_HW_PWM2_NAME "PWM2" + +#define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/bluefruit_feather/mpconfigboard.mk b/nrf5/boards/bluefruit_feather/mpconfigboard.mk new file mode 100644 index 0000000000..84906b78ee --- /dev/null +++ b/nrf5/boards/bluefruit_feather/mpconfigboard.mk @@ -0,0 +1,13 @@ + +define HELPER + +######################################################### +# # +# Use SD=s132 make flag to generate a firmware suitable # +# for bluefruit nrf52 feather. # +# # +######################################################### + +endef + +$(error $(HELPER)) diff --git a/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk b/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk new file mode 100644 index 0000000000..88ef2e41cb --- /dev/null +++ b/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk @@ -0,0 +1,8 @@ +MCU_SERIES = m4 +MCU_VARIANT = nrf52 +MCU_SUB_VARIANT = nrf52832 +SOFTDEV_VERSION = 2.0.1 + +LD_FILE = boards/nrf52832_512k_64k_s132_$(SOFTDEV_VERSION).ld + +NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf5/boards/bluefruit_feather/nrf52_hal_conf.h b/nrf5/boards/bluefruit_feather/nrf52_hal_conf.h new file mode 100644 index 0000000000..585506b8d6 --- /dev/null +++ b/nrf5/boards/bluefruit_feather/nrf52_hal_conf.h @@ -0,0 +1,17 @@ +#ifndef NRF52_HAL_CONF_H__ +#define NRF52_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED +#define HAL_PWM_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED +#define HAL_ADCE_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED +// #define HAL_UARTE_MODULE_ENABLED +// #define HAL_SPIE_MODULE_ENABLED +// #define HAL_TWIE_MODULE_ENABLED + +#endif // NRF52_HAL_CONF_H__ diff --git a/nrf5/boards/bluefruit_feather/pins.csv b/nrf5/boards/bluefruit_feather/pins.csv new file mode 100644 index 0000000000..c177133983 --- /dev/null +++ b/nrf5/boards/bluefruit_feather/pins.csv @@ -0,0 +1,30 @@ +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA5,PA5 +PA6,PA6 +PA7,PA7 +PA8,PA8 +PA9,PA9 +PA10,PA10 +PA11,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 \ No newline at end of file From ec6502c1ea2b97688a8e3ca6c4142e331c99adb6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 24 Apr 2017 23:29:05 +0200 Subject: [PATCH 618/809] nrf5/boards: Adding linker script for nrf52832 s132 v.2.0.1. --- nrf5/boards/nrf52832_512k_64k_s132_2.0.1.ld | 27 +++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 nrf5/boards/nrf52832_512k_64k_s132_2.0.1.ld diff --git a/nrf5/boards/nrf52832_512k_64k_s132_2.0.1.ld b/nrf5/boards/nrf52832_512k_64k_s132_2.0.1.ld new file mode 100644 index 0000000000..05e1daa896 --- /dev/null +++ b/nrf5/boards/nrf52832_512k_64k_s132_2.0.1.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for NRF52 w/ s132 2.0.1 SoftDevice +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x0001c000, LENGTH = 0x001000 /* sector 0, 4 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x0001d000, LENGTH = 0x060000 /* 396 KiB */ + RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 49.5 KiB, give 8KiB headroom for softdevice */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20007000; /* tunable */ + +INCLUDE "boards/common.ld" From 7043680f1ff6fa4beabff30368dfa4ada6d1be40 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 25 Apr 2017 08:49:18 +0200 Subject: [PATCH 619/809] nrf5/boards: Adding custom linker script for adafruit nrf52 bluefruit feather to be able to detect application upper boundry in flash. Pointing s132 mk file to use this new custom linker script instead of the generic s132 v2 linker script. --- .../bluefruit_feather/custom_nrf52832_app.ld | 27 +++++++++++++++++++ .../bluefruit_feather/mpconfigboard_s132.mk | 2 +- 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 nrf5/boards/bluefruit_feather/custom_nrf52832_app.ld diff --git a/nrf5/boards/bluefruit_feather/custom_nrf52832_app.ld b/nrf5/boards/bluefruit_feather/custom_nrf52832_app.ld new file mode 100644 index 0000000000..b868fdaae6 --- /dev/null +++ b/nrf5/boards/bluefruit_feather/custom_nrf52832_app.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for NRF52 w/ s132 2.0.1 SoftDevice +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */ + FLASH_ISR (rx) : ORIGIN = 0x0001f000, LENGTH = 0x001000 /* sector 0, 4 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x026000 /* 152 KiB - APP - ISR */ + RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 49.5 KiB, give 8KiB headroom for softdevice */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* top end of the stack */ + +/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_end = 0x20007000; /* tunable */ + +INCLUDE "boards/common.ld" diff --git a/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk b/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk index 88ef2e41cb..33e9573d0e 100644 --- a/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk +++ b/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk @@ -3,6 +3,6 @@ MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52832 SOFTDEV_VERSION = 2.0.1 -LD_FILE = boards/nrf52832_512k_64k_s132_$(SOFTDEV_VERSION).ld +LD_FILE = boards/bluefruit_feather/custom_nrf52832_app.ld NRF_DEFINES += -DNRF52832_XXAA From 8429d022e1aabf55542cdafc93f05fc688e0c572 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 25 Apr 2017 08:53:27 +0200 Subject: [PATCH 620/809] nrf5/boards: Renaming custom linker script for bluefruit feather to reflect that the purpose of the custom linker script is DFU. The script is diverging from the generic s132 v2 linker script in the offset of the application. --- .../{custom_nrf52832_app.ld => custom_nrf52832_dfu_app.ld} | 0 nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename nrf5/boards/bluefruit_feather/{custom_nrf52832_app.ld => custom_nrf52832_dfu_app.ld} (100%) diff --git a/nrf5/boards/bluefruit_feather/custom_nrf52832_app.ld b/nrf5/boards/bluefruit_feather/custom_nrf52832_dfu_app.ld similarity index 100% rename from nrf5/boards/bluefruit_feather/custom_nrf52832_app.ld rename to nrf5/boards/bluefruit_feather/custom_nrf52832_dfu_app.ld diff --git a/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk b/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk index 33e9573d0e..1c1eb88711 100644 --- a/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk +++ b/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk @@ -3,6 +3,6 @@ MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52832 SOFTDEV_VERSION = 2.0.1 -LD_FILE = boards/bluefruit_feather/custom_nrf52832_app.ld +LD_FILE = boards/bluefruit_feather/custom_nrf52832_dfu_app.ld NRF_DEFINES += -DNRF52832_XXAA From 195c492419c64d358ed506edb8b6b6eefdb9f9fd Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 25 Apr 2017 21:44:01 +0200 Subject: [PATCH 621/809] nrf5/boards: Updating adafruit bluefruit nrf52 feather linker script to use 0x1c000 application offset. --- nrf5/boards/bluefruit_feather/custom_nrf52832_dfu_app.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/boards/bluefruit_feather/custom_nrf52832_dfu_app.ld b/nrf5/boards/bluefruit_feather/custom_nrf52832_dfu_app.ld index b868fdaae6..b2b785e3d8 100644 --- a/nrf5/boards/bluefruit_feather/custom_nrf52832_dfu_app.ld +++ b/nrf5/boards/bluefruit_feather/custom_nrf52832_dfu_app.ld @@ -6,8 +6,8 @@ MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */ - FLASH_ISR (rx) : ORIGIN = 0x0001f000, LENGTH = 0x001000 /* sector 0, 4 KiB */ - FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x026000 /* 152 KiB - APP - ISR */ + FLASH_ISR (rx) : ORIGIN = 0x0001c000, LENGTH = 0x001000 /* sector 0, 4 KiB */ + FLASH_TEXT (rx) : ORIGIN = 0x0001d000, LENGTH = 0x026000 /* 152 KiB - APP - ISR */ RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 49.5 KiB, give 8KiB headroom for softdevice */ } From 8aa6e0388ef92e666e5081c383e9eb131b339fcb Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 25 Apr 2017 21:48:01 +0200 Subject: [PATCH 622/809] nrf5/boards: Updating mpconfigboard.h for bluefruit nrf52 feather with correct board, mcu and platform name. --- nrf5/boards/bluefruit_feather/mpconfigboard.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/boards/bluefruit_feather/mpconfigboard.h b/nrf5/boards/bluefruit_feather/mpconfigboard.h index 50b3da7fc3..c7d80ccfa5 100644 --- a/nrf5/boards/bluefruit_feather/mpconfigboard.h +++ b/nrf5/boards/bluefruit_feather/mpconfigboard.h @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2016 Glenn Ruben Bakke + * Copyright (c) 2017 Glenn Ruben Bakke * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,9 +26,9 @@ #define PCA10040 -#define MICROPY_HW_BOARD_NAME "PCA10040" +#define MICROPY_HW_BOARD_NAME "Bluefruit nRF52 Feather" #define MICROPY_HW_MCU_NAME "NRF52832" -#define MICROPY_PY_SYS_PLATFORM "nrf52-DK" +#define MICROPY_PY_SYS_PLATFORM "nrf52" #define MICROPY_PY_MACHINE_PWM (1) #define MICROPY_PY_MACHINE_HW_SPI (1) From 4ae600be8a56c0a7b569eb229cbb25b16c61172b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 25 Apr 2017 21:49:17 +0200 Subject: [PATCH 623/809] nrf5/boards: Renaming bluefruit_feather to bluefruit_nrf52_feather as it also exist a m0 variant of the board name. --- .../custom_nrf52832_dfu_app.ld | 0 .../mpconfigboard.h | 0 .../mpconfigboard.mk | 0 .../mpconfigboard_s132.mk | 0 .../nrf52_hal_conf.h | 0 .../{bluefruit_feather => bluefruit_nrf52_feather}/pins.csv | 0 6 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/boards/{bluefruit_feather => bluefruit_nrf52_feather}/custom_nrf52832_dfu_app.ld (100%) rename nrf5/boards/{bluefruit_feather => bluefruit_nrf52_feather}/mpconfigboard.h (100%) rename nrf5/boards/{bluefruit_feather => bluefruit_nrf52_feather}/mpconfigboard.mk (100%) rename nrf5/boards/{bluefruit_feather => bluefruit_nrf52_feather}/mpconfigboard_s132.mk (100%) rename nrf5/boards/{bluefruit_feather => bluefruit_nrf52_feather}/nrf52_hal_conf.h (100%) rename nrf5/boards/{bluefruit_feather => bluefruit_nrf52_feather}/pins.csv (100%) diff --git a/nrf5/boards/bluefruit_feather/custom_nrf52832_dfu_app.ld b/nrf5/boards/bluefruit_nrf52_feather/custom_nrf52832_dfu_app.ld similarity index 100% rename from nrf5/boards/bluefruit_feather/custom_nrf52832_dfu_app.ld rename to nrf5/boards/bluefruit_nrf52_feather/custom_nrf52832_dfu_app.ld diff --git a/nrf5/boards/bluefruit_feather/mpconfigboard.h b/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard.h similarity index 100% rename from nrf5/boards/bluefruit_feather/mpconfigboard.h rename to nrf5/boards/bluefruit_nrf52_feather/mpconfigboard.h diff --git a/nrf5/boards/bluefruit_feather/mpconfigboard.mk b/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard.mk similarity index 100% rename from nrf5/boards/bluefruit_feather/mpconfigboard.mk rename to nrf5/boards/bluefruit_nrf52_feather/mpconfigboard.mk diff --git a/nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk b/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard_s132.mk similarity index 100% rename from nrf5/boards/bluefruit_feather/mpconfigboard_s132.mk rename to nrf5/boards/bluefruit_nrf52_feather/mpconfigboard_s132.mk diff --git a/nrf5/boards/bluefruit_feather/nrf52_hal_conf.h b/nrf5/boards/bluefruit_nrf52_feather/nrf52_hal_conf.h similarity index 100% rename from nrf5/boards/bluefruit_feather/nrf52_hal_conf.h rename to nrf5/boards/bluefruit_nrf52_feather/nrf52_hal_conf.h diff --git a/nrf5/boards/bluefruit_feather/pins.csv b/nrf5/boards/bluefruit_nrf52_feather/pins.csv similarity index 100% rename from nrf5/boards/bluefruit_feather/pins.csv rename to nrf5/boards/bluefruit_nrf52_feather/pins.csv From 6f6c5d30e86852a0cd6f0b053e841e19b5030ce1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 25 Apr 2017 21:51:10 +0200 Subject: [PATCH 624/809] nrf5/boards: Updating path to custom bluefruit feather linker script after renaming board folder. --- nrf5/boards/bluefruit_nrf52_feather/mpconfigboard_s132.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard_s132.mk b/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard_s132.mk index 1c1eb88711..cfdb94efdd 100644 --- a/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard_s132.mk +++ b/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard_s132.mk @@ -3,6 +3,6 @@ MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52832 SOFTDEV_VERSION = 2.0.1 -LD_FILE = boards/bluefruit_feather/custom_nrf52832_dfu_app.ld +LD_FILE = boards/bluefruit_nrf52_feather/custom_nrf52832_dfu_app.ld NRF_DEFINES += -DNRF52832_XXAA From 50bb18015aa7cd4305706aee1bb1f328db9a5cd0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 25 Apr 2017 21:54:35 +0200 Subject: [PATCH 625/809] nrf5/boards: Renaming bluefruit_nrf52_feather to feather52 to shorten down the name quite drastically. --- .../custom_nrf52832_dfu_app.ld | 0 .../boards/{bluefruit_nrf52_feather => feather52}/mpconfigboard.h | 0 .../{bluefruit_nrf52_feather => feather52}/mpconfigboard.mk | 0 .../{bluefruit_nrf52_feather => feather52}/mpconfigboard_s132.mk | 0 .../{bluefruit_nrf52_feather => feather52}/nrf52_hal_conf.h | 0 nrf5/boards/{bluefruit_nrf52_feather => feather52}/pins.csv | 0 6 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/boards/{bluefruit_nrf52_feather => feather52}/custom_nrf52832_dfu_app.ld (100%) rename nrf5/boards/{bluefruit_nrf52_feather => feather52}/mpconfigboard.h (100%) rename nrf5/boards/{bluefruit_nrf52_feather => feather52}/mpconfigboard.mk (100%) rename nrf5/boards/{bluefruit_nrf52_feather => feather52}/mpconfigboard_s132.mk (100%) rename nrf5/boards/{bluefruit_nrf52_feather => feather52}/nrf52_hal_conf.h (100%) rename nrf5/boards/{bluefruit_nrf52_feather => feather52}/pins.csv (100%) diff --git a/nrf5/boards/bluefruit_nrf52_feather/custom_nrf52832_dfu_app.ld b/nrf5/boards/feather52/custom_nrf52832_dfu_app.ld similarity index 100% rename from nrf5/boards/bluefruit_nrf52_feather/custom_nrf52832_dfu_app.ld rename to nrf5/boards/feather52/custom_nrf52832_dfu_app.ld diff --git a/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard.h b/nrf5/boards/feather52/mpconfigboard.h similarity index 100% rename from nrf5/boards/bluefruit_nrf52_feather/mpconfigboard.h rename to nrf5/boards/feather52/mpconfigboard.h diff --git a/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard.mk b/nrf5/boards/feather52/mpconfigboard.mk similarity index 100% rename from nrf5/boards/bluefruit_nrf52_feather/mpconfigboard.mk rename to nrf5/boards/feather52/mpconfigboard.mk diff --git a/nrf5/boards/bluefruit_nrf52_feather/mpconfigboard_s132.mk b/nrf5/boards/feather52/mpconfigboard_s132.mk similarity index 100% rename from nrf5/boards/bluefruit_nrf52_feather/mpconfigboard_s132.mk rename to nrf5/boards/feather52/mpconfigboard_s132.mk diff --git a/nrf5/boards/bluefruit_nrf52_feather/nrf52_hal_conf.h b/nrf5/boards/feather52/nrf52_hal_conf.h similarity index 100% rename from nrf5/boards/bluefruit_nrf52_feather/nrf52_hal_conf.h rename to nrf5/boards/feather52/nrf52_hal_conf.h diff --git a/nrf5/boards/bluefruit_nrf52_feather/pins.csv b/nrf5/boards/feather52/pins.csv similarity index 100% rename from nrf5/boards/bluefruit_nrf52_feather/pins.csv rename to nrf5/boards/feather52/pins.csv From 5f4798b0f2494bb65870eda9aabc88b439a5e587 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 25 Apr 2017 21:55:50 +0200 Subject: [PATCH 626/809] nrf5/boards: Updating path to custom linker script for feather52 board. --- nrf5/boards/feather52/mpconfigboard_s132.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/feather52/mpconfigboard_s132.mk b/nrf5/boards/feather52/mpconfigboard_s132.mk index cfdb94efdd..17dda95899 100644 --- a/nrf5/boards/feather52/mpconfigboard_s132.mk +++ b/nrf5/boards/feather52/mpconfigboard_s132.mk @@ -3,6 +3,6 @@ MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52832 SOFTDEV_VERSION = 2.0.1 -LD_FILE = boards/bluefruit_nrf52_feather/custom_nrf52832_dfu_app.ld +LD_FILE = boards/feather52/custom_nrf52832_dfu_app.ld NRF_DEFINES += -DNRF52832_XXAA From 3286d81a48a4a5874f9d2478826bd9176189b2db Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 26 Apr 2017 00:15:14 +0200 Subject: [PATCH 627/809] nrf5/boards: Updating feather52 mpconfigboard.h to use correct uart pins, flow control disabled. Also adjusting leds down to two leds. --- nrf5/boards/feather52/mpconfigboard.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/nrf5/boards/feather52/mpconfigboard.h b/nrf5/boards/feather52/mpconfigboard.h index c7d80ccfa5..3116078641 100644 --- a/nrf5/boards/feather52/mpconfigboard.h +++ b/nrf5/boards/feather52/mpconfigboard.h @@ -51,19 +51,16 @@ #define MICROPY_HW_ENABLE_DAC (0) #define MICROPY_HW_ENABLE_CAN (0) +#define MICROPY_HW_LED_COUNT (2) #define MICROPY_HW_LED_PULLUP (1) #define MICROPY_HW_LED1 (17) // LED1 -#define MICROPY_HW_LED2 (18) // LED2 -#define MICROPY_HW_LED3 (19) // LED3 -#define MICROPY_HW_LED4 (20) // LED4 +#define MICROPY_HW_LED2 (19) // LED2 // UART config #define MICROPY_HW_UART1_RX (pin_A8) #define MICROPY_HW_UART1_TX (pin_A6) -#define MICROPY_HW_UART1_CTS (pin_A7) -#define MICROPY_HW_UART1_RTS (pin_A5) -#define MICROPY_HW_UART1_HWFC (1) +#define MICROPY_HW_UART1_HWFC (0) // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" @@ -75,4 +72,4 @@ #define MICROPY_HW_PWM1_NAME "PWM1" #define MICROPY_HW_PWM2_NAME "PWM2" -#define HELP_TEXT_BOARD_LED "1,2,3,4" +#define HELP_TEXT_BOARD_LED "1,2" From 97d46bae6a0dca2f8829044dd27052df230c4c3f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 26 Apr 2017 00:16:14 +0200 Subject: [PATCH 628/809] nrf5/boards: decrease size of ISR region from 4k to 1k in custom feather52 linker script to get some more flash space. --- nrf5/boards/feather52/custom_nrf52832_dfu_app.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/feather52/custom_nrf52832_dfu_app.ld b/nrf5/boards/feather52/custom_nrf52832_dfu_app.ld index b2b785e3d8..de737e1584 100644 --- a/nrf5/boards/feather52/custom_nrf52832_dfu_app.ld +++ b/nrf5/boards/feather52/custom_nrf52832_dfu_app.ld @@ -7,7 +7,7 @@ MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */ FLASH_ISR (rx) : ORIGIN = 0x0001c000, LENGTH = 0x001000 /* sector 0, 4 KiB */ - FLASH_TEXT (rx) : ORIGIN = 0x0001d000, LENGTH = 0x026000 /* 152 KiB - APP - ISR */ + FLASH_TEXT (rx) : ORIGIN = 0x0001c400, LENGTH = 0x026c00 /* 152 KiB - APP - ISR */ RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 49.5 KiB, give 8KiB headroom for softdevice */ } From 7bcc61b0c1b7397a25f3a6ad088c9681cad6b759 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 26 Apr 2017 00:18:10 +0200 Subject: [PATCH 629/809] nrf5/boards: Adding board target for feather52 using s132 v.2.0.1 application offset even if the device is not using softdevice. To be worked on later. --- nrf5/boards/feather52/mpconfigboard.mk | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/nrf5/boards/feather52/mpconfigboard.mk b/nrf5/boards/feather52/mpconfigboard.mk index 84906b78ee..1b0e1460e9 100644 --- a/nrf5/boards/feather52/mpconfigboard.mk +++ b/nrf5/boards/feather52/mpconfigboard.mk @@ -1,13 +1,16 @@ +MCU_SERIES = m4 +MCU_VARIANT = nrf52 +MCU_SUB_VARIANT = nrf52832 +SOFTDEV_VERSION = 2.0.1 -define HELPER +LD_FILE = boards/feather52/custom_nrf52832_dfu_app.ld -######################################################### -# # -# Use SD=s132 make flag to generate a firmware suitable # -# for bluefruit nrf52 feather. # -# # -######################################################### +NRF_DEFINES += -DNRF52832_XXAA -endef +.PHONY: dfu-gen dfu-flash -$(error $(HELPER)) +dfu-gen: + nrfutil dfu genpkg --dev-type 0x0052 --application $(BUILD)/$(OUTPUT_FILENAME).hex $(BUILD)/dfu-package.zip + +dfu-flash: + sudo nrfutil dfu serial --package $(BUILD)/dfu-package.zip -p /dev/ttyACM3 From 976785e1d5764ee9e5d6326eb87cc37b8db2f650 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 26 Apr 2017 19:18:27 +0200 Subject: [PATCH 630/809] nrf5/bluetooth: Updating Bluetooth LE stack download script to allow to be invoked from any parent folder. No need to change directory to bluetooth/ in order to get the correct download target folder position. Using the script location to determine the target folder. --- nrf5/bluetooth/download_ble_stack.sh | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/nrf5/bluetooth/download_ble_stack.sh b/nrf5/bluetooth/download_ble_stack.sh index e142b9f410..537742605b 100755 --- a/nrf5/bluetooth/download_ble_stack.sh +++ b/nrf5/bluetooth/download_ble_stack.sh @@ -8,8 +8,8 @@ function download_s110_nrf51_8_0_0 echo "####################################" echo "" - mkdir -p s110_nrf51_8.0.0 - cd s110_nrf51_8.0.0 + mkdir -p $1/s110_nrf51_8.0.0 + cd $1/s110_nrf51_8.0.0 wget https://www.nordicsemi.com/eng/nordic/download_resource/45846/3/78153065/80234 mv 80234 temp.zip unzip -u temp.zip @@ -25,9 +25,8 @@ function download_s132_nrf52_2_0_1 echo "####################################" echo "" - mkdir -p s132_nrf52_2.0.1 - cd s132_nrf52_2.0.1 - + mkdir -p $1/s132_nrf52_2.0.1 + cd $1/s132_nrf52_2.0.1 wget https://www.nordicsemi.com/eng/nordic/download_resource/51479/6/84640562/95151 mv 95151 temp.zip unzip -u temp.zip @@ -43,8 +42,8 @@ function download_s132_nrf52_3_0_0 echo "####################################" echo "" - mkdir -p s132_nrf52_3.0.0 - cd s132_nrf52_3.0.0 + mkdir -p $1/s132_nrf52_3.0.0 + cd $1/s132_nrf52_3.0.0 wget https://www.nordicsemi.com/eng/nordic/download_resource/56261/6/26298825/108144 mv 108144 temp.zip @@ -53,19 +52,22 @@ function download_s132_nrf52_3_0_0 cd - } + +SCRIPT_DIR="$(cd -P "$(dirname "${BASH_SOURCE[0]}")" && pwd)" + if [ $# -eq 0 ]; then echo "No Bluetooth LE stack defined, downloading all." - download_s110_nrf51_8_0_0 - download_s132_nrf52_2_0_1 - download_s132_nrf52_3_0_0 + download_s110_nrf51_8_0_0 ${SCRIPT_DIR} + download_s132_nrf52_2_0_1 ${SCRIPT_DIR} + download_s132_nrf52_3_0_0 ${SCRIPT_DIR} else case $1 in "s110_nrf51" ) - download_s110_nrf51_8_0_0 ;; + download_s110_nrf51_8_0_0 ${SCRIPT_DIR} ;; "s132_nrf52_2_0_1" ) - download_s132_nrf52_2_0_1 ;; + download_s132_nrf52_2_0_1 ${SCRIPT_DIR} ;; "s132_nrf52_3_0_0" ) - download_s132_nrf52_3_0_0 ;; + download_s132_nrf52_3_0_0 ${SCRIPT_DIR} ;; esac fi From 7aa7bad78a37d30fa5294de2b83e933b745d6c1e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 29 Apr 2017 19:50:50 +0200 Subject: [PATCH 631/809] nrf5: Updating example in main.c on how to execute string before REPL is set up, to allow for boards with two leds. Todo for later is to update this code such that it will skip this LED toggle when there are no leds defined. Or use an example not depending on LEDs. --- nrf5/main.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/nrf5/main.c b/nrf5/main.c index c89afbb8e5..348f77fcac 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -178,8 +178,11 @@ pin_init0(); do_str("import pyb\r\n" \ "pyb.LED(1).on()", MP_PARSE_FILE_INPUT); +#elif (MICROPY_HW_LED_COUNT == 2) + do_str("import pyb\r\n" \ + "pyb.LED(1).on()", + MP_PARSE_FILE_INPUT); #else - do_str("import pyb\r\n" \ "pyb.LED(1).on()\r\n" \ "pyb.LED(3).on()", From 7449f8d861f9fb57c7e82b9808b6081bfa14d6f1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 30 Apr 2017 19:42:19 +0200 Subject: [PATCH 632/809] nrf5/hal/timer: Changing hardcoded hal timer instance base to a lookup, so that IRQ num can be detected automatically without the need of using struct param on it. Size of binary does not increase when using Os. --- nrf5/hal/hal_timer.h | 45 ++++++++++++++++++------------------ nrf5/modules/machine/timer.c | 6 ++--- 2 files changed, 25 insertions(+), 26 deletions(-) diff --git a/nrf5/hal/hal_timer.h b/nrf5/hal/hal_timer.h index 18905c9096..a9dffad2aa 100644 --- a/nrf5/hal/hal_timer.h +++ b/nrf5/hal/hal_timer.h @@ -30,31 +30,30 @@ #include "nrf.h" #if NRF51 - -#define TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0) -#define TIMER0_IRQ_NUM TIMER0_IRQn -#define TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1) -#define TIMER1_IRQ_NUM TIMER1_IRQn -#define TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2) -#define TIMER2_IRQ_NUM TIMER2_IRQn - -#elif NRF52 - -#define TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0) -#define TIMER0_IRQ_NUM TIMER0_IRQn -#define TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1) -#define TIMER1_IRQ_NUM TIMER1_IRQn -#define TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2) -#define TIMER2_IRQ_NUM TIMER2_IRQn -#define TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3) -#define TIMER3_IRQ_NUM TIMER3_IRQn -#define TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4) -#define TIMER4_IRQ_NUM TIMER4_IRQn - -#else -#error "Device not supported." + #define TIMER_BASE_POINTERS (const uint32_t[]){NRF_TIMER0_BASE, \ + NRF_TIMER1_BASE, \ + NRF_TIMER2_BASE} + #define TIMER_IRQ_VALUES (const uint32_t[]){TIMER0_IRQn, \ + TIMER1_IRQn, \ + TIMER2_IRQn} #endif +#if NRF52 + #define TIMER_BASE_POINTERS (const uint32_t[]){NRF_TIMER0_BASE, \ + NRF_TIMER1_BASE, \ + NRF_TIMER1_BASE, \ + NRF_TIMER1_BASE, \ + NRF_TIMER2_BASE} + #define TIMER_IRQ_VALUES (const uint32_t[]){TIMER0_IRQn, \ + TIMER1_IRQn, \ + TIMER2_IRQn, \ + TIMER3_IRQn, \ + TIMER4_IRQn} +#endif + +#define TIMER_BASE(x) ((NRF_TIMER_Type *)TIMER_BASE_POINTERS[x]) +#define TIMER_IRQ_NUM(x) (TIMER_IRQ_VALUES[x]) + /** * @brief Timer Configuration Structure definition */ diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index b973800963..6329aaab3d 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -53,11 +53,11 @@ STATIC const machine_timer_obj_t machine_timer_obj[] = { void timer_init0(void) { // reset the Timer handles memset(&TimerHandle0, 0, sizeof(Timer_HandleTypeDef)); - TimerHandle0.instance = TIMER0; + TimerHandle0.instance = TIMER_BASE(0); memset(&TimerHandle1, 0, sizeof(Timer_HandleTypeDef)); - TimerHandle0.instance = TIMER1; + TimerHandle0.instance = TIMER_BASE(1); memset(&TimerHandle2, 0, sizeof(Timer_HandleTypeDef)); - TimerHandle0.instance = TIMER2; + TimerHandle0.instance = TIMER_BASE(2); } STATIC int timer_find(mp_obj_t id) { From 0437fafaacbf7603697668e303d130d1815b17db Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 30 Apr 2017 19:42:54 +0200 Subject: [PATCH 633/809] nrf5/hal/timer: Adding empty IRQ handlers for all timers. --- nrf5/hal/hal_timer.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/nrf5/hal/hal_timer.c b/nrf5/hal/hal_timer.c index fbf3520fe7..dd2cbfceef 100644 --- a/nrf5/hal/hal_timer.c +++ b/nrf5/hal/hal_timer.c @@ -30,6 +30,31 @@ #ifdef HAL_TIMER_MODULE_ENABLED void hal_timer_init(NRF_TIMER_Type * p_instance, hal_timer_init_t const * p_timer_init) { + } +void TIMER0_IRQHandler(void) { + +} + +void TIMER1_IRQHandler(void) { + +} + +void TIMER2_IRQHandler(void) { + +} + +#if NRF52 + +void TIMER3_IRQHandler(void) { + +} + +void TIMER4_IRQHandler(void) { + +} + +#endif + #endif // HAL_TIMER_MODULE_ENABLED From a0638880b391b6fddb76a0d0cc76b9263ba6d76e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 30 Apr 2017 20:15:03 +0200 Subject: [PATCH 634/809] nrf5/modules/timer: Optimizing timer object structure and updating the module to use new hal_timer_init structures and parameters. --- nrf5/hal/hal_timer.c | 2 +- nrf5/hal/hal_timer.h | 16 ++++------------ nrf5/modules/machine/timer.c | 29 +++++++++++------------------ 3 files changed, 16 insertions(+), 31 deletions(-) diff --git a/nrf5/hal/hal_timer.c b/nrf5/hal/hal_timer.c index dd2cbfceef..ac0d20846c 100644 --- a/nrf5/hal/hal_timer.c +++ b/nrf5/hal/hal_timer.c @@ -29,7 +29,7 @@ #ifdef HAL_TIMER_MODULE_ENABLED -void hal_timer_init(NRF_TIMER_Type * p_instance, hal_timer_init_t const * p_timer_init) { +void hal_timer_init(hal_timer_conf_t const * p_timer_conf) { } diff --git a/nrf5/hal/hal_timer.h b/nrf5/hal/hal_timer.h index a9dffad2aa..245a33955b 100644 --- a/nrf5/hal/hal_timer.h +++ b/nrf5/hal/hal_timer.h @@ -58,18 +58,10 @@ * @brief Timer Configuration Structure definition */ typedef struct { -} hal_timer_init_t; + uint8_t id; + uint8_t irq_priority; +} hal_timer_conf_t; -/** - * @brief Timer handle Structure definition - */ -typedef struct __Timer_HandleTypeDef -{ - NRF_TIMER_Type *instance; /* Timer registers base address */ - hal_timer_init_t init; /* Timer initialization parameters */ - uint8_t id; /* Timer instance id */ -} Timer_HandleTypeDef; - -void hal_timer_init(NRF_TIMER_Type * p_instance, hal_timer_init_t const * p_timer_init); +void hal_timer_init(hal_timer_conf_t const * p_timer_config); #endif // HAL_TIMER_H__ diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index 6329aaab3d..9a3403b2b5 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -36,35 +36,28 @@ #if MICROPY_PY_MACHINE_TIMER typedef struct _machine_timer_obj_t { - mp_obj_base_t base; - Timer_HandleTypeDef *timer; + mp_obj_base_t base; + hal_timer_conf_t * p_config; } machine_timer_obj_t; -Timer_HandleTypeDef TimerHandle0 = {.instance = NULL, .id = 0}; -Timer_HandleTypeDef TimerHandle1 = {.instance = NULL, .id = 1}; -Timer_HandleTypeDef TimerHandle2 = {.instance = NULL, .id = 2}; +static hal_timer_conf_t timer_config0 = {.id = 0}; +static hal_timer_conf_t timer_config1 = {.id = 1}; +static hal_timer_conf_t timer_config2 = {.id = 2}; STATIC const machine_timer_obj_t machine_timer_obj[] = { - {{&machine_timer_type}, &TimerHandle0}, - {{&machine_timer_type}, &TimerHandle1}, - {{&machine_timer_type}, &TimerHandle2}, + {{&machine_timer_type}, &timer_config0}, + {{&machine_timer_type}, &timer_config1}, + {{&machine_timer_type}, &timer_config2}, }; void timer_init0(void) { - // reset the Timer handles - memset(&TimerHandle0, 0, sizeof(Timer_HandleTypeDef)); - TimerHandle0.instance = TIMER_BASE(0); - memset(&TimerHandle1, 0, sizeof(Timer_HandleTypeDef)); - TimerHandle0.instance = TIMER_BASE(1); - memset(&TimerHandle2, 0, sizeof(Timer_HandleTypeDef)); - TimerHandle0.instance = TIMER_BASE(2); } STATIC int timer_find(mp_obj_t id) { // given an integer id int timer_id = mp_obj_get_int(id); if (timer_id >= 0 && timer_id <= MP_ARRAY_SIZE(machine_timer_obj) - && machine_timer_obj[timer_id].timer != NULL) { + && machine_timer_obj[timer_id].p_config != NULL) { return timer_id; } nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, @@ -73,7 +66,7 @@ STATIC int timer_find(mp_obj_t id) { STATIC void timer_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { machine_timer_obj_t *self = o; - mp_printf(print, "Timer(%u)", self->timer->id); + mp_printf(print, "Timer(%u)", self->p_config->id); } /******************************************************************************/ @@ -103,7 +96,7 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, int timer_id = timer_find(args[ARG_NEW_id].u_obj); const machine_timer_obj_t *self = &machine_timer_obj[timer_id]; - hal_timer_init(self->timer->instance, &self->timer->init); + hal_timer_init(self->p_config); return MP_OBJ_FROM_PTR(self); } From 1c756af9a4597358fd1c9ac244227b2aacde4e00 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 30 Apr 2017 20:18:46 +0200 Subject: [PATCH 635/809] nrf5/modules/timer: Adding timer3 and timer4 to timer object in case of nrf52 target. --- nrf5/modules/machine/timer.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index 9a3403b2b5..16c466c89a 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -44,10 +44,19 @@ static hal_timer_conf_t timer_config0 = {.id = 0}; static hal_timer_conf_t timer_config1 = {.id = 1}; static hal_timer_conf_t timer_config2 = {.id = 2}; +#if NRF52 +static hal_timer_conf_t timer_config3 = {.id = 3}; +static hal_timer_conf_t timer_config4 = {.id = 4}; +#endif + STATIC const machine_timer_obj_t machine_timer_obj[] = { {{&machine_timer_type}, &timer_config0}, {{&machine_timer_type}, &timer_config1}, {{&machine_timer_type}, &timer_config2}, +#if NRF52 + {{&machine_timer_type}, &timer_config3}, + {{&machine_timer_type}, &timer_config4}, +#endif }; void timer_init0(void) { From f9b9d59434a9adb5ef37269426db732ca2648750 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 1 May 2017 19:06:49 +0200 Subject: [PATCH 636/809] nrf5/modules/microbit: Copying microbit music module to the port. --- nrf5/modules/microbit/microbitmusic.cpp | 481 +++++++++++++++++++++ nrf5/modules/microbit/microbitmusic.h | 10 + nrf5/modules/microbit/microbitmusictunes.c | 160 +++++++ 3 files changed, 651 insertions(+) create mode 100644 nrf5/modules/microbit/microbitmusic.cpp create mode 100644 nrf5/modules/microbit/microbitmusic.h create mode 100644 nrf5/modules/microbit/microbitmusictunes.c diff --git a/nrf5/modules/microbit/microbitmusic.cpp b/nrf5/modules/microbit/microbitmusic.cpp new file mode 100644 index 0000000000..95a3f33c77 --- /dev/null +++ b/nrf5/modules/microbit/microbitmusic.cpp @@ -0,0 +1,481 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "microbitobj.h" +#include "microbitmusic.h" + +extern "C" { + +#include "py/runtime.h" +#include "py/objstr.h" +#include "py/mphal.h" +#include "modmicrobit.h" +#include "microbit/microbitobj.h" +#include "microbit/microbitpin.h" +#include "lib/pwm.h" + +#define DEFAULT_BPM 120 +#define DEFAULT_TICKS 4 // i.e. 4 ticks per beat +#define DEFAULT_OCTAVE 4 // C4 is middle C +#define DEFAULT_DURATION 4 // Crotchet +#define ARTICULATION_MS 10 // articulation between notes in milliseconds + +typedef struct _music_data_t { + uint16_t bpm; + uint16_t ticks; + + // store these to simplify the writing process + uint8_t last_octave; + uint8_t last_duration; + + // Asynchronous parts. + volatile uint8_t async_state; + bool async_loop; + uint32_t async_wait_ticks; + uint16_t async_notes_len; + uint16_t async_notes_index; + const microbit_pin_obj_t *async_pin; + mp_obj_t async_note; +} music_data_t; + +enum { + ASYNC_MUSIC_STATE_IDLE, + ASYNC_MUSIC_STATE_NEXT_NOTE, + ASYNC_MUSIC_STATE_ARTICULATE, +}; + +#define music_data MP_STATE_PORT(music_data) + +extern uint32_t ticks; + +STATIC uint32_t start_note(const char *note_str, size_t note_len, const microbit_pin_obj_t *pin); + +void microbit_music_tick(void) { + if (music_data == NULL) { + // music module not yet imported + return; + } + + if (music_data->async_state == ASYNC_MUSIC_STATE_IDLE) { + // nothing to do + return; + } + + if (ticks < music_data->async_wait_ticks) { + // need to wait for timeout to expire + return; + } + + if (music_data->async_state == ASYNC_MUSIC_STATE_ARTICULATE) { + // turn off output and rest + pwm_set_duty_cycle(music_data->async_pin->name, 0); + music_data->async_wait_ticks = ticks + ARTICULATION_MS; + music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE; + } else if (music_data->async_state == ASYNC_MUSIC_STATE_NEXT_NOTE) { + // play next note + if (music_data->async_notes_index >= music_data->async_notes_len) { + if (music_data->async_loop) { + music_data->async_notes_index = 0; + } else { + music_data->async_state = ASYNC_MUSIC_STATE_IDLE; + microbit_obj_pin_free(music_data->async_pin); + music_data->async_pin = NULL; + return; + } + } + mp_obj_t note; + if (music_data->async_notes_len == 1) { + note = music_data->async_note; + } else { + note = ((mp_obj_t*)music_data->async_note)[music_data->async_notes_index]; + } + if (note == mp_const_none) { + // a rest (is this even used anymore?) + pwm_set_duty_cycle(music_data->async_pin->name, 0); + music_data->async_wait_ticks = 60000 / music_data->bpm; + music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE; + } else { + // a note + mp_uint_t note_len; + const char *note_str = mp_obj_str_get_data(note, ¬e_len); + uint32_t delay_on = start_note(note_str, note_len, music_data->async_pin); + music_data->async_wait_ticks = ticks + delay_on; + music_data->async_notes_index += 1; + music_data->async_state = ASYNC_MUSIC_STATE_ARTICULATE; + } + } +} + +STATIC void wait_async_music_idle(void) { + // wait for the async music state to become idle + while (music_data->async_state != ASYNC_MUSIC_STATE_IDLE) { + // allow CTRL-C to stop the music + if (MP_STATE_VM(mp_pending_exception) != MP_OBJ_NULL) { + music_data->async_state = ASYNC_MUSIC_STATE_IDLE; + pwm_set_duty_cycle(music_data->async_pin->name, 0); + break; + } + } +} + +STATIC uint32_t start_note(const char *note_str, size_t note_len, const microbit_pin_obj_t *pin) { + pwm_set_duty_cycle(pin->name, 128); + + // [NOTE](#|b)(octave)(:length) + // technically, c4 is middle c, so we'll go with that... + // if we define A as 0 and G as 7, then we can use the following + // array of us periods + + // these are the periods of note4 (the octave ascending from middle c) from A->B then C->G + STATIC uint16_t periods_us[] = {2273, 2025, 3822, 3405, 3034, 2863, 2551}; + // A#, -, C#, D#, -, F#, G# + STATIC uint16_t periods_sharps_us[] = {2145, 0, 3608, 3214, 0, 2703, 2408}; + + // we'll represent the note as an integer (A=0, G=6) + // TODO: validate the note + uint8_t note_index = (note_str[0] & 0x1f) - 1; + + // TODO: the duration and bpm should be persistent between notes + uint32_t ms_per_tick = (60000 / music_data->bpm) / music_data->ticks; + + int8_t octave = 0; + bool sharp = false; + + size_t current_position = 1; + + // parse sharp or flat + if (current_position < note_len && (note_str[current_position] == '#' || note_str[current_position] == 'b')) { + if (note_str[current_position] == 'b') { + // make sure we handle wrapping round gracefully + if (note_index == 0) { + note_index = 6; + } else { + note_index--; + } + + // handle the unusual edge case of Cb + if (note_index == 1) { + octave--; + } + } + + sharp = true; + current_position++; + } + + // parse the octave + if (current_position < note_len && note_str[current_position] != ':') { + // currently this will only work with a one digit number + // use +=, since the sharp/flat code changes octave to compensate. + music_data->last_octave = (note_str[current_position] & 0xf); + current_position++; + } + + octave += music_data->last_octave; + + // parse the duration + if (current_position < note_len && note_str[current_position] == ':') { + // I'll make this handle up to two digits for the time being. + current_position++; + + if (current_position < note_len) { + music_data->last_duration = note_str[current_position] & 0xf; + + current_position++; + if (current_position < note_len) { + music_data->last_duration *= 10; + music_data->last_duration += note_str[current_position] & 0xf; + } + } else { + // technically, this should be a syntax error, since this means + // that no duration has been specified. For the time being, + // we'll let you off :D + } + } + // play the note! + + // make the octave relative to octave 4 + octave -= 4; + + // 18 is 'r' or 'R' + if (note_index < 10) { + uint32_t period; + if (sharp) { + if (octave >= 0) { + period = periods_sharps_us[note_index] >> octave; + } + else { + period = periods_sharps_us[note_index] << -octave; + } + } else { + if (octave >= 0) { + period = periods_us[note_index] >> octave; + } + else { + period = periods_us[note_index] << -octave; + } + } + pwm_set_period_us(period); + } else { + pwm_set_duty_cycle(pin->name, 0); + } + + // Cut off a short time from end of note so we hear articulation. + mp_int_t gap_ms = (ms_per_tick * music_data->last_duration) - ARTICULATION_MS; + if (gap_ms < ARTICULATION_MS) { + gap_ms = ARTICULATION_MS; + } + return gap_ms; +} + +STATIC mp_obj_t microbit_music_reset(void) { + music_data->bpm = DEFAULT_BPM; + music_data->ticks = DEFAULT_TICKS; + music_data->last_octave = DEFAULT_OCTAVE; + music_data->last_duration = DEFAULT_DURATION; + + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(microbit_music_reset_obj, microbit_music_reset); + +STATIC mp_obj_t microbit_music_get_tempo(void) { + mp_obj_t tempo_tuple[2]; + + tempo_tuple[0] = mp_obj_new_int(music_data->bpm); + tempo_tuple[1] = mp_obj_new_int(music_data->ticks); + + return mp_obj_new_tuple(2, tempo_tuple); +} +MP_DEFINE_CONST_FUN_OBJ_0(microbit_music_get_tempo_obj, microbit_music_get_tempo); + +STATIC mp_obj_t microbit_music_stop(mp_uint_t n_args, const mp_obj_t *args) { + const microbit_pin_obj_t *pin; + if (n_args == 0) { + pin = µbit_p0_obj; + } else { + pin = microbit_obj_get_pin(args[0]); + } + // Raise exception if the pin we are trying to stop is not in a compatible mode. + microbit_obj_pin_acquire(pin, microbit_pin_mode_music); + pwm_set_duty_cycle(pin->name, 0); + microbit_obj_pin_free(pin); + music_data->async_pin = NULL; + music_data->async_state = ASYNC_MUSIC_STATE_IDLE; + + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(microbit_music_stop_obj, 0, 1, microbit_music_stop); + +STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_music, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, + { MP_QSTR_wait, MP_ARG_BOOL, {.u_bool = true} }, + { MP_QSTR_loop, MP_ARG_BOOL, {.u_bool = false} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // reset octave and duration so tunes always play the same + music_data->last_octave = DEFAULT_OCTAVE; + music_data->last_duration = DEFAULT_DURATION; + + // get either a single note or a list of notes + mp_uint_t len; + mp_obj_t *items; + if (MP_OBJ_IS_STR_OR_BYTES(args[0].u_obj)) { + len = 1; + items = &args[0].u_obj; + } else { + mp_obj_get_array(args[0].u_obj, &len, &items); + } + + // Release the previous pin + microbit_obj_pin_free(music_data->async_pin); + music_data->async_pin = NULL; + + // get the pin to play on + const microbit_pin_obj_t *pin = microbit_obj_get_pin(args[1].u_obj); + microbit_obj_pin_acquire(pin, microbit_pin_mode_music); + + // start the tune running in the background + music_data->async_state = ASYNC_MUSIC_STATE_IDLE; + music_data->async_wait_ticks = ticks; + music_data->async_loop = args[3].u_bool; + music_data->async_notes_len = len; + music_data->async_notes_index = 0; + if (len == 1) { + // If a string was passed as a single note then we can't store a pointer + // to args[0].u_obj, so instead store the single string directly (also + // works if a tuple/list of one element was passed). + music_data->async_note = items[0]; + } else { + music_data->async_note = items; + } + music_data->async_pin = pin; + music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE; + + if (args[2].u_bool) { + // wait for tune to finish + wait_async_music_idle(); + } + + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_KW(microbit_music_play_obj, 0, microbit_music_play); + +STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_frequency, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_duration, MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, + { MP_QSTR_wait, MP_ARG_BOOL, {.u_bool = true} }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // get the parameters + mp_uint_t frequency = args[0].u_int; + mp_int_t duration = args[1].u_int; + const microbit_pin_obj_t *pin = microbit_obj_get_pin(args[2].u_obj); + + // Update pin modes + microbit_obj_pin_free(music_data->async_pin); + music_data->async_pin = NULL; + microbit_obj_pin_acquire(pin, microbit_pin_mode_music); + bool wait = args[3].u_bool; + pwm_set_duty_cycle(pin->name, 128); + if (frequency == 0) { + pwm_release(pin->name); + } else if (pwm_set_period_us(1000000/frequency)) { + pwm_release(pin->name); + nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "invalid pitch")); + } + if (duration >= 0) { + // use async machinery to stop the pitch after the duration + music_data->async_state = ASYNC_MUSIC_STATE_IDLE; + music_data->async_wait_ticks = ticks + duration; + music_data->async_loop = false; + music_data->async_notes_len = 0; + music_data->async_notes_index = 0; + music_data->async_note = NULL; + music_data->async_pin = pin; + music_data->async_state = ASYNC_MUSIC_STATE_ARTICULATE; + + if (wait) { + // wait for the pitch to finish + wait_async_music_idle(); + } + } else { + // don't block here, since there's no reason to leave a pitch forever in a blocking C function + } + + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_KW(microbit_music_pitch_obj, 0, microbit_music_pitch); + +STATIC mp_obj_t microbit_music_set_tempo(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_ticks, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_bpm, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + }; + + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (args[0].u_int != 0) { + // set ticks + music_data->ticks = args[0].u_int; + } + + if (args[1].u_int != 0) { + music_data->bpm = args[1].u_int; + } + + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_KW(microbit_music_set_tempo_obj, 0, microbit_music_set_tempo); + + +static mp_obj_t music_init(void) { + music_data = m_new_obj(music_data_t); + music_data->bpm = DEFAULT_BPM; + music_data->ticks = DEFAULT_TICKS; + music_data->last_octave = DEFAULT_OCTAVE; + music_data->last_duration = DEFAULT_DURATION; + music_data->async_state = ASYNC_MUSIC_STATE_IDLE; + music_data->async_pin = NULL; + music_data->async_note = NULL; + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(music___init___obj, music_init); + +STATIC const mp_map_elem_t microbit_music_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR___init__), (mp_obj_t)&music___init___obj }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_reset), (mp_obj_t)µbit_music_reset_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_set_tempo), (mp_obj_t)µbit_music_set_tempo_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_get_tempo), (mp_obj_t)µbit_music_get_tempo_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_play), (mp_obj_t)µbit_music_play_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_pitch), (mp_obj_t)µbit_music_pitch_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)µbit_music_stop_obj }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_DADADADUM), (mp_obj_t)µbit_music_tune_dadadadum_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ENTERTAINER), (mp_obj_t)µbit_music_tune_entertainer_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PRELUDE), (mp_obj_t)µbit_music_tune_prelude_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ODE), (mp_obj_t)µbit_music_tune_ode_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_NYAN), (mp_obj_t)µbit_music_tune_nyan_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_RINGTONE), (mp_obj_t)µbit_music_tune_ringtone_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FUNK), (mp_obj_t)µbit_music_tune_funk_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_BLUES), (mp_obj_t)µbit_music_tune_blues_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_BIRTHDAY), (mp_obj_t)µbit_music_tune_birthday_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_WEDDING), (mp_obj_t)µbit_music_tune_wedding_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_FUNERAL), (mp_obj_t)µbit_music_tune_funeral_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PUNCHLINE), (mp_obj_t)µbit_music_tune_punchline_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PYTHON), (mp_obj_t)µbit_music_tune_python_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_BADDY), (mp_obj_t)µbit_music_tune_baddy_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_CHASE), (mp_obj_t)µbit_music_tune_chase_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_BA_DING), (mp_obj_t)µbit_music_tune_ba_ding_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_WAWAWAWAA), (mp_obj_t)µbit_music_tune_wawawawaa_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_JUMP_UP), (mp_obj_t)µbit_music_tune_jump_up_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_JUMP_DOWN), (mp_obj_t)µbit_music_tune_jump_down_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_POWER_UP), (mp_obj_t)µbit_music_tune_power_up_obj }, + { MP_OBJ_NEW_QSTR(MP_QSTR_POWER_DOWN), (mp_obj_t)µbit_music_tune_power_down_obj }, +}; + +STATIC MP_DEFINE_CONST_DICT(microbit_music_locals_dict, microbit_music_locals_dict_table); + +const mp_obj_module_t music_module = { + .base = { &mp_type_module }, + .name = MP_QSTR_music, + .globals = (mp_obj_dict_t*)µbit_music_locals_dict, +}; + +} diff --git a/nrf5/modules/microbit/microbitmusic.h b/nrf5/modules/microbit/microbitmusic.h new file mode 100644 index 0000000000..530c414593 --- /dev/null +++ b/nrf5/modules/microbit/microbitmusic.h @@ -0,0 +1,10 @@ +#ifndef __MICROPY_INCLUDED_MICROBIT_MUSIC_H__ +#define __MICROPY_INCLUDED_MICROBIT_MUSIC_H__ + +extern "C" { + +void microbit_music_tick(void); + +} + +#endif // __MICROPY_INCLUDED_MICROBIT_MUSIC_H__ diff --git a/nrf5/modules/microbit/microbitmusictunes.c b/nrf5/modules/microbit/microbitmusictunes.c new file mode 100644 index 0000000000..16184e4925 --- /dev/null +++ b/nrf5/modules/microbit/microbitmusictunes.c @@ -0,0 +1,160 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The music encoded herein is either in the public domain, composed by + * Nicholas H.Tollervey or the composer is untraceable and covered by fair + * (educational) use. + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Damien P. George + * Copyright (c) 2015 Nicholas H. Tollervey + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/objtuple.h" +#include "modmicrobit.h" + +#define N(q) MP_OBJ_NEW_QSTR(MP_QSTR_ ## q) +#define T(name, ...) const mp_obj_tuple_t microbit_music_tune_ ## name ## _obj = {{&mp_type_tuple}, .len = (sizeof((mp_obj_t[]){__VA_ARGS__})/sizeof(mp_obj_t)), .items = {__VA_ARGS__}}; + + +T(dadadadum, + N(r4_colon_2), N(g), N(g), N(g), N(eb_colon_8), N(r_colon_2), N(f), N(f), + N(f), N(d_colon_8)); + +T(entertainer, + N(d4_colon_1), N(d_hash_), N(e), N(c5_colon_2), N(e4_colon_1), + N(c5_colon_2), N(e4_colon_1), N(c5_colon_3), N(c_colon_1), N(d), + N(d_hash_), N(e), N(c), N(d), N(e_colon_2), N(b4_colon_1), N(d5_colon_2), + N(c_colon_4)); + +T(prelude, + N(c4_colon_1), N(e), N(g), N(c5), N(e), N(g4), N(c5), N(e), N(c4), N(e), + N(g), N(c5), N(e), N(g4), N(c5), N(e), N(c4), N(d), N(g), N(d5), N(f), + N(g4), N(d5), N(f), N(c4), N(d), N(g), N(d5), N(f), N(g4), N(d5), N(f), + N(b3), N(d4), N(g), N(d5), N(f), N(g4), N(d5), N(f), N(b3), N(d4), N(g), + N(d5), N(f), N(g4), N(d5), N(f), N(c4), N(e), N(g), N(c5), N(e), N(g4), + N(c5), N(e), N(c4), N(e), N(g), N(c5), N(e), N(g4), N(c5), N(e)); + +T(ode, + N(e4), N(e), N(f), N(g), N(g), N(f), N(e), N(d), N(c), N(c), N(d), N(e), + N(e_colon_6), N(d_colon_2), N(d_colon_8), N(e_colon_4), N(e), N(f), N(g), + N(g), N(f), N(e), N(d), N(c), N(c), N(d), N(e), N(d_colon_6), + N(c_colon_2), N(c_colon_8)); + +T(nyan, + N(f_hash_5_colon_2), N(g_hash_), N(c_hash__colon_1), N(d_hash__colon_2), + N(b4_colon_1), N(d5_colon_1), N(c_hash_), N(b4_colon_2), N(b), + N(c_hash_5), N(d), N(d_colon_1), N(c_hash_), N(b4_colon_1), + N(c_hash_5_colon_1), N(d_hash_), N(f_hash_), N(g_hash_), N(d_hash_), + N(f_hash_), N(c_hash_), N(d), N(b4), N(c_hash_5), N(b4), + N(d_hash_5_colon_2), N(f_hash_), N(g_hash__colon_1), N(d_hash_), + N(f_hash_), N(c_hash_), N(d_hash_), N(b4), N(d5), N(d_hash_), N(d), + N(c_hash_), N(b4), N(c_hash_5), N(d_colon_2), N(b4_colon_1), N(c_hash_5), + N(d_hash_), N(f_hash_), N(c_hash_), N(d), N(c_hash_), N(b4), + N(c_hash_5_colon_2), N(b4), N(c_hash_5), N(b4), N(f_hash__colon_1), + N(g_hash_), N(b_colon_2), N(f_hash__colon_1), N(g_hash_), N(b), + N(c_hash_5), N(d_hash_), N(b4), N(e5), N(d_hash_), N(e), N(f_hash_), + N(b4_colon_2), N(b), N(f_hash__colon_1), N(g_hash_), N(b), N(f_hash_), + N(e5), N(d_hash_), N(c_hash_), N(b4), N(f_hash_), N(d_hash_), N(e), + N(f_hash_), N(b_colon_2), N(f_hash__colon_1), N(g_hash_), N(b_colon_2), + N(f_hash__colon_1), N(g_hash_), N(b), N(b), N(c_hash_5), N(d_hash_), + N(b4), N(f_hash_), N(g_hash_), N(f_hash_), N(b_colon_2), N(b_colon_1), + N(a_hash_), N(b), N(f_hash_), N(g_hash_), N(b), N(e5), N(d_hash_), N(e), + N(f_hash_), N(b4_colon_2), N(c_hash_5)); + +T(ringtone, + N(c4_colon_1), N(d), N(e_colon_2), N(g), N(d_colon_1), N(e), N(f_colon_2), + N(a), N(e_colon_1), N(f), N(g_colon_2), N(b), N(c5_colon_4)); + +T(funk, + N(c2_colon_2), N(c), N(d_hash_), N(c_colon_1), N(f_colon_2), N(c_colon_1), + N(f_colon_2), N(f_hash_), N(g), N(c), N(c), N(g), N(c_colon_1), + N(f_hash__colon_2), N(c_colon_1), N(f_hash__colon_2), N(f), N(d_hash_)); + +T(blues, + N(c2_colon_2), N(e), N(g), N(a), N(a_hash_), N(a), N(g), N(e), + N(c2_colon_2), N(e), N(g), N(a), N(a_hash_), N(a), N(g), N(e), N(f), N(a), + N(c3), N(d), N(d_hash_), N(d), N(c), N(a2), N(c2_colon_2), N(e), N(g), + N(a), N(a_hash_), N(a), N(g), N(e), N(g), N(b), N(d3), N(f), N(f2), N(a), + N(c3), N(d_hash_), N(c2_colon_2), N(e), N(g), N(e), N(g), N(f), N(e), + N(d)); + +T(birthday, + N(c4_colon_3), N(c_colon_1), N(d_colon_4), N(c_colon_4), N(f), + N(e_colon_8), N(c_colon_3), N(c_colon_1), N(d_colon_4), N(c_colon_4), + N(g), N(f_colon_8), N(c_colon_3), N(c_colon_1), N(c5_colon_4), N(a4), + N(f), N(e), N(d), N(a_hash__colon_3), N(a_hash__colon_1), N(a_colon_4), + N(f), N(g), N(f_colon_8)); + +T(wedding, + N(c4_colon_4), N(f_colon_3), N(f_colon_1), N(f_colon_8), N(c_colon_4), + N(g_colon_3), N(e_colon_1), N(f_colon_8), N(c_colon_4), N(f_colon_3), + N(a_colon_1), N(c5_colon_4), N(a4_colon_3), N(f_colon_1), N(f_colon_4), + N(e_colon_3), N(f_colon_1), N(g_colon_8)); + +T(funeral, + N(c3_colon_4), N(c_colon_3), N(c_colon_1), N(c_colon_4), + N(d_hash__colon_3), N(d_colon_1), N(d_colon_3), N(c_colon_1), + N(c_colon_3), N(b2_colon_1), N(c3_colon_4)); + +T(punchline, + N(c4_colon_3), N(g3_colon_1), N(f_hash_), N(g), N(g_hash__colon_3), N(g), + N(r), N(b), N(c4)); + +T(python, + N(d5_colon_1), N(b4), N(r), N(b), N(b), N(a_hash_), N(b), N(g5), N(r), + N(d), N(d), N(r), N(b4), N(c5), N(r), N(c), N(c), N(r), N(d), + N(e_colon_5), N(c_colon_1), N(a4), N(r), N(a), N(a), N(g_hash_), N(a), + N(f_hash_5), N(r), N(e), N(e), N(r), N(c), N(b4), N(r), N(b), N(b), N(r), + N(c5), N(d_colon_5), N(d_colon_1), N(b4), N(r), N(b), N(b), N(a_hash_), + N(b), N(b5), N(r), N(g), N(g), N(r), N(d), N(c_hash_), N(r), N(a), N(a), + N(r), N(a), N(a_colon_5), N(g_colon_1), N(f_hash__colon_2), N(a_colon_1), + N(a), N(g_hash_), N(a), N(e_colon_2), N(a_colon_1), N(a), N(g_hash_), + N(a), N(d), N(r), N(c_hash_), N(d), N(r), N(c_hash_), N(d_colon_2), + N(r_colon_3)); + +T(baddy, + N(c3_colon_3), N(r), N(d_colon_2), N(d_hash_), N(r), N(c), N(r), N(f_hash__colon_8), ); + +T(chase, + N(a4_colon_1), N(b), N(c5), N(b4), N(a_colon_2), N(r), N(a_colon_1), N(b), N(c5), N(b4), N(a_colon_2), N(r), N(a_colon_2), N(e5), N(d_hash_), N(e), N(f), N(e), N(d_hash_), N(e), N(b4_colon_1), N(c5), N(d), N(c), N(b4_colon_2), N(r), N(b_colon_1), N(c5), N(d), N(c), N(b4_colon_2), N(r), N(b_colon_2), N(e5), N(d_hash_), N(e), N(f), N(e), N(d_hash_), N(e), ); + +T(ba_ding, + N(b5_colon_1), N(e6_colon_3), ); + +T(wawawawaa, + N(e3_colon_3), N(r_colon_1), N(d_hash__colon_3), N(r_colon_1), N(d_colon_4), N(r_colon_1), N(c_hash__colon_8), ); + +T(jump_up, + N(c5_colon_1), N(d), N(e), N(f), N(g), ); + +T(jump_down, + N(g5_colon_1), N(f), N(e), N(d), N(c), ); + +T(power_up, + N(g4_colon_1), N(c5), N(e), N(g_colon_2), N(e_colon_1), N(g_colon_3), ); + +T(power_down, + N(g5_colon_1), N(d_hash_), N(c), N(g4_colon_2), N(b_colon_1), N(c5_colon_3), ); + +#undef N +#undef T From 20bdb7dc908987ccca4b2709fdc7c6cb70011632 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 1 May 2017 19:08:36 +0200 Subject: [PATCH 637/809] nrf5/modules/music: Renaming microbit module to music. --- nrf5/modules/{microbit => music}/microbitmusic.cpp | 0 nrf5/modules/{microbit => music}/microbitmusic.h | 0 nrf5/modules/{microbit => music}/microbitmusictunes.c | 0 3 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/modules/{microbit => music}/microbitmusic.cpp (100%) rename nrf5/modules/{microbit => music}/microbitmusic.h (100%) rename nrf5/modules/{microbit => music}/microbitmusictunes.c (100%) diff --git a/nrf5/modules/microbit/microbitmusic.cpp b/nrf5/modules/music/microbitmusic.cpp similarity index 100% rename from nrf5/modules/microbit/microbitmusic.cpp rename to nrf5/modules/music/microbitmusic.cpp diff --git a/nrf5/modules/microbit/microbitmusic.h b/nrf5/modules/music/microbitmusic.h similarity index 100% rename from nrf5/modules/microbit/microbitmusic.h rename to nrf5/modules/music/microbitmusic.h diff --git a/nrf5/modules/microbit/microbitmusictunes.c b/nrf5/modules/music/microbitmusictunes.c similarity index 100% rename from nrf5/modules/microbit/microbitmusictunes.c rename to nrf5/modules/music/microbitmusictunes.c From eedd9eabe9d044b72417a2576eb6a91bb7238947 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 1 May 2017 19:11:44 +0200 Subject: [PATCH 638/809] nrf5/modules/music: Renaming microbitmusic files to modmusic/music. --- nrf5/modules/music/{microbitmusic.cpp => modmusic.c} | 0 nrf5/modules/music/{microbitmusic.h => modmusic.h} | 0 nrf5/modules/music/{microbitmusictunes.c => musictunes.c} | 0 3 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/modules/music/{microbitmusic.cpp => modmusic.c} (100%) rename nrf5/modules/music/{microbitmusic.h => modmusic.h} (100%) rename nrf5/modules/music/{microbitmusictunes.c => musictunes.c} (100%) diff --git a/nrf5/modules/music/microbitmusic.cpp b/nrf5/modules/music/modmusic.c similarity index 100% rename from nrf5/modules/music/microbitmusic.cpp rename to nrf5/modules/music/modmusic.c diff --git a/nrf5/modules/music/microbitmusic.h b/nrf5/modules/music/modmusic.h similarity index 100% rename from nrf5/modules/music/microbitmusic.h rename to nrf5/modules/music/modmusic.h diff --git a/nrf5/modules/music/microbitmusictunes.c b/nrf5/modules/music/musictunes.c similarity index 100% rename from nrf5/modules/music/microbitmusictunes.c rename to nrf5/modules/music/musictunes.c From 5c6fc791e37b173b243814bab8040940794bf0c7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 1 May 2017 19:13:50 +0200 Subject: [PATCH 639/809] nrf5/drivers: Adding copy of microbit soft pwm. --- nrf5/drivers/pwm.c | 241 +++++++++++++++++++++++++++++++++++++++++++++ nrf5/drivers/pwm.h | 12 +++ 2 files changed, 253 insertions(+) create mode 100644 nrf5/drivers/pwm.c create mode 100644 nrf5/drivers/pwm.h diff --git a/nrf5/drivers/pwm.c b/nrf5/drivers/pwm.c new file mode 100644 index 0000000000..d873b703ec --- /dev/null +++ b/nrf5/drivers/pwm.c @@ -0,0 +1,241 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Mark Shannon + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stddef.h" +#include "lib/ticker.h" +#include "nrf_gpio.h" +#include "py/runtime.h" +#include "py/gc.h" +#include "PinNames.h" + +#define PWM_TICKER_INDEX 2 + +// Default period of 20ms +#define DEFAULT_PERIOD ((20*1000)/MICROSECONDS_PER_TICK) + +typedef struct _pwm_event { + uint16_t time; + uint8_t pin; + uint8_t turn_on; +} pwm_event; + +typedef struct _pwm_events { + uint8_t count; + uint16_t period; + uint32_t all_pins; + pwm_event events[1]; +} pwm_events; + +static const pwm_events OFF_EVENTS = { + .count = 1, + .period = DEFAULT_PERIOD, + .all_pins = 0, + .events = { + { + .time = 1024, + .pin = 31, + .turn_on = 0 + } + } +}; + +#define active_events MP_STATE_PORT(pwm_active_events) +#define pending_events MP_STATE_PORT(pwm_pending_events) + +void pwm_init(void) { + active_events = &OFF_EVENTS; + pending_events = NULL; +} + +static uint8_t next_event = 0; + +static inline int32_t pwm_get_period_ticks(void) { + const pwm_events *tmp = pending_events; + if (tmp == NULL) + tmp = active_events; + return tmp->period; +} + +#if 0 +void pwm_dump_events(const pwm_events *events) { + printf("Count %d, period %d, all pins %d\r\n", events->count, events->period, events->all_pins); + for (uint32_t i = 0; i < events->count; i++) { + const pwm_event *event = &events->events[i]; + printf("Event. pin: %d, duty cycle: %d, turn_on: %d\r\n", + event->pin, event->time, event->turn_on); + } +} + +void pwm_dump_state(void) { + while(pending_events); + pwm_dump_events(active_events); +} +#endif + +static const pwm_events *swap_pending(const pwm_events *in) { + __disable_irq(); + const pwm_events *result = pending_events; + pending_events = in; + __enable_irq(); + return result; +} + +static pwm_events *copy_events(const pwm_events *orig, uint32_t count) { + pwm_events *events = m_malloc(sizeof(pwm_events) + (count-1)*sizeof(pwm_event)); + events->count = count; + uint32_t copy = count > orig->count ? orig->count : count; + for (uint32_t i = 0; i < copy; i++) { + events->events[i] = orig->events[i]; + } + return events; +} + +static int find_pin_in_events(const pwm_events *events, uint32_t pin) { + for (int i = 0; i < events->count; i++) { + if (events->events[i].pin == pin) + return i; + } + return -1; +} + +static void sort_events(pwm_events *events) { + // Insertion sort + for (int32_t i = 1; i < events->count; i++) { + pwm_event x = events->events[i]; + int32_t j; + for (j = i - 1; j >= 0 && events->events[j].time > x.time; j--) { + events->events[j+1] = events->events[j]; + } + events->events[j+1] = x; + } +} + +int32_t pwm_callback(void) { + int32_t tdiff; + const pwm_events *events = active_events; + const pwm_event *event = &events->events[next_event]; + int32_t tnow = (event->time*events->period)>>10; + do { + if (event->turn_on) { + nrf_gpio_pin_set(event->pin); + next_event++; + } else { + nrf_gpio_pins_clear(events->all_pins); + next_event = 0; + tnow = 0; + if (pending_events) { + events = pending_events; + active_events = events; + pending_events = NULL; + } + } + event = &events->events[next_event]; + tdiff = ((event->time*events->period)>>10) - tnow; + } while (tdiff == 0); + return tdiff; +} + +void pwm_start(void) { + set_ticker_callback(PWM_TICKER_INDEX, pwm_callback, 120); +} + +void pwm_stop(void) { + clear_ticker_callback(PWM_TICKER_INDEX); +} + +static void pwm_set_period_ticks(int32_t ticks) { + const pwm_events *old_events = swap_pending(NULL); + if (old_events == NULL) { + old_events = active_events; + } + pwm_events *events = copy_events(old_events, old_events->count); + events->all_pins = old_events->all_pins; + events->period = ticks; + pending_events = events; +} + +int pwm_set_period_us(int32_t us) { + if ((us < 256) || + (us > 1000000)) { + return -1; + } + pwm_set_period_ticks(us/MICROSECONDS_PER_TICK); + return 0; +} + +int32_t pwm_get_period_us(void) { + return pwm_get_period_ticks()*MICROSECONDS_PER_TICK; +} + +void pwm_set_duty_cycle(int32_t pin, uint32_t value) { + if (value >= (1<<10)) { + value = (1<<10)-1; + } + uint32_t turn_on_time = 1024-value; + const pwm_events *old_events = swap_pending(NULL); + if (old_events == NULL) { + old_events = active_events; + } + if (((1<all_pins) == 0) { + nrf_gpio_cfg_output(pin); + } + int ev = find_pin_in_events(old_events, pin); + pwm_events *events; + if (ev < 0 && value == 0) { + return; + } else if (ev < 0) { + events = copy_events(old_events, old_events->count+1); + events->all_pins = old_events->all_pins | (1<events[old_events->count].time = turn_on_time; + events->events[old_events->count].pin = pin; + events->events[old_events->count].turn_on = 1; + } else if (value == 0) { + events = copy_events(old_events, old_events->count-1); + events->all_pins = old_events->all_pins & ~(1<count-1) { + events->events[ev] = old_events->events[old_events->count-1]; + } + } else { + events = copy_events(old_events, old_events->count); + events->all_pins = old_events->all_pins; + events->events[ev].time = turn_on_time; + } + events->period = old_events->period; + sort_events(events); + pending_events = events; + return; +} + +void pwm_release(int32_t pin) { + pwm_set_duty_cycle(pin, 0); + const pwm_events *ev = active_events; + int i = find_pin_in_events(ev, pin); + if (i < 0) + return; + // If i >= 0 it means that `ev` is in RAM, so it safe to discard the const qualifier + ((pwm_events *)ev)->events[i].pin = 31; + nrf_gpio_pin_clear(pin); +} diff --git a/nrf5/drivers/pwm.h b/nrf5/drivers/pwm.h new file mode 100644 index 0000000000..38ca471d17 --- /dev/null +++ b/nrf5/drivers/pwm.h @@ -0,0 +1,12 @@ +#ifndef __MICROPY_INCLUDED_LIB_PWM_H__ +#define __MICROPY_INCLUDED_LIB_PWM_H__ + +void pwm_start(void); +void pwm_stop(void); + +int pwm_set_period_us(int32_t us); +int32_t pwm_get_period_us(void); +void pwm_set_duty_cycle(int32_t pin, int32_t value); +void pwm_release(int32_t pin); + +#endif // __MICROPY_INCLUDED_LIB_PWM_H__ \ No newline at end of file From e766c7ebbea1e03261ac93043a4395a11bb74078 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 1 May 2017 19:51:47 +0200 Subject: [PATCH 640/809] nrf5/modules/music: Adding header to expose extern structs defined in musictunes.c --- nrf5/modules/music/musictunes.h | 52 +++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 nrf5/modules/music/musictunes.h diff --git a/nrf5/modules/music/musictunes.h b/nrf5/modules/music/musictunes.h new file mode 100644 index 0000000000..152b4058e4 --- /dev/null +++ b/nrf5/modules/music/musictunes.h @@ -0,0 +1,52 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MUSIC_TUNES_H__ +#define MUSIC_TUNES_H__ + +extern const struct _mp_obj_tuple_t microbit_music_tune_dadadadum_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_entertainer_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_prelude_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_ode_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_nyan_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_ringtone_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_funk_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_blues_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_birthday_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_wedding_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_funeral_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_punchline_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_python_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_baddy_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_chase_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_ba_ding_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_wawawawaa_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_jump_up_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_jump_down_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_power_up_obj; +extern const struct _mp_obj_tuple_t microbit_music_tune_power_down_obj; + +#endif // MUSIC_TUNES_H__ From 01441c8f59370d4757c3dc5cf143d9dcef35d86d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 1 May 2017 19:52:40 +0200 Subject: [PATCH 641/809] nrf5/modules/music: Removing include of modmicrobit.h in musictunes.c. --- nrf5/modules/music/musictunes.c | 1 - 1 file changed, 1 deletion(-) diff --git a/nrf5/modules/music/musictunes.c b/nrf5/modules/music/musictunes.c index 16184e4925..beaeea0487 100644 --- a/nrf5/modules/music/musictunes.c +++ b/nrf5/modules/music/musictunes.c @@ -30,7 +30,6 @@ */ #include "py/objtuple.h" -#include "modmicrobit.h" #define N(q) MP_OBJ_NEW_QSTR(MP_QSTR_ ## q) #define T(name, ...) const mp_obj_tuple_t microbit_music_tune_ ## name ## _obj = {{&mp_type_tuple}, .len = (sizeof((mp_obj_t[]){__VA_ARGS__})/sizeof(mp_obj_t)), .items = {__VA_ARGS__}}; From 10e6b4309b0a1c605f86d90dccb67cdd7c551f67 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 1 May 2017 19:55:43 +0200 Subject: [PATCH 642/809] nrf5/modules/music: Removing c++ extern definition. Updating include list in modmusic.c. Removing module name from module struct. --- nrf5/modules/music/modmusic.c | 17 +++++------------ nrf5/modules/music/modmusic.h | 4 ---- 2 files changed, 5 insertions(+), 16 deletions(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index 95a3f33c77..f2dd166432 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -24,18 +24,14 @@ * THE SOFTWARE. */ -#include "microbitobj.h" -#include "microbitmusic.h" - -extern "C" { - +// #include "microbitobj.h" +// #include "microbitmusic.h" +#include "py/obj.h" #include "py/runtime.h" #include "py/objstr.h" #include "py/mphal.h" -#include "modmicrobit.h" -#include "microbit/microbitobj.h" -#include "microbit/microbitpin.h" -#include "lib/pwm.h" +#include "modmusic.h" +#include "musictunes.h" #define DEFAULT_BPM 120 #define DEFAULT_TICKS 4 // i.e. 4 ticks per beat @@ -474,8 +470,5 @@ STATIC MP_DEFINE_CONST_DICT(microbit_music_locals_dict, microbit_music_locals_di const mp_obj_module_t music_module = { .base = { &mp_type_module }, - .name = MP_QSTR_music, .globals = (mp_obj_dict_t*)µbit_music_locals_dict, }; - -} diff --git a/nrf5/modules/music/modmusic.h b/nrf5/modules/music/modmusic.h index 530c414593..a78588bb71 100644 --- a/nrf5/modules/music/modmusic.h +++ b/nrf5/modules/music/modmusic.h @@ -1,10 +1,6 @@ #ifndef __MICROPY_INCLUDED_MICROBIT_MUSIC_H__ #define __MICROPY_INCLUDED_MICROBIT_MUSIC_H__ -extern "C" { - void microbit_music_tick(void); -} - #endif // __MICROPY_INCLUDED_MICROBIT_MUSIC_H__ From 40b37227a0bb3845fb902562db5eb4ccaa6c89b9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 2 May 2017 01:07:52 +0200 Subject: [PATCH 643/809] nrf5/drivers/pwm: Work in progress commit of soft PWM from microbit repo. --- nrf5/drivers/pwm.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/nrf5/drivers/pwm.c b/nrf5/drivers/pwm.c index d873b703ec..5f873751b1 100644 --- a/nrf5/drivers/pwm.c +++ b/nrf5/drivers/pwm.c @@ -25,11 +25,19 @@ */ #include "stddef.h" -#include "lib/ticker.h" -#include "nrf_gpio.h" #include "py/runtime.h" #include "py/gc.h" -#include "PinNames.h" +#include "hal_timer.h" +#include "hal_gpio.h" +#include "pin.h" + +#define CYCLES_PER_MICROSECONDS 16 + +#define MICROSECONDS_PER_TICK 16 +#define CYCLES_PER_TICK (CYCLES_PER_MICROSECONDS*MICROSECONDS_PER_TICK) +// This must be an integer multiple of MICROSECONDS_PER_TICK +#define MICROSECONDS_PER_MACRO_TICK 6000 +#define MILLISECONDS_PER_MACRO_TICK 6 #define PWM_TICKER_INDEX 2 @@ -140,10 +148,10 @@ int32_t pwm_callback(void) { int32_t tnow = (event->time*events->period)>>10; do { if (event->turn_on) { - nrf_gpio_pin_set(event->pin); + hal_gpio_pin_set(0, event->pin); next_event++; } else { - nrf_gpio_pins_clear(events->all_pins); + hal_gpio_out_clear(0, events->all_pins); next_event = 0; tnow = 0; if (pending_events) { @@ -159,11 +167,11 @@ int32_t pwm_callback(void) { } void pwm_start(void) { - set_ticker_callback(PWM_TICKER_INDEX, pwm_callback, 120); + // set_ticker_callback(PWM_TICKER_INDEX, pwm_callback, 120); } void pwm_stop(void) { - clear_ticker_callback(PWM_TICKER_INDEX); + // clear_ticker_callback(PWM_TICKER_INDEX); } static void pwm_set_period_ticks(int32_t ticks) { @@ -200,7 +208,7 @@ void pwm_set_duty_cycle(int32_t pin, uint32_t value) { old_events = active_events; } if (((1<all_pins) == 0) { - nrf_gpio_cfg_output(pin); + hal_gpio_cfg_pin(0, pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED); } int ev = find_pin_in_events(old_events, pin); pwm_events *events; @@ -237,5 +245,5 @@ void pwm_release(int32_t pin) { return; // If i >= 0 it means that `ev` is in RAM, so it safe to discard the const qualifier ((pwm_events *)ev)->events[i].pin = 31; - nrf_gpio_pin_clear(pin); + hal_gpio_pin_clear(0, pin); } From 57442c2b25ca5b362036493fadb0d24be634426d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 2 May 2017 01:09:59 +0200 Subject: [PATCH 644/809] nrf5/modules/music: Updating music module to use pin_obj_t instad of microbit_pin_obj_t. Update include to drivers/pwm.h to resolve some undefined functions. --- nrf5/modules/music/modmusic.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index f2dd166432..e8a2c0ada5 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -32,6 +32,7 @@ #include "py/mphal.h" #include "modmusic.h" #include "musictunes.h" +#include "drivers/pwm.h" #define DEFAULT_BPM 120 #define DEFAULT_TICKS 4 // i.e. 4 ticks per beat @@ -53,7 +54,7 @@ typedef struct _music_data_t { uint32_t async_wait_ticks; uint16_t async_notes_len; uint16_t async_notes_index; - const microbit_pin_obj_t *async_pin; + const pin_obj_t *async_pin; mp_obj_t async_note; } music_data_t; @@ -67,7 +68,7 @@ enum { extern uint32_t ticks; -STATIC uint32_t start_note(const char *note_str, size_t note_len, const microbit_pin_obj_t *pin); +STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_t *pin); void microbit_music_tick(void) { if (music_data == NULL) { @@ -137,7 +138,7 @@ STATIC void wait_async_music_idle(void) { } } -STATIC uint32_t start_note(const char *note_str, size_t note_len, const microbit_pin_obj_t *pin) { +STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_t *pin) { pwm_set_duty_cycle(pin->name, 128); // [NOTE](#|b)(octave)(:length) @@ -268,7 +269,7 @@ STATIC mp_obj_t microbit_music_get_tempo(void) { MP_DEFINE_CONST_FUN_OBJ_0(microbit_music_get_tempo_obj, microbit_music_get_tempo); STATIC mp_obj_t microbit_music_stop(mp_uint_t n_args, const mp_obj_t *args) { - const microbit_pin_obj_t *pin; + const pin_obj_t *pin; if (n_args == 0) { pin = µbit_p0_obj; } else { @@ -316,7 +317,7 @@ STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, music_data->async_pin = NULL; // get the pin to play on - const microbit_pin_obj_t *pin = microbit_obj_get_pin(args[1].u_obj); + const pin_obj_t *pin = microbit_obj_get_pin(args[1].u_obj); microbit_obj_pin_acquire(pin, microbit_pin_mode_music); // start the tune running in the background @@ -360,7 +361,7 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, // get the parameters mp_uint_t frequency = args[0].u_int; mp_int_t duration = args[1].u_int; - const microbit_pin_obj_t *pin = microbit_obj_get_pin(args[2].u_obj); + const pin_obj_t *pin = microbit_obj_get_pin(args[2].u_obj); // Update pin modes microbit_obj_pin_free(music_data->async_pin); From d170ca5d03c0b7d121af69a6be0f68bb2945ee40 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 2 May 2017 21:50:46 +0200 Subject: [PATCH 645/809] nrf5/modules/music: Commenting out backend function calls in modmusic.c to make module compile for now. --- nrf5/modules/music/modmusic.c | 45 +++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index e8a2c0ada5..a02e3d0518 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -66,7 +66,8 @@ enum { #define music_data MP_STATE_PORT(music_data) -extern uint32_t ticks; +// extern uint32_t ticks; +static uint32_t ticks = 0; // TODO STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_t *pin); @@ -98,7 +99,7 @@ void microbit_music_tick(void) { music_data->async_notes_index = 0; } else { music_data->async_state = ASYNC_MUSIC_STATE_IDLE; - microbit_obj_pin_free(music_data->async_pin); +// TODO: microbit_obj_pin_free(music_data->async_pin); music_data->async_pin = NULL; return; } @@ -269,16 +270,16 @@ STATIC mp_obj_t microbit_music_get_tempo(void) { MP_DEFINE_CONST_FUN_OBJ_0(microbit_music_get_tempo_obj, microbit_music_get_tempo); STATIC mp_obj_t microbit_music_stop(mp_uint_t n_args, const mp_obj_t *args) { - const pin_obj_t *pin; +// TODO: const pin_obj_t *pin; if (n_args == 0) { - pin = µbit_p0_obj; +// TODO:pin = µbit_p0_obj; } else { - pin = microbit_obj_get_pin(args[0]); +// TODO:pin = microbit_obj_get_pin(args[0]); } // Raise exception if the pin we are trying to stop is not in a compatible mode. - microbit_obj_pin_acquire(pin, microbit_pin_mode_music); - pwm_set_duty_cycle(pin->name, 0); - microbit_obj_pin_free(pin); +// TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music); +// TODO: pwm_set_duty_cycle(pin->name, 0); +// TODO: microbit_obj_pin_free(pin); music_data->async_pin = NULL; music_data->async_state = ASYNC_MUSIC_STATE_IDLE; @@ -289,7 +290,8 @@ MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(microbit_music_stop_obj, 0, 1, microbit_musi STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { static const mp_arg_t allowed_args[] = { { MP_QSTR_music, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, - { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, +// TODO:{ MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, + { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_wait, MP_ARG_BOOL, {.u_bool = true} }, { MP_QSTR_loop, MP_ARG_BOOL, {.u_bool = false} }, }; @@ -313,12 +315,12 @@ STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, } // Release the previous pin - microbit_obj_pin_free(music_data->async_pin); +// TODO: microbit_obj_pin_free(music_data->async_pin); music_data->async_pin = NULL; // get the pin to play on - const pin_obj_t *pin = microbit_obj_get_pin(args[1].u_obj); - microbit_obj_pin_acquire(pin, microbit_pin_mode_music); +// TODO: const pin_obj_t *pin = microbit_obj_get_pin(args[1].u_obj); +// TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music); // start the tune running in the background music_data->async_state = ASYNC_MUSIC_STATE_IDLE; @@ -334,7 +336,7 @@ STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, } else { music_data->async_note = items; } - music_data->async_pin = pin; +// TODO: music_data->async_pin = pin; music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE; if (args[2].u_bool) { @@ -350,7 +352,8 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, static const mp_arg_t allowed_args[] = { { MP_QSTR_frequency, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} }, { MP_QSTR_duration, MP_ARG_INT, {.u_int = -1} }, - { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, +//TODO: { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, + { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_wait, MP_ARG_BOOL, {.u_bool = true} }, }; @@ -361,18 +364,18 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, // get the parameters mp_uint_t frequency = args[0].u_int; mp_int_t duration = args[1].u_int; - const pin_obj_t *pin = microbit_obj_get_pin(args[2].u_obj); +//TODO: const pin_obj_t *pin = microbit_obj_get_pin(args[2].u_obj); // Update pin modes - microbit_obj_pin_free(music_data->async_pin); +//TODO: microbit_obj_pin_free(music_data->async_pin); music_data->async_pin = NULL; - microbit_obj_pin_acquire(pin, microbit_pin_mode_music); +//TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music); bool wait = args[3].u_bool; - pwm_set_duty_cycle(pin->name, 128); +//TODO: pwm_set_duty_cycle(pin->name, 128); if (frequency == 0) { - pwm_release(pin->name); +//TODO: pwm_release(pin->name); } else if (pwm_set_period_us(1000000/frequency)) { - pwm_release(pin->name); +//TODO: pwm_release(pin->name); nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "invalid pitch")); } if (duration >= 0) { @@ -383,7 +386,7 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, music_data->async_notes_len = 0; music_data->async_notes_index = 0; music_data->async_note = NULL; - music_data->async_pin = pin; +//TODO: music_data->async_pin = pin; music_data->async_state = ASYNC_MUSIC_STATE_ARTICULATE; if (wait) { From a7f10336e106122fbf014573d35d2c28178ff5a1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 2 May 2017 22:40:31 +0200 Subject: [PATCH 646/809] nrf5/modules/music: backing up porting progress in modmusic.c. --- nrf5/modules/music/modmusic.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index a02e3d0518..15e71e2b4a 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -33,6 +33,8 @@ #include "modmusic.h" #include "musictunes.h" #include "drivers/pwm.h" +#include "pin.h" +#include "genhdr/pins.h" #define DEFAULT_BPM 120 #define DEFAULT_TICKS 4 // i.e. 4 ticks per beat @@ -270,12 +272,17 @@ STATIC mp_obj_t microbit_music_get_tempo(void) { MP_DEFINE_CONST_FUN_OBJ_0(microbit_music_get_tempo_obj, microbit_music_get_tempo); STATIC mp_obj_t microbit_music_stop(mp_uint_t n_args, const mp_obj_t *args) { -// TODO: const pin_obj_t *pin; + const pin_obj_t *pin; if (n_args == 0) { -// TODO:pin = µbit_p0_obj; +#ifdef MICROPY_HW_MUSIC_PIN + pin = &MICROPY_HW_MUSIC_PIN; +#else + nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "pin parameter not given")); +#endif } else { -// TODO:pin = microbit_obj_get_pin(args[0]); + pin = (pin_obj_t *)args[0]; } + (void)pin; // Raise exception if the pin we are trying to stop is not in a compatible mode. // TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music); // TODO: pwm_set_duty_cycle(pin->name, 0); @@ -291,7 +298,7 @@ STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, static const mp_arg_t allowed_args[] = { { MP_QSTR_music, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, // TODO:{ MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, - { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_wait, MP_ARG_BOOL, {.u_bool = true} }, { MP_QSTR_loop, MP_ARG_BOOL, {.u_bool = false} }, }; @@ -353,7 +360,7 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, { MP_QSTR_frequency, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} }, { MP_QSTR_duration, MP_ARG_INT, {.u_int = -1} }, //TODO: { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, - { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_wait, MP_ARG_BOOL, {.u_bool = true} }, }; @@ -364,8 +371,8 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, // get the parameters mp_uint_t frequency = args[0].u_int; mp_int_t duration = args[1].u_int; -//TODO: const pin_obj_t *pin = microbit_obj_get_pin(args[2].u_obj); - + const pin_obj_t *pin = args[2].u_obj; + (void)pin; // Update pin modes //TODO: microbit_obj_pin_free(music_data->async_pin); music_data->async_pin = NULL; From 311ae77dc0a16a35eb8641ee0d7702d22b84fc76 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 4 May 2017 00:18:05 +0200 Subject: [PATCH 647/809] nrf5/modules/music: Backing up progress in modmusic. --- nrf5/modules/music/modmusic.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index 15e71e2b4a..f06264a474 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -326,8 +326,17 @@ STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, music_data->async_pin = NULL; // get the pin to play on -// TODO: const pin_obj_t *pin = microbit_obj_get_pin(args[1].u_obj); -// TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music); + const pin_obj_t *pin; + if (n_args >= 2) { +#ifdef MICROPY_HW_MUSIC_PIN + pin = &MICROPY_HW_MUSIC_PIN; +#else + nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "pin parameter not given")); +#endif + } else { + pin = (pin_obj_t *)args[1].u_obj; + } + // TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music); // start the tune running in the background music_data->async_state = ASYNC_MUSIC_STATE_IDLE; @@ -343,7 +352,7 @@ STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, } else { music_data->async_note = items; } -// TODO: music_data->async_pin = pin; + music_data->async_pin = pin; music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE; if (args[2].u_bool) { @@ -393,7 +402,7 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, music_data->async_notes_len = 0; music_data->async_notes_index = 0; music_data->async_note = NULL; -//TODO: music_data->async_pin = pin; + music_data->async_pin = pin; music_data->async_state = ASYNC_MUSIC_STATE_ARTICULATE; if (wait) { From 10cbc83cf09c0d9d8be58487b3843eed4eb80f05 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 21:10:18 +0200 Subject: [PATCH 648/809] nrf5/pwm: Updating config name of PWM to hardware PWM to prepare for introduction of soft variant. --- nrf5/boards/feather52/mpconfigboard.h | 2 +- nrf5/boards/pca10040/mpconfigboard.h | 2 +- nrf5/boards/pca10056/mpconfigboard.h | 2 +- nrf5/main.c | 4 ++-- nrf5/modules/machine/modmachine.c | 4 ++-- nrf5/modules/machine/pwm.c | 4 ++-- nrf5/mpconfigport.h | 4 ++-- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/nrf5/boards/feather52/mpconfigboard.h b/nrf5/boards/feather52/mpconfigboard.h index 3116078641..01fca8a08a 100644 --- a/nrf5/boards/feather52/mpconfigboard.h +++ b/nrf5/boards/feather52/mpconfigboard.h @@ -30,7 +30,7 @@ #define MICROPY_HW_MCU_NAME "NRF52832" #define MICROPY_PY_SYS_PLATFORM "nrf52" -#define MICROPY_PY_MACHINE_PWM (1) +#define MICROPY_PY_MACHINE_HW_PWM (1) #define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 50b3da7fc3..57f686c057 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -30,7 +30,7 @@ #define MICROPY_HW_MCU_NAME "NRF52832" #define MICROPY_PY_SYS_PLATFORM "nrf52-DK" -#define MICROPY_PY_MACHINE_PWM (1) +#define MICROPY_PY_MACHINE_HW_PWM (1) #define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index f111e737d6..d5d685177a 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -30,7 +30,7 @@ #define MICROPY_HW_MCU_NAME "NRF52840" #define MICROPY_PY_SYS_PLATFORM "nrf52840-PDK" -#define MICROPY_PY_MACHINE_PWM (1) +#define MICROPY_PY_MACHINE_HW_PWM (1) #define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) diff --git a/nrf5/main.c b/nrf5/main.c index 348f77fcac..af384de492 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -48,7 +48,7 @@ #include "spi.h" #include "i2c.h" #include "rtc.h" -#if MICROPY_PY_MACHINE_PWM +#if MICROPY_PY_MACHINE_HW_PWM #include "pwm.h" #endif #include "timer.h" @@ -110,7 +110,7 @@ int main(int argc, char **argv) { i2c_init0(); #endif -#if MICROPY_PY_MACHINE_PWM +#if MICROPY_PY_MACHINE_HW_PWM pwm_init0(); #endif diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 8f78a12606..5e24ca9cd1 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -41,7 +41,7 @@ #include "uart.h" #include "spi.h" #include "i2c.h" -#if MICROPY_PY_MACHINE_PWM +#if MICROPY_PY_MACHINE_HW_PWM #include "pwm.h" #endif #if MICROPY_PY_MACHINE_ADC @@ -213,7 +213,7 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { #if MICROPY_PY_MACHINE_RTC { MP_OBJ_NEW_QSTR(MP_QSTR_RTC), (mp_obj_t)&machine_rtc_type }, #endif -#if MICROPY_PY_MACHINE_PWM +#if MICROPY_PY_MACHINE_HW_PWM { MP_OBJ_NEW_QSTR(MP_QSTR_PWM), (mp_obj_t)&machine_hard_pwm_type }, #endif #if MICROPY_PY_MACHINE_TEMP diff --git a/nrf5/modules/machine/pwm.c b/nrf5/modules/machine/pwm.c index 4b6f1a858d..6dfa9aa418 100644 --- a/nrf5/modules/machine/pwm.c +++ b/nrf5/modules/machine/pwm.c @@ -31,7 +31,7 @@ #include "py/runtime.h" #include "py/mphal.h" -#if MICROPY_PY_MACHINE_PWM +#if MICROPY_PY_MACHINE_HW_PWM #include "pin.h" #include "genhdr/pins.h" @@ -329,4 +329,4 @@ const mp_obj_type_t machine_hard_pwm_type = { .locals_dict = (mp_obj_t)&machine_pwm_locals_dict, }; -#endif // MICROPY_PY_MACHINE_PWM +#endif // MICROPY_PY_MACHINE_HW_PWM diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 98e41ca972..939c0d61fc 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -127,8 +127,8 @@ #define MICROPY_PY_MACHINE_HW_SPI (1) #endif -#ifndef MICROPY_PY_MACHINE_PWM -#define MICROPY_PY_MACHINE_PWM (0) +#ifndef MICROPY_PY_MACHINE_HW_PWM +#define MICROPY_PY_MACHINE_HW_PWM (0) #endif #ifndef MICROPY_PY_MACHINE_TIMER From ad6a1d91367fef0c1562eda90fb7c2cdaa3d695e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 21:11:21 +0200 Subject: [PATCH 649/809] nrf5/boards: Removing PWM config set to 0 from pca10001 board. Config will later be re-introduced as SOFT_PWM variant. --- nrf5/boards/pca10001/mpconfigboard.h | 1 - 1 file changed, 1 deletion(-) diff --git a/nrf5/boards/pca10001/mpconfigboard.h b/nrf5/boards/pca10001/mpconfigboard.h index 985eb31a29..280c4764d9 100644 --- a/nrf5/boards/pca10001/mpconfigboard.h +++ b/nrf5/boards/pca10001/mpconfigboard.h @@ -31,7 +31,6 @@ #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" #define MICROPY_PY_MACHINE_HW_SPI (0) -#define MICROPY_PY_MACHINE_PWM (0) #define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_HW_HAS_SWITCH (0) From 94efa02084e2eb2d293cf812ffc93a3880d0a6da Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 21:14:34 +0200 Subject: [PATCH 650/809] nrf5: Adding new configuration called MICROPY_PY_MACHINE_SOFT_PWM to mpconfigport.h. This config will enable software defined PWM using timer instead of using dedicated PWM hardware. Aimed to be used in nrf51 targets. --- nrf5/mpconfigport.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 939c0d61fc..516925f88d 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -131,6 +131,10 @@ #define MICROPY_PY_MACHINE_HW_PWM (0) #endif +#ifndef MICROPY_PY_MACHINE_SOFT_PWM +#define MICROPY_PY_MACHINE_SOFT_PWM (0) +#endif + #ifndef MICROPY_PY_MACHINE_TIMER #define MICROPY_PY_MACHINE_TIMER (0) #endif From a4513f01592628599f3461fcc5862902d3da7ea4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 21:20:08 +0200 Subject: [PATCH 651/809] nrf5/hal/gpio: Add function to clear output register using a pin mask. --- nrf5/hal/hal_gpio.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/hal/hal_gpio.h b/nrf5/hal/hal_gpio.h index 2cc73a5fe9..06fadcbef9 100644 --- a/nrf5/hal/hal_gpio.h +++ b/nrf5/hal/hal_gpio.h @@ -78,6 +78,10 @@ static inline void hal_gpio_out_set(uint8_t port, uint32_t pin_mask) { GPIO_BASE(port)->OUTSET = pin_mask; } +static inline void hal_gpio_out_clear(uint8_t port, uint32_t pin_mask) { + GPIO_BASE(port)->OUTCLR = pin_mask; +} + static inline void hal_gpio_pin_set(uint8_t port, uint32_t pin) { GPIO_BASE(port)->OUTSET = (1 << pin); } From 8d06dd3281b53e62c604ed2af3c03b02a88844dc Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 21:21:57 +0200 Subject: [PATCH 652/809] nrf5/drivers/pwm: Updating soft PWM driver to only be included if SOFT_PWM config is set. --- nrf5/drivers/pwm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/drivers/pwm.c b/nrf5/drivers/pwm.c index 5f873751b1..77ef8be2ce 100644 --- a/nrf5/drivers/pwm.c +++ b/nrf5/drivers/pwm.c @@ -24,6 +24,8 @@ * THE SOFTWARE. */ +#if MICROPY_PY_MACHINE_SOFT_PWM + #include "stddef.h" #include "py/runtime.h" #include "py/gc.h" @@ -247,3 +249,5 @@ void pwm_release(int32_t pin) { ((pwm_events *)ev)->events[i].pin = 31; hal_gpio_pin_clear(0, pin); } + +#endif // MICROPY_PY_MACHINE_SOFT_PWM From c3ccef800d588f91be28ffb4d91b7921af15de35 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 21:22:53 +0200 Subject: [PATCH 653/809] nrf5/modules/music: Backing up progress in music module. --- nrf5/modules/music/modmusic.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index f06264a474..fb73b6e7a7 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -24,6 +24,8 @@ * THE SOFTWARE. */ +#if MICROPY_PY_MACHINE_SOFT_PWM || MICROPY_PY_MACHINE_HW_PWM + // #include "microbitobj.h" // #include "microbitmusic.h" #include "py/obj.h" @@ -91,7 +93,7 @@ void microbit_music_tick(void) { if (music_data->async_state == ASYNC_MUSIC_STATE_ARTICULATE) { // turn off output and rest - pwm_set_duty_cycle(music_data->async_pin->name, 0); + pwm_set_duty_cycle(music_data->async_pin->pin, 0); // TODO: remove pin setting. music_data->async_wait_ticks = ticks + ARTICULATION_MS; music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE; } else if (music_data->async_state == ASYNC_MUSIC_STATE_NEXT_NOTE) { @@ -114,7 +116,7 @@ void microbit_music_tick(void) { } if (note == mp_const_none) { // a rest (is this even used anymore?) - pwm_set_duty_cycle(music_data->async_pin->name, 0); + pwm_set_duty_cycle(music_data->async_pin->pin, 0); // TODO: remove pin setting. music_data->async_wait_ticks = 60000 / music_data->bpm; music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE; } else { @@ -135,14 +137,14 @@ STATIC void wait_async_music_idle(void) { // allow CTRL-C to stop the music if (MP_STATE_VM(mp_pending_exception) != MP_OBJ_NULL) { music_data->async_state = ASYNC_MUSIC_STATE_IDLE; - pwm_set_duty_cycle(music_data->async_pin->name, 0); + pwm_set_duty_cycle(music_data->async_pin->pin, 0); // TODO: remove pin setting. break; } } } STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_t *pin) { - pwm_set_duty_cycle(pin->name, 128); + pwm_set_duty_cycle(pin->pin, 128); // TODO: remove pin setting. // [NOTE](#|b)(octave)(:length) // technically, c4 is middle c, so we'll go with that... @@ -240,7 +242,7 @@ STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_ } pwm_set_period_us(period); } else { - pwm_set_duty_cycle(pin->name, 0); + pwm_set_duty_cycle(pin->pin, 0); // TODO: remove pin setting. } // Cut off a short time from end of note so we hear articulation. @@ -285,7 +287,7 @@ STATIC mp_obj_t microbit_music_stop(mp_uint_t n_args, const mp_obj_t *args) { (void)pin; // Raise exception if the pin we are trying to stop is not in a compatible mode. // TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music); -// TODO: pwm_set_duty_cycle(pin->name, 0); + pwm_set_duty_cycle(pin->pin, 0); // TODO: remove pin setting. // TODO: microbit_obj_pin_free(pin); music_data->async_pin = NULL; music_data->async_state = ASYNC_MUSIC_STATE_IDLE; @@ -387,11 +389,11 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, music_data->async_pin = NULL; //TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music); bool wait = args[3].u_bool; -//TODO: pwm_set_duty_cycle(pin->name, 128); + pwm_set_duty_cycle(pin->pin, 128); // TODO: remove pin setting. if (frequency == 0) { //TODO: pwm_release(pin->name); } else if (pwm_set_period_us(1000000/frequency)) { -//TODO: pwm_release(pin->name); + pwm_release(pin->pin); // TODO: remove pin setting. nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "invalid pitch")); } if (duration >= 0) { @@ -492,3 +494,5 @@ const mp_obj_module_t music_module = { .base = { &mp_type_module }, .globals = (mp_obj_dict_t*)µbit_music_locals_dict, }; + +#endif // MICROPY_PY_MACHINE_SOFT_PWM || MICROPY_PY_MACHINE_HW_PWM From cf1c6939eacda140cbab9878d802d1a74337102f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 22:01:05 +0200 Subject: [PATCH 654/809] nrf5: Updating mpconfigport.h to include music module as builtin. Adding new configuration for enabling music module. Activating MODULE_BUILTIN_INIT in order to run music module init function on import. --- nrf5/mpconfigport.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 516925f88d..f871f31df1 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -84,6 +84,7 @@ #define MICROPY_PY_BUILTINS_HELP (1) #define MICROPY_PY_BUILTINS_HELP_TEXT nrf5_help_text #define MICROPY_PY_BUILTINS_HELP_MODULES (1) +#define MICROPY_MODULE_BUILTIN_INIT (1) #define MICROPY_PY_ALL_SPECIAL_METHODS (0) #define MICROPY_PY_MICROPYTHON_MEM_INFO (1) #define MICROPY_PY_ARRAY_SLICE_ASSIGN (0) @@ -115,6 +116,10 @@ #define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) #define MICROPY_PY_FRAMEBUF (0) +#ifndef MICROPY_PY_MUSIC +#define MICROPY_PY_MUSIC (0) +#endif + #ifndef MICROPY_PY_MACHINE_ADC #define MICROPY_PY_MACHINE_ADC (0) #endif @@ -181,6 +186,7 @@ extern const struct _mp_obj_module_t machine_module; extern const struct _mp_obj_module_t mp_module_utime; extern const struct _mp_obj_module_t mp_module_uos; extern const struct _mp_obj_module_t mp_module_ubluepy; +extern const struct _mp_obj_module_t music_module; #if MICROPY_PY_UBLUEPY #define UBLUEPY_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy), (mp_obj_t)&mp_module_ubluepy }, @@ -188,6 +194,12 @@ extern const struct _mp_obj_module_t mp_module_ubluepy; #define UBLUEPY_MODULE #endif +#if MICROPY_PY_MUSIC +#define MUSIC_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_music), (mp_obj_t)&music_module }, +#else +#define MUSIC_MODULE +#endif + #if BLUETOOTH_SD extern const struct _mp_obj_module_t ble_module; @@ -198,6 +210,7 @@ extern const struct _mp_obj_module_t ble_module; { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&mp_module_utime }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ + MUSIC_MODULE \ UBLUEPY_MODULE \ @@ -208,6 +221,8 @@ extern const struct _mp_obj_module_t ble_module; { MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ + MUSIC_MODULE \ + #endif // BLUETOOTH_SD @@ -244,6 +259,11 @@ extern const struct _mp_obj_module_t ble_module; \ /* list of registered NICs */ \ mp_obj_list_t mod_network_nic_list; \ + \ + /* microbit modules */ \ + struct _music_data_t *music_data; \ + const struct _pwm_events *pwm_active_events; \ + const struct _pwm_events *pwm_pending_events; \ #define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len) From 24e902aa8fa3df93abdcdb013210e3add763a395 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 22:01:47 +0200 Subject: [PATCH 655/809] nrf5/drivers/pwm: Including mphal.h before config guard in pwm.c. --- nrf5/drivers/pwm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/drivers/pwm.c b/nrf5/drivers/pwm.c index 77ef8be2ce..8d6ab0fa4f 100644 --- a/nrf5/drivers/pwm.c +++ b/nrf5/drivers/pwm.c @@ -24,6 +24,8 @@ * THE SOFTWARE. */ +#include "py/mphal.h" + #if MICROPY_PY_MACHINE_SOFT_PWM #include "stddef.h" From a84ed760b527ddb7214454e4cb8feb69796cc7f2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 22:03:33 +0200 Subject: [PATCH 656/809] nrf5/modules/music: Including mphal.h before config guard in modmusic.c. Also changed name on config guard to MICROPY_PY_MUSIC. Missing PWM functions during linkage will show up if PWM module has not not configured. --- nrf5/modules/music/modmusic.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index fb73b6e7a7..31e2bd2100 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -24,14 +24,15 @@ * THE SOFTWARE. */ -#if MICROPY_PY_MACHINE_SOFT_PWM || MICROPY_PY_MACHINE_HW_PWM +#include "py/mphal.h" + +#if MICROPY_PY_MUSIC // #include "microbitobj.h" // #include "microbitmusic.h" #include "py/obj.h" #include "py/runtime.h" #include "py/objstr.h" -#include "py/mphal.h" #include "modmusic.h" #include "musictunes.h" #include "drivers/pwm.h" @@ -495,4 +496,4 @@ const mp_obj_module_t music_module = { .globals = (mp_obj_dict_t*)µbit_music_locals_dict, }; -#endif // MICROPY_PY_MACHINE_SOFT_PWM || MICROPY_PY_MACHINE_HW_PWM +#endif // MICROPY_PY_MUSIC From d3509517f59164ce5462eec50e9c273ddd1ac727 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 22:05:23 +0200 Subject: [PATCH 657/809] nrf5/modules/music: Adding config guard in musictunes.c and adding import of mphal.h. --- nrf5/modules/music/musictunes.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nrf5/modules/music/musictunes.c b/nrf5/modules/music/musictunes.c index beaeea0487..895c40a1ca 100644 --- a/nrf5/modules/music/musictunes.c +++ b/nrf5/modules/music/musictunes.c @@ -29,8 +29,11 @@ * THE SOFTWARE. */ +#include "py/mphal.h" #include "py/objtuple.h" +#if MICROPY_PY_MUSIC + #define N(q) MP_OBJ_NEW_QSTR(MP_QSTR_ ## q) #define T(name, ...) const mp_obj_tuple_t microbit_music_tune_ ## name ## _obj = {{&mp_type_tuple}, .len = (sizeof((mp_obj_t[]){__VA_ARGS__})/sizeof(mp_obj_t)), .items = {__VA_ARGS__}}; @@ -157,3 +160,5 @@ T(power_down, #undef N #undef T + +#endif // MICROPY_PY_MUSIC From 64f91e01acabe9801d1f5f8ba3dfbf27c4d745b6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 22:06:25 +0200 Subject: [PATCH 658/809] nrf5/Makefile: Adding drivers/pwm.c and modules/music files to the source file list. --- nrf5/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 84b149c665..fa24ae0fb2 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -126,6 +126,7 @@ SRC_C += \ gccollect.c \ pin_named_pins.c \ fatfs_port.c \ + drivers/pwm.c \ DRIVERS_SRC_C += $(addprefix modules/,\ machine/modmachine.c \ @@ -152,6 +153,8 @@ DRIVERS_SRC_C += $(addprefix modules/,\ ubluepy/ubluepy_descriptor.c \ ubluepy/ubluepy_scanner.c \ ubluepy/ubluepy_scan_entry.c \ + music/modmusic.c \ + music/musictunes.c \ ) #ifeq ($(SD), ) From 130a00fdeb15b4aa735c85e542d7abde5c9ea78b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 22:10:02 +0200 Subject: [PATCH 659/809] nrf5/hal/timer: Adding start/stop template functions to hal_timer.h/.c --- nrf5/hal/hal_timer.c | 6 ++++++ nrf5/hal/hal_timer.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/nrf5/hal/hal_timer.c b/nrf5/hal/hal_timer.c index ac0d20846c..3046f74383 100644 --- a/nrf5/hal/hal_timer.c +++ b/nrf5/hal/hal_timer.c @@ -33,6 +33,12 @@ void hal_timer_init(hal_timer_conf_t const * p_timer_conf) { } +void hal_timer_start(uint8_t id) { +} + +void hal_timer_stop(uint8_t id) { +} + void TIMER0_IRQHandler(void) { } diff --git a/nrf5/hal/hal_timer.h b/nrf5/hal/hal_timer.h index 245a33955b..32e53c498e 100644 --- a/nrf5/hal/hal_timer.h +++ b/nrf5/hal/hal_timer.h @@ -64,4 +64,8 @@ typedef struct { void hal_timer_init(hal_timer_conf_t const * p_timer_config); +void hal_timer_start(uint8_t id); + +void hal_timer_stop(uint8_t id); + #endif // HAL_TIMER_H__ From bf796998103359e7f879f502fd79e68db7d94654 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 22:16:59 +0200 Subject: [PATCH 660/809] nrf5/boards: Adding micro:bit default music pin definition. Also adding config flag for enabling pwm machine module. --- nrf5/boards/microbit/mpconfigboard.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index f5bfdba88a..3c226a5b76 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -30,6 +30,7 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51" +#define MICROPY_PY_MACHINE_SOFT_PWM (0) #define MICROPY_PY_MACHINE_HW_SPI (1) #define MICROPY_PY_MACHINE_TIMER (1) #define MICROPY_PY_MACHINE_RTC (1) @@ -68,4 +69,7 @@ #define MICROPY_HW_SPI0_MOSI (pin_A15) #define MICROPY_HW_SPI0_MISO (pin_A14) +// micro:bit music pin +#define MICROPY_HW_MUSIC_PIN (pin_A3) + #define HELP_TEXT_BOARD_LED "1,2,3,4" From 9e6cca66b46c1ef616fd5d75f6b9201ac9c4bb78 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 23:09:15 +0200 Subject: [PATCH 661/809] nrf5/modules/timer: Adding timer module to modmachine. --- nrf5/modules/machine/modmachine.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 5e24ca9cd1..11ce93e628 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -41,6 +41,7 @@ #include "uart.h" #include "spi.h" #include "i2c.h" +#include "timer.h" #if MICROPY_PY_MACHINE_HW_PWM #include "pwm.h" #endif @@ -213,11 +214,14 @@ STATIC const mp_map_elem_t machine_module_globals_table[] = { #if MICROPY_PY_MACHINE_RTC { MP_OBJ_NEW_QSTR(MP_QSTR_RTC), (mp_obj_t)&machine_rtc_type }, #endif +#if MICROPY_PY_MACHINE_TIMER + { MP_OBJ_NEW_QSTR(MP_QSTR_Timer), (mp_obj_t)&machine_timer_type }, +#endif #if MICROPY_PY_MACHINE_HW_PWM { MP_OBJ_NEW_QSTR(MP_QSTR_PWM), (mp_obj_t)&machine_hard_pwm_type }, #endif #if MICROPY_PY_MACHINE_TEMP - { MP_OBJ_NEW_QSTR(MP_QSTR_Temp), (mp_obj_t)&machine_temp_type }, + { MP_OBJ_NEW_QSTR(MP_QSTR_Temp), (mp_obj_t)&machine_temp_type }, #endif { MP_OBJ_NEW_QSTR(MP_QSTR_HARD_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_HARD) }, { MP_OBJ_NEW_QSTR(MP_QSTR_WDT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_WDT) }, From 2cf9e3e6250d75d865c18796b1ccfd7098d82c8f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 23:24:15 +0200 Subject: [PATCH 662/809] nrf5/modules/timer: Adding locals dict table and adding start/stop template functions. Also adding constants for oneshot and periodic to locals dict. --- nrf5/modules/machine/timer.c | 37 ++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index 16c466c89a..1e92549327 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -110,14 +110,47 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, return MP_OBJ_FROM_PTR(self); } +/// \method start(period) +/// Start the timer. +/// +STATIC mp_obj_t machine_timer_start(mp_obj_t self_in, mp_obj_t period_in) { + machine_timer_obj_t * self = MP_OBJ_TO_PTR(self_in); + (void)self; + // hal_timer_start(id); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_timer_start_obj, machine_timer_start); + +/// \method stop() +/// Stop the timer. +/// +STATIC mp_obj_t machine_timer_stop(mp_obj_t self_in) { + machine_timer_obj_t * self = MP_OBJ_TO_PTR(self_in); + (void)self; + // hal_timer_stop(id); + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_stop_obj, machine_timer_stop); + +STATIC const mp_map_elem_t machine_timer_locals_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_start), (mp_obj_t)(&machine_timer_start_obj) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)(&machine_timer_stop_obj) }, + + // constants + { MP_OBJ_NEW_QSTR(MP_QSTR_ONESHOT), MP_OBJ_NEW_SMALL_INT(0) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_PERIODIC), MP_OBJ_NEW_SMALL_INT(1) }, +}; + +STATIC MP_DEFINE_CONST_DICT(machine_timer_locals_dict, machine_timer_locals_dict_table); + const mp_obj_type_t machine_timer_type = { { &mp_type_type }, .name = MP_QSTR_Timer, .print = timer_print, .make_new = machine_timer_make_new, -#if 0 .locals_dict = (mp_obj_t)&machine_timer_locals_dict -#endif }; #endif // MICROPY_PY_MACHINE_TIMER From 1063a44ec6926be1d96629681650b8a710790645 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 23:31:14 +0200 Subject: [PATCH 663/809] nrf5/modules/timer: Remove test which is covered by timer_find() function in the line below. --- nrf5/modules/machine/timer.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index 1e92549327..3806fca7e0 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -95,12 +95,6 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { - // index -1 does not exist - return mp_const_none; - // TODO: raise exception - } - // get static peripheral object int timer_id = timer_find(args[ARG_NEW_id].u_obj); const machine_timer_obj_t *self = &machine_timer_obj[timer_id]; From 00d96f5695a3e579f0654c18f16953409a6baba3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 8 May 2017 23:32:42 +0200 Subject: [PATCH 664/809] nrf5/modules/timer: Fixing bug in timer_find(). Function allowed to locate index out of range and started to look up in config pointer (index == size of array). --- nrf5/modules/machine/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index 3806fca7e0..0eb35dc80e 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -65,7 +65,7 @@ void timer_init0(void) { STATIC int timer_find(mp_obj_t id) { // given an integer id int timer_id = mp_obj_get_int(id); - if (timer_id >= 0 && timer_id <= MP_ARRAY_SIZE(machine_timer_obj) + if (timer_id >= 0 && timer_id < MP_ARRAY_SIZE(machine_timer_obj) && machine_timer_obj[timer_id].p_config != NULL) { return timer_id; } From 54656044f76e9b42ea1b2bb2ce99b17a1410dbf8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 9 May 2017 22:54:30 +0200 Subject: [PATCH 665/809] nrf5: Syncing code with upstream master and converting all module and method tables to use MP_ROM macros. Also adding explicit casting of local dicts to (mp_obj_dict_t*). --- nrf5/bluetooth/modble.c | 12 +-- nrf5/boards/make-pins.py | 8 +- nrf5/modules/machine/adc.c | 8 +- nrf5/modules/machine/led.c | 10 +-- nrf5/modules/machine/modmachine.c | 56 ++++++------- nrf5/modules/machine/pin.c | 84 +++++++++---------- nrf5/modules/machine/pwm.c | 28 +++---- nrf5/modules/machine/rtc.c | 12 +-- nrf5/modules/machine/spi.c | 2 +- nrf5/modules/machine/temp.c | 6 +- nrf5/modules/machine/timer.c | 12 +-- nrf5/modules/machine/uart.c | 20 ++--- nrf5/modules/music/modmusic.c | 58 ++++++------- nrf5/modules/music/musictunes.c | 2 +- nrf5/modules/pyb/modpyb.c | 12 +-- nrf5/modules/ubluepy/modubluepy.c | 24 +++--- nrf5/modules/ubluepy/ubluepy_characteristic.c | 38 ++++----- nrf5/modules/ubluepy/ubluepy_constants.c | 80 +++++++++--------- nrf5/modules/ubluepy/ubluepy_delegate.c | 10 +-- nrf5/modules/ubluepy/ubluepy_descriptor.c | 6 +- nrf5/modules/ubluepy/ubluepy_peripheral.c | 46 +++++----- nrf5/modules/ubluepy/ubluepy_scan_entry.c | 12 +-- nrf5/modules/ubluepy/ubluepy_scanner.c | 6 +- nrf5/modules/ubluepy/ubluepy_service.c | 18 ++-- nrf5/modules/ubluepy/ubluepy_uuid.c | 8 +- nrf5/modules/uos/moduos.c | 40 ++++----- nrf5/mpconfigport.h | 38 ++++----- 27 files changed, 328 insertions(+), 328 deletions(-) diff --git a/nrf5/bluetooth/modble.c b/nrf5/bluetooth/modble.c index 565b88bebd..c5904275ff 100644 --- a/nrf5/bluetooth/modble.c +++ b/nrf5/bluetooth/modble.c @@ -86,12 +86,12 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_disable_obj, ble_obj_disable); STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_enabled_obj, ble_obj_enabled); STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_address_obj, ble_obj_address); -STATIC const mp_map_elem_t ble_module_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ble) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_enable), (mp_obj_t)&ble_obj_enable_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_disable), (mp_obj_t)&ble_obj_disable_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_enabled), (mp_obj_t)&ble_obj_enabled_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_address), (mp_obj_t)&ble_obj_address_obj}, +STATIC const mp_rom_map_elem_t ble_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_ble) }, + { MP_ROM_QSTR(MP_QSTR_enable), MP_ROM_PTR(&ble_obj_enable_obj) }, + { MP_ROM_QSTR(MP_QSTR_disable), MP_ROM_PTR(&ble_obj_disable_obj) }, + { MP_ROM_QSTR(MP_QSTR_enabled), MP_ROM_PTR(&ble_obj_enabled_obj) }, + { MP_ROM_QSTR(MP_QSTR_address), MP_ROM_PTR(&ble_obj_address_obj) }, }; diff --git a/nrf5/boards/make-pins.py b/nrf5/boards/make-pins.py index f8756a5d92..733bd8c33c 100644 --- a/nrf5/boards/make-pins.py +++ b/nrf5/boards/make-pins.py @@ -233,11 +233,11 @@ class Pins(object): self.board_pins.append(NamedPin(row[0], pin)) def print_named(self, label, named_pins): - print('STATIC const mp_map_elem_t pin_{:s}_pins_locals_dict_table[] = {{'.format(label)) + print('STATIC const mp_rom_map_elem_t pin_{:s}_pins_locals_dict_table[] = {{'.format(label)) for named_pin in named_pins: pin = named_pin.pin() if pin.is_board_pin(): - print(' {{ MP_OBJ_NEW_QSTR(MP_QSTR_{:s}), (mp_obj_t)&pin_{:s} }},'.format(named_pin.name(), pin.cpu_pin_name())) + print(' {{ MP_ROM_QSTR(MP_QSTR_{:s}), MP_ROM_PTR(&pin_{:s}) }},'.format(named_pin.name(), pin.cpu_pin_name())) print('};') print('MP_DEFINE_CONST_DICT(pin_{:s}_pins_locals_dict, pin_{:s}_pins_locals_dict_table);'.format(label, label)); @@ -305,8 +305,8 @@ class Pins(object): if len(mux_name) > mux_name_width: mux_name_width = len(mux_name) for mux_name in sorted(af_hdr_set): - key = 'MP_OBJ_NEW_QSTR(MP_QSTR_{}),'.format(mux_name) - val = 'MP_OBJ_NEW_SMALL_INT(GPIO_{})'.format(mux_name) + key = 'MP_ROM_QSTR(MP_QSTR_{}),'.format(mux_name) + val = 'MP_ROM_INT(GPIO_{})'.format(mux_name) print(' { %-*s %s },' % (mux_name_width + 26, key, val), file=af_const_file) diff --git a/nrf5/modules/machine/adc.c b/nrf5/modules/machine/adc.c index 2adb318b6e..c47e0d775f 100644 --- a/nrf5/modules/machine/adc.c +++ b/nrf5/modules/machine/adc.c @@ -123,12 +123,12 @@ mp_obj_t machine_adc_battery_level(void) { } STATIC MP_DEFINE_CONST_FUN_OBJ_0(mp_machine_adc_battery_level_obj, machine_adc_battery_level); -STATIC const mp_map_elem_t machine_adc_locals_dict_table[] = { +STATIC const mp_rom_map_elem_t machine_adc_locals_dict_table[] = { // instance methods - { MP_OBJ_NEW_QSTR(MP_QSTR_value), (mp_obj_t)&mp_machine_adc_value_obj }, + { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&mp_machine_adc_value_obj) }, // class methods - { MP_OBJ_NEW_QSTR(MP_QSTR_battery_level), (mp_obj_t)&mp_machine_adc_battery_level_obj }, + { MP_ROM_QSTR(MP_QSTR_battery_level), MP_ROM_PTR(&mp_machine_adc_battery_level_obj) }, }; STATIC MP_DEFINE_CONST_DICT(machine_adc_locals_dict, machine_adc_locals_dict_table); @@ -137,7 +137,7 @@ const mp_obj_type_t machine_adc_type = { { &mp_type_type }, .name = MP_QSTR_ADC, .make_new = machine_adc_make_new, - .locals_dict = (mp_obj_t)&machine_adc_locals_dict, + .locals_dict = (mp_obj_dict_t*)&machine_adc_locals_dict, .print = machine_adc_print, }; diff --git a/nrf5/modules/machine/led.c b/nrf5/modules/machine/led.c index 0c9bd8928a..a23ef4427b 100644 --- a/nrf5/modules/machine/led.c +++ b/nrf5/modules/machine/led.c @@ -138,10 +138,10 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_on_obj, led_obj_on); STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_off_obj, led_obj_off); STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_toggle_obj, led_obj_toggle); -STATIC const mp_map_elem_t led_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_on), (mp_obj_t)&led_obj_on_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_off), (mp_obj_t)&led_obj_off_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_toggle), (mp_obj_t)&led_obj_toggle_obj }, +STATIC const mp_rom_map_elem_t led_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_on), MP_ROM_PTR(&led_obj_on_obj) }, + { MP_ROM_QSTR(MP_QSTR_off), MP_ROM_PTR(&led_obj_off_obj) }, + { MP_ROM_QSTR(MP_QSTR_toggle), MP_ROM_PTR(&led_obj_toggle_obj) }, }; STATIC MP_DEFINE_CONST_DICT(led_locals_dict, led_locals_dict_table); @@ -151,6 +151,6 @@ const mp_obj_type_t pyb_led_type = { .name = MP_QSTR_LED, .print = led_obj_print, .make_new = led_obj_make_new, - .locals_dict = (mp_obj_t)&led_locals_dict, + .locals_dict = (mp_obj_dict_t*)&led_locals_dict, }; diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 11ce93e628..0901e6836b 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -187,51 +187,51 @@ STATIC mp_obj_t machine_disable_irq(void) { } MP_DEFINE_CONST_FUN_OBJ_0(machine_disable_irq_obj, machine_disable_irq); -STATIC const mp_map_elem_t machine_module_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_umachine) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_info), (mp_obj_t)&machine_info_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_reset), (mp_obj_t)&machine_reset_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_soft_reset), (mp_obj_t)&machine_soft_reset_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_enable_irq), (mp_obj_t)&machine_enable_irq_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_disable_irq), (mp_obj_t)&machine_disable_irq_obj }, +STATIC const mp_rom_map_elem_t machine_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_umachine) }, + { MP_ROM_QSTR(MP_QSTR_info), MP_ROM_PTR(&machine_info_obj) }, + { MP_ROM_QSTR(MP_QSTR_reset), MP_ROM_PTR(&machine_reset_obj) }, + { MP_ROM_QSTR(MP_QSTR_soft_reset), MP_ROM_PTR(&machine_soft_reset_obj) }, + { MP_ROM_QSTR(MP_QSTR_enable_irq), MP_ROM_PTR(&machine_enable_irq_obj) }, + { MP_ROM_QSTR(MP_QSTR_disable_irq), MP_ROM_PTR(&machine_disable_irq_obj) }, #if MICROPY_HW_ENABLE_RNG - { MP_OBJ_NEW_QSTR(MP_QSTR_rng), (mp_obj_t)&pyb_rng_get_obj }, + { MP_ROM_QSTR(MP_QSTR_rng), MP_ROM_PTR(&pyb_rng_get_obj) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_sleep), (mp_obj_t)&machine_sleep_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_deepsleep), (mp_obj_t)&machine_deepsleep_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_reset_cause), (mp_obj_t)&machine_reset_cause_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_Pin), (mp_obj_t)&pin_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&machine_hard_uart_type }, + { MP_ROM_QSTR(MP_QSTR_sleep), MP_ROM_PTR(&machine_sleep_obj) }, + { MP_ROM_QSTR(MP_QSTR_deepsleep), MP_ROM_PTR(&machine_deepsleep_obj) }, + { MP_ROM_QSTR(MP_QSTR_reset_cause), MP_ROM_PTR(&machine_reset_cause_obj) }, + { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&pin_type) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&machine_hard_uart_type) }, #if MICROPY_PY_MACHINE_HW_SPI - { MP_OBJ_NEW_QSTR(MP_QSTR_SPI), (mp_obj_t)&machine_hard_spi_type }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&machine_hard_spi_type) }, #endif #if MICROPY_PY_MACHINE_I2C - { MP_OBJ_NEW_QSTR(MP_QSTR_I2C), (mp_obj_t)&machine_i2c_type }, + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&machine_i2c_type) }, #endif #if MICROPY_PY_MACHINE_ADC - { MP_OBJ_NEW_QSTR(MP_QSTR_ADC), (mp_obj_t)&machine_adc_type }, + { MP_ROM_QSTR(MP_QSTR_ADC), MP_ROM_PTR(&machine_adc_type) }, #endif #if MICROPY_PY_MACHINE_RTC - { MP_OBJ_NEW_QSTR(MP_QSTR_RTC), (mp_obj_t)&machine_rtc_type }, + { MP_ROM_QSTR(MP_QSTR_RTC), MP_ROM_PTR(&machine_rtc_type) }, #endif #if MICROPY_PY_MACHINE_TIMER - { MP_OBJ_NEW_QSTR(MP_QSTR_Timer), (mp_obj_t)&machine_timer_type }, + { MP_ROM_QSTR(MP_QSTR_Timer), MP_ROM_PTR(&machine_timer_type) }, #endif #if MICROPY_PY_MACHINE_HW_PWM - { MP_OBJ_NEW_QSTR(MP_QSTR_PWM), (mp_obj_t)&machine_hard_pwm_type }, + { MP_ROM_QSTR(MP_QSTR_PWM), MP_ROM_PTR(mp_obj_t)&machine_hard_pwm_type) }, #endif #if MICROPY_PY_MACHINE_TEMP - { MP_OBJ_NEW_QSTR(MP_QSTR_Temp), (mp_obj_t)&machine_temp_type }, + { MP_ROM_QSTR(MP_QSTR_Temp), MP_ROM_PTR(&machine_temp_type) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_HARD_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_HARD) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_WDT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_WDT) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_SOFT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_SOFT) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_LOCKUP_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_LOCKUP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PWRON_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_POWER_ON) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_LPCOMP_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_LPCOMP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_DEBUG_IF_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_DIF) }, + { MP_ROM_QSTR(MP_QSTR_HARD_RESET), MP_ROM_INT(PYB_RESET_HARD) }, + { MP_ROM_QSTR(MP_QSTR_WDT_RESET), MP_ROM_INT(PYB_RESET_WDT) }, + { MP_ROM_QSTR(MP_QSTR_SOFT_RESET), MP_ROM_INT(PYB_RESET_SOFT) }, + { MP_ROM_QSTR(MP_QSTR_LOCKUP_RESET), MP_ROM_INT(PYB_RESET_LOCKUP) }, + { MP_ROM_QSTR(MP_QSTR_PWRON_RESET), MP_ROM_INT(PYB_RESET_POWER_ON) }, + { MP_ROM_QSTR(MP_QSTR_LPCOMP_RESET), MP_ROM_INT(PYB_RESET_LPCOMP) }, + { MP_ROM_QSTR(MP_QSTR_DEBUG_IF_RESET), MP_ROM_INT(PYB_RESET_DIF) }, #if NRF52 - { MP_OBJ_NEW_QSTR(MP_QSTR_NFC_RESET), MP_OBJ_NEW_SMALL_INT(PYB_RESET_NFC) }, + { MP_ROM_QSTR(MP_QSTR_NFC_RESET), MP_ROM_INT(PYB_RESET_NFC) }, #endif }; diff --git a/nrf5/modules/machine/pin.c b/nrf5/modules/machine/pin.c index 18d86d6e44..5dfaa296a1 100644 --- a/nrf5/modules/machine/pin.c +++ b/nrf5/modules/machine/pin.c @@ -501,55 +501,55 @@ STATIC mp_obj_t pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_ar STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pin_irq_obj, 1, pin_irq); -STATIC const mp_map_elem_t pin_locals_dict_table[] = { +STATIC const mp_rom_map_elem_t pin_locals_dict_table[] = { // instance methods - { MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&pin_init_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_value), (mp_obj_t)&pin_value_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_low), (mp_obj_t)&pin_low_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_high), (mp_obj_t)&pin_high_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_name), (mp_obj_t)&pin_name_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_names), (mp_obj_t)&pin_names_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_af_list), (mp_obj_t)&pin_af_list_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_port), (mp_obj_t)&pin_port_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_pin), (mp_obj_t)&pin_pin_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_gpio), (mp_obj_t)&pin_gpio_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_mode), (mp_obj_t)&pin_mode_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_pull), (mp_obj_t)&pin_pull_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_af), (mp_obj_t)&pin_af_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_irq), (mp_obj_t)&pin_irq_obj }, + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pin_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&pin_value_obj) }, + { MP_ROM_QSTR(MP_QSTR_low), MP_ROM_PTR(&pin_low_obj) }, + { MP_ROM_QSTR(MP_QSTR_high), MP_ROM_PTR(&pin_high_obj) }, + { MP_ROM_QSTR(MP_QSTR_name), MP_ROM_PTR(&pin_name_obj) }, + { MP_ROM_QSTR(MP_QSTR_names), MP_ROM_PTR(&pin_names_obj) }, + { MP_ROM_QSTR(MP_QSTR_af_list), MP_ROM_PTR(&pin_af_list_obj) }, + { MP_ROM_QSTR(MP_QSTR_port), MP_ROM_PTR(&pin_port_obj) }, + { MP_ROM_QSTR(MP_QSTR_pin), MP_ROM_PTR(&pin_pin_obj) }, + { MP_ROM_QSTR(MP_QSTR_gpio), MP_ROM_PTR(&pin_gpio_obj) }, + { MP_ROM_QSTR(MP_QSTR_mode), MP_ROM_PTR(&pin_mode_obj) }, + { MP_ROM_QSTR(MP_QSTR_pull), MP_ROM_PTR(&pin_pull_obj) }, + { MP_ROM_QSTR(MP_QSTR_af), MP_ROM_PTR(&pin_af_obj) }, + { MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&pin_irq_obj) }, // class methods - { MP_OBJ_NEW_QSTR(MP_QSTR_mapper), (mp_obj_t)&pin_mapper_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_dict), (mp_obj_t)&pin_map_dict_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_debug), (mp_obj_t)&pin_debug_obj }, + { MP_ROM_QSTR(MP_QSTR_mapper), MP_ROM_PTR(&pin_mapper_obj) }, + { MP_ROM_QSTR(MP_QSTR_dict), MP_ROM_PTR(&pin_map_dict_obj) }, + { MP_ROM_QSTR(MP_QSTR_debug), MP_ROM_PTR(&pin_debug_obj) }, // class attributes - { MP_OBJ_NEW_QSTR(MP_QSTR_board), (mp_obj_t)&pin_board_pins_obj_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_cpu), (mp_obj_t)&pin_cpu_pins_obj_type }, + { MP_ROM_QSTR(MP_QSTR_board), MP_ROM_PTR(&pin_board_pins_obj_type) }, + { MP_ROM_QSTR(MP_QSTR_cpu), MP_ROM_PTR(&pin_cpu_pins_obj_type) }, // class constants - { MP_OBJ_NEW_QSTR(MP_QSTR_IN), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_MODE_INPUT) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_OUT), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_MODE_OUTPUT) }, + { MP_ROM_QSTR(MP_QSTR_IN), MP_ROM_INT(HAL_GPIO_MODE_INPUT) }, + { MP_ROM_QSTR(MP_QSTR_OUT), MP_ROM_INT(HAL_GPIO_MODE_OUTPUT) }, /* - { MP_OBJ_NEW_QSTR(MP_QSTR_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ALT), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_PP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ALT_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_OD) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ANALOG), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_ANALOG) }, + { MP_ROM_QSTR(MP_QSTR_OPEN_DRAIN), MP_ROM_INT(GPIO_MODE_OUTPUT_OD) }, + { MP_ROM_QSTR(MP_QSTR_ALT), MP_ROM_INT(GPIO_MODE_AF_PP) }, + { MP_ROM_QSTR(MP_QSTR_ALT_OPEN_DRAIN), MP_ROM_INT(GPIO_MODE_AF_OD) }, + { MP_ROM_QSTR(MP_QSTR_ANALOG), MP_ROM_INT(GPIO_MODE_ANALOG) }, */ - { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DISABLED), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_DISABLED) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_UP), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_UP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DOWN), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_DOWN) }, + { MP_ROM_QSTR(MP_QSTR_PULL_DISABLED), MP_ROM_INT(HAL_GPIO_PULL_DISABLED) }, + { MP_ROM_QSTR(MP_QSTR_PULL_UP), MP_ROM_INT(HAL_GPIO_PULL_UP) }, + { MP_ROM_QSTR(MP_QSTR_PULL_DOWN), MP_ROM_INT(HAL_GPIO_PULL_DOWN) }, // IRQ triggers, can be or'd together - { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_RISING), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_FALLING), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW) }, + { MP_ROM_QSTR(MP_QSTR_IRQ_RISING), MP_ROM_INT(HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH) }, + { MP_ROM_QSTR(MP_QSTR_IRQ_FALLING), MP_ROM_INT(HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW) }, /* // legacy class constants - { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_PP), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_OD), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AF_PP), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_PP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AF_OD), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_OD) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_NONE), MP_OBJ_NEW_SMALL_INT(GPIO_NOPULL) }, + { MP_ROM_QSTR(MP_QSTR_OUT_PP), MP_ROM_INT(GPIO_MODE_OUTPUT_PP) }, + { MP_ROM_QSTR(MP_QSTR_OUT_OD), MP_ROM_INT(GPIO_MODE_OUTPUT_OD) }, + { MP_ROM_QSTR(MP_QSTR_AF_PP), MP_ROM_INT(GPIO_MODE_AF_PP) }, + { MP_ROM_QSTR(MP_QSTR_AF_OD), MP_ROM_INT(GPIO_MODE_AF_OD) }, + { MP_ROM_QSTR(MP_QSTR_PULL_NONE), MP_ROM_INT(GPIO_NOPULL) }, */ #include "genhdr/pins_af_const.h" }; @@ -562,7 +562,7 @@ const mp_obj_type_t pin_type = { .print = pin_print, .make_new = pin_make_new, .call = pin_call, - .locals_dict = (mp_obj_t)&pin_locals_dict, + .locals_dict = (mp_obj_dict_t*)&pin_locals_dict, }; /// \moduleref pyb @@ -624,10 +624,10 @@ STATIC mp_obj_t pin_af_reg(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_reg_obj, pin_af_reg); -STATIC const mp_map_elem_t pin_af_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_index), (mp_obj_t)&pin_af_index_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_name), (mp_obj_t)&pin_af_name_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_reg), (mp_obj_t)&pin_af_reg_obj }, +STATIC const mp_rom_map_elem_t pin_af_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_index), MP_ROM_PTR(&pin_af_index_obj) }, + { MP_ROM_QSTR(MP_QSTR_name), MP_ROM_PTR(&pin_af_name_obj) }, + { MP_ROM_QSTR(MP_QSTR_reg), MP_ROM_PTR(&pin_af_reg_obj) }, }; STATIC MP_DEFINE_CONST_DICT(pin_af_locals_dict, pin_af_locals_dict_table); @@ -635,7 +635,7 @@ const mp_obj_type_t pin_af_type = { { &mp_type_type }, .name = MP_QSTR_PinAF, .print = pin_af_obj_print, - .locals_dict = (mp_obj_t)&pin_af_locals_dict, + .locals_dict = (mp_obj_dict_t*)&pin_af_locals_dict, }; /******************************************************************************/ diff --git a/nrf5/modules/machine/pwm.c b/nrf5/modules/machine/pwm.c index 6dfa9aa418..522f5425df 100644 --- a/nrf5/modules/machine/pwm.c +++ b/nrf5/modules/machine/pwm.c @@ -215,24 +215,24 @@ STATIC mp_obj_t machine_pwm_duty(size_t n_args, const mp_obj_t *args) { STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_pwm_duty_obj, 1, 2, machine_pwm_duty); STATIC const mp_rom_map_elem_t machine_pwm_locals_dict_table[] = { - { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_pwm_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_pwm_init_obj) }, { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_pwm_deinit_obj) }, - { MP_ROM_QSTR(MP_QSTR_freq), MP_ROM_PTR(&mp_machine_pwm_freq_obj) }, + { MP_ROM_QSTR(MP_QSTR_freq), MP_ROM_PTR(&mp_machine_pwm_freq_obj) }, { MP_ROM_QSTR(MP_QSTR_period), MP_ROM_PTR(&mp_machine_pwm_period_obj) }, - { MP_ROM_QSTR(MP_QSTR_duty), MP_ROM_PTR(&mp_machine_pwm_duty_obj) }, + { MP_ROM_QSTR(MP_QSTR_duty), MP_ROM_PTR(&mp_machine_pwm_duty_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_16MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_16Mhz) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_8MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_8Mhz) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_4MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_4Mhz) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_2MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_2Mhz) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_1MHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_1Mhz) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_500KHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_500khz) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_250KHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_250khz) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FREQ_125KHZ), MP_OBJ_NEW_SMALL_INT(HAL_PWM_FREQ_125khz) }, + { MP_ROM_QSTR(MP_QSTR_FREQ_16MHZ), MP_ROM_INT(HAL_PWM_FREQ_16Mhz) }, + { MP_ROM_QSTR(MP_QSTR_FREQ_8MHZ), MP_ROM_INT(HAL_PWM_FREQ_8Mhz) }, + { MP_ROM_QSTR(MP_QSTR_FREQ_4MHZ), MP_ROM_INT(HAL_PWM_FREQ_4Mhz) }, + { MP_ROM_QSTR(MP_QSTR_FREQ_2MHZ), MP_ROM_INT(HAL_PWM_FREQ_2Mhz) }, + { MP_ROM_QSTR(MP_QSTR_FREQ_1MHZ), MP_ROM_INT(HAL_PWM_FREQ_1Mhz) }, + { MP_ROM_QSTR(MP_QSTR_FREQ_500KHZ), MP_ROM_INT(HAL_PWM_FREQ_500khz) }, + { MP_ROM_QSTR(MP_QSTR_FREQ_250KHZ), MP_ROM_INT(HAL_PWM_FREQ_250khz) }, + { MP_ROM_QSTR(MP_QSTR_FREQ_125KHZ), MP_ROM_INT(HAL_PWM_FREQ_125khz) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_MODE_LOW_HIGH), MP_OBJ_NEW_SMALL_INT(HAL_PWM_MODE_LOW_HIGH) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_MODE_HIGH_LOW), MP_OBJ_NEW_SMALL_INT(HAL_PWM_MODE_HIGH_LOW) }, + { MP_ROM_QSTR(MP_QSTR_MODE_LOW_HIGH), MP_ROM_INT(HAL_PWM_MODE_LOW_HIGH) }, + { MP_ROM_QSTR(MP_QSTR_MODE_HIGH_LOW), MP_ROM_INT(HAL_PWM_MODE_HIGH_LOW) }, }; STATIC MP_DEFINE_CONST_DICT(machine_pwm_locals_dict, machine_pwm_locals_dict_table); @@ -326,7 +326,7 @@ const mp_obj_type_t machine_hard_pwm_type = { .name = MP_QSTR_PWM, .print = machine_hard_pwm_print, .make_new = machine_pwm_make_new, - .locals_dict = (mp_obj_t)&machine_pwm_locals_dict, + .locals_dict = (mp_obj_dict_t*)&machine_pwm_locals_dict, }; #endif // MICROPY_PY_MACHINE_HW_PWM diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index d7559ae8c2..2fdc32fe87 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -197,13 +197,13 @@ STATIC mp_obj_t machine_rtc_stop(mp_obj_t self_in) { STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_stop_obj, machine_rtc_stop); -STATIC const mp_map_elem_t machine_rtc_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_start), (mp_obj_t)(&machine_rtc_start_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)(&machine_rtc_stop_obj) }, +STATIC const mp_rom_map_elem_t machine_rtc_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&machine_rtc_start_obj) }, + { MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&machine_rtc_stop_obj) }, // constants - { MP_OBJ_NEW_QSTR(MP_QSTR_ONESHOT), MP_OBJ_NEW_SMALL_INT(0) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PERIODIC), MP_OBJ_NEW_SMALL_INT(1) }, + { MP_ROM_QSTR(MP_QSTR_ONESHOT), MP_ROM_INT(0) }, + { MP_ROM_QSTR(MP_QSTR_PERIODIC), MP_ROM_INT(1) }, }; STATIC MP_DEFINE_CONST_DICT(machine_rtc_locals_dict, machine_rtc_locals_dict_table); @@ -213,7 +213,7 @@ const mp_obj_type_t machine_rtc_type = { .name = MP_QSTR_RTC, .print = rtc_print, .make_new = machine_rtc_make_new, - .locals_dict = (mp_obj_t)&machine_rtc_locals_dict + .locals_dict = (mp_obj_dict_t*)&machine_rtc_locals_dict }; #endif // MICROPY_PY_MACHINE_RTC diff --git a/nrf5/modules/machine/spi.c b/nrf5/modules/machine/spi.c index c5956c806f..989942bf5e 100644 --- a/nrf5/modules/machine/spi.c +++ b/nrf5/modules/machine/spi.c @@ -379,7 +379,7 @@ const mp_obj_type_t machine_hard_spi_type = { .print = machine_hard_spi_print, .make_new = machine_spi_make_new, .protocol = &machine_hard_spi_p, - .locals_dict = (mp_obj_t)&machine_spi_locals_dict, + .locals_dict = (mp_obj_dict_t*)&machine_spi_locals_dict, }; #endif // MICROPY_PY_MACHINE_HW_SPI diff --git a/nrf5/modules/machine/temp.c b/nrf5/modules/machine/temp.c index a5b660c00f..1848fd2985 100644 --- a/nrf5/modules/machine/temp.c +++ b/nrf5/modules/machine/temp.c @@ -77,10 +77,10 @@ STATIC mp_obj_t machine_temp_read(mp_uint_t n_args, const mp_obj_t *args) { STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_temp_read_obj, 0, 1, machine_temp_read); -STATIC const mp_map_elem_t machine_temp_locals_dict_table[] = { +STATIC const mp_rom_map_elem_t machine_temp_locals_dict_table[] = { // instance methods // class methods - { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&mp_machine_temp_read_obj }, + { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_machine_temp_read_obj) }, }; STATIC MP_DEFINE_CONST_DICT(machine_temp_locals_dict, machine_temp_locals_dict_table); @@ -89,7 +89,7 @@ const mp_obj_type_t machine_temp_type = { { &mp_type_type }, .name = MP_QSTR_Temp, .make_new = machine_temp_make_new, - .locals_dict = (mp_obj_t)&machine_temp_locals_dict, + .locals_dict = (mp_obj_dict_t*)&machine_temp_locals_dict, .print = machine_temp_print, }; diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index 0eb35dc80e..d22f808751 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -128,13 +128,13 @@ STATIC mp_obj_t machine_timer_stop(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_stop_obj, machine_timer_stop); -STATIC const mp_map_elem_t machine_timer_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_start), (mp_obj_t)(&machine_timer_start_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)(&machine_timer_stop_obj) }, +STATIC const mp_rom_map_elem_t machine_timer_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&machine_timer_start_obj) }, + { MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&machine_timer_stop_obj) }, // constants - { MP_OBJ_NEW_QSTR(MP_QSTR_ONESHOT), MP_OBJ_NEW_SMALL_INT(0) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PERIODIC), MP_OBJ_NEW_SMALL_INT(1) }, + { MP_ROM_QSTR(MP_QSTR_ONESHOT), MP_ROM_INT(0) }, + { MP_ROM_QSTR(MP_QSTR_PERIODIC), MP_ROM_INT(1) }, }; STATIC MP_DEFINE_CONST_DICT(machine_timer_locals_dict, machine_timer_locals_dict_table); @@ -144,7 +144,7 @@ const mp_obj_type_t machine_timer_type = { .name = MP_QSTR_Timer, .print = timer_print, .make_new = machine_timer_make_new, - .locals_dict = (mp_obj_t)&machine_timer_locals_dict + .locals_dict = (mp_obj_dict_t*)&machine_timer_locals_dict }; #endif // MICROPY_PY_MACHINE_TIMER diff --git a/nrf5/modules/machine/uart.c b/nrf5/modules/machine/uart.c index e8533e455b..94166508d6 100644 --- a/nrf5/modules/machine/uart.c +++ b/nrf5/modules/machine/uart.c @@ -331,23 +331,23 @@ STATIC mp_obj_t machine_hard_uart_sendbreak(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_hard_uart_sendbreak_obj, machine_hard_uart_sendbreak); -STATIC const mp_map_elem_t machine_hard_uart_locals_dict_table[] = { +STATIC const mp_rom_map_elem_t machine_hard_uart_locals_dict_table[] = { // instance methods /// \method read([nbytes]) - { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&mp_stream_read_obj }, + { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_stream_read_obj) }, /// \method readline() - { MP_OBJ_NEW_QSTR(MP_QSTR_readline), (mp_obj_t)&mp_stream_unbuffered_readline_obj}, + { MP_ROM_QSTR(MP_QSTR_readline), MP_ROM_PTR(&mp_stream_unbuffered_readline_obj) }, /// \method readinto(buf[, nbytes]) - { MP_OBJ_NEW_QSTR(MP_QSTR_readinto), (mp_obj_t)&mp_stream_readinto_obj }, + { MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&mp_stream_readinto_obj) }, /// \method writechar(buf) - { MP_OBJ_NEW_QSTR(MP_QSTR_writechar), (mp_obj_t)&machine_hard_uart_writechar_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readchar), (mp_obj_t)&machine_hard_uart_readchar_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_sendbreak), (mp_obj_t)&machine_hard_uart_sendbreak_obj }, + { MP_ROM_QSTR(MP_QSTR_writechar), MP_ROM_PTR(&machine_hard_uart_writechar_obj) }, + { MP_ROM_QSTR(MP_QSTR_readchar), MP_ROM_PTR(&machine_hard_uart_readchar_obj) }, + { MP_ROM_QSTR(MP_QSTR_sendbreak), MP_ROM_PTR(&machine_hard_uart_sendbreak_obj) }, // class constants /* - { MP_OBJ_NEW_QSTR(MP_QSTR_RTS), MP_OBJ_NEW_SMALL_INT(UART_HWCONTROL_RTS) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_CTS), MP_OBJ_NEW_SMALL_INT(UART_HWCONTROL_CTS) }, + { MP_ROM_QSTR(MP_QSTR_RTS), MP_ROM_INT(UART_HWCONTROL_RTS) }, + { MP_ROM_QSTR(MP_QSTR_CTS), MP_ROM_INT(UART_HWCONTROL_CTS) }, */ }; @@ -430,6 +430,6 @@ const mp_obj_type_t machine_hard_uart_type = { .getiter = mp_identity_getiter, .iternext = mp_stream_unbuffered_iter, .protocol = &uart_stream_p, - .locals_dict = (mp_obj_t)&machine_hard_uart_locals_dict, + .locals_dict = (mp_obj_dict_t*)&machine_hard_uart_locals_dict, }; diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index 31e2bd2100..88311f2cd2 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -456,37 +456,37 @@ static mp_obj_t music_init(void) { } MP_DEFINE_CONST_FUN_OBJ_0(music___init___obj, music_init); -STATIC const mp_map_elem_t microbit_music_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___init__), (mp_obj_t)&music___init___obj }, +STATIC const mp_rom_map_elem_t microbit_music_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR___init__), MP_ROM_PTR(&music___init___obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_reset), (mp_obj_t)µbit_music_reset_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_set_tempo), (mp_obj_t)µbit_music_set_tempo_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_get_tempo), (mp_obj_t)µbit_music_get_tempo_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_play), (mp_obj_t)µbit_music_play_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_pitch), (mp_obj_t)µbit_music_pitch_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)µbit_music_stop_obj }, + { MP_ROM_QSTR(MP_QSTR_reset), MP_ROM_PTR(µbit_music_reset_obj) }, + { MP_ROM_QSTR(MP_QSTR_set_tempo), MP_ROM_PTR(µbit_music_set_tempo_obj) }, + { MP_ROM_QSTR(MP_QSTR_get_tempo), MP_ROM_PTR(µbit_music_get_tempo_obj) }, + { MP_ROM_QSTR(MP_QSTR_play), MP_ROM_PTR(µbit_music_play_obj) }, + { MP_ROM_QSTR(MP_QSTR_pitch), MP_ROM_PTR(µbit_music_pitch_obj) }, + { MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(µbit_music_stop_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_DADADADUM), (mp_obj_t)µbit_music_tune_dadadadum_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ENTERTAINER), (mp_obj_t)µbit_music_tune_entertainer_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PRELUDE), (mp_obj_t)µbit_music_tune_prelude_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ODE), (mp_obj_t)µbit_music_tune_ode_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_NYAN), (mp_obj_t)µbit_music_tune_nyan_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_RINGTONE), (mp_obj_t)µbit_music_tune_ringtone_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FUNK), (mp_obj_t)µbit_music_tune_funk_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_BLUES), (mp_obj_t)µbit_music_tune_blues_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_BIRTHDAY), (mp_obj_t)µbit_music_tune_birthday_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_WEDDING), (mp_obj_t)µbit_music_tune_wedding_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_FUNERAL), (mp_obj_t)µbit_music_tune_funeral_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PUNCHLINE), (mp_obj_t)µbit_music_tune_punchline_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PYTHON), (mp_obj_t)µbit_music_tune_python_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_BADDY), (mp_obj_t)µbit_music_tune_baddy_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_CHASE), (mp_obj_t)µbit_music_tune_chase_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_BA_DING), (mp_obj_t)µbit_music_tune_ba_ding_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_WAWAWAWAA), (mp_obj_t)µbit_music_tune_wawawawaa_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_JUMP_UP), (mp_obj_t)µbit_music_tune_jump_up_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_JUMP_DOWN), (mp_obj_t)µbit_music_tune_jump_down_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_POWER_UP), (mp_obj_t)µbit_music_tune_power_up_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_POWER_DOWN), (mp_obj_t)µbit_music_tune_power_down_obj }, + { MP_ROM_QSTR(MP_QSTR_DADADADUM), MP_ROM_PTR(µbit_music_tune_dadadadum_obj) }, + { MP_ROM_QSTR(MP_QSTR_ENTERTAINER), MP_ROM_PTR(µbit_music_tune_entertainer_obj) }, + { MP_ROM_QSTR(MP_QSTR_PRELUDE), MP_ROM_PTR(µbit_music_tune_prelude_obj) }, + { MP_ROM_QSTR(MP_QSTR_ODE), MP_ROM_PTR(µbit_music_tune_ode_obj) }, + { MP_ROM_QSTR(MP_QSTR_NYAN), MP_ROM_PTR(µbit_music_tune_nyan_obj) }, + { MP_ROM_QSTR(MP_QSTR_RINGTONE), MP_ROM_PTR(µbit_music_tune_ringtone_obj) }, + { MP_ROM_QSTR(MP_QSTR_FUNK), MP_ROM_PTR(µbit_music_tune_funk_obj) }, + { MP_ROM_QSTR(MP_QSTR_BLUES), MP_ROM_PTR(µbit_music_tune_blues_obj) }, + { MP_ROM_QSTR(MP_QSTR_BIRTHDAY), MP_ROM_PTR(µbit_music_tune_birthday_obj) }, + { MP_ROM_QSTR(MP_QSTR_WEDDING), MP_ROM_PTR(µbit_music_tune_wedding_obj) }, + { MP_ROM_QSTR(MP_QSTR_FUNERAL), MP_ROM_PTR(µbit_music_tune_funeral_obj) }, + { MP_ROM_QSTR(MP_QSTR_PUNCHLINE), MP_ROM_PTR(µbit_music_tune_punchline_obj) }, + { MP_ROM_QSTR(MP_QSTR_PYTHON), MP_ROM_PTR(µbit_music_tune_python_obj) }, + { MP_ROM_QSTR(MP_QSTR_BADDY), MP_ROM_PTR(µbit_music_tune_baddy_obj) }, + { MP_ROM_QSTR(MP_QSTR_CHASE), MP_ROM_PTR(µbit_music_tune_chase_obj) }, + { MP_ROM_QSTR(MP_QSTR_BA_DING), MP_ROM_PTR(µbit_music_tune_ba_ding_obj) }, + { MP_ROM_QSTR(MP_QSTR_WAWAWAWAA), MP_ROM_PTR(µbit_music_tune_wawawawaa_obj) }, + { MP_ROM_QSTR(MP_QSTR_JUMP_UP), MP_ROM_PTR(µbit_music_tune_jump_up_obj) }, + { MP_ROM_QSTR(MP_QSTR_JUMP_DOWN), MP_ROM_PTR(µbit_music_tune_jump_down_obj) }, + { MP_ROM_QSTR(MP_QSTR_POWER_UP), MP_ROM_PTR(µbit_music_tune_power_up_obj) }, + { MP_ROM_QSTR(MP_QSTR_POWER_DOWN), MP_ROM_PTR(µbit_music_tune_power_down_obj) }, }; STATIC MP_DEFINE_CONST_DICT(microbit_music_locals_dict, microbit_music_locals_dict_table); diff --git a/nrf5/modules/music/musictunes.c b/nrf5/modules/music/musictunes.c index 895c40a1ca..2d9f9d38ba 100644 --- a/nrf5/modules/music/musictunes.c +++ b/nrf5/modules/music/musictunes.c @@ -34,7 +34,7 @@ #if MICROPY_PY_MUSIC -#define N(q) MP_OBJ_NEW_QSTR(MP_QSTR_ ## q) +#define N(q) MP_ROM_QSTR(MP_QSTR_ ## q) #define T(name, ...) const mp_obj_tuple_t microbit_music_tune_ ## name ## _obj = {{&mp_type_tuple}, .len = (sizeof((mp_obj_t[]){__VA_ARGS__})/sizeof(mp_obj_t)), .items = {__VA_ARGS__}}; diff --git a/nrf5/modules/pyb/modpyb.c b/nrf5/modules/pyb/modpyb.c index 8d09944a25..ec49224bc7 100644 --- a/nrf5/modules/pyb/modpyb.c +++ b/nrf5/modules/pyb/modpyb.c @@ -32,12 +32,12 @@ #include "nrf.h" // TODO: figure out where to put this import #include "pin.h" -STATIC const mp_map_elem_t pyb_module_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_pyb) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_LED), (mp_obj_t)&pyb_led_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_repl_info), (mp_obj_t)&pyb_set_repl_info_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_Pin), (mp_obj_t)&pin_type }, -/* { MP_OBJ_NEW_QSTR(MP_QSTR_main), (mp_obj_t)&pyb_main_obj }*/ +STATIC const mp_rom_map_elem_t pyb_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_pyb) }, + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pyb_led_type) }, + { MP_ROM_QSTR(MP_QSTR_repl_info), MP_ROM_PTR(&pyb_set_repl_info_obj) }, + { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&pin_type) }, +/* { MP_ROM_QSTR(MP_QSTR_main), MP_ROM_PTR(&pyb_main_obj) }*/ }; diff --git a/nrf5/modules/ubluepy/modubluepy.c b/nrf5/modules/ubluepy/modubluepy.c index 6835e9ef7c..dae4e713bc 100644 --- a/nrf5/modules/ubluepy/modubluepy.c +++ b/nrf5/modules/ubluepy/modubluepy.c @@ -37,25 +37,25 @@ extern const mp_obj_type_t ubluepy_constants_type; extern const mp_obj_type_t ubluepy_scanner_type; extern const mp_obj_type_t ubluepy_scan_entry_type; -STATIC const mp_map_elem_t mp_module_ubluepy_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy) }, +STATIC const mp_rom_map_elem_t mp_module_ubluepy_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_ubluepy) }, #if MICROPY_PY_UBLUEPY_PERIPHERAL - { MP_OBJ_NEW_QSTR(MP_QSTR_Peripheral), (mp_obj_t)&ubluepy_peripheral_type }, + { MP_ROM_QSTR(MP_QSTR_Peripheral), MP_ROM_PTR(&ubluepy_peripheral_type) }, #endif #if 0 // MICROPY_PY_UBLUEPY_CENTRAL - { MP_OBJ_NEW_QSTR(MP_QSTR_Central), (mp_obj_t)&ubluepy_central_type }, + { MP_ROM_QSTR(MP_QSTR_Central), MP_ROM_PTR(&ubluepy_central_type) }, #endif #if MICROPY_PY_UBLUEPY_CENTRAL - { MP_OBJ_NEW_QSTR(MP_QSTR_Scanner), (mp_obj_t)&ubluepy_scanner_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ScanEntry), (mp_obj_t)&ubluepy_scan_entry_type }, + { MP_ROM_QSTR(MP_QSTR_Scanner), MP_ROM_PTR(&ubluepy_scanner_type) }, + { MP_ROM_QSTR(MP_QSTR_ScanEntry), MP_ROM_PTR(&ubluepy_scan_entry_type) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_DefaultDelegate), (mp_obj_t)&ubluepy_delegate_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_UUID), (mp_obj_t)&ubluepy_uuid_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_Service), (mp_obj_t)&ubluepy_service_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_Characteristic), (mp_obj_t)&ubluepy_characteristic_type }, - { MP_OBJ_NEW_QSTR(MP_QSTR_constants), (mp_obj_t)&ubluepy_constants_type }, + { MP_ROM_QSTR(MP_QSTR_DefaultDelegate), MP_ROM_PTR(&ubluepy_delegate_type) }, + { MP_ROM_QSTR(MP_QSTR_UUID), MP_ROM_PTR(&ubluepy_uuid_type) }, + { MP_ROM_QSTR(MP_QSTR_Service), MP_ROM_PTR(&ubluepy_service_type) }, + { MP_ROM_QSTR(MP_QSTR_Characteristic), MP_ROM_PTR(&ubluepy_characteristic_type) }, + { MP_ROM_QSTR(MP_QSTR_constants), MP_ROM_PTR(&ubluepy_constants_type) }, #if MICROPY_PY_UBLUEPY_DESCRIPTOR - { MP_OBJ_NEW_QSTR(MP_QSTR_Descriptor), (mp_obj_t)&ubluepy_descriptor_type }, + { MP_ROM_QSTR(MP_QSTR_Descriptor), MP_ROM_PTR(&ubluepy_descriptor_type) }, #endif }; diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index 1a68e070b0..6c005fab34 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -156,34 +156,34 @@ STATIC mp_obj_t char_uuid(mp_obj_t self_in) { STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_get_uuid_obj, char_uuid); -STATIC const mp_map_elem_t ubluepy_characteristic_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)(&ubluepy_characteristic_read_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_write), (mp_obj_t)(&ubluepy_characteristic_write_obj) }, +STATIC const mp_rom_map_elem_t ubluepy_characteristic_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&ubluepy_characteristic_read_obj) }, + { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&ubluepy_characteristic_write_obj) }, #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_supportsRead), (mp_obj_t)(&ubluepy_characteristic_supports_read_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_propertiesToString), (mp_obj_t)(&ubluepy_characteristic_properties_to_str_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getHandle), (mp_obj_t)(&ubluepy_characteristic_get_handle_obj) }, + { MP_ROM_QSTR(MP_QSTR_supportsRead), MP_ROM_PTR(&ubluepy_characteristic_supports_read_obj) }, + { MP_ROM_QSTR(MP_QSTR_propertiesToString), MP_ROM_PTR(&ubluepy_characteristic_properties_to_str_obj) }, + { MP_ROM_QSTR(MP_QSTR_getHandle), MP_ROM_PTR(&ubluepy_characteristic_get_handle_obj) }, // Properties - { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_characteristic_get_peripheral_obj) }, + { MP_ROM_QSTR(MP_QSTR_peripheral), MP_ROM_PTR(&ubluepy_characteristic_get_peripheral_obj) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_characteristic_get_uuid_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_properties), (mp_obj_t)(&ubluepy_characteristic_get_properties_obj) }, + { MP_ROM_QSTR(MP_QSTR_uuid), MP_ROM_PTR(&ubluepy_characteristic_get_uuid_obj) }, + { MP_ROM_QSTR(MP_QSTR_properties), MP_ROM_PTR(&ubluepy_characteristic_get_properties_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_BROADCAST), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_BROADCAST) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_READ), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_READ) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_WRITE_WO_RESP), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_WRITE_WO_RESP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_WRITE), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_WRITE) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_NOTIFY), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_NOTIFY) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_INDICATE), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_INDICATE) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_AUTH_SIGNED_WR), MP_OBJ_NEW_SMALL_INT(UBLUEPY_PROP_AUTH_SIGNED_WR) }, + { MP_ROM_QSTR(MP_QSTR_PROP_BROADCAST), MP_ROM_INT(UBLUEPY_PROP_BROADCAST) }, + { MP_ROM_QSTR(MP_QSTR_PROP_READ), MP_ROM_INT(UBLUEPY_PROP_READ) }, + { MP_ROM_QSTR(MP_QSTR_PROP_WRITE_WO_RESP), MP_ROM_INT(UBLUEPY_PROP_WRITE_WO_RESP) }, + { MP_ROM_QSTR(MP_QSTR_PROP_WRITE), MP_ROM_INT(UBLUEPY_PROP_WRITE) }, + { MP_ROM_QSTR(MP_QSTR_PROP_NOTIFY), MP_ROM_INT(UBLUEPY_PROP_NOTIFY) }, + { MP_ROM_QSTR(MP_QSTR_PROP_INDICATE), MP_ROM_INT(UBLUEPY_PROP_INDICATE) }, + { MP_ROM_QSTR(MP_QSTR_PROP_AUTH_SIGNED_WR), MP_ROM_INT(UBLUEPY_PROP_AUTH_SIGNED_WR) }, #if MICROPY_PY_UBLUEPY_PERIPHERAL - { MP_OBJ_NEW_QSTR(MP_QSTR_ATTR_CCCD), MP_OBJ_NEW_SMALL_INT(UBLUEPY_ATTR_CCCD) }, + { MP_ROM_QSTR(MP_QSTR_ATTR_CCCD), MP_ROM_INT(UBLUEPY_ATTR_CCCD) }, #endif #if MICROPY_PY_UBLUEPY_CENTRAL - { MP_OBJ_NEW_QSTR(MP_QSTR_PROP_AUTH_SIGNED_WR), MP_OBJ_NEW_SMALL_INT(UBLUEPY_ATTR_SCCD) }, + { MP_ROM_QSTR(MP_QSTR_PROP_AUTH_SIGNED_WR), MP_ROM_INT(UBLUEPY_ATTR_SCCD) }, #endif }; @@ -194,7 +194,7 @@ const mp_obj_type_t ubluepy_characteristic_type = { .name = MP_QSTR_Characteristic, .print = ubluepy_characteristic_print, .make_new = ubluepy_characteristic_make_new, - .locals_dict = (mp_obj_t)&ubluepy_characteristic_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_characteristic_locals_dict }; #endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL diff --git a/nrf5/modules/ubluepy/ubluepy_constants.c b/nrf5/modules/ubluepy/ubluepy_constants.c index 6b808905b3..7c7a8168dd 100644 --- a/nrf5/modules/ubluepy/ubluepy_constants.c +++ b/nrf5/modules/ubluepy/ubluepy_constants.c @@ -31,40 +31,40 @@ #include "modubluepy.h" -STATIC const mp_map_elem_t ubluepy_constants_ad_types_locals_dict_table[] = { +STATIC const mp_rom_map_elem_t ubluepy_constants_ad_types_locals_dict_table[] = { // GAP AD Types - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_FLAGS), MP_OBJ_NEW_SMALL_INT(0x01) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE), MP_OBJ_NEW_SMALL_INT(0x02) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE), MP_OBJ_NEW_SMALL_INT(0x03) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE), MP_OBJ_NEW_SMALL_INT(0x04) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE), MP_OBJ_NEW_SMALL_INT(0x05) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE), MP_OBJ_NEW_SMALL_INT(0x06) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE), MP_OBJ_NEW_SMALL_INT(0x07) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SHORT_LOCAL_NAME), MP_OBJ_NEW_SMALL_INT(0x08) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_COMPLETE_LOCAL_NAME), MP_OBJ_NEW_SMALL_INT(0x09) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_TX_POWER_LEVEL), MP_OBJ_NEW_SMALL_INT(0x0A) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_CLASS_OF_DEVICE), MP_OBJ_NEW_SMALL_INT(0x0D) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_HASH_C), MP_OBJ_NEW_SMALL_INT(0x0E) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R), MP_OBJ_NEW_SMALL_INT(0x0F) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SECURITY_MANAGER_TK_VALUE), MP_OBJ_NEW_SMALL_INT(0x10) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS), MP_OBJ_NEW_SMALL_INT(0x11) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE), MP_OBJ_NEW_SMALL_INT(0x12) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT), MP_OBJ_NEW_SMALL_INT(0x14) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT), MP_OBJ_NEW_SMALL_INT(0x15) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA), MP_OBJ_NEW_SMALL_INT(0x16) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_PUBLIC_TARGET_ADDRESS), MP_OBJ_NEW_SMALL_INT(0x17) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_RANDOM_TARGET_ADDRESS), MP_OBJ_NEW_SMALL_INT(0x18) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_APPEARANCE), MP_OBJ_NEW_SMALL_INT(0x19) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_ADVERTISING_INTERVAL), MP_OBJ_NEW_SMALL_INT(0x1A) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS), MP_OBJ_NEW_SMALL_INT(0x1B) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_LE_ROLE), MP_OBJ_NEW_SMALL_INT(0x1C) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_HASH_C256), MP_OBJ_NEW_SMALL_INT(0x1D) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256), MP_OBJ_NEW_SMALL_INT(0x1E) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA_32BIT_UUID), MP_OBJ_NEW_SMALL_INT(0x20) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA_128BIT_UUID), MP_OBJ_NEW_SMALL_INT(0x21) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_URI), MP_OBJ_NEW_SMALL_INT(0x24) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_3D_INFORMATION_DATA), MP_OBJ_NEW_SMALL_INT(0x3D) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_AD_TYPE_MANUFACTURER_SPECIFIC_DATA), MP_OBJ_NEW_SMALL_INT(0xFF) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_FLAGS), MP_ROM_INT(0x01) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE), MP_ROM_INT(0x02) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE), MP_ROM_INT(0x03) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE), MP_ROM_INT(0x04) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE), MP_ROM_INT(0x05) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE), MP_ROM_INT(0x06) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE), MP_ROM_INT(0x07) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SHORT_LOCAL_NAME), MP_ROM_INT(0x08) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_COMPLETE_LOCAL_NAME), MP_ROM_INT(0x09) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_TX_POWER_LEVEL), MP_ROM_INT(0x0A) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_CLASS_OF_DEVICE), MP_ROM_INT(0x0D) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_HASH_C), MP_ROM_INT(0x0E) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R), MP_ROM_INT(0x0F) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SECURITY_MANAGER_TK_VALUE), MP_ROM_INT(0x10) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS), MP_ROM_INT(0x11) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE), MP_ROM_INT(0x12) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT), MP_ROM_INT(0x14) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT), MP_ROM_INT(0x15) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA), MP_ROM_INT(0x16) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_PUBLIC_TARGET_ADDRESS), MP_ROM_INT(0x17) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_RANDOM_TARGET_ADDRESS), MP_ROM_INT(0x18) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_APPEARANCE), MP_ROM_INT(0x19) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_ADVERTISING_INTERVAL), MP_ROM_INT(0x1A) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS), MP_ROM_INT(0x1B) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_LE_ROLE), MP_ROM_INT(0x1C) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_HASH_C256), MP_ROM_INT(0x1D) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256), MP_ROM_INT(0x1E) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA_32BIT_UUID), MP_ROM_INT(0x20) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA_128BIT_UUID), MP_ROM_INT(0x21) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_URI), MP_ROM_INT(0x24) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_3D_INFORMATION_DATA), MP_ROM_INT(0x3D) }, + { MP_ROM_QSTR(MP_QSTR_AD_TYPE_MANUFACTURER_SPECIFIC_DATA), MP_ROM_INT(0xFF) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_ad_types_locals_dict, ubluepy_constants_ad_types_locals_dict_table); @@ -72,16 +72,16 @@ STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_ad_types_locals_dict, ubluepy_cons const mp_obj_type_t ubluepy_constants_ad_types_type = { { &mp_type_type }, .name = MP_QSTR_ad_types, - .locals_dict = (mp_obj_t)&ubluepy_constants_ad_types_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_constants_ad_types_locals_dict }; -STATIC const mp_map_elem_t ubluepy_constants_locals_dict_table[] = { +STATIC const mp_rom_map_elem_t ubluepy_constants_locals_dict_table[] = { // GAP events - { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_OBJ_NEW_SMALL_INT(16) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_OBJ_NEW_SMALL_INT(17) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_UUID_CCCD), MP_OBJ_NEW_SMALL_INT(0x2902) }, + { MP_ROM_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_ROM_INT(16) }, + { MP_ROM_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_ROM_INT(17) }, + { MP_ROM_QSTR(MP_QSTR_UUID_CCCD), MP_ROM_INT(0x2902) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ad_types), (mp_obj_t)(&ubluepy_constants_ad_types_type) }, + { MP_ROM_QSTR(MP_QSTR_ad_types), MP_ROM_PTR(&ubluepy_constants_ad_types_type) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_locals_dict, ubluepy_constants_locals_dict_table); @@ -89,7 +89,7 @@ STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_locals_dict, ubluepy_constants_loc const mp_obj_type_t ubluepy_constants_type = { { &mp_type_type }, .name = MP_QSTR_constants, - .locals_dict = (mp_obj_t)&ubluepy_constants_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_constants_locals_dict }; #endif // MICROPY_PY_UBLUEPY diff --git a/nrf5/modules/ubluepy/ubluepy_delegate.c b/nrf5/modules/ubluepy/ubluepy_delegate.c index 7467398e68..9df135a285 100644 --- a/nrf5/modules/ubluepy/ubluepy_delegate.c +++ b/nrf5/modules/ubluepy/ubluepy_delegate.c @@ -68,11 +68,11 @@ STATIC mp_obj_t delegate_handle_notif(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_delegate_handle_notif_obj, delegate_handle_notif); -STATIC const mp_map_elem_t ubluepy_delegate_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_handleConnection), (mp_obj_t)(&ubluepy_delegate_handle_conn_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_handleNotification), (mp_obj_t)(&ubluepy_delegate_handle_notif_obj) }, +STATIC const mp_rom_map_elem_t ubluepy_delegate_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_handleConnection), MP_ROM_PTR(&ubluepy_delegate_handle_conn_obj) }, + { MP_ROM_QSTR(MP_QSTR_handleNotification), MP_ROM_PTR(&ubluepy_delegate_handle_notif_obj) }, #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_handleDiscovery), (mp_obj_t)(&ubluepy_delegate_handle_disc_obj) }, + { MP_ROM_QSTR(MP_QSTR_handleDiscovery), MP_ROM_PTR(&ubluepy_delegate_handle_disc_obj) }, #endif }; @@ -83,7 +83,7 @@ const mp_obj_type_t ubluepy_delegate_type = { .name = MP_QSTR_DefaultDelegate, .print = ubluepy_delegate_print, .make_new = ubluepy_delegate_make_new, - .locals_dict = (mp_obj_t)&ubluepy_delegate_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_delegate_locals_dict }; #endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL diff --git a/nrf5/modules/ubluepy/ubluepy_descriptor.c b/nrf5/modules/ubluepy/ubluepy_descriptor.c index 959764a327..d67db066b4 100644 --- a/nrf5/modules/ubluepy/ubluepy_descriptor.c +++ b/nrf5/modules/ubluepy/ubluepy_descriptor.c @@ -63,9 +63,9 @@ STATIC mp_obj_t ubluepy_descriptor_make_new(const mp_obj_type_t *type, size_t n_ return MP_OBJ_FROM_PTR(s); } -STATIC const mp_map_elem_t ubluepy_descriptor_locals_dict_table[] = { +STATIC const mp_rom_map_elem_t ubluepy_descriptor_locals_dict_table[] = { #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_binVal), (mp_obj_t)(&ubluepy_descriptor_bin_val_obj) }, + { MP_ROM_QSTR(MP_QSTR_binVal), MP_ROM_PTR(&ubluepy_descriptor_bin_val_obj) }, #endif }; @@ -76,7 +76,7 @@ const mp_obj_type_t ubluepy_descriptor_type = { .name = MP_QSTR_Descriptor, .print = ubluepy_descriptor_print, .make_new = ubluepy_descriptor_make_new, - .locals_dict = (mp_obj_t)&ubluepy_descriptor_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_descriptor_locals_dict }; #endif // MICROPY_PY_UBLUEPY diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 3d434ad882..d8f450c3a5 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -405,37 +405,37 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_connect_obj, peripheral_conn #endif -STATIC const mp_map_elem_t ubluepy_peripheral_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_withDelegate), (mp_obj_t)(&ubluepy_peripheral_with_delegate_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setNotificationHandler), (mp_obj_t)(&ubluepy_peripheral_set_notif_handler_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_setConnectionHandler), (mp_obj_t)(&ubluepy_peripheral_set_conn_handler_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getServices), (mp_obj_t)(&ubluepy_peripheral_get_services_obj) }, +STATIC const mp_rom_map_elem_t ubluepy_peripheral_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_withDelegate), MP_ROM_PTR(&ubluepy_peripheral_with_delegate_obj) }, + { MP_ROM_QSTR(MP_QSTR_setNotificationHandler), MP_ROM_PTR(&ubluepy_peripheral_set_notif_handler_obj) }, + { MP_ROM_QSTR(MP_QSTR_setConnectionHandler), MP_ROM_PTR(&ubluepy_peripheral_set_conn_handler_obj) }, + { MP_ROM_QSTR(MP_QSTR_getServices), MP_ROM_PTR(&ubluepy_peripheral_get_services_obj) }, #if MICROPY_PY_UBLUEPY_CENTRAL - { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)(&ubluepy_peripheral_connect_obj) }, + { MP_ROM_QSTR(MP_QSTR_connect), MP_ROM_PTR(&ubluepy_peripheral_connect_obj) }, #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getServiceByUUID), (mp_obj_t)(&ubluepy_peripheral_get_service_by_uuid_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_peripheral_get_chars_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getDescriptors), (mp_obj_t)(&ubluepy_peripheral_get_descs_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_waitForNotifications), (mp_obj_t)(&ubluepy_peripheral_wait_for_notif_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, + { MP_ROM_QSTR(MP_QSTR_disconnect), MP_ROM_PTR(&ubluepy_peripheral_disconnect_obj) }, + { MP_ROM_QSTR(MP_QSTR_getServiceByUUID), MP_ROM_PTR(&ubluepy_peripheral_get_service_by_uuid_obj) }, + { MP_ROM_QSTR(MP_QSTR_getCharacteristics), MP_ROM_PTR(&ubluepy_peripheral_get_chars_obj) }, + { MP_ROM_QSTR(MP_QSTR_getDescriptors), MP_ROM_PTR(&ubluepy_peripheral_get_descs_obj) }, + { MP_ROM_QSTR(MP_QSTR_waitForNotifications), MP_ROM_PTR(&ubluepy_peripheral_wait_for_notif_obj) }, + { MP_ROM_QSTR(MP_QSTR_writeCharacteristic), MP_ROM_PTR(&ubluepy_peripheral_write_char_obj) }, + { MP_ROM_QSTR(MP_QSTR_readCharacteristic), MP_ROM_PTR(&ubluepy_peripheral_read_char_obj) }, #endif // 0 #endif // MICROPY_PY_UBLUEPY_CENTRAL #if MICROPY_PY_UBLUEPY_PERIPHERAL - { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_advertise_stop), (mp_obj_t)(&ubluepy_peripheral_advertise_stop_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)(&ubluepy_peripheral_disconnect_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_addService), (mp_obj_t)(&ubluepy_peripheral_add_service_obj) }, + { MP_ROM_QSTR(MP_QSTR_advertise), MP_ROM_PTR(&ubluepy_peripheral_advertise_obj) }, + { MP_ROM_QSTR(MP_QSTR_advertise_stop), MP_ROM_PTR(&ubluepy_peripheral_advertise_stop_obj) }, + { MP_ROM_QSTR(MP_QSTR_disconnect), MP_ROM_PTR(&ubluepy_peripheral_disconnect_obj) }, + { MP_ROM_QSTR(MP_QSTR_addService), MP_ROM_PTR(&ubluepy_peripheral_add_service_obj) }, #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_peripheral_add_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_addDescriptor), (mp_obj_t)(&ubluepy_peripheral_add_desc_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_writeCharacteristic), (mp_obj_t)(&ubluepy_peripheral_write_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readCharacteristic), (mp_obj_t)(&ubluepy_peripheral_read_char_obj) }, + { MP_ROM_QSTR(MP_QSTR_addCharacteristic), MP_ROM_PTR(&ubluepy_peripheral_add_char_obj) }, + { MP_ROM_QSTR(MP_QSTR_addDescriptor), MP_ROM_PTR(&ubluepy_peripheral_add_desc_obj) }, + { MP_ROM_QSTR(MP_QSTR_writeCharacteristic), MP_ROM_PTR(&ubluepy_peripheral_write_char_obj) }, + { MP_ROM_QSTR(MP_QSTR_readCharacteristic), MP_ROM_PTR(&ubluepy_peripheral_read_char_obj) }, #endif #endif #if MICROPY_PY_UBLUEPY_BROADCASTER - { MP_OBJ_NEW_QSTR(MP_QSTR_advertise), (mp_obj_t)(&ubluepy_peripheral_advertise_obj) }, + { MP_ROM_QSTR(MP_QSTR_advertise), MP_ROM_PTR(&ubluepy_peripheral_advertise_obj) }, #endif #if MICROPY_PY_UBLUEPY_OBSERVER // Nothing yet. @@ -449,7 +449,7 @@ const mp_obj_type_t ubluepy_peripheral_type = { .name = MP_QSTR_Peripheral, .print = ubluepy_peripheral_print, .make_new = ubluepy_peripheral_make_new, - .locals_dict = (mp_obj_t)&ubluepy_peripheral_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_peripheral_locals_dict }; #endif // MICROPY_PY_UBLUEPY diff --git a/nrf5/modules/ubluepy/ubluepy_scan_entry.c b/nrf5/modules/ubluepy/ubluepy_scan_entry.c index bf7d704607..e9028f9320 100644 --- a/nrf5/modules/ubluepy/ubluepy_scan_entry.c +++ b/nrf5/modules/ubluepy/ubluepy_scan_entry.c @@ -127,11 +127,11 @@ STATIC mp_obj_t scan_entry_get_scan_data(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_scan_entry_get_scan_data_obj, scan_entry_get_scan_data); -STATIC const mp_map_elem_t ubluepy_scan_entry_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_addr), (mp_obj_t)(&bluepy_scan_entry_get_addr_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_addr_type), (mp_obj_t)(&bluepy_scan_entry_get_addr_type_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_rssi), (mp_obj_t)(&bluepy_scan_entry_get_rssi_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getScanData), (mp_obj_t)(&ubluepy_scan_entry_get_scan_data_obj) }, +STATIC const mp_rom_map_elem_t ubluepy_scan_entry_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_addr), MP_ROM_PTR(&bluepy_scan_entry_get_addr_obj) }, + { MP_ROM_QSTR(MP_QSTR_addr_type), MP_ROM_PTR(&bluepy_scan_entry_get_addr_type_obj) }, + { MP_ROM_QSTR(MP_QSTR_rssi), MP_ROM_PTR(&bluepy_scan_entry_get_rssi_obj) }, + { MP_ROM_QSTR(MP_QSTR_getScanData), MP_ROM_PTR(&ubluepy_scan_entry_get_scan_data_obj) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_scan_entry_locals_dict, ubluepy_scan_entry_locals_dict_table); @@ -140,7 +140,7 @@ const mp_obj_type_t ubluepy_scan_entry_type = { { &mp_type_type }, .name = MP_QSTR_ScanEntry, .print = ubluepy_scan_entry_print, - .locals_dict = (mp_obj_t)&ubluepy_scan_entry_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_scan_entry_locals_dict }; #endif // MICROPY_PY_UBLUEPY_CENTRAL diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf5/modules/ubluepy/ubluepy_scanner.c index 6946fbb5c8..b7c9b99758 100644 --- a/nrf5/modules/ubluepy/ubluepy_scanner.c +++ b/nrf5/modules/ubluepy/ubluepy_scanner.c @@ -106,8 +106,8 @@ STATIC mp_obj_t scanner_scan(mp_obj_t self_in, mp_obj_t timeout_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_scanner_scan_obj, scanner_scan); -STATIC const mp_map_elem_t ubluepy_scanner_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_scan), (mp_obj_t)(&ubluepy_scanner_scan_obj) }, +STATIC const mp_rom_map_elem_t ubluepy_scanner_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_scan), MP_ROM_PTR(&ubluepy_scanner_scan_obj) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_scanner_locals_dict, ubluepy_scanner_locals_dict_table); @@ -118,7 +118,7 @@ const mp_obj_type_t ubluepy_scanner_type = { .name = MP_QSTR_Scanner, .print = ubluepy_scanner_print, .make_new = ubluepy_scanner_make_new, - .locals_dict = (mp_obj_t)&ubluepy_scanner_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_scanner_locals_dict }; #endif // MICROPY_PY_UBLUEPY_CENTRAL diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf5/modules/ubluepy/ubluepy_service.c index 6523d22da5..3cff2377da 100644 --- a/nrf5/modules/ubluepy/ubluepy_service.c +++ b/nrf5/modules/ubluepy/ubluepy_service.c @@ -160,17 +160,17 @@ STATIC mp_obj_t service_uuid(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_service_get_uuid_obj, service_uuid); -STATIC const mp_map_elem_t ubluepy_service_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristic), (mp_obj_t)(&ubluepy_service_get_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_addCharacteristic), (mp_obj_t)(&ubluepy_service_add_char_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getCharacteristics), (mp_obj_t)(&ubluepy_service_get_chars_obj) }, +STATIC const mp_rom_map_elem_t ubluepy_service_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_getCharacteristic), MP_ROM_PTR(&ubluepy_service_get_char_obj) }, + { MP_ROM_QSTR(MP_QSTR_addCharacteristic), MP_ROM_PTR(&ubluepy_service_add_char_obj) }, + { MP_ROM_QSTR(MP_QSTR_getCharacteristics), MP_ROM_PTR(&ubluepy_service_get_chars_obj) }, #if 0 // Properties - { MP_OBJ_NEW_QSTR(MP_QSTR_peripheral), (mp_obj_t)(&ubluepy_service_get_peripheral_obj) }, + { MP_ROM_QSTR(MP_QSTR_peripheral), MP_ROM_PTR(&ubluepy_service_get_peripheral_obj) }, #endif - { MP_OBJ_NEW_QSTR(MP_QSTR_uuid), (mp_obj_t)(&ubluepy_service_get_uuid_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PRIMARY), MP_OBJ_NEW_SMALL_INT(UBLUEPY_SERVICE_PRIMARY) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_SECONDARY), MP_OBJ_NEW_SMALL_INT(UBLUEPY_SERVICE_SECONDARY) }, + { MP_ROM_QSTR(MP_QSTR_uuid), MP_ROM_PTR(&ubluepy_service_get_uuid_obj) }, + { MP_ROM_QSTR(MP_QSTR_PRIMARY), MP_ROM_INT(UBLUEPY_SERVICE_PRIMARY) }, + { MP_ROM_QSTR(MP_QSTR_SECONDARY), MP_ROM_INT(UBLUEPY_SERVICE_SECONDARY) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_service_locals_dict, ubluepy_service_locals_dict_table); @@ -180,7 +180,7 @@ const mp_obj_type_t ubluepy_service_type = { .name = MP_QSTR_Service, .print = ubluepy_service_print, .make_new = ubluepy_service_make_new, - .locals_dict = (mp_obj_t)&ubluepy_service_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_service_locals_dict }; #endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf5/modules/ubluepy/ubluepy_uuid.c index d5627bd2e1..1d34097c4a 100644 --- a/nrf5/modules/ubluepy/ubluepy_uuid.c +++ b/nrf5/modules/ubluepy/ubluepy_uuid.c @@ -152,12 +152,12 @@ STATIC mp_obj_t uuid_bin_val(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_uuid_bin_val_obj, uuid_bin_val); -STATIC const mp_map_elem_t ubluepy_uuid_locals_dict_table[] = { +STATIC const mp_rom_map_elem_t ubluepy_uuid_locals_dict_table[] = { #if 0 - { MP_OBJ_NEW_QSTR(MP_QSTR_getCommonName), (mp_obj_t)(&ubluepy_uuid_get_common_name_obj) }, + { MP_ROM_QSTR(MP_QSTR_getCommonName), MP_ROM_PTR(&ubluepy_uuid_get_common_name_obj) }, #endif // Properties - { MP_OBJ_NEW_QSTR(MP_QSTR_binVal), (mp_obj_t)(&ubluepy_uuid_bin_val_obj) }, + { MP_ROM_QSTR(MP_QSTR_binVal), MP_ROM_PTR(&ubluepy_uuid_bin_val_obj) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_uuid_locals_dict, ubluepy_uuid_locals_dict_table); @@ -167,7 +167,7 @@ const mp_obj_type_t ubluepy_uuid_type = { .name = MP_QSTR_UUID, .print = ubluepy_uuid_print, .make_new = ubluepy_uuid_make_new, - .locals_dict = (mp_obj_t)&ubluepy_uuid_locals_dict + .locals_dict = (mp_obj_dict_t*)&ubluepy_uuid_locals_dict }; #endif // MICROPY_PY_UBLUEPY diff --git a/nrf5/modules/uos/moduos.c b/nrf5/modules/uos/moduos.c index 0f814a9c55..da5a303152 100644 --- a/nrf5/modules/uos/moduos.c +++ b/nrf5/modules/uos/moduos.c @@ -128,36 +128,36 @@ STATIC mp_obj_t os_dupterm(mp_uint_t n_args, const mp_obj_t *args) { } MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mod_os_dupterm_obj, 0, 1, os_dupterm); -STATIC const mp_map_elem_t os_module_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_uos) }, +STATIC const mp_rom_map_elem_t os_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_uos) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_uname), (mp_obj_t)&os_uname_obj }, + { MP_ROM_QSTR(MP_QSTR_uname), MP_ROM_PTR(&os_uname_obj) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_chdir), (mp_obj_t)&mp_vfs_chdir_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_getcwd), (mp_obj_t)&mp_vfs_getcwd_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_listdir), (mp_obj_t)&mp_vfs_listdir_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_mkdir), (mp_obj_t)&mp_vfs_mkdir_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_remove), (mp_obj_t)&mp_vfs_remove_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_rename),(mp_obj_t)&mp_vfs_rename_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_rmdir), (mp_obj_t)&mp_vfs_rmdir_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_stat), (mp_obj_t)&mp_vfs_stat_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_statvfs), (mp_obj_t)&mp_vfs_statvfs_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_unlink), (mp_obj_t)&mp_vfs_remove_obj }, // unlink aliases to remove + { MP_ROM_QSTR(MP_QSTR_chdir), MP_ROM_PTR(&mp_vfs_chdir_obj) }, + { MP_ROM_QSTR(MP_QSTR_getcwd), MP_ROM_PTR(&mp_vfs_getcwd_obj) }, + { MP_ROM_QSTR(MP_QSTR_listdir), MP_ROM_PTR(&mp_vfs_listdir_obj) }, + { MP_ROM_QSTR(MP_QSTR_mkdir), MP_ROM_PTR(&mp_vfs_mkdir_obj) }, + { MP_ROM_QSTR(MP_QSTR_remove), MP_ROM_PTR(&mp_vfs_remove_obj) }, + { MP_ROM_QSTR(MP_QSTR_rename), MP_ROM_PTR(&mp_vfs_rename_obj) }, + { MP_ROM_QSTR(MP_QSTR_rmdir), MP_ROM_PTR(&mp_vfs_rmdir_obj) }, + { MP_ROM_QSTR(MP_QSTR_stat), MP_ROM_PTR(&mp_vfs_stat_obj) }, + { MP_ROM_QSTR(MP_QSTR_statvfs), MP_ROM_PTR(&mp_vfs_statvfs_obj) }, + { MP_ROM_QSTR(MP_QSTR_unlink), MP_ROM_PTR(&mp_vfs_remove_obj) }, // unlink aliases to remove - { MP_OBJ_NEW_QSTR(MP_QSTR_sync), (mp_obj_t)&mod_os_sync_obj }, + { MP_ROM_QSTR(MP_QSTR_sync), MP_ROM_PTR(&mod_os_sync_obj) }, /// \constant sep - separation character used in paths - { MP_OBJ_NEW_QSTR(MP_QSTR_sep), MP_OBJ_NEW_QSTR(MP_QSTR__slash_) }, + { MP_ROM_QSTR(MP_QSTR_sep), MP_ROM_QSTR(MP_QSTR__slash_) }, #if MICROPY_HW_ENABLE_RNG - { MP_OBJ_NEW_QSTR(MP_QSTR_urandom), (mp_obj_t)&os_urandom_obj }, + { MP_ROM_QSTR(MP_QSTR_urandom), MP_ROM_PTR(&os_urandom_obj) }, #endif // these are MicroPython extensions - { MP_OBJ_NEW_QSTR(MP_QSTR_dupterm), (mp_obj_t)&mod_os_dupterm_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_mount), (mp_obj_t)&mp_vfs_mount_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_umount), (mp_obj_t)&mp_vfs_umount_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_VfsFat), (mp_obj_t)&mp_fat_vfs_type }, + { MP_ROM_QSTR(MP_QSTR_dupterm), MP_ROM_PTR(&mod_os_dupterm_obj) }, + { MP_ROM_QSTR(MP_QSTR_mount), MP_ROM_PTR(&mp_vfs_mount_obj) }, + { MP_ROM_QSTR(MP_QSTR_umount), MP_ROM_PTR(&mp_vfs_umount_obj) }, + { MP_ROM_QSTR(MP_QSTR_VfsFat), MP_ROM_PTR(&mp_fat_vfs_type) }, }; STATIC MP_DEFINE_CONST_DICT(os_module_globals, os_module_globals_table); diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index f871f31df1..08167b5f55 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -189,13 +189,13 @@ extern const struct _mp_obj_module_t mp_module_ubluepy; extern const struct _mp_obj_module_t music_module; #if MICROPY_PY_UBLUEPY -#define UBLUEPY_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_ubluepy), (mp_obj_t)&mp_module_ubluepy }, +#define UBLUEPY_MODULE { MP_ROM_QSTR(MP_QSTR_ubluepy), MP_ROM_PTR(&mp_module_ubluepy) }, #else #define UBLUEPY_MODULE #endif #if MICROPY_PY_MUSIC -#define MUSIC_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_music), (mp_obj_t)&music_module }, +#define MUSIC_MODULE { MP_ROM_QSTR(MP_QSTR_music), MP_ROM_PTR(&music_module) }, #else #define MUSIC_MODULE #endif @@ -204,12 +204,12 @@ extern const struct _mp_obj_module_t music_module; #if BLUETOOTH_SD extern const struct _mp_obj_module_t ble_module; #define MICROPY_PORT_BUILTIN_MODULES \ - { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_ble), (mp_obj_t)&ble_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&mp_module_utime }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ + { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \ + { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) }, \ + { MP_ROM_QSTR(MP_QSTR_ble), MP_ROM_PTR(&ble_module) }, \ + { MP_ROM_QSTR(MP_QSTR_utime), MP_ROM_PTR(&mp_module_utime) }, \ + { MP_ROM_QSTR(MP_QSTR_time), MP_ROM_PTR(&mp_module_utime) }, \ + { MP_ROM_QSTR(MP_QSTR_uos), MP_ROM_PTR(&mp_module_uos) }, \ MUSIC_MODULE \ UBLUEPY_MODULE \ @@ -217,29 +217,29 @@ extern const struct _mp_obj_module_t ble_module; #else extern const struct _mp_obj_module_t ble_module; #define MICROPY_PORT_BUILTIN_MODULES \ - { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_uos), (mp_obj_t)&mp_module_uos }, \ + { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \ + { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) }, \ + { MP_ROM_QSTR(MP_QSTR_utime), MP_ROM_PTR(&mp_module_utime) }, \ + { MP_ROM_QSTR(MP_QSTR_uos), MP_ROM_PTR(&mp_module_uos) }, \ MUSIC_MODULE \ #endif // BLUETOOTH_SD #define MICROPY_PORT_BUILTIN_MODULE_WEAK_LINKS \ - { MP_OBJ_NEW_QSTR(MP_QSTR_os), (mp_obj_t)&mp_module_uos }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&mp_module_utime }, \ + { MP_ROM_QSTR(MP_QSTR_os), MP_ROM_PTR(&mp_module_uos) }, \ + { MP_ROM_QSTR(MP_QSTR_time), MP_ROM_PTR(&mp_module_utime) }, \ // extra built in names to add to the global namespace #define MICROPY_PORT_BUILTINS \ - { MP_OBJ_NEW_QSTR(MP_QSTR_help), (mp_obj_t)&mp_builtin_help_obj }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_open), (mp_obj_t)&mp_builtin_open_obj }, \ + { MP_ROM_QSTR(MP_QSTR_help), MP_ROM_PTR(&mp_builtin_help_obj) }, \ + { MP_ROM_QSTR(MP_QSTR_open), MP_ROM_PTR(&mp_builtin_open_obj) }, \ // extra constants #define MICROPY_PORT_CONSTANTS \ - { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_ble), (mp_obj_t)&ble_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \ + { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \ + { MP_ROM_QSTR(MP_QSTR_ble), MP_ROM_PTR(&ble_module) }, \ + { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) }, \ #define MP_STATE_PORT MP_STATE_VM From b24501125964f7ab5153ab057ae4c93c2d47a661 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 11 May 2017 00:04:10 +0200 Subject: [PATCH 666/809] nrf5/modules/machine: bugfix after changing to MP_ROM_PTR in machine module local dict. --- nrf5/modules/machine/modmachine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/machine/modmachine.c b/nrf5/modules/machine/modmachine.c index 0901e6836b..443baa9ffb 100644 --- a/nrf5/modules/machine/modmachine.c +++ b/nrf5/modules/machine/modmachine.c @@ -218,7 +218,7 @@ STATIC const mp_rom_map_elem_t machine_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_Timer), MP_ROM_PTR(&machine_timer_type) }, #endif #if MICROPY_PY_MACHINE_HW_PWM - { MP_ROM_QSTR(MP_QSTR_PWM), MP_ROM_PTR(mp_obj_t)&machine_hard_pwm_type) }, + { MP_ROM_QSTR(MP_QSTR_PWM), MP_ROM_PTR(&machine_hard_pwm_type) }, #endif #if MICROPY_PY_MACHINE_TEMP { MP_ROM_QSTR(MP_QSTR_Temp), MP_ROM_PTR(&machine_temp_type) }, From d61dcf18fb2d9e27ad08a17d9da77278bb319ece Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 11 May 2017 18:32:18 +0200 Subject: [PATCH 667/809] nrf5/bluetooth: Moving help_sd.h and modble.c to modules/ble. --- nrf5/{bluetooth => modules/ble}/help_sd.h | 0 nrf5/{bluetooth => modules/ble}/modble.c | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/{bluetooth => modules/ble}/help_sd.h (100%) rename nrf5/{bluetooth => modules/ble}/modble.c (100%) diff --git a/nrf5/bluetooth/help_sd.h b/nrf5/modules/ble/help_sd.h similarity index 100% rename from nrf5/bluetooth/help_sd.h rename to nrf5/modules/ble/help_sd.h diff --git a/nrf5/bluetooth/modble.c b/nrf5/modules/ble/modble.c similarity index 100% rename from nrf5/bluetooth/modble.c rename to nrf5/modules/ble/modble.c From 4676e5900b6744fb4fe0c85a1ba3233a19ae71b7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 11 May 2017 18:34:12 +0200 Subject: [PATCH 668/809] nrf5/bluetooth: Moving makefile include folder and source files of bluetooth driver, ble uart and ble module to main Makefile. --- nrf5/Makefile | 5 +++++ nrf5/bluetooth/bluetooth_common.mk | 7 ------- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index fa24ae0fb2..6d6f043635 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -54,7 +54,9 @@ INC += -I./hal INC += -I./hal/$(MCU_VARIANT) INC += -I./modules/machine INC += -I./modules/ubluepy +INC += -I./modules/ble INC += -I../lib/mp-readline +INC += -I./bluetooth NRF_DEFINES += -D$(MCU_VARIANT_UPPER) NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET @@ -127,6 +129,8 @@ SRC_C += \ pin_named_pins.c \ fatfs_port.c \ drivers/pwm.c \ + bluetooth/ble_drv.c \ + bluetooth/ble_uart.c \ DRIVERS_SRC_C += $(addprefix modules/,\ machine/modmachine.c \ @@ -155,6 +159,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ ubluepy/ubluepy_scan_entry.c \ music/modmusic.c \ music/musictunes.c \ + ble/modble.c \ ) #ifeq ($(SD), ) diff --git a/nrf5/bluetooth/bluetooth_common.mk b/nrf5/bluetooth/bluetooth_common.mk index 0c1b8fabf2..84999efef6 100644 --- a/nrf5/bluetooth/bluetooth_common.mk +++ b/nrf5/bluetooth/bluetooth_common.mk @@ -53,10 +53,3 @@ SOFTDEV_HEX = $(SOFTDEV_HEX_PATH)/$(SOFTDEV_HEX_NAME) ifeq ($(shell test ! -e $(SOFTDEV_HEX) && echo -n no),no) $(error $(STACK_MISSING_ERROR)) endif - -INC += -I./bluetooth - -SRC_C += \ - bluetooth/modble.c \ - bluetooth/ble_drv.c \ - bluetooth/ble_uart.c From e69e47bc241a73c6965b7127560d3599ce03c1bf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 11 May 2017 18:37:48 +0200 Subject: [PATCH 669/809] nrf5/bluetooth: Guarding implementation against being linked in by surrounding it with BLUETOOTH_SD flag. Flag is only set if SD= parameter is provided during make. --- nrf5/bluetooth/ble_drv.c | 4 ++++ nrf5/bluetooth/ble_drv.h | 4 ++++ nrf5/bluetooth/ble_uart.c | 3 +++ nrf5/bluetooth/ble_uart.h | 5 +++++ 4 files changed, 16 insertions(+) diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/bluetooth/ble_drv.c index 45338c42df..1a5dc5e00d 100644 --- a/nrf5/bluetooth/ble_drv.c +++ b/nrf5/bluetooth/ble_drv.c @@ -24,6 +24,8 @@ * THE SOFTWARE. */ +#if BLUETOOTH_SD + #include #include #include @@ -1003,3 +1005,5 @@ void SWI2_EGU2_IRQHandler(void) { ble_evt_handler((ble_evt_t *)m_ble_evt_buf); } while (err_code != NRF_ERROR_NOT_FOUND && err_code != NRF_SUCCESS); } + +#endif // BLUETOOTH_SD diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/bluetooth/ble_drv.h index 4ebc249023..08cda8e4fa 100644 --- a/nrf5/bluetooth/ble_drv.h +++ b/nrf5/bluetooth/ble_drv.h @@ -27,6 +27,8 @@ #ifndef BLUETOOTH_LE_DRIVER_H__ #define BLUETOOTH_LE_DRIVER_H__ +#if BLUETOOTH_SD + #include #include @@ -120,4 +122,6 @@ bool ble_drv_discover_characteristic(mp_obj_t obj, void ble_drv_discover_descriptors(void); +#endif // BLUETOOTH_SD + #endif // BLUETOOTH_LE_DRIVER_H__ diff --git a/nrf5/bluetooth/ble_uart.c b/nrf5/bluetooth/ble_uart.c index bb5292bf5d..a2f8e1a7d2 100644 --- a/nrf5/bluetooth/ble_uart.c +++ b/nrf5/bluetooth/ble_uart.c @@ -24,6 +24,8 @@ * THE SOFTWARE. */ +#if BLUETOOTH_SD + #include #include "ble_uart.h" #include "ringbuffer.h" @@ -263,3 +265,4 @@ bool ble_uart_enabled(void) { #endif // MICROPY_PY_BLE_NUS +#endif // BLUETOOTH_SD diff --git a/nrf5/bluetooth/ble_uart.h b/nrf5/bluetooth/ble_uart.h index e84e5ed0fa..eadc7b37ab 100644 --- a/nrf5/bluetooth/ble_uart.h +++ b/nrf5/bluetooth/ble_uart.h @@ -27,6 +27,8 @@ #ifndef BLUETOOTH_LE_UART_H__ #define BLUETOOTH_LE_UART_H__ +#if BLUETOOTH_SD + #include "modubluepy.h" #include "ble_drv.h" @@ -34,4 +36,7 @@ void ble_uart_init0(void); void ble_uart_advertise(void); bool ble_uart_connected(void); bool ble_uart_enabled(void); + +#endif // BLUETOOTH_SD + #endif // BLUETOOTH_LE_UART_H__ From bdaa714f8549516a781a16961bbcf8eedfe278da Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 11 May 2017 18:43:25 +0200 Subject: [PATCH 670/809] nrf5/bluetooth: Move bluetooth driver files to drivers/bluetooth. Move bluetooth stack download script to root folder. --- nrf5/{bluetooth => }/download_ble_stack.sh | 0 nrf5/{ => drivers}/bluetooth/ble_drv.c | 0 nrf5/{ => drivers}/bluetooth/ble_drv.h | 0 nrf5/{ => drivers}/bluetooth/ble_uart.c | 0 nrf5/{ => drivers}/bluetooth/ble_uart.h | 0 nrf5/{ => drivers}/bluetooth/bluetooth_common.mk | 0 nrf5/{ => drivers}/bluetooth/ringbuffer.h | 0 7 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/{bluetooth => }/download_ble_stack.sh (100%) rename nrf5/{ => drivers}/bluetooth/ble_drv.c (100%) rename nrf5/{ => drivers}/bluetooth/ble_drv.h (100%) rename nrf5/{ => drivers}/bluetooth/ble_uart.c (100%) rename nrf5/{ => drivers}/bluetooth/ble_uart.h (100%) rename nrf5/{ => drivers}/bluetooth/bluetooth_common.mk (100%) rename nrf5/{ => drivers}/bluetooth/ringbuffer.h (100%) diff --git a/nrf5/bluetooth/download_ble_stack.sh b/nrf5/download_ble_stack.sh similarity index 100% rename from nrf5/bluetooth/download_ble_stack.sh rename to nrf5/download_ble_stack.sh diff --git a/nrf5/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c similarity index 100% rename from nrf5/bluetooth/ble_drv.c rename to nrf5/drivers/bluetooth/ble_drv.c diff --git a/nrf5/bluetooth/ble_drv.h b/nrf5/drivers/bluetooth/ble_drv.h similarity index 100% rename from nrf5/bluetooth/ble_drv.h rename to nrf5/drivers/bluetooth/ble_drv.h diff --git a/nrf5/bluetooth/ble_uart.c b/nrf5/drivers/bluetooth/ble_uart.c similarity index 100% rename from nrf5/bluetooth/ble_uart.c rename to nrf5/drivers/bluetooth/ble_uart.c diff --git a/nrf5/bluetooth/ble_uart.h b/nrf5/drivers/bluetooth/ble_uart.h similarity index 100% rename from nrf5/bluetooth/ble_uart.h rename to nrf5/drivers/bluetooth/ble_uart.h diff --git a/nrf5/bluetooth/bluetooth_common.mk b/nrf5/drivers/bluetooth/bluetooth_common.mk similarity index 100% rename from nrf5/bluetooth/bluetooth_common.mk rename to nrf5/drivers/bluetooth/bluetooth_common.mk diff --git a/nrf5/bluetooth/ringbuffer.h b/nrf5/drivers/bluetooth/ringbuffer.h similarity index 100% rename from nrf5/bluetooth/ringbuffer.h rename to nrf5/drivers/bluetooth/ringbuffer.h From 3d503cf7a83ef7b52f388489598fe25d87713279 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 11 May 2017 18:47:12 +0200 Subject: [PATCH 671/809] nrf5/bluetooth: Moving stack download script to drivers/bluetooth folder. --- nrf5/{ => drivers/bluetooth}/download_ble_stack.sh | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename nrf5/{ => drivers/bluetooth}/download_ble_stack.sh (100%) diff --git a/nrf5/download_ble_stack.sh b/nrf5/drivers/bluetooth/download_ble_stack.sh similarity index 100% rename from nrf5/download_ble_stack.sh rename to nrf5/drivers/bluetooth/download_ble_stack.sh From 96b203b729e8efefafa1ff8ef33b6f10093fdd44 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 11 May 2017 18:53:53 +0200 Subject: [PATCH 672/809] nrf5/bluetooth: Updating makefiles with updated paths to bluetooth le components after moving files. --- nrf5/Makefile | 8 ++++---- nrf5/drivers/bluetooth/bluetooth_common.mk | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 6d6f043635..493beacae8 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -23,7 +23,7 @@ else include ../py/mkenv.mk include boards/$(BOARD)/mpconfigboard_$(SD_LOWER).mk - include bluetooth/bluetooth_common.mk + include drivers/bluetooth/bluetooth_common.mk endif # qstr definitions (must come before including py.mk) @@ -56,7 +56,7 @@ INC += -I./modules/machine INC += -I./modules/ubluepy INC += -I./modules/ble INC += -I../lib/mp-readline -INC += -I./bluetooth +INC += -I./drivers/bluetooth NRF_DEFINES += -D$(MCU_VARIANT_UPPER) NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET @@ -129,8 +129,8 @@ SRC_C += \ pin_named_pins.c \ fatfs_port.c \ drivers/pwm.c \ - bluetooth/ble_drv.c \ - bluetooth/ble_uart.c \ + drivers/bluetooth/ble_drv.c \ + drivers/bluetooth/ble_uart.c \ DRIVERS_SRC_C += $(addprefix modules/,\ machine/modmachine.c \ diff --git a/nrf5/drivers/bluetooth/bluetooth_common.mk b/nrf5/drivers/bluetooth/bluetooth_common.mk index 84999efef6..38c604e04c 100644 --- a/nrf5/drivers/bluetooth/bluetooth_common.mk +++ b/nrf5/drivers/bluetooth/bluetooth_common.mk @@ -3,19 +3,19 @@ SOFTDEV_HEX_NAME ?= SOFTDEV_HEX_PATH ?= ifeq ($(SD), s110) - INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include + INC += -Idrivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include CFLAGS += -DBLUETOOTH_SD_DEBUG=1 CFLAGS += -DBLUETOOTH_SD=110 SOFTDEV_HEX_NAME = $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_softdevice.hex - SOFTDEV_HEX_PATH = bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION) + SOFTDEV_HEX_PATH = drivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION) else ifeq ($(SD), s120) $(error No BLE wrapper available yet) else ifeq ($(SD), s130) $(error No BLE wrapper available yet) else ifeq ($(SD), s132) - INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include - INC += -Ibluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include/$(MCU_VARIANT) + INC += -Idrivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include + INC += -Idrivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include/$(MCU_VARIANT) CFLAGS += -DBLUETOOTH_SD_DEBUG=1 CFLAGS += -DBLUETOOTH_SD=132 @@ -26,7 +26,7 @@ else ifeq ($(SOFTDEV_VERSION), 3.0.0) endif SOFTDEV_HEX_NAME = $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_softdevice.hex - SOFTDEV_HEX_PATH = bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION) + SOFTDEV_HEX_PATH = drivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION) else $(error Incorrect softdevice set flag) endif @@ -41,7 +41,7 @@ define STACK_MISSING_ERROR # # # Please run the download script: # # # -# bluetooth/download_ble_stack.sh # +# drivers/bluetooth/download_ble_stack.sh # # # ####################################################### From 18e73d4214fd52ddb5b1b7ca7dd54f5827f2e775 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 12 May 2017 20:09:26 +0200 Subject: [PATCH 673/809] nrf5/modules/ubluepy: Fixing compilation bug of wrong variable name when registering gattc event handler in ublupy peripheral connect function (central mode). --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index d8f450c3a5..7afa3839bc 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -372,7 +372,7 @@ STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { ; } - ble_drv_gattc_event_handler_set(MP_OBJ_FROM_PTR(s), gattc_event_handler); + ble_drv_gattc_event_handler_set(MP_OBJ_FROM_PTR(self), gattc_event_handler); bool retval = ble_drv_discover_services(self, self->conn_handle, disc_add_service); if (retval != true) { From 0865fbd92df613fa9e40f35ffaf6fd3cdc2dd77e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 13 May 2017 15:05:22 +0200 Subject: [PATCH 674/809] nrf5/modules/ubluepy: Register central GAP event handler before issuing connect to a peripheral. Has to be done before connect() function as a connected event will be propergated upon successfull connection. The handler will set the connection handle which gets connect function out of the busy loop waiting for connection to succeed. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 7afa3839bc..06922c5e2b 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -342,6 +342,8 @@ void static disc_add_char(mp_obj_t service_in, ble_drv_char_data_t * p_desc_data STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); + ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(self), gap_event_handler); + if (MP_OBJ_IS_STR(dev_addr)) { GET_STR_DATA_LEN(dev_addr, str_data, str_len); if (str_len == 17) { // Example "11:22:33:aa:bb:cc" From 4584ef4acee32bcd2a8895fb62973e944fe7d0cc Mon Sep 17 00:00:00 2001 From: glennrub Date: Sat, 13 May 2017 16:12:14 +0200 Subject: [PATCH 675/809] Support address types (#18) * nrf5/modules/ubluepy: Adding new enumeration of address types. * nrf5/modules/ubluepy: Adding constants that can be used from micropython for public and random static address types. * nrf5/modules/ubluepy: Adding support for optionally setting address type in Peripheral.connect(). Public address is used as default. Address types can be retrieved from 'constants'. Either constants.ADDR_TYPE_PUBLIC or constants.ADDR_TYPE_RANDOM_STATIC. * nrf5/modules/ubluepy: Register central GAP event handler before issuing connect to a peripheral. Has to be done before connect() function as a connected event will be propergated upon successfull connection. The handler will set the connection handle which gets connect function out of the busy loop waiting for connection to succeed. * nrf5/modules/ubluepy: Removing duplicate setting of GAP event handler in connect(). --- nrf5/modules/ubluepy/modubluepy.h | 9 ++++++++ nrf5/modules/ubluepy/ubluepy_constants.c | 11 ++++++---- nrf5/modules/ubluepy/ubluepy_peripheral.c | 25 ++++++++++++++++++----- 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 1560fa0467..aa5e6a7ffa 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -92,6 +92,15 @@ typedef enum { UBLUEPY_SERVICE_SECONDARY = 2 } ubluepy_service_type_t; +typedef enum { + UBLUEPY_ADDR_TYPE_PUBLIC = 0, + UBLUEPY_ADDR_TYPE_RANDOM_STATIC = 1, +#if 0 + UBLUEPY_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE = 2, + UBLUEPY_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE = 3, +#endif +} ubluepy_addr_type_t; + typedef struct _ubluepy_uuid_obj_t { mp_obj_base_t base; ubluepy_uuid_type_t type; diff --git a/nrf5/modules/ubluepy/ubluepy_constants.c b/nrf5/modules/ubluepy/ubluepy_constants.c index 7c7a8168dd..5e12661e02 100644 --- a/nrf5/modules/ubluepy/ubluepy_constants.c +++ b/nrf5/modules/ubluepy/ubluepy_constants.c @@ -77,11 +77,14 @@ const mp_obj_type_t ubluepy_constants_ad_types_type = { STATIC const mp_rom_map_elem_t ubluepy_constants_locals_dict_table[] = { // GAP events - { MP_ROM_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_ROM_INT(16) }, - { MP_ROM_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_ROM_INT(17) }, - { MP_ROM_QSTR(MP_QSTR_UUID_CCCD), MP_ROM_INT(0x2902) }, + { MP_ROM_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_ROM_INT(16) }, + { MP_ROM_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_ROM_INT(17) }, + { MP_ROM_QSTR(MP_QSTR_UUID_CCCD), MP_ROM_INT(0x2902) }, - { MP_ROM_QSTR(MP_QSTR_ad_types), MP_ROM_PTR(&ubluepy_constants_ad_types_type) }, + { MP_ROM_QSTR(MP_QSTR_ADDR_TYPE_PUBLIC), MP_ROM_INT(UBLUEPY_ADDR_TYPE_PUBLIC) }, + { MP_ROM_QSTR(MP_QSTR_ADDR_TYPE_RANDOM_STATIC), MP_ROM_INT(UBLUEPY_ADDR_TYPE_RANDOM_STATIC) }, + + { MP_ROM_QSTR(MP_QSTR_ad_types), MP_ROM_PTR(&ubluepy_constants_ad_types_type) }, }; STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_locals_dict, ubluepy_constants_locals_dict_table); diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 06922c5e2b..4f3a93f82a 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -336,11 +336,26 @@ void static disc_add_char(mp_obj_t service_in, ble_drv_char_data_t * p_desc_data mp_obj_list_append(p_service->char_list, MP_OBJ_FROM_PTR(p_char)); } -/// \method connect(device_address) +/// \method connect(device_address [, addr_type=ADDR_TYPE_PUBLIC]) /// Connect to device peripheral with the given device address. +/// addr_type can be either ADDR_TYPE_PUBLIC (default) or +/// ADDR_TYPE_RANDOM_STATIC. /// -STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { - ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in); +STATIC mp_obj_t peripheral_connect(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + mp_obj_t dev_addr = pos_args[1]; + + static const mp_arg_t allowed_args[] = { + { MP_QSTR_addr_type, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UBLUEPY_ADDR_TYPE_PUBLIC } }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 2, pos_args + 2, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + uint8_t addr_type = args[0].u_int; + + ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(self), gap_event_handler); ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(self), gap_event_handler); @@ -363,7 +378,7 @@ STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { p_addr[5] = unichar_xdigit_value(str_data[1]); p_addr[5] += unichar_xdigit_value(str_data[0]) << 4; - ble_drv_connect(p_addr, 1); + ble_drv_connect(p_addr, addr_type); m_del(uint8_t, p_addr, 6); } @@ -403,7 +418,7 @@ STATIC mp_obj_t peripheral_connect(mp_obj_t self_in, mp_obj_t dev_addr) { return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_connect_obj, peripheral_connect); +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(ubluepy_peripheral_connect_obj, 2, peripheral_connect); #endif From 34208437746a0959af83684edba098b2d6b035e6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 13 May 2017 16:15:47 +0200 Subject: [PATCH 676/809] nrf5/modules/ubluepy: Remove duplication GAP event handler registration in peripheral.connect(). --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 4f3a93f82a..ac1584d044 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -357,8 +357,6 @@ STATIC mp_obj_t peripheral_connect(mp_uint_t n_args, const mp_obj_t *pos_args, m ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(self), gap_event_handler); - ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(self), gap_event_handler); - if (MP_OBJ_IS_STR(dev_addr)) { GET_STR_DATA_LEN(dev_addr, str_data, str_len); if (str_len == 17) { // Example "11:22:33:aa:bb:cc" From b4f96a1dc3fb7902b9a26ea27b7c685c78736ec2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 13 May 2017 18:03:50 +0200 Subject: [PATCH 677/809] nrf5/drivers/bluetooth: Updating primary service discovery api to take in start handle from where to start the service discovery. Also adjusting return parameter to signal whether anything was found or not. --- nrf5/drivers/bluetooth/ble_drv.c | 19 +++++++++++++++---- nrf5/drivers/bluetooth/ble_drv.h | 2 +- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index 1a5dc5e00d..5972fe7be6 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -67,6 +67,7 @@ if (ble_drv_stack_enabled() == 0) { \ static volatile bool m_adv_in_progress; static volatile bool m_tx_in_progress; +static volatile bool m_primary_service_found; static ble_drv_gap_evt_callback_t gap_event_handler; static ble_drv_gatts_evt_callback_t gatts_event_handler; @@ -755,16 +756,18 @@ void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) { } } -bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, ble_drv_disc_add_service_callback_t cb) { +bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, uint16_t start_handle, ble_drv_disc_add_service_callback_t cb) { BLE_DRIVER_LOG("Discover primary services. Conn handle: 0x" HEX2_FMT "\n", conn_handle); mp_gattc_disc_service_observer = obj; disc_add_service_handler = cb; + m_primary_service_found = false; + uint32_t err_code; err_code = sd_ble_gattc_primary_services_discover(conn_handle, - 0x0001, + start_handle, NULL); if (err_code != 0) { return false; @@ -775,7 +778,11 @@ bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, ble_drv_disc_ ; } - return true; + if (m_primary_service_found) { + return true; + } else { + return false; + } } bool ble_drv_discover_characteristic(mp_obj_t obj, @@ -907,7 +914,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: BLE_DRIVER_LOG("BLE EVT PRIMARY SERVICE DISCOVERY RESPONSE\n"); - + BLE_DRIVER_LOG(">>> service count: %d\n", p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count); for (uint16_t i = 0; i < p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count; i++) { ble_gattc_service_t * p_service = &p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.services[i]; @@ -920,6 +927,10 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { disc_add_service_handler(mp_gattc_disc_service_observer, &service); } + if (p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count > 0) { + m_primary_service_found = true; + } + // mark end of service discovery disc_add_service_handler = NULL; diff --git a/nrf5/drivers/bluetooth/ble_drv.h b/nrf5/drivers/bluetooth/ble_drv.h index 08cda8e4fa..07f149695d 100644 --- a/nrf5/drivers/bluetooth/ble_drv.h +++ b/nrf5/drivers/bluetooth/ble_drv.h @@ -112,7 +112,7 @@ void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type); -bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, ble_drv_disc_add_service_callback_t cb); +bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, uint16_t start_handle, ble_drv_disc_add_service_callback_t cb); bool ble_drv_discover_characteristic(mp_obj_t obj, uint16_t conn_handle, From 370c20ff6c3a6c362c140dacb6c31200e877e923 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 13 May 2017 18:10:33 +0200 Subject: [PATCH 678/809] nrf5/modules/ubluepy: Continue primary service discovery until nothing more is found in connect proceedure. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index ac1584d044..a68e46f4a6 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -389,10 +389,21 @@ STATIC mp_obj_t peripheral_connect(mp_uint_t n_args, const mp_obj_t *pos_args, m ble_drv_gattc_event_handler_set(MP_OBJ_FROM_PTR(self), gattc_event_handler); - bool retval = ble_drv_discover_services(self, self->conn_handle, disc_add_service); - if (retval != true) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Error during service discovery")); + bool service_disc_retval = ble_drv_discover_services(self, self->conn_handle, 0x0001, disc_add_service); + + // continue discovery of primary services ... + while (service_disc_retval) { + // locate the last added service + mp_obj_t * services = NULL; + mp_uint_t num_services; + mp_obj_get_array(self->service_list, &num_services, &services); + + ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)services[num_services - 1]; + + service_disc_retval = ble_drv_discover_services(self, + self->conn_handle, + p_service->end_handle, + disc_add_service); } // For each service perform a characteristic discovery From e8cd010f593b107798dd697c0f634d08588605b7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 17:11:29 +0200 Subject: [PATCH 679/809] nrf5/drivers/bluetooth: Updating characteristic discovery to signal whether anything was found or not. --- nrf5/drivers/bluetooth/ble_drv.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index 5972fe7be6..3961d609e8 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -68,6 +68,7 @@ if (ble_drv_stack_enabled() == 0) { \ static volatile bool m_adv_in_progress; static volatile bool m_tx_in_progress; static volatile bool m_primary_service_found; +static volatile bool m_characteristic_found; static ble_drv_gap_evt_callback_t gap_event_handler; static ble_drv_gatts_evt_callback_t gatts_event_handler; @@ -800,6 +801,8 @@ bool ble_drv_discover_characteristic(mp_obj_t obj, handle_range.start_handle = start_handle; handle_range.end_handle = end_handle; + m_characteristic_found = false; + uint32_t err_code; err_code = sd_ble_gattc_characteristics_discover(conn_handle, &handle_range); if (err_code != 0) { @@ -811,7 +814,11 @@ bool ble_drv_discover_characteristic(mp_obj_t obj, ; } - return true; + if (m_characteristic_found) { + return true; + } else { + return false; + } } void ble_drv_discover_descriptors(void) { @@ -938,7 +945,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GATTC_EVT_CHAR_DISC_RSP: BLE_DRIVER_LOG("BLE EVT CHAR DISCOVERY RESPONSE\n"); - + BLE_DRIVER_LOG(">>> characteristic count: %d\n", p_ble_evt->evt.gattc_evt.params.char_disc_rsp.count); for (uint16_t i = 0; i < p_ble_evt->evt.gattc_evt.params.char_disc_rsp.count; i++) { ble_gattc_char_t * p_char = &p_ble_evt->evt.gattc_evt.params.char_disc_rsp.chars[i]; @@ -961,6 +968,10 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { disc_add_char_handler(mp_gattc_disc_char_observer, &char_data); } + if (p_ble_evt->evt.gattc_evt.params.char_disc_rsp.count > 0) { + m_characteristic_found = true; + } + // mark end of characteristic discovery disc_add_char_handler = NULL; From 653f4a86d529ab979b22e0cf5e61f77b309ad93b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 17:14:57 +0200 Subject: [PATCH 680/809] nrf5/drivers/bluetooth: Refactoring code to group statics for s130 and s132 into the same ifdef. Also adding two empty lines in discovery functions to make it more easy to read. --- nrf5/drivers/bluetooth/ble_drv.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index 3961d609e8..0050c91417 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -67,24 +67,23 @@ if (ble_drv_stack_enabled() == 0) { \ static volatile bool m_adv_in_progress; static volatile bool m_tx_in_progress; -static volatile bool m_primary_service_found; -static volatile bool m_characteristic_found; static ble_drv_gap_evt_callback_t gap_event_handler; static ble_drv_gatts_evt_callback_t gatts_event_handler; -#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) -static ble_drv_adv_evt_callback_t adv_event_handler; -static ble_drv_gattc_evt_callback_t gattc_event_handler; -static ble_drv_disc_add_service_callback_t disc_add_service_handler; -static ble_drv_disc_add_char_callback_t disc_add_char_handler; -static ble_drv_gattc_char_data_callback_t gattc_char_data_handle; -#endif - static mp_obj_t mp_gap_observer; static mp_obj_t mp_gatts_observer; #if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) +static volatile bool m_primary_service_found; +static volatile bool m_characteristic_found; + +static ble_drv_adv_evt_callback_t adv_event_handler; +static ble_drv_gattc_evt_callback_t gattc_event_handler; +static ble_drv_disc_add_service_callback_t disc_add_service_handler; +static ble_drv_disc_add_char_callback_t disc_add_char_handler; +static ble_drv_gattc_char_data_callback_t gattc_char_data_handle; + static mp_obj_t mp_adv_observer; static mp_obj_t mp_gattc_observer; static mp_obj_t mp_gattc_disc_service_observer; @@ -922,6 +921,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: BLE_DRIVER_LOG("BLE EVT PRIMARY SERVICE DISCOVERY RESPONSE\n"); BLE_DRIVER_LOG(">>> service count: %d\n", p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count); + for (uint16_t i = 0; i < p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count; i++) { ble_gattc_service_t * p_service = &p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.services[i]; @@ -946,6 +946,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GATTC_EVT_CHAR_DISC_RSP: BLE_DRIVER_LOG("BLE EVT CHAR DISCOVERY RESPONSE\n"); BLE_DRIVER_LOG(">>> characteristic count: %d\n", p_ble_evt->evt.gattc_evt.params.char_disc_rsp.count); + for (uint16_t i = 0; i < p_ble_evt->evt.gattc_evt.params.char_disc_rsp.count; i++) { ble_gattc_char_t * p_char = &p_ble_evt->evt.gattc_evt.params.char_disc_rsp.chars[i]; From 78c08212163a845b40e39af1755c823019785e52 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 18:04:27 +0200 Subject: [PATCH 681/809] nrf5/modules/ubluepy: Continue characteristic discovery until nothing more is found during connect proceedure. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 31 ++++++++++++++++------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index a68e46f4a6..19c59a1a63 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -402,7 +402,7 @@ STATIC mp_obj_t peripheral_connect(mp_uint_t n_args, const mp_obj_t *pos_args, m service_disc_retval = ble_drv_discover_services(self, self->conn_handle, - p_service->end_handle, + p_service->end_handle + 1, disc_add_service); } @@ -413,15 +413,28 @@ STATIC mp_obj_t peripheral_connect(mp_uint_t n_args, const mp_obj_t *pos_args, m for (uint16_t s = 0; s < num_services; s++) { ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)services[s]; + bool char_disc_retval = ble_drv_discover_characteristic(p_service, + self->conn_handle, + p_service->start_handle, + p_service->end_handle, + disc_add_char); + // continue discovery of characteristics ... + while (char_disc_retval) { + mp_obj_t * characteristics = NULL; + mp_uint_t num_chars; + mp_obj_get_array(p_service->char_list, &num_chars, &characteristics); - bool retval = ble_drv_discover_characteristic(p_service, - self->conn_handle, - p_service->start_handle, - p_service->end_handle, - disc_add_char); - if (retval != true) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, - "Error during characteristic discovery")); + ubluepy_characteristic_obj_t * p_char = (ubluepy_characteristic_obj_t *)characteristics[num_chars - 1]; + uint16_t next_handle = p_char->handle + 1; + if ((next_handle) < p_service->end_handle) { + char_disc_retval = ble_drv_discover_characteristic(p_service, + self->conn_handle, + next_handle, + p_service->end_handle, + disc_add_char); + } else { + break; + } } } From f8c0ff6413e9a096a9b64f8ac9dcf6776a44fc4d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 18:28:49 +0200 Subject: [PATCH 682/809] nrf5/drivers/bluetooth: Adding role member to peripheral object to indicate whether Peripheral object is Peripheral or Central role. --- nrf5/modules/ubluepy/modubluepy.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index aa5e6a7ffa..c7778d3c3d 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -101,6 +101,11 @@ typedef enum { #endif } ubluepy_addr_type_t; +typedef enum { + UBLUEPY_ROLE_PERIPHERAL, + UBLUEPY_ROLE_CENTRAL +} ubluepy_role_type_t; + typedef struct _ubluepy_uuid_obj_t { mp_obj_base_t base; ubluepy_uuid_type_t type; @@ -109,12 +114,13 @@ typedef struct _ubluepy_uuid_obj_t { } ubluepy_uuid_obj_t; typedef struct _ubluepy_peripheral_obj_t { - mp_obj_base_t base; - uint16_t conn_handle; - mp_obj_t delegate; - mp_obj_t notif_handler; - mp_obj_t conn_handler; - mp_obj_t service_list; + mp_obj_base_t base; + ubluepy_role_type_t role; + uint16_t conn_handle; + mp_obj_t delegate; + mp_obj_t notif_handler; + mp_obj_t conn_handler; + mp_obj_t service_list; } ubluepy_peripheral_obj_t; typedef struct _ubluepy_service_obj_t { From cf0d2bb457e04fc0f8ad32700f115263571630e2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 18:29:41 +0200 Subject: [PATCH 683/809] nrf5/modules/ubluepy: Setting peripheral role upon advertise() or connect(). --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index 19c59a1a63..f2a99508f1 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -178,6 +178,8 @@ STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + self->role = UBLUEPY_ROLE_PERIPHERAL; + // parse args mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); @@ -345,6 +347,8 @@ STATIC mp_obj_t peripheral_connect(mp_uint_t n_args, const mp_obj_t *pos_args, m ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); mp_obj_t dev_addr = pos_args[1]; + self->role = self->role = UBLUEPY_ROLE_CENTRAL; + static const mp_arg_t allowed_args[] = { { MP_QSTR_addr_type, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UBLUEPY_ADDR_TYPE_PUBLIC } }, }; From 5d9c191a198e3d9945010deb4a550a60f2f98505 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 18:37:41 +0200 Subject: [PATCH 684/809] nrf5/modules/ubluepy: Fixing type in ubluepy_peripheral.c. --- nrf5/modules/ubluepy/ubluepy_peripheral.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf5/modules/ubluepy/ubluepy_peripheral.c index f2a99508f1..a54fe2e673 100644 --- a/nrf5/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf5/modules/ubluepy/ubluepy_peripheral.c @@ -347,7 +347,7 @@ STATIC mp_obj_t peripheral_connect(mp_uint_t n_args, const mp_obj_t *pos_args, m ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); mp_obj_t dev_addr = pos_args[1]; - self->role = self->role = UBLUEPY_ROLE_CENTRAL; + self->role = UBLUEPY_ROLE_CENTRAL; static const mp_arg_t allowed_args[] = { { MP_QSTR_addr_type, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UBLUEPY_ADDR_TYPE_PUBLIC } }, From fd52691f02fa2cc2a9210669237236c929a11366 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 18:57:58 +0200 Subject: [PATCH 685/809] nrf5/drivers/bluetooth: Renaming attr_write and attr_notify to attr_s_write and attr_s_notify to prepare for introduction of attribute write for gatt client. --- nrf5/drivers/bluetooth/ble_drv.c | 4 ++-- nrf5/drivers/bluetooth/ble_drv.h | 4 ++-- nrf5/drivers/bluetooth/ble_uart.c | 8 ++++---- nrf5/modules/ubluepy/ubluepy_characteristic.c | 16 ++++++++-------- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index 0050c91417..23a470d2d2 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -604,7 +604,7 @@ void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, ui } -void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { +void ble_drv_attr_s_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { ble_gatts_value_t gatts_value; memset(&gatts_value, 0, sizeof(gatts_value)); @@ -620,7 +620,7 @@ void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uin } } -void ble_drv_attr_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { +void ble_drv_attr_s_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { uint16_t hvx_len = len; ble_gatts_hvx_params_t hvx_params; diff --git a/nrf5/drivers/bluetooth/ble_drv.h b/nrf5/drivers/bluetooth/ble_drv.h index 07f149695d..bac3ebf474 100644 --- a/nrf5/drivers/bluetooth/ble_drv.h +++ b/nrf5/drivers/bluetooth/ble_drv.h @@ -100,9 +100,9 @@ void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, ui void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, ble_drv_gattc_char_data_callback_t cb); -void ble_drv_attr_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); +void ble_drv_attr_s_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); -void ble_drv_attr_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); +void ble_drv_attr_s_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); void ble_drv_scan_start(void); diff --git a/nrf5/drivers/bluetooth/ble_uart.c b/nrf5/drivers/bluetooth/ble_uart.c index a2f8e1a7d2..61fd18a8ac 100644 --- a/nrf5/drivers/bluetooth/ble_uart.c +++ b/nrf5/drivers/bluetooth/ble_uart.c @@ -118,10 +118,10 @@ void mp_hal_stdout_tx_strn(const char *str, size_t len) { ubluepy_characteristic_obj_t * p_char = &ble_uart_char_tx; - ble_drv_attr_notify(p_char->p_service->p_periph->conn_handle, - p_char->handle, - send_len, - buf); + ble_drv_attr_s_notify(p_char->p_service->p_periph->conn_handle, + p_char->handle, + send_len, + buf); len -= send_len; buf += send_len; diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index 6c005fab34..a28ce20862 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -121,15 +121,15 @@ STATIC mp_obj_t char_write(mp_obj_t self_in, mp_obj_t data) { mp_get_buffer_raise(data, &bufinfo, MP_BUFFER_READ); if (self->props & UBLUEPY_PROP_NOTIFY) { - ble_drv_attr_notify(self->p_service->p_periph->conn_handle, - self->handle, - bufinfo.len, - bufinfo.buf); + ble_drv_attr_s_notify(self->p_service->p_periph->conn_handle, + self->handle, + bufinfo.len, + bufinfo.buf); } else { - ble_drv_attr_write(self->p_service->p_periph->conn_handle, - self->handle, - bufinfo.len, - bufinfo.buf); + ble_drv_attr_s_write(self->p_service->p_periph->conn_handle, + self->handle, + bufinfo.len, + bufinfo.buf); } return mp_const_none; From 1f8ceaa6fbf38350681d7d77c3d64f435d41ba73 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 19:00:22 +0200 Subject: [PATCH 686/809] nrf5/drivers/bluetooth: Adding template function for attr_c_write. --- nrf5/drivers/bluetooth/ble_drv.c | 4 ++++ nrf5/drivers/bluetooth/ble_drv.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index 23a470d2d2..a53754ce69 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -685,6 +685,10 @@ void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, bl } } +void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { + +} + void ble_drv_scan_start(void) { SD_TEST_OR_ENABLE(); diff --git a/nrf5/drivers/bluetooth/ble_drv.h b/nrf5/drivers/bluetooth/ble_drv.h index bac3ebf474..dc3cf168ef 100644 --- a/nrf5/drivers/bluetooth/ble_drv.h +++ b/nrf5/drivers/bluetooth/ble_drv.h @@ -104,6 +104,8 @@ void ble_drv_attr_s_write(uint16_t conn_handle, uint16_t handle, uint16_t len, u void ble_drv_attr_s_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); +void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); + void ble_drv_scan_start(void); void ble_drv_scan_stop(void); From ceb26020057ac81bb84e39aa9865004c37b0ca2a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 19:01:53 +0200 Subject: [PATCH 687/809] nrf5/modules/ubluepy: Updating characteristic object write function to be role aware. Either peripheral or central (gatts or gattc). Adding dummy call to attr_c_write if central is compiled in. Still in progress to be implemented. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 33 ++++++++++++------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index a28ce20862..2a33bee8f7 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -120,18 +120,29 @@ STATIC mp_obj_t char_write(mp_obj_t self_in, mp_obj_t data) { mp_buffer_info_t bufinfo; mp_get_buffer_raise(data, &bufinfo, MP_BUFFER_READ); - if (self->props & UBLUEPY_PROP_NOTIFY) { - ble_drv_attr_s_notify(self->p_service->p_periph->conn_handle, - self->handle, - bufinfo.len, - bufinfo.buf); - } else { - ble_drv_attr_s_write(self->p_service->p_periph->conn_handle, - self->handle, - bufinfo.len, - bufinfo.buf); - } + // figure out mode of the Peripheral + ubluepy_role_type_t role = self->p_service->p_periph->role; + if (role == UBLUEPY_ROLE_PERIPHERAL) { + if (self->props & UBLUEPY_PROP_NOTIFY) { + ble_drv_attr_s_notify(self->p_service->p_periph->conn_handle, + self->handle, + bufinfo.len, + bufinfo.buf); + } else { + ble_drv_attr_s_write(self->p_service->p_periph->conn_handle, + self->handle, + bufinfo.len, + bufinfo.buf); + } + } else { +#if MICROPY_PY_UBLUEPY_CENTRAL + ble_drv_attr_c_write(self->p_service->p_periph->conn_handle, + self->handle, + 0, + NULL); +#endif + } return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_characteristic_write_obj, char_write); From 8f423c26d04db1285e1f7c2ff395ccf62fe2e3b4 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 19:04:49 +0200 Subject: [PATCH 688/809] nrf5/modules/ubluepy: Pass on buffer to write in characteristic write central mode. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index 2a33bee8f7..18b58809f3 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -139,8 +139,8 @@ STATIC mp_obj_t char_write(mp_obj_t self_in, mp_obj_t data) { #if MICROPY_PY_UBLUEPY_CENTRAL ble_drv_attr_c_write(self->p_service->p_periph->conn_handle, self->handle, - 0, - NULL); + bufinfo.len, + bufinfo.buf); #endif } return mp_const_none; From d96e2a3e08df98f26e967e90d02d632ab1105616 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 19:52:58 +0200 Subject: [PATCH 689/809] nrf5/drivers/bluetooth: Add implementation of client attribute write without response. --- nrf5/drivers/bluetooth/ble_drv.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index a53754ce69..1c5d31bf68 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -687,6 +687,21 @@ void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, bl void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { + ble_gattc_write_params_t write_params; + + write_params.write_op = BLE_GATT_OP_WRITE_CMD; + write_params.flags = BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL; + write_params.handle = handle; + write_params.offset = 0; + write_params.len = len; + write_params.p_value = p_data; + + uint32_t err_code = sd_ble_gattc_write(conn_handle, &write_params); + + if (err_code != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, + "Can not write attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); + } } void ble_drv_scan_start(void) { From 63805bac9cdcc13d62cf683d164542f1a882fa52 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 14 May 2017 19:57:20 +0200 Subject: [PATCH 690/809] nrf5/modules/ubluepy: Correcting alignment of enum values in modubluepy.h. --- nrf5/modules/ubluepy/modubluepy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index c7778d3c3d..17922b0a3e 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -103,7 +103,7 @@ typedef enum { typedef enum { UBLUEPY_ROLE_PERIPHERAL, - UBLUEPY_ROLE_CENTRAL + UBLUEPY_ROLE_CENTRAL } ubluepy_role_type_t; typedef struct _ubluepy_uuid_obj_t { From 9b76983af9625d15e4914bc0972fbb96b46ede58 Mon Sep 17 00:00:00 2001 From: glennrub Date: Sun, 14 May 2017 23:02:10 +0200 Subject: [PATCH 691/809] Powerup (#26) * nrf5/examples: Adding python example template for PowerUp 3.0 Bluetooth LE controlled Paper Airplane. * nrf5: Enable bluetooth le central while developing powerup 3.0 example. * nrf5/examples: Backing up powerup 3.0 progress. * nrf5/examples: Adding working example on how to control PowerUp 3.0 paper airplane using bluetooth le. * nrf5/bluetooth: Disable central role. --- nrf5/examples/powerup.py | 216 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 216 insertions(+) create mode 100644 nrf5/examples/powerup.py diff --git a/nrf5/examples/powerup.py b/nrf5/examples/powerup.py new file mode 100644 index 0000000000..5749800dd0 --- /dev/null +++ b/nrf5/examples/powerup.py @@ -0,0 +1,216 @@ +# This file is part of the Micro Python project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2017 Glenn Ruben Bakke +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE + +# MicroPython controller for PowerUp 3.0 paper airplane +# https://www.poweruptoys.com/products/powerup-v3 +# +# Examples is written for nrf52832, pca10040 using s132 bluetooth stack. +# +# Joystick shield pin mapping: +# - analog stick x-direction - ADC0 - P0.02/"A02" +# - buttons P0.13 - P0.16 / "A13", "A14", "A15", "A16" +# +# Example usage: +# +# from powerup import PowerUp3 +# p = PowerUp3() + +import time +from machine import ADC +from machine import Pin +from ubluepy import Peripheral, Scanner, constants + +def bytes_to_str(bytes): + string = "" + for b in bytes: + string += chr(b) + return string + +def get_device_names(scan_entries): + dev_names = [] + for e in scan_entries: + scan = e.getScanData() + if scan: + for s in scan: + if s[0] == constants.ad_types.AD_TYPE_COMPLETE_LOCAL_NAME: + dev_names.append((e, bytes_to_str(s[2]))) + return dev_names + +def find_device_by_name(name): + s = Scanner() + scan_res = s.scan(500) + + device_names = get_device_names(scan_res) + # print(device_names) + for dev in device_names: + if name == dev[1]: + return dev[0] + +class PowerUp3: + def __init__(self): + self.x_adc = ADC(1) + + self.button_speed_up = Pin("A13", mode=Pin.IN, pull=Pin.PULL_UP) + self.button_speed_down = Pin("A15", mode=Pin.IN, pull=Pin.PULL_UP) + self.button_speed_full = Pin("A14", mode=Pin.IN, pull=Pin.PULL_UP) + self.button_speed_off = Pin("A16", mode=Pin.IN, pull=Pin.PULL_UP) + + self.x_mid = 0 + + self.calibrate() + self.connect() + self.loop() + + def read_stick_x(self): + return self.x_adc.value() + + def button_speed_up(self): + return bool(self.button_speed_up.value()) + + def button_speed_down(self): + return bool(self.button_speed_down.value()) + + def button_speed_full(self): + return bool(self.button_speed_full.value()) + + def button_speed_off(self): + return bool(self.button_speed_off.value()) + + def calibrate(self): + self.x_mid = self.read_stick_x() + + def __str__(self): + return "calibration x: %i, y: %i" % (self.x_mid) + + def map_chars(self): + s = self.p.getServices() + + service_batt = s[3] + service_control = s[4] + + self.char_batt_lvl = service_batt.getCharacteristics()[0] + self.char_control_speed = service_control.getCharacteristics()[0] + self.char_control_angle = service_control.getCharacteristics()[2] + + def battery_level(self): + return int(self.char_batt_lvl.read()[0]) + + def speed(self, new_speed=None): + if new_speed == None: + return int(self.char_control_speed.read()[0]) + else: + self.char_control_speed.write(bytearray([new_speed])) + + def angle(self, new_angle=None): + if new_angle == None: + return int(self.char_control_angle.read()[0]) + else: + self.char_control_angle.write(bytearray([new_angle])) + + def connect(self): + dev = None + + # connect to the airplane + while not dev: + dev = find_device_by_name("TailorToys PowerUp") + if dev: + # print(dev.addr()) + self.p = Peripheral() + self.p.connect(dev.addr()) + + # locate interesting characteristics + self.map_chars() + + def rudder_center(self): + if self.old_angle != 0: + self.old_angle = 0 + self.angle(0) + + def rudder_left(self, angle): + steps = (angle // self.interval_size_left) + new_angle = 7 - steps + + if self.old_angle != new_angle: + self.angle(new_angle) + self.old_angle = new_angle + + def rudder_right(self, angle): + steps = (angle // self.interval_size_right) + new_angle = -steps + + if self.old_angle != new_angle: + self.angle(new_angle) + self.old_angle = new_angle + + def throttle(self, speed): + if (speed > 100): + speed = 100 + elif (speed < 0): + speed = 0 + + if self.old_speed != speed: + self.speed(speed) + self.old_speed = speed + + def loop(self): + adc_threshold = 10 + right_threshold = self.x_mid + adc_threshold + left_threshold = self.x_mid - adc_threshold + + self.interval_size_left = self.x_mid // 7 + self.interval_size_right = (255 - self.x_mid) // 7 + + self.old_angle = 0 + self.old_speed = 0 + + while True: + + time.sleep_ms(100) + + # read out new angle + new_angle = self.read_stick_x() + if (new_angle < 256): + if (new_angle > right_threshold): + self.rudder_right(new_angle - self.x_mid) + elif (new_angle < left_threshold): + self.rudder_left(new_angle) + else: + self.rudder_center() + + # read out new speed + new_speed = self.old_speed + + # TODO: bool return not working correctly, so test negated for now. + if not self.button_speed_up(): + new_speed += 25 + elif not self.button_speed_down(): + new_speed -= 25 + elif not self.button_speed_full(): + new_speed = 100 + elif not self.button_speed_off(): + new_speed = 0 + else: + pass + + self.throttle(new_speed) From e6b49af27eae13c3152f8584fcaf63a00ce0480b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 15 May 2017 21:20:52 +0200 Subject: [PATCH 692/809] nrf5/examples: Fixing overlapping function names and variable names inside the object. Also removing some print statements. Tuning max angle from -7/7 to -25/25. --- nrf5/examples/powerup.py | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/nrf5/examples/powerup.py b/nrf5/examples/powerup.py index 5749800dd0..ba8fe0cd0e 100644 --- a/nrf5/examples/powerup.py +++ b/nrf5/examples/powerup.py @@ -62,7 +62,6 @@ def find_device_by_name(name): scan_res = s.scan(500) device_names = get_device_names(scan_res) - # print(device_names) for dev in device_names: if name == dev[1]: return dev[0] @@ -71,10 +70,10 @@ class PowerUp3: def __init__(self): self.x_adc = ADC(1) - self.button_speed_up = Pin("A13", mode=Pin.IN, pull=Pin.PULL_UP) - self.button_speed_down = Pin("A15", mode=Pin.IN, pull=Pin.PULL_UP) - self.button_speed_full = Pin("A14", mode=Pin.IN, pull=Pin.PULL_UP) - self.button_speed_off = Pin("A16", mode=Pin.IN, pull=Pin.PULL_UP) + self.btn_speed_up = Pin("A13", mode=Pin.IN, pull=Pin.PULL_UP) + self.btn_speed_down = Pin("A15", mode=Pin.IN, pull=Pin.PULL_UP) + self.btn_speed_full = Pin("A14", mode=Pin.IN, pull=Pin.PULL_UP) + self.btn_speed_off = Pin("A16", mode=Pin.IN, pull=Pin.PULL_UP) self.x_mid = 0 @@ -86,16 +85,16 @@ class PowerUp3: return self.x_adc.value() def button_speed_up(self): - return bool(self.button_speed_up.value()) + return not bool(self.btn_speed_up.value()) def button_speed_down(self): - return bool(self.button_speed_down.value()) + return not bool(self.btn_speed_down.value()) def button_speed_full(self): - return bool(self.button_speed_full.value()) + return not bool(self.btn_speed_full.value()) def button_speed_off(self): - return bool(self.button_speed_off.value()) + return not bool(self.btn_speed_off.value()) def calibrate(self): self.x_mid = self.read_stick_x() @@ -135,7 +134,6 @@ class PowerUp3: while not dev: dev = find_device_by_name("TailorToys PowerUp") if dev: - # print(dev.addr()) self.p = Peripheral() self.p.connect(dev.addr()) @@ -149,7 +147,7 @@ class PowerUp3: def rudder_left(self, angle): steps = (angle // self.interval_size_left) - new_angle = 7 - steps + new_angle = 25 - steps if self.old_angle != new_angle: self.angle(new_angle) @@ -178,8 +176,8 @@ class PowerUp3: right_threshold = self.x_mid + adc_threshold left_threshold = self.x_mid - adc_threshold - self.interval_size_left = self.x_mid // 7 - self.interval_size_right = (255 - self.x_mid) // 7 + self.interval_size_left = self.x_mid // 25 + self.interval_size_right = (255 - self.x_mid) // 25 self.old_angle = 0 self.old_speed = 0 @@ -201,14 +199,13 @@ class PowerUp3: # read out new speed new_speed = self.old_speed - # TODO: bool return not working correctly, so test negated for now. - if not self.button_speed_up(): + if self.button_speed_up(): new_speed += 25 - elif not self.button_speed_down(): + elif self.button_speed_down(): new_speed -= 25 - elif not self.button_speed_full(): + elif self.button_speed_full(): new_speed = 100 - elif not self.button_speed_off(): + elif self.button_speed_off(): new_speed = 0 else: pass From 36d9c0cb831d58a87cbd581770c11130466e28b7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 15 May 2017 23:00:10 +0200 Subject: [PATCH 693/809] nrf5/drivers/bluetooth: As callback functions are in most usecases are set to NULL upon last event to get public API function out of blocking mode, these function pointers has to be set as volatile, as they are updated to NULL in interrupt context, but read in blocking main-thread. --- nrf5/drivers/bluetooth/ble_drv.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index 1c5d31bf68..43dc5c87e3 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -78,11 +78,11 @@ static mp_obj_t mp_gatts_observer; static volatile bool m_primary_service_found; static volatile bool m_characteristic_found; -static ble_drv_adv_evt_callback_t adv_event_handler; -static ble_drv_gattc_evt_callback_t gattc_event_handler; -static ble_drv_disc_add_service_callback_t disc_add_service_handler; -static ble_drv_disc_add_char_callback_t disc_add_char_handler; -static ble_drv_gattc_char_data_callback_t gattc_char_data_handle; +static volatile ble_drv_adv_evt_callback_t adv_event_handler; +static volatile ble_drv_gattc_evt_callback_t gattc_event_handler; +static volatile ble_drv_disc_add_service_callback_t disc_add_service_handler; +static volatile ble_drv_disc_add_char_callback_t disc_add_char_handler; +static volatile ble_drv_gattc_char_data_callback_t gattc_char_data_handle; static mp_obj_t mp_adv_observer; static mp_obj_t mp_gattc_observer; From 02e215dc5930eecafd9d634773e6719486913531 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 15 May 2017 22:55:08 +0200 Subject: [PATCH 694/809] nrf5/modules/ubluepy: Making peripheral conn_handle volatile. Upon connection event, the variable is accessed in thread mode. However, the main-loop is blocking on conn_handle != 0xFFFF. If this is not volatile, optimized code will not exit the loop. --- nrf5/modules/ubluepy/modubluepy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf5/modules/ubluepy/modubluepy.h index 17922b0a3e..e8edf27dc0 100644 --- a/nrf5/modules/ubluepy/modubluepy.h +++ b/nrf5/modules/ubluepy/modubluepy.h @@ -116,7 +116,7 @@ typedef struct _ubluepy_uuid_obj_t { typedef struct _ubluepy_peripheral_obj_t { mp_obj_base_t base; ubluepy_role_type_t role; - uint16_t conn_handle; + volatile uint16_t conn_handle; mp_obj_t delegate; mp_obj_t notif_handler; mp_obj_t conn_handler; From 226d872d11b0612b48a2ab1ea62aea1e9a01aaea Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 00:47:44 +0200 Subject: [PATCH 695/809] nrf5/drivers/pwm: Expose pwm_init() as public function. --- nrf5/drivers/pwm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/nrf5/drivers/pwm.h b/nrf5/drivers/pwm.h index 38ca471d17..fb8167448f 100644 --- a/nrf5/drivers/pwm.h +++ b/nrf5/drivers/pwm.h @@ -1,6 +1,7 @@ #ifndef __MICROPY_INCLUDED_LIB_PWM_H__ #define __MICROPY_INCLUDED_LIB_PWM_H__ +void pwm_init(void); void pwm_start(void); void pwm_stop(void); @@ -9,4 +10,4 @@ int32_t pwm_get_period_us(void); void pwm_set_duty_cycle(int32_t pin, int32_t value); void pwm_release(int32_t pin); -#endif // __MICROPY_INCLUDED_LIB_PWM_H__ \ No newline at end of file +#endif // __MICROPY_INCLUDED_LIB_PWM_H__ From 3bc8309dababd3711a3bd341ad52befbe694acc6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 00:50:17 +0200 Subject: [PATCH 696/809] nrf5/drivers/pwm: Renaming pwm.c/.h to softpwm.c/.h --- nrf5/drivers/{pwm.c => softpwm.c} | 0 nrf5/drivers/{pwm.h => softpwm.h} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename nrf5/drivers/{pwm.c => softpwm.c} (100%) rename nrf5/drivers/{pwm.h => softpwm.h} (100%) diff --git a/nrf5/drivers/pwm.c b/nrf5/drivers/softpwm.c similarity index 100% rename from nrf5/drivers/pwm.c rename to nrf5/drivers/softpwm.c diff --git a/nrf5/drivers/pwm.h b/nrf5/drivers/softpwm.h similarity index 100% rename from nrf5/drivers/pwm.h rename to nrf5/drivers/softpwm.h From cab515a02245d62dd1def114027635b4ff049a69 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 00:51:52 +0200 Subject: [PATCH 697/809] nrf5/drivers/ticker: Adding ticker.c/.h from microbit port. --- nrf5/drivers/ticker.c | 171 ++++++++++++++++++++++++++++++++++++++++++ nrf5/drivers/ticker.h | 30 ++++++++ 2 files changed, 201 insertions(+) create mode 100644 nrf5/drivers/ticker.c create mode 100644 nrf5/drivers/ticker.h diff --git a/nrf5/drivers/ticker.c b/nrf5/drivers/ticker.c new file mode 100644 index 0000000000..efaca823c7 --- /dev/null +++ b/nrf5/drivers/ticker.c @@ -0,0 +1,171 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Mark Shannon + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mphal.h" + +#include "ticker.h" + +#define FastTicker NRF_TIMER0 +#define FastTicker_IRQn TIMER0_IRQn +#define FastTicker_IRQHandler TIMER0_IRQHandler + +#define SlowTicker_IRQn SWI3_IRQn +#define SlowTicker_IRQHandler SWI3_IRQHandler + +#define LowPriority_IRQn SWI4_IRQn +#define LowPriority_IRQHandler SWI4_IRQHandler + +// Ticker callback function called every MACRO_TICK +static callback_ptr slow_ticker; + +void ticker_init(callback_ptr slow_ticker_callback) { + slow_ticker = slow_ticker_callback; + NRF_TIMER_Type *ticker = FastTicker; +#if NRF51 + ticker->POWER = 1; +#endif + __NOP(); + ticker_stop(); + ticker->TASKS_CLEAR = 1; + ticker->CC[3] = MICROSECONDS_PER_MACRO_TICK; + ticker->MODE = TIMER_MODE_MODE_Timer; + ticker->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos; + ticker->PRESCALER = 4; // 1 tick == 1 microsecond + ticker->INTENSET = TIMER_INTENSET_COMPARE3_Msk; + ticker->SHORTS = 0; + NVIC_SetPriority(FastTicker_IRQn, 1); + NVIC_SetPriority(SlowTicker_IRQn, 2); + NVIC_SetPriority(LowPriority_IRQn, 3); + NVIC_EnableIRQ(SlowTicker_IRQn); + NVIC_EnableIRQ(LowPriority_IRQn); +} + +/* Start and stop timer 0 including workarounds for Anomaly 73 for Timer +* http://www.nordicsemi.com/eng/content/download/29490/494569/file/nRF51822-PAN%20v3.0.pdf +*/ +void ticker_start(void) { + NVIC_EnableIRQ(FastTicker_IRQn); + *(uint32_t *)0x40008C0C = 1; //for Timer 0 + FastTicker->TASKS_START = 1; +} + +void ticker_stop(void) { + NVIC_DisableIRQ(FastTicker_IRQn); + FastTicker->TASKS_STOP = 1; + *(uint32_t *)0x40008C0C = 0; //for Timer 0 +} + +int32_t noop(void) { + return -1; +} + +uint32_t ticks; + +static ticker_callback_ptr callbacks[3] = { noop, noop, noop }; + +void FastTicker_IRQHandler(void) { + NRF_TIMER_Type *ticker = FastTicker; + ticker_callback_ptr *call = callbacks; + if (ticker->EVENTS_COMPARE[0]) { + ticker->EVENTS_COMPARE[0] = 0; + ticker->CC[0] += call[0]()*MICROSECONDS_PER_TICK; + } + if (ticker->EVENTS_COMPARE[1]) { + ticker->EVENTS_COMPARE[1] = 0; + ticker->CC[1] += call[1]()*MICROSECONDS_PER_TICK; + } + if (ticker->EVENTS_COMPARE[2]) { + ticker->EVENTS_COMPARE[2] = 0; + ticker->CC[2] += call[2]()*MICROSECONDS_PER_TICK; + } + if (ticker->EVENTS_COMPARE[3]) { + ticker->EVENTS_COMPARE[3] = 0; + ticker->CC[3] += MICROSECONDS_PER_MACRO_TICK; + ticks += MILLISECONDS_PER_MACRO_TICK; + NVIC_SetPendingIRQ(SlowTicker_IRQn); + } +} + + +static const uint32_t masks[3] = { + TIMER_INTENCLR_COMPARE0_Msk, + TIMER_INTENCLR_COMPARE1_Msk, + TIMER_INTENCLR_COMPARE2_Msk, +}; + +int set_ticker_callback(uint32_t index, ticker_callback_ptr func, int32_t initial_delay_us) { + if (index > 3) + return -1; + NRF_TIMER_Type *ticker = FastTicker; + callbacks[index] = noop; + ticker->INTENCLR = masks[index]; + ticker->TASKS_CAPTURE[index] = 1; + uint32_t t = FastTicker->CC[index]; + // Need to make sure that set tick is aligned to lastest tick + // Use CC[3] as a reference, as that is always up-to-date. + int32_t cc3 = FastTicker->CC[3]; + int32_t delta = t+initial_delay_us-cc3; + delta = (delta/MICROSECONDS_PER_TICK+1)*MICROSECONDS_PER_TICK; + callbacks[index] = func; + ticker->INTENSET = masks[index]; + FastTicker->CC[index] = cc3 + delta; + return 0; +} + +int clear_ticker_callback(uint32_t index) { + if (index > 3) + return -1; + FastTicker->INTENCLR = masks[index]; + callbacks[index] = noop; + return 0; +} + +void SlowTicker_IRQHandler(void) +{ + slow_ticker(); +} + +#define LOW_PRIORITY_CALLBACK_LIMIT 4 +callback_ptr low_priority_callbacks[LOW_PRIORITY_CALLBACK_LIMIT] = { NULL, NULL, NULL, NULL }; + +void LowPriority_IRQHandler(void) +{ + for (int id = 0; id < LOW_PRIORITY_CALLBACK_LIMIT; id++) { + callback_ptr callback = low_priority_callbacks[id]; + if (callback != NULL) { + low_priority_callbacks[id] = NULL; + callback(); + } + } +} + +int set_low_priority_callback(callback_ptr callback, int id) { + if (low_priority_callbacks[id] != NULL) + return -1; + low_priority_callbacks[id] = callback; + NVIC_SetPendingIRQ(LowPriority_IRQn); + return 0; +} diff --git a/nrf5/drivers/ticker.h b/nrf5/drivers/ticker.h new file mode 100644 index 0000000000..6ac87cd503 --- /dev/null +++ b/nrf5/drivers/ticker.h @@ -0,0 +1,30 @@ +#ifndef __MICROPY_INCLUDED_LIB_TICKER_H__ +#define __MICROPY_INCLUDED_LIB_TICKER_H__ + +/************************************* + * 62.5kHz (16µs cycle time) ticker. + ************************************/ + +#include "nrf.h" + +typedef void (*callback_ptr)(void); +typedef int32_t (*ticker_callback_ptr)(void); + +void ticker_init(callback_ptr slow_ticker_callback); +void ticker_start(void); +void ticker_stop(void); + +int clear_ticker_callback(uint32_t index); +int set_ticker_callback(uint32_t index, ticker_callback_ptr func, int32_t initial_delay_us); + +int set_low_priority_callback(callback_ptr callback, int id); + +#define CYCLES_PER_MICROSECONDS 16 + +#define MICROSECONDS_PER_TICK 16 +#define CYCLES_PER_TICK (CYCLES_PER_MICROSECONDS*MICROSECONDS_PER_TICK) +// This must be an integer multiple of MICROSECONDS_PER_TICK +#define MICROSECONDS_PER_MACRO_TICK 6000 +#define MILLISECONDS_PER_MACRO_TICK 6 + +#endif // __MICROPY_INCLUDED_LIB_TICKER_H__ \ No newline at end of file From a0ad7ce0b4468cf2d43d4d6c930e7b360ec03257 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 00:52:35 +0200 Subject: [PATCH 698/809] nrf5/drivers/softpwm: Enable use of ticker in softpwm driver. --- nrf5/drivers/softpwm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/softpwm.c b/nrf5/drivers/softpwm.c index 8d6ab0fa4f..5623c279a5 100644 --- a/nrf5/drivers/softpwm.c +++ b/nrf5/drivers/softpwm.c @@ -35,6 +35,8 @@ #include "hal_gpio.h" #include "pin.h" +#include "ticker.h" + #define CYCLES_PER_MICROSECONDS 16 #define MICROSECONDS_PER_TICK 16 @@ -171,11 +173,11 @@ int32_t pwm_callback(void) { } void pwm_start(void) { - // set_ticker_callback(PWM_TICKER_INDEX, pwm_callback, 120); + set_ticker_callback(PWM_TICKER_INDEX, pwm_callback, 120); } void pwm_stop(void) { - // clear_ticker_callback(PWM_TICKER_INDEX); + clear_ticker_callback(PWM_TICKER_INDEX); } static void pwm_set_period_ticks(int32_t ticks) { From d4122411434a55006a87ea59d89d2bf44c41e874 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 00:57:10 +0200 Subject: [PATCH 699/809] nrf5/modules/music: Update modmusic to use updated includes. Add extern ticks. Add function which implements initialization of pwm and ticker, register ticker callback, and start the pwm and ticker. This corresponds to microbit port main.cpp init. --- nrf5/modules/music/modmusic.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index 88311f2cd2..6916ba6baa 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -35,7 +35,8 @@ #include "py/objstr.h" #include "modmusic.h" #include "musictunes.h" -#include "drivers/pwm.h" +#include "softpwm.h" +#include "ticker.h" #include "pin.h" #include "genhdr/pins.h" @@ -71,11 +72,17 @@ enum { #define music_data MP_STATE_PORT(music_data) -// extern uint32_t ticks; -static uint32_t ticks = 0; // TODO +extern uint32_t ticks; STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_t *pin); +void microbit_music_init0(void) { + pwm_init(); + ticker_init(microbit_music_tick); + ticker_start(); + pwm_start(); +} + void microbit_music_tick(void) { if (music_data == NULL) { // music module not yet imported From 6330fd4f319bbd48e3abbb1863784a5c5e30d80a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 00:57:56 +0200 Subject: [PATCH 700/809] nrf5/modules/music: Expose public init function for music module. --- nrf5/modules/music/modmusic.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/modules/music/modmusic.h b/nrf5/modules/music/modmusic.h index a78588bb71..8e64f02198 100644 --- a/nrf5/modules/music/modmusic.h +++ b/nrf5/modules/music/modmusic.h @@ -1,6 +1,7 @@ #ifndef __MICROPY_INCLUDED_MICROBIT_MUSIC_H__ #define __MICROPY_INCLUDED_MICROBIT_MUSIC_H__ +void microbit_music_init0(void); void microbit_music_tick(void); #endif // __MICROPY_INCLUDED_MICROBIT_MUSIC_H__ From 4c5c83567e7bb85ffcb8a000f4b231a0bc873c3e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 00:59:35 +0200 Subject: [PATCH 701/809] nrf5: Call microbit_music_init0() if enabled in main.c. --- nrf5/main.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nrf5/main.c b/nrf5/main.c index af384de492..3965551a36 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -122,6 +122,9 @@ int main(int argc, char **argv) { timer_init0(); #endif +#if MICROPY_PY_MUSIC + microbit_music_init0(); +#endif /* extint_init0(); timer_init0(); From 52be9eec9d2e6c797e459e32e122dd544598d0ce Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 01:04:17 +0200 Subject: [PATCH 702/809] nrf5: Adding include of modmusic.h in main.c. --- nrf5/main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/main.c b/nrf5/main.c index 3965551a36..aa799c8f63 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -41,6 +41,7 @@ #include "readline.h" #include "gccollect.h" #include "modmachine.h" +#include "modmusic.h" #include "led.h" #include "uart.h" #include "nrf.h" From c6b36ad4ca110d4d08d1a82aa1716407079c16ac Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 01:05:41 +0200 Subject: [PATCH 703/809] nrf5: Update Makefile to include ticker.c and renamed softpwm. Updating also include paths to include modules/music and drivers/. --- nrf5/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 493beacae8..5086ae7774 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -54,9 +54,11 @@ INC += -I./hal INC += -I./hal/$(MCU_VARIANT) INC += -I./modules/machine INC += -I./modules/ubluepy +INC += -I./modules/music INC += -I./modules/ble INC += -I../lib/mp-readline INC += -I./drivers/bluetooth +INC += -I./drivers NRF_DEFINES += -D$(MCU_VARIANT_UPPER) NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET @@ -128,7 +130,8 @@ SRC_C += \ gccollect.c \ pin_named_pins.c \ fatfs_port.c \ - drivers/pwm.c \ + drivers/softpwm.c \ + drivers/ticker.c \ drivers/bluetooth/ble_drv.c \ drivers/bluetooth/ble_uart.c \ From 2584684e06523c73f6aba3cd7b9dbe4e2030161c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 19:32:33 +0200 Subject: [PATCH 704/809] nrf5: Add modmusic QSTR definition of notes to qstrdefsport.h. --- nrf5/qstrdefsport.h | 112 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/nrf5/qstrdefsport.h b/nrf5/qstrdefsport.h index 5138fbfb5d..c945ca779d 100644 --- a/nrf5/qstrdefsport.h +++ b/nrf5/qstrdefsport.h @@ -25,3 +25,115 @@ */ // qstrs specific to this port +Q(a) +Q(a#) +Q(a#:1) +Q(a#:3) +Q(a2) +Q(a4) +Q(a4:1) +Q(a4:3) +Q(a:1) +Q(a:2) +Q(a:4) +Q(a:5) +Q(b) +Q(b2:1) +Q(b3) +Q(b4) +Q(b4:1) +Q(b4:2) +Q(b5) +Q(b5:1) +Q(b:1) +Q(b:2) +Q(c) +Q(c#) +Q(c#5) +Q(c#5:1) +Q(c#5:2) +Q(c#:1) +Q(c#:8) +Q(c2:2) +Q(c3) +Q(c3:3) +Q(c3:4) +Q(c4) +Q(c4:1) +Q(c4:3) +Q(c4:4) +Q(c5) +Q(c5:1) +Q(c5:2) +Q(c5:3) +Q(c5:4) +Q(c:1) +Q(c:2) +Q(c:3) +Q(c:4) +Q(c:8) +Q(d) +Q(d#) +Q(d#5:2) +Q(d#:2) +Q(d#:3) +Q(d3) +Q(d4) +Q(d4:1) +Q(d5) +Q(d5:1) +Q(d5:2) +Q(d:1) +Q(d:2) +Q(d:3) +Q(d:4) +Q(d:5) +Q(d:6) +Q(d:8) +Q(e) +Q(e3:3) +Q(e4) +Q(e4:1) +Q(e5) +Q(e6:3) +Q(e:1) +Q(e:2) +Q(e:3) +Q(e:4) +Q(e:5) +Q(e:6) +Q(e:8) +Q(eb:8) +Q(f) +Q(f#) +Q(f#5) +Q(f#5:2) +Q(f#:1) +Q(f#:2) +Q(f#:8) +Q(f2) +Q(f:1) +Q(f:2) +Q(f:3) +Q(f:4) +Q(f:8) +Q(g) +Q(g#) +Q(g#:1) +Q(g#:3) +Q(g3:1) +Q(g4) +Q(g4:1) +Q(g4:2) +Q(g5) +Q(g5:1) +Q(g:1) +Q(g:2) +Q(g:3) +Q(g:8) +Q(r) +Q(r4:2) +Q(r:1) +Q(r:2) +Q(r:3) + From 234c9f3688f0c875d30cee5c521fbff2e4edae27 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 19:49:41 +0200 Subject: [PATCH 705/809] nrf5/drivers/softpwm: Renaming pwm_init to softpwm_init to not collide on symbol name with pwm_init in nrf52 machine PWM object. --- nrf5/drivers/softpwm.c | 2 +- nrf5/drivers/softpwm.h | 2 +- nrf5/modules/music/modmusic.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/drivers/softpwm.c b/nrf5/drivers/softpwm.c index 5623c279a5..41425a6e2e 100644 --- a/nrf5/drivers/softpwm.c +++ b/nrf5/drivers/softpwm.c @@ -79,7 +79,7 @@ static const pwm_events OFF_EVENTS = { #define active_events MP_STATE_PORT(pwm_active_events) #define pending_events MP_STATE_PORT(pwm_pending_events) -void pwm_init(void) { +void softpwm_init(void) { active_events = &OFF_EVENTS; pending_events = NULL; } diff --git a/nrf5/drivers/softpwm.h b/nrf5/drivers/softpwm.h index fb8167448f..a73c15cd85 100644 --- a/nrf5/drivers/softpwm.h +++ b/nrf5/drivers/softpwm.h @@ -1,7 +1,7 @@ #ifndef __MICROPY_INCLUDED_LIB_PWM_H__ #define __MICROPY_INCLUDED_LIB_PWM_H__ -void pwm_init(void); +void softpwm_init(void); void pwm_start(void); void pwm_stop(void); diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index 6916ba6baa..7e8ff30dbd 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -77,7 +77,7 @@ extern uint32_t ticks; STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_t *pin); void microbit_music_init0(void) { - pwm_init(); + softpwm_init(); ticker_init(microbit_music_tick); ticker_start(); pwm_start(); From 086d79fbad0e0f9934090c5cb6b8e0ec052feb77 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 19:50:39 +0200 Subject: [PATCH 706/809] nrf5/drivers/ticker: Add compile config guard in ticker.c to only include the driver if SOFT_PWM is configured in by board. --- nrf5/drivers/ticker.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/nrf5/drivers/ticker.c b/nrf5/drivers/ticker.c index efaca823c7..10bb506b67 100644 --- a/nrf5/drivers/ticker.c +++ b/nrf5/drivers/ticker.c @@ -26,6 +26,8 @@ #include "py/mphal.h" +#if MICROPY_PY_MACHINE_SOFT_PWM + #include "ticker.h" #define FastTicker NRF_TIMER0 @@ -169,3 +171,5 @@ int set_low_priority_callback(callback_ptr callback, int id) { NVIC_SetPendingIRQ(LowPriority_IRQn); return 0; } + +#endif // MICROPY_PY_MACHINE_SOFT_PWM From 6f72e731377508fa1fc63816be78b1c1004a3ebe Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 19:52:09 +0200 Subject: [PATCH 707/809] nrf5/hal/timer: Quickfix. Disable IRQ handler if SOFT_PWM is configured to be enabled. Ticker driver has in current driver a seperate IRQ handler for this timer instance. --- nrf5/hal/hal_timer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/hal/hal_timer.c b/nrf5/hal/hal_timer.c index 3046f74383..42d4d24c21 100644 --- a/nrf5/hal/hal_timer.c +++ b/nrf5/hal/hal_timer.c @@ -39,9 +39,11 @@ void hal_timer_start(uint8_t id) { void hal_timer_stop(uint8_t id) { } +#if (MICROPY_PY_MACHINE_SOFT_PWM != 1) void TIMER0_IRQHandler(void) { } +#endif void TIMER1_IRQHandler(void) { From 952c14c4bf0c4247bef68544b8646019acff19aa Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 19:54:08 +0200 Subject: [PATCH 708/809] nrf5/modules/machine: Quickfix. Update timer object to not allow instanciation of Timer(0) if SOFT_PWM is enabled by board. --- nrf5/modules/machine/timer.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index d22f808751..a8284cd741 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -97,6 +97,14 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, // get static peripheral object int timer_id = timer_find(args[ARG_NEW_id].u_obj); + +#if MICROPY_PY_MACHINE_SOFT_PWM + if (timer_id == 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Timer(%d) reserved by ticker driver.", timer_id)); + } +#endif + const machine_timer_obj_t *self = &machine_timer_obj[timer_id]; hal_timer_init(self->p_config); From 147d03feff9e3e5e3aed785f49be11b767d7b93c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 17 May 2017 21:22:15 +0200 Subject: [PATCH 709/809] nrf5/boards/microbit: Enable music module by default. However, timer and rtc module has to be disabled. Bluetooth support broken. Optimization needed. --- nrf5/boards/microbit/mpconfigboard.h | 7 ++++--- nrf5/boards/microbit/nrf51_hal_conf.h | 5 +++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index 3c226a5b76..a0e4f0ee36 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -30,10 +30,11 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51" -#define MICROPY_PY_MACHINE_SOFT_PWM (0) +#define MICROPY_PY_MUSIC (1) +#define MICROPY_PY_MACHINE_SOFT_PWM (1) #define MICROPY_PY_MACHINE_HW_SPI (1) -#define MICROPY_PY_MACHINE_TIMER (1) -#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_TIMER (0) +#define MICROPY_PY_MACHINE_RTC (0) #define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) diff --git a/nrf5/boards/microbit/nrf51_hal_conf.h b/nrf5/boards/microbit/nrf51_hal_conf.h index e83e2d346e..65754ff0f1 100644 --- a/nrf5/boards/microbit/nrf51_hal_conf.h +++ b/nrf5/boards/microbit/nrf51_hal_conf.h @@ -4,10 +4,11 @@ #define HAL_UART_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED -#define HAL_TIMER_MODULE_ENABLED +// #define HAL_RTC_MODULE_ENABLED +// #define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED + #endif // NRF51_HAL_CONF_H__ From d1a4b19dc5473e418ed4777f319d3beeb94d95a1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 18 May 2017 00:41:16 +0200 Subject: [PATCH 710/809] nrf5: Facilitate option to configure away the modble if needed. Enabled if MICROPY_PY_BLE config is enabled in bluetooth_conf.h. --- nrf5/mpconfigport.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 08167b5f55..7cd2f08690 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -202,14 +202,21 @@ extern const struct _mp_obj_module_t music_module; #if BLUETOOTH_SD + +#if MICROPY_PY_BLE extern const struct _mp_obj_module_t ble_module; +#define BLE_MODULE { MP_ROM_QSTR(MP_QSTR_ble), MP_ROM_PTR(&ble_module) }, +#else +#define BLE_MODULE +#endif + #define MICROPY_PORT_BUILTIN_MODULES \ { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \ { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) }, \ - { MP_ROM_QSTR(MP_QSTR_ble), MP_ROM_PTR(&ble_module) }, \ { MP_ROM_QSTR(MP_QSTR_utime), MP_ROM_PTR(&mp_module_utime) }, \ { MP_ROM_QSTR(MP_QSTR_time), MP_ROM_PTR(&mp_module_utime) }, \ { MP_ROM_QSTR(MP_QSTR_uos), MP_ROM_PTR(&mp_module_uos) }, \ + BLE_MODULE \ MUSIC_MODULE \ UBLUEPY_MODULE \ @@ -238,8 +245,8 @@ extern const struct _mp_obj_module_t ble_module; // extra constants #define MICROPY_PORT_CONSTANTS \ { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \ - { MP_ROM_QSTR(MP_QSTR_ble), MP_ROM_PTR(&ble_module) }, \ { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) }, \ + BLE_MODULE \ #define MP_STATE_PORT MP_STATE_VM From 981b3e61ddcd58321cabc7f7402c2069c4dc46d1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 18 May 2017 01:12:17 +0200 Subject: [PATCH 711/809] nrf5/hal/irq: Adding IRQ wrappers if Bluetooth Stack is present. --- nrf5/hal/hal_irq.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/nrf5/hal/hal_irq.h b/nrf5/hal/hal_irq.h index f834e33598..de0ebaf6e8 100644 --- a/nrf5/hal/hal_irq.h +++ b/nrf5/hal/hal_irq.h @@ -31,21 +31,49 @@ #include "nrf.h" +#if BLUETOOTH_SD +#include "nrf_sdm.h" +#endif + static inline void hal_irq_clear(uint32_t irq_num) { +#if BLUETOOTH_SD + sd_nvic_ClearPendingIRQ(irq_num); +#else NVIC_ClearPendingIRQ(irq_num); +#endif } static inline void hal_irq_enable(uint32_t irq_num) { hal_irq_clear(irq_num); +#if BLUETOOTH_SD + sd_nvic_EnableIRQ(irq_num); +#else NVIC_EnableIRQ(irq_num); +#endif } static inline void hal_irq_disable(uint32_t irq_num) { +#if BLUETOOTH_SD + sd_nvic_DisableIRQ(irq_num); +#else NVIC_DisableIRQ(irq_num); +#endif } static inline void hal_irq_priority(uint32_t irq_num, uint8_t priority) { +#if BLUETOOTH_SD + sd_nvic_SetPriority(irq_num, priority); +#else NVIC_SetPriority(irq_num, priority); +#endif +} + +static inline void hal_irq_pending(uint32_t irq_num) { +#if BLUETOOTH_SD + sd_nvic_SetPendingIRQ(irq_num); +#else + NVIC_SetPendingIRQ(irq_num); +#endif } #endif // HAL_IRQ_H__ From c921bbd9ac317c9464075b0ef2e4167aa70e31e2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 18 May 2017 01:14:33 +0200 Subject: [PATCH 712/809] nrf5/drivers/ticker: Removing LowPriority callback from nrf51 as there is only one SoftwareIRQ free if bluetooth stack is enabled. Also setting new IRQ priority on SlowTicker to 3 instead of 2, to interleave with bluetooth stack if needed. Updating all NVIC calls to use hal_irq.h defined static inlines instead of direct access. --- nrf5/drivers/ticker.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/nrf5/drivers/ticker.c b/nrf5/drivers/ticker.c index 10bb506b67..e4011d4022 100644 --- a/nrf5/drivers/ticker.c +++ b/nrf5/drivers/ticker.c @@ -29,22 +29,21 @@ #if MICROPY_PY_MACHINE_SOFT_PWM #include "ticker.h" +#include "hal_irq.h" #define FastTicker NRF_TIMER0 #define FastTicker_IRQn TIMER0_IRQn #define FastTicker_IRQHandler TIMER0_IRQHandler -#define SlowTicker_IRQn SWI3_IRQn -#define SlowTicker_IRQHandler SWI3_IRQHandler - -#define LowPriority_IRQn SWI4_IRQn -#define LowPriority_IRQHandler SWI4_IRQHandler +#define SlowTicker_IRQn SWI0_IRQn +#define SlowTicker_IRQHandler SWI0_IRQHandler // Ticker callback function called every MACRO_TICK static callback_ptr slow_ticker; void ticker_init(callback_ptr slow_ticker_callback) { slow_ticker = slow_ticker_callback; + NRF_TIMER_Type *ticker = FastTicker; #if NRF51 ticker->POWER = 1; @@ -58,24 +57,23 @@ void ticker_init(callback_ptr slow_ticker_callback) { ticker->PRESCALER = 4; // 1 tick == 1 microsecond ticker->INTENSET = TIMER_INTENSET_COMPARE3_Msk; ticker->SHORTS = 0; - NVIC_SetPriority(FastTicker_IRQn, 1); - NVIC_SetPriority(SlowTicker_IRQn, 2); - NVIC_SetPriority(LowPriority_IRQn, 3); - NVIC_EnableIRQ(SlowTicker_IRQn); - NVIC_EnableIRQ(LowPriority_IRQn); + + hal_irq_priority(FastTicker_IRQn, 1); + hal_irq_priority(SlowTicker_IRQn, 3); + hal_irq_enable(SlowTicker_IRQn); } /* Start and stop timer 0 including workarounds for Anomaly 73 for Timer * http://www.nordicsemi.com/eng/content/download/29490/494569/file/nRF51822-PAN%20v3.0.pdf */ void ticker_start(void) { - NVIC_EnableIRQ(FastTicker_IRQn); + hal_irq_enable(FastTicker_IRQn); *(uint32_t *)0x40008C0C = 1; //for Timer 0 FastTicker->TASKS_START = 1; } void ticker_stop(void) { - NVIC_DisableIRQ(FastTicker_IRQn); + hal_irq_disable(FastTicker_IRQn); FastTicker->TASKS_STOP = 1; *(uint32_t *)0x40008C0C = 0; //for Timer 0 } @@ -107,7 +105,7 @@ void FastTicker_IRQHandler(void) { ticker->EVENTS_COMPARE[3] = 0; ticker->CC[3] += MICROSECONDS_PER_MACRO_TICK; ticks += MILLISECONDS_PER_MACRO_TICK; - NVIC_SetPendingIRQ(SlowTicker_IRQn); + hal_irq_pending(SlowTicker_IRQn); } } @@ -150,6 +148,8 @@ void SlowTicker_IRQHandler(void) slow_ticker(); } +#if NRF52 + #define LOW_PRIORITY_CALLBACK_LIMIT 4 callback_ptr low_priority_callbacks[LOW_PRIORITY_CALLBACK_LIMIT] = { NULL, NULL, NULL, NULL }; @@ -172,4 +172,6 @@ int set_low_priority_callback(callback_ptr callback, int id) { return 0; } +#endif // NRF52 + #endif // MICROPY_PY_MACHINE_SOFT_PWM From d06c6f4587d446090514d0fe65d4c76369297f15 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 18 May 2017 22:41:06 +0200 Subject: [PATCH 713/809] nrf5: Adding -fstack-usage flag to gcc CFLAGS to be able to trace stack usage on modules. --- nrf5/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/Makefile b/nrf5/Makefile index 5086ae7774..70dea01e33 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -73,6 +73,7 @@ CFLAGS_MCU_m0 = $(CFLAGS_CORTEX_M) --short-enums -mtune=cortex-m0 -mcpu=cortex-m CFLAGS += $(CFLAGS_MCU_$(MCU_SERIES)) CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) $(CFLAGS_MOD) CFLAGS += -fno-strict-aliasing +CFLAGS += -fstack-usage CFLAGS += -Iboards/$(BOARD) CFLAGS += -DNRF5_HAL_H='<$(MCU_VARIANT)_hal.h>' From 1ff44dd5b85f9db2e6361db66009a3315566741d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 18 May 2017 22:43:47 +0200 Subject: [PATCH 714/809] nrf5/boards/microbit: Disable music and softPWM as there are some issues with the ticker. --- nrf5/boards/microbit/mpconfigboard.h | 8 ++++---- nrf5/boards/microbit/nrf51_hal_conf.h | 5 ++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index a0e4f0ee36..b265795569 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -30,11 +30,11 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51" -#define MICROPY_PY_MUSIC (1) -#define MICROPY_PY_MACHINE_SOFT_PWM (1) +#define MICROPY_PY_MUSIC (0) +#define MICROPY_PY_MACHINE_SOFT_PWM (0) #define MICROPY_PY_MACHINE_HW_SPI (1) -#define MICROPY_PY_MACHINE_TIMER (0) -#define MICROPY_PY_MACHINE_RTC (0) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) diff --git a/nrf5/boards/microbit/nrf51_hal_conf.h b/nrf5/boards/microbit/nrf51_hal_conf.h index 65754ff0f1..e83e2d346e 100644 --- a/nrf5/boards/microbit/nrf51_hal_conf.h +++ b/nrf5/boards/microbit/nrf51_hal_conf.h @@ -4,11 +4,10 @@ #define HAL_UART_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED -// #define HAL_RTC_MODULE_ENABLED -// #define HAL_TIMER_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED #define HAL_TWI_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED - #endif // NRF51_HAL_CONF_H__ From 0fa70ec988b4d48b3ef6c64713b12985c00ea54f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 18 May 2017 23:07:34 +0200 Subject: [PATCH 715/809] nrf5/examples: Adding music example. Only working if bluetooth stack is not enabled. --- nrf5/examples/musictest.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 nrf5/examples/musictest.py diff --git a/nrf5/examples/musictest.py b/nrf5/examples/musictest.py new file mode 100644 index 0000000000..d958543ec3 --- /dev/null +++ b/nrf5/examples/musictest.py @@ -0,0 +1,13 @@ +# +# Example usage where "A3" is the Buzzer pin. +# +# from musictest import play +# play("A3") +# + +from machine import Pin +import music + +def play(pin_str): + p = Pin(pin_str, mode=Pin.OUT) + music.play(music.PRELUDE, pin=p) From 1192981d24d87f1991e5a5206519e626a482c374 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 18 May 2017 23:10:15 +0200 Subject: [PATCH 716/809] nrf5/drivers/ticker: Removing unused code. --- nrf5/drivers/ticker.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/nrf5/drivers/ticker.c b/nrf5/drivers/ticker.c index e4011d4022..3e439a96d8 100644 --- a/nrf5/drivers/ticker.c +++ b/nrf5/drivers/ticker.c @@ -148,30 +148,4 @@ void SlowTicker_IRQHandler(void) slow_ticker(); } -#if NRF52 - -#define LOW_PRIORITY_CALLBACK_LIMIT 4 -callback_ptr low_priority_callbacks[LOW_PRIORITY_CALLBACK_LIMIT] = { NULL, NULL, NULL, NULL }; - -void LowPriority_IRQHandler(void) -{ - for (int id = 0; id < LOW_PRIORITY_CALLBACK_LIMIT; id++) { - callback_ptr callback = low_priority_callbacks[id]; - if (callback != NULL) { - low_priority_callbacks[id] = NULL; - callback(); - } - } -} - -int set_low_priority_callback(callback_ptr callback, int id) { - if (low_priority_callbacks[id] != NULL) - return -1; - low_priority_callbacks[id] = callback; - NVIC_SetPendingIRQ(LowPriority_IRQn); - return 0; -} - -#endif // NRF52 - #endif // MICROPY_PY_MACHINE_SOFT_PWM From 003f43b5c93b47b63a1c19cd8d3945a138db9ed1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 18 May 2017 23:19:46 +0200 Subject: [PATCH 717/809] nrf5/hal/irq: Adding include of nrf_nvic.h if s132 bluetooth stack is used to resolve IRQ function wrappers on newer bluetooth stacks. --- nrf5/hal/hal_irq.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/nrf5/hal/hal_irq.h b/nrf5/hal/hal_irq.h index de0ebaf6e8..266758beec 100644 --- a/nrf5/hal/hal_irq.h +++ b/nrf5/hal/hal_irq.h @@ -32,7 +32,11 @@ #include "nrf.h" #if BLUETOOTH_SD -#include "nrf_sdm.h" +#if NRF51 + #include "nrf_sdm.h" +#elif NRF52 + #include "nrf_nvic.h" +#endif #endif static inline void hal_irq_clear(uint32_t irq_num) { From d877e0e53373b45744a6c54d406a2eedf4f02861 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 21 May 2017 18:12:44 +0200 Subject: [PATCH 718/809] nrf5/examples: Tuning Bluetooth LE example controller python script after testing out the example live. Motor speed of 100 was not enought to lift the airplane. Also turning was hard without setting higher angle values. The new values are just guessed values. However, the flying experience was good. --- nrf5/examples/powerup.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/nrf5/examples/powerup.py b/nrf5/examples/powerup.py index ba8fe0cd0e..d65f9b7e3c 100644 --- a/nrf5/examples/powerup.py +++ b/nrf5/examples/powerup.py @@ -147,7 +147,7 @@ class PowerUp3: def rudder_left(self, angle): steps = (angle // self.interval_size_left) - new_angle = 25 - steps + new_angle = 60 - steps if self.old_angle != new_angle: self.angle(new_angle) @@ -162,8 +162,8 @@ class PowerUp3: self.old_angle = new_angle def throttle(self, speed): - if (speed > 100): - speed = 100 + if (speed > 200): + speed = 200 elif (speed < 0): speed = 0 @@ -176,8 +176,8 @@ class PowerUp3: right_threshold = self.x_mid + adc_threshold left_threshold = self.x_mid - adc_threshold - self.interval_size_left = self.x_mid // 25 - self.interval_size_right = (255 - self.x_mid) // 25 + self.interval_size_left = self.x_mid // 60 + self.interval_size_right = (255 - self.x_mid) // 60 self.old_angle = 0 self.old_speed = 0 @@ -204,7 +204,7 @@ class PowerUp3: elif self.button_speed_down(): new_speed -= 25 elif self.button_speed_full(): - new_speed = 100 + new_speed = 200 elif self.button_speed_off(): new_speed = 0 else: From d7145339aa9ed0405648ffc5d12a9f9340a63aa1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 21 May 2017 23:05:16 +0200 Subject: [PATCH 719/809] nrf5/device: Adding startup files in .c to replace current asm versions. --- nrf5/device/nrf51/startup_nrf51822.c | 151 ++++++++++++++++++++++ nrf5/device/nrf52/startup_nrf52832.c | 167 ++++++++++++++++++++++++ nrf5/device/nrf52/startup_nrf52840.c | 182 +++++++++++++++++++++++++++ 3 files changed, 500 insertions(+) create mode 100644 nrf5/device/nrf51/startup_nrf51822.c create mode 100644 nrf5/device/nrf52/startup_nrf52832.c create mode 100644 nrf5/device/nrf52/startup_nrf52840.c diff --git a/nrf5/device/nrf51/startup_nrf51822.c b/nrf5/device/nrf51/startup_nrf51822.c new file mode 100644 index 0000000000..826339da3f --- /dev/null +++ b/nrf5/device/nrf51/startup_nrf51822.c @@ -0,0 +1,151 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +extern uint32_t _estack; +extern uint32_t _sidata; +extern uint32_t _sdata; +extern uint32_t _edata; +extern uint32_t _sbss; +extern uint32_t _ebss; + +typedef void (*func)(void); + +extern void _start(void) __attribute__((noreturn)); +extern void SystemInit(void); + +void Default_Handler(void) { + while (1); +} + +void Reset_Handler(void) { + uint32_t * ram_on_addr = (uint32_t *)0x40000524; + uint32_t * ram_on_b_addr = (uint32_t *)0x40000554; + // RAM on in on-mode + *ram_on_addr = 3; // block 0 and 1 + *ram_on_b_addr = 3; // block 2 and 3 +#if 0 + // RAM on in off-mode + ram_on_addr = 1 << 16; + ram_on_b_addr = 1 << 17; +#endif + + uint32_t * p_src = &_sidata; + uint32_t * p_dest = &_sdata; + + while (p_dest < &_edata) { + *p_dest++ = *p_src++; + } + + uint32_t * p_bss = &_sbss; + uint32_t * p_bss_end = &_ebss; + while (p_bss < p_bss_end) { + *p_bss++ = 0ul; + } + + SystemInit(); + _start(); +} + +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void POWER_CLOCK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RADIO_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOTE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TEMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ECB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CCM_AAR_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void QDEC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPCOMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + +const func __Vectors[] __attribute__ ((section(".isr_vector"))) = { + (func)&_estack, + Reset_Handler, + NMI_Handler, + HardFault_Handler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SVC_Handler, + 0, + 0, + PendSV_Handler, + SysTick_Handler, + + /* External Interrupts */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UART0_IRQHandler, + SPI0_TWI0_IRQHandler, + SPI1_TWI1_IRQHandler, + 0, + GPIOTE_IRQHandler, + ADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + LPCOMP_IRQHandler, + SWI0_IRQHandler, + SWI1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler +}; diff --git a/nrf5/device/nrf52/startup_nrf52832.c b/nrf5/device/nrf52/startup_nrf52832.c new file mode 100644 index 0000000000..d568fd62be --- /dev/null +++ b/nrf5/device/nrf52/startup_nrf52832.c @@ -0,0 +1,167 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +extern uint32_t _estack; +extern uint32_t _sidata; +extern uint32_t _sdata; +extern uint32_t _edata; +extern uint32_t _sbss; +extern uint32_t _ebss; + +typedef void (*func)(void); + +extern void _start(void) __attribute__((noreturn)); +extern void SystemInit(void); + +void Default_Handler(void) { + while (1); +} + +void Reset_Handler(void) { + uint32_t * p_src = &_sidata; + uint32_t * p_dest = &_sdata; + + while (p_dest < &_edata) { + *p_dest++ = *p_src++; + } + + uint32_t * p_bss = &_sbss; + uint32_t * p_bss_end = &_ebss; + while (p_bss < p_bss_end) { + *p_bss++ = 0ul; + } + + SystemInit(); + _start(); +} + +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemoryManagement_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void POWER_CLOCK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RADIO_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTE0_UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NFCT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOTE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAADC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TEMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ECB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CCM_AAR_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void QDEC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void COMP_LPCOMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI0_EGU0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI1_EGU1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI2_EGU2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI3_EGU3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI4_EGU4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI5_EGU5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PDM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MWU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM2_SPIS2_SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + +const func __Vectors[] __attribute__ ((section(".isr_vector"))) = { + (func)&_estack, + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + + /* External Interrupts */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UARTE0_UART0_IRQHandler, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, + NFCT_IRQHandler, + GPIOTE_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + COMP_LPCOMP_IRQHandler, + SWI0_EGU0_IRQHandler, + SWI1_EGU1_IRQHandler, + SWI2_EGU2_IRQHandler, + SWI3_EGU3_IRQHandler, + SWI4_EGU4_IRQHandler, + SWI5_EGU5_IRQHandler, + TIMER3_IRQHandler, + TIMER4_IRQHandler, + PWM0_IRQHandler, + PDM_IRQHandler, + 0, + 0, + MWU_IRQHandler, + PWM1_IRQHandler, + PWM2_IRQHandler, + SPIM2_SPIS2_SPI2_IRQHandler, + RTC2_IRQHandler, + I2S_IRQHandler +}; diff --git a/nrf5/device/nrf52/startup_nrf52840.c b/nrf5/device/nrf52/startup_nrf52840.c new file mode 100644 index 0000000000..6d0347f7a8 --- /dev/null +++ b/nrf5/device/nrf52/startup_nrf52840.c @@ -0,0 +1,182 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +extern uint32_t _estack; +extern uint32_t _sidata; +extern uint32_t _sdata; +extern uint32_t _edata; +extern uint32_t _sbss; +extern uint32_t _ebss; + +typedef void (*func)(void); + +extern void _start(void) __attribute__((noreturn)); +extern void SystemInit(void); + +void Default_Handler(void) { + while (1); +} + +void Reset_Handler(void) { + uint32_t * p_src = &_sidata; + uint32_t * p_dest = &_sdata; + + while (p_dest < &_edata) { + *p_dest++ = *p_src++; + } + + uint32_t * p_bss = &_sbss; + uint32_t * p_bss_end = &_ebss; + while (p_bss < p_bss_end) { + *p_bss++ = 0ul; + } + + SystemInit(); + _start(); +} + +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemoryManagement_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void POWER_CLOCK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RADIO_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTE0_UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NFCT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOTE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAADC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TEMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ECB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CCM_AAR_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void QDEC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void COMP_LPCOMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI0_EGU0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI1_EGU1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI2_EGU2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI3_EGU3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI4_EGU4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI5_EGU5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PDM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MWU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM2_SPIS2_SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTE1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void QSPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CRYPTOCELL_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + +const func __Vectors[] __attribute__ ((section(".isr_vector"))) = { + (func)&_estack, + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + + /* External Interrupts */ + POWER_CLOCK_IRQHandler, + RADIO_IRQHandler, + UARTE0_UART0_IRQHandler, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, + NFCT_IRQHandler, + GPIOTE_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + RTC0_IRQHandler, + TEMP_IRQHandler, + RNG_IRQHandler, + ECB_IRQHandler, + CCM_AAR_IRQHandler, + WDT_IRQHandler, + RTC1_IRQHandler, + QDEC_IRQHandler, + COMP_LPCOMP_IRQHandler, + SWI0_EGU0_IRQHandler, + SWI1_EGU1_IRQHandler, + SWI2_EGU2_IRQHandler, + SWI3_EGU3_IRQHandler, + SWI4_EGU4_IRQHandler, + SWI5_EGU5_IRQHandler, + TIMER3_IRQHandler, + TIMER4_IRQHandler, + PWM0_IRQHandler, + PDM_IRQHandler, + 0, + 0, + MWU_IRQHandler, + PWM1_IRQHandler, + PWM2_IRQHandler, + SPIM2_SPIS2_SPI2_IRQHandler, + RTC2_IRQHandler, + I2S_IRQHandler, + FPU_IRQHandler, + USBD_IRQHandler, + UARTE1_IRQHandler, + QSPI_IRQHandler, + CRYPTOCELL_IRQHandler, + SPIM3_IRQHandler, + 0, + PWM3_IRQHandler, +}; From d580fa4088e9158df975edd619918539bf9d065e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 21 May 2017 23:06:34 +0200 Subject: [PATCH 720/809] nrf5: Update Makefile to add c-implementation of startup scripts instead of the .s files. --- nrf5/Makefile | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 70dea01e33..1de1354f27 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -166,20 +166,14 @@ DRIVERS_SRC_C += $(addprefix modules/,\ ble/modble.c \ ) -#ifeq ($(SD), ) - SRC_C += \ device/$(MCU_VARIANT)/system_$(MCU_SUB_VARIANT).c \ - -SRC_S = \ - device/$(MCU_VARIANT)/startup_$(MCU_VARIANT).s \ - -#endif + device/$(MCU_VARIANT)/startup_$(MCU_SUB_VARIANT).c \ FROZEN_MPY_PY_FILES := $(shell find -L $(FROZEN_MPY_DIR) -type f -name '*.py') FROZEN_MPY_MPY_FILES := $(addprefix $(BUILD)/,$(FROZEN_MPY_PY_FILES:.py=.mpy)) -OBJ += $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o)) +OBJ += $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_HAL:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(DRIVERS_SRC_C:.c=.o)) From e87dcd8940c60ba73379765fcd6a9e699751eb4a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 21 May 2017 23:08:56 +0200 Subject: [PATCH 721/809] nrf5/device: Remove old startup files in asm, which has now been replaced with c-implementation. --- nrf5/device/nrf51/startup_nrf51.s | 219 ------------------------ nrf5/device/nrf52/startup_nrf52.s | 266 ------------------------------ 2 files changed, 485 deletions(-) delete mode 100644 nrf5/device/nrf51/startup_nrf51.s delete mode 100644 nrf5/device/nrf52/startup_nrf52.s diff --git a/nrf5/device/nrf51/startup_nrf51.s b/nrf5/device/nrf51/startup_nrf51.s deleted file mode 100644 index 9b6d541708..0000000000 --- a/nrf5/device/nrf51/startup_nrf51.s +++ /dev/null @@ -1,219 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2015 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - - .syntax unified - .arch armv6-m - -.global __Vectors -.global Default_Handler - -.word _sidata -.word _sdata -.word _edata -.word _sbss -.word _ebss - -/* Reset Handler */ - - .equ NRF_POWER_RAMON_ADDRESS, 0x40000524 - .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554 - .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3 - - .text - .thumb - .thumb_func - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - .fnstart - - movs R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk - ldr R0, =NRF_POWER_RAMON_ADDRESS - ldr R2, [R0] - orrs R2, R1 - str R2, [R0] - - ldr R0, =NRF_POWER_RAMONB_ADDRESS - ldr R2, [R0] - orrs R2, R1 - str R2, [R0] - - ldr r1, =_sidata - ldr r2, =_sdata - ldr r3, =_edata - - subs r3, r2 - ble LC0 - -LC1: - subs r3, 4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt LC1 - -LC0: - bl SystemInit - bl main - bx lr - - .pool - .cantunwind - .fnend - .size Reset_Handler,.-Reset_Handler - -/* Default Handler */ - - .section ".text" - .section .text.Default_Handler,"ax",%progbits -Default_Handler: - b . - .size Default_Handler, .-Default_Handler - - -/* Vector Table */ - - .section .isr_vector,"a",%progbits - .type __Vectors, %object - .size __Vectors, .-__Vectors - -__Vectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word POWER_CLOCK_IRQHandler - .word RADIO_IRQHandler - .word UART0_IRQHandler - .word SPI0_TWI0_IRQHandler - .word SPI1_TWI1_IRQHandler - .word 0 - .word GPIOTE_IRQHandler - .word ADC_IRQHandler - .word TIMER0_IRQHandler - .word TIMER1_IRQHandler - .word TIMER2_IRQHandler - .word RTC0_IRQHandler - .word TEMP_IRQHandler - .word RNG_IRQHandler - .word ECB_IRQHandler - .word CCM_AAR_IRQHandler - .word WDT_IRQHandler - .word RTC1_IRQHandler - .word QDEC_IRQHandler - .word LPCOMP_IRQHandler - .word SWI0_IRQHandler - .word SWI1_IRQHandler - .word SWI2_IRQHandler - .word SWI3_IRQHandler - .word SWI4_IRQHandler - .word SWI5_IRQHandler - -/* Dummy Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - b . - .size NMI_Handler, . - NMI_Handler - - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - b . - .size HardFault_Handler, . - HardFault_Handler - - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - b . - .size PendSV_Handler, . - PendSV_Handler - - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - b . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ POWER_CLOCK_IRQHandler - IRQ RADIO_IRQHandler - IRQ UART0_IRQHandler - IRQ SPI0_TWI0_IRQHandler - IRQ SPI1_TWI1_IRQHandler - IRQ GPIOTE_IRQHandler - IRQ ADC_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ RTC0_IRQHandler - IRQ TEMP_IRQHandler - IRQ RNG_IRQHandler - IRQ ECB_IRQHandler - IRQ CCM_AAR_IRQHandler - IRQ WDT_IRQHandler - IRQ RTC1_IRQHandler - IRQ QDEC_IRQHandler - IRQ LPCOMP_IRQHandler - IRQ SWI0_IRQHandler - IRQ SWI1_IRQHandler - IRQ SWI2_IRQHandler - IRQ SWI3_IRQHandler - IRQ SWI4_IRQHandler - IRQ SWI5_IRQHandler - - .end diff --git a/nrf5/device/nrf52/startup_nrf52.s b/nrf5/device/nrf52/startup_nrf52.s deleted file mode 100644 index 28906b7d9f..0000000000 --- a/nrf5/device/nrf52/startup_nrf52.s +++ /dev/null @@ -1,266 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2015 Glenn Ruben Bakke - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -.syntax unified -.arch armv6-m - -.section .stack -.align 3 - -.global __Vectors -.global Default_Handler - -.word _sidata -.word _sdata -.word _edata -.word _sbss -.word _ebss - -/* Reset Handler */ - - .text - .thumb - .thumb_func - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - .fnstart - - ldr r1, =_sidata - ldr r2, =_sdata - ldr r3, =_sbss - - subs r3, r2 - ble CopyDone - b CopyData - -CopyData: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt CopyData - -CopyDone: - ldr r1, =_sbss - ldr r2, =_ebss - - movs r0, 0 - - subs r2, r1 - ble ZeroDone - -ZeroLoop: - subs r2, #4 - str r0, [r1, r2] - bgt ZeroLoop - -ZeroDone: - - bl SystemInit - bl _start - bx lr - - .pool - .cantunwind - .fnend - .size Reset_Handler,.-Reset_Handler - -/* Default Handler */ - - .section ".text" - .section .text.Default_Handler,"ax",%progbits -Default_Handler: - b . - .size Default_Handler, .-Default_Handler - -/* Vector Table */ - - .section .isr_vector,"a",%progbits - .type __Vectors, %object - .size __Vectors, .-__Vectors - -__Vectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word POWER_CLOCK_IRQHandler - .word RADIO_IRQHandler - .word UARTE0_UART0_IRQHandler - .word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .word NFCT_IRQHandler - .word GPIOTE_IRQHandler - .word SAADC_IRQHandler - .word TIMER0_IRQHandler - .word TIMER1_IRQHandler - .word TIMER2_IRQHandler - .word RTC0_IRQHandler - .word TEMP_IRQHandler - .word RNG_IRQHandler - .word ECB_IRQHandler - .word CCM_AAR_IRQHandler - .word WDT_IRQHandler - .word RTC1_IRQHandler - .word QDEC_IRQHandler - .word COMP_LPCOMP_IRQHandler - .word SWI0_EGU0_IRQHandler - .word SWI1_EGU1_IRQHandler - .word SWI2_EGU2_IRQHandler - .word SWI3_EGU3_IRQHandler - .word SWI4_EGU4_IRQHandler - .word SWI5_EGU5_IRQHandler - .word TIMER3_IRQHandler - .word TIMER4_IRQHandler - .word PWM0_IRQHandler - .word PDM_IRQHandler - .word 0 - .word 0 - .word MWU_IRQHandler - .word PWM1_IRQHandler - .word PWM2_IRQHandler - .word SPIM2_SPIS2_SPI2_IRQHandler - .word RTC2_IRQHandler - .word I2S_IRQHandler - -/* Dummy Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - - .weak MemoryManagement_Handler - .type MemoryManagement_Handler, %function -MemoryManagement_Handler: - B . - .size MemoryManagement_Handler, . - MemoryManagement_Handler - - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - B . - .size BusFault_Handler, . - BusFault_Handler - - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - B . - .size UsageFault_Handler, . - UsageFault_Handler - - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ POWER_CLOCK_IRQHandler - IRQ RADIO_IRQHandler - IRQ UARTE0_UART0_IRQHandler - IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - IRQ NFCT_IRQHandler - IRQ GPIOTE_IRQHandler - IRQ SAADC_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ RTC0_IRQHandler - IRQ TEMP_IRQHandler - IRQ RNG_IRQHandler - IRQ ECB_IRQHandler - IRQ CCM_AAR_IRQHandler - IRQ WDT_IRQHandler - IRQ RTC1_IRQHandler - IRQ QDEC_IRQHandler - IRQ COMP_LPCOMP_IRQHandler - IRQ SWI0_EGU0_IRQHandler - IRQ SWI1_EGU1_IRQHandler - IRQ SWI2_EGU2_IRQHandler - IRQ SWI3_EGU3_IRQHandler - IRQ SWI4_EGU4_IRQHandler - IRQ SWI5_EGU5_IRQHandler - IRQ TIMER3_IRQHandler - IRQ TIMER4_IRQHandler - IRQ PWM0_IRQHandler - IRQ PDM_IRQHandler - IRQ MWU_IRQHandler - IRQ PWM1_IRQHandler - IRQ PWM2_IRQHandler - IRQ SPIM2_SPIS2_SPI2_IRQHandler - IRQ RTC2_IRQHandler - IRQ I2S_IRQHandler - - .end From c7cc57eaa0e9af95b5226001e6fca90ad1bd22e3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 25 May 2017 00:12:45 +0200 Subject: [PATCH 722/809] nrf5/modules/machine: Updating IRQ levels in SPI with IRQ priorities compatible with Bluetooth stacks. --- nrf5/modules/machine/spi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/machine/spi.c b/nrf5/modules/machine/spi.c index 989942bf5e..b415b87925 100644 --- a/nrf5/modules/machine/spi.c +++ b/nrf5/modules/machine/spi.c @@ -306,8 +306,11 @@ STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) { } else { // Default self->pyb->spi->init.freq = HAL_SPI_FREQ_1_Mbps; } - - self->pyb->spi->init.irq_priority = 4; +#ifdef NRF51 + self->pyb->spi->init.irq_priority = 3; +#else + self->pyb->spi->init.irq_priority = 6; +#endif self->pyb->spi->init.mode = HAL_SPI_MODE_CPOL0_CPHA0; self->pyb->spi->init.firstbit = (args[ARG_NEW_firstbit].u_int == 0) ? HAL_SPI_MSB_FIRST : HAL_SPI_LSB_FIRST;; hal_spi_master_init(self->pyb->spi->instance, &self->pyb->spi->init); From 2f40c61c3e1eaf97ae12650a00530718bf9cd4be Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 24 May 2017 23:22:23 +0200 Subject: [PATCH 723/809] nrf5/hal/irq: Adding wrappers for handling nvic calls when Bluetooth LE stack is enabled. --- nrf5/hal/hal_irq.h | 84 +++++++++++++++++++++++++++++++++------------- 1 file changed, 60 insertions(+), 24 deletions(-) diff --git a/nrf5/hal/hal_irq.h b/nrf5/hal/hal_irq.h index 266758beec..a610f1035a 100644 --- a/nrf5/hal/hal_irq.h +++ b/nrf5/hal/hal_irq.h @@ -32,52 +32,88 @@ #include "nrf.h" #if BLUETOOTH_SD -#if NRF51 - #include "nrf_sdm.h" -#elif NRF52 +#include "py/nlr.h" +#include "ble_drv.h" + +#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled()) + +#ifdef NRF51 + #include "nrf_soc.h" +#elif defined(NRF52) #include "nrf_nvic.h" #endif -#endif +#endif // BLUETOOTH_SD static inline void hal_irq_clear(uint32_t irq_num) { #if BLUETOOTH_SD - sd_nvic_ClearPendingIRQ(irq_num); -#else - NVIC_ClearPendingIRQ(irq_num); -#endif + if (BLUETOOTH_STACK_ENABLED() == 1) { + if (sd_nvic_ClearPendingIRQ(irq_num) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "IRQ (%d) clear error", irq_num)); + } + } else +#endif // BLUETOOTH_SD + { + NVIC_ClearPendingIRQ(irq_num); + } } static inline void hal_irq_enable(uint32_t irq_num) { hal_irq_clear(irq_num); + #if BLUETOOTH_SD - sd_nvic_EnableIRQ(irq_num); -#else - NVIC_EnableIRQ(irq_num); -#endif + if (BLUETOOTH_STACK_ENABLED() == 1) { + if (sd_nvic_EnableIRQ(irq_num) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "IRQ (%d) enable error", irq_num)); + } + } else +#endif // BLUETOOTH_SD + { + NVIC_EnableIRQ(irq_num); + } } static inline void hal_irq_disable(uint32_t irq_num) { #if BLUETOOTH_SD - sd_nvic_DisableIRQ(irq_num); -#else - NVIC_DisableIRQ(irq_num); -#endif + if (BLUETOOTH_STACK_ENABLED() == 1) { + if (sd_nvic_DisableIRQ(irq_num) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "IRQ (%d) disable error", irq_num)); + } + } else +#endif // BLUETOOTH_SD + { + NVIC_DisableIRQ(irq_num); + } } static inline void hal_irq_priority(uint32_t irq_num, uint8_t priority) { #if BLUETOOTH_SD - sd_nvic_SetPriority(irq_num, priority); -#else - NVIC_SetPriority(irq_num, priority); -#endif + if (BLUETOOTH_STACK_ENABLED() == 1) { + if (sd_nvic_SetPriority(irq_num, priority) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "IRQ (%d) priority error", irq_num, priority)); + } + } else +#endif // BLUETOOTH_SD + { + NVIC_SetPriority(irq_num, priority); + } } static inline void hal_irq_pending(uint32_t irq_num) { #if BLUETOOTH_SD - sd_nvic_SetPendingIRQ(irq_num); -#else - NVIC_SetPendingIRQ(irq_num); -#endif + if (BLUETOOTH_STACK_ENABLED() == 1) { + if (sd_nvic_SetPendingIRQ(irq_num) != 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "IRQ (%d) pending error", irq_num)); + } + } else +#endif // BLUETOOTH_SD + { + NVIC_SetPendingIRQ(irq_num); + } } #endif // HAL_IRQ_H__ From ed93392d8764b5d8eafce6c7c3ac24780a5751b0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 24 May 2017 23:24:14 +0200 Subject: [PATCH 724/809] nrf5/drivers/bluetooth: Updating bluetooth driver to initialize nrf_nvic_state_t struct during declaration of the global variable instead of explicit memset. --- nrf5/drivers/bluetooth/ble_drv.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index 43dc5c87e3..418c1f4a3f 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -94,11 +94,9 @@ static mp_obj_t mp_gattc_char_data_observer; #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) #include "nrf_nvic.h" -#if NRF51 -nrf_nvic_state_t nrf_nvic_state;; -#else -nrf_nvic_state_t nrf_nvic_state; -#endif // NRF51 +#ifdef NRF52 +nrf_nvic_state_t nrf_nvic_state = {0}; +#endif // NRF52 #endif // (BLUETOOTH_SD != 100) @@ -115,10 +113,6 @@ uint32_t ble_drv_stack_enable(void) { m_adv_in_progress = false; m_tx_in_progress = false; -#if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) - memset(&nrf_nvic_state, 0, sizeof(nrf_nvic_state_t)); -#endif - #if (BLUETOOTH_SD == 100) || (BLUETOOTH_SD == 110) #if BLUETOOTH_LFCLK_RC uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_RC_250_PPM_250MS_CALIBRATION, From aa9ad6be014e83aa77e39f1cf0915178d6e2005c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 24 May 2017 23:30:27 +0200 Subject: [PATCH 725/809] nrf5/modules/music: Update ticker and modmusic to share global ticks counter as a volatile variable. Use Timer1 hardware peripheral instead of instance 0. Timer0 is not free if used in combination with a bluetooth stack. Update IRQ priority to levels that are compatible in use with a bluetooth stack for both nrf51 and nrf52. Apply nrf51 PAN fixes for Timer1 instead of original Timer0. --- nrf5/drivers/ticker.c | 29 ++++++++++++++++++++--------- nrf5/modules/music/modmusic.c | 2 +- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/nrf5/drivers/ticker.c b/nrf5/drivers/ticker.c index 3e439a96d8..bbba231213 100644 --- a/nrf5/drivers/ticker.c +++ b/nrf5/drivers/ticker.c @@ -31,21 +31,21 @@ #include "ticker.h" #include "hal_irq.h" -#define FastTicker NRF_TIMER0 -#define FastTicker_IRQn TIMER0_IRQn -#define FastTicker_IRQHandler TIMER0_IRQHandler +#define FastTicker NRF_TIMER1 +#define FastTicker_IRQn TIMER1_IRQn +#define FastTicker_IRQHandler TIMER1_IRQHandler #define SlowTicker_IRQn SWI0_IRQn #define SlowTicker_IRQHandler SWI0_IRQHandler // Ticker callback function called every MACRO_TICK -static callback_ptr slow_ticker; +static volatile callback_ptr slow_ticker; void ticker_init(callback_ptr slow_ticker_callback) { slow_ticker = slow_ticker_callback; NRF_TIMER_Type *ticker = FastTicker; -#if NRF51 +#ifdef NRF51 ticker->POWER = 1; #endif __NOP(); @@ -58,31 +58,42 @@ void ticker_init(callback_ptr slow_ticker_callback) { ticker->INTENSET = TIMER_INTENSET_COMPARE3_Msk; ticker->SHORTS = 0; +#ifdef NRF51 hal_irq_priority(FastTicker_IRQn, 1); +#else + hal_irq_priority(FastTicker_IRQn, 2); +#endif + hal_irq_priority(SlowTicker_IRQn, 3); + hal_irq_priority(SlowTicker_IRQn, 3); + hal_irq_enable(SlowTicker_IRQn); } -/* Start and stop timer 0 including workarounds for Anomaly 73 for Timer +/* Start and stop timer 1 including workarounds for Anomaly 73 for Timer * http://www.nordicsemi.com/eng/content/download/29490/494569/file/nRF51822-PAN%20v3.0.pdf */ void ticker_start(void) { hal_irq_enable(FastTicker_IRQn); - *(uint32_t *)0x40008C0C = 1; //for Timer 0 +#ifdef NRF51 + *(uint32_t *)0x40009C0C = 1; // for Timer 1 +#endif FastTicker->TASKS_START = 1; } void ticker_stop(void) { hal_irq_disable(FastTicker_IRQn); FastTicker->TASKS_STOP = 1; - *(uint32_t *)0x40008C0C = 0; //for Timer 0 +#ifdef NRF51 + *(uint32_t *)0x40009C0C = 0; // for Timer 1 +#endif } int32_t noop(void) { return -1; } -uint32_t ticks; +volatile uint32_t ticks; static ticker_callback_ptr callbacks[3] = { noop, noop, noop }; diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index 7e8ff30dbd..029200ea9d 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -72,7 +72,7 @@ enum { #define music_data MP_STATE_PORT(music_data) -extern uint32_t ticks; +extern volatile uint32_t ticks; STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_t *pin); From d9813910dad9d95b8e53ef3c6916a24747070390 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 24 May 2017 23:33:28 +0200 Subject: [PATCH 726/809] nrf5/modules/machine/timer: If timer is used in combination with SOFT_PWM (implicitly use of ticker.c) guard the Timer1 instance from being instantiated trough python timer module. Also disable implementation of the HAL IRQ handler which is for now explicitly implemented in ticker.c for Timer1. --- nrf5/hal/hal_timer.c | 4 ++-- nrf5/modules/machine/timer.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/hal/hal_timer.c b/nrf5/hal/hal_timer.c index 42d4d24c21..715d540288 100644 --- a/nrf5/hal/hal_timer.c +++ b/nrf5/hal/hal_timer.c @@ -39,15 +39,15 @@ void hal_timer_start(uint8_t id) { void hal_timer_stop(uint8_t id) { } -#if (MICROPY_PY_MACHINE_SOFT_PWM != 1) void TIMER0_IRQHandler(void) { } -#endif +#if (MICROPY_PY_MACHINE_SOFT_PWM != 1) void TIMER1_IRQHandler(void) { } +#endif void TIMER2_IRQHandler(void) { diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index a8284cd741..e81379ae3e 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -99,7 +99,7 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, int timer_id = timer_find(args[ARG_NEW_id].u_obj); #if MICROPY_PY_MACHINE_SOFT_PWM - if (timer_id == 0) { + if (timer_id == 1) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Timer(%d) reserved by ticker driver.", timer_id)); } From aba5fcbf0fff3bfc11bc6a06693c5435de855ea7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 24 May 2017 23:38:33 +0200 Subject: [PATCH 727/809] nrf5/main: Move initializaton of modmusic to the module itself. Upon init of the module, the hardware, pwm and ticker will be started. Could be moved back to main if pwm or ticker should be shared among more modules and have to be initialized more global. --- nrf5/main.c | 8 -------- nrf5/modules/music/modmusic.c | 2 ++ 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/nrf5/main.c b/nrf5/main.c index aa799c8f63..72b4a79653 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -123,14 +123,6 @@ int main(int argc, char **argv) { timer_init0(); #endif -#if MICROPY_PY_MUSIC - microbit_music_init0(); -#endif - /* - extint_init0(); - timer_init0(); - */ - uart_init0(); #if (MICROPY_PY_BLE_NUS == 0) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index 029200ea9d..680c7c0422 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -451,6 +451,8 @@ MP_DEFINE_CONST_FUN_OBJ_KW(microbit_music_set_tempo_obj, 0, microbit_music_set_t static mp_obj_t music_init(void) { + microbit_music_init0(); + music_data = m_new_obj(music_data_t); music_data->bpm = DEFAULT_BPM; music_data->ticks = DEFAULT_TICKS; From 88b4ebc71557962e7689b1e51c5228ba60459d05 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 25 May 2017 21:32:18 +0200 Subject: [PATCH 728/809] nrf5/boards/feather52: Update SPI pinout. --- nrf5/boards/feather52/mpconfigboard.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/boards/feather52/mpconfigboard.h b/nrf5/boards/feather52/mpconfigboard.h index 01fca8a08a..81c9f8c0bb 100644 --- a/nrf5/boards/feather52/mpconfigboard.h +++ b/nrf5/boards/feather52/mpconfigboard.h @@ -64,9 +64,9 @@ // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" -#define MICROPY_HW_SPI0_SCK (pin_A25) // (Arduino D13) -#define MICROPY_HW_SPI0_MOSI (pin_A23) // (Arduino D11) -#define MICROPY_HW_SPI0_MISO (pin_A24) // (Arduino D12) +#define MICROPY_HW_SPI0_SCK (pin_A12) // (Arduino D13) +#define MICROPY_HW_SPI0_MOSI (pin_A13) // (Arduino D11) +#define MICROPY_HW_SPI0_MISO (pin_A14) // (Arduino D12) #define MICROPY_HW_PWM0_NAME "PWM0" #define MICROPY_HW_PWM1_NAME "PWM1" From cb7a0aefa079928d5bdb4c79d4186491431d2237 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 25 May 2017 21:44:36 +0200 Subject: [PATCH 729/809] nrf5/boards/feather52: Updating LED pull to low. --- nrf5/boards/feather52/mpconfigboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/boards/feather52/mpconfigboard.h b/nrf5/boards/feather52/mpconfigboard.h index 81c9f8c0bb..3d99f3c489 100644 --- a/nrf5/boards/feather52/mpconfigboard.h +++ b/nrf5/boards/feather52/mpconfigboard.h @@ -52,7 +52,7 @@ #define MICROPY_HW_ENABLE_CAN (0) #define MICROPY_HW_LED_COUNT (2) -#define MICROPY_HW_LED_PULLUP (1) +#define MICROPY_HW_LED_PULLUP (0) #define MICROPY_HW_LED1 (17) // LED1 #define MICROPY_HW_LED2 (19) // LED2 From 44673de11496b133540348614d2b9b8f733723e7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 25 May 2017 22:14:27 +0200 Subject: [PATCH 730/809] nrf5/boards/feather52: Updating pins.csv for the feather52 board. --- nrf5/boards/feather52/pins.csv | 43 +++++++++++++++------------------- 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/nrf5/boards/feather52/pins.csv b/nrf5/boards/feather52/pins.csv index c177133983..9ac45403c3 100644 --- a/nrf5/boards/feather52/pins.csv +++ b/nrf5/boards/feather52/pins.csv @@ -1,30 +1,25 @@ -PA2,PA2 -PA3,PA3 -PA4,PA4 -PA5,PA5 -PA6,PA6 +PA2,PA2,ADC0_IN0 +PA3,PA3,ADC0_IN1 +PA4,PA4,ADC0_IN2 +PA5,PA5,ADC0_IN3 +UART_TX,PA6 PA7,PA7 -PA8,PA8 -PA9,PA9 -PA10,PA10 +UART_RX,PA8 +NFC1,PA9 +NFC2,PA10 PA11,PA11 -PA12,PA12 -PA13,PA13 -PA14,PA14 +SPI_SCK,PA12 +SPI_MOSI,PA13 +SPI_MISO,PA14 PA15,PA15 PA16,PA16 -PA17,PA17 -PA18,PA18 -PA19,PA19 +LED1,PA17 +LED2,PA19 PA20,PA20 -PA21,PA21 -PA22,PA22 -PA23,PA23 -PA24,PA24 PA25,PA25 -PA26,PA26 -PA27,PA27 -PA28,PA28 -PA29,PA29 -PA30,PA30 -PA31,PA31 \ No newline at end of file +I2C_SCL,PA26 +I2C_SDA,PA27 +PA28,PA28,ADC0_IN4 +PA29,PA29,ADC0_IN5 +PA30,PA30,ADC0_IN6 +PA31,PA31,ADC0_IN7 From cb9ed6bb55a5020770ad31fd30a05b4a91b70a81 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 25 May 2017 22:19:12 +0200 Subject: [PATCH 731/809] nrf5/drivers/bluetooth: Enable ubluepy central by default if running nrf52/s132 bluetooth stack. Maturity of the module is pretty OK now. --- nrf5/bluetooth_conf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/bluetooth_conf.h b/nrf5/bluetooth_conf.h index 701cc13a6d..6a3cbdc83e 100644 --- a/nrf5/bluetooth_conf.h +++ b/nrf5/bluetooth_conf.h @@ -18,7 +18,7 @@ #define BLUETOOTH_WEBBLUETOOTH_REPL (0) #define MICROPY_PY_UBLUEPY (1) #define MICROPY_PY_UBLUEPY_PERIPHERAL (1) -#define MICROPY_PY_UBLUEPY_CENTRAL (0) +#define MICROPY_PY_UBLUEPY_CENTRAL (1) #else #error "SD not supported" From f3909c49f57197a14530076896c81158a1ad670c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 28 May 2017 19:33:33 +0200 Subject: [PATCH 732/809] nrf5/modules/spi: Remove pyb abstraction from SPI module, as there was a bug in transfer of bytes due to casting errors. The update removes the pyb_spi_obj_t wrapper going directly on the machine_hard_spi_obj_t as base for machine SPI objects. SDCard mounting is also tested. --- nrf5/modules/machine/spi.c | 67 ++++++++++++++++---------------------- nrf5/modules/machine/spi.h | 7 +--- 2 files changed, 29 insertions(+), 45 deletions(-) diff --git a/nrf5/modules/machine/spi.c b/nrf5/modules/machine/spi.c index b415b87925..34ea45dc18 100644 --- a/nrf5/modules/machine/spi.c +++ b/nrf5/modules/machine/spi.c @@ -72,7 +72,7 @@ SPI_HandleTypeDef SPIHandle3 = {.instance = NULL}; // 32 Mbs master only #endif // NRF52840_XXAA #endif // NRF52 -STATIC const pyb_spi_obj_t machine_spi_obj[] = { +STATIC const machine_hard_spi_obj_t machine_hard_spi_obj[] = { {{&machine_hard_spi_type}, &SPIHandle0}, {{&machine_hard_spi_type}, &SPIHandle1}, #if NRF52 @@ -115,8 +115,8 @@ STATIC int spi_find(mp_obj_t id) { } else { // given an integer id int spi_id = mp_obj_get_int(id); - if (spi_id >= 0 && spi_id <= MP_ARRAY_SIZE(machine_spi_obj) - && machine_spi_obj[spi_id].spi != NULL) { + if (spi_id >= 0 && spi_id <= MP_ARRAY_SIZE(machine_hard_spi_obj) + && machine_hard_spi_obj[spi_id].spi != NULL) { return spi_id; } nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, @@ -130,7 +130,7 @@ void spi_init(SPI_HandleTypeDef *spi, bool enable_nss_pin) { void spi_deinit(SPI_HandleTypeDef *spi) { } -STATIC void spi_transfer(const pyb_spi_obj_t * self, size_t len, const void * src, void * dest) { +STATIC void spi_transfer(const machine_hard_spi_obj_t * self, size_t len, const void * src, void * dest) { hal_spi_master_tx_rx(self->spi->instance, len, src, dest); } @@ -246,20 +246,9 @@ STATIC MP_DEFINE_CONST_DICT(machine_spi_locals_dict, machine_spi_locals_dict_tab /* code for hard implementation ***********************************************/ -STATIC const machine_hard_spi_obj_t machine_hard_spi_obj[] = { - {{&machine_hard_spi_type}, &machine_spi_obj[0]}, - {{&machine_hard_spi_type}, &machine_spi_obj[1]}, -#if NRF52 - {{&machine_hard_spi_type}, &machine_spi_obj[2]}, -#if NRF52840_XXAA - {{&machine_hard_spi_type}, &machine_spi_obj[3]}, -#endif -#endif -}; - STATIC void machine_hard_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { machine_hard_spi_obj_t *self = self_in; - spi_print(print, self->pyb->spi, false); + spi_print(print, self->spi, false); } STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) { @@ -272,48 +261,48 @@ STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) { && args[ARG_NEW_mosi].u_obj != MP_OBJ_NULL && args[ARG_NEW_miso].u_obj != MP_OBJ_NULL) { - self->pyb->spi->init.clk_pin = args[ARG_NEW_sck].u_obj; - self->pyb->spi->init.mosi_pin = args[ARG_NEW_mosi].u_obj; - self->pyb->spi->init.miso_pin = args[ARG_NEW_miso].u_obj; + self->spi->init.clk_pin = args[ARG_NEW_sck].u_obj; + self->spi->init.mosi_pin = args[ARG_NEW_mosi].u_obj; + self->spi->init.miso_pin = args[ARG_NEW_miso].u_obj; } else { - self->pyb->spi->init.clk_pin = &MICROPY_HW_SPI0_SCK; - self->pyb->spi->init.mosi_pin = &MICROPY_HW_SPI0_MOSI; - self->pyb->spi->init.miso_pin = &MICROPY_HW_SPI0_MISO; + self->spi->init.clk_pin = &MICROPY_HW_SPI0_SCK; + self->spi->init.mosi_pin = &MICROPY_HW_SPI0_MOSI; + self->spi->init.miso_pin = &MICROPY_HW_SPI0_MISO; } int baudrate = args[ARG_NEW_baudrate].u_int; if (baudrate <= 125000) { - self->pyb->spi->init.freq = HAL_SPI_FREQ_125_Kbps; + self->spi->init.freq = HAL_SPI_FREQ_125_Kbps; } else if (baudrate <= 250000) { - self->pyb->spi->init.freq = HAL_SPI_FREQ_250_Kbps; + self->spi->init.freq = HAL_SPI_FREQ_250_Kbps; } else if (baudrate <= 500000) { - self->pyb->spi->init.freq = HAL_SPI_FREQ_500_Kbps; + self->spi->init.freq = HAL_SPI_FREQ_500_Kbps; } else if (baudrate <= 1000000) { - self->pyb->spi->init.freq = HAL_SPI_FREQ_1_Mbps; + self->spi->init.freq = HAL_SPI_FREQ_1_Mbps; } else if (baudrate <= 2000000) { - self->pyb->spi->init.freq = HAL_SPI_FREQ_2_Mbps; + self->spi->init.freq = HAL_SPI_FREQ_2_Mbps; } else if (baudrate <= 4000000) { - self->pyb->spi->init.freq = HAL_SPI_FREQ_4_Mbps; + self->spi->init.freq = HAL_SPI_FREQ_4_Mbps; } else if (baudrate <= 8000000) { - self->pyb->spi->init.freq = HAL_SPI_FREQ_8_Mbps; + self->spi->init.freq = HAL_SPI_FREQ_8_Mbps; #if NRF52840_XXAA } else if (baudrate <= 16000000) { - self->pyb->spi->init.freq = HAL_SPI_FREQ_16_Mbps; + self->spi->init.freq = HAL_SPI_FREQ_16_Mbps; } else if (baudrate <= 32000000) { - self->pyb->spi->init.freq = HAL_SPI_FREQ_32_Mbps; + self->spi->init.freq = HAL_SPI_FREQ_32_Mbps; #endif } else { // Default - self->pyb->spi->init.freq = HAL_SPI_FREQ_1_Mbps; + self->spi->init.freq = HAL_SPI_FREQ_1_Mbps; } #ifdef NRF51 - self->pyb->spi->init.irq_priority = 3; + self->spi->init.irq_priority = 3; #else - self->pyb->spi->init.irq_priority = 6; + self->spi->init.irq_priority = 6; #endif - self->pyb->spi->init.mode = HAL_SPI_MODE_CPOL0_CPHA0; - self->pyb->spi->init.firstbit = (args[ARG_NEW_firstbit].u_int == 0) ? HAL_SPI_MSB_FIRST : HAL_SPI_LSB_FIRST;; - hal_spi_master_init(self->pyb->spi->instance, &self->pyb->spi->init); + self->spi->init.mode = HAL_SPI_MODE_CPOL0_CPHA0; + self->spi->init.firstbit = (args[ARG_NEW_firstbit].u_int == 0) ? HAL_SPI_MSB_FIRST : HAL_SPI_LSB_FIRST;; + hal_spi_master_init(self->spi->instance, &self->spi->init); return MP_OBJ_FROM_PTR(self); } @@ -323,12 +312,12 @@ STATIC void machine_hard_spi_init(mp_obj_t self_in, mp_arg_val_t *args) { STATIC void machine_hard_spi_deinit(mp_obj_t self_in) { machine_hard_spi_obj_t *self = self_in; - spi_deinit(self->pyb->spi); + spi_deinit(self->spi); } STATIC void machine_hard_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8_t *src, uint8_t *dest) { machine_hard_spi_obj_t *self = (machine_hard_spi_obj_t*)self_in; - spi_transfer(self->pyb, len, src, dest); + spi_transfer(self, len, src, dest); } diff --git a/nrf5/modules/machine/spi.h b/nrf5/modules/machine/spi.h index 58d683c19c..65373b4040 100644 --- a/nrf5/modules/machine/spi.h +++ b/nrf5/modules/machine/spi.h @@ -28,14 +28,9 @@ #include "hal_spi.h" -typedef struct _pyb_spi_obj_t { - mp_obj_base_t base; - SPI_HandleTypeDef *spi; -} pyb_spi_obj_t; - typedef struct _machine_hard_spi_obj_t { mp_obj_base_t base; - const pyb_spi_obj_t *pyb; + SPI_HandleTypeDef *spi; } machine_hard_spi_obj_t; extern const mp_obj_type_t machine_hard_spi_type; From 5fb937f1473bfc4a8a1572f0882dfc31e1f8b3e5 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 28 May 2017 21:08:56 +0200 Subject: [PATCH 733/809] nrf5/modules/pin: Adding on() and off() methods to Pin object to be forward compatible with upstream master. Legacy high() and low() methods are kept. --- nrf5/modules/machine/pin.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/nrf5/modules/machine/pin.c b/nrf5/modules/machine/pin.c index 5dfaa296a1..472a720d90 100644 --- a/nrf5/modules/machine/pin.c +++ b/nrf5/modules/machine/pin.c @@ -284,6 +284,20 @@ STATIC mp_obj_t pin_call(mp_obj_t self_in, mp_uint_t n_args, mp_uint_t n_kw, con } } +STATIC mp_obj_t pin_off(mp_obj_t self_in) { + pin_obj_t *self = self_in; + mp_hal_pin_low(self); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_off_obj, pin_off); + +STATIC mp_obj_t pin_on(mp_obj_t self_in) { + pin_obj_t *self = self_in; + mp_hal_pin_high(self); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_on_obj, pin_on); + /// \classmethod mapper([fun]) /// Get or set the pin mapper function. STATIC mp_obj_t pin_mapper(mp_uint_t n_args, const mp_obj_t *args) { @@ -505,6 +519,8 @@ STATIC const mp_rom_map_elem_t pin_locals_dict_table[] = { // instance methods { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pin_init_obj) }, { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&pin_value_obj) }, + { MP_ROM_QSTR(MP_QSTR_off), MP_ROM_PTR(&pin_off_obj) }, + { MP_ROM_QSTR(MP_QSTR_on), MP_ROM_PTR(&pin_on_obj) }, { MP_ROM_QSTR(MP_QSTR_low), MP_ROM_PTR(&pin_low_obj) }, { MP_ROM_QSTR(MP_QSTR_high), MP_ROM_PTR(&pin_high_obj) }, { MP_ROM_QSTR(MP_QSTR_name), MP_ROM_PTR(&pin_name_obj) }, From 95b01db098ff40ab517c7dd53d418c79076830d1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 28 May 2017 22:41:34 +0200 Subject: [PATCH 734/809] nrf5/examples: Updating documentation in SDCard module example. Correcting typo and adding SD card wireing documentation for direct SPI connection. --- nrf5/examples/sdcard.py | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/nrf5/examples/sdcard.py b/nrf5/examples/sdcard.py index 953c486a46..91cb79fbb2 100644 --- a/nrf5/examples/sdcard.py +++ b/nrf5/examples/sdcard.py @@ -22,10 +22,25 @@ Example usage on ESP8266: Example usage on NRF52832: import os, machine, sdcard - sd = sdcard.SDCard(machine.SPI(0), machine.PIN("A22", mode=machine.Pin.OUT)) + sd = sdcard.SDCard(machine.SPI(0), machine.Pin("A22", mode=machine.Pin.OUT)) os.mount(sd, "") os.listdir() +Direct wireing on SD card (SPI): +# ______________________________ +# | \ +# | 9. | NC | \ +# | 1. | ~CS | | +# | 2. | MOSI | | +# | 3. | GND | | +# | 4. | VCC3.3| | +# | 5. | SCK | | +# | 6. | GND | | +# | 7. | MISO | | +# | 8. | NC | | +# | | +# --------------------------------- + """ import time From 7dac28575d71eff9c82df54bef2a3e8efd44df54 Mon Sep 17 00:00:00 2001 From: Matt Trentini Date: Mon, 29 May 2017 13:20:46 +1000 Subject: [PATCH 735/809] Adding a README for the nRF5 port --- nrf5/README.md | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 nrf5/README.md diff --git a/nrf5/README.md b/nrf5/README.md new file mode 100644 index 0000000000..a7bbc011cf --- /dev/null +++ b/nrf5/README.md @@ -0,0 +1,46 @@ +# MicroPython port to the NRF5 + +This is a port of MicroPython to the Nordic nRF5 series of chips. + +## Supported features + +* UART +* SPI +* LEDs +* Pins +* ADC +* I2C +* PWM (nRF52 only) +* Temperature +* RTC +* Some BLE support including _REPL over BLE_ + +Note that this port is still a work-in-progress and some modules are not fully feature complete. + +## Tested hardware +* nRF51 +* nRF52 + * [PCA10040](http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52%2Fdita%2Fnrf52%2Fdevelopment%2Fnrf52_dev_kit.html) + * [D52Q](https://www.dynastream.com/components/d52) + * [Adafruit Feather nRF52](https://www.adafruit.com/product/3406) + +## Build steps + +Example is for the Adafruit Feather nRF52: + +``` +> sudo apt-get install build-essential libffi-dev pkg-config gcc-arm-none-eabi git python python-pip +> git clone https://github.com/adafruit/Adafruit_nRF52_Arduino.git +> cd Adafruit_nRF52_Arduino/tools/nrfutil-0.5.2/ +> sudo pip install -r requirements.txt +> sudo python setup.py install +> cd ../../.. +> git clone https://github.com/tralamazza/micropython.git nrf5_no_sdk +> cd nrf5_no_sdk/ +> git submodule update --init +> make -C mpy-cross +> cd nrf5/ +> make BOARD=feather52 +> make BOARD=feather52 dfu-gen +> make BOARD=feather52 dfu-flash +``` \ No newline at end of file From 8b9f14244dd1a8856d6d24b3e0af9bdf68bb1202 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 29 May 2017 00:54:47 +0200 Subject: [PATCH 736/809] nrf5/examples: Removing seeed.py which used a lcd mono framebuffer has been removed. --- nrf5/examples/seeed.py | 215 ----------------------------------------- 1 file changed, 215 deletions(-) delete mode 100644 nrf5/examples/seeed.py diff --git a/nrf5/examples/seeed.py b/nrf5/examples/seeed.py deleted file mode 100644 index 7c73087ef9..0000000000 --- a/nrf5/examples/seeed.py +++ /dev/null @@ -1,215 +0,0 @@ -# This file is part of the Micro Python project, http://micropython.org/ -# -# The MIT License (MIT) -# -# Copyright (c) 2016 Glenn Ruben Bakke -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -# THE SOFTWARE. - -""" -MicroPython Seeedstudio TFT Shield V2 driver, SPI interfaces, Analog GPIO -Contains SD-card reader, LCD and Touch sensor - -Example usage of LCD: - - from seeed import ILI9341 - - lcd = ILI9341(320, 240, False) # Horizontal view - lcd.text("Hello World!, 32, 32) - lcd.show() - -Example usage of SD card reader: - - import os - from seeedstudio_tft_shield_v2 import mount_tf - - tf = mount_tf() - os.listdir() -""" -import os -import time -import lcd_mono_fb - -from machine import SPI, Pin -from sdcard import SDCard - -def mount_tf(self, mount_point="/"): - sd = SDCard(SPI(0), Pin("A15", mode=Pin.OUT)) - os.mount(sd, mount_point) - -class ILI9341: - def __init__(self, width=240, height=320, vertical=True): - self.width = width - self.height = height - self.vertical = vertical - self.framebuf = lcd_mono_fb.MonoFB(self.line_update, self.width, self.height) - - self.spi = SPI(0) - # chip select - self.cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP) - # command - self.dc = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP) - - # initialize all pins high - self.cs.high() - self.dc.high() - - self.spi.init(baudrate=8000000, phase=0, polarity=0) - - self.init_display() - - def line_update(self, o, line, bytes): - if self.vertical: - # set col - self.write_cmd(0x2A) - self.write_data(bytearray([0x00, 0x00, 0x00, 0xEF])) - - # set page - self.write_cmd(0x2B) - self.write_data(bytearray([line >> 8, line & 0xFF, line >> 8, line & 0xFF])) - else: - # set col - self.write_cmd(0x2A) - self.write_data(bytearray([0x00, 0x00, 0x01, 0x3F])) - - # set page - self.write_cmd(0x2B) - self.write_data(bytearray([line >> 8, line & 0xFF, line >> 8, line & 0xFF])) - - self.write_cmd(0x2c); - - for compressed_pixel in bytes: - for pixel_pos in range(0, 8): - if ((compressed_pixel >> pixel_pos) & 0x1) == 0: - self.write_data(bytearray([0x00, 0x00])) - else: - self.write_data(bytearray([0xFF, 0xFF])) - - def init_display(self): - time.sleep_ms(500) - - self.write_cmd(0x01) - - time.sleep_ms(200) - - self.write_cmd(0xCF) - self.write_data(bytearray([0x00, 0x8B, 0x30])) - - self.write_cmd(0xED) - self.write_data(bytearray([0x67, 0x03, 0x12, 0x81])) - - self.write_cmd(0xE8) - self.write_data(bytearray([0x85, 0x10, 0x7A])) - - self.write_cmd(0xCB) - self.write_data(bytearray([0x39, 0x2C, 0x00, 0x34, 0x02])) - - self.write_cmd(0xF7) - self.write_data(bytearray([0x20])) - - self.write_cmd(0xEA) - self.write_data(bytearray([0x00, 0x00])) - - # Power control - self.write_cmd(0xC0) - # VRH[5:0] - self.write_data(bytearray([0x1B])) - - # Power control - self.write_cmd(0xC1) - # SAP[2:0];BT[3:0] - self.write_data(bytearray([0x10])) - - # VCM control - self.write_cmd(0xC5) - self.write_data(bytearray([0x3F, 0x3C])) - - # VCM control2 - self.write_cmd(0xC7) - self.write_data(bytearray([0xB7])) - - # Memory Access Control - self.write_cmd(0x36) - if self.vertical: - self.write_data(bytearray([0x08])) - else: - self.write_data(bytearray([0x08 | (0x4 | 0x1) << 5])) - - self.write_cmd(0x3A) - self.write_data(bytearray([0x55])) - - self.write_cmd(0xB1) - self.write_data(bytearray([0x00, 0x1B])) - - # Display Function Control - self.write_cmd(0xB6) - self.write_data(bytearray([0x0A, 0xA2])) - - # 3Gamma Function Disable - self.write_cmd(0xF2) - self.write_data(bytearray([0x00])) - - # Gamma curve selected - self.write_cmd(0x26) - self.write_data(bytearray([0x01])) - - # Set Gamma - self.write_cmd(0xE0) - self.write_data(bytearray([0x0F, 0x2A, 0x28, 0x08, 0x0E, 0x08, 0x54, 0XA9, 0x43, 0x0A, 0x0F, 0x00, 0x00, 0x00, 0x00])) - - # Set Gamma - self.write_cmd(0XE1) - self.write_data(bytearray([0x00, 0x15, 0x17, 0x07, 0x11, 0x06, 0x2B, 0x56, 0x3C, 0x05, 0x10, 0x0F, 0x3F, 0x3F, 0x0F])) - - # Exit Sleep - self.write_cmd(0x11) - time.sleep_ms(120) - - # Display on - self.write_cmd(0x29) - time.sleep_ms(500) - self.fill(0) - - def show(self): - self.framebuf.show() - - def fill(self, col): - self.framebuf.fill(col) - - def pixel(self, x, y, col): - self.framebuf.pixel(x, y, col) - - def scroll(self, dx, dy): - self.framebuf.scroll(dx, dy) - - def text(self, string, x, y, col=1): - self.framebuf.text(string, x, y, col) - - def write_cmd(self, cmd): - self.dc.low() - self.cs.low() - self.spi.write(bytearray([cmd])) - self.cs.high() - - def write_data(self, buf): - self.dc.high() - self.cs.low() - self.spi.write(buf) - self.cs.high() - From 0bce2ea74acde09d1f659ee5ff6a85a4205542a0 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 29 May 2017 23:03:31 +0200 Subject: [PATCH 737/809] nrf5/examples: Updating ili9341 example to use new Frambuffer object instead of legacy Framebuffer1. --- nrf5/examples/seeedstudio_tft_shield_v2.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/examples/seeedstudio_tft_shield_v2.py b/nrf5/examples/seeedstudio_tft_shield_v2.py index 95f66ed742..0620f8661b 100644 --- a/nrf5/examples/seeedstudio_tft_shield_v2.py +++ b/nrf5/examples/seeedstudio_tft_shield_v2.py @@ -59,7 +59,7 @@ class ILI9341: self.height = height self.pages = self.height // 8 self.buffer = bytearray(self.pages * self.width) - self.framebuf = framebuf.FrameBuffer1(self.buffer, self.width, self.height) + self.framebuf = framebuf.FrameBuffer(self.buffer, self.width, self.height, framebuf.MONO_VLSB) self.spi = SPI(0) # chip select From 94b94d7ff4bff93b30926b426668bc3d2b15648e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 29 May 2017 23:04:33 +0200 Subject: [PATCH 738/809] nrf5/examples: Shorten name on seeedstudio_tft_shield_v2.py to seeed_tft.py. --- nrf5/examples/{seeedstudio_tft_shield_v2.py => seeed_tft.py} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename nrf5/examples/{seeedstudio_tft_shield_v2.py => seeed_tft.py} (100%) diff --git a/nrf5/examples/seeedstudio_tft_shield_v2.py b/nrf5/examples/seeed_tft.py similarity index 100% rename from nrf5/examples/seeedstudio_tft_shield_v2.py rename to nrf5/examples/seeed_tft.py From e07088ce23e317ffa2255db4dadea00d6140ad15 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 29 May 2017 23:07:44 +0200 Subject: [PATCH 739/809] nrf5/examples: Adding some notes on which pin layout that has been used in the seeed_tft.py ILI9341 driver for driving the display. --- nrf5/examples/seeed_tft.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/examples/seeed_tft.py b/nrf5/examples/seeed_tft.py index 0620f8661b..4e5db06fcb 100644 --- a/nrf5/examples/seeed_tft.py +++ b/nrf5/examples/seeed_tft.py @@ -26,6 +26,8 @@ MicroPython Seeedstudio TFT Shield V2 driver, SPI interfaces, Analog GPIO Contains SD-card reader, LCD and Touch sensor +The pca10040 pin layout is used as reference. + Example usage of LCD: from seeedstudio_tft_shield_v2 import ILI9341 From 66db0791927daf63b8b68da9b5851bf72a5c7024 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 30 May 2017 19:29:46 +0200 Subject: [PATCH 740/809] nrf5/drivers/bluetooth: Updating ble_drv_attr_c_write with possibility to do client write with response. Blocking call. --- nrf5/drivers/bluetooth/ble_drv.c | 36 ++++++++++++++++++++++---------- nrf5/drivers/bluetooth/ble_drv.h | 2 +- 2 files changed, 26 insertions(+), 12 deletions(-) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index 418c1f4a3f..52009b3eac 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -77,6 +77,7 @@ static mp_obj_t mp_gatts_observer; #if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132) static volatile bool m_primary_service_found; static volatile bool m_characteristic_found; +static volatile bool m_write_done; static volatile ble_drv_adv_evt_callback_t adv_event_handler; static volatile ble_drv_gattc_evt_callback_t gattc_event_handler; @@ -89,6 +90,7 @@ static mp_obj_t mp_gattc_observer; static mp_obj_t mp_gattc_disc_service_observer; static mp_obj_t mp_gattc_disc_char_observer; static mp_obj_t mp_gattc_char_data_observer; +static mp_obj_t mp_gattc_char_data_observer; #endif #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) @@ -679,23 +681,34 @@ void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, bl } } -void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) { +void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data, bool w_response) { - ble_gattc_write_params_t write_params; + ble_gattc_write_params_t write_params; - write_params.write_op = BLE_GATT_OP_WRITE_CMD; - write_params.flags = BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL; - write_params.handle = handle; - write_params.offset = 0; - write_params.len = len; - write_params.p_value = p_data; + if (w_response) { + write_params.write_op = BLE_GATT_OP_WRITE_REQ; + } else { + write_params.write_op = BLE_GATT_OP_WRITE_CMD; + } - uint32_t err_code = sd_ble_gattc_write(conn_handle, &write_params); + write_params.flags = BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL; + write_params.handle = handle; + write_params.offset = 0; + write_params.len = len; + write_params.p_value = p_data; - if (err_code != 0) { + uint32_t err_code = sd_ble_gattc_write(conn_handle, &write_params); + + m_write_done = !w_response; + + if (err_code != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not write attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); - } + } + + while (m_write_done != true) { + ; + } } void ble_drv_scan_start(void) { @@ -1007,6 +1020,7 @@ static void ble_evt_handler(ble_evt_t * p_ble_evt) { case BLE_GATTC_EVT_WRITE_RSP: BLE_DRIVER_LOG("BLE EVT WRITE RESPONSE\n"); + m_write_done = true; break; case BLE_GATTC_EVT_HVX: diff --git a/nrf5/drivers/bluetooth/ble_drv.h b/nrf5/drivers/bluetooth/ble_drv.h index dc3cf168ef..e038f5cc96 100644 --- a/nrf5/drivers/bluetooth/ble_drv.h +++ b/nrf5/drivers/bluetooth/ble_drv.h @@ -104,7 +104,7 @@ void ble_drv_attr_s_write(uint16_t conn_handle, uint16_t handle, uint16_t len, u void ble_drv_attr_s_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); -void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data); +void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data, bool w_response); void ble_drv_scan_start(void); From 1eb8792fa54fe9e7d06dd0043475771558d25d3a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 30 May 2017 19:32:26 +0200 Subject: [PATCH 741/809] nrf5/modules/ubluepy: Updating characteristic write method to take in an additional keyword, 'with_response'. Default value is False. Only activated in central role. --- nrf5/modules/ubluepy/ubluepy_characteristic.c | 23 ++++++++++++++----- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf5/modules/ubluepy/ubluepy_characteristic.c index 18b58809f3..ea3f9b29e5 100644 --- a/nrf5/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf5/modules/ubluepy/ubluepy_characteristic.c @@ -111,11 +111,20 @@ STATIC mp_obj_t char_read(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_read_obj, char_read); -/// \method write(data) +/// \method write(data, [with_response=False]) /// Write Characteristic value. /// -STATIC mp_obj_t char_write(mp_obj_t self_in, mp_obj_t data) { - ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in); +STATIC mp_obj_t char_write(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + ubluepy_characteristic_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + mp_obj_t data = pos_args[1]; + + static const mp_arg_t allowed_args[] = { + { MP_QSTR_with_response, MP_ARG_KW_ONLY | MP_ARG_BOOL, {.u_bool = false } }, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 2, pos_args + 2, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); mp_buffer_info_t bufinfo; mp_get_buffer_raise(data, &bufinfo, MP_BUFFER_READ); @@ -137,16 +146,18 @@ STATIC mp_obj_t char_write(mp_obj_t self_in, mp_obj_t data) { } } else { #if MICROPY_PY_UBLUEPY_CENTRAL + bool with_response = args[0].u_bool; + ble_drv_attr_c_write(self->p_service->p_periph->conn_handle, self->handle, bufinfo.len, - bufinfo.buf); + bufinfo.buf, + with_response); #endif } return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_characteristic_write_obj, char_write); - +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(ubluepy_characteristic_write_obj, 2, char_write); /// \method properties() /// Read Characteristic value properties. From b17665b8adf3eae47be29f2046a52c233d5ec249 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 30 May 2017 23:19:34 +0200 Subject: [PATCH 742/809] nrf5/drivers/bluetooth: Removing duplicate static variable declaration. --- nrf5/drivers/bluetooth/ble_drv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index 52009b3eac..b1670d0354 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -90,7 +90,6 @@ static mp_obj_t mp_gattc_observer; static mp_obj_t mp_gattc_disc_service_observer; static mp_obj_t mp_gattc_disc_char_observer; static mp_obj_t mp_gattc_char_data_observer; -static mp_obj_t mp_gattc_char_data_observer; #endif #if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110) From a81de242c560aa8cf871b43b32efb5afff04baaa Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 30 May 2017 23:23:31 +0200 Subject: [PATCH 743/809] nrf5/drivers/bluetooth: Moving stop condition initialization before call to bluetooth stack write function is done, to make sure that its not overwritten after reception of the write event in case of with_response writes. --- nrf5/drivers/bluetooth/ble_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf5/drivers/bluetooth/ble_drv.c index b1670d0354..8d3348f5fc 100644 --- a/nrf5/drivers/bluetooth/ble_drv.c +++ b/nrf5/drivers/bluetooth/ble_drv.c @@ -696,10 +696,10 @@ void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, u write_params.len = len; write_params.p_value = p_data; - uint32_t err_code = sd_ble_gattc_write(conn_handle, &write_params); - m_write_done = !w_response; + uint32_t err_code = sd_ble_gattc_write(conn_handle, &write_params); + if (err_code != 0) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Can not write attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code)); From 147e579e28eea4c3bfee13212e0d1038f2b50b20 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 1 Jun 2017 22:58:24 +0200 Subject: [PATCH 744/809] nrf5/hal/rtc: Aligning RTC (real-time counter) HAL driver with Timer HAL driver. To make api's symetric. Also updating modules/rtc to get aligned with new HAL api. --- nrf5/hal/hal_rtc.c | 85 +++++++++++++------------- nrf5/hal/hal_rtc.h | 55 +++++++---------- nrf5/modules/machine/rtc.c | 119 +++++++++++-------------------------- 3 files changed, 101 insertions(+), 158 deletions(-) diff --git a/nrf5/hal/hal_rtc.c b/nrf5/hal/hal_rtc.c index d539d78c48..bd3905bb4f 100644 --- a/nrf5/hal/hal_rtc.c +++ b/nrf5/hal/hal_rtc.c @@ -32,13 +32,14 @@ static hal_rtc_app_callback m_callback; +static uint32_t m_period[sizeof(RTC_BASE_POINTERS) / sizeof(uint32_t)]; + void hal_rtc_callback_set(hal_rtc_app_callback callback) { m_callback = callback; } void hal_rtc_init(hal_rtc_conf_t const * p_rtc_conf) { - p_rtc_conf->p_instance->PRESCALER = (32768 / p_rtc_conf->frequency) - 1; // approx correct. - hal_irq_priority(p_rtc_conf->irq_num, p_rtc_conf->irq_priority); + NRF_RTC_Type * p_rtc = RTC_BASE(p_rtc_conf->id); // start LFCLK if not already started if (NRF_CLOCK->LFCLKSTAT == 0) { @@ -46,70 +47,70 @@ void hal_rtc_init(hal_rtc_conf_t const * p_rtc_conf) { while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0); NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; } + + m_period[p_rtc_conf->id] = p_rtc_conf->period; + + p_rtc->PRESCALER = (32768 / 32) - 1; // approx ms ticks. + hal_irq_priority(RTC_IRQ_NUM(p_rtc_conf->id), p_rtc_conf->irq_priority); } -void hal_rtc_start(hal_rtc_conf_t const * p_rtc_conf, uint16_t period) { - uint32_t counter = p_rtc_conf->p_instance->COUNTER; +void hal_rtc_start(uint8_t id) { + NRF_RTC_Type * p_rtc = RTC_BASE(id); - p_rtc_conf->p_instance->CC[0] = counter + period; + uint32_t period = m_period[id]; + uint32_t counter = p_rtc->COUNTER; - p_rtc_conf->p_instance->EVTENSET = RTC_EVTEN_COMPARE0_Msk; - p_rtc_conf->p_instance->INTENSET = RTC_INTENSET_COMPARE0_Msk; + p_rtc->CC[0] = counter + period; - hal_irq_clear(p_rtc_conf->irq_num); - hal_irq_enable(p_rtc_conf->irq_num); + p_rtc->EVTENSET = RTC_EVTEN_COMPARE0_Msk; + p_rtc->INTENSET = RTC_INTENSET_COMPARE0_Msk; - p_rtc_conf->p_instance->TASKS_START = 1; + hal_irq_clear(RTC_IRQ_NUM(id)); + hal_irq_enable(RTC_IRQ_NUM(id)); + + p_rtc->TASKS_START = 1; } -void hal_rtc_stop(hal_rtc_conf_t const * p_rtc_conf) { - p_rtc_conf->p_instance->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; - p_rtc_conf->p_instance->INTENCLR = RTC_INTENSET_COMPARE0_Msk; +void hal_rtc_stop(uint8_t id) { + NRF_RTC_Type * p_rtc = RTC_BASE(id); - hal_irq_disable(p_rtc_conf->irq_num); + p_rtc->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; + p_rtc->INTENCLR = RTC_INTENSET_COMPARE0_Msk; - p_rtc_conf->p_instance->TASKS_STOP = 1; + hal_irq_disable(RTC_IRQ_NUM(id)); + + p_rtc->TASKS_STOP = 1; +} + +static void common_irq_handler(uint8_t id) { + NRF_RTC_Type * p_rtc = RTC_BASE(id); + + // clear all events + p_rtc->EVENTS_COMPARE[0] = 0; + p_rtc->EVENTS_COMPARE[1] = 0; + p_rtc->EVENTS_COMPARE[2] = 0; + p_rtc->EVENTS_COMPARE[3] = 0; + p_rtc->EVENTS_TICK = 0; + p_rtc->EVENTS_OVRFLW = 0; + + m_callback(id); } void RTC0_IRQHandler(void) { - // clear all events - NRF_RTC0->EVENTS_COMPARE[0] = 0; - NRF_RTC0->EVENTS_COMPARE[1] = 0; - NRF_RTC0->EVENTS_COMPARE[2] = 0; - NRF_RTC0->EVENTS_COMPARE[3] = 0; - NRF_RTC0->EVENTS_TICK = 0; - NRF_RTC0->EVENTS_OVRFLW = 0; - - m_callback(NRF_RTC0); + common_irq_handler(0); } void RTC1_IRQHandler(void) { - // clear all events - NRF_RTC1->EVENTS_COMPARE[0] = 0; - NRF_RTC1->EVENTS_COMPARE[1] = 0; - NRF_RTC1->EVENTS_COMPARE[2] = 0; - NRF_RTC1->EVENTS_COMPARE[3] = 0; - NRF_RTC1->EVENTS_TICK = 0; - NRF_RTC1->EVENTS_OVRFLW = 0; - - m_callback(NRF_RTC1); + common_irq_handler(1); } #if NRF52 void RTC2_IRQHandler(void) { - // clear all events - NRF_RTC2->EVENTS_COMPARE[0] = 0; - NRF_RTC2->EVENTS_COMPARE[1] = 0; - NRF_RTC2->EVENTS_COMPARE[2] = 0; - NRF_RTC2->EVENTS_COMPARE[3] = 0; - NRF_RTC2->EVENTS_TICK = 0; - NRF_RTC2->EVENTS_OVRFLW = 0; - - m_callback(NRF_RTC2); + common_irq_handler(2); } #endif // NRF52 diff --git a/nrf5/hal/hal_rtc.h b/nrf5/hal/hal_rtc.h index 16ef2f7ed2..81797bfb55 100644 --- a/nrf5/hal/hal_rtc.h +++ b/nrf5/hal/hal_rtc.h @@ -30,52 +30,41 @@ #include "nrf.h" #if NRF51 - -#define RTC0 ((NRF_RTC_Type *) NRF_RTC0) -#define RTC0_IRQ_NUM RTC0_IRQn -#define RTC1 ((NRF_RTC_Type *) NRF_RTC1) -#define RTC1_IRQ_NUM RTC1_IRQn - -#elif NRF52 - -#define RTC0 ((NRF_RTC_Type *) NRF_RTC0) -#define RTC0_IRQ_NUM RTC0_IRQn -#define RTC1 ((NRF_RTC_Type *) NRF_RTC1) -#define RTC1_IRQ_NUM RTC1_IRQn -#define RTC2 ((NRF_RTC_Type *) NRF_RTC2) -#define RTC2_IRQ_NUM RTC2_IRQn - -#else -#error "Device not supported." + #define RTC_BASE_POINTERS (const uint32_t[]){NRF_RTC0_BASE, \ + NRF_RTC1_BASE} + #define RTC_IRQ_VALUES (const uint32_t[]){RTC0_IRQn, \ + RTC1_IRQn} #endif -typedef void (*hal_rtc_app_callback)(NRF_RTC_Type * p_instance); +#if NRF52 + #define RTC_BASE_POINTERS (const uint32_t[]){NRF_RTC0_BASE, \ + NRF_RTC1_BASE, \ + NRF_RTC2_BASE} + #define RTC_IRQ_VALUES (const uint32_t[]){RTC0_IRQn, \ + RTC1_IRQn, \ + RTC2_IRQn} +#endif + +#define RTC_BASE(x) ((NRF_RTC_Type *)RTC_BASE_POINTERS[x]) +#define RTC_IRQ_NUM(x) (RTC_IRQ_VALUES[x]) + +typedef void (*hal_rtc_app_callback)(uint8_t id); /** * @brief RTC Configuration Structure definition */ typedef struct { - NRF_RTC_Type * p_instance; /* RTC registers base address */ - uint32_t irq_num; /* RTC IRQ num */ - uint32_t irq_priority; /* RTC IRQ priority */ - uint16_t frequency; /* RTC frequency in Hz */ + uint8_t id; /* RTC instance id */ + uint32_t period; /* RTC period in ms */ + uint32_t irq_priority; /* RTC IRQ priority */ } hal_rtc_conf_t; -/** - * @brief RTC handle Structure definition - */ -typedef struct __RTC_HandleTypeDef -{ - uint8_t id; /* RTC instance id */ - hal_rtc_conf_t config; /* RTC config */ -} RTC_HandleTypeDef; - void hal_rtc_callback_set(hal_rtc_app_callback callback); void hal_rtc_init(hal_rtc_conf_t const * p_rtc_config); -void hal_rtc_start(hal_rtc_conf_t const * p_rtc_conf, uint16_t period); +void hal_rtc_start(uint8_t id); -void hal_rtc_stop(hal_rtc_conf_t const * p_rtc_conf); +void hal_rtc_stop(uint8_t id); #endif // HAL_RTC_H__ diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index 2fdc32fe87..ca4b575d1e 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -36,73 +36,49 @@ #if MICROPY_PY_MACHINE_RTC typedef struct _machine_rtc_obj_t { - mp_obj_base_t base; - RTC_HandleTypeDef *rtc; + mp_obj_base_t base; + hal_rtc_conf_t * p_config; mp_obj_t callback; mp_int_t period; mp_int_t mode; } machine_rtc_obj_t; -RTC_HandleTypeDef RTCHandle0 = {.config.p_instance = NULL, .id = 0}; -RTC_HandleTypeDef RTCHandle1 = {.config.p_instance = NULL, .id = 1}; - -STATIC machine_rtc_obj_t machine_rtc_obj[] = { - {{&machine_rtc_type}, &RTCHandle0}, - {{&machine_rtc_type}, &RTCHandle1}, -}; - -STATIC void hal_interrupt_handle(NRF_RTC_Type * p_instance) { - const machine_rtc_obj_t * self = NULL; - if (p_instance == RTC0) { - self = &machine_rtc_obj[0]; - mp_call_function_0(self->callback); - } else if (p_instance == RTC1) { - self = &machine_rtc_obj[1]; - mp_call_function_0(self->callback); - } +static hal_rtc_conf_t rtc_config0 = {.id = 0}; +static hal_rtc_conf_t rtc_config1 = {.id = 1}; #if NRF52 - else if (p_instance == RTC2) { - self = &machine_rtc_obj[2]; - mp_call_function_0(self->callback); - } +static hal_rtc_conf_t rtc_config2 = {.id = 2}; #endif +STATIC machine_rtc_obj_t machine_rtc_obj[] = { + {{&machine_rtc_type}, &rtc_config0}, + {{&machine_rtc_type}, &rtc_config1}, +#if NRF52 + {{&machine_rtc_type}, &rtc_config2}, +#endif +}; + +STATIC void hal_interrupt_handle(uint8_t id) { + machine_rtc_obj_t * self = &machine_rtc_obj[id];; + + mp_call_function_1(self->callback, self); + if (self != NULL) { - hal_rtc_stop(&self->rtc->config); + hal_rtc_stop(id); if (self->mode == 1) { - hal_rtc_start(&self->rtc->config, self->period); + hal_rtc_start(id); } } } void rtc_init0(void) { - hal_rtc_callback_set(hal_interrupt_handle); - - // reset the RTC handles - memset(&RTCHandle0, 0, sizeof(RTC_HandleTypeDef)); - RTCHandle0.config.p_instance = RTC0; - RTCHandle0.config.irq_num = RTC0_IRQ_NUM; -#if (BLUETOOTH_SD == 100) - RTCHandle0.config.irq_priority = 3; -#else - RTCHandle0.config.irq_priority = 6; -#endif - memset(&RTCHandle1, 0, sizeof(RTC_HandleTypeDef)); - RTCHandle1.config.p_instance = RTC1; - RTCHandle1.config.irq_num = RTC1_IRQ_NUM; -#if (BLUETOOTH_SD == 100) - RTCHandle1.config.irq_priority = 3; -#else - RTCHandle1.config.irq_priority = 6; -#endif } STATIC int rtc_find(mp_obj_t id) { // given an integer id int rtc_id = mp_obj_get_int(id); if (rtc_id >= 0 && rtc_id <= MP_ARRAY_SIZE(machine_rtc_obj) - && machine_rtc_obj[rtc_id].rtc != NULL) { + && machine_rtc_obj[rtc_id].p_config != NULL) { return rtc_id; } nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, @@ -111,59 +87,39 @@ STATIC int rtc_find(mp_obj_t id) { STATIC void rtc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { machine_rtc_obj_t *self = o; - mp_printf(print, "RTC(%u)", self->rtc->id); + mp_printf(print, "RTC(%u)", self->p_config->id); } /******************************************************************************/ /* MicroPython bindings for machine API */ -/* -from machine import RTC -def cb(): - print("Callback") -r = RTC(0, 8, cb, mode=RTC.PERIODIC) -r.start(16) -*/ - STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { - { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, - { MP_QSTR_frequency, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, - { MP_QSTR_callback, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} }, - { MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + { MP_QSTR_period, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} }, + { MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1} }, + { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, }; // parse args mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - if (args[0].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) { - // index -1 does not exist - return mp_const_none; - // TODO: raise exception - } - // get static peripheral object int rtc_id = rtc_find(args[0].u_obj); // unconst machine object in order to set a callback. machine_rtc_obj_t * self = (machine_rtc_obj_t *)&machine_rtc_obj[rtc_id]; - mp_obj_t freq_obj = args[1].u_obj; + self->p_config->period = args[1].u_int; - if (freq_obj != mp_const_none && MP_OBJ_IS_INT(freq_obj)) { - self->rtc->config.frequency = mp_obj_get_int(freq_obj); - } else { - // raise exception + self->mode = args[2].u_int; + + if (args[3].u_obj != mp_const_none) { + self->callback = args[3].u_obj; } - if (args[2].u_obj != mp_const_none) { - self->callback = args[2].u_obj; - } - - self->mode = args[3].u_int; - - hal_rtc_init(&self->rtc->config); + hal_rtc_init(self->p_config); return MP_OBJ_FROM_PTR(self); } @@ -172,17 +128,14 @@ STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, s /// Start the RTC timer. Timeout occurs after number of periods /// in the configured frequency has been reached. /// -STATIC mp_obj_t machine_rtc_start(mp_obj_t self_in, mp_obj_t period_in) { +STATIC mp_obj_t machine_rtc_start(mp_obj_t self_in) { machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in); - mp_int_t period = mp_obj_get_int(period_in); - self->period = mp_obj_get_int(period_in); - - hal_rtc_start(&self->rtc->config, period); + hal_rtc_start(self->p_config->id); return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_rtc_start_obj, machine_rtc_start); +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_start_obj, machine_rtc_start); /// \method stop() /// Stop the RTC timer. @@ -190,7 +143,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_rtc_start_obj, machine_rtc_start); STATIC mp_obj_t machine_rtc_stop(mp_obj_t self_in) { machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in); - hal_rtc_stop(&self->rtc->config); + hal_rtc_stop(self->p_config->id); return mp_const_none; } From 5cfd6d166cc3d8e2653f5d5470ddffc72f7e8394 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 2 Jun 2017 18:35:04 +0200 Subject: [PATCH 745/809] nrf5/modules/machine: Update rtc init to set default IRQ priority before initializing RTC instance. --- nrf5/modules/machine/rtc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index ca4b575d1e..deadb385ee 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -119,6 +119,12 @@ STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, s self->callback = args[3].u_obj; } +#ifdef NRF51 + self->p_config.irq_priority = 3; +#else + self->p_config.irq_priority = 6; +#endif + hal_rtc_init(self->p_config); return MP_OBJ_FROM_PTR(self); From b785e145d29a5cd39a26fcba13c731e806dbb6fe Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 2 Jun 2017 18:41:13 +0200 Subject: [PATCH 746/809] nrf5/modules/machine: Fixing type in RTC. --- nrf5/modules/machine/rtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf5/modules/machine/rtc.c b/nrf5/modules/machine/rtc.c index deadb385ee..9b5e5601b3 100644 --- a/nrf5/modules/machine/rtc.c +++ b/nrf5/modules/machine/rtc.c @@ -120,9 +120,9 @@ STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, s } #ifdef NRF51 - self->p_config.irq_priority = 3; + self->p_config->irq_priority = 3; #else - self->p_config.irq_priority = 6; + self->p_config->irq_priority = 6; #endif hal_rtc_init(self->p_config); From 45303796d77051e2520a94b01ee6a18da23b27c9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 2 Jun 2017 19:04:19 +0200 Subject: [PATCH 747/809] nrf5/hal/rtc: Updating hal driver to calculate prescaler a bit more verbose. Using 1 second interval ticks. --- nrf5/hal/hal_rtc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/nrf5/hal/hal_rtc.c b/nrf5/hal/hal_rtc.c index bd3905bb4f..d3ea751915 100644 --- a/nrf5/hal/hal_rtc.c +++ b/nrf5/hal/hal_rtc.c @@ -30,6 +30,10 @@ #ifdef HAL_RTC_MODULE_ENABLED +#define HAL_LFCLK_FREQ (32768UL) +#define HAL_RTC_FREQ (10UL) +#define HAL_RTC_COUNTER_PRESCALER ((HAL_LFCLK_FREQ/HAL_RTC_FREQ)-1) + static hal_rtc_app_callback m_callback; static uint32_t m_period[sizeof(RTC_BASE_POINTERS) / sizeof(uint32_t)]; @@ -50,14 +54,14 @@ void hal_rtc_init(hal_rtc_conf_t const * p_rtc_conf) { m_period[p_rtc_conf->id] = p_rtc_conf->period; - p_rtc->PRESCALER = (32768 / 32) - 1; // approx ms ticks. + p_rtc->PRESCALER = HAL_RTC_COUNTER_PRESCALER; hal_irq_priority(RTC_IRQ_NUM(p_rtc_conf->id), p_rtc_conf->irq_priority); } void hal_rtc_start(uint8_t id) { NRF_RTC_Type * p_rtc = RTC_BASE(id); - uint32_t period = m_period[id]; + uint32_t period = HAL_RTC_FREQ * m_period[id]; uint32_t counter = p_rtc->COUNTER; p_rtc->CC[0] = counter + period; From ad1076b2062835e3f96094156dc277bed2d79169 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 31 May 2017 19:29:29 +0200 Subject: [PATCH 748/809] nrf5/modules/machine: Removing unused code from uart module. --- nrf5/modules/machine/uart.c | 53 ------------------------------------- 1 file changed, 53 deletions(-) diff --git a/nrf5/modules/machine/uart.c b/nrf5/modules/machine/uart.c index 94166508d6..3e7393b61c 100644 --- a/nrf5/modules/machine/uart.c +++ b/nrf5/modules/machine/uart.c @@ -43,9 +43,6 @@ #include "mphalport.h" #include "hal_uart.h" -#define CHAR_WIDTH_8BIT (0) -#define CHAR_WIDTH_9BIT (1) - typedef struct _machine_hard_uart_obj_t { mp_obj_base_t base; UART_HandleTypeDef * uart; @@ -72,11 +69,6 @@ void uart_init0(void) { memset(&UARTHandle1, 0, sizeof(UART_HandleTypeDef)); UARTHandle0.p_instance = UART_BASE(1); #endif -#if 0 - for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) { - MP_STATE_PORT(pyb_uart_obj_all)[i] = NULL; - } -#endif } STATIC int uart_find(mp_obj_t id) { @@ -99,15 +91,6 @@ bool uart_rx_any(machine_hard_uart_obj_t *uart_obj) { return true; } -#if 0 -// Waits at most timeout milliseconds for at least 1 char to become ready for -// reading (from buf or for direct reading). -// Returns true if something available, false if not. -STATIC bool uart_rx_wait(machine_hard_uart_obj_t * self, uint32_t timeout) { - return false; -} -#endif - int uart_rx_char(machine_hard_uart_obj_t * self) { uint8_t ch; hal_uart_char_read(self->uart->p_instance, &ch); @@ -178,33 +161,6 @@ STATIC mp_obj_t machine_hard_uart_make_new(const mp_obj_type_t *type, size_t n_a // flow control init->flow_control = args[5].u_int; -#if 0 - // init UART (if it fails, it's because the port doesn't exist) - if (!uart_init2(self)) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%d) does not exist", self->uart_id)); - } - - // set timeouts - self->timeout = args[6].u_int; - self->timeout_char = args[7].u_int; - - // setup the read buffer - m_del(byte, self->read_buf, self->read_buf_len << self->char_width); - - self->read_buf_head = 0; - self->read_buf_tail = 0; - - if (args[8].u_int <= 0) { - // no read buffer - self->read_buf_len = 0; - self->read_buf = NULL; - } else { - // read buffer using interrupts - self->read_buf_len = args[8].u_int; - self->read_buf = m_new(byte, args[8].u_int << self->char_width); - } - -#endif // 0 #if MICROPY_HW_UART1_HWFC init->flow_control = true; @@ -312,16 +268,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_hard_uart_writechar_obj, machine_hard_u /// Return value: The character read, as an integer. Returns -1 on timeout. STATIC mp_obj_t machine_hard_uart_readchar(mp_obj_t self_in) { machine_hard_uart_obj_t *self = self_in; -#if 0 - if (uart_rx_wait(self, self->timeout)) { -#endif return MP_OBJ_NEW_SMALL_INT(uart_rx_char(self)); -#if 0 - } else { - // return -1 on timeout - return MP_OBJ_NEW_SMALL_INT(-1); - } -#endif } STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_hard_uart_readchar_obj, machine_hard_uart_readchar); From daf34742474bdbaef3b5f97de77bf9ff0b4603ad Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 31 May 2017 19:50:54 +0200 Subject: [PATCH 749/809] nrf5/modules/machine: Indention fix in uart module. --- nrf5/modules/machine/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/machine/uart.c b/nrf5/modules/machine/uart.c index 3e7393b61c..08c03876d8 100644 --- a/nrf5/modules/machine/uart.c +++ b/nrf5/modules/machine/uart.c @@ -268,7 +268,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_hard_uart_writechar_obj, machine_hard_u /// Return value: The character read, as an integer. Returns -1 on timeout. STATIC mp_obj_t machine_hard_uart_readchar(mp_obj_t self_in) { machine_hard_uart_obj_t *self = self_in; - return MP_OBJ_NEW_SMALL_INT(uart_rx_char(self)); + return MP_OBJ_NEW_SMALL_INT(uart_rx_char(self)); } STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_hard_uart_readchar_obj, machine_hard_uart_readchar); From ac7fae2e0ab3ddd3815a343cd72607ccf1e278c7 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 31 May 2017 19:17:02 +0200 Subject: [PATCH 750/809] nrf5: Makefile cleanup. Removing duplicate include and unused netutils.c used by BLE 6lowpan network which has been removed for now. --- nrf5/Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/nrf5/Makefile b/nrf5/Makefile index 1de1354f27..83ed917c52 100644 --- a/nrf5/Makefile +++ b/nrf5/Makefile @@ -46,7 +46,6 @@ MCU_VARIANT_UPPER = $(shell echo $(MCU_VARIANT) | tr '[:lower:]' '[:upper:]') INC += -I. INC += -I.. INC += -I$(BUILD) -INC += -I./device INC += -I./../lib/cmsis/inc INC += -I./device INC += -I./device/$(MCU_VARIANT) @@ -100,7 +99,6 @@ SRC_LIB = $(addprefix lib/,\ timeutils/timeutils.c \ oofatfs/ff.c \ oofatfs/option/unicode.c \ - netutils/netutils.c \ ) SRC_HAL = $(addprefix hal/,\ From f49f20a24ea4badb0850e5977b0a20f6e7ad152a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 31 May 2017 22:25:23 +0200 Subject: [PATCH 751/809] nrf5/hal/timer: Implementing hal_timer to 1us prescaler. Multiplier inside to get to millisecond resolution. Callback must be registered before starting a timer. --- nrf5/hal/hal_timer.c | 47 ++++++++++++++++++++++++++++++++++++++------ nrf5/hal/hal_timer.h | 5 +++++ 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/nrf5/hal/hal_timer.c b/nrf5/hal/hal_timer.c index 715d540288..4a29e847c4 100644 --- a/nrf5/hal/hal_timer.c +++ b/nrf5/hal/hal_timer.c @@ -26,41 +26,76 @@ #include "mphalport.h" #include "hal_timer.h" +#include "hal_irq.h" #ifdef HAL_TIMER_MODULE_ENABLED -void hal_timer_init(hal_timer_conf_t const * p_timer_conf) { +static hal_timer_app_callback m_callback; +void hal_timer_callback_set(hal_timer_app_callback callback) { + m_callback = callback; +} + +void hal_timer_init(hal_timer_conf_t const * p_timer_conf) { + NRF_TIMER_Type * p_timer = TIMER_BASE(p_timer_conf->id); + + p_timer->CC[0] = 1000 * p_timer_conf->period; + p_timer->MODE = TIMER_MODE_MODE_Timer; + p_timer->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos; + p_timer->PRESCALER = 4; // 1 us + p_timer->INTENSET = TIMER_INTENSET_COMPARE0_Msk; + p_timer->SHORTS = (TIMER_SHORTS_COMPARE0_CLEAR_Enabled << TIMER_SHORTS_COMPARE0_CLEAR_Pos); + p_timer->TASKS_CLEAR = 1; + + hal_irq_priority(TIMER_IRQ_NUM(p_timer_conf->id), 3); } void hal_timer_start(uint8_t id) { + NRF_TIMER_Type * p_timer = TIMER_BASE(id); + + p_timer->TASKS_CLEAR = 1; + hal_irq_enable(TIMER_IRQ_NUM(id)); + p_timer->TASKS_START = 1; } void hal_timer_stop(uint8_t id) { + NRF_TIMER_Type * p_timer = TIMER_BASE(id); + + hal_irq_disable(TIMER_IRQ_NUM(id)); + p_timer->TASKS_STOP = 1; +} + +static void common_irq_handler(uint8_t id) { + NRF_TIMER_Type * p_timer = TIMER_BASE(id); + + if (p_timer->EVENTS_COMPARE[0]) { + p_timer->EVENTS_COMPARE[0] = 0; + m_callback(id); + } } void TIMER0_IRQHandler(void) { - + common_irq_handler(0); } #if (MICROPY_PY_MACHINE_SOFT_PWM != 1) void TIMER1_IRQHandler(void) { - + common_irq_handler(1); } #endif void TIMER2_IRQHandler(void) { - + common_irq_handler(2); } #if NRF52 void TIMER3_IRQHandler(void) { - + common_irq_handler(3); } void TIMER4_IRQHandler(void) { - + common_irq_handler(4); } #endif diff --git a/nrf5/hal/hal_timer.h b/nrf5/hal/hal_timer.h index 32e53c498e..25b55557cc 100644 --- a/nrf5/hal/hal_timer.h +++ b/nrf5/hal/hal_timer.h @@ -54,14 +54,19 @@ #define TIMER_BASE(x) ((NRF_TIMER_Type *)TIMER_BASE_POINTERS[x]) #define TIMER_IRQ_NUM(x) (TIMER_IRQ_VALUES[x]) +typedef void (*hal_timer_app_callback)(uint8_t id); + /** * @brief Timer Configuration Structure definition */ typedef struct { uint8_t id; + uint32_t period; uint8_t irq_priority; } hal_timer_conf_t; +void hal_timer_callback_set(hal_timer_app_callback callback); + void hal_timer_init(hal_timer_conf_t const * p_timer_config); void hal_timer_start(uint8_t id); From 6ddaba532a852288f6048bd437175b0f33eeb56d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 31 May 2017 22:27:41 +0200 Subject: [PATCH 752/809] nrf5/modules/machine: Updating timer module to use new hal. Adding new parameters to the init to set period, mode and callback. --- nrf5/modules/machine/timer.c | 51 ++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index e81379ae3e..b1f9ad297a 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -38,6 +38,9 @@ typedef struct _machine_timer_obj_t { mp_obj_base_t base; hal_timer_conf_t * p_config; + mp_obj_t callback; + mp_int_t period; + mp_int_t mode; } machine_timer_obj_t; static hal_timer_conf_t timer_config0 = {.id = 0}; @@ -49,7 +52,7 @@ static hal_timer_conf_t timer_config3 = {.id = 3}; static hal_timer_conf_t timer_config4 = {.id = 4}; #endif -STATIC const machine_timer_obj_t machine_timer_obj[] = { +STATIC machine_timer_obj_t machine_timer_obj[] = { {{&machine_timer_type}, &timer_config0}, {{&machine_timer_type}, &timer_config1}, {{&machine_timer_type}, &timer_config2}, @@ -59,7 +62,21 @@ STATIC const machine_timer_obj_t machine_timer_obj[] = { #endif }; +STATIC void hal_interrupt_handle(uint8_t id) { + machine_timer_obj_t * self = &machine_timer_obj[id]; + + mp_call_function_1(self->callback, self); + + if (self != NULL) { + hal_timer_stop(id); + if (self->mode == 1) { + hal_timer_start(id); + } + } +} + void timer_init0(void) { + hal_timer_callback_set(hal_interrupt_handle); } STATIC int timer_find(mp_obj_t id) { @@ -81,14 +98,12 @@ STATIC void timer_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kin /******************************************************************************/ /* MicroPython bindings for machine API */ -// for make_new -enum { - ARG_NEW_id, -}; - STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} }, + { MP_QSTR_period, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} }, + { MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1} }, + { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, }; // parse args @@ -96,7 +111,7 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); // get static peripheral object - int timer_id = timer_find(args[ARG_NEW_id].u_obj); + int timer_id = timer_find(args[0].u_obj); #if MICROPY_PY_MACHINE_SOFT_PWM if (timer_id == 1) { @@ -105,7 +120,15 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, } #endif - const machine_timer_obj_t *self = &machine_timer_obj[timer_id]; + machine_timer_obj_t *self = &machine_timer_obj[timer_id]; + + self->p_config->period = args[1].u_int; + + self->mode = args[2].u_int; + + if (args[3].u_obj != mp_const_none) { + self->callback = args[3].u_obj; + } hal_timer_init(self->p_config); @@ -115,22 +138,22 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, /// \method start(period) /// Start the timer. /// -STATIC mp_obj_t machine_timer_start(mp_obj_t self_in, mp_obj_t period_in) { +STATIC mp_obj_t machine_timer_start(mp_obj_t self_in) { machine_timer_obj_t * self = MP_OBJ_TO_PTR(self_in); - (void)self; - // hal_timer_start(id); + + hal_timer_start(self->p_config->id); return mp_const_none; } -STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_timer_start_obj, machine_timer_start); +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_start_obj, machine_timer_start); /// \method stop() /// Stop the timer. /// STATIC mp_obj_t machine_timer_stop(mp_obj_t self_in) { machine_timer_obj_t * self = MP_OBJ_TO_PTR(self_in); - (void)self; - // hal_timer_stop(id); + + hal_timer_stop(self->p_config->id); return mp_const_none; } From c28e94b534aa5a3297a839b0e6cbed60df05be79 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 1 Jun 2017 00:32:53 +0200 Subject: [PATCH 753/809] nrf5/modules/machine: Reserving timer0 instance for bluetooth if compiled in. Leaving timer1 and timer2 for application. Note that music module soft-pwm will also occupy timer1 if enabled. --- nrf5/modules/machine/timer.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index b1f9ad297a..1866dfa18e 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -113,6 +113,13 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, // get static peripheral object int timer_id = timer_find(args[0].u_obj); +#if BLUETOOTH_SD + if (timer_id == 0) { + nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, + "Timer(%d) reserved by Bluetooth LE stack.", timer_id)); + } +#endif + #if MICROPY_PY_MACHINE_SOFT_PWM if (timer_id == 1) { nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, From ea95dcba4d2006982e6f471ac5e37bc55e45082d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 2 Jun 2017 18:24:59 +0200 Subject: [PATCH 754/809] nrf5/hal/timer: Update timer hal to use value provided in init to configure the irq_priority. --- nrf5/hal/hal_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/hal/hal_timer.c b/nrf5/hal/hal_timer.c index 4a29e847c4..46d9c389a5 100644 --- a/nrf5/hal/hal_timer.c +++ b/nrf5/hal/hal_timer.c @@ -47,7 +47,7 @@ void hal_timer_init(hal_timer_conf_t const * p_timer_conf) { p_timer->SHORTS = (TIMER_SHORTS_COMPARE0_CLEAR_Enabled << TIMER_SHORTS_COMPARE0_CLEAR_Pos); p_timer->TASKS_CLEAR = 1; - hal_irq_priority(TIMER_IRQ_NUM(p_timer_conf->id), 3); + hal_irq_priority(TIMER_IRQ_NUM(p_timer_conf->id), p_timer_conf->irq_priority); } void hal_timer_start(uint8_t id) { From db0f4963b7be52a2a45870b5cdbd1011c351dd58 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 2 Jun 2017 18:25:28 +0200 Subject: [PATCH 755/809] nrf5/modules/machine: Update timer init to set default IRQ priority before initializing Timer instance. --- nrf5/modules/machine/timer.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/nrf5/modules/machine/timer.c b/nrf5/modules/machine/timer.c index 1866dfa18e..d9d4cf32e5 100644 --- a/nrf5/modules/machine/timer.c +++ b/nrf5/modules/machine/timer.c @@ -137,6 +137,12 @@ STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, self->callback = args[3].u_obj; } +#ifdef NRF51 + self->p_config->irq_priority = 3; +#else + self->p_config->irq_priority = 6; +#endif + hal_timer_init(self->p_config); return MP_OBJ_FROM_PTR(self); From d5acc13d5e4c3f1a125f9a1ebbc39b5faa1b9496 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 2 Jun 2017 21:06:36 +0200 Subject: [PATCH 756/809] nrf5/modules/music: Correct parameter checking of pin argument to deside whether to use MUSIC_PIN define or throw an error. If MUSIC_PIN define is configured the pin argument to music module play() can be elided. --- nrf5/modules/music/modmusic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index 680c7c0422..3239e2cc0b 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -337,7 +337,7 @@ STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, // get the pin to play on const pin_obj_t *pin; - if (n_args >= 2) { + if (args[1].u_obj == MP_OBJ_NULL) { #ifdef MICROPY_HW_MUSIC_PIN pin = &MICROPY_HW_MUSIC_PIN; #else From db0fa6aafb7047f63933e9be8ba4bdee0e4c7665 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 2 Jun 2017 21:18:28 +0200 Subject: [PATCH 757/809] nrf5/modules/music: Updating pitch method to also use configured pin from mpconfigboard.h if set, in the case of lacking kwarg for pin. Also removing some commented out arguments to remove some confusion in the argument list. Done for both play() and pitch(). --- nrf5/modules/music/modmusic.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/nrf5/modules/music/modmusic.c b/nrf5/modules/music/modmusic.c index 3239e2cc0b..06d98aec12 100644 --- a/nrf5/modules/music/modmusic.c +++ b/nrf5/modules/music/modmusic.c @@ -307,7 +307,6 @@ MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(microbit_music_stop_obj, 0, 1, microbit_musi STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { static const mp_arg_t allowed_args[] = { { MP_QSTR_music, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, -// TODO:{ MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_wait, MP_ARG_BOOL, {.u_bool = true} }, { MP_QSTR_loop, MP_ARG_BOOL, {.u_bool = false} }, @@ -378,7 +377,6 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, static const mp_arg_t allowed_args[] = { { MP_QSTR_frequency, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} }, { MP_QSTR_duration, MP_ARG_INT, {.u_int = -1} }, -//TODO: { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = (mp_obj_t)µbit_p0_obj} }, { MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, { MP_QSTR_wait, MP_ARG_BOOL, {.u_bool = true} }, }; @@ -390,8 +388,19 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, // get the parameters mp_uint_t frequency = args[0].u_int; mp_int_t duration = args[1].u_int; - const pin_obj_t *pin = args[2].u_obj; - (void)pin; + + // get the pin to play on + const pin_obj_t *pin; + if (args[2].u_obj == MP_OBJ_NULL) { +#ifdef MICROPY_HW_MUSIC_PIN + pin = &MICROPY_HW_MUSIC_PIN; +#else + nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "pin parameter not given")); +#endif + } else { + pin = (pin_obj_t *)args[2].u_obj; + } + // Update pin modes //TODO: microbit_obj_pin_free(music_data->async_pin); music_data->async_pin = NULL; From 65b3e9875d6a0671cfe23725113cb1129199ba13 Mon Sep 17 00:00:00 2001 From: glennrub Date: Sat, 3 Jun 2017 00:16:31 +0200 Subject: [PATCH 758/809] Update README.md --- nrf5/README.md | 143 ++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 119 insertions(+), 24 deletions(-) diff --git a/nrf5/README.md b/nrf5/README.md index a7bbc011cf..1a2470b0df 100644 --- a/nrf5/README.md +++ b/nrf5/README.md @@ -12,35 +12,130 @@ This is a port of MicroPython to the Nordic nRF5 series of chips. * I2C * PWM (nRF52 only) * Temperature -* RTC -* Some BLE support including _REPL over BLE_ - -Note that this port is still a work-in-progress and some modules are not fully feature complete. +* RTC (Real Time Counter. Low-Power counter) +* BLE support including: + * Peripheral role on nrf51 targets + * Central role and Peripheral role on nrf52 targets + * _REPL over Bluetooth LE_ (optionally using WebBluetooth) + * ubluepy: Bluetooth LE module for micropython ## Tested hardware + * nRF51 -* nRF52 + * [micro:bit](http://microbit.org/) + * PCA10000 (dongle) + * PCA10001 + * PCA10028 + * PCA10031 (dongle) +* nRF52832 * [PCA10040](http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52%2Fdita%2Fnrf52%2Fdevelopment%2Fnrf52_dev_kit.html) - * [D52Q](https://www.dynastream.com/components/d52) * [Adafruit Feather nRF52](https://www.adafruit.com/product/3406) + * [Thingy:52](http://www.nordicsemi.com/eng/Products/Nordic-Thingy-52) + * [Arduino Primo](http://www.arduino.org/products/boards/arduino-primo) +* nRF52840 + * [PCA10056](http://www.nordicsemi.com/eng/Products/nRF52840-Preview-DK) -## Build steps +## Compile and Flash -Example is for the Adafruit Feather nRF52: +Before any compilation of any targets some basic operatons needs to be done: -``` -> sudo apt-get install build-essential libffi-dev pkg-config gcc-arm-none-eabi git python python-pip -> git clone https://github.com/adafruit/Adafruit_nRF52_Arduino.git -> cd Adafruit_nRF52_Arduino/tools/nrfutil-0.5.2/ -> sudo pip install -r requirements.txt -> sudo python setup.py install -> cd ../../.. -> git clone https://github.com/tralamazza/micropython.git nrf5_no_sdk -> cd nrf5_no_sdk/ -> git submodule update --init -> make -C mpy-cross -> cd nrf5/ -> make BOARD=feather52 -> make BOARD=feather52 dfu-gen -> make BOARD=feather52 dfu-flash -``` \ No newline at end of file + git clone .git micropython + cd micropython + git submodule update --init + make -C mpy-cross + +By default PCA10040 (nrf52832) is used as compile target. To build issue the following command inside the nrf5/ folder: + + make + make flash + +Alternativly the target board could be defined: + + make BOARD=pca10040 + make flash + +Available board target names: +* microbit +* feather52 +* pca10000 +* pca10001 +* pca10028 +* pca10031 +* pca10040 +* pca10056 + +## Compile and Flash with Bluetooth Stack + +First prepare the bluetooth folder by downloading Bluetooth LE stacks and headers: + + ./drivers/bluetooth/download_ble_stack.sh + +If the Bluetooth stacks has been downloaded, compile the target with the following command: + + make BOARD=pca10040 SD=s132 + make sd + +The **make sd** will trigger a flash of the bluetooth stack before that application is flashed. Note that **make sd** will perform a full erase of the chip, which could cause 3rd party bootloaders to also be wiped. + +Note: further tuning of features to include in bluetooth or even setting up the device to use REPL over Bluetooth can be configured in the bluetooth_conf.h. + +Board | SD param | Support +------------|-------------|---------- +microbit | s110 | Peripheral +pca10000 | s110 | Peripheral +pca10001 | s110 | Peripheral +pca10028 | s110 | Peripheral +pca10031 | s110 | Peripheral +pca10040 | s132 | Peripheral and Central +feather52 | s132 | Peripheral and Central +pca10056 | | + +## Segger targets + +Install the necessary tools to flash and debug using Segger: + +[JLink](https://www.segger.com/downloads/jlink#) + +[nrfjprog linux-32bit](https://www.nordicsemi.com/eng/nordic/download_resource/52615/16/95882111/97746) +[nrfjprog linux-64bit](https://www.nordicsemi.com/eng/nordic/download_resource/51386/21/77886419/94917) +[nrfjprog osx](https://www.nordicsemi.com/eng/nordic/download_resource/53402/12/97293750/99977) +[nrfjprog win32](https://www.nordicsemi.com/eng/nordic/download_resource/33444/40/22191727/53210) + +Boards that would need JLink/nrfjprog: +* PCA10000 +* PCA10001 +* PCA10028 +* PCA10031 +* PCA10040 +* PCA10056 + +## PyOCD/OpenOCD targets + +Install the necessary tools to flash and debug using OpenOCD: + + sudo apt-get install openocd + sudo pip install pyOCD + +Boards that would need PyOCD: +* micro:bit + +## DFU targets + + sudo apt-get install build-essential libffi-dev pkg-config gcc-arm-none-eabi git python python-pip + git clone https://github.com/adafruit/Adafruit_nRF52_Arduino.git + cd Adafruit_nRF52_Arduino/tools/nrfutil-0.5.2/ + sudo pip install -r requirements.txt + sudo python setup.py install + +**make flash** and **make sd** will not work with DFU targets. Hence, **dfu-gen** and **dfu-flash** must be used instead. +* dfu-gen: Generates a Firmware zip to be used by the DFU flash application. +* dfu-flash: Triggers the DFU flash application to upload the firmware from the generated Firmware zip file. + +Example on how to generate and flash feather52 target: + + make BOARD=feather52 + make BOARD=feather52 dfu-gen + make BOARD=feather52 dfu-flash + +Boards that would need DFU flash utilities: +* feather52 (Adafruit Feather nRF52) From a37416dc2ddfc65c08947a29cb00794da585cf4a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 3 Jun 2017 19:34:05 +0200 Subject: [PATCH 759/809] nrf5: Updating main.c to support RAW REPL. --- nrf5/main.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/nrf5/main.c b/nrf5/main.c index 72b4a79653..41929f2042 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -83,6 +83,7 @@ extern uint32_t _heap_end; int main(int argc, char **argv) { +soft_reset: mp_stack_set_top(&_ram_end); // Stack limit should be less than real stack size, so we have a chance @@ -197,9 +198,15 @@ pin_init0(); #endif for (;;) { - ret_code = pyexec_friendly_repl(); - if (ret_code != 0) { - break; + if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) { + if (pyexec_raw_repl() != 0) { + break; + } + } else { + ret_code = pyexec_friendly_repl(); + if (ret_code != 0) { + break; + } } } @@ -207,6 +214,8 @@ pin_init0(); if (ret_code == PYEXEC_FORCED_EXIT) { NVIC_SystemReset(); + } else { + goto soft_reset; } return 0; From a2a8115ed48cf9990a20c795e48fd26a29028f90 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 3 Jun 2017 19:56:30 +0200 Subject: [PATCH 760/809] nrf5: Update help.c with documentation of CTRL-A and CTRL-B to enter and exit raw REPL mode. --- nrf5/help.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nrf5/help.c b/nrf5/help.c index f17439a19d..2911d25600 100644 --- a/nrf5/help.c +++ b/nrf5/help.c @@ -43,6 +43,8 @@ const char * nrf5_help_text = HELP_TEXT_SD #endif "Control commands:\n" +" CTRL-A -- on a blank line, enter raw REPL mode\n" +" CTRL-B -- on a blank line, enter normal REPL mode\n" " CTRL-D -- on a blank line, do a soft reset of the board\n" " CTRL-E -- on a blank line, enter paste mode\n" "\n" From dbf33fdc4633b218acdef4a8c7eedef6afc6abb6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 3 Jun 2017 20:20:38 +0200 Subject: [PATCH 761/809] nrf5: Updating readme.md file based on review comments. --- nrf5/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nrf5/README.md b/nrf5/README.md index 1a2470b0df..75fb9281dc 100644 --- a/nrf5/README.md +++ b/nrf5/README.md @@ -37,19 +37,19 @@ This is a port of MicroPython to the Nordic nRF5 series of chips. ## Compile and Flash -Before any compilation of any targets some basic operatons needs to be done: +Prerequisite steps for building the nrf5 port: git clone .git micropython cd micropython git submodule update --init make -C mpy-cross -By default PCA10040 (nrf52832) is used as compile target. To build issue the following command inside the nrf5/ folder: +By default PCA10040 (nrf52832) is used as compile target. To build and flash issue the following command inside the nrf5/ folder: make make flash -Alternativly the target board could be defined: +Alternatively the target board could be defined: make BOARD=pca10040 make flash From 235e848ea70582e986e1653bb6e2a2bc4244b554 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sat, 3 Jun 2017 21:42:42 +0200 Subject: [PATCH 762/809] nrf5/boards/feather52: Add SERIAL makeflag if dfu-flash target is used. --- nrf5/boards/feather52/mpconfigboard.mk | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/nrf5/boards/feather52/mpconfigboard.mk b/nrf5/boards/feather52/mpconfigboard.mk index 1b0e1460e9..ce8dcde30d 100644 --- a/nrf5/boards/feather52/mpconfigboard.mk +++ b/nrf5/boards/feather52/mpconfigboard.mk @@ -7,10 +7,19 @@ LD_FILE = boards/feather52/custom_nrf52832_dfu_app.ld NRF_DEFINES += -DNRF52832_XXAA + +check_defined = \ + $(strip $(foreach 1,$1, \ + $(call __check_defined,$1,$(strip $(value 2))))) +__check_defined = \ + $(if $(value $1),, \ + $(error Undefined make flag: $1$(if $2, ($2)))) + .PHONY: dfu-gen dfu-flash dfu-gen: nrfutil dfu genpkg --dev-type 0x0052 --application $(BUILD)/$(OUTPUT_FILENAME).hex $(BUILD)/dfu-package.zip dfu-flash: - sudo nrfutil dfu serial --package $(BUILD)/dfu-package.zip -p /dev/ttyACM3 + @:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyUSB0) + sudo nrfutil dfu serial --package $(BUILD)/dfu-package.zip -p $(SERIAL) From 3996ed7183b33678bd05c9adb6b3b5f30d55465c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Sun, 4 Jun 2017 12:50:14 +0200 Subject: [PATCH 763/809] nrf5/boards/feather52: Update s132 target makefile with dfu-gen and dfu-flash. This enables feather52 with Bluetooth LE. Features to be configured in bluetooth_conf.h. --- nrf5/boards/feather52/mpconfigboard_s132.mk | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/nrf5/boards/feather52/mpconfigboard_s132.mk b/nrf5/boards/feather52/mpconfigboard_s132.mk index 17dda95899..ce8dcde30d 100644 --- a/nrf5/boards/feather52/mpconfigboard_s132.mk +++ b/nrf5/boards/feather52/mpconfigboard_s132.mk @@ -6,3 +6,20 @@ SOFTDEV_VERSION = 2.0.1 LD_FILE = boards/feather52/custom_nrf52832_dfu_app.ld NRF_DEFINES += -DNRF52832_XXAA + + +check_defined = \ + $(strip $(foreach 1,$1, \ + $(call __check_defined,$1,$(strip $(value 2))))) +__check_defined = \ + $(if $(value $1),, \ + $(error Undefined make flag: $1$(if $2, ($2)))) + +.PHONY: dfu-gen dfu-flash + +dfu-gen: + nrfutil dfu genpkg --dev-type 0x0052 --application $(BUILD)/$(OUTPUT_FILENAME).hex $(BUILD)/dfu-package.zip + +dfu-flash: + @:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyUSB0) + sudo nrfutil dfu serial --package $(BUILD)/dfu-package.zip -p $(SERIAL) From e645b0b425daefe7e3c4bc8d369a4ea8bee52394 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 15:28:54 +0200 Subject: [PATCH 764/809] nrf5: Updating mpconfigport.h to set default values for MICROPY_HW_LED_COUNT (0) and MICROPY_HW_LED_PULLUP (0). --- nrf5/mpconfigport.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/nrf5/mpconfigport.h b/nrf5/mpconfigport.h index 7cd2f08690..a21bf89030 100644 --- a/nrf5/mpconfigport.h +++ b/nrf5/mpconfigport.h @@ -116,6 +116,14 @@ #define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) #define MICROPY_PY_FRAMEBUF (0) +#ifndef MICROPY_HW_LED_COUNT +#define MICROPY_HW_LED_COUNT (0) +#endif + +#ifndef MICROPY_HW_LED_PULLUP +#define MICROPY_HW_LED_PULLUP (0) +#endif + #ifndef MICROPY_PY_MUSIC #define MICROPY_PY_MUSIC (0) #endif From c4304d69e02f29bae2fbc5d0f83be1f49942dfa1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 15:29:55 +0200 Subject: [PATCH 765/809] nrf5: Generalize script setting LED(1) on to be applied only when there are leds present on the board. --- nrf5/main.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/nrf5/main.c b/nrf5/main.c index 41929f2042..465a0c9513 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -175,15 +175,10 @@ pin_init0(); do_str("import pyb\r\n" \ "pyb.LED(1).on()", MP_PARSE_FILE_INPUT); -#elif (MICROPY_HW_LED_COUNT == 2) +#elif (MICROPY_HW_LED_COUNT > 0) do_str("import pyb\r\n" \ "pyb.LED(1).on()", MP_PARSE_FILE_INPUT); -#else - do_str("import pyb\r\n" \ - "pyb.LED(1).on()\r\n" \ - "pyb.LED(3).on()", - MP_PARSE_FILE_INPUT); #endif // Main script is finished, so now go into REPL mode. From 044e36f26f7e88ab091418ee03746a6a712a853d Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 15:30:45 +0200 Subject: [PATCH 766/809] nrf5/boards: Updating pca10040 board header to set the LED count. --- nrf5/boards/pca10040/mpconfigboard.h | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 57f686c057..175253c2a1 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -51,6 +51,7 @@ #define MICROPY_HW_ENABLE_DAC (0) #define MICROPY_HW_ENABLE_CAN (0) +#define MICROPY_HW_LED_COUNT (4) #define MICROPY_HW_LED_PULLUP (1) #define MICROPY_HW_LED1 (17) // LED1 From 9779910e3e66d56e013f44e9f1854438bea503a2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 17:36:56 +0200 Subject: [PATCH 767/809] nrf5/boards: Updating boards with correct LED count. Also adding new flag, MICROPY_HW_HAS_LED, to select whether the board has LED's at all. If not, this will unselect LED module from being compiled in. --- nrf5/boards/feather52/mpconfigboard.h | 1 + nrf5/boards/microbit/mpconfigboard.h | 10 +--------- nrf5/boards/pca10000/mpconfigboard.h | 1 + nrf5/boards/pca10001/mpconfigboard.h | 1 + nrf5/boards/pca10028/mpconfigboard.h | 2 ++ nrf5/boards/pca10031/mpconfigboard.h | 1 + nrf5/boards/pca10040/mpconfigboard.h | 1 + nrf5/boards/pca10056/mpconfigboard.h | 2 ++ 8 files changed, 10 insertions(+), 9 deletions(-) diff --git a/nrf5/boards/feather52/mpconfigboard.h b/nrf5/boards/feather52/mpconfigboard.h index 3d99f3c489..9a97381ec5 100644 --- a/nrf5/boards/feather52/mpconfigboard.h +++ b/nrf5/boards/feather52/mpconfigboard.h @@ -38,6 +38,7 @@ #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) +#define MICROPY_HW_HAS_LED (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf5/boards/microbit/mpconfigboard.h index b265795569..5985d04661 100644 --- a/nrf5/boards/microbit/mpconfigboard.h +++ b/nrf5/boards/microbit/mpconfigboard.h @@ -39,6 +39,7 @@ #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) +#define MICROPY_HW_HAS_LED (0) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) @@ -52,13 +53,6 @@ #define MICROPY_HW_ENABLE_DAC (0) #define MICROPY_HW_ENABLE_CAN (0) -#define MICROPY_HW_LED_PULLUP (1) - -#define MICROPY_HW_LED1 (21) // LED1 -#define MICROPY_HW_LED2 (22) // LED2 -#define MICROPY_HW_LED3 (23) // LED3 -#define MICROPY_HW_LED4 (24) // LED4 - // UART config #define MICROPY_HW_UART1_RX (pin_A25) #define MICROPY_HW_UART1_TX (pin_A24) @@ -72,5 +66,3 @@ // micro:bit music pin #define MICROPY_HW_MUSIC_PIN (pin_A3) - -#define HELP_TEXT_BOARD_LED "1,2,3,4" diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf5/boards/pca10000/mpconfigboard.h index a734e512ed..a2a8a3a36d 100644 --- a/nrf5/boards/pca10000/mpconfigboard.h +++ b/nrf5/boards/pca10000/mpconfigboard.h @@ -33,6 +33,7 @@ #define MICROPY_PY_MACHINE_HW_SPI (0) #define MICROPY_PY_MACHINE_TEMP (1) +#define MICROPY_HW_HAS_LED (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/pca10001/mpconfigboard.h b/nrf5/boards/pca10001/mpconfigboard.h index 280c4764d9..0ef5a2492d 100644 --- a/nrf5/boards/pca10001/mpconfigboard.h +++ b/nrf5/boards/pca10001/mpconfigboard.h @@ -33,6 +33,7 @@ #define MICROPY_PY_MACHINE_HW_SPI (0) #define MICROPY_PY_MACHINE_TEMP (1) +#define MICROPY_HW_HAS_LED (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf5/boards/pca10028/mpconfigboard.h index cd04f9b4eb..ef9a0a94bf 100644 --- a/nrf5/boards/pca10028/mpconfigboard.h +++ b/nrf5/boards/pca10028/mpconfigboard.h @@ -37,6 +37,7 @@ #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) +#define MICROPY_HW_HAS_LED (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) @@ -50,6 +51,7 @@ #define MICROPY_HW_ENABLE_DAC (0) #define MICROPY_HW_ENABLE_CAN (0) +#define MICROPY_HW_LED_COUNT (4) #define MICROPY_HW_LED_PULLUP (1) #define MICROPY_HW_LED1 (21) // LED1 diff --git a/nrf5/boards/pca10031/mpconfigboard.h b/nrf5/boards/pca10031/mpconfigboard.h index 8baef4335e..06de2e6440 100644 --- a/nrf5/boards/pca10031/mpconfigboard.h +++ b/nrf5/boards/pca10031/mpconfigboard.h @@ -32,6 +32,7 @@ #define MICROPY_PY_MACHINE_TEMP (1) +#define MICROPY_HW_HAS_LED (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf5/boards/pca10040/mpconfigboard.h index 175253c2a1..c46db9ea6c 100644 --- a/nrf5/boards/pca10040/mpconfigboard.h +++ b/nrf5/boards/pca10040/mpconfigboard.h @@ -38,6 +38,7 @@ #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) +#define MICROPY_HW_HAS_LED (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf5/boards/pca10056/mpconfigboard.h index d5d685177a..05cf1a7be0 100644 --- a/nrf5/boards/pca10056/mpconfigboard.h +++ b/nrf5/boards/pca10056/mpconfigboard.h @@ -36,6 +36,7 @@ #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) +#define MICROPY_HW_HAS_LED (1) #define MICROPY_HW_HAS_SWITCH (0) #define MICROPY_HW_HAS_FLASH (0) #define MICROPY_HW_HAS_SDCARD (0) @@ -49,6 +50,7 @@ #define MICROPY_HW_ENABLE_DAC (0) #define MICROPY_HW_ENABLE_CAN (0) +#define MICROPY_HW_LED_COUNT (4) #define MICROPY_HW_LED_PULLUP (1) #define MICROPY_HW_LED1 (13) // LED1 From 2f983d3ef96278610daf420d4971cdd5cea4a9d3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 17:39:47 +0200 Subject: [PATCH 768/809] nrf5: Update pyb module, and led module to only be compiled in if MICROPY_HW_HAS_LED is set to 1. --- nrf5/help.c | 2 ++ nrf5/main.c | 9 +++------ nrf5/modules/machine/led.c | 3 +++ nrf5/modules/pyb/modpyb.c | 8 +++++++- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/nrf5/help.c b/nrf5/help.c index 2911d25600..8022f5bf6b 100644 --- a/nrf5/help.c +++ b/nrf5/help.c @@ -37,8 +37,10 @@ const char * nrf5_help_text = "For online help please visit http://micropython.org/help/.\n" "\n" "Quick overview of commands for the board:\n" +#if MICROPY_HW_HAS_LED " pyb.LED(n) -- create an LED object for LED n (n=" HELP_TEXT_BOARD_LED ")\n" "\n" +#endif #if BLUETOOTH_SD HELP_TEXT_SD #endif diff --git a/nrf5/main.c b/nrf5/main.c index 465a0c9513..0b5385fc3d 100644 --- a/nrf5/main.c +++ b/nrf5/main.c @@ -90,7 +90,6 @@ soft_reset: // to recover from limit hit. (Limit is measured in bytes.) mp_stack_set_limit((char*)&_ram_end - (char*)&_heap_end - 400); - led_init(); machine_init(); gc_init(&_heap_start, &_heap_end); @@ -171,11 +170,9 @@ pin_init0(); } #endif -#if MICROPY_HW_LED_TRICOLOR - do_str("import pyb\r\n" \ - "pyb.LED(1).on()", - MP_PARSE_FILE_INPUT); -#elif (MICROPY_HW_LED_COUNT > 0) +#if (MICROPY_HW_HAS_LED) + led_init(); + do_str("import pyb\r\n" \ "pyb.LED(1).on()", MP_PARSE_FILE_INPUT); diff --git a/nrf5/modules/machine/led.c b/nrf5/modules/machine/led.c index a23ef4427b..5b6aab102e 100644 --- a/nrf5/modules/machine/led.c +++ b/nrf5/modules/machine/led.c @@ -31,6 +31,8 @@ #include "led.h" #include "mpconfigboard.h" +#if MICROPY_HW_HAS_LED + #define LED_OFF(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_set(0, led) : hal_gpio_pin_clear(0, led); } #define LED_ON(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_clear(0, led) : hal_gpio_pin_set(0, led); } @@ -154,3 +156,4 @@ const mp_obj_type_t pyb_led_type = { .locals_dict = (mp_obj_dict_t*)&led_locals_dict, }; +#endif // MICROPY_HW_HAS_LED diff --git a/nrf5/modules/pyb/modpyb.c b/nrf5/modules/pyb/modpyb.c index ec49224bc7..f6cf2b1069 100644 --- a/nrf5/modules/pyb/modpyb.c +++ b/nrf5/modules/pyb/modpyb.c @@ -32,11 +32,17 @@ #include "nrf.h" // TODO: figure out where to put this import #include "pin.h" +#if MICROPY_HW_HAS_LED +#define PYB_LED_MODULE { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pyb_led_type) }, +#else +#define PYB_LED_MODULE +#endif + STATIC const mp_rom_map_elem_t pyb_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_pyb) }, - { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pyb_led_type) }, { MP_ROM_QSTR(MP_QSTR_repl_info), MP_ROM_PTR(&pyb_set_repl_info_obj) }, { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&pin_type) }, + PYB_LED_MODULE /* { MP_ROM_QSTR(MP_QSTR_main), MP_ROM_PTR(&pyb_main_obj) }*/ }; From 35a3abb9984a9541776bf190fdaa3e3f7ab560b6 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 17:46:56 +0200 Subject: [PATCH 769/809] nrf5/examples: Moving nrf52 specific HW example from freeze to examples to replace test.py with a more generic example. --- nrf5/{freeze/test.py => examples/nrf52_pwm.py} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename nrf5/{freeze/test.py => examples/nrf52_pwm.py} (100%) diff --git a/nrf5/freeze/test.py b/nrf5/examples/nrf52_pwm.py similarity index 100% rename from nrf5/freeze/test.py rename to nrf5/examples/nrf52_pwm.py From 56c28d2ba6b994cf73c864db7f942a3c45f7396e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 17:54:39 +0200 Subject: [PATCH 770/809] nrf5/freeze: Adding generic example to freeze. Hello world with board name as parameter. --- nrf5/freeze/test.py | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 nrf5/freeze/test.py diff --git a/nrf5/freeze/test.py b/nrf5/freeze/test.py new file mode 100644 index 0000000000..e64bbc9f52 --- /dev/null +++ b/nrf5/freeze/test.py @@ -0,0 +1,4 @@ +import sys + +def hello(): + print("Hello %s!" % sys.platform) From e35a552f1ffc1eee2eda9df74bfc2fd4535ee5d3 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 21:38:41 +0200 Subject: [PATCH 771/809] nrf5/examples: Renaming servo.py to nrf52_servo.py as it is only implemented machine.PWM for nrf52. --- nrf5/examples/{servo.py => nrf52_servo.py} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename nrf5/examples/{servo.py => nrf52_servo.py} (100%) diff --git a/nrf5/examples/servo.py b/nrf5/examples/nrf52_servo.py similarity index 100% rename from nrf5/examples/servo.py rename to nrf5/examples/nrf52_servo.py From de3a78a097114f3ca35887d01aa23c12affa6b53 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 21:59:37 +0200 Subject: [PATCH 772/809] nrf5/hal/gpio: Updating toggle inline function to work correctly, currently only used by LED module. --- nrf5/hal/hal_gpio.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/nrf5/hal/hal_gpio.h b/nrf5/hal/hal_gpio.h index 06fadcbef9..fcdc49ad75 100644 --- a/nrf5/hal/hal_gpio.h +++ b/nrf5/hal/hal_gpio.h @@ -91,13 +91,11 @@ static inline void hal_gpio_pin_clear(uint8_t port, uint32_t pin) { } static inline void hal_gpio_pin_toggle(uint8_t port, uint32_t pin) { - uint32_t pin_mask = (1 << pin); + uint32_t pin_mask = (1 << pin); + uint32_t pins_state = NRF_GPIO->OUT; - if (GPIO_BASE(port)->OUT ^ pin_mask) { - GPIO_BASE(port)->OUTSET = pin_mask; - } else { - GPIO_BASE(port)->OUTCLR = pin_mask; - } + GPIO_BASE(port)->OUTSET = (~pins_state) & pin_mask; + GPIO_BASE(port)->OUTCLR = pins_state & pin_mask; } typedef enum { From dbc184816a554f4f6b0c84b3588856b5ccef1d51 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 6 Jun 2017 21:43:51 +0200 Subject: [PATCH 773/809] nrf5/examples: Removing copy of ssd1306 driver, creating a new class that overrides the needed function for i2c. Also adding some example usage in the comment in top of the file for both SPI and I2C variant. --- nrf5/examples/ssd1306.py | 177 ----------------------------------- nrf5/examples/ssd1306_mod.py | 27 ++++++ 2 files changed, 27 insertions(+), 177 deletions(-) delete mode 100644 nrf5/examples/ssd1306.py create mode 100644 nrf5/examples/ssd1306_mod.py diff --git a/nrf5/examples/ssd1306.py b/nrf5/examples/ssd1306.py deleted file mode 100644 index d9bb957618..0000000000 --- a/nrf5/examples/ssd1306.py +++ /dev/null @@ -1,177 +0,0 @@ -# MicroPython SSD1306 OLED driver, I2C and SPI interfaces - -# Example usage for I2C on pca10040 / pca10056 -# -# from machine import Pin, I2C -# from ssd1306 import SSD1306_I2C -# self.scl = Pin("A3", mode=Pin.OUT, pull=Pin.PULL_UP) -# self.sda = Pin("A4", mode=Pin.OUT, pull=Pin.PULL_UP) -# self.i2c = I2C(0, self.scl, self.sda) -# self.ssd = SSD1306_I2C(128, 64, self.i2c) - -import time -import framebuf -from machine import SPI, Pin - -# register definitions -SET_CONTRAST = const(0x81) -SET_ENTIRE_ON = const(0xa4) -SET_NORM_INV = const(0xa6) -SET_DISP = const(0xae) -SET_MEM_ADDR = const(0x20) -SET_COL_ADDR = const(0x21) -SET_PAGE_ADDR = const(0x22) -SET_DISP_START_LINE = const(0x40) -SET_SEG_REMAP = const(0xa0) -SET_MUX_RATIO = const(0xa8) -SET_COM_OUT_DIR = const(0xc0) -SET_DISP_OFFSET = const(0xd3) -SET_COM_PIN_CFG = const(0xda) -SET_DISP_CLK_DIV = const(0xd5) -SET_PRECHARGE = const(0xd9) -SET_VCOM_DESEL = const(0xdb) -SET_CHARGE_PUMP = const(0x8d) - - -class SSD1306: - def __init__(self, width, height, external_vcc): - self.width = width - self.height = height - self.external_vcc = external_vcc - self.pages = self.height // 8 - self.buffer = bytearray(self.pages * self.width) - self.framebuf = framebuf.FrameBuffer1(self.buffer, self.width, self.height) - self.poweron() - self.init_display() - - def init_display(self): - for cmd in ( - SET_DISP | 0x00, # off - # address setting - SET_MEM_ADDR, 0x00, # horizontal - # resolution and layout - SET_DISP_START_LINE | 0x00, - SET_SEG_REMAP | 0x01, # column addr 127 mapped to SEG0 - SET_MUX_RATIO, self.height - 1, - SET_COM_OUT_DIR | 0x08, # scan from COM[N] to COM0 - SET_DISP_OFFSET, 0x00, - SET_COM_PIN_CFG, 0x02 if self.height == 32 else 0x12, - # timing and driving scheme - SET_DISP_CLK_DIV, 0x80, - SET_PRECHARGE, 0x22 if self.external_vcc else 0xf1, - SET_VCOM_DESEL, 0x30, # 0.83*Vcc - # display - SET_CONTRAST, 0xff, # maximum - SET_ENTIRE_ON, # output follows RAM contents - SET_NORM_INV, # not inverted - # charge pump - SET_CHARGE_PUMP, 0x10 if self.external_vcc else 0x14, - SET_DISP | 0x01): # on - self.write_cmd(cmd) - self.fill(0) - self.show() - - def poweroff(self): - self.write_cmd(SET_DISP | 0x00) - - def contrast(self, contrast): - self.write_cmd(SET_CONTRAST) - self.write_cmd(contrast) - - def invert(self, invert): - self.write_cmd(SET_NORM_INV | (invert & 1)) - - def show(self): - x0 = 0 - x1 = self.width - 1 - if self.width == 64: - # displays with width of 64 pixels are shifted by 32 - x0 += 32 - x1 += 32 - self.write_cmd(SET_COL_ADDR) - self.write_cmd(x0) - self.write_cmd(x1) - self.write_cmd(SET_PAGE_ADDR) - self.write_cmd(0) - self.write_cmd(self.pages - 1) - self.write_data(self.buffer) - - def fill(self, col): - self.framebuf.fill(col) - - def pixel(self, x, y, col): - self.framebuf.pixel(x, y, col) - - def scroll(self, dx, dy): - self.framebuf.scroll(dx, dy) - - def text(self, string, x, y, col=1): - self.framebuf.text(string, x, y, col) - - -class SSD1306_I2C(SSD1306): - def __init__(self, width, height, i2c, addr=0x3c, external_vcc=False): - self.i2c = i2c - self.addr = addr - self.temp = bytearray(2) - super().__init__(width, height, external_vcc) - - def write_cmd(self, cmd): - self.temp[0] = 0x80 # Co=1, D/C#=0 - self.temp[1] = cmd - self.i2c.writeto(self.addr, self.temp) - - def write_data(self, buf): - buffer = bytearray([0x40]) + buf # Co=0, D/C#=1 - self.i2c.writeto(self.addr, buffer) - - def poweron(self): - pass - -class SSD1306_SPI(SSD1306): - def __init__(self, width, height, external_vcc=False): - self.rate = 10 * 1024 * 1024 - self.spi = SPI(0, baudrate=4000000) - -# self.dc = Pin("A11", mode=Pin.OUT, pull=Pin.PULL_UP) -# self.dc.low() -# -# self.res = Pin("A12", mode=Pin.OUT, pull=Pin.PULL_UP) -# self.res.low() -# -# self.cs = Pin("A13", mode=Pin.OUT, pull=Pin.PULL_UP) -# self.cs.high() - - self.dc = Pin("B1", mode=Pin.OUT, pull=Pin.PULL_UP) - self.dc.low() - - self.res = Pin("B2", mode=Pin.OUT, pull=Pin.PULL_UP) - self.res.low() - - self.cs = Pin("B3", mode=Pin.OUT, pull=Pin.PULL_UP) - self.cs.high() - - super().__init__(width, height, external_vcc) - - def write_cmd(self, cmd): - self.spi.init(baudrate=self.rate, polarity=0, phase=0) - self.cs.high() - self.dc.low() - self.cs.low() - self.spi.write(bytearray([cmd])) - self.cs.high() - - def write_data(self, buf): - self.spi.init(baudrate=self.rate, polarity=0, phase=0) - self.cs.high() - self.dc.high() - self.cs.low() - self.spi.write(buf) - self.cs.high() - - def poweron(self): - self.res.high() - time.sleep_ms(1) - self.res.low() - time.sleep_ms(10) - self.res.high() diff --git a/nrf5/examples/ssd1306_mod.py b/nrf5/examples/ssd1306_mod.py new file mode 100644 index 0000000000..1c3ba85f70 --- /dev/null +++ b/nrf5/examples/ssd1306_mod.py @@ -0,0 +1,27 @@ +# NOTE: Modified version to align with implemented I2C API in nrf5 port. +# +# Examples usage of SSD1306_SPI on pca10040 +# +# from machine import Pin, SPI +# from ssd1306 import SSD1306_SPI +# spi = SPI(0, baudrate=40000000) +# dc = Pin.board.PA11 +# res = Pin.board.PA12 +# cs = Pin.board.PA13 +# disp = SSD1306_SPI(128, 64, spi, dc, res, cs) +# +# +# Example usage of SSD1306_I2C on pca10040 +# +# from machine import Pin, I2C +# from ssd1306 import SSD1306_I2C +# i2c = I2C(0, Pin.board.PA3, Pin.board.PA4) +# disp = SSD1306_I2C_Mod(128, 64, i2c) + +from ssd1306 import SSD1306_I2C + +class SSD1306_I2C_Mod(SSD1306_I2C): + + def write_data(self, buf): + buffer = bytearray([0x40]) + buf # Co=0, D/C#=1 + self.i2c.writeto(self.addr, buffer) From d21b11fe0ee1f22d60802b0608ed33f8c46eb5a2 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 6 Jun 2017 22:16:49 +0200 Subject: [PATCH 774/809] nrf5/examples: Removing copy of sdcard.py also found in drivers/sdcard. --- nrf5/examples/sdcard.py | 293 ---------------------------------------- 1 file changed, 293 deletions(-) delete mode 100644 nrf5/examples/sdcard.py diff --git a/nrf5/examples/sdcard.py b/nrf5/examples/sdcard.py deleted file mode 100644 index 91cb79fbb2..0000000000 --- a/nrf5/examples/sdcard.py +++ /dev/null @@ -1,293 +0,0 @@ -""" -Micro Python driver for SD cards using SPI bus. - -Requires an SPI bus and a CS pin. Provides readblocks and writeblocks -methods so the device can be mounted as a filesystem. - -Example usage on pyboard: - - import pyb, sdcard, os - sd = sdcard.SDCard(pyb.SPI(1), pyb.Pin.board.X5) - pyb.mount(sd, '/sd2') - os.listdir('/') - -Example usage on ESP8266: - - import machine, sdcard, os - sd = sdcard.SDCard(machine.SPI(0), machine.Pin(15)) - os.umount() - os.VfsFat(sd, "") - os.listdir() - -Example usage on NRF52832: - - import os, machine, sdcard - sd = sdcard.SDCard(machine.SPI(0), machine.Pin("A22", mode=machine.Pin.OUT)) - os.mount(sd, "") - os.listdir() - -Direct wireing on SD card (SPI): -# ______________________________ -# | \ -# | 9. | NC | \ -# | 1. | ~CS | | -# | 2. | MOSI | | -# | 3. | GND | | -# | 4. | VCC3.3| | -# | 5. | SCK | | -# | 6. | GND | | -# | 7. | MISO | | -# | 8. | NC | | -# | | -# --------------------------------- - -""" - -import time - - -_CMD_TIMEOUT = const(100) - -_R1_IDLE_STATE = const(1 << 0) -#R1_ERASE_RESET = const(1 << 1) -_R1_ILLEGAL_COMMAND = const(1 << 2) -#R1_COM_CRC_ERROR = const(1 << 3) -#R1_ERASE_SEQUENCE_ERROR = const(1 << 4) -#R1_ADDRESS_ERROR = const(1 << 5) -#R1_PARAMETER_ERROR = const(1 << 6) -_TOKEN_CMD25 = const(0xfc) -_TOKEN_STOP_TRAN = const(0xfd) -_TOKEN_DATA = const(0xfe) - - -class SDCard: - def __init__(self, spi, cs): - self.spi = spi - self.cs = cs - - self.cmdbuf = bytearray(6) - self.dummybuf = bytearray(512) - for i in range(512): - self.dummybuf[i] = 0xff - self.dummybuf_memoryview = memoryview(self.dummybuf) - - # initialise the card - self.init_card() - - def init_spi(self, baudrate): - try: - master = self.spi.MASTER - except AttributeError: - # on ESP8266 - self.spi.init(baudrate=baudrate, phase=0, polarity=0) - else: - # on pyboard - self.spi.init(master, baudrate=baudrate, phase=0, polarity=0) - - def init_card(self): - # init CS pin - #self.cs.init(self.cs.OUT, value=1) - - # init SPI bus; use low data rate for initialisation - self.init_spi(100000) - - # clock card at least 100 cycles with cs high - for i in range(16): - self.spi.write(b'\xff') - - # CMD0: init card; should return _R1_IDLE_STATE (allow 5 attempts) - for _ in range(5): - if self.cmd(0, 0, 0x95) == _R1_IDLE_STATE: - break - else: - raise OSError("no SD card") - - # CMD8: determine card version - r = self.cmd(8, 0x01aa, 0x87, 4) - if r == _R1_IDLE_STATE: - self.init_card_v2() - elif r == (_R1_IDLE_STATE | _R1_ILLEGAL_COMMAND): - self.init_card_v1() - else: - raise OSError("couldn't determine SD card version") - - # get the number of sectors - # CMD9: response R2 (R1 byte + 16-byte block read) - if self.cmd(9, 0, 0, 0, False) != 0: - raise OSError("no response from SD card") - csd = bytearray(16) - self.readinto(csd) - if csd[0] & 0xc0 != 0x40: - raise OSError("SD card CSD format not supported") - self.sectors = ((csd[8] << 8 | csd[9]) + 1) * 2014 - #print('sectors', self.sectors) - - # CMD16: set block length to 512 bytes - if self.cmd(16, 512, 0) != 0: - raise OSError("can't set 512 block size") - - # set to high data rate now that it's initialised - self.init_spi(1320000) - - def init_card_v1(self): - for i in range(_CMD_TIMEOUT): - self.cmd(55, 0, 0) - if self.cmd(41, 0, 0) == 0: - self.cdv = 512 - #print("[SDCard] v1 card") - return - raise OSError("timeout waiting for v1 card") - - def init_card_v2(self): - for i in range(_CMD_TIMEOUT): - time.sleep_ms(50) - self.cmd(58, 0, 0, 4) - self.cmd(55, 0, 0) - if self.cmd(41, 0x40000000, 0) == 0: - self.cmd(58, 0, 0, 4) - self.cdv = 1 - #print("[SDCard] v2 card") - return - raise OSError("timeout waiting for v2 card") - - def cmd(self, cmd, arg, crc, final=0, release=True): - self.cs.low() - - # create and send the command - buf = self.cmdbuf - buf[0] = 0x40 | cmd - buf[1] = arg >> 24 - buf[2] = arg >> 16 - buf[3] = arg >> 8 - buf[4] = arg - buf[5] = crc - self.spi.write(buf) - - # wait for the repsonse (response[7] == 0) - for i in range(_CMD_TIMEOUT): - response = self.spi.read(1, 0xff)[0] - if not (response & 0x80): - # this could be a big-endian integer that we are getting here - for j in range(final): - self.spi.write(b'\xff') - if release: - self.cs.high() - self.spi.write(b'\xff') - return response - - # timeout - self.cs.high() - self.spi.write(b'\xff') - return -1 - - def cmd_nodata(self, cmd): - self.spi.write(cmd) - self.spi.read(1, 0xff) # ignore stuff byte - for _ in range(_CMD_TIMEOUT): - if self.spi.read(1, 0xff)[0] == 0xff: - self.cs.high() - self.spi.write(b'\xff') - return 0 # OK - self.cs.high() - self.spi.write(b'\xff') - return 1 # timeout - - def readinto(self, buf): - self.cs.low() - - # read until start byte (0xff) - while self.spi.read(1, 0xff)[0] != 0xfe: - pass - - # read data - mv = self.dummybuf_memoryview[:len(buf)] - self.spi.write_readinto(mv, buf) - - # read checksum - self.spi.write(b'\xff') - self.spi.write(b'\xff') - - self.cs.high() - self.spi.write(b'\xff') - - def write(self, token, buf): - self.cs.low() - - # send: start of block, data, checksum - self.spi.read(1, token) - self.spi.write(buf) - self.spi.write(b'\xff') - self.spi.write(b'\xff') - - # check the response - if (self.spi.read(1, 0xff)[0] & 0x1f) != 0x05: - self.cs.high() - self.spi.write(b'\xff') - return - - # wait for write to finish - while self.spi.read(1, 0xff)[0] == 0: - pass - - self.cs.high() - self.spi.write(b'\xff') - - def write_token(self, token): - self.cs.low() - self.spi.read(1, token) - self.spi.write(b'\xff') - # wait for write to finish - while self.spi.read(1, 0xff)[0] == 0x00: - pass - - self.cs.high() - self.spi.write(b'\xff') - - def count(self): - return self.sectors - - def readblocks(self, block_num, buf): - nblocks, err = divmod(len(buf), 512) - assert nblocks and not err, 'Buffer length is invalid' - if nblocks == 1: - # CMD17: set read address for single block - if self.cmd(17, block_num * self.cdv, 0) != 0: - return 1 - # receive the data - self.readinto(buf) - else: - # CMD18: set read address for multiple blocks - if self.cmd(18, block_num * self.cdv, 0) != 0: - return 1 - offset = 0 - mv = memoryview(buf) - while nblocks: - self.readinto(mv[offset : offset + 512]) - offset += 512 - nblocks -= 1 - return self.cmd_nodata(b'\x0c') # cmd 12 - return 0 - - def writeblocks(self, block_num, buf): - nblocks, err = divmod(len(buf), 512) - assert nblocks and not err, 'Buffer length is invalid' - if nblocks == 1: - # CMD24: set write address for single block - if self.cmd(24, block_num * self.cdv, 0) != 0: - return 1 - - # send the data - self.write(_TOKEN_DATA, buf) - else: - # CMD25: set write address for first block - if self.cmd(25, block_num * self.cdv, 0) != 0: - return 1 - # send the data - offset = 0 - mv = memoryview(buf) - while nblocks: - self.write(_TOKEN_CMD25, mv[offset : offset + 512]) - offset += 512 - nblocks -= 1 - self.write_token(_TOKEN_STOP_TRAN) - return 0 From 391cb3ebe8aa7f0dbbfecf56f47598086ce6b565 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 6 Jun 2017 22:17:35 +0200 Subject: [PATCH 775/809] nrf5/examples: Updating mountsd example with comment from deleted sdcard.py on how to wire SD directly to SPI. --- nrf5/examples/mountsd.py | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/nrf5/examples/mountsd.py b/nrf5/examples/mountsd.py index e449a692dc..1577221a62 100644 --- a/nrf5/examples/mountsd.py +++ b/nrf5/examples/mountsd.py @@ -1,8 +1,35 @@ +""" + +Example for pca10040 / nrf52832 to show how mount +and list a sdcard connected over SPI. + + +Direct wireing on SD card (SPI): + ______________________________ + | \ + | 9. | NC | \ + | 1. | ~CS | | + | 2. | MOSI | | + | 3. | GND | | + | 4. | VCC3.3| | + | 5. | SCK | | + | 6. | GND | | + | 7. | MISO | | + | 8. | NC | | + | | + --------------------------------- +""" + import os from machine import SPI, Pin from sdcard import SDCard -def mount_sd(): - sd = SDCard(SPI(0), Pin("A22", mode=Pin.OUT)) +def mnt(): + cs = Pin("A22", mode=Pin.OUT) + sd = SDCard(SPI(0), cs) os.mount(sd, '/') +def list(): + files = os.listdir() + print(files) + From e5802fd9f8103e4b0e648398103eb7a538fc6cbe Mon Sep 17 00:00:00 2001 From: Daniel Tralamazza Date: Wed, 7 Jun 2017 18:56:20 +0200 Subject: [PATCH 776/809] implement #50 --- {nrf5 => nrf}/.gitignore | 0 {nrf5 => nrf}/Makefile | 0 {nrf5 => nrf}/README.md | 4 ++-- {nrf5 => nrf}/bluetooth_conf.h | 0 {nrf5 => nrf}/boards/common.ld | 0 {nrf5 => nrf}/boards/feather52/custom_nrf52832_dfu_app.ld | 0 {nrf5 => nrf}/boards/feather52/mpconfigboard.h | 0 {nrf5 => nrf}/boards/feather52/mpconfigboard.mk | 0 {nrf5 => nrf}/boards/feather52/mpconfigboard_s132.mk | 0 {nrf5 => nrf}/boards/feather52/nrf52_hal_conf.h | 0 {nrf5 => nrf}/boards/feather52/pins.csv | 0 {nrf5 => nrf}/boards/make-pins.py | 0 {nrf5 => nrf}/boards/microbit/mpconfigboard.h | 0 {nrf5 => nrf}/boards/microbit/mpconfigboard.mk | 0 {nrf5 => nrf}/boards/microbit/mpconfigboard_s110.mk | 0 {nrf5 => nrf}/boards/microbit/nrf51_hal_conf.h | 0 {nrf5 => nrf}/boards/microbit/pins.csv | 0 {nrf5 => nrf}/boards/nrf51_prefix.c | 0 {nrf5 => nrf}/boards/nrf51x22_256k_16k.ld | 0 {nrf5 => nrf}/boards/nrf51x22_256k_16k_s110_8.0.0.ld | 0 {nrf5 => nrf}/boards/nrf51x22_256k_32k.ld | 0 {nrf5 => nrf}/boards/nrf51x22_256k_32k_s110_8.0.0.ld | 0 {nrf5 => nrf}/boards/nrf51x22_256k_32k_s120_2.1.0.ld | 0 {nrf5 => nrf}/boards/nrf51x22_256k_32k_s130_2.0.1.ld | 0 {nrf5 => nrf}/boards/nrf52832_512k_64k.ld | 0 {nrf5 => nrf}/boards/nrf52832_512k_64k_s132_2.0.1.ld | 0 {nrf5 => nrf}/boards/nrf52832_512k_64k_s132_3.0.0.ld | 0 {nrf5 => nrf}/boards/nrf52840_1M_256k.ld | 0 {nrf5 => nrf}/boards/nrf52_prefix.c | 0 {nrf5 => nrf}/boards/pca10000/mpconfigboard.h | 0 {nrf5 => nrf}/boards/pca10000/mpconfigboard.mk | 0 {nrf5 => nrf}/boards/pca10000/mpconfigboard_s110.mk | 0 {nrf5 => nrf}/boards/pca10000/nrf51_hal_conf.h | 0 {nrf5 => nrf}/boards/pca10000/pins.csv | 0 {nrf5 => nrf}/boards/pca10001/mpconfigboard.h | 0 {nrf5 => nrf}/boards/pca10001/mpconfigboard.mk | 0 {nrf5 => nrf}/boards/pca10001/mpconfigboard_s110.mk | 0 {nrf5 => nrf}/boards/pca10001/nrf51_hal_conf.h | 0 {nrf5 => nrf}/boards/pca10001/pins.csv | 0 {nrf5 => nrf}/boards/pca10028/mpconfigboard.h | 0 {nrf5 => nrf}/boards/pca10028/mpconfigboard.mk | 0 {nrf5 => nrf}/boards/pca10028/mpconfigboard_s110.mk | 0 {nrf5 => nrf}/boards/pca10028/mpconfigboard_s120.mk | 0 {nrf5 => nrf}/boards/pca10028/mpconfigboard_s130.mk | 0 {nrf5 => nrf}/boards/pca10028/nrf51_hal_conf.h | 0 {nrf5 => nrf}/boards/pca10028/pins.csv | 0 {nrf5 => nrf}/boards/pca10031/mpconfigboard.h | 0 {nrf5 => nrf}/boards/pca10031/mpconfigboard.mk | 0 {nrf5 => nrf}/boards/pca10031/mpconfigboard_s110.mk | 0 {nrf5 => nrf}/boards/pca10031/mpconfigboard_s120.mk | 0 {nrf5 => nrf}/boards/pca10031/mpconfigboard_s130.mk | 0 {nrf5 => nrf}/boards/pca10031/nrf51_hal_conf.h | 0 {nrf5 => nrf}/boards/pca10031/pins.csv | 0 {nrf5 => nrf}/boards/pca10040/mpconfigboard.h | 0 {nrf5 => nrf}/boards/pca10040/mpconfigboard.mk | 0 {nrf5 => nrf}/boards/pca10040/mpconfigboard_s132.mk | 0 {nrf5 => nrf}/boards/pca10040/nrf52_hal_conf.h | 0 {nrf5 => nrf}/boards/pca10040/pins.csv | 0 {nrf5 => nrf}/boards/pca10056/mpconfigboard.h | 0 {nrf5 => nrf}/boards/pca10056/mpconfigboard.mk | 0 {nrf5 => nrf}/boards/pca10056/nrf52_hal_conf.h | 0 {nrf5 => nrf}/boards/pca10056/pins.csv | 0 {nrf5 => nrf}/builtin_open.c | 0 {nrf5 => nrf}/device/compiler_abstraction.h | 0 {nrf5 => nrf}/device/nrf.h | 0 {nrf5 => nrf}/device/nrf51/nrf51.h | 0 {nrf5 => nrf}/device/nrf51/nrf51_bitfields.h | 0 {nrf5 => nrf}/device/nrf51/nrf51_deprecated.h | 0 {nrf5 => nrf}/device/nrf51/startup_nrf51822.c | 0 {nrf5 => nrf}/device/nrf51/system_nrf51.h | 0 {nrf5 => nrf}/device/nrf51/system_nrf51822.c | 0 {nrf5 => nrf}/device/nrf52/nrf51_to_nrf52.h | 0 {nrf5 => nrf}/device/nrf52/nrf51_to_nrf52840.h | 0 {nrf5 => nrf}/device/nrf52/nrf52.h | 0 {nrf5 => nrf}/device/nrf52/nrf52840.h | 0 {nrf5 => nrf}/device/nrf52/nrf52840_bitfields.h | 0 {nrf5 => nrf}/device/nrf52/nrf52_bitfields.h | 0 {nrf5 => nrf}/device/nrf52/nrf52_name_change.h | 0 {nrf5 => nrf}/device/nrf52/nrf52_to_nrf52840.h | 0 {nrf5 => nrf}/device/nrf52/startup_nrf52832.c | 0 {nrf5 => nrf}/device/nrf52/startup_nrf52840.c | 0 {nrf5 => nrf}/device/nrf52/system_nrf52.h | 0 {nrf5 => nrf}/device/nrf52/system_nrf52832.c | 0 {nrf5 => nrf}/device/nrf52/system_nrf52840.c | 0 {nrf5 => nrf}/device/nrf52/system_nrf52840.h | 0 {nrf5 => nrf}/drivers/bluetooth/ble_drv.c | 0 {nrf5 => nrf}/drivers/bluetooth/ble_drv.h | 0 {nrf5 => nrf}/drivers/bluetooth/ble_uart.c | 0 {nrf5 => nrf}/drivers/bluetooth/ble_uart.h | 0 {nrf5 => nrf}/drivers/bluetooth/bluetooth_common.mk | 0 {nrf5 => nrf}/drivers/bluetooth/download_ble_stack.sh | 0 {nrf5 => nrf}/drivers/bluetooth/ringbuffer.h | 0 {nrf5 => nrf}/drivers/softpwm.c | 0 {nrf5 => nrf}/drivers/softpwm.h | 0 {nrf5 => nrf}/drivers/ticker.c | 0 {nrf5 => nrf}/drivers/ticker.h | 0 {nrf5 => nrf}/examples/mountsd.py | 0 {nrf5 => nrf}/examples/musictest.py | 0 {nrf5 => nrf}/examples/nrf52_pwm.py | 0 {nrf5 => nrf}/examples/nrf52_servo.py | 0 {nrf5 => nrf}/examples/powerup.py | 0 {nrf5 => nrf}/examples/seeed_tft.py | 0 {nrf5 => nrf}/examples/ssd1306_mod.py | 2 +- {nrf5 => nrf}/examples/ubluepy_eddystone.py | 0 {nrf5 => nrf}/examples/ubluepy_scan.py | 0 {nrf5 => nrf}/fatfs_port.c | 0 {nrf5 => nrf}/font_petme128_8x8.h | 0 {nrf5 => nrf}/freeze/test.py | 0 {nrf5 => nrf}/gccollect.c | 0 {nrf5 => nrf}/gccollect.h | 0 {nrf5 => nrf}/hal/hal_adc.c | 0 {nrf5 => nrf}/hal/hal_adc.h | 0 {nrf5 => nrf}/hal/hal_adce.c | 0 {nrf5 => nrf}/hal/hal_gpio.c | 0 {nrf5 => nrf}/hal/hal_gpio.h | 0 {nrf5 => nrf}/hal/hal_irq.h | 0 {nrf5 => nrf}/hal/hal_pwm.c | 0 {nrf5 => nrf}/hal/hal_pwm.h | 0 {nrf5 => nrf}/hal/hal_qspie.c | 0 {nrf5 => nrf}/hal/hal_qspie.h | 0 {nrf5 => nrf}/hal/hal_rtc.c | 0 {nrf5 => nrf}/hal/hal_rtc.h | 0 {nrf5 => nrf}/hal/hal_spi.c | 0 {nrf5 => nrf}/hal/hal_spi.h | 0 {nrf5 => nrf}/hal/hal_spie.c | 0 {nrf5 => nrf}/hal/hal_temp.c | 0 {nrf5 => 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nrf}/modules/ubluepy/ubluepy_descriptor.c | 0 {nrf5 => nrf}/modules/ubluepy/ubluepy_peripheral.c | 0 {nrf5 => nrf}/modules/ubluepy/ubluepy_scan_entry.c | 0 {nrf5 => nrf}/modules/ubluepy/ubluepy_scanner.c | 0 {nrf5 => nrf}/modules/ubluepy/ubluepy_service.c | 0 {nrf5 => nrf}/modules/ubluepy/ubluepy_uuid.c | 0 {nrf5 => nrf}/modules/uos/moduos.c | 0 {nrf5 => nrf}/modules/utime/modutime.c | 0 {nrf5 => nrf}/mpconfigport.h | 0 {nrf5 => nrf}/mphalport.c | 0 {nrf5 => nrf}/mphalport.h | 0 {nrf5 => nrf}/nrf51_af.csv | 0 {nrf5 => nrf}/nrf52_af.csv | 0 {nrf5 => nrf}/pin_defs_nrf5.h | 2 +- {nrf5 => nrf}/pin_named_pins.c | 0 {nrf5 => nrf}/qstrdefsport.h | 0 191 files changed, 4 insertions(+), 4 deletions(-) rename {nrf5 => nrf}/.gitignore (100%) rename {nrf5 => nrf}/Makefile (100%) rename {nrf5 => nrf}/README.md (97%) rename {nrf5 => nrf}/bluetooth_conf.h (100%) rename {nrf5 => nrf}/boards/common.ld (100%) rename {nrf5 => nrf}/boards/feather52/custom_nrf52832_dfu_app.ld (100%) rename {nrf5 => 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nrf}/hal/hal_adc.c (100%) rename {nrf5 => nrf}/hal/hal_adc.h (100%) rename {nrf5 => nrf}/hal/hal_adce.c (100%) rename {nrf5 => nrf}/hal/hal_gpio.c (100%) rename {nrf5 => nrf}/hal/hal_gpio.h (100%) rename {nrf5 => nrf}/hal/hal_irq.h (100%) rename {nrf5 => nrf}/hal/hal_pwm.c (100%) rename {nrf5 => nrf}/hal/hal_pwm.h (100%) rename {nrf5 => nrf}/hal/hal_qspie.c (100%) rename {nrf5 => nrf}/hal/hal_qspie.h (100%) rename {nrf5 => nrf}/hal/hal_rtc.c (100%) rename {nrf5 => nrf}/hal/hal_rtc.h (100%) rename {nrf5 => nrf}/hal/hal_spi.c (100%) rename {nrf5 => nrf}/hal/hal_spi.h (100%) rename {nrf5 => nrf}/hal/hal_spie.c (100%) rename {nrf5 => nrf}/hal/hal_temp.c (100%) rename {nrf5 => nrf}/hal/hal_temp.h (100%) rename {nrf5 => nrf}/hal/hal_time.c (100%) rename {nrf5 => nrf}/hal/hal_time.h (100%) rename {nrf5 => nrf}/hal/hal_timer.c (100%) rename {nrf5 => nrf}/hal/hal_timer.h (100%) rename {nrf5 => nrf}/hal/hal_twi.c (100%) rename {nrf5 => nrf}/hal/hal_twi.h (100%) rename {nrf5 => nrf}/hal/hal_twie.c (100%) rename {nrf5 => nrf}/hal/hal_uart.c (100%) rename {nrf5 => nrf}/hal/hal_uart.h (100%) rename {nrf5 => nrf}/hal/hal_uarte.c (100%) rename {nrf5 => nrf}/hal/nrf51_hal.h (100%) rename {nrf5 => nrf}/hal/nrf52_hal.h (100%) rename {nrf5 => nrf}/help.c (100%) rename {nrf5 => nrf}/main.c (100%) rename {nrf5 => nrf}/modules/ble/help_sd.h (100%) rename {nrf5 => nrf}/modules/ble/modble.c (100%) rename {nrf5 => nrf}/modules/machine/adc.c (100%) rename {nrf5 => nrf}/modules/machine/adc.h (100%) rename {nrf5 => nrf}/modules/machine/i2c.c (100%) rename {nrf5 => nrf}/modules/machine/i2c.h (100%) rename {nrf5 => nrf}/modules/machine/led.c (100%) rename {nrf5 => nrf}/modules/machine/led.h (100%) rename {nrf5 => nrf}/modules/machine/modmachine.c (100%) rename {nrf5 => nrf}/modules/machine/modmachine.h (100%) rename {nrf5 => nrf}/modules/machine/pin.c (100%) rename {nrf5 => nrf}/modules/machine/pin.h (100%) rename {nrf5 => nrf}/modules/machine/pwm.c (100%) rename {nrf5 => nrf}/modules/machine/pwm.h (100%) rename {nrf5 => nrf}/modules/machine/rtc.c (100%) rename {nrf5 => nrf}/modules/machine/rtc.h (100%) rename {nrf5 => nrf}/modules/machine/spi.c (100%) rename {nrf5 => nrf}/modules/machine/spi.h (100%) rename {nrf5 => nrf}/modules/machine/temp.c (100%) rename {nrf5 => nrf}/modules/machine/temp.h (100%) rename {nrf5 => nrf}/modules/machine/timer.c (100%) rename {nrf5 => nrf}/modules/machine/timer.h (100%) rename {nrf5 => nrf}/modules/machine/uart.c (100%) rename {nrf5 => nrf}/modules/machine/uart.h (100%) rename {nrf5 => nrf}/modules/music/modmusic.c (100%) rename {nrf5 => nrf}/modules/music/modmusic.h (100%) rename {nrf5 => nrf}/modules/music/musictunes.c (100%) rename {nrf5 => nrf}/modules/music/musictunes.h (100%) rename {nrf5 => nrf}/modules/pyb/modpyb.c (100%) rename {nrf5 => nrf}/modules/ubluepy/modubluepy.c (100%) rename {nrf5 => nrf}/modules/ubluepy/modubluepy.h (100%) rename {nrf5 => nrf}/modules/ubluepy/ubluepy_characteristic.c (100%) rename {nrf5 => nrf}/modules/ubluepy/ubluepy_constants.c (100%) rename {nrf5 => nrf}/modules/ubluepy/ubluepy_delegate.c (100%) rename {nrf5 => nrf}/modules/ubluepy/ubluepy_descriptor.c (100%) rename {nrf5 => nrf}/modules/ubluepy/ubluepy_peripheral.c (100%) rename {nrf5 => nrf}/modules/ubluepy/ubluepy_scan_entry.c (100%) rename {nrf5 => nrf}/modules/ubluepy/ubluepy_scanner.c (100%) rename {nrf5 => nrf}/modules/ubluepy/ubluepy_service.c (100%) rename {nrf5 => nrf}/modules/ubluepy/ubluepy_uuid.c (100%) rename {nrf5 => nrf}/modules/uos/moduos.c (100%) rename {nrf5 => nrf}/modules/utime/modutime.c (100%) rename {nrf5 => nrf}/mpconfigport.h (100%) rename {nrf5 => nrf}/mphalport.c (100%) rename {nrf5 => nrf}/mphalport.h (100%) rename {nrf5 => nrf}/nrf51_af.csv (100%) rename {nrf5 => nrf}/nrf52_af.csv (100%) rename {nrf5 => nrf}/pin_defs_nrf5.h (99%) rename {nrf5 => nrf}/pin_named_pins.c (100%) rename {nrf5 => nrf}/qstrdefsport.h (100%) diff --git a/nrf5/.gitignore b/nrf/.gitignore similarity index 100% rename from nrf5/.gitignore rename to nrf/.gitignore diff --git a/nrf5/Makefile b/nrf/Makefile similarity index 100% rename from nrf5/Makefile rename to nrf/Makefile diff --git a/nrf5/README.md b/nrf/README.md similarity index 97% rename from nrf5/README.md rename to nrf/README.md index 75fb9281dc..0bfc524cbf 100644 --- a/nrf5/README.md +++ b/nrf/README.md @@ -37,14 +37,14 @@ This is a port of MicroPython to the Nordic nRF5 series of chips. ## Compile and Flash -Prerequisite steps for building the nrf5 port: +Prerequisite steps for building the nrf port: git clone .git micropython cd micropython git submodule update --init make -C mpy-cross -By default PCA10040 (nrf52832) is used as compile target. To build and flash issue the following command inside the nrf5/ folder: +By default PCA10040 (nrf52832) is used as compile target. To build and flash issue the following command inside the nrf/ folder: make make flash diff --git a/nrf5/bluetooth_conf.h b/nrf/bluetooth_conf.h similarity index 100% rename from nrf5/bluetooth_conf.h rename to nrf/bluetooth_conf.h diff --git a/nrf5/boards/common.ld b/nrf/boards/common.ld similarity index 100% rename from nrf5/boards/common.ld rename to nrf/boards/common.ld diff --git a/nrf5/boards/feather52/custom_nrf52832_dfu_app.ld b/nrf/boards/feather52/custom_nrf52832_dfu_app.ld similarity index 100% rename from nrf5/boards/feather52/custom_nrf52832_dfu_app.ld rename to nrf/boards/feather52/custom_nrf52832_dfu_app.ld diff --git a/nrf5/boards/feather52/mpconfigboard.h b/nrf/boards/feather52/mpconfigboard.h similarity index 100% rename from nrf5/boards/feather52/mpconfigboard.h rename to nrf/boards/feather52/mpconfigboard.h diff --git a/nrf5/boards/feather52/mpconfigboard.mk b/nrf/boards/feather52/mpconfigboard.mk similarity index 100% rename from nrf5/boards/feather52/mpconfigboard.mk rename to nrf/boards/feather52/mpconfigboard.mk diff --git a/nrf5/boards/feather52/mpconfigboard_s132.mk b/nrf/boards/feather52/mpconfigboard_s132.mk similarity index 100% rename from nrf5/boards/feather52/mpconfigboard_s132.mk rename to nrf/boards/feather52/mpconfigboard_s132.mk diff --git a/nrf5/boards/feather52/nrf52_hal_conf.h b/nrf/boards/feather52/nrf52_hal_conf.h similarity index 100% rename from nrf5/boards/feather52/nrf52_hal_conf.h rename to nrf/boards/feather52/nrf52_hal_conf.h diff --git a/nrf5/boards/feather52/pins.csv b/nrf/boards/feather52/pins.csv similarity index 100% rename from nrf5/boards/feather52/pins.csv rename to nrf/boards/feather52/pins.csv diff --git a/nrf5/boards/make-pins.py b/nrf/boards/make-pins.py similarity index 100% rename from nrf5/boards/make-pins.py rename to nrf/boards/make-pins.py diff --git a/nrf5/boards/microbit/mpconfigboard.h b/nrf/boards/microbit/mpconfigboard.h similarity index 100% rename from nrf5/boards/microbit/mpconfigboard.h rename to nrf/boards/microbit/mpconfigboard.h diff --git a/nrf5/boards/microbit/mpconfigboard.mk b/nrf/boards/microbit/mpconfigboard.mk similarity index 100% rename from nrf5/boards/microbit/mpconfigboard.mk rename to nrf/boards/microbit/mpconfigboard.mk diff --git a/nrf5/boards/microbit/mpconfigboard_s110.mk b/nrf/boards/microbit/mpconfigboard_s110.mk similarity index 100% rename from nrf5/boards/microbit/mpconfigboard_s110.mk rename to nrf/boards/microbit/mpconfigboard_s110.mk diff --git a/nrf5/boards/microbit/nrf51_hal_conf.h b/nrf/boards/microbit/nrf51_hal_conf.h similarity index 100% rename from nrf5/boards/microbit/nrf51_hal_conf.h rename to nrf/boards/microbit/nrf51_hal_conf.h diff --git a/nrf5/boards/microbit/pins.csv b/nrf/boards/microbit/pins.csv similarity index 100% rename from nrf5/boards/microbit/pins.csv rename to nrf/boards/microbit/pins.csv diff --git a/nrf5/boards/nrf51_prefix.c b/nrf/boards/nrf51_prefix.c similarity index 100% rename from nrf5/boards/nrf51_prefix.c rename to nrf/boards/nrf51_prefix.c diff --git a/nrf5/boards/nrf51x22_256k_16k.ld b/nrf/boards/nrf51x22_256k_16k.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_16k.ld rename to nrf/boards/nrf51x22_256k_16k.ld diff --git a/nrf5/boards/nrf51x22_256k_16k_s110_8.0.0.ld b/nrf/boards/nrf51x22_256k_16k_s110_8.0.0.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_16k_s110_8.0.0.ld rename to nrf/boards/nrf51x22_256k_16k_s110_8.0.0.ld diff --git a/nrf5/boards/nrf51x22_256k_32k.ld b/nrf/boards/nrf51x22_256k_32k.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_32k.ld rename to nrf/boards/nrf51x22_256k_32k.ld diff --git a/nrf5/boards/nrf51x22_256k_32k_s110_8.0.0.ld b/nrf/boards/nrf51x22_256k_32k_s110_8.0.0.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_32k_s110_8.0.0.ld rename to nrf/boards/nrf51x22_256k_32k_s110_8.0.0.ld diff --git a/nrf5/boards/nrf51x22_256k_32k_s120_2.1.0.ld b/nrf/boards/nrf51x22_256k_32k_s120_2.1.0.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_32k_s120_2.1.0.ld rename to nrf/boards/nrf51x22_256k_32k_s120_2.1.0.ld diff --git a/nrf5/boards/nrf51x22_256k_32k_s130_2.0.1.ld b/nrf/boards/nrf51x22_256k_32k_s130_2.0.1.ld similarity index 100% rename from nrf5/boards/nrf51x22_256k_32k_s130_2.0.1.ld rename to nrf/boards/nrf51x22_256k_32k_s130_2.0.1.ld diff --git a/nrf5/boards/nrf52832_512k_64k.ld b/nrf/boards/nrf52832_512k_64k.ld similarity index 100% rename from nrf5/boards/nrf52832_512k_64k.ld rename to nrf/boards/nrf52832_512k_64k.ld diff --git a/nrf5/boards/nrf52832_512k_64k_s132_2.0.1.ld b/nrf/boards/nrf52832_512k_64k_s132_2.0.1.ld similarity index 100% rename from nrf5/boards/nrf52832_512k_64k_s132_2.0.1.ld rename to nrf/boards/nrf52832_512k_64k_s132_2.0.1.ld diff --git a/nrf5/boards/nrf52832_512k_64k_s132_3.0.0.ld b/nrf/boards/nrf52832_512k_64k_s132_3.0.0.ld similarity index 100% rename from nrf5/boards/nrf52832_512k_64k_s132_3.0.0.ld rename to nrf/boards/nrf52832_512k_64k_s132_3.0.0.ld diff --git a/nrf5/boards/nrf52840_1M_256k.ld b/nrf/boards/nrf52840_1M_256k.ld similarity index 100% rename from nrf5/boards/nrf52840_1M_256k.ld rename to nrf/boards/nrf52840_1M_256k.ld diff --git a/nrf5/boards/nrf52_prefix.c b/nrf/boards/nrf52_prefix.c similarity index 100% rename from nrf5/boards/nrf52_prefix.c rename to nrf/boards/nrf52_prefix.c diff --git a/nrf5/boards/pca10000/mpconfigboard.h b/nrf/boards/pca10000/mpconfigboard.h similarity index 100% rename from nrf5/boards/pca10000/mpconfigboard.h rename to nrf/boards/pca10000/mpconfigboard.h diff --git a/nrf5/boards/pca10000/mpconfigboard.mk b/nrf/boards/pca10000/mpconfigboard.mk similarity index 100% rename from nrf5/boards/pca10000/mpconfigboard.mk rename to nrf/boards/pca10000/mpconfigboard.mk diff --git a/nrf5/boards/pca10000/mpconfigboard_s110.mk b/nrf/boards/pca10000/mpconfigboard_s110.mk similarity index 100% rename from nrf5/boards/pca10000/mpconfigboard_s110.mk rename to nrf/boards/pca10000/mpconfigboard_s110.mk diff --git a/nrf5/boards/pca10000/nrf51_hal_conf.h b/nrf/boards/pca10000/nrf51_hal_conf.h similarity index 100% rename from nrf5/boards/pca10000/nrf51_hal_conf.h rename to nrf/boards/pca10000/nrf51_hal_conf.h diff --git a/nrf5/boards/pca10000/pins.csv b/nrf/boards/pca10000/pins.csv similarity index 100% rename from nrf5/boards/pca10000/pins.csv rename to nrf/boards/pca10000/pins.csv diff --git a/nrf5/boards/pca10001/mpconfigboard.h b/nrf/boards/pca10001/mpconfigboard.h similarity index 100% rename from nrf5/boards/pca10001/mpconfigboard.h rename to nrf/boards/pca10001/mpconfigboard.h diff --git a/nrf5/boards/pca10001/mpconfigboard.mk b/nrf/boards/pca10001/mpconfigboard.mk similarity index 100% rename from nrf5/boards/pca10001/mpconfigboard.mk rename to nrf/boards/pca10001/mpconfigboard.mk diff --git a/nrf5/boards/pca10001/mpconfigboard_s110.mk b/nrf/boards/pca10001/mpconfigboard_s110.mk similarity index 100% rename from nrf5/boards/pca10001/mpconfigboard_s110.mk rename to nrf/boards/pca10001/mpconfigboard_s110.mk diff --git a/nrf5/boards/pca10001/nrf51_hal_conf.h b/nrf/boards/pca10001/nrf51_hal_conf.h similarity index 100% rename from nrf5/boards/pca10001/nrf51_hal_conf.h rename to nrf/boards/pca10001/nrf51_hal_conf.h diff --git a/nrf5/boards/pca10001/pins.csv b/nrf/boards/pca10001/pins.csv similarity index 100% rename from nrf5/boards/pca10001/pins.csv rename to nrf/boards/pca10001/pins.csv diff --git a/nrf5/boards/pca10028/mpconfigboard.h b/nrf/boards/pca10028/mpconfigboard.h similarity index 100% rename from nrf5/boards/pca10028/mpconfigboard.h rename to nrf/boards/pca10028/mpconfigboard.h diff --git a/nrf5/boards/pca10028/mpconfigboard.mk b/nrf/boards/pca10028/mpconfigboard.mk similarity index 100% rename from nrf5/boards/pca10028/mpconfigboard.mk rename to nrf/boards/pca10028/mpconfigboard.mk diff --git a/nrf5/boards/pca10028/mpconfigboard_s110.mk b/nrf/boards/pca10028/mpconfigboard_s110.mk similarity index 100% rename from nrf5/boards/pca10028/mpconfigboard_s110.mk rename to nrf/boards/pca10028/mpconfigboard_s110.mk diff --git a/nrf5/boards/pca10028/mpconfigboard_s120.mk b/nrf/boards/pca10028/mpconfigboard_s120.mk similarity index 100% rename from nrf5/boards/pca10028/mpconfigboard_s120.mk rename to nrf/boards/pca10028/mpconfigboard_s120.mk diff --git a/nrf5/boards/pca10028/mpconfigboard_s130.mk b/nrf/boards/pca10028/mpconfigboard_s130.mk similarity index 100% rename from nrf5/boards/pca10028/mpconfigboard_s130.mk rename to nrf/boards/pca10028/mpconfigboard_s130.mk diff --git a/nrf5/boards/pca10028/nrf51_hal_conf.h b/nrf/boards/pca10028/nrf51_hal_conf.h similarity index 100% rename from nrf5/boards/pca10028/nrf51_hal_conf.h rename to nrf/boards/pca10028/nrf51_hal_conf.h diff --git a/nrf5/boards/pca10028/pins.csv b/nrf/boards/pca10028/pins.csv similarity index 100% rename from nrf5/boards/pca10028/pins.csv rename to nrf/boards/pca10028/pins.csv diff --git a/nrf5/boards/pca10031/mpconfigboard.h b/nrf/boards/pca10031/mpconfigboard.h similarity index 100% rename from nrf5/boards/pca10031/mpconfigboard.h rename to nrf/boards/pca10031/mpconfigboard.h diff --git a/nrf5/boards/pca10031/mpconfigboard.mk b/nrf/boards/pca10031/mpconfigboard.mk similarity index 100% rename from nrf5/boards/pca10031/mpconfigboard.mk rename to nrf/boards/pca10031/mpconfigboard.mk diff --git a/nrf5/boards/pca10031/mpconfigboard_s110.mk b/nrf/boards/pca10031/mpconfigboard_s110.mk similarity index 100% rename from nrf5/boards/pca10031/mpconfigboard_s110.mk rename to nrf/boards/pca10031/mpconfigboard_s110.mk diff --git a/nrf5/boards/pca10031/mpconfigboard_s120.mk b/nrf/boards/pca10031/mpconfigboard_s120.mk similarity index 100% rename from nrf5/boards/pca10031/mpconfigboard_s120.mk rename to nrf/boards/pca10031/mpconfigboard_s120.mk diff --git a/nrf5/boards/pca10031/mpconfigboard_s130.mk b/nrf/boards/pca10031/mpconfigboard_s130.mk similarity index 100% rename from nrf5/boards/pca10031/mpconfigboard_s130.mk rename to nrf/boards/pca10031/mpconfigboard_s130.mk diff --git a/nrf5/boards/pca10031/nrf51_hal_conf.h b/nrf/boards/pca10031/nrf51_hal_conf.h similarity index 100% rename from nrf5/boards/pca10031/nrf51_hal_conf.h rename to nrf/boards/pca10031/nrf51_hal_conf.h diff --git a/nrf5/boards/pca10031/pins.csv b/nrf/boards/pca10031/pins.csv similarity index 100% rename from nrf5/boards/pca10031/pins.csv rename to nrf/boards/pca10031/pins.csv diff --git a/nrf5/boards/pca10040/mpconfigboard.h b/nrf/boards/pca10040/mpconfigboard.h similarity index 100% rename from nrf5/boards/pca10040/mpconfigboard.h rename to nrf/boards/pca10040/mpconfigboard.h diff --git a/nrf5/boards/pca10040/mpconfigboard.mk b/nrf/boards/pca10040/mpconfigboard.mk similarity index 100% rename from nrf5/boards/pca10040/mpconfigboard.mk rename to nrf/boards/pca10040/mpconfigboard.mk diff --git a/nrf5/boards/pca10040/mpconfigboard_s132.mk b/nrf/boards/pca10040/mpconfigboard_s132.mk similarity index 100% rename from nrf5/boards/pca10040/mpconfigboard_s132.mk rename to nrf/boards/pca10040/mpconfigboard_s132.mk diff --git a/nrf5/boards/pca10040/nrf52_hal_conf.h b/nrf/boards/pca10040/nrf52_hal_conf.h similarity index 100% rename from nrf5/boards/pca10040/nrf52_hal_conf.h rename to nrf/boards/pca10040/nrf52_hal_conf.h diff --git a/nrf5/boards/pca10040/pins.csv b/nrf/boards/pca10040/pins.csv similarity index 100% rename from nrf5/boards/pca10040/pins.csv rename to nrf/boards/pca10040/pins.csv diff --git a/nrf5/boards/pca10056/mpconfigboard.h b/nrf/boards/pca10056/mpconfigboard.h similarity index 100% rename from nrf5/boards/pca10056/mpconfigboard.h rename to nrf/boards/pca10056/mpconfigboard.h diff --git a/nrf5/boards/pca10056/mpconfigboard.mk b/nrf/boards/pca10056/mpconfigboard.mk similarity index 100% rename from nrf5/boards/pca10056/mpconfigboard.mk rename to nrf/boards/pca10056/mpconfigboard.mk diff --git a/nrf5/boards/pca10056/nrf52_hal_conf.h b/nrf/boards/pca10056/nrf52_hal_conf.h similarity index 100% rename from nrf5/boards/pca10056/nrf52_hal_conf.h rename to nrf/boards/pca10056/nrf52_hal_conf.h diff --git a/nrf5/boards/pca10056/pins.csv b/nrf/boards/pca10056/pins.csv similarity index 100% rename from nrf5/boards/pca10056/pins.csv rename to nrf/boards/pca10056/pins.csv diff --git a/nrf5/builtin_open.c b/nrf/builtin_open.c similarity index 100% rename from nrf5/builtin_open.c rename to nrf/builtin_open.c diff --git a/nrf5/device/compiler_abstraction.h b/nrf/device/compiler_abstraction.h similarity index 100% rename from nrf5/device/compiler_abstraction.h rename to nrf/device/compiler_abstraction.h diff --git a/nrf5/device/nrf.h b/nrf/device/nrf.h similarity index 100% rename from nrf5/device/nrf.h rename to nrf/device/nrf.h diff --git a/nrf5/device/nrf51/nrf51.h b/nrf/device/nrf51/nrf51.h similarity index 100% rename from nrf5/device/nrf51/nrf51.h rename to nrf/device/nrf51/nrf51.h diff --git a/nrf5/device/nrf51/nrf51_bitfields.h b/nrf/device/nrf51/nrf51_bitfields.h similarity index 100% rename from nrf5/device/nrf51/nrf51_bitfields.h rename to nrf/device/nrf51/nrf51_bitfields.h diff --git a/nrf5/device/nrf51/nrf51_deprecated.h b/nrf/device/nrf51/nrf51_deprecated.h similarity index 100% rename from nrf5/device/nrf51/nrf51_deprecated.h rename to nrf/device/nrf51/nrf51_deprecated.h diff --git a/nrf5/device/nrf51/startup_nrf51822.c b/nrf/device/nrf51/startup_nrf51822.c similarity index 100% rename from nrf5/device/nrf51/startup_nrf51822.c rename to nrf/device/nrf51/startup_nrf51822.c diff --git a/nrf5/device/nrf51/system_nrf51.h b/nrf/device/nrf51/system_nrf51.h similarity index 100% rename from nrf5/device/nrf51/system_nrf51.h rename to nrf/device/nrf51/system_nrf51.h diff --git a/nrf5/device/nrf51/system_nrf51822.c b/nrf/device/nrf51/system_nrf51822.c similarity index 100% rename from nrf5/device/nrf51/system_nrf51822.c rename to nrf/device/nrf51/system_nrf51822.c diff --git a/nrf5/device/nrf52/nrf51_to_nrf52.h b/nrf/device/nrf52/nrf51_to_nrf52.h similarity index 100% rename from nrf5/device/nrf52/nrf51_to_nrf52.h rename to nrf/device/nrf52/nrf51_to_nrf52.h diff --git a/nrf5/device/nrf52/nrf51_to_nrf52840.h b/nrf/device/nrf52/nrf51_to_nrf52840.h similarity index 100% rename from nrf5/device/nrf52/nrf51_to_nrf52840.h rename to nrf/device/nrf52/nrf51_to_nrf52840.h diff --git a/nrf5/device/nrf52/nrf52.h b/nrf/device/nrf52/nrf52.h similarity index 100% rename from nrf5/device/nrf52/nrf52.h rename to nrf/device/nrf52/nrf52.h diff --git a/nrf5/device/nrf52/nrf52840.h b/nrf/device/nrf52/nrf52840.h similarity index 100% rename from nrf5/device/nrf52/nrf52840.h rename to nrf/device/nrf52/nrf52840.h diff --git a/nrf5/device/nrf52/nrf52840_bitfields.h b/nrf/device/nrf52/nrf52840_bitfields.h similarity index 100% rename from nrf5/device/nrf52/nrf52840_bitfields.h rename to nrf/device/nrf52/nrf52840_bitfields.h diff --git a/nrf5/device/nrf52/nrf52_bitfields.h b/nrf/device/nrf52/nrf52_bitfields.h similarity index 100% rename from nrf5/device/nrf52/nrf52_bitfields.h rename to nrf/device/nrf52/nrf52_bitfields.h diff --git a/nrf5/device/nrf52/nrf52_name_change.h b/nrf/device/nrf52/nrf52_name_change.h similarity index 100% rename from nrf5/device/nrf52/nrf52_name_change.h rename to nrf/device/nrf52/nrf52_name_change.h diff --git a/nrf5/device/nrf52/nrf52_to_nrf52840.h b/nrf/device/nrf52/nrf52_to_nrf52840.h similarity index 100% rename from nrf5/device/nrf52/nrf52_to_nrf52840.h rename to nrf/device/nrf52/nrf52_to_nrf52840.h diff --git a/nrf5/device/nrf52/startup_nrf52832.c b/nrf/device/nrf52/startup_nrf52832.c similarity index 100% rename from nrf5/device/nrf52/startup_nrf52832.c rename to nrf/device/nrf52/startup_nrf52832.c diff --git a/nrf5/device/nrf52/startup_nrf52840.c b/nrf/device/nrf52/startup_nrf52840.c similarity index 100% rename from nrf5/device/nrf52/startup_nrf52840.c rename to nrf/device/nrf52/startup_nrf52840.c diff --git a/nrf5/device/nrf52/system_nrf52.h b/nrf/device/nrf52/system_nrf52.h similarity index 100% rename from nrf5/device/nrf52/system_nrf52.h rename to nrf/device/nrf52/system_nrf52.h diff --git a/nrf5/device/nrf52/system_nrf52832.c b/nrf/device/nrf52/system_nrf52832.c similarity index 100% rename from nrf5/device/nrf52/system_nrf52832.c rename to nrf/device/nrf52/system_nrf52832.c diff --git a/nrf5/device/nrf52/system_nrf52840.c b/nrf/device/nrf52/system_nrf52840.c similarity index 100% rename from nrf5/device/nrf52/system_nrf52840.c rename to nrf/device/nrf52/system_nrf52840.c diff --git a/nrf5/device/nrf52/system_nrf52840.h b/nrf/device/nrf52/system_nrf52840.h similarity index 100% rename from nrf5/device/nrf52/system_nrf52840.h rename to nrf/device/nrf52/system_nrf52840.h diff --git a/nrf5/drivers/bluetooth/ble_drv.c b/nrf/drivers/bluetooth/ble_drv.c similarity index 100% rename from nrf5/drivers/bluetooth/ble_drv.c rename to nrf/drivers/bluetooth/ble_drv.c diff --git a/nrf5/drivers/bluetooth/ble_drv.h b/nrf/drivers/bluetooth/ble_drv.h similarity index 100% rename from nrf5/drivers/bluetooth/ble_drv.h rename to nrf/drivers/bluetooth/ble_drv.h diff --git a/nrf5/drivers/bluetooth/ble_uart.c b/nrf/drivers/bluetooth/ble_uart.c similarity index 100% rename from nrf5/drivers/bluetooth/ble_uart.c rename to nrf/drivers/bluetooth/ble_uart.c diff --git a/nrf5/drivers/bluetooth/ble_uart.h b/nrf/drivers/bluetooth/ble_uart.h similarity index 100% rename from nrf5/drivers/bluetooth/ble_uart.h rename to nrf/drivers/bluetooth/ble_uart.h diff --git a/nrf5/drivers/bluetooth/bluetooth_common.mk b/nrf/drivers/bluetooth/bluetooth_common.mk similarity index 100% rename from nrf5/drivers/bluetooth/bluetooth_common.mk rename to nrf/drivers/bluetooth/bluetooth_common.mk diff --git a/nrf5/drivers/bluetooth/download_ble_stack.sh b/nrf/drivers/bluetooth/download_ble_stack.sh similarity index 100% rename from nrf5/drivers/bluetooth/download_ble_stack.sh rename to nrf/drivers/bluetooth/download_ble_stack.sh diff --git a/nrf5/drivers/bluetooth/ringbuffer.h b/nrf/drivers/bluetooth/ringbuffer.h similarity index 100% rename from nrf5/drivers/bluetooth/ringbuffer.h rename to nrf/drivers/bluetooth/ringbuffer.h diff --git a/nrf5/drivers/softpwm.c b/nrf/drivers/softpwm.c similarity index 100% rename from nrf5/drivers/softpwm.c rename to nrf/drivers/softpwm.c diff --git a/nrf5/drivers/softpwm.h b/nrf/drivers/softpwm.h similarity index 100% rename from nrf5/drivers/softpwm.h rename to nrf/drivers/softpwm.h diff --git a/nrf5/drivers/ticker.c b/nrf/drivers/ticker.c similarity index 100% rename from nrf5/drivers/ticker.c rename to nrf/drivers/ticker.c diff --git a/nrf5/drivers/ticker.h b/nrf/drivers/ticker.h similarity index 100% rename from nrf5/drivers/ticker.h rename to nrf/drivers/ticker.h diff --git a/nrf5/examples/mountsd.py b/nrf/examples/mountsd.py similarity index 100% rename from nrf5/examples/mountsd.py rename to nrf/examples/mountsd.py diff --git a/nrf5/examples/musictest.py b/nrf/examples/musictest.py similarity index 100% rename from nrf5/examples/musictest.py rename to nrf/examples/musictest.py diff --git a/nrf5/examples/nrf52_pwm.py b/nrf/examples/nrf52_pwm.py similarity index 100% rename from nrf5/examples/nrf52_pwm.py rename to nrf/examples/nrf52_pwm.py diff --git a/nrf5/examples/nrf52_servo.py b/nrf/examples/nrf52_servo.py similarity index 100% rename from nrf5/examples/nrf52_servo.py rename to nrf/examples/nrf52_servo.py diff --git a/nrf5/examples/powerup.py b/nrf/examples/powerup.py similarity index 100% rename from nrf5/examples/powerup.py rename to nrf/examples/powerup.py diff --git a/nrf5/examples/seeed_tft.py b/nrf/examples/seeed_tft.py similarity index 100% rename from nrf5/examples/seeed_tft.py rename to nrf/examples/seeed_tft.py diff --git a/nrf5/examples/ssd1306_mod.py b/nrf/examples/ssd1306_mod.py similarity index 98% rename from nrf5/examples/ssd1306_mod.py rename to nrf/examples/ssd1306_mod.py index 1c3ba85f70..5480c646c2 100644 --- a/nrf5/examples/ssd1306_mod.py +++ b/nrf/examples/ssd1306_mod.py @@ -1,4 +1,4 @@ -# NOTE: Modified version to align with implemented I2C API in nrf5 port. +# NOTE: Modified version to align with implemented I2C API in nrf port. # # Examples usage of SSD1306_SPI on pca10040 # diff --git a/nrf5/examples/ubluepy_eddystone.py b/nrf/examples/ubluepy_eddystone.py similarity index 100% rename from nrf5/examples/ubluepy_eddystone.py rename to nrf/examples/ubluepy_eddystone.py diff --git a/nrf5/examples/ubluepy_scan.py b/nrf/examples/ubluepy_scan.py similarity index 100% rename from nrf5/examples/ubluepy_scan.py rename to nrf/examples/ubluepy_scan.py diff --git a/nrf5/fatfs_port.c b/nrf/fatfs_port.c similarity index 100% rename from nrf5/fatfs_port.c rename to nrf/fatfs_port.c diff --git a/nrf5/font_petme128_8x8.h b/nrf/font_petme128_8x8.h similarity index 100% rename from nrf5/font_petme128_8x8.h rename to nrf/font_petme128_8x8.h diff --git a/nrf5/freeze/test.py b/nrf/freeze/test.py similarity index 100% rename from nrf5/freeze/test.py rename to nrf/freeze/test.py diff --git a/nrf5/gccollect.c b/nrf/gccollect.c similarity index 100% rename from nrf5/gccollect.c rename to nrf/gccollect.c diff --git a/nrf5/gccollect.h b/nrf/gccollect.h similarity index 100% rename from nrf5/gccollect.h rename to nrf/gccollect.h diff --git a/nrf5/hal/hal_adc.c b/nrf/hal/hal_adc.c similarity index 100% rename from nrf5/hal/hal_adc.c rename to nrf/hal/hal_adc.c diff --git a/nrf5/hal/hal_adc.h b/nrf/hal/hal_adc.h similarity index 100% rename from nrf5/hal/hal_adc.h rename to nrf/hal/hal_adc.h diff --git a/nrf5/hal/hal_adce.c b/nrf/hal/hal_adce.c similarity index 100% rename from nrf5/hal/hal_adce.c rename to nrf/hal/hal_adce.c diff --git a/nrf5/hal/hal_gpio.c b/nrf/hal/hal_gpio.c similarity index 100% rename from nrf5/hal/hal_gpio.c rename to nrf/hal/hal_gpio.c diff --git a/nrf5/hal/hal_gpio.h b/nrf/hal/hal_gpio.h similarity index 100% rename from nrf5/hal/hal_gpio.h rename to nrf/hal/hal_gpio.h diff --git a/nrf5/hal/hal_irq.h b/nrf/hal/hal_irq.h similarity index 100% rename from nrf5/hal/hal_irq.h rename to nrf/hal/hal_irq.h diff --git a/nrf5/hal/hal_pwm.c b/nrf/hal/hal_pwm.c similarity index 100% rename from nrf5/hal/hal_pwm.c rename to nrf/hal/hal_pwm.c diff --git a/nrf5/hal/hal_pwm.h b/nrf/hal/hal_pwm.h similarity index 100% rename from nrf5/hal/hal_pwm.h rename to nrf/hal/hal_pwm.h diff --git a/nrf5/hal/hal_qspie.c b/nrf/hal/hal_qspie.c similarity index 100% rename from nrf5/hal/hal_qspie.c rename to nrf/hal/hal_qspie.c diff --git a/nrf5/hal/hal_qspie.h b/nrf/hal/hal_qspie.h similarity index 100% rename from nrf5/hal/hal_qspie.h rename to nrf/hal/hal_qspie.h diff --git a/nrf5/hal/hal_rtc.c b/nrf/hal/hal_rtc.c similarity index 100% rename from nrf5/hal/hal_rtc.c rename to nrf/hal/hal_rtc.c diff --git a/nrf5/hal/hal_rtc.h b/nrf/hal/hal_rtc.h similarity index 100% rename from nrf5/hal/hal_rtc.h rename to nrf/hal/hal_rtc.h diff --git a/nrf5/hal/hal_spi.c b/nrf/hal/hal_spi.c similarity index 100% rename from nrf5/hal/hal_spi.c rename to nrf/hal/hal_spi.c diff --git a/nrf5/hal/hal_spi.h b/nrf/hal/hal_spi.h similarity index 100% rename from nrf5/hal/hal_spi.h rename to nrf/hal/hal_spi.h diff --git a/nrf5/hal/hal_spie.c b/nrf/hal/hal_spie.c similarity index 100% rename from nrf5/hal/hal_spie.c rename to nrf/hal/hal_spie.c diff --git a/nrf5/hal/hal_temp.c b/nrf/hal/hal_temp.c similarity index 100% rename from nrf5/hal/hal_temp.c rename to nrf/hal/hal_temp.c diff --git a/nrf5/hal/hal_temp.h b/nrf/hal/hal_temp.h similarity index 100% rename from nrf5/hal/hal_temp.h rename to nrf/hal/hal_temp.h diff --git a/nrf5/hal/hal_time.c b/nrf/hal/hal_time.c similarity index 100% rename from nrf5/hal/hal_time.c rename to nrf/hal/hal_time.c diff --git a/nrf5/hal/hal_time.h b/nrf/hal/hal_time.h similarity index 100% rename from nrf5/hal/hal_time.h rename to nrf/hal/hal_time.h diff --git a/nrf5/hal/hal_timer.c b/nrf/hal/hal_timer.c similarity index 100% rename from nrf5/hal/hal_timer.c rename to nrf/hal/hal_timer.c diff --git a/nrf5/hal/hal_timer.h b/nrf/hal/hal_timer.h similarity index 100% rename from nrf5/hal/hal_timer.h rename to nrf/hal/hal_timer.h diff --git a/nrf5/hal/hal_twi.c b/nrf/hal/hal_twi.c similarity index 100% rename from nrf5/hal/hal_twi.c rename to nrf/hal/hal_twi.c diff --git a/nrf5/hal/hal_twi.h b/nrf/hal/hal_twi.h similarity index 100% rename from nrf5/hal/hal_twi.h rename to nrf/hal/hal_twi.h diff --git a/nrf5/hal/hal_twie.c b/nrf/hal/hal_twie.c similarity index 100% rename from nrf5/hal/hal_twie.c rename to nrf/hal/hal_twie.c diff --git a/nrf5/hal/hal_uart.c b/nrf/hal/hal_uart.c similarity index 100% rename from nrf5/hal/hal_uart.c rename to nrf/hal/hal_uart.c diff --git a/nrf5/hal/hal_uart.h b/nrf/hal/hal_uart.h similarity index 100% rename from nrf5/hal/hal_uart.h rename to nrf/hal/hal_uart.h diff --git a/nrf5/hal/hal_uarte.c b/nrf/hal/hal_uarte.c similarity index 100% rename from nrf5/hal/hal_uarte.c rename to nrf/hal/hal_uarte.c diff --git a/nrf5/hal/nrf51_hal.h b/nrf/hal/nrf51_hal.h similarity index 100% rename from nrf5/hal/nrf51_hal.h rename to nrf/hal/nrf51_hal.h diff --git a/nrf5/hal/nrf52_hal.h b/nrf/hal/nrf52_hal.h similarity index 100% rename from nrf5/hal/nrf52_hal.h rename to nrf/hal/nrf52_hal.h diff --git a/nrf5/help.c b/nrf/help.c similarity index 100% rename from nrf5/help.c rename to nrf/help.c diff --git a/nrf5/main.c b/nrf/main.c similarity index 100% rename from nrf5/main.c rename to nrf/main.c diff --git a/nrf5/modules/ble/help_sd.h b/nrf/modules/ble/help_sd.h similarity index 100% rename from nrf5/modules/ble/help_sd.h rename to nrf/modules/ble/help_sd.h diff --git a/nrf5/modules/ble/modble.c b/nrf/modules/ble/modble.c similarity index 100% rename from nrf5/modules/ble/modble.c rename to nrf/modules/ble/modble.c diff --git a/nrf5/modules/machine/adc.c b/nrf/modules/machine/adc.c similarity index 100% rename from nrf5/modules/machine/adc.c rename to nrf/modules/machine/adc.c diff --git a/nrf5/modules/machine/adc.h b/nrf/modules/machine/adc.h similarity index 100% rename from nrf5/modules/machine/adc.h rename to nrf/modules/machine/adc.h diff --git a/nrf5/modules/machine/i2c.c b/nrf/modules/machine/i2c.c similarity index 100% rename from nrf5/modules/machine/i2c.c rename to nrf/modules/machine/i2c.c diff --git a/nrf5/modules/machine/i2c.h b/nrf/modules/machine/i2c.h similarity index 100% rename from nrf5/modules/machine/i2c.h rename to nrf/modules/machine/i2c.h diff --git a/nrf5/modules/machine/led.c b/nrf/modules/machine/led.c similarity index 100% rename from nrf5/modules/machine/led.c rename to nrf/modules/machine/led.c diff --git a/nrf5/modules/machine/led.h b/nrf/modules/machine/led.h similarity index 100% rename from nrf5/modules/machine/led.h rename to nrf/modules/machine/led.h diff --git a/nrf5/modules/machine/modmachine.c b/nrf/modules/machine/modmachine.c similarity index 100% rename from nrf5/modules/machine/modmachine.c rename to nrf/modules/machine/modmachine.c diff --git a/nrf5/modules/machine/modmachine.h b/nrf/modules/machine/modmachine.h similarity index 100% rename from nrf5/modules/machine/modmachine.h rename to nrf/modules/machine/modmachine.h diff --git a/nrf5/modules/machine/pin.c b/nrf/modules/machine/pin.c similarity index 100% rename from nrf5/modules/machine/pin.c rename to nrf/modules/machine/pin.c diff --git a/nrf5/modules/machine/pin.h b/nrf/modules/machine/pin.h similarity index 100% rename from nrf5/modules/machine/pin.h rename to nrf/modules/machine/pin.h diff --git a/nrf5/modules/machine/pwm.c b/nrf/modules/machine/pwm.c similarity index 100% rename from nrf5/modules/machine/pwm.c rename to nrf/modules/machine/pwm.c diff --git a/nrf5/modules/machine/pwm.h b/nrf/modules/machine/pwm.h similarity index 100% rename from nrf5/modules/machine/pwm.h rename to nrf/modules/machine/pwm.h diff --git a/nrf5/modules/machine/rtc.c b/nrf/modules/machine/rtc.c similarity index 100% rename from nrf5/modules/machine/rtc.c rename to nrf/modules/machine/rtc.c diff --git a/nrf5/modules/machine/rtc.h b/nrf/modules/machine/rtc.h similarity index 100% rename from nrf5/modules/machine/rtc.h rename to nrf/modules/machine/rtc.h diff --git a/nrf5/modules/machine/spi.c b/nrf/modules/machine/spi.c similarity index 100% rename from nrf5/modules/machine/spi.c rename to nrf/modules/machine/spi.c diff --git a/nrf5/modules/machine/spi.h b/nrf/modules/machine/spi.h similarity index 100% rename from nrf5/modules/machine/spi.h rename to nrf/modules/machine/spi.h diff --git a/nrf5/modules/machine/temp.c b/nrf/modules/machine/temp.c similarity index 100% rename from nrf5/modules/machine/temp.c rename to nrf/modules/machine/temp.c diff --git a/nrf5/modules/machine/temp.h b/nrf/modules/machine/temp.h similarity index 100% rename from nrf5/modules/machine/temp.h rename to nrf/modules/machine/temp.h diff --git a/nrf5/modules/machine/timer.c b/nrf/modules/machine/timer.c similarity index 100% rename from nrf5/modules/machine/timer.c rename to nrf/modules/machine/timer.c diff --git a/nrf5/modules/machine/timer.h b/nrf/modules/machine/timer.h similarity index 100% rename from nrf5/modules/machine/timer.h rename to nrf/modules/machine/timer.h diff --git a/nrf5/modules/machine/uart.c b/nrf/modules/machine/uart.c similarity index 100% rename from nrf5/modules/machine/uart.c rename to nrf/modules/machine/uart.c diff --git a/nrf5/modules/machine/uart.h b/nrf/modules/machine/uart.h similarity index 100% rename from nrf5/modules/machine/uart.h rename to nrf/modules/machine/uart.h diff --git a/nrf5/modules/music/modmusic.c b/nrf/modules/music/modmusic.c similarity index 100% rename from nrf5/modules/music/modmusic.c rename to nrf/modules/music/modmusic.c diff --git a/nrf5/modules/music/modmusic.h b/nrf/modules/music/modmusic.h similarity index 100% rename from nrf5/modules/music/modmusic.h rename to nrf/modules/music/modmusic.h diff --git a/nrf5/modules/music/musictunes.c b/nrf/modules/music/musictunes.c similarity index 100% rename from nrf5/modules/music/musictunes.c rename to nrf/modules/music/musictunes.c diff --git a/nrf5/modules/music/musictunes.h b/nrf/modules/music/musictunes.h similarity index 100% rename from nrf5/modules/music/musictunes.h rename to nrf/modules/music/musictunes.h diff --git a/nrf5/modules/pyb/modpyb.c b/nrf/modules/pyb/modpyb.c similarity index 100% rename from nrf5/modules/pyb/modpyb.c rename to nrf/modules/pyb/modpyb.c diff --git a/nrf5/modules/ubluepy/modubluepy.c b/nrf/modules/ubluepy/modubluepy.c similarity index 100% rename from nrf5/modules/ubluepy/modubluepy.c rename to nrf/modules/ubluepy/modubluepy.c diff --git a/nrf5/modules/ubluepy/modubluepy.h b/nrf/modules/ubluepy/modubluepy.h similarity index 100% rename from nrf5/modules/ubluepy/modubluepy.h rename to nrf/modules/ubluepy/modubluepy.h diff --git a/nrf5/modules/ubluepy/ubluepy_characteristic.c b/nrf/modules/ubluepy/ubluepy_characteristic.c similarity index 100% rename from nrf5/modules/ubluepy/ubluepy_characteristic.c rename to nrf/modules/ubluepy/ubluepy_characteristic.c diff --git a/nrf5/modules/ubluepy/ubluepy_constants.c b/nrf/modules/ubluepy/ubluepy_constants.c similarity index 100% rename from nrf5/modules/ubluepy/ubluepy_constants.c rename to nrf/modules/ubluepy/ubluepy_constants.c diff --git a/nrf5/modules/ubluepy/ubluepy_delegate.c b/nrf/modules/ubluepy/ubluepy_delegate.c similarity index 100% rename from nrf5/modules/ubluepy/ubluepy_delegate.c rename to nrf/modules/ubluepy/ubluepy_delegate.c diff --git a/nrf5/modules/ubluepy/ubluepy_descriptor.c b/nrf/modules/ubluepy/ubluepy_descriptor.c similarity index 100% rename from nrf5/modules/ubluepy/ubluepy_descriptor.c rename to nrf/modules/ubluepy/ubluepy_descriptor.c diff --git a/nrf5/modules/ubluepy/ubluepy_peripheral.c b/nrf/modules/ubluepy/ubluepy_peripheral.c similarity index 100% rename from nrf5/modules/ubluepy/ubluepy_peripheral.c rename to nrf/modules/ubluepy/ubluepy_peripheral.c diff --git a/nrf5/modules/ubluepy/ubluepy_scan_entry.c b/nrf/modules/ubluepy/ubluepy_scan_entry.c similarity index 100% rename from nrf5/modules/ubluepy/ubluepy_scan_entry.c rename to nrf/modules/ubluepy/ubluepy_scan_entry.c diff --git a/nrf5/modules/ubluepy/ubluepy_scanner.c b/nrf/modules/ubluepy/ubluepy_scanner.c similarity index 100% rename from nrf5/modules/ubluepy/ubluepy_scanner.c rename to nrf/modules/ubluepy/ubluepy_scanner.c diff --git a/nrf5/modules/ubluepy/ubluepy_service.c b/nrf/modules/ubluepy/ubluepy_service.c similarity index 100% rename from nrf5/modules/ubluepy/ubluepy_service.c rename to nrf/modules/ubluepy/ubluepy_service.c diff --git a/nrf5/modules/ubluepy/ubluepy_uuid.c b/nrf/modules/ubluepy/ubluepy_uuid.c similarity index 100% rename from nrf5/modules/ubluepy/ubluepy_uuid.c rename to nrf/modules/ubluepy/ubluepy_uuid.c diff --git a/nrf5/modules/uos/moduos.c b/nrf/modules/uos/moduos.c similarity index 100% rename from nrf5/modules/uos/moduos.c rename to nrf/modules/uos/moduos.c diff --git a/nrf5/modules/utime/modutime.c b/nrf/modules/utime/modutime.c similarity index 100% rename from nrf5/modules/utime/modutime.c rename to nrf/modules/utime/modutime.c diff --git a/nrf5/mpconfigport.h b/nrf/mpconfigport.h similarity index 100% rename from nrf5/mpconfigport.h rename to nrf/mpconfigport.h diff --git a/nrf5/mphalport.c b/nrf/mphalport.c similarity index 100% rename from nrf5/mphalport.c rename to nrf/mphalport.c diff --git a/nrf5/mphalport.h b/nrf/mphalport.h similarity index 100% rename from nrf5/mphalport.h rename to nrf/mphalport.h diff --git a/nrf5/nrf51_af.csv b/nrf/nrf51_af.csv similarity index 100% rename from nrf5/nrf51_af.csv rename to nrf/nrf51_af.csv diff --git a/nrf5/nrf52_af.csv b/nrf/nrf52_af.csv similarity index 100% rename from nrf5/nrf52_af.csv rename to nrf/nrf52_af.csv diff --git a/nrf5/pin_defs_nrf5.h b/nrf/pin_defs_nrf5.h similarity index 99% rename from nrf5/pin_defs_nrf5.h rename to nrf/pin_defs_nrf5.h index 9922cd5e41..1d4146b120 100644 --- a/nrf5/pin_defs_nrf5.h +++ b/nrf/pin_defs_nrf5.h @@ -25,7 +25,7 @@ * THE SOFTWARE. */ -// This file contains pin definitions that are specific to the nrf5 port. +// This file contains pin definitions that are specific to the nrf port. // This file should only ever be #included by pin.h and not directly. enum { diff --git a/nrf5/pin_named_pins.c b/nrf/pin_named_pins.c similarity index 100% rename from nrf5/pin_named_pins.c rename to nrf/pin_named_pins.c diff --git a/nrf5/qstrdefsport.h b/nrf/qstrdefsport.h similarity index 100% rename from nrf5/qstrdefsport.h rename to nrf/qstrdefsport.h From 4a52f8401b9391454196a1b5038ec824edbbfb4a Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 18:56:11 +0200 Subject: [PATCH 777/809] nrf5/drivers/bluetooth: Make printf in 'ble_drv_service_add' function part of debug log. --- nrf/drivers/bluetooth/ble_drv.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/nrf/drivers/bluetooth/ble_drv.c b/nrf/drivers/bluetooth/ble_drv.c index 8d3348f5fc..dab0e42fb2 100644 --- a/nrf/drivers/bluetooth/ble_drv.c +++ b/nrf/drivers/bluetooth/ble_drv.c @@ -271,14 +271,13 @@ bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj) { "Can not add Service.")); } } else if (p_service_obj->p_uuid->type == BLE_UUID_TYPE_BLE) { - printf("adding service\n"); + BLE_DRIVER_LOG("adding service\n"); ble_uuid_t uuid; uuid.type = p_service_obj->p_uuid->type; uuid.uuid = p_service_obj->p_uuid->value[0]; uuid.uuid += p_service_obj->p_uuid->value[1] << 8; - printf("adding service\n"); if (sd_ble_gatts_service_add(p_service_obj->type, &uuid, &p_service_obj->handle) != 0) { From d53596145a8332296c0bac3988aeda221e59528e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 21:11:44 +0200 Subject: [PATCH 778/809] nrf5/hal/timer: Add support for fetching temperature if bluetooth stack is enabled. --- nrf/hal/hal_temp.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/nrf/hal/hal_temp.c b/nrf/hal/hal_temp.c index 98b27ed725..a8435c4ebe 100644 --- a/nrf/hal/hal_temp.c +++ b/nrf/hal/hal_temp.c @@ -25,9 +25,17 @@ */ #include +#include #include "mphalport.h" #include "hal_temp.h" +#if BLUETOOTH_SD +#include "py/nlr.h" +#include "ble_drv.h" +#include "nrf_soc.h" +#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled()) +#endif // BLUETOOTH_SD + #ifdef HAL_TEMP_MODULE_ENABLED void hal_temp_init(void) { @@ -35,8 +43,18 @@ void hal_temp_init(void) { *(uint32_t *) 0x4000C504 = 0; } -int32_t hal_temp_read(void) { - int32_t volatile temp; + + +int32_t hal_temp_read(void) { +#if BLUETOOTH_SD + if (BLUETOOTH_STACK_ENABLED() == 1) { + int32_t temp; + (void)sd_temp_get(&temp); + return temp / 4; // resolution of 0.25 degree celsius + } +#endif // BLUETOOTH_SD + + int32_t volatile temp; hal_temp_init(); NRF_TEMP->TASKS_START = 1; // Start the temperature measurement. From fc26a2ef7cb9624703459c4212561e6e8d60635e Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 21:13:32 +0200 Subject: [PATCH 779/809] nrf5/modules/ubluepy: Adding new event constant for gatts write (80) events from bluetooth stacks. --- nrf/modules/ubluepy/ubluepy_constants.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nrf/modules/ubluepy/ubluepy_constants.c b/nrf/modules/ubluepy/ubluepy_constants.c index 5e12661e02..0f291d6a24 100644 --- a/nrf/modules/ubluepy/ubluepy_constants.c +++ b/nrf/modules/ubluepy/ubluepy_constants.c @@ -79,6 +79,7 @@ STATIC const mp_rom_map_elem_t ubluepy_constants_locals_dict_table[] = { // GAP events { MP_ROM_QSTR(MP_QSTR_EVT_GAP_CONNECTED), MP_ROM_INT(16) }, { MP_ROM_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED), MP_ROM_INT(17) }, + { MP_ROM_QSTR(MP_QSTR_EVT_GATTS_WRITE), MP_ROM_INT(80) }, { MP_ROM_QSTR(MP_QSTR_UUID_CCCD), MP_ROM_INT(0x2902) }, { MP_ROM_QSTR(MP_QSTR_ADDR_TYPE_PUBLIC), MP_ROM_INT(UBLUEPY_ADDR_TYPE_PUBLIC) }, From f0485c06a1d1a8e21afe418a0db615317744e2bf Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Mon, 5 Jun 2017 21:22:59 +0200 Subject: [PATCH 780/809] nrf5/examples: Adding ubluepy peripheral example that works across nrf51 and nrf52. The example uses Environmenting Sensing Service to provide the temperature characteristic. The temperature is fetched from the machine.Temp module. One note is that the example uses 1 LED which is not present on all boards. --- nrf5/examples/ubluepy_temp.py | 92 +++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 nrf5/examples/ubluepy_temp.py diff --git a/nrf5/examples/ubluepy_temp.py b/nrf5/examples/ubluepy_temp.py new file mode 100644 index 0000000000..59fcfe9694 --- /dev/null +++ b/nrf5/examples/ubluepy_temp.py @@ -0,0 +1,92 @@ +# This file is part of the Micro Python project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2017 Glenn Ruben Bakke +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE + +from pyb import LED +from machine import RTC, Temp +from ubluepy import Service, Characteristic, UUID, Peripheral, constants + +def event_handler(id, handle, data): + global rtc + global periph + global serv_env_sense + global notif_enabled + + if id == constants.EVT_GAP_CONNECTED: + # indicated 'connected' + LED(1).on() + + elif id == constants.EVT_GAP_DISCONNECTED: + # stop low power timer + rtc.stop() + # indicate 'disconnected' + LED(1).off() + # restart advertisment + periph.advertise(device_name="micr_temp", services=[serv_env_sense]) + + elif id == constants.EVT_GATTS_WRITE: + # write to this Characteristic is to CCCD + if int(data[0]) == 1: + notif_enabled = True + # start low power timer + rtc.start() + else: + notif_enabled = False + # stop low power timer + rtc.stop() + +def send_temp(timer_id): + global notif_enabled + global char_temp + + if notif_enabled: + # measure chip temperature + temp = Temp.read() + temp = temp * 100 + char_temp.write(bytearray([temp & 0xFF, temp >> 8])) + +# start off with LED(1) off +LED(1).off() + +# use RTC1 as RTC0 is used by bluetooth stack +# set up RTC callback every 5 second +rtc = RTC(1, period=5, mode=RTC.PERIODIC, callback=send_temp) + +notif_enabled = False + +uuid_env_sense = UUID("0x181A") # Environmental Sensing service +uuid_temp = UUID("0x2A6E") # Temperature characteristic + +serv_env_sense = Service(uuid_env_sense) + +temp_props = Characteristic.PROP_NOTIFY | Characteristic.PROP_READ +temp_attrs = Characteristic.ATTR_CCCD +char_temp = Characteristic(uuid_temp, props = temp_props, attrs = temp_attrs) + +serv_env_sense.addCharacteristic(char_temp) + +periph = Peripheral() +periph.addService(serv_env_sense) +periph.setConnectionHandler(event_handler) +periph.advertise(device_name="micr_temp", services=[serv_env_sense]) + From bf09cdff605d4dc0e08da4103693c0c355b093b9 Mon Sep 17 00:00:00 2001 From: Daniel Tralamazza Date: Wed, 7 Jun 2017 19:41:45 +0200 Subject: [PATCH 781/809] rename temperature example --- {nrf5 => nrf}/examples/ubluepy_temp.py | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename {nrf5 => nrf}/examples/ubluepy_temp.py (100%) diff --git a/nrf5/examples/ubluepy_temp.py b/nrf/examples/ubluepy_temp.py similarity index 100% rename from nrf5/examples/ubluepy_temp.py rename to nrf/examples/ubluepy_temp.py From d6905b961e3dc819950fbb425a261e2bc5b5f70c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 7 Jun 2017 20:54:36 +0200 Subject: [PATCH 782/809] nrf: Removing unused font header. --- nrf/font_petme128_8x8.h | 124 ---------------------------------------- 1 file changed, 124 deletions(-) delete mode 100644 nrf/font_petme128_8x8.h diff --git a/nrf/font_petme128_8x8.h b/nrf/font_petme128_8x8.h deleted file mode 100644 index 7f928edda4..0000000000 --- a/nrf/font_petme128_8x8.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2013, 2014 Damien P. George - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -static const uint8_t font_petme128_8x8[] = { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // 32= - 0x00,0x00,0x00,0x4f,0x4f,0x00,0x00,0x00, // 33=! - 0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00, // 34=" - 0x14,0x7f,0x7f,0x14,0x14,0x7f,0x7f,0x14, // 35=# - 0x00,0x24,0x2e,0x6b,0x6b,0x3a,0x12,0x00, // 36=$ - 0x00,0x63,0x33,0x18,0x0c,0x66,0x63,0x00, // 37=% - 0x00,0x32,0x7f,0x4d,0x4d,0x77,0x72,0x50, // 38=& - 0x00,0x00,0x00,0x04,0x06,0x03,0x01,0x00, // 39=' - 0x00,0x00,0x1c,0x3e,0x63,0x41,0x00,0x00, // 40=( - 0x00,0x00,0x41,0x63,0x3e,0x1c,0x00,0x00, // 41=) - 0x08,0x2a,0x3e,0x1c,0x1c,0x3e,0x2a,0x08, // 42=* - 0x00,0x08,0x08,0x3e,0x3e,0x08,0x08,0x00, // 43=+ - 0x00,0x00,0x80,0xe0,0x60,0x00,0x00,0x00, // 44=, - 0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x00, // 45=- - 0x00,0x00,0x00,0x60,0x60,0x00,0x00,0x00, // 46=. - 0x00,0x40,0x60,0x30,0x18,0x0c,0x06,0x02, // 47=/ - 0x00,0x3e,0x7f,0x49,0x45,0x7f,0x3e,0x00, // 48=0 - 0x00,0x40,0x44,0x7f,0x7f,0x40,0x40,0x00, // 49=1 - 0x00,0x62,0x73,0x51,0x49,0x4f,0x46,0x00, // 50=2 - 0x00,0x22,0x63,0x49,0x49,0x7f,0x36,0x00, // 51=3 - 0x00,0x18,0x18,0x14,0x16,0x7f,0x7f,0x10, // 52=4 - 0x00,0x27,0x67,0x45,0x45,0x7d,0x39,0x00, // 53=5 - 0x00,0x3e,0x7f,0x49,0x49,0x7b,0x32,0x00, // 54=6 - 0x00,0x03,0x03,0x79,0x7d,0x07,0x03,0x00, // 55=7 - 0x00,0x36,0x7f,0x49,0x49,0x7f,0x36,0x00, // 56=8 - 0x00,0x26,0x6f,0x49,0x49,0x7f,0x3e,0x00, // 57=9 - 0x00,0x00,0x00,0x24,0x24,0x00,0x00,0x00, // 58=: - 0x00,0x00,0x80,0xe4,0x64,0x00,0x00,0x00, // 59=; - 0x00,0x08,0x1c,0x36,0x63,0x41,0x41,0x00, // 60=< - 0x00,0x14,0x14,0x14,0x14,0x14,0x14,0x00, // 61== - 0x00,0x41,0x41,0x63,0x36,0x1c,0x08,0x00, // 62=> - 0x00,0x02,0x03,0x51,0x59,0x0f,0x06,0x00, // 63=? - 0x00,0x3e,0x7f,0x41,0x4d,0x4f,0x2e,0x00, // 64=@ - 0x00,0x7c,0x7e,0x0b,0x0b,0x7e,0x7c,0x00, // 65=A - 0x00,0x7f,0x7f,0x49,0x49,0x7f,0x36,0x00, // 66=B - 0x00,0x3e,0x7f,0x41,0x41,0x63,0x22,0x00, // 67=C - 0x00,0x7f,0x7f,0x41,0x63,0x3e,0x1c,0x00, // 68=D - 0x00,0x7f,0x7f,0x49,0x49,0x41,0x41,0x00, // 69=E - 0x00,0x7f,0x7f,0x09,0x09,0x01,0x01,0x00, // 70=F - 0x00,0x3e,0x7f,0x41,0x49,0x7b,0x3a,0x00, // 71=G - 0x00,0x7f,0x7f,0x08,0x08,0x7f,0x7f,0x00, // 72=H - 0x00,0x00,0x41,0x7f,0x7f,0x41,0x00,0x00, // 73=I - 0x00,0x20,0x60,0x41,0x7f,0x3f,0x01,0x00, // 74=J - 0x00,0x7f,0x7f,0x1c,0x36,0x63,0x41,0x00, // 75=K - 0x00,0x7f,0x7f,0x40,0x40,0x40,0x40,0x00, // 76=L - 0x00,0x7f,0x7f,0x06,0x0c,0x06,0x7f,0x7f, // 77=M - 0x00,0x7f,0x7f,0x0e,0x1c,0x7f,0x7f,0x00, // 78=N - 0x00,0x3e,0x7f,0x41,0x41,0x7f,0x3e,0x00, // 79=O - 0x00,0x7f,0x7f,0x09,0x09,0x0f,0x06,0x00, // 80=P - 0x00,0x1e,0x3f,0x21,0x61,0x7f,0x5e,0x00, // 81=Q - 0x00,0x7f,0x7f,0x19,0x39,0x6f,0x46,0x00, // 82=R - 0x00,0x26,0x6f,0x49,0x49,0x7b,0x32,0x00, // 83=S - 0x00,0x01,0x01,0x7f,0x7f,0x01,0x01,0x00, // 84=T - 0x00,0x3f,0x7f,0x40,0x40,0x7f,0x3f,0x00, // 85=U - 0x00,0x1f,0x3f,0x60,0x60,0x3f,0x1f,0x00, // 86=V - 0x00,0x7f,0x7f,0x30,0x18,0x30,0x7f,0x7f, // 87=W - 0x00,0x63,0x77,0x1c,0x1c,0x77,0x63,0x00, // 88=X - 0x00,0x07,0x0f,0x78,0x78,0x0f,0x07,0x00, // 89=Y - 0x00,0x61,0x71,0x59,0x4d,0x47,0x43,0x00, // 90=Z - 0x00,0x00,0x7f,0x7f,0x41,0x41,0x00,0x00, // 91=[ - 0x00,0x02,0x06,0x0c,0x18,0x30,0x60,0x40, // 92='\' - 0x00,0x00,0x41,0x41,0x7f,0x7f,0x00,0x00, // 93=] - 0x00,0x08,0x0c,0x06,0x06,0x0c,0x08,0x00, // 94=^ - 0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0, // 95=_ - 0x00,0x00,0x01,0x03,0x06,0x04,0x00,0x00, // 96=` - 0x00,0x20,0x74,0x54,0x54,0x7c,0x78,0x00, // 97=a - 0x00,0x7f,0x7f,0x44,0x44,0x7c,0x38,0x00, // 98=b - 0x00,0x38,0x7c,0x44,0x44,0x6c,0x28,0x00, // 99=c - 0x00,0x38,0x7c,0x44,0x44,0x7f,0x7f,0x00, // 100=d - 0x00,0x38,0x7c,0x54,0x54,0x5c,0x58,0x00, // 101=e - 0x00,0x08,0x7e,0x7f,0x09,0x03,0x02,0x00, // 102=f - 0x00,0x98,0xbc,0xa4,0xa4,0xfc,0x7c,0x00, // 103=g - 0x00,0x7f,0x7f,0x04,0x04,0x7c,0x78,0x00, // 104=h - 0x00,0x00,0x00,0x7d,0x7d,0x00,0x00,0x00, // 105=i - 0x00,0x40,0xc0,0x80,0x80,0xfd,0x7d,0x00, // 106=j - 0x00,0x7f,0x7f,0x30,0x38,0x6c,0x44,0x00, // 107=k - 0x00,0x00,0x41,0x7f,0x7f,0x40,0x00,0x00, // 108=l - 0x00,0x7c,0x7c,0x18,0x30,0x18,0x7c,0x7c, // 109=m - 0x00,0x7c,0x7c,0x04,0x04,0x7c,0x78,0x00, // 110=n - 0x00,0x38,0x7c,0x44,0x44,0x7c,0x38,0x00, // 111=o - 0x00,0xfc,0xfc,0x24,0x24,0x3c,0x18,0x00, // 112=p - 0x00,0x18,0x3c,0x24,0x24,0xfc,0xfc,0x00, // 113=q - 0x00,0x7c,0x7c,0x04,0x04,0x0c,0x08,0x00, // 114=r - 0x00,0x48,0x5c,0x54,0x54,0x74,0x20,0x00, // 115=s - 0x04,0x04,0x3f,0x7f,0x44,0x64,0x20,0x00, // 116=t - 0x00,0x3c,0x7c,0x40,0x40,0x7c,0x3c,0x00, // 117=u - 0x00,0x1c,0x3c,0x60,0x60,0x3c,0x1c,0x00, // 118=v - 0x00,0x1c,0x7c,0x30,0x18,0x30,0x7c,0x1c, // 119=w - 0x00,0x44,0x6c,0x38,0x38,0x6c,0x44,0x00, // 120=x - 0x00,0x9c,0xbc,0xa0,0xa0,0xfc,0x7c,0x00, // 121=y - 0x00,0x44,0x64,0x74,0x5c,0x4c,0x44,0x00, // 122=z - 0x00,0x08,0x08,0x3e,0x77,0x41,0x41,0x00, // 123={ - 0x00,0x00,0x00,0xff,0xff,0x00,0x00,0x00, // 124=| - 0x00,0x41,0x41,0x77,0x3e,0x08,0x08,0x00, // 125=} - 0x00,0x02,0x03,0x01,0x03,0x02,0x03,0x01, // 126=~ - 0xaa,0x55,0xaa,0x55,0xaa,0x55,0xaa,0x55, // 127 -}; From 10965eef5c8cff98ab77eb2d988618f2984192d8 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 7 Jun 2017 21:33:47 +0200 Subject: [PATCH 783/809] nrf: Updating README. --- nrf/README.md | 85 +++++++++++++++++++++------------------------------ 1 file changed, 34 insertions(+), 51 deletions(-) diff --git a/nrf/README.md b/nrf/README.md index 0bfc524cbf..ebfedbb945 100644 --- a/nrf/README.md +++ b/nrf/README.md @@ -1,8 +1,8 @@ -# MicroPython port to the NRF5 +# MicroPython Port To The Nordic Semiconductor nRF Series -This is a port of MicroPython to the Nordic nRF5 series of chips. +This is a port of MicroPython to the Nordic Semiconductor nRF series of chips. -## Supported features +## Supported Features * UART * SPI @@ -16,10 +16,11 @@ This is a port of MicroPython to the Nordic nRF5 series of chips. * BLE support including: * Peripheral role on nrf51 targets * Central role and Peripheral role on nrf52 targets - * _REPL over Bluetooth LE_ (optionally using WebBluetooth) - * ubluepy: Bluetooth LE module for micropython + * _REPL over Bluetooth LE_ (optionally using WebBluetooth) + * ubluepy: Bluetooth LE module for micropython + * 1 non-connectable advertiser while in connection -## Tested hardware +## Tested Hardware * nRF51 * [micro:bit](http://microbit.org/) @@ -44,7 +45,7 @@ Prerequisite steps for building the nrf port: git submodule update --init make -C mpy-cross -By default PCA10040 (nrf52832) is used as compile target. To build and flash issue the following command inside the nrf/ folder: +By default, the PCA10040 (nrf52832) is used as compile target. To build and flash issue the following command inside the nrf/ folder: make make flash @@ -54,16 +55,6 @@ Alternatively the target board could be defined: make BOARD=pca10040 make flash -Available board target names: -* microbit -* feather52 -* pca10000 -* pca10001 -* pca10028 -* pca10031 -* pca10040 -* pca10056 - ## Compile and Flash with Bluetooth Stack First prepare the bluetooth folder by downloading Bluetooth LE stacks and headers: @@ -79,47 +70,42 @@ The **make sd** will trigger a flash of the bluetooth stack before that applicat Note: further tuning of features to include in bluetooth or even setting up the device to use REPL over Bluetooth can be configured in the bluetooth_conf.h. -Board | SD param | Support -------------|-------------|---------- -microbit | s110 | Peripheral -pca10000 | s110 | Peripheral -pca10001 | s110 | Peripheral -pca10028 | s110 | Peripheral -pca10031 | s110 | Peripheral -pca10040 | s132 | Peripheral and Central -feather52 | s132 | Peripheral and Central -pca10056 | | +## Target Boards and Make Flags -## Segger targets +Target Board (BOARD) | Bluetooth Stack (SD) | Bluetooth Support | Flash Util +---------------------|-------------------------|------------------------|------------------------------- +microbit | s110 | Peripheral | [PyOCD](#pyocdopenocd-targets) +pca10000 | s110 | Peripheral | [Segger](#segger-targets) +pca10001 | s110 | Peripheral | [Segger](#segger-targets) +pca10028 | s110 | Peripheral | [Segger](#segger-targets) +pca10031 | s110 | Peripheral | [Segger](#segger-targets) +pca10040 | s132 | Peripheral and Central | [Segger](#segger-targets) +feather52 | s132 | Peripheral and Central | [UART DFU](#dfu-targets) +pca10056 | | | [Segger](#segger-targets) + +## Segger Targets Install the necessary tools to flash and debug using Segger: -[JLink](https://www.segger.com/downloads/jlink#) +[JLink Download](https://www.segger.com/downloads/jlink#) -[nrfjprog linux-32bit](https://www.nordicsemi.com/eng/nordic/download_resource/52615/16/95882111/97746) -[nrfjprog linux-64bit](https://www.nordicsemi.com/eng/nordic/download_resource/51386/21/77886419/94917) -[nrfjprog osx](https://www.nordicsemi.com/eng/nordic/download_resource/53402/12/97293750/99977) -[nrfjprog win32](https://www.nordicsemi.com/eng/nordic/download_resource/33444/40/22191727/53210) +[nrfjprog linux-32bit Download](https://www.nordicsemi.com/eng/nordic/download_resource/52615/16/95882111/97746) -Boards that would need JLink/nrfjprog: -* PCA10000 -* PCA10001 -* PCA10028 -* PCA10031 -* PCA10040 -* PCA10056 +[nrfjprog linux-64bit Download](https://www.nordicsemi.com/eng/nordic/download_resource/51386/21/77886419/94917) -## PyOCD/OpenOCD targets +[nrfjprog osx Download](https://www.nordicsemi.com/eng/nordic/download_resource/53402/12/97293750/99977) + +[nrfjprog win32 Download](https://www.nordicsemi.com/eng/nordic/download_resource/33444/40/22191727/53210) + + +## PyOCD/OpenOCD Targets Install the necessary tools to flash and debug using OpenOCD: sudo apt-get install openocd sudo pip install pyOCD -Boards that would need PyOCD: -* micro:bit - -## DFU targets +## DFU Targets sudo apt-get install build-essential libffi-dev pkg-config gcc-arm-none-eabi git python python-pip git clone https://github.com/adafruit/Adafruit_nRF52_Arduino.git @@ -133,9 +119,6 @@ Boards that would need PyOCD: Example on how to generate and flash feather52 target: - make BOARD=feather52 - make BOARD=feather52 dfu-gen - make BOARD=feather52 dfu-flash - -Boards that would need DFU flash utilities: -* feather52 (Adafruit Feather nRF52) + make BOARD=feather52 SD=s132 + make BOARD=feather52 SD=s132 dfu-gen + make BOARD=feather52 SD=s132 dfu-flash From 4b4fee8b78de1dff7e37ebf1aac9d7b08146526b Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 8 Jun 2017 20:58:19 +0200 Subject: [PATCH 784/809] nrf/boards: Adding RTC and Timer module and HAL to pca10000. --- nrf/boards/pca10000/mpconfigboard.h | 4 ++++ nrf/boards/pca10000/nrf51_hal_conf.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/nrf/boards/pca10000/mpconfigboard.h b/nrf/boards/pca10000/mpconfigboard.h index a2a8a3a36d..46efdad307 100644 --- a/nrf/boards/pca10000/mpconfigboard.h +++ b/nrf/boards/pca10000/mpconfigboard.h @@ -31,6 +31,10 @@ #define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" #define MICROPY_PY_MACHINE_HW_SPI (0) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_I2C (0) +#define MICROPY_PY_MACHINE_ADC (0) #define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_HW_HAS_LED (1) diff --git a/nrf/boards/pca10000/nrf51_hal_conf.h b/nrf/boards/pca10000/nrf51_hal_conf.h index c1ac8268ea..484fb8c38f 100644 --- a/nrf/boards/pca10000/nrf51_hal_conf.h +++ b/nrf/boards/pca10000/nrf51_hal_conf.h @@ -2,6 +2,8 @@ #define NRF51_HAL_CONF_H__ #define HAL_UART_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED From 362e2946a57ce16ded2ef2b2c85e74c41fb04768 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 8 Jun 2017 21:06:27 +0200 Subject: [PATCH 785/809] nrf/boards: Activate RTC, Timer, I2C and ADC module and HAL on pca10001. --- nrf/boards/pca10001/mpconfigboard.h | 4 ++++ nrf/boards/pca10001/nrf51_hal_conf.h | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/nrf/boards/pca10001/mpconfigboard.h b/nrf/boards/pca10001/mpconfigboard.h index 0ef5a2492d..bd49876862 100644 --- a/nrf/boards/pca10001/mpconfigboard.h +++ b/nrf/boards/pca10001/mpconfigboard.h @@ -31,6 +31,10 @@ #define MICROPY_PY_SYS_PLATFORM "nrf51-DK" #define MICROPY_PY_MACHINE_HW_SPI (0) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_HW_HAS_LED (1) diff --git a/nrf/boards/pca10001/nrf51_hal_conf.h b/nrf/boards/pca10001/nrf51_hal_conf.h index f5a1c6adb8..e83e2d346e 100644 --- a/nrf/boards/pca10001/nrf51_hal_conf.h +++ b/nrf/boards/pca10001/nrf51_hal_conf.h @@ -2,7 +2,7 @@ #define NRF51_HAL_CONF_H__ #define HAL_UART_MODULE_ENABLED -// #define HAL_SPI_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED #define HAL_RTC_MODULE_ENABLED #define HAL_TIMER_MODULE_ENABLED From 8906084d8014c6257772999a91e6315672dddbee Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 8 Jun 2017 21:23:30 +0200 Subject: [PATCH 786/809] nrf/boards: Activate RTC, Timer, I2C, ADC and HW_SPI module and HAL on pca10031. --- nrf/boards/pca10031/mpconfigboard.h | 5 +++++ nrf/boards/pca10031/nrf51_hal_conf.h | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/nrf/boards/pca10031/mpconfigboard.h b/nrf/boards/pca10031/mpconfigboard.h index 06de2e6440..d8b69e2ede 100644 --- a/nrf/boards/pca10031/mpconfigboard.h +++ b/nrf/boards/pca10031/mpconfigboard.h @@ -30,6 +30,11 @@ #define MICROPY_HW_MCU_NAME "NRF51822" #define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" +#define MICROPY_PY_MACHINE_HW_SPI (1) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) #define MICROPY_HW_HAS_LED (1) diff --git a/nrf/boards/pca10031/nrf51_hal_conf.h b/nrf/boards/pca10031/nrf51_hal_conf.h index ecc150fe9e..e83e2d346e 100644 --- a/nrf/boards/pca10031/nrf51_hal_conf.h +++ b/nrf/boards/pca10031/nrf51_hal_conf.h @@ -4,6 +4,10 @@ #define HAL_UART_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ From 5d28a99114b495352655470ab022f0fe28c99cb9 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 8 Jun 2017 21:42:13 +0200 Subject: [PATCH 787/809] nrf/boards: Activate RTC and Timer module and HAL on pca10056. Also swapping out UART with UART DMA variant on this target board. --- nrf/boards/pca10056/mpconfigboard.h | 2 ++ nrf/boards/pca10056/nrf52_hal_conf.h | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/nrf/boards/pca10056/mpconfigboard.h b/nrf/boards/pca10056/mpconfigboard.h index 05cf1a7be0..b28112a186 100644 --- a/nrf/boards/pca10056/mpconfigboard.h +++ b/nrf/boards/pca10056/mpconfigboard.h @@ -32,6 +32,8 @@ #define MICROPY_PY_MACHINE_HW_PWM (1) #define MICROPY_PY_MACHINE_HW_SPI (1) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) #define MICROPY_PY_MACHINE_I2C (1) #define MICROPY_PY_MACHINE_ADC (1) #define MICROPY_PY_MACHINE_TEMP (1) diff --git a/nrf/boards/pca10056/nrf52_hal_conf.h b/nrf/boards/pca10056/nrf52_hal_conf.h index 585506b8d6..0db35d615b 100644 --- a/nrf/boards/pca10056/nrf52_hal_conf.h +++ b/nrf/boards/pca10056/nrf52_hal_conf.h @@ -1,7 +1,7 @@ #ifndef NRF52_HAL_CONF_H__ #define NRF52_HAL_CONF_H__ -#define HAL_UART_MODULE_ENABLED +// #define HAL_UART_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED #define HAL_PWM_MODULE_ENABLED @@ -10,7 +10,7 @@ #define HAL_TWI_MODULE_ENABLED #define HAL_ADCE_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED -// #define HAL_UARTE_MODULE_ENABLED +#define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED From 708571834a7a0c92273e628c2854b4ebefad3f4f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Thu, 8 Jun 2017 23:36:26 +0200 Subject: [PATCH 788/809] nrf/examples: Update ssd1306 modification example to import correct class. --- nrf/examples/ssd1306_mod.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nrf/examples/ssd1306_mod.py b/nrf/examples/ssd1306_mod.py index 5480c646c2..0cee2c2a67 100644 --- a/nrf/examples/ssd1306_mod.py +++ b/nrf/examples/ssd1306_mod.py @@ -14,7 +14,7 @@ # Example usage of SSD1306_I2C on pca10040 # # from machine import Pin, I2C -# from ssd1306 import SSD1306_I2C +# from ssd1306_mod import SSD1306_I2C_Mod # i2c = I2C(0, Pin.board.PA3, Pin.board.PA4) # disp = SSD1306_I2C_Mod(128, 64, i2c) From 30b27b1370a113241a9ee218a74ef0c322164741 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 9 Jun 2017 00:06:26 +0200 Subject: [PATCH 789/809] nrf/boards: Correcting feather52 I2C SDA pin assigned to the board. --- nrf/boards/feather52/pins.csv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nrf/boards/feather52/pins.csv b/nrf/boards/feather52/pins.csv index 9ac45403c3..b7017602a7 100644 --- a/nrf/boards/feather52/pins.csv +++ b/nrf/boards/feather52/pins.csv @@ -16,9 +16,9 @@ PA16,PA16 LED1,PA17 LED2,PA19 PA20,PA20 -PA25,PA25 +I2C_SDA,PA25 I2C_SCL,PA26 -I2C_SDA,PA27 +PA27,PA27 PA28,PA28,ADC0_IN4 PA29,PA29,ADC0_IN5 PA30,PA30,ADC0_IN6 From 72a564b065ba26f143c82ec62b9a784088733a9c Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 9 Jun 2017 00:48:37 +0200 Subject: [PATCH 790/809] nrf/boards: Updating microbit pin mapping for SPI and I2C. --- nrf/boards/microbit/mpconfigboard.h | 6 +++--- nrf/boards/microbit/pins.csv | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/nrf/boards/microbit/mpconfigboard.h b/nrf/boards/microbit/mpconfigboard.h index 5985d04661..935a0049b7 100644 --- a/nrf/boards/microbit/mpconfigboard.h +++ b/nrf/boards/microbit/mpconfigboard.h @@ -60,9 +60,9 @@ // SPI0 config #define MICROPY_HW_SPI0_NAME "SPI0" -#define MICROPY_HW_SPI0_SCK (pin_A13) -#define MICROPY_HW_SPI0_MOSI (pin_A15) -#define MICROPY_HW_SPI0_MISO (pin_A14) +#define MICROPY_HW_SPI0_SCK (pin_A23) +#define MICROPY_HW_SPI0_MOSI (pin_A21) +#define MICROPY_HW_SPI0_MISO (pin_A22) // micro:bit music pin #define MICROPY_HW_MUSIC_PIN (pin_A3) diff --git a/nrf/boards/microbit/pins.csv b/nrf/boards/microbit/pins.csv index 2b16969869..bb118c30a8 100644 --- a/nrf/boards/microbit/pins.csv +++ b/nrf/boards/microbit/pins.csv @@ -1,4 +1,4 @@ -PA0,PA0 +I2C_SCL,PA0 PA1,PA1 PA2,PA2 PA3,PA3 @@ -19,14 +19,14 @@ PA17,PA17 PA18,PA18 PA19,PA19 PA20,PA20 -PA21,PA21 -PA22,PA22 -PA23,PA23 +SPI_MOSI,PA21 +SPI_MISO,PA22 +SPI_SCK,PA23 PA24,PA24 PA25,PA25 PA26,PA26 PA27,PA27 PA28,PA28 PA29,PA29 -PA30,PA30 -PA31,PA31 \ No newline at end of file +I2C_SDA,PA30 +PA31,PA31 From decb260890d75122c8baad670da7c425ec176706 Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Thu, 8 Jun 2017 15:33:31 +0100 Subject: [PATCH 791/809] nrf: Add nordic sd folders to the .gitignore --- nrf/.gitignore | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/nrf/.gitignore b/nrf/.gitignore index 3168dd4aba..ace93515a2 100644 --- a/nrf/.gitignore +++ b/nrf/.gitignore @@ -1 +1,8 @@ -build-*/ \ No newline at end of file +# Nordic files +##################### +drivers/bluetooth/s1*/ + +# Build files +##################### +build-*/ + From 8326d777cc36af4086cc3d9fca00eff83557d710 Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Fri, 9 Jun 2017 10:23:27 +0100 Subject: [PATCH 792/809] nrf/drivers/bluetooth: Allow s132 to use LFCLK --- nrf/drivers/bluetooth/ble_drv.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/nrf/drivers/bluetooth/ble_drv.c b/nrf/drivers/bluetooth/ble_drv.c index dab0e42fb2..c58c087335 100644 --- a/nrf/drivers/bluetooth/ble_drv.c +++ b/nrf/drivers/bluetooth/ble_drv.c @@ -122,6 +122,14 @@ uint32_t ble_drv_stack_enable(void) { uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, softdevice_assert_handler); #endif // BLUETOOTH_LFCLK_RC +#else +#if BLUETOOTH_LFCLK_RC + nrf_clock_lf_cfg_t clock_config = { + .source = NRF_CLOCK_LF_SRC_RC, + .rc_ctiv = 16, + .rc_temp_ctiv = 2, + .xtal_accuracy = 0 + }; #else nrf_clock_lf_cfg_t clock_config = { .source = NRF_CLOCK_LF_SRC_XTAL, @@ -129,7 +137,7 @@ uint32_t ble_drv_stack_enable(void) { .rc_temp_ctiv = 0, .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM }; - +#endif uint32_t err_code = sd_softdevice_enable(&clock_config, softdevice_assert_handler); #endif From 60ad0157f79653d69e0e5be67c59ca434c0ffd25 Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Wed, 10 May 2017 11:39:28 +0100 Subject: [PATCH 793/809] nrf/boards: Add DVK BL652 from Laird To build run 'make BOARD=dvk_bl652 SD=s132' To flash with jlink run 'make sd BOARD=dvk_bl652 SD=s132' This will remove the existing licences in the bl652 --- nrf/boards/dvk_bl652/mpconfigboard.h | 78 ++++++++++++++++++++++ nrf/boards/dvk_bl652/mpconfigboard.mk | 6 ++ nrf/boards/dvk_bl652/mpconfigboard_s132.mk | 10 +++ nrf/boards/dvk_bl652/nrf52_hal_conf.h | 17 +++++ nrf/boards/dvk_bl652/pins.csv | 31 +++++++++ 5 files changed, 142 insertions(+) create mode 100644 nrf/boards/dvk_bl652/mpconfigboard.h create mode 100644 nrf/boards/dvk_bl652/mpconfigboard.mk create mode 100644 nrf/boards/dvk_bl652/mpconfigboard_s132.mk create mode 100644 nrf/boards/dvk_bl652/nrf52_hal_conf.h create mode 100644 nrf/boards/dvk_bl652/pins.csv diff --git a/nrf/boards/dvk_bl652/mpconfigboard.h b/nrf/boards/dvk_bl652/mpconfigboard.h new file mode 100644 index 0000000000..032a599e1f --- /dev/null +++ b/nrf/boards/dvk_bl652/mpconfigboard.h @@ -0,0 +1,78 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define DVK_BL652 + +#define MICROPY_HW_BOARD_NAME "DVK-BL652" +#define MICROPY_HW_MCU_NAME "NRF52832" +#define MICROPY_PY_SYS_PLATFORM "bl652" + +#define MICROPY_PY_MACHINE_PWM (1) +#define MICROPY_PY_MACHINE_HW_SPI (1) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) +#define MICROPY_PY_MACHINE_TEMP (1) + +#define MICROPY_HW_HAS_LED (1) +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_COUNT (2) +#define MICROPY_HW_LED_PULLUP (0) + +#define MICROPY_HW_LED1 (17) // LED1 +#define MICROPY_HW_LED2 (19) // LED2 + +// UART config +#define MICROPY_HW_UART1_RX (pin_A8) +#define MICROPY_HW_UART1_TX (pin_A6) +#define MICROPY_HW_UART1_CTS (pin_A7) +#define MICROPY_HW_UART1_RTS (pin_A5) +#define MICROPY_HW_UART1_HWFC (1) + +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (pin_A25) +#define MICROPY_HW_SPI0_MOSI (pin_A23) +#define MICROPY_HW_SPI0_MISO (pin_A24) + +#define MICROPY_HW_PWM0_NAME "PWM0" +#define MICROPY_HW_PWM1_NAME "PWM1" +#define MICROPY_HW_PWM2_NAME "PWM2" + +#define HELP_TEXT_BOARD_LED "1,2" diff --git a/nrf/boards/dvk_bl652/mpconfigboard.mk b/nrf/boards/dvk_bl652/mpconfigboard.mk new file mode 100644 index 0000000000..83dbb5ab42 --- /dev/null +++ b/nrf/boards/dvk_bl652/mpconfigboard.mk @@ -0,0 +1,6 @@ +MCU_SERIES = m4 +MCU_VARIANT = nrf52 +MCU_SUB_VARIANT = nrf52832 +LD_FILE = boards/nrf52832_512k_64k.ld + +NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf/boards/dvk_bl652/mpconfigboard_s132.mk b/nrf/boards/dvk_bl652/mpconfigboard_s132.mk new file mode 100644 index 0000000000..62e3b0f334 --- /dev/null +++ b/nrf/boards/dvk_bl652/mpconfigboard_s132.mk @@ -0,0 +1,10 @@ +MCU_SERIES = m4 +MCU_VARIANT = nrf52 +MCU_SUB_VARIANT = nrf52832 +SOFTDEV_VERSION = 3.0.0 + +LD_FILE = boards/nrf52832_512k_64k_s132_$(SOFTDEV_VERSION).ld + +NRF_DEFINES += -DNRF52832_XXAA +CFLAGS += -DBLUETOOTH_LFCLK_RC + diff --git a/nrf/boards/dvk_bl652/nrf52_hal_conf.h b/nrf/boards/dvk_bl652/nrf52_hal_conf.h new file mode 100644 index 0000000000..585506b8d6 --- /dev/null +++ b/nrf/boards/dvk_bl652/nrf52_hal_conf.h @@ -0,0 +1,17 @@ +#ifndef NRF52_HAL_CONF_H__ +#define NRF52_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED +#define HAL_PWM_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED +#define HAL_ADCE_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED +// #define HAL_UARTE_MODULE_ENABLED +// #define HAL_SPIE_MODULE_ENABLED +// #define HAL_TWIE_MODULE_ENABLED + +#endif // NRF52_HAL_CONF_H__ diff --git a/nrf/boards/dvk_bl652/pins.csv b/nrf/boards/dvk_bl652/pins.csv new file mode 100644 index 0000000000..126fa5b2f0 --- /dev/null +++ b/nrf/boards/dvk_bl652/pins.csv @@ -0,0 +1,31 @@ +PA2,PA2 +PA3,PA3 +PA4,PA4 +UART_RTS,PA5 +UART_TX,PA6 +UART_CTS,PA7 +UART_RX,PA8 +PA9,PA9 +PA10,PA10 +PA11,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 + From 3193bcc7ee52ce80cd6fe7507239387bd2d47914 Mon Sep 17 00:00:00 2001 From: glennrub Date: Fri, 9 Jun 2017 22:33:51 +0200 Subject: [PATCH 794/809] nrf5: Updating readme with BLE REPL --- nrf/README.md | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/nrf/README.md b/nrf/README.md index ebfedbb945..b6d750550c 100644 --- a/nrf/README.md +++ b/nrf/README.md @@ -68,7 +68,7 @@ If the Bluetooth stacks has been downloaded, compile the target with the followi The **make sd** will trigger a flash of the bluetooth stack before that application is flashed. Note that **make sd** will perform a full erase of the chip, which could cause 3rd party bootloaders to also be wiped. -Note: further tuning of features to include in bluetooth or even setting up the device to use REPL over Bluetooth can be configured in the bluetooth_conf.h. +Note: further tuning of features to include in bluetooth or even setting up the device to use REPL over Bluetooth can be configured in the `bluetooth_conf.h`. ## Target Boards and Make Flags @@ -122,3 +122,18 @@ Example on how to generate and flash feather52 target: make BOARD=feather52 SD=s132 make BOARD=feather52 SD=s132 dfu-gen make BOARD=feather52 SD=s132 dfu-flash + +## Bluetooth LE REPL + +The port also implements a BLE REPL driver. This feature is disabled by default, as it will deactivate the UART REPL when activated. As some of the nRF devices only have one UART, using the BLE REPL free's the UART instance such that it can be used as a general UART peripheral not bound to REPL. + +The configuration can be enabled by editing the `bluetooth_conf.h` and set `MICROPY_PY_BLE_NUS` to 1. + +When enabled you have different options to test it: +* [NUS Console for Linux](https://github.com/tralamazza/nus_console) (recommended) +* [WebBluetooth REPL](https://glennrub.github.io/webbluetooth/micropython/repl/) (experimental) + +Other: +* nRF UART application for IPhone/Android + +WebBluetooth mode can also be configured by editing `bluetooth_conf.h` and set `BLUETOOTH_WEBBLUETOOTH_REPL` to 1. This will alternate advertisement between Eddystone URL and regular connectable advertisement. The Eddystone URL will point the phone or PC to download [WebBluetooth REPL](https://glennrub.github.io/webbluetooth/micropython/repl/) (experimental), which subsequently can be used to connect to the Bluetooth REPL from the PC or Phone browser. From def719e7a70e3c488a2c6721d93b642f89b26b68 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Fri, 4 Aug 2017 18:05:38 +0200 Subject: [PATCH 795/809] nrf: Use the name MicroPython consistently in comments There were several different spellings of MicroPython present in comments, when there should be only one. Aligning to upstream commit 55f33240f3d7051d4213629e92437a36f1fac50e. --- nrf/README.md | 2 +- nrf/boards/dvk_bl652/mpconfigboard.h | 2 +- nrf/boards/feather52/mpconfigboard.h | 2 +- nrf/boards/microbit/mpconfigboard.h | 2 +- nrf/boards/pca10000/mpconfigboard.h | 2 +- nrf/boards/pca10001/mpconfigboard.h | 2 +- nrf/boards/pca10028/mpconfigboard.h | 2 +- nrf/boards/pca10031/mpconfigboard.h | 2 +- nrf/boards/pca10040/mpconfigboard.h | 2 +- nrf/boards/pca10056/mpconfigboard.h | 2 +- nrf/device/nrf51/startup_nrf51822.c | 2 +- nrf/device/nrf52/startup_nrf52832.c | 2 +- nrf/device/nrf52/startup_nrf52840.c | 2 +- nrf/drivers/bluetooth/ble_drv.c | 2 +- nrf/drivers/bluetooth/ble_drv.h | 2 +- nrf/drivers/bluetooth/ble_uart.c | 2 +- nrf/drivers/bluetooth/ble_uart.h | 2 +- nrf/drivers/softpwm.c | 2 +- nrf/drivers/ticker.c | 2 +- nrf/examples/nrf52_servo.py | 2 +- nrf/examples/powerup.py | 2 +- nrf/examples/seeed_tft.py | 2 +- nrf/examples/ubluepy_temp.py | 2 +- nrf/gccollect.c | 2 +- nrf/gccollect.h | 2 +- nrf/hal/hal_adc.c | 2 +- nrf/hal/hal_adc.h | 2 +- nrf/hal/hal_adce.c | 2 +- nrf/hal/hal_gpio.c | 2 +- nrf/hal/hal_gpio.h | 2 +- nrf/hal/hal_irq.h | 2 +- nrf/hal/hal_pwm.c | 2 +- nrf/hal/hal_pwm.h | 2 +- nrf/hal/hal_qspie.c | 2 +- nrf/hal/hal_qspie.h | 2 +- nrf/hal/hal_rtc.c | 2 +- nrf/hal/hal_rtc.h | 2 +- nrf/hal/hal_spi.c | 2 +- nrf/hal/hal_spi.h | 2 +- nrf/hal/hal_spie.c | 2 +- nrf/hal/hal_temp.c | 2 +- nrf/hal/hal_temp.h | 2 +- nrf/hal/hal_time.c | 2 +- nrf/hal/hal_time.h | 2 +- nrf/hal/hal_timer.c | 2 +- nrf/hal/hal_timer.h | 2 +- nrf/hal/hal_twi.c | 2 +- nrf/hal/hal_twi.h | 2 +- nrf/hal/hal_twie.c | 2 +- nrf/hal/hal_uart.c | 2 +- nrf/hal/hal_uart.h | 2 +- nrf/hal/hal_uarte.c | 2 +- nrf/hal/nrf51_hal.h | 2 +- nrf/hal/nrf52_hal.h | 2 +- nrf/help.c | 2 +- nrf/main.c | 2 +- nrf/modules/ble/help_sd.h | 2 +- nrf/modules/ble/modble.c | 2 +- nrf/modules/machine/adc.c | 2 +- nrf/modules/machine/adc.h | 2 +- nrf/modules/machine/i2c.c | 2 +- nrf/modules/machine/i2c.h | 2 +- nrf/modules/machine/led.c | 4 ++-- nrf/modules/machine/led.h | 2 +- nrf/modules/machine/modmachine.c | 2 +- nrf/modules/machine/modmachine.h | 2 +- nrf/modules/machine/pin.c | 2 +- nrf/modules/machine/pin.h | 2 +- nrf/modules/machine/pwm.c | 2 +- nrf/modules/machine/pwm.h | 2 +- nrf/modules/machine/rtc.c | 2 +- nrf/modules/machine/rtc.h | 2 +- nrf/modules/machine/spi.c | 2 +- nrf/modules/machine/spi.h | 2 +- nrf/modules/machine/temp.c | 2 +- nrf/modules/machine/temp.h | 2 +- nrf/modules/machine/timer.c | 2 +- nrf/modules/machine/timer.h | 2 +- nrf/modules/machine/uart.c | 4 ++-- nrf/modules/machine/uart.h | 2 +- nrf/modules/music/modmusic.c | 2 +- nrf/modules/music/musictunes.c | 2 +- nrf/modules/music/musictunes.h | 2 +- nrf/modules/pyb/modpyb.c | 2 +- nrf/modules/ubluepy/modubluepy.c | 2 +- nrf/modules/ubluepy/modubluepy.h | 2 +- nrf/modules/ubluepy/ubluepy_characteristic.c | 2 +- nrf/modules/ubluepy/ubluepy_constants.c | 2 +- nrf/modules/ubluepy/ubluepy_delegate.c | 2 +- nrf/modules/ubluepy/ubluepy_descriptor.c | 2 +- nrf/modules/ubluepy/ubluepy_peripheral.c | 2 +- nrf/modules/ubluepy/ubluepy_scan_entry.c | 2 +- nrf/modules/ubluepy/ubluepy_scanner.c | 2 +- nrf/modules/ubluepy/ubluepy_service.c | 2 +- nrf/modules/ubluepy/ubluepy_uuid.c | 2 +- nrf/modules/uos/moduos.c | 2 +- nrf/modules/utime/modutime.c | 2 +- nrf/mpconfigport.h | 4 ++-- nrf/mphalport.c | 2 +- nrf/mphalport.h | 2 +- nrf/pin_defs_nrf5.h | 2 +- nrf/pin_named_pins.c | 2 +- nrf/qstrdefsport.h | 2 +- 103 files changed, 106 insertions(+), 106 deletions(-) diff --git a/nrf/README.md b/nrf/README.md index b6d750550c..3cba4df485 100644 --- a/nrf/README.md +++ b/nrf/README.md @@ -17,7 +17,7 @@ This is a port of MicroPython to the Nordic Semiconductor nRF series of chips. * Peripheral role on nrf51 targets * Central role and Peripheral role on nrf52 targets * _REPL over Bluetooth LE_ (optionally using WebBluetooth) - * ubluepy: Bluetooth LE module for micropython + * ubluepy: Bluetooth LE module for MicroPython * 1 non-connectable advertiser while in connection ## Tested Hardware diff --git a/nrf/boards/dvk_bl652/mpconfigboard.h b/nrf/boards/dvk_bl652/mpconfigboard.h index 032a599e1f..1eb9fe5c9a 100644 --- a/nrf/boards/dvk_bl652/mpconfigboard.h +++ b/nrf/boards/dvk_bl652/mpconfigboard.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/boards/feather52/mpconfigboard.h b/nrf/boards/feather52/mpconfigboard.h index 9a97381ec5..fca9274b79 100644 --- a/nrf/boards/feather52/mpconfigboard.h +++ b/nrf/boards/feather52/mpconfigboard.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/boards/microbit/mpconfigboard.h b/nrf/boards/microbit/mpconfigboard.h index 935a0049b7..6dc8b0597f 100644 --- a/nrf/boards/microbit/mpconfigboard.h +++ b/nrf/boards/microbit/mpconfigboard.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/boards/pca10000/mpconfigboard.h b/nrf/boards/pca10000/mpconfigboard.h index 46efdad307..75932a4937 100644 --- a/nrf/boards/pca10000/mpconfigboard.h +++ b/nrf/boards/pca10000/mpconfigboard.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/boards/pca10001/mpconfigboard.h b/nrf/boards/pca10001/mpconfigboard.h index bd49876862..e2320752ae 100644 --- a/nrf/boards/pca10001/mpconfigboard.h +++ b/nrf/boards/pca10001/mpconfigboard.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/boards/pca10028/mpconfigboard.h b/nrf/boards/pca10028/mpconfigboard.h index ef9a0a94bf..3c557bdb49 100644 --- a/nrf/boards/pca10028/mpconfigboard.h +++ b/nrf/boards/pca10028/mpconfigboard.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/boards/pca10031/mpconfigboard.h b/nrf/boards/pca10031/mpconfigboard.h index d8b69e2ede..78d66e4b3d 100644 --- a/nrf/boards/pca10031/mpconfigboard.h +++ b/nrf/boards/pca10031/mpconfigboard.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/boards/pca10040/mpconfigboard.h b/nrf/boards/pca10040/mpconfigboard.h index c46db9ea6c..7c46aa381d 100644 --- a/nrf/boards/pca10040/mpconfigboard.h +++ b/nrf/boards/pca10040/mpconfigboard.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/boards/pca10056/mpconfigboard.h b/nrf/boards/pca10056/mpconfigboard.h index b28112a186..dc16f65674 100644 --- a/nrf/boards/pca10056/mpconfigboard.h +++ b/nrf/boards/pca10056/mpconfigboard.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/device/nrf51/startup_nrf51822.c b/nrf/device/nrf51/startup_nrf51822.c index 826339da3f..add8218e6c 100644 --- a/nrf/device/nrf51/startup_nrf51822.c +++ b/nrf/device/nrf51/startup_nrf51822.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/device/nrf52/startup_nrf52832.c b/nrf/device/nrf52/startup_nrf52832.c index d568fd62be..b36ac0d971 100644 --- a/nrf/device/nrf52/startup_nrf52832.c +++ b/nrf/device/nrf52/startup_nrf52832.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/device/nrf52/startup_nrf52840.c b/nrf/device/nrf52/startup_nrf52840.c index 6d0347f7a8..998696c08e 100644 --- a/nrf/device/nrf52/startup_nrf52840.c +++ b/nrf/device/nrf52/startup_nrf52840.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/drivers/bluetooth/ble_drv.c b/nrf/drivers/bluetooth/ble_drv.c index c58c087335..2bb6fac2d2 100644 --- a/nrf/drivers/bluetooth/ble_drv.c +++ b/nrf/drivers/bluetooth/ble_drv.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/drivers/bluetooth/ble_drv.h b/nrf/drivers/bluetooth/ble_drv.h index e038f5cc96..d8b7154671 100644 --- a/nrf/drivers/bluetooth/ble_drv.h +++ b/nrf/drivers/bluetooth/ble_drv.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/drivers/bluetooth/ble_uart.c b/nrf/drivers/bluetooth/ble_uart.c index 61fd18a8ac..28356d61c4 100644 --- a/nrf/drivers/bluetooth/ble_uart.c +++ b/nrf/drivers/bluetooth/ble_uart.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/drivers/bluetooth/ble_uart.h b/nrf/drivers/bluetooth/ble_uart.h index eadc7b37ab..e67176a26f 100644 --- a/nrf/drivers/bluetooth/ble_uart.h +++ b/nrf/drivers/bluetooth/ble_uart.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/drivers/softpwm.c b/nrf/drivers/softpwm.c index 41425a6e2e..22564f7d0a 100644 --- a/nrf/drivers/softpwm.c +++ b/nrf/drivers/softpwm.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/drivers/ticker.c b/nrf/drivers/ticker.c index bbba231213..aa730d643d 100644 --- a/nrf/drivers/ticker.c +++ b/nrf/drivers/ticker.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/examples/nrf52_servo.py b/nrf/examples/nrf52_servo.py index 221ced7111..e9c594af3e 100644 --- a/nrf/examples/nrf52_servo.py +++ b/nrf/examples/nrf52_servo.py @@ -1,4 +1,4 @@ -# This file is part of the Micro Python project, http://micropython.org/ +# This file is part of the MicroPython project, http://micropython.org/ # # The MIT License (MIT) # diff --git a/nrf/examples/powerup.py b/nrf/examples/powerup.py index d65f9b7e3c..fd7dd83439 100644 --- a/nrf/examples/powerup.py +++ b/nrf/examples/powerup.py @@ -1,4 +1,4 @@ -# This file is part of the Micro Python project, http://micropython.org/ +# This file is part of the MicroPython project, http://micropython.org/ # # The MIT License (MIT) # diff --git a/nrf/examples/seeed_tft.py b/nrf/examples/seeed_tft.py index 4e5db06fcb..f751bbb0f2 100644 --- a/nrf/examples/seeed_tft.py +++ b/nrf/examples/seeed_tft.py @@ -1,4 +1,4 @@ -# This file is part of the Micro Python project, http://micropython.org/ +# This file is part of the MicroPython project, http://micropython.org/ # # The MIT License (MIT) # diff --git a/nrf/examples/ubluepy_temp.py b/nrf/examples/ubluepy_temp.py index 59fcfe9694..fac091bc17 100644 --- a/nrf/examples/ubluepy_temp.py +++ b/nrf/examples/ubluepy_temp.py @@ -1,4 +1,4 @@ -# This file is part of the Micro Python project, http://micropython.org/ +# This file is part of the MicroPython project, http://micropython.org/ # # The MIT License (MIT) # diff --git a/nrf/gccollect.c b/nrf/gccollect.c index 7f1d055685..b7aa57a55a 100644 --- a/nrf/gccollect.c +++ b/nrf/gccollect.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/gccollect.h b/nrf/gccollect.h index 297a9d53ae..6a285b017a 100644 --- a/nrf/gccollect.h +++ b/nrf/gccollect.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_adc.c b/nrf/hal/hal_adc.c index e39a1f35cc..a6cf453914 100644 --- a/nrf/hal/hal_adc.c +++ b/nrf/hal/hal_adc.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_adc.h b/nrf/hal/hal_adc.h index deca7d90a7..76ed7e6618 100644 --- a/nrf/hal/hal_adc.h +++ b/nrf/hal/hal_adc.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_adce.c b/nrf/hal/hal_adce.c index fbfe7750b3..90d42338b7 100644 --- a/nrf/hal/hal_adce.c +++ b/nrf/hal/hal_adce.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_gpio.c b/nrf/hal/hal_gpio.c index c36ed9905e..7cc57af2b9 100644 --- a/nrf/hal/hal_gpio.c +++ b/nrf/hal/hal_gpio.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_gpio.h b/nrf/hal/hal_gpio.h index fcdc49ad75..afd03d0dce 100644 --- a/nrf/hal/hal_gpio.h +++ b/nrf/hal/hal_gpio.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_irq.h b/nrf/hal/hal_irq.h index a610f1035a..d8e4ddba42 100644 --- a/nrf/hal/hal_irq.h +++ b/nrf/hal/hal_irq.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_pwm.c b/nrf/hal/hal_pwm.c index a0e69f469f..c7ae31a996 100644 --- a/nrf/hal/hal_pwm.c +++ b/nrf/hal/hal_pwm.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_pwm.h b/nrf/hal/hal_pwm.h index 5097763aa4..49214ed200 100644 --- a/nrf/hal/hal_pwm.h +++ b/nrf/hal/hal_pwm.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_qspie.c b/nrf/hal/hal_qspie.c index c4c59534fb..90863b6203 100644 --- a/nrf/hal/hal_qspie.c +++ b/nrf/hal/hal_qspie.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_qspie.h b/nrf/hal/hal_qspie.h index 85b9a6021f..c964ff4387 100644 --- a/nrf/hal/hal_qspie.h +++ b/nrf/hal/hal_qspie.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_rtc.c b/nrf/hal/hal_rtc.c index d3ea751915..ba968f90c0 100644 --- a/nrf/hal/hal_rtc.c +++ b/nrf/hal/hal_rtc.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_rtc.h b/nrf/hal/hal_rtc.h index 81797bfb55..62bc028b05 100644 --- a/nrf/hal/hal_rtc.h +++ b/nrf/hal/hal_rtc.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_spi.c b/nrf/hal/hal_spi.c index 86758e840f..2de203d237 100644 --- a/nrf/hal/hal_spi.c +++ b/nrf/hal/hal_spi.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_spi.h b/nrf/hal/hal_spi.h index 56e03dffec..cb01284689 100644 --- a/nrf/hal/hal_spi.h +++ b/nrf/hal/hal_spi.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_spie.c b/nrf/hal/hal_spie.c index 994f9914d1..e2639e4560 100644 --- a/nrf/hal/hal_spie.c +++ b/nrf/hal/hal_spie.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_temp.c b/nrf/hal/hal_temp.c index a8435c4ebe..c88814dd1b 100644 --- a/nrf/hal/hal_temp.c +++ b/nrf/hal/hal_temp.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_temp.h b/nrf/hal/hal_temp.h index 4ae5d15b05..b203c944dd 100644 --- a/nrf/hal/hal_temp.h +++ b/nrf/hal/hal_temp.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_time.c b/nrf/hal/hal_time.c index d98dd4de8c..706bd3a175 100644 --- a/nrf/hal/hal_time.c +++ b/nrf/hal/hal_time.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_time.h b/nrf/hal/hal_time.h index 79b643acc7..20393f918b 100644 --- a/nrf/hal/hal_time.h +++ b/nrf/hal/hal_time.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_timer.c b/nrf/hal/hal_timer.c index 46d9c389a5..458353c8ca 100644 --- a/nrf/hal/hal_timer.c +++ b/nrf/hal/hal_timer.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_timer.h b/nrf/hal/hal_timer.h index 25b55557cc..7d109c6d11 100644 --- a/nrf/hal/hal_timer.h +++ b/nrf/hal/hal_timer.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_twi.c b/nrf/hal/hal_twi.c index 551595111b..65d729c94b 100644 --- a/nrf/hal/hal_twi.c +++ b/nrf/hal/hal_twi.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_twi.h b/nrf/hal/hal_twi.h index d7a189e985..834c512a08 100644 --- a/nrf/hal/hal_twi.h +++ b/nrf/hal/hal_twi.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_twie.c b/nrf/hal/hal_twie.c index c784fa1364..cfa930f1d9 100644 --- a/nrf/hal/hal_twie.c +++ b/nrf/hal/hal_twie.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_uart.c b/nrf/hal/hal_uart.c index 13d549e103..39590272b5 100644 --- a/nrf/hal/hal_uart.c +++ b/nrf/hal/hal_uart.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_uart.h b/nrf/hal/hal_uart.h index 3f39f117c3..ca0110c3e4 100644 --- a/nrf/hal/hal_uart.h +++ b/nrf/hal/hal_uart.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/hal_uarte.c b/nrf/hal/hal_uarte.c index 6393c136d1..d3e899b91d 100644 --- a/nrf/hal/hal_uarte.c +++ b/nrf/hal/hal_uarte.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/nrf51_hal.h b/nrf/hal/nrf51_hal.h index e4be297054..68b3c1ae0d 100644 --- a/nrf/hal/nrf51_hal.h +++ b/nrf/hal/nrf51_hal.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/hal/nrf52_hal.h b/nrf/hal/nrf52_hal.h index aab3a84512..daa05e9101 100644 --- a/nrf/hal/nrf52_hal.h +++ b/nrf/hal/nrf52_hal.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/help.c b/nrf/help.c index 8022f5bf6b..a2f6878d0d 100644 --- a/nrf/help.c +++ b/nrf/help.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/main.c b/nrf/main.c index 0b5385fc3d..262573d5ff 100644 --- a/nrf/main.c +++ b/nrf/main.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ble/help_sd.h b/nrf/modules/ble/help_sd.h index 2dde1a9e91..027bbdd513 100644 --- a/nrf/modules/ble/help_sd.h +++ b/nrf/modules/ble/help_sd.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ble/modble.c b/nrf/modules/ble/modble.c index c5904275ff..e025006b17 100644 --- a/nrf/modules/ble/modble.c +++ b/nrf/modules/ble/modble.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/adc.c b/nrf/modules/machine/adc.c index c47e0d775f..61cb6f7b49 100644 --- a/nrf/modules/machine/adc.c +++ b/nrf/modules/machine/adc.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/adc.h b/nrf/modules/machine/adc.h index a9f68e73da..a8ff56fbba 100644 --- a/nrf/modules/machine/adc.h +++ b/nrf/modules/machine/adc.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/i2c.c b/nrf/modules/machine/i2c.c index 75e7528551..943599816e 100644 --- a/nrf/modules/machine/i2c.c +++ b/nrf/modules/machine/i2c.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/i2c.h b/nrf/modules/machine/i2c.h index 46a93a8a63..cd8d4507c3 100644 --- a/nrf/modules/machine/i2c.h +++ b/nrf/modules/machine/i2c.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/led.c b/nrf/modules/machine/led.c index 5b6aab102e..3eec949e9e 100644 --- a/nrf/modules/machine/led.c +++ b/nrf/modules/machine/led.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * @@ -85,7 +85,7 @@ void led_toggle(pyb_led_obj_t * led_obj) { /******************************************************************************/ -/* Micro Python bindings */ +/* MicroPython bindings */ void led_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { pyb_led_obj_t *self = self_in; diff --git a/nrf/modules/machine/led.h b/nrf/modules/machine/led.h index 29139a4d48..c9e20ce4c8 100644 --- a/nrf/modules/machine/led.h +++ b/nrf/modules/machine/led.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/modmachine.c b/nrf/modules/machine/modmachine.c index 443baa9ffb..ad536a37db 100644 --- a/nrf/modules/machine/modmachine.c +++ b/nrf/modules/machine/modmachine.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/modmachine.h b/nrf/modules/machine/modmachine.h index 35852ffec3..76b4ad7242 100644 --- a/nrf/modules/machine/modmachine.h +++ b/nrf/modules/machine/modmachine.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/pin.c b/nrf/modules/machine/pin.c index 472a720d90..3ba0926a2d 100644 --- a/nrf/modules/machine/pin.c +++ b/nrf/modules/machine/pin.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/pin.h b/nrf/modules/machine/pin.h index 2556faf743..1935a0d263 100644 --- a/nrf/modules/machine/pin.h +++ b/nrf/modules/machine/pin.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/pwm.c b/nrf/modules/machine/pwm.c index 522f5425df..eaba96606f 100644 --- a/nrf/modules/machine/pwm.c +++ b/nrf/modules/machine/pwm.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/pwm.h b/nrf/modules/machine/pwm.h index fe4e26c895..85184bae01 100644 --- a/nrf/modules/machine/pwm.h +++ b/nrf/modules/machine/pwm.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/rtc.c b/nrf/modules/machine/rtc.c index 9b5e5601b3..cbf9e62114 100644 --- a/nrf/modules/machine/rtc.c +++ b/nrf/modules/machine/rtc.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/rtc.h b/nrf/modules/machine/rtc.h index 3aa22e262f..6bf6efa6ad 100644 --- a/nrf/modules/machine/rtc.h +++ b/nrf/modules/machine/rtc.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/spi.c b/nrf/modules/machine/spi.c index 34ea45dc18..0a82f1db52 100644 --- a/nrf/modules/machine/spi.c +++ b/nrf/modules/machine/spi.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/spi.h b/nrf/modules/machine/spi.h index 65373b4040..71053fc276 100644 --- a/nrf/modules/machine/spi.h +++ b/nrf/modules/machine/spi.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/temp.c b/nrf/modules/machine/temp.c index 1848fd2985..9f1840c6ef 100644 --- a/nrf/modules/machine/temp.c +++ b/nrf/modules/machine/temp.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/temp.h b/nrf/modules/machine/temp.h index 588d93107d..e8f751bdfa 100644 --- a/nrf/modules/machine/temp.h +++ b/nrf/modules/machine/temp.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/timer.c b/nrf/modules/machine/timer.c index d9d4cf32e5..c8eb2ef30b 100644 --- a/nrf/modules/machine/timer.c +++ b/nrf/modules/machine/timer.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/timer.h b/nrf/modules/machine/timer.h index 7419b1fd85..2989dc69be 100644 --- a/nrf/modules/machine/timer.h +++ b/nrf/modules/machine/timer.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/machine/uart.c b/nrf/modules/machine/uart.c index 08c03876d8..b99afef622 100644 --- a/nrf/modules/machine/uart.c +++ b/nrf/modules/machine/uart.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * @@ -118,7 +118,7 @@ void uart_tx_strn_cooked(machine_hard_uart_obj_t *uart_obj, const char *str, uin } /******************************************************************************/ -/* Micro Python bindings */ +/* MicroPython bindings */ STATIC void machine_hard_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { } diff --git a/nrf/modules/machine/uart.h b/nrf/modules/machine/uart.h index e05744dba8..a4453eadff 100644 --- a/nrf/modules/machine/uart.h +++ b/nrf/modules/machine/uart.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/music/modmusic.c b/nrf/modules/music/modmusic.c index 06d98aec12..13efc18bf8 100644 --- a/nrf/modules/music/modmusic.c +++ b/nrf/modules/music/modmusic.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/music/musictunes.c b/nrf/modules/music/musictunes.c index 2d9f9d38ba..f5e7f4a519 100644 --- a/nrf/modules/music/musictunes.c +++ b/nrf/modules/music/musictunes.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The music encoded herein is either in the public domain, composed by * Nicholas H.Tollervey or the composer is untraceable and covered by fair diff --git a/nrf/modules/music/musictunes.h b/nrf/modules/music/musictunes.h index 152b4058e4..82dda5cc7a 100644 --- a/nrf/modules/music/musictunes.h +++ b/nrf/modules/music/musictunes.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/pyb/modpyb.c b/nrf/modules/pyb/modpyb.c index f6cf2b1069..dc2f0ae517 100644 --- a/nrf/modules/pyb/modpyb.c +++ b/nrf/modules/pyb/modpyb.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/modubluepy.c b/nrf/modules/ubluepy/modubluepy.c index dae4e713bc..b306c065b2 100644 --- a/nrf/modules/ubluepy/modubluepy.c +++ b/nrf/modules/ubluepy/modubluepy.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/modubluepy.h b/nrf/modules/ubluepy/modubluepy.h index e8edf27dc0..83d86c5dfd 100644 --- a/nrf/modules/ubluepy/modubluepy.h +++ b/nrf/modules/ubluepy/modubluepy.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/ubluepy_characteristic.c b/nrf/modules/ubluepy/ubluepy_characteristic.c index ea3f9b29e5..8e1d0eb1e4 100644 --- a/nrf/modules/ubluepy/ubluepy_characteristic.c +++ b/nrf/modules/ubluepy/ubluepy_characteristic.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/ubluepy_constants.c b/nrf/modules/ubluepy/ubluepy_constants.c index 0f291d6a24..14e433e6eb 100644 --- a/nrf/modules/ubluepy/ubluepy_constants.c +++ b/nrf/modules/ubluepy/ubluepy_constants.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/ubluepy_delegate.c b/nrf/modules/ubluepy/ubluepy_delegate.c index 9df135a285..07bb7f4928 100644 --- a/nrf/modules/ubluepy/ubluepy_delegate.c +++ b/nrf/modules/ubluepy/ubluepy_delegate.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/ubluepy_descriptor.c b/nrf/modules/ubluepy/ubluepy_descriptor.c index d67db066b4..b15301954d 100644 --- a/nrf/modules/ubluepy/ubluepy_descriptor.c +++ b/nrf/modules/ubluepy/ubluepy_descriptor.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/ubluepy_peripheral.c b/nrf/modules/ubluepy/ubluepy_peripheral.c index a54fe2e673..48e4673748 100644 --- a/nrf/modules/ubluepy/ubluepy_peripheral.c +++ b/nrf/modules/ubluepy/ubluepy_peripheral.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/ubluepy_scan_entry.c b/nrf/modules/ubluepy/ubluepy_scan_entry.c index e9028f9320..8a936d5928 100644 --- a/nrf/modules/ubluepy/ubluepy_scan_entry.c +++ b/nrf/modules/ubluepy/ubluepy_scan_entry.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/ubluepy_scanner.c b/nrf/modules/ubluepy/ubluepy_scanner.c index b7c9b99758..b9c442ac59 100644 --- a/nrf/modules/ubluepy/ubluepy_scanner.c +++ b/nrf/modules/ubluepy/ubluepy_scanner.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/ubluepy_service.c b/nrf/modules/ubluepy/ubluepy_service.c index 3cff2377da..68d905743f 100644 --- a/nrf/modules/ubluepy/ubluepy_service.c +++ b/nrf/modules/ubluepy/ubluepy_service.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/ubluepy/ubluepy_uuid.c b/nrf/modules/ubluepy/ubluepy_uuid.c index 1d34097c4a..380d2e4046 100644 --- a/nrf/modules/ubluepy/ubluepy_uuid.c +++ b/nrf/modules/ubluepy/ubluepy_uuid.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/uos/moduos.c b/nrf/modules/uos/moduos.c index da5a303152..50ca9a90ef 100644 --- a/nrf/modules/uos/moduos.c +++ b/nrf/modules/uos/moduos.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/modules/utime/modutime.c b/nrf/modules/utime/modutime.c index bb3f6a401a..8e9c05c1ee 100644 --- a/nrf/modules/utime/modutime.c +++ b/nrf/modules/utime/modutime.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/mpconfigport.h b/nrf/mpconfigport.h index a21bf89030..4c437f0232 100644 --- a/nrf/mpconfigport.h +++ b/nrf/mpconfigport.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * @@ -29,7 +29,7 @@ #include -// options to control how Micro Python is built +// options to control how MicroPython is built #define MICROPY_ALLOC_PATH_MAX (512) #define MICROPY_PERSISTENT_CODE_LOAD (0) #define MICROPY_EMIT_THUMB (0) diff --git a/nrf/mphalport.c b/nrf/mphalport.c index 92c6d34af2..1abd4b186a 100644 --- a/nrf/mphalport.c +++ b/nrf/mphalport.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/mphalport.h b/nrf/mphalport.h index bda223cea3..4e4e117033 100644 --- a/nrf/mphalport.h +++ b/nrf/mphalport.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/pin_defs_nrf5.h b/nrf/pin_defs_nrf5.h index 1d4146b120..94f8f3c9c1 100644 --- a/nrf/pin_defs_nrf5.h +++ b/nrf/pin_defs_nrf5.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/pin_named_pins.c b/nrf/pin_named_pins.c index 9e5f9593b4..e1d8736b9c 100644 --- a/nrf/pin_named_pins.c +++ b/nrf/pin_named_pins.c @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * diff --git a/nrf/qstrdefsport.h b/nrf/qstrdefsport.h index c945ca779d..ef398a4c0a 100644 --- a/nrf/qstrdefsport.h +++ b/nrf/qstrdefsport.h @@ -1,5 +1,5 @@ /* - * This file is part of the Micro Python project, http://micropython.org/ + * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) * From c017f2d2673007e9890a38514f2575e8627ad903 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 13 Jun 2017 21:04:19 +0200 Subject: [PATCH 796/809] nrf/drivers/bluetooth: Speedup Bluetooth LE REPL. Updating mp_hal_stdout_tx_strn_cooked to pass on the whole string to mp_hal_stdout_tx_strn instead of passing byte by byte. --- nrf/drivers/bluetooth/ble_uart.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/nrf/drivers/bluetooth/ble_uart.c b/nrf/drivers/bluetooth/ble_uart.c index 28356d61c4..cc829750cd 100644 --- a/nrf/drivers/bluetooth/ble_uart.c +++ b/nrf/drivers/bluetooth/ble_uart.c @@ -129,9 +129,7 @@ void mp_hal_stdout_tx_strn(const char *str, size_t len) { } void mp_hal_stdout_tx_strn_cooked(const char *str, mp_uint_t len) { - for (uint8_t i = 0; i < len; i++) { - mp_hal_stdout_tx_strn(&str[i], 1); - } + mp_hal_stdout_tx_strn(str, len); } STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data) { From 3e0d3d283d5619e52e04dc8484d7bf413e66d130 Mon Sep 17 00:00:00 2001 From: Daniel Tralamazza Date: Mon, 7 Aug 2017 04:03:58 +0200 Subject: [PATCH 797/809] nrf: clean compiler warnings --- nrf/fatfs_port.c | 2 +- nrf/hal/hal_adce.c | 4 ++-- nrf/modules/machine/pin.c | 24 ++++++++++++------------ 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/nrf/fatfs_port.c b/nrf/fatfs_port.c index 4d44e2d1d5..13ac21fb1b 100644 --- a/nrf/fatfs_port.c +++ b/nrf/fatfs_port.c @@ -29,5 +29,5 @@ DWORD get_fattime(void) { // TODO: Implement this function. For now, fake it. - return ((2000 + 2016 - 1980) << 25) | ((12) << 21) | ((4) << 16) | ((00) << 11) | ((18) << 5) | (23 / 2); + return ((2016 - 1980) << 25) | ((12) << 21) | ((4) << 16) | ((00) << 11) | ((18) << 5) | (23 / 2); } diff --git a/nrf/hal/hal_adce.c b/nrf/hal/hal_adce.c index 90d42338b7..0abdf07c37 100644 --- a/nrf/hal/hal_adce.c +++ b/nrf/hal/hal_adce.c @@ -43,7 +43,7 @@ static const uint32_t hal_adc_input_lookup_pos[] = { #define HAL_ADCE_PSELP_NOT_CONNECTED (SAADC_CH_PSELP_PSELP_NC << SAADC_CH_PSELP_PSELP_Pos) #define HAL_ADCE_PSELP_VDD (SAADC_CH_PSELP_PSELP_VDD << SAADC_CH_PSELP_PSELP_Pos) -static const uint32_t hal_adc_input_lookup_neg[] = { +/*static const uint32_t hal_adc_input_lookup_neg[] = { SAADC_CH_PSELN_PSELN_AnalogInput0 << SAADC_CH_PSELN_PSELN_Pos, SAADC_CH_PSELN_PSELN_AnalogInput1 << SAADC_CH_PSELN_PSELN_Pos, SAADC_CH_PSELN_PSELN_AnalogInput2 << SAADC_CH_PSELN_PSELN_Pos, @@ -52,7 +52,7 @@ static const uint32_t hal_adc_input_lookup_neg[] = { SAADC_CH_PSELN_PSELN_AnalogInput5 << SAADC_CH_PSELN_PSELN_Pos, SAADC_CH_PSELN_PSELN_AnalogInput6 << SAADC_CH_PSELN_PSELN_Pos, SAADC_CH_PSELN_PSELN_AnalogInput7 << SAADC_CH_PSELN_PSELN_Pos -}; +};*/ #define HAL_ADCE_PSELN_NOT_CONNECTED (SAADC_CH_PSELN_PSELN_NC << SAADC_CH_PSELN_PSELN_Pos) #define HAL_ADCE_PSELN_VDD (SAADC_CH_PSELN_PSELN_VDD << SAADC_CH_PSELN_PSELN_Pos) diff --git a/nrf/modules/machine/pin.c b/nrf/modules/machine/pin.c index 3ba0926a2d..126ec02d3f 100644 --- a/nrf/modules/machine/pin.c +++ b/nrf/modules/machine/pin.c @@ -666,30 +666,30 @@ typedef struct _pin_irq_obj_t { pin_obj_t pin; } pin_irq_obj_t; -STATIC const mp_obj_type_t pin_irq_type; +// STATIC const mp_obj_type_t pin_irq_type; -STATIC mp_obj_t pin_irq_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_obj_t *args) { +/*STATIC mp_obj_t pin_irq_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_obj_t *args) { pin_irq_obj_t *self = self_in; (void)self; return mp_const_none; -} +}*/ -STATIC mp_obj_t pin_irq_trigger(size_t n_args, const mp_obj_t *args) { +/*STATIC mp_obj_t pin_irq_trigger(size_t n_args, const mp_obj_t *args) { pin_irq_obj_t *self = args[0]; (void)self; return mp_const_none; -} -STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_irq_trigger_obj, 1, 2, pin_irq_trigger); +}*/ +// STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_irq_trigger_obj, 1, 2, pin_irq_trigger); -STATIC const mp_rom_map_elem_t pin_irq_locals_dict_table[] = { - { MP_ROM_QSTR(MP_QSTR_trigger), MP_ROM_PTR(&pin_irq_trigger_obj) }, -}; +// STATIC const mp_rom_map_elem_t pin_irq_locals_dict_table[] = { +// { MP_ROM_QSTR(MP_QSTR_trigger), MP_ROM_PTR(&pin_irq_trigger_obj) }, +// }; -STATIC MP_DEFINE_CONST_DICT(pin_irq_locals_dict, pin_irq_locals_dict_table); +// STATIC MP_DEFINE_CONST_DICT(pin_irq_locals_dict, pin_irq_locals_dict_table); -STATIC const mp_obj_type_t pin_irq_type = { +/*STATIC const mp_obj_type_t pin_irq_type = { { &mp_type_type }, .name = MP_QSTR_IRQ, .call = pin_irq_call, .locals_dict = (mp_obj_dict_t*)&pin_irq_locals_dict, -}; +};*/ From 785fb6928b70afd0c42677b21c71287993d7fdde Mon Sep 17 00:00:00 2001 From: Daniel Tralamazza Date: Tue, 8 Aug 2017 18:45:42 +0200 Subject: [PATCH 798/809] nrf: add a note for running the nrfjprog tool on Linux, and touch up the make sd comment --- nrf/README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/nrf/README.md b/nrf/README.md index 3cba4df485..f3e4ac4999 100644 --- a/nrf/README.md +++ b/nrf/README.md @@ -64,10 +64,11 @@ First prepare the bluetooth folder by downloading Bluetooth LE stacks and header If the Bluetooth stacks has been downloaded, compile the target with the following command: make BOARD=pca10040 SD=s132 - make sd The **make sd** will trigger a flash of the bluetooth stack before that application is flashed. Note that **make sd** will perform a full erase of the chip, which could cause 3rd party bootloaders to also be wiped. + make BOARD=pca10040 SD=s132 sd + Note: further tuning of features to include in bluetooth or even setting up the device to use REPL over Bluetooth can be configured in the `bluetooth_conf.h`. ## Target Boards and Make Flags @@ -97,6 +98,7 @@ Install the necessary tools to flash and debug using Segger: [nrfjprog win32 Download](https://www.nordicsemi.com/eng/nordic/download_resource/33444/40/22191727/53210) +note: On Linux it might be required to link SEGGER's `libjlinkarm.so` inside nrfjprog's folder. ## PyOCD/OpenOCD Targets From 863a5c1734f9c6d4da43c1b3f3f9b528d7c8dcf1 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 18 Jul 2017 00:18:05 +0200 Subject: [PATCH 799/809] nrf: Add support for floating point on nrf52 targets. Duplicating pattern for detecting location of libm, libc and libgcc from teensy port. Activating MICROPY_FLOAT_IMPL (FLOAT) for nrf52 targets and adding libs into the compile. For nrf51 targets it is still set to NONE as code grows to much (about 30k). Some numbers on flash use if MICROPY_FLOAT_IMPL is set to MICROPY_FLOAT_IMPL_FLOAT and math libraries are enabled (lgcc, lc, lm). nrf51: ====== without float support: text data bss dec hex filename 144088 260 30020 174368 2a920 build-pca10028/firmware.elf with float support: text data bss dec hex filename 176228 1336 30020 207584 32ae0 build-pca10028/firmware.elf nrf52: ====== without float support: text data bss dec hex filename 142040 356 36236 178632 2b9c8 build-pca10040/firmware.elf with float support: text data bss dec hex filename 165068 1436 36236 202740 317f4 build-pca10040/firmware.elf --- nrf/Makefile | 12 +++++++++++- nrf/mpconfigport.h | 5 +++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/nrf/Makefile b/nrf/Makefile index 83ed917c52..1b0a7c655b 100644 --- a/nrf/Makefile +++ b/nrf/Makefile @@ -90,7 +90,17 @@ CFLAGS += -Os -DNDEBUG LDFLAGS += -Os endif -LIBS += \ +LIBS = \ + +ifeq ($(MCU_VARIANT), nrf52) +LIBM_FILE_NAME = $(shell $(CC) $(CFLAGS) -print-file-name=libm.a) +LIBC_FILE_NAME = $(shell $(CC) $(CFLAGS) -print-file-name=libc.a) +LIBGCC_FILE_NAME = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) + +LIBS += -L $(dir $(LIBM_FILE_NAME)) -lm +LIBS += -L $(dir $(LIBC_FILE_NAME)) -lc +LIBS += -L $(dir $(LIBGCC_FILE_NAME)) -lgcc +endif SRC_LIB = $(addprefix lib/,\ libc/string0.c \ diff --git a/nrf/mpconfigport.h b/nrf/mpconfigport.h index 4c437f0232..e90c5a4ccd 100644 --- a/nrf/mpconfigport.h +++ b/nrf/mpconfigport.h @@ -45,7 +45,12 @@ #define MICROPY_REPL_AUTO_INDENT (1) #define MICROPY_ENABLE_SOURCE_LINE (0) #define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ) +#if NRF51 #define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_NONE) +#else +#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_FLOAT) +#endif + #define MICROPY_OPT_COMPUTED_GOTO (0) #define MICROPY_OPT_CACHE_MAP_LOOKUP_IN_BYTECODE (0) #define MICROPY_OPT_MPZ_BITWISE (0) From 8c0bbb983b9f917b05aa7390b09966bef567d1fe Mon Sep 17 00:00:00 2001 From: glennrub Date: Wed, 4 Oct 2017 20:44:11 +0200 Subject: [PATCH 800/809] nrf/boards: Adding Arduino Primo board support (#88) * nrf: Adding Arduino Primo board support * nrf: Adding arduino_primo to target boards table in readme.md * nrf/boards: Activating pyb.LED module for arduino_primo board. * nrf/boards: Removing define not needed for arduino_primo Updating arduino_primo board mpconfigboard.h. Removing a define that was wrongly named. Instead of renaming it, it was removed as it was never used. --- nrf/README.md | 1 + nrf/boards/arduino_primo/mpconfigboard.h | 79 +++++++++++++++++++ nrf/boards/arduino_primo/mpconfigboard.mk | 7 ++ .../arduino_primo/mpconfigboard_s132.mk | 9 +++ nrf/boards/arduino_primo/nrf52_hal_conf.h | 17 ++++ nrf/boards/arduino_primo/pins.csv | 30 +++++++ 6 files changed, 143 insertions(+) create mode 100644 nrf/boards/arduino_primo/mpconfigboard.h create mode 100644 nrf/boards/arduino_primo/mpconfigboard.mk create mode 100644 nrf/boards/arduino_primo/mpconfigboard_s132.mk create mode 100644 nrf/boards/arduino_primo/nrf52_hal_conf.h create mode 100644 nrf/boards/arduino_primo/pins.csv diff --git a/nrf/README.md b/nrf/README.md index f3e4ac4999..54d95087a1 100644 --- a/nrf/README.md +++ b/nrf/README.md @@ -82,6 +82,7 @@ pca10028 | s110 | Peripheral | [Segge pca10031 | s110 | Peripheral | [Segger](#segger-targets) pca10040 | s132 | Peripheral and Central | [Segger](#segger-targets) feather52 | s132 | Peripheral and Central | [UART DFU](#dfu-targets) +arduino_primo | s132 | Peripheral and Central | [PyOCD](#pyocdopenocd-targets) pca10056 | | | [Segger](#segger-targets) ## Segger Targets diff --git a/nrf/boards/arduino_primo/mpconfigboard.h b/nrf/boards/arduino_primo/mpconfigboard.h new file mode 100644 index 0000000000..eec2ba3f78 --- /dev/null +++ b/nrf/boards/arduino_primo/mpconfigboard.h @@ -0,0 +1,79 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define MICROPY_HW_BOARD_NAME "Arduino Primo" +#define MICROPY_HW_MCU_NAME "NRF52832" +#define MICROPY_PY_SYS_PLATFORM "nrf52" + +#define MICROPY_PY_MACHINE_SOFT_PWM (1) +#define MICROPY_PY_MUSIC (1) + +#define MICROPY_PY_MACHINE_HW_PWM (1) +#define MICROPY_PY_MACHINE_HW_SPI (1) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) +#define MICROPY_PY_MACHINE_TEMP (1) + +#define MICROPY_HW_HAS_LED (1) +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +#define MICROPY_HW_LED_COUNT (1) +#define MICROPY_HW_LED_PULLUP (0) + +#define MICROPY_HW_LED1 (20) // LED1 + +// UART config +#define MICROPY_HW_UART1_RX (pin_A11) +#define MICROPY_HW_UART1_TX (pin_A12) +#define MICROPY_HW_UART1_HWFC (0) + +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (pin_A25) // (Arduino D13) +#define MICROPY_HW_SPI0_MOSI (pin_A23) // (Arduino D11) +#define MICROPY_HW_SPI0_MISO (pin_A24) // (Arduino D12) + +#define MICROPY_HW_PWM0_NAME "PWM0" +#define MICROPY_HW_PWM1_NAME "PWM1" +#define MICROPY_HW_PWM2_NAME "PWM2" + +// buzzer pin +#define MICROPY_HW_MUSIC_PIN (pin_A8) + +#define HELP_TEXT_BOARD_LED "1" diff --git a/nrf/boards/arduino_primo/mpconfigboard.mk b/nrf/boards/arduino_primo/mpconfigboard.mk new file mode 100644 index 0000000000..0be6b3f953 --- /dev/null +++ b/nrf/boards/arduino_primo/mpconfigboard.mk @@ -0,0 +1,7 @@ +MCU_SERIES = m4 +MCU_VARIANT = nrf52 +MCU_SUB_VARIANT = nrf52832 +LD_FILE = boards/nrf52832_512k_64k.ld +FLASHER = pyocd + +NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf/boards/arduino_primo/mpconfigboard_s132.mk b/nrf/boards/arduino_primo/mpconfigboard_s132.mk new file mode 100644 index 0000000000..cbbafebfa1 --- /dev/null +++ b/nrf/boards/arduino_primo/mpconfigboard_s132.mk @@ -0,0 +1,9 @@ +MCU_SERIES = m4 +MCU_VARIANT = nrf52 +MCU_SUB_VARIANT = nrf52832 +SOFTDEV_VERSION = 3.0.0 +FLASHER=pyocd + +LD_FILE = boards/nrf52832_512k_64k_s132_$(SOFTDEV_VERSION).ld + +NRF_DEFINES += -DNRF52832_XXAA diff --git a/nrf/boards/arduino_primo/nrf52_hal_conf.h b/nrf/boards/arduino_primo/nrf52_hal_conf.h new file mode 100644 index 0000000000..585506b8d6 --- /dev/null +++ b/nrf/boards/arduino_primo/nrf52_hal_conf.h @@ -0,0 +1,17 @@ +#ifndef NRF52_HAL_CONF_H__ +#define NRF52_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED +#define HAL_PWM_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED +#define HAL_ADCE_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED +// #define HAL_UARTE_MODULE_ENABLED +// #define HAL_SPIE_MODULE_ENABLED +// #define HAL_TWIE_MODULE_ENABLED + +#endif // NRF52_HAL_CONF_H__ diff --git a/nrf/boards/arduino_primo/pins.csv b/nrf/boards/arduino_primo/pins.csv new file mode 100644 index 0000000000..c177133983 --- /dev/null +++ b/nrf/boards/arduino_primo/pins.csv @@ -0,0 +1,30 @@ +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA5,PA5 +PA6,PA6 +PA7,PA7 +PA8,PA8 +PA9,PA9 +PA10,PA10 +PA11,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PA16,PA16 +PA17,PA17 +PA18,PA18 +PA19,PA19 +PA20,PA20 +PA21,PA21 +PA22,PA22 +PA23,PA23 +PA24,PA24 +PA25,PA25 +PA26,PA26 +PA27,PA27 +PA28,PA28 +PA29,PA29 +PA30,PA30 +PA31,PA31 \ No newline at end of file From f49b202e7d11c36a41d096a58a0dfeb6af5d1df7 Mon Sep 17 00:00:00 2001 From: glennrub Date: Wed, 4 Oct 2017 20:45:40 +0200 Subject: [PATCH 801/809] nrf/hal/rng: Adding HAL driver for accessing RNG peripheral The driver also takes care of calling the Bluetooth LE stack for random values if the stack is enabled. The reason for this is that the Bluetooth LE stack take ownership of the NRF_RNG when enabled. Tolerate to enable/disable on the fly, and will choose to use direct access to the peripheral if Bluetooth LE stack is disabled or not compiled in at all. Driver has been included in the top Makefile, and will not be compiled in unless nrf51_hal_conf.h/nrf52_hal_conf.h defines HAL_RNG_MODULE_ENABLED (1). --- nrf/Makefile | 1 + nrf/hal/hal_rng.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++ nrf/hal/hal_rng.h | 34 +++++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 nrf/hal/hal_rng.c create mode 100644 nrf/hal/hal_rng.h diff --git a/nrf/Makefile b/nrf/Makefile index 1b0a7c655b..d9ef89075f 100644 --- a/nrf/Makefile +++ b/nrf/Makefile @@ -124,6 +124,7 @@ SRC_HAL = $(addprefix hal/,\ hal_adce.c \ hal_temp.c \ hal_gpio.c \ + hal_rng.c \ ) ifeq ($(MCU_VARIANT), nrf52) diff --git a/nrf/hal/hal_rng.c b/nrf/hal/hal_rng.c new file mode 100644 index 0000000000..39b6f57896 --- /dev/null +++ b/nrf/hal/hal_rng.c @@ -0,0 +1,76 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "hal_rng.h" + +#ifdef HAL_RNG_MODULE_ENABLED + +#if BLUETOOTH_SD +#include "py/nlr.h" +#include "ble_drv.h" +#include "nrf_soc.h" + +#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled()) + +#endif // BLUETOOTH_SD + +uint32_t hal_rng_generate(void) { + + uint32_t retval = 0; + +#if BLUETOOTH_SD + + if (BLUETOOTH_STACK_ENABLED() == 1) { + uint32_t status; + do { + status = sd_rand_application_vector_get((uint8_t *)&retval, 4); // Extract 4 bytes + } while (status != 0); + } else { +#endif + uint8_t * p_retval = (uint8_t *)&retval; + + NRF_RNG->EVENTS_VALRDY = 0; + NRF_RNG->TASKS_START = 1; + + for (uint16_t i = 0; i < 4; i++) { + while (NRF_RNG->EVENTS_VALRDY == 0) { + ; + } + NRF_RNG->EVENTS_VALRDY = 0; + p_retval[i] = NRF_RNG->VALUE; + } + + NRF_RNG->TASKS_STOP = 1; +#if BLUETOOTH_SD + } +#endif + + return retval; +} + +#endif // HAL_RNG_MODULE_ENABLED + diff --git a/nrf/hal/hal_rng.h b/nrf/hal/hal_rng.h new file mode 100644 index 0000000000..d09a26eb9e --- /dev/null +++ b/nrf/hal/hal_rng.h @@ -0,0 +1,34 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HAL_RNG_H__ +#define HAL_RNG_H__ + +#include "nrf.h" + +uint32_t hal_rng_generate(void); + +#endif // HAL_RNG_H__ From 795116b432826496043a5a4f68f391b1706ba664 Mon Sep 17 00:00:00 2001 From: glennrub Date: Wed, 4 Oct 2017 20:49:03 +0200 Subject: [PATCH 802/809] nrf/modules/random: Backport of microbit random number generator module Backport of micro:bit random module. Plugged into the port as a general random module for all nrf51/nrf52 targets. Works both with and without Bluetooth LE stack enabled. Behavioral change: seed() method has been removed, as the use of RNG peripheral generates true random sequences and not pseudo-random sequences. --- nrf/Makefile | 2 + nrf/boards/dvk_bl652/nrf52_hal_conf.h | 1 + nrf/boards/feather52/nrf52_hal_conf.h | 1 + nrf/boards/microbit/nrf51_hal_conf.h | 1 + nrf/boards/pca10000/nrf51_hal_conf.h | 1 + nrf/boards/pca10001/nrf51_hal_conf.h | 1 + nrf/boards/pca10028/nrf51_hal_conf.h | 1 + nrf/boards/pca10031/nrf51_hal_conf.h | 1 + nrf/boards/pca10040/nrf52_hal_conf.h | 1 + nrf/boards/pca10056/nrf52_hal_conf.h | 1 + nrf/modules/random/modrandom.c | 177 ++++++++++++++++++++++++++ nrf/mpconfigport.h | 13 ++ 12 files changed, 201 insertions(+) create mode 100644 nrf/modules/random/modrandom.c diff --git a/nrf/Makefile b/nrf/Makefile index d9ef89075f..be52b749fd 100644 --- a/nrf/Makefile +++ b/nrf/Makefile @@ -54,6 +54,7 @@ INC += -I./hal/$(MCU_VARIANT) INC += -I./modules/machine INC += -I./modules/ubluepy INC += -I./modules/music +INC += -I./modules/random INC += -I./modules/ble INC += -I../lib/mp-readline INC += -I./drivers/bluetooth @@ -173,6 +174,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\ music/modmusic.c \ music/musictunes.c \ ble/modble.c \ + random/modrandom.c \ ) SRC_C += \ diff --git a/nrf/boards/dvk_bl652/nrf52_hal_conf.h b/nrf/boards/dvk_bl652/nrf52_hal_conf.h index 585506b8d6..fd6073a187 100644 --- a/nrf/boards/dvk_bl652/nrf52_hal_conf.h +++ b/nrf/boards/dvk_bl652/nrf52_hal_conf.h @@ -10,6 +10,7 @@ #define HAL_TWI_MODULE_ENABLED #define HAL_ADCE_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED diff --git a/nrf/boards/feather52/nrf52_hal_conf.h b/nrf/boards/feather52/nrf52_hal_conf.h index 585506b8d6..fd6073a187 100644 --- a/nrf/boards/feather52/nrf52_hal_conf.h +++ b/nrf/boards/feather52/nrf52_hal_conf.h @@ -10,6 +10,7 @@ #define HAL_TWI_MODULE_ENABLED #define HAL_ADCE_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED diff --git a/nrf/boards/microbit/nrf51_hal_conf.h b/nrf/boards/microbit/nrf51_hal_conf.h index e83e2d346e..79af193468 100644 --- a/nrf/boards/microbit/nrf51_hal_conf.h +++ b/nrf/boards/microbit/nrf51_hal_conf.h @@ -9,5 +9,6 @@ #define HAL_TWI_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf/boards/pca10000/nrf51_hal_conf.h b/nrf/boards/pca10000/nrf51_hal_conf.h index 484fb8c38f..64d48b14eb 100644 --- a/nrf/boards/pca10000/nrf51_hal_conf.h +++ b/nrf/boards/pca10000/nrf51_hal_conf.h @@ -6,5 +6,6 @@ #define HAL_TIMER_MODULE_ENABLED #define HAL_TIME_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf/boards/pca10001/nrf51_hal_conf.h b/nrf/boards/pca10001/nrf51_hal_conf.h index e83e2d346e..79af193468 100644 --- a/nrf/boards/pca10001/nrf51_hal_conf.h +++ b/nrf/boards/pca10001/nrf51_hal_conf.h @@ -9,5 +9,6 @@ #define HAL_TWI_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf/boards/pca10028/nrf51_hal_conf.h b/nrf/boards/pca10028/nrf51_hal_conf.h index e83e2d346e..79af193468 100644 --- a/nrf/boards/pca10028/nrf51_hal_conf.h +++ b/nrf/boards/pca10028/nrf51_hal_conf.h @@ -9,5 +9,6 @@ #define HAL_TWI_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf/boards/pca10031/nrf51_hal_conf.h b/nrf/boards/pca10031/nrf51_hal_conf.h index e83e2d346e..79af193468 100644 --- a/nrf/boards/pca10031/nrf51_hal_conf.h +++ b/nrf/boards/pca10031/nrf51_hal_conf.h @@ -9,5 +9,6 @@ #define HAL_TWI_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED #endif // NRF51_HAL_CONF_H__ diff --git a/nrf/boards/pca10040/nrf52_hal_conf.h b/nrf/boards/pca10040/nrf52_hal_conf.h index 585506b8d6..fd6073a187 100644 --- a/nrf/boards/pca10040/nrf52_hal_conf.h +++ b/nrf/boards/pca10040/nrf52_hal_conf.h @@ -10,6 +10,7 @@ #define HAL_TWI_MODULE_ENABLED #define HAL_ADCE_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED // #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED diff --git a/nrf/boards/pca10056/nrf52_hal_conf.h b/nrf/boards/pca10056/nrf52_hal_conf.h index 0db35d615b..0f42e8975b 100644 --- a/nrf/boards/pca10056/nrf52_hal_conf.h +++ b/nrf/boards/pca10056/nrf52_hal_conf.h @@ -10,6 +10,7 @@ #define HAL_TWI_MODULE_ENABLED #define HAL_ADCE_MODULE_ENABLED #define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED #define HAL_UARTE_MODULE_ENABLED // #define HAL_SPIE_MODULE_ENABLED // #define HAL_TWIE_MODULE_ENABLED diff --git a/nrf/modules/random/modrandom.c b/nrf/modules/random/modrandom.c new file mode 100644 index 0000000000..0e140750da --- /dev/null +++ b/nrf/modules/random/modrandom.c @@ -0,0 +1,177 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Paul Sokolovsky + * Copyright (c) 2016 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "py/runtime.h" +#include "hal_rng.h" + +#if MICROPY_PY_HW_RNG + +static inline int rand30() { + uint32_t val = hal_rng_generate(); + return (val & 0x3fffffff); // binary mask b00111111111111111111111111111111 +} + +static inline int randbelow(int n) { + return rand30() % n; +} + +STATIC mp_obj_t mod_random_getrandbits(mp_obj_t num_in) { + int n = mp_obj_get_int(num_in); + if (n > 30 || n == 0) { + nlr_raise(mp_obj_new_exception(&mp_type_ValueError)); + } + uint32_t mask = ~0; + // Beware of C undefined behavior when shifting by >= than bit size + mask >>= (32 - n); + return mp_obj_new_int_from_uint(rand30() & mask); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(mod_random_getrandbits_obj, mod_random_getrandbits); + +STATIC mp_obj_t mod_random_randrange(size_t n_args, const mp_obj_t *args) { + mp_int_t start = mp_obj_get_int(args[0]); + if (n_args == 1) { + // range(stop) + if (start > 0) { + return mp_obj_new_int(randbelow(start)); + } else { + nlr_raise(mp_obj_new_exception(&mp_type_ValueError)); + } + } else { + mp_int_t stop = mp_obj_get_int(args[1]); + if (n_args == 2) { + // range(start, stop) + if (start < stop) { + return mp_obj_new_int(start + randbelow(stop - start)); + } else { + nlr_raise(mp_obj_new_exception(&mp_type_ValueError)); + } + } else { + // range(start, stop, step) + mp_int_t step = mp_obj_get_int(args[2]); + mp_int_t n; + if (step > 0) { + n = (stop - start + step - 1) / step; + } else if (step < 0) { + n = (stop - start + step + 1) / step; + } else { + nlr_raise(mp_obj_new_exception(&mp_type_ValueError)); + } + if (n > 0) { + return mp_obj_new_int(start + step * randbelow(n)); + } else { + nlr_raise(mp_obj_new_exception(&mp_type_ValueError)); + } + } + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mod_random_randrange_obj, 1, 3, mod_random_randrange); + +STATIC mp_obj_t mod_random_randint(mp_obj_t a_in, mp_obj_t b_in) { + mp_int_t a = mp_obj_get_int(a_in); + mp_int_t b = mp_obj_get_int(b_in); + if (a <= b) { + return mp_obj_new_int(a + randbelow(b - a + 1)); + } else { + nlr_raise(mp_obj_new_exception(&mp_type_ValueError)); + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(mod_random_randint_obj, mod_random_randint); + +STATIC mp_obj_t mod_random_choice(mp_obj_t seq) { + mp_int_t len = mp_obj_get_int(mp_obj_len(seq)); + if (len > 0) { + return mp_obj_subscr(seq, mp_obj_new_int(randbelow(len)), MP_OBJ_SENTINEL); + } else { + nlr_raise(mp_obj_new_exception(&mp_type_IndexError)); + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(mod_random_choice_obj, mod_random_choice); + +#if MICROPY_PY_BUILTINS_FLOAT + +// returns a number in the range [0..1) using RNG to fill in the fraction bits +STATIC mp_float_t randfloat(void) { + #if MICROPY_FLOAT_IMPL == MICROPY_FLOAT_IMPL_DOUBLE + typedef uint64_t mp_float_int_t; + #elif MICROPY_FLOAT_IMPL == MICROPY_FLOAT_IMPL_FLOAT + typedef uint32_t mp_float_int_t; + #endif + union { + mp_float_t f; + #if MP_ENDIANNESS_LITTLE + struct { mp_float_int_t frc:MP_FLOAT_FRAC_BITS, exp:MP_FLOAT_EXP_BITS, sgn:1; } p; + #else + struct { mp_float_int_t sgn:1, exp:MP_FLOAT_EXP_BITS, frc:MP_FLOAT_FRAC_BITS; } p; + #endif + } u; + u.p.sgn = 0; + u.p.exp = (1 << (MP_FLOAT_EXP_BITS - 1)) - 1; + if (MP_FLOAT_FRAC_BITS <= 30) { + u.p.frc = rand30(); + } else { + u.p.frc = ((uint64_t)rand30() << 30) | (uint64_t)rand30(); + } + return u.f - 1; +} + +STATIC mp_obj_t mod_random_random(void) { + return mp_obj_new_float(randfloat()); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(mod_random_random_obj, mod_random_random); + +STATIC mp_obj_t mod_random_uniform(mp_obj_t a_in, mp_obj_t b_in) { + mp_float_t a = mp_obj_get_float(a_in); + mp_float_t b = mp_obj_get_float(b_in); + return mp_obj_new_float(a + (b - a) * randfloat()); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(mod_random_uniform_obj, mod_random_uniform); + +#endif + +STATIC const mp_rom_map_elem_t mp_module_random_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_random) }, + { MP_ROM_QSTR(MP_QSTR_getrandbits), MP_ROM_PTR(&mod_random_getrandbits_obj) }, + { MP_ROM_QSTR(MP_QSTR_randrange), MP_ROM_PTR(&mod_random_randrange_obj) }, + { MP_ROM_QSTR(MP_QSTR_randint), MP_ROM_PTR(&mod_random_randint_obj) }, + { MP_ROM_QSTR(MP_QSTR_choice), MP_ROM_PTR(&mod_random_choice_obj) }, +#if MICROPY_PY_BUILTINS_FLOAT + { MP_ROM_QSTR(MP_QSTR_random), MP_ROM_PTR(&mod_random_random_obj) }, + { MP_ROM_QSTR(MP_QSTR_uniform), MP_ROM_PTR(&mod_random_uniform_obj) }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(mp_module_random_globals, mp_module_random_globals_table); + +const mp_obj_module_t random_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t*)&mp_module_random_globals, +}; + +#endif // MICROPY_PY_HW_RNG diff --git a/nrf/mpconfigport.h b/nrf/mpconfigport.h index e90c5a4ccd..bc924d514c 100644 --- a/nrf/mpconfigport.h +++ b/nrf/mpconfigport.h @@ -161,6 +161,11 @@ #define MICROPY_PY_MACHINE_RTC (0) #endif +#ifndef MICROPY_PY_HW_RNG +#define MICROPY_PY_HW_RNG (1) +#endif + + #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) #define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0) @@ -200,6 +205,7 @@ extern const struct _mp_obj_module_t mp_module_utime; extern const struct _mp_obj_module_t mp_module_uos; extern const struct _mp_obj_module_t mp_module_ubluepy; extern const struct _mp_obj_module_t music_module; +extern const struct _mp_obj_module_t random_module; #if MICROPY_PY_UBLUEPY #define UBLUEPY_MODULE { MP_ROM_QSTR(MP_QSTR_ubluepy), MP_ROM_PTR(&mp_module_ubluepy) }, @@ -213,6 +219,11 @@ extern const struct _mp_obj_module_t music_module; #define MUSIC_MODULE #endif +#if MICROPY_PY_HW_RNG +#define RANDOM_MODULE { MP_ROM_QSTR(MP_QSTR_random), MP_ROM_PTR(&random_module) }, +#else +#define RANDOM_MODULE +#endif #if BLUETOOTH_SD @@ -232,6 +243,7 @@ extern const struct _mp_obj_module_t ble_module; BLE_MODULE \ MUSIC_MODULE \ UBLUEPY_MODULE \ + RANDOM_MODULE \ #else @@ -242,6 +254,7 @@ extern const struct _mp_obj_module_t ble_module; { MP_ROM_QSTR(MP_QSTR_utime), MP_ROM_PTR(&mp_module_utime) }, \ { MP_ROM_QSTR(MP_QSTR_uos), MP_ROM_PTR(&mp_module_uos) }, \ MUSIC_MODULE \ + RANDOM_MODULE \ #endif // BLUETOOTH_SD From 4468731e3d039a3f72ac25aa43e936cf5ebb3f78 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Tue, 15 Aug 2017 23:37:14 +0200 Subject: [PATCH 803/809] nrf: Aligning with upstream the use of nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, ...) --- nrf/modules/machine/pin.c | 2 +- nrf/modules/music/modmusic.c | 8 ++++---- nrf/modules/uos/moduos.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/nrf/modules/machine/pin.c b/nrf/modules/machine/pin.c index 126ec02d3f..62160d785f 100644 --- a/nrf/modules/machine/pin.c +++ b/nrf/modules/machine/pin.c @@ -125,7 +125,7 @@ const pin_obj_t *pin_find(mp_obj_t user_obj) { pin_obj = mp_call_function_1(MP_STATE_PORT(pin_class_mapper), user_obj); if (pin_obj != mp_const_none) { if (!MP_OBJ_IS_TYPE(pin_obj, &pin_type)) { - nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "Pin.mapper didn't return a Pin object")); + mp_raise_ValueError("Pin.mapper didn't return a Pin object"); } if (pin_class_debug) { printf("Pin.mapper maps "); diff --git a/nrf/modules/music/modmusic.c b/nrf/modules/music/modmusic.c index 13efc18bf8..c2afc341cb 100644 --- a/nrf/modules/music/modmusic.c +++ b/nrf/modules/music/modmusic.c @@ -287,7 +287,7 @@ STATIC mp_obj_t microbit_music_stop(mp_uint_t n_args, const mp_obj_t *args) { #ifdef MICROPY_HW_MUSIC_PIN pin = &MICROPY_HW_MUSIC_PIN; #else - nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "pin parameter not given")); + mp_raise_ValueError("pin parameter not given"); #endif } else { pin = (pin_obj_t *)args[0]; @@ -340,7 +340,7 @@ STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, #ifdef MICROPY_HW_MUSIC_PIN pin = &MICROPY_HW_MUSIC_PIN; #else - nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "pin parameter not given")); + mp_raise_ValueError("pin parameter not given"); #endif } else { pin = (pin_obj_t *)args[1].u_obj; @@ -395,7 +395,7 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, #ifdef MICROPY_HW_MUSIC_PIN pin = &MICROPY_HW_MUSIC_PIN; #else - nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "pin parameter not given")); + mp_raise_ValueError("pin parameter not given"); #endif } else { pin = (pin_obj_t *)args[2].u_obj; @@ -411,7 +411,7 @@ STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, //TODO: pwm_release(pin->name); } else if (pwm_set_period_us(1000000/frequency)) { pwm_release(pin->pin); // TODO: remove pin setting. - nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "invalid pitch")); + mp_raise_ValueError("invalid pitch"); } if (duration >= 0) { // use async machinery to stop the pitch after the duration diff --git a/nrf/modules/uos/moduos.c b/nrf/modules/uos/moduos.c index 50ca9a90ef..84671bc59d 100644 --- a/nrf/modules/uos/moduos.c +++ b/nrf/modules/uos/moduos.c @@ -121,7 +121,7 @@ STATIC mp_obj_t os_dupterm(mp_uint_t n_args, const mp_obj_t *args) { } else if (mp_obj_get_type(args[0]) == &machine_hard_uart_type) { MP_STATE_PORT(pyb_stdio_uart) = args[0]; } else { - nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "need a UART object")); + mp_raise_ValueError("need a UART object"); } return mp_const_none; } From 44e2cb415f0b571e36b9d08def533c018fa99f1f Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Oct 2017 21:46:48 +0200 Subject: [PATCH 804/809] ports/nrf: Moving nrf51/52 port to new ports directory --- {nrf => ports/nrf}/.gitignore | 0 {nrf => ports/nrf}/Makefile | 0 {nrf => ports/nrf}/README.md | 0 {nrf => ports/nrf}/bluetooth_conf.h | 0 {nrf => ports/nrf}/boards/arduino_primo/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/arduino_primo/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/arduino_primo/mpconfigboard_s132.mk | 0 {nrf => ports/nrf}/boards/arduino_primo/nrf52_hal_conf.h | 0 {nrf => ports/nrf}/boards/arduino_primo/pins.csv | 0 {nrf => ports/nrf}/boards/common.ld | 0 {nrf => ports/nrf}/boards/dvk_bl652/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/dvk_bl652/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/dvk_bl652/mpconfigboard_s132.mk | 0 {nrf => ports/nrf}/boards/dvk_bl652/nrf52_hal_conf.h | 0 {nrf => ports/nrf}/boards/dvk_bl652/pins.csv | 0 {nrf => ports/nrf}/boards/feather52/custom_nrf52832_dfu_app.ld | 0 {nrf => ports/nrf}/boards/feather52/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/feather52/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/feather52/mpconfigboard_s132.mk | 0 {nrf => ports/nrf}/boards/feather52/nrf52_hal_conf.h | 0 {nrf => ports/nrf}/boards/feather52/pins.csv | 0 {nrf => ports/nrf}/boards/make-pins.py | 0 {nrf => ports/nrf}/boards/microbit/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/microbit/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/microbit/mpconfigboard_s110.mk | 0 {nrf => ports/nrf}/boards/microbit/nrf51_hal_conf.h | 0 {nrf => ports/nrf}/boards/microbit/pins.csv | 0 {nrf => ports/nrf}/boards/nrf51_prefix.c | 0 {nrf => ports/nrf}/boards/nrf51x22_256k_16k.ld | 0 {nrf => ports/nrf}/boards/nrf51x22_256k_16k_s110_8.0.0.ld | 0 {nrf => ports/nrf}/boards/nrf51x22_256k_32k.ld | 0 {nrf => ports/nrf}/boards/nrf51x22_256k_32k_s110_8.0.0.ld | 0 {nrf => ports/nrf}/boards/nrf51x22_256k_32k_s120_2.1.0.ld | 0 {nrf => ports/nrf}/boards/nrf51x22_256k_32k_s130_2.0.1.ld | 0 {nrf => ports/nrf}/boards/nrf52832_512k_64k.ld | 0 {nrf => ports/nrf}/boards/nrf52832_512k_64k_s132_2.0.1.ld | 0 {nrf => ports/nrf}/boards/nrf52832_512k_64k_s132_3.0.0.ld | 0 {nrf => ports/nrf}/boards/nrf52840_1M_256k.ld | 0 {nrf => ports/nrf}/boards/nrf52_prefix.c | 0 {nrf => ports/nrf}/boards/pca10000/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/pca10000/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/pca10000/mpconfigboard_s110.mk | 0 {nrf => ports/nrf}/boards/pca10000/nrf51_hal_conf.h | 0 {nrf => ports/nrf}/boards/pca10000/pins.csv | 0 {nrf => ports/nrf}/boards/pca10001/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/pca10001/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/pca10001/mpconfigboard_s110.mk | 0 {nrf => ports/nrf}/boards/pca10001/nrf51_hal_conf.h | 0 {nrf => ports/nrf}/boards/pca10001/pins.csv | 0 {nrf => ports/nrf}/boards/pca10028/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/pca10028/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/pca10028/mpconfigboard_s110.mk | 0 {nrf => ports/nrf}/boards/pca10028/mpconfigboard_s120.mk | 0 {nrf => ports/nrf}/boards/pca10028/mpconfigboard_s130.mk | 0 {nrf => ports/nrf}/boards/pca10028/nrf51_hal_conf.h | 0 {nrf => ports/nrf}/boards/pca10028/pins.csv | 0 {nrf => ports/nrf}/boards/pca10031/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/pca10031/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/pca10031/mpconfigboard_s110.mk | 0 {nrf => ports/nrf}/boards/pca10031/mpconfigboard_s120.mk | 0 {nrf => ports/nrf}/boards/pca10031/mpconfigboard_s130.mk | 0 {nrf => ports/nrf}/boards/pca10031/nrf51_hal_conf.h | 0 {nrf => ports/nrf}/boards/pca10031/pins.csv | 0 {nrf => ports/nrf}/boards/pca10040/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/pca10040/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/pca10040/mpconfigboard_s132.mk | 0 {nrf => ports/nrf}/boards/pca10040/nrf52_hal_conf.h | 0 {nrf => ports/nrf}/boards/pca10040/pins.csv | 0 {nrf => ports/nrf}/boards/pca10056/mpconfigboard.h | 0 {nrf => ports/nrf}/boards/pca10056/mpconfigboard.mk | 0 {nrf => ports/nrf}/boards/pca10056/nrf52_hal_conf.h | 0 {nrf => ports/nrf}/boards/pca10056/pins.csv | 0 {nrf => ports/nrf}/builtin_open.c | 0 {nrf => ports/nrf}/device/compiler_abstraction.h | 0 {nrf => ports/nrf}/device/nrf.h | 0 {nrf => ports/nrf}/device/nrf51/nrf51.h | 0 {nrf => ports/nrf}/device/nrf51/nrf51_bitfields.h | 0 {nrf => ports/nrf}/device/nrf51/nrf51_deprecated.h | 0 {nrf => ports/nrf}/device/nrf51/startup_nrf51822.c | 0 {nrf => ports/nrf}/device/nrf51/system_nrf51.h | 0 {nrf => ports/nrf}/device/nrf51/system_nrf51822.c | 0 {nrf => ports/nrf}/device/nrf52/nrf51_to_nrf52.h | 0 {nrf => ports/nrf}/device/nrf52/nrf51_to_nrf52840.h | 0 {nrf => ports/nrf}/device/nrf52/nrf52.h | 0 {nrf => ports/nrf}/device/nrf52/nrf52840.h | 0 {nrf => ports/nrf}/device/nrf52/nrf52840_bitfields.h | 0 {nrf => ports/nrf}/device/nrf52/nrf52_bitfields.h | 0 {nrf => ports/nrf}/device/nrf52/nrf52_name_change.h | 0 {nrf => ports/nrf}/device/nrf52/nrf52_to_nrf52840.h | 0 {nrf => ports/nrf}/device/nrf52/startup_nrf52832.c | 0 {nrf => ports/nrf}/device/nrf52/startup_nrf52840.c | 0 {nrf => ports/nrf}/device/nrf52/system_nrf52.h | 0 {nrf => ports/nrf}/device/nrf52/system_nrf52832.c | 0 {nrf => ports/nrf}/device/nrf52/system_nrf52840.c | 0 {nrf => ports/nrf}/device/nrf52/system_nrf52840.h | 0 {nrf => ports/nrf}/drivers/bluetooth/ble_drv.c | 0 {nrf => ports/nrf}/drivers/bluetooth/ble_drv.h | 0 {nrf => ports/nrf}/drivers/bluetooth/ble_uart.c | 0 {nrf => ports/nrf}/drivers/bluetooth/ble_uart.h | 0 {nrf => ports/nrf}/drivers/bluetooth/bluetooth_common.mk | 0 {nrf => ports/nrf}/drivers/bluetooth/download_ble_stack.sh | 0 {nrf => ports/nrf}/drivers/bluetooth/ringbuffer.h | 0 {nrf => ports/nrf}/drivers/softpwm.c | 0 {nrf => ports/nrf}/drivers/softpwm.h | 0 {nrf => ports/nrf}/drivers/ticker.c | 0 {nrf => ports/nrf}/drivers/ticker.h | 0 {nrf => ports/nrf}/examples/mountsd.py | 0 {nrf => ports/nrf}/examples/musictest.py | 0 {nrf => ports/nrf}/examples/nrf52_pwm.py | 0 {nrf => ports/nrf}/examples/nrf52_servo.py | 0 {nrf => ports/nrf}/examples/powerup.py | 0 {nrf => ports/nrf}/examples/seeed_tft.py | 0 {nrf => ports/nrf}/examples/ssd1306_mod.py | 0 {nrf => ports/nrf}/examples/ubluepy_eddystone.py | 0 {nrf => ports/nrf}/examples/ubluepy_scan.py | 0 {nrf => ports/nrf}/examples/ubluepy_temp.py | 0 {nrf => ports/nrf}/fatfs_port.c | 0 {nrf => ports/nrf}/freeze/test.py | 0 {nrf => ports/nrf}/gccollect.c | 0 {nrf => ports/nrf}/gccollect.h | 0 {nrf => ports/nrf}/hal/hal_adc.c | 0 {nrf => ports/nrf}/hal/hal_adc.h | 0 {nrf => ports/nrf}/hal/hal_adce.c | 0 {nrf => ports/nrf}/hal/hal_gpio.c | 0 {nrf => ports/nrf}/hal/hal_gpio.h | 0 {nrf => ports/nrf}/hal/hal_irq.h | 0 {nrf => ports/nrf}/hal/hal_pwm.c | 0 {nrf => ports/nrf}/hal/hal_pwm.h | 0 {nrf => ports/nrf}/hal/hal_qspie.c | 0 {nrf => ports/nrf}/hal/hal_qspie.h | 0 {nrf => ports/nrf}/hal/hal_rng.c | 0 {nrf => ports/nrf}/hal/hal_rng.h | 0 {nrf => ports/nrf}/hal/hal_rtc.c | 0 {nrf => ports/nrf}/hal/hal_rtc.h | 0 {nrf => ports/nrf}/hal/hal_spi.c | 0 {nrf => ports/nrf}/hal/hal_spi.h | 0 {nrf => ports/nrf}/hal/hal_spie.c | 0 {nrf => ports/nrf}/hal/hal_temp.c | 0 {nrf => ports/nrf}/hal/hal_temp.h | 0 {nrf => ports/nrf}/hal/hal_time.c | 0 {nrf => ports/nrf}/hal/hal_time.h | 0 {nrf => ports/nrf}/hal/hal_timer.c | 0 {nrf => ports/nrf}/hal/hal_timer.h | 0 {nrf => ports/nrf}/hal/hal_twi.c | 0 {nrf => ports/nrf}/hal/hal_twi.h | 0 {nrf => ports/nrf}/hal/hal_twie.c | 0 {nrf => ports/nrf}/hal/hal_uart.c | 0 {nrf => ports/nrf}/hal/hal_uart.h | 0 {nrf => ports/nrf}/hal/hal_uarte.c | 0 {nrf => ports/nrf}/hal/nrf51_hal.h | 0 {nrf => ports/nrf}/hal/nrf52_hal.h | 0 {nrf => ports/nrf}/help.c | 0 {nrf => ports/nrf}/main.c | 0 {nrf => ports/nrf}/modules/ble/help_sd.h | 0 {nrf => ports/nrf}/modules/ble/modble.c | 0 {nrf => ports/nrf}/modules/machine/adc.c | 0 {nrf => ports/nrf}/modules/machine/adc.h | 0 {nrf => ports/nrf}/modules/machine/i2c.c | 0 {nrf => ports/nrf}/modules/machine/i2c.h | 0 {nrf => ports/nrf}/modules/machine/led.c | 0 {nrf => ports/nrf}/modules/machine/led.h | 0 {nrf => ports/nrf}/modules/machine/modmachine.c | 0 {nrf => ports/nrf}/modules/machine/modmachine.h | 0 {nrf => ports/nrf}/modules/machine/pin.c | 0 {nrf => ports/nrf}/modules/machine/pin.h | 0 {nrf => ports/nrf}/modules/machine/pwm.c | 0 {nrf => ports/nrf}/modules/machine/pwm.h | 0 {nrf => ports/nrf}/modules/machine/rtc.c | 0 {nrf => ports/nrf}/modules/machine/rtc.h | 0 {nrf => ports/nrf}/modules/machine/spi.c | 0 {nrf => ports/nrf}/modules/machine/spi.h | 0 {nrf => ports/nrf}/modules/machine/temp.c | 0 {nrf => ports/nrf}/modules/machine/temp.h | 0 {nrf => ports/nrf}/modules/machine/timer.c | 0 {nrf => ports/nrf}/modules/machine/timer.h | 0 {nrf => ports/nrf}/modules/machine/uart.c | 0 {nrf => ports/nrf}/modules/machine/uart.h | 0 {nrf => ports/nrf}/modules/music/modmusic.c | 0 {nrf => ports/nrf}/modules/music/modmusic.h | 0 {nrf => ports/nrf}/modules/music/musictunes.c | 0 {nrf => ports/nrf}/modules/music/musictunes.h | 0 {nrf => ports/nrf}/modules/pyb/modpyb.c | 0 {nrf => ports/nrf}/modules/random/modrandom.c | 0 {nrf => ports/nrf}/modules/ubluepy/modubluepy.c | 0 {nrf => ports/nrf}/modules/ubluepy/modubluepy.h | 0 {nrf => ports/nrf}/modules/ubluepy/ubluepy_characteristic.c | 0 {nrf => ports/nrf}/modules/ubluepy/ubluepy_constants.c | 0 {nrf => ports/nrf}/modules/ubluepy/ubluepy_delegate.c | 0 {nrf => ports/nrf}/modules/ubluepy/ubluepy_descriptor.c | 0 {nrf => ports/nrf}/modules/ubluepy/ubluepy_peripheral.c | 0 {nrf => ports/nrf}/modules/ubluepy/ubluepy_scan_entry.c | 0 {nrf => ports/nrf}/modules/ubluepy/ubluepy_scanner.c | 0 {nrf => ports/nrf}/modules/ubluepy/ubluepy_service.c | 0 {nrf => ports/nrf}/modules/ubluepy/ubluepy_uuid.c | 0 {nrf => ports/nrf}/modules/uos/moduos.c | 0 {nrf => ports/nrf}/modules/utime/modutime.c | 0 {nrf => ports/nrf}/mpconfigport.h | 0 {nrf => ports/nrf}/mphalport.c | 0 {nrf => ports/nrf}/mphalport.h | 0 {nrf => ports/nrf}/nrf51_af.csv | 0 {nrf => ports/nrf}/nrf52_af.csv | 0 {nrf => ports/nrf}/pin_defs_nrf5.h | 0 {nrf => ports/nrf}/pin_named_pins.c | 0 {nrf => ports/nrf}/qstrdefsport.h | 0 204 files changed, 0 insertions(+), 0 deletions(-) rename {nrf => ports/nrf}/.gitignore (100%) rename {nrf => ports/nrf}/Makefile (100%) rename {nrf => ports/nrf}/README.md (100%) rename {nrf => ports/nrf}/bluetooth_conf.h (100%) rename {nrf => ports/nrf}/boards/arduino_primo/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/arduino_primo/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/arduino_primo/mpconfigboard_s132.mk (100%) rename {nrf => ports/nrf}/boards/arduino_primo/nrf52_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/arduino_primo/pins.csv (100%) rename {nrf => ports/nrf}/boards/common.ld (100%) rename {nrf => ports/nrf}/boards/dvk_bl652/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/dvk_bl652/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/dvk_bl652/mpconfigboard_s132.mk (100%) rename {nrf => ports/nrf}/boards/dvk_bl652/nrf52_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/dvk_bl652/pins.csv (100%) rename {nrf => ports/nrf}/boards/feather52/custom_nrf52832_dfu_app.ld (100%) rename {nrf => ports/nrf}/boards/feather52/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/feather52/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/feather52/mpconfigboard_s132.mk (100%) rename {nrf => ports/nrf}/boards/feather52/nrf52_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/feather52/pins.csv (100%) rename {nrf => ports/nrf}/boards/make-pins.py (100%) rename {nrf => ports/nrf}/boards/microbit/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/microbit/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/microbit/mpconfigboard_s110.mk (100%) rename {nrf => ports/nrf}/boards/microbit/nrf51_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/microbit/pins.csv (100%) rename {nrf => ports/nrf}/boards/nrf51_prefix.c (100%) rename {nrf => ports/nrf}/boards/nrf51x22_256k_16k.ld (100%) rename {nrf => ports/nrf}/boards/nrf51x22_256k_16k_s110_8.0.0.ld (100%) rename {nrf => ports/nrf}/boards/nrf51x22_256k_32k.ld (100%) rename {nrf => ports/nrf}/boards/nrf51x22_256k_32k_s110_8.0.0.ld (100%) rename {nrf => ports/nrf}/boards/nrf51x22_256k_32k_s120_2.1.0.ld (100%) rename {nrf => ports/nrf}/boards/nrf51x22_256k_32k_s130_2.0.1.ld (100%) rename {nrf => ports/nrf}/boards/nrf52832_512k_64k.ld (100%) rename {nrf => ports/nrf}/boards/nrf52832_512k_64k_s132_2.0.1.ld (100%) rename {nrf => ports/nrf}/boards/nrf52832_512k_64k_s132_3.0.0.ld (100%) rename {nrf => ports/nrf}/boards/nrf52840_1M_256k.ld (100%) rename {nrf => ports/nrf}/boards/nrf52_prefix.c (100%) rename {nrf => ports/nrf}/boards/pca10000/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/pca10000/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/pca10000/mpconfigboard_s110.mk (100%) rename {nrf => ports/nrf}/boards/pca10000/nrf51_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/pca10000/pins.csv (100%) rename {nrf => ports/nrf}/boards/pca10001/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/pca10001/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/pca10001/mpconfigboard_s110.mk (100%) rename {nrf => ports/nrf}/boards/pca10001/nrf51_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/pca10001/pins.csv (100%) rename {nrf => ports/nrf}/boards/pca10028/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/pca10028/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/pca10028/mpconfigboard_s110.mk (100%) rename {nrf => ports/nrf}/boards/pca10028/mpconfigboard_s120.mk (100%) rename {nrf => ports/nrf}/boards/pca10028/mpconfigboard_s130.mk (100%) rename {nrf => ports/nrf}/boards/pca10028/nrf51_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/pca10028/pins.csv (100%) rename {nrf => ports/nrf}/boards/pca10031/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/pca10031/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/pca10031/mpconfigboard_s110.mk (100%) rename {nrf => ports/nrf}/boards/pca10031/mpconfigboard_s120.mk (100%) rename {nrf => ports/nrf}/boards/pca10031/mpconfigboard_s130.mk (100%) rename {nrf => ports/nrf}/boards/pca10031/nrf51_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/pca10031/pins.csv (100%) rename {nrf => ports/nrf}/boards/pca10040/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/pca10040/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/pca10040/mpconfigboard_s132.mk (100%) rename {nrf => ports/nrf}/boards/pca10040/nrf52_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/pca10040/pins.csv (100%) rename {nrf => ports/nrf}/boards/pca10056/mpconfigboard.h (100%) rename {nrf => ports/nrf}/boards/pca10056/mpconfigboard.mk (100%) rename {nrf => ports/nrf}/boards/pca10056/nrf52_hal_conf.h (100%) rename {nrf => ports/nrf}/boards/pca10056/pins.csv (100%) rename {nrf => ports/nrf}/builtin_open.c (100%) rename {nrf => ports/nrf}/device/compiler_abstraction.h (100%) rename {nrf => ports/nrf}/device/nrf.h (100%) rename {nrf => ports/nrf}/device/nrf51/nrf51.h (100%) rename {nrf => ports/nrf}/device/nrf51/nrf51_bitfields.h (100%) rename {nrf => ports/nrf}/device/nrf51/nrf51_deprecated.h (100%) rename {nrf => ports/nrf}/device/nrf51/startup_nrf51822.c (100%) rename {nrf => ports/nrf}/device/nrf51/system_nrf51.h (100%) rename {nrf => ports/nrf}/device/nrf51/system_nrf51822.c (100%) rename {nrf => ports/nrf}/device/nrf52/nrf51_to_nrf52.h (100%) rename {nrf => ports/nrf}/device/nrf52/nrf51_to_nrf52840.h (100%) rename {nrf => ports/nrf}/device/nrf52/nrf52.h (100%) rename {nrf => ports/nrf}/device/nrf52/nrf52840.h (100%) rename {nrf => ports/nrf}/device/nrf52/nrf52840_bitfields.h (100%) rename {nrf => ports/nrf}/device/nrf52/nrf52_bitfields.h (100%) rename {nrf => ports/nrf}/device/nrf52/nrf52_name_change.h (100%) rename {nrf => ports/nrf}/device/nrf52/nrf52_to_nrf52840.h (100%) rename {nrf => ports/nrf}/device/nrf52/startup_nrf52832.c (100%) rename {nrf => ports/nrf}/device/nrf52/startup_nrf52840.c (100%) rename {nrf => ports/nrf}/device/nrf52/system_nrf52.h (100%) rename {nrf => ports/nrf}/device/nrf52/system_nrf52832.c (100%) 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(100%) rename {nrf => ports/nrf}/examples/powerup.py (100%) rename {nrf => ports/nrf}/examples/seeed_tft.py (100%) rename {nrf => ports/nrf}/examples/ssd1306_mod.py (100%) rename {nrf => ports/nrf}/examples/ubluepy_eddystone.py (100%) rename {nrf => ports/nrf}/examples/ubluepy_scan.py (100%) rename {nrf => ports/nrf}/examples/ubluepy_temp.py (100%) rename {nrf => ports/nrf}/fatfs_port.c (100%) rename {nrf => ports/nrf}/freeze/test.py (100%) rename {nrf => ports/nrf}/gccollect.c (100%) rename {nrf => ports/nrf}/gccollect.h (100%) rename {nrf => ports/nrf}/hal/hal_adc.c (100%) rename {nrf => ports/nrf}/hal/hal_adc.h (100%) rename {nrf => ports/nrf}/hal/hal_adce.c (100%) rename {nrf => ports/nrf}/hal/hal_gpio.c (100%) rename {nrf => ports/nrf}/hal/hal_gpio.h (100%) rename {nrf => ports/nrf}/hal/hal_irq.h (100%) rename {nrf => ports/nrf}/hal/hal_pwm.c (100%) rename {nrf => ports/nrf}/hal/hal_pwm.h (100%) rename {nrf => ports/nrf}/hal/hal_qspie.c (100%) rename {nrf => ports/nrf}/hal/hal_qspie.h (100%) rename {nrf => ports/nrf}/hal/hal_rng.c (100%) rename {nrf => ports/nrf}/hal/hal_rng.h (100%) rename {nrf => ports/nrf}/hal/hal_rtc.c (100%) rename {nrf => ports/nrf}/hal/hal_rtc.h (100%) rename {nrf => ports/nrf}/hal/hal_spi.c (100%) rename {nrf => ports/nrf}/hal/hal_spi.h (100%) rename {nrf => ports/nrf}/hal/hal_spie.c (100%) rename {nrf => ports/nrf}/hal/hal_temp.c (100%) rename {nrf => ports/nrf}/hal/hal_temp.h (100%) rename {nrf => ports/nrf}/hal/hal_time.c (100%) rename {nrf => ports/nrf}/hal/hal_time.h (100%) rename {nrf => ports/nrf}/hal/hal_timer.c (100%) rename {nrf => ports/nrf}/hal/hal_timer.h (100%) rename {nrf => ports/nrf}/hal/hal_twi.c (100%) rename {nrf => ports/nrf}/hal/hal_twi.h (100%) rename {nrf => ports/nrf}/hal/hal_twie.c (100%) rename {nrf => ports/nrf}/hal/hal_uart.c (100%) rename {nrf => ports/nrf}/hal/hal_uart.h (100%) rename {nrf => ports/nrf}/hal/hal_uarte.c (100%) rename {nrf => ports/nrf}/hal/nrf51_hal.h (100%) rename {nrf => ports/nrf}/hal/nrf52_hal.h (100%) rename {nrf => ports/nrf}/help.c (100%) rename {nrf => ports/nrf}/main.c (100%) rename {nrf => ports/nrf}/modules/ble/help_sd.h (100%) rename {nrf => ports/nrf}/modules/ble/modble.c (100%) rename {nrf => ports/nrf}/modules/machine/adc.c (100%) rename {nrf => ports/nrf}/modules/machine/adc.h (100%) rename {nrf => ports/nrf}/modules/machine/i2c.c (100%) rename {nrf => ports/nrf}/modules/machine/i2c.h (100%) rename {nrf => ports/nrf}/modules/machine/led.c (100%) rename {nrf => ports/nrf}/modules/machine/led.h (100%) rename {nrf => ports/nrf}/modules/machine/modmachine.c (100%) rename {nrf => ports/nrf}/modules/machine/modmachine.h (100%) rename {nrf => ports/nrf}/modules/machine/pin.c (100%) rename {nrf => ports/nrf}/modules/machine/pin.h (100%) rename {nrf => ports/nrf}/modules/machine/pwm.c (100%) rename {nrf => ports/nrf}/modules/machine/pwm.h (100%) rename {nrf => ports/nrf}/modules/machine/rtc.c (100%) rename {nrf => ports/nrf}/modules/machine/rtc.h (100%) rename {nrf => ports/nrf}/modules/machine/spi.c (100%) rename {nrf => ports/nrf}/modules/machine/spi.h (100%) rename {nrf => ports/nrf}/modules/machine/temp.c (100%) rename {nrf => ports/nrf}/modules/machine/temp.h (100%) rename {nrf => ports/nrf}/modules/machine/timer.c (100%) rename {nrf => ports/nrf}/modules/machine/timer.h (100%) rename {nrf => ports/nrf}/modules/machine/uart.c (100%) rename {nrf => ports/nrf}/modules/machine/uart.h (100%) rename {nrf => ports/nrf}/modules/music/modmusic.c (100%) rename {nrf => ports/nrf}/modules/music/modmusic.h (100%) rename {nrf => ports/nrf}/modules/music/musictunes.c (100%) rename {nrf => ports/nrf}/modules/music/musictunes.h (100%) rename {nrf => ports/nrf}/modules/pyb/modpyb.c (100%) rename {nrf => ports/nrf}/modules/random/modrandom.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/modubluepy.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/modubluepy.h (100%) rename {nrf => ports/nrf}/modules/ubluepy/ubluepy_characteristic.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/ubluepy_constants.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/ubluepy_delegate.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/ubluepy_descriptor.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/ubluepy_peripheral.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/ubluepy_scan_entry.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/ubluepy_scanner.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/ubluepy_service.c (100%) rename {nrf => ports/nrf}/modules/ubluepy/ubluepy_uuid.c (100%) rename {nrf => ports/nrf}/modules/uos/moduos.c (100%) rename {nrf => ports/nrf}/modules/utime/modutime.c (100%) rename {nrf => ports/nrf}/mpconfigport.h (100%) rename {nrf => ports/nrf}/mphalport.c (100%) rename {nrf => ports/nrf}/mphalport.h (100%) rename {nrf => ports/nrf}/nrf51_af.csv (100%) rename {nrf => ports/nrf}/nrf52_af.csv (100%) rename {nrf => ports/nrf}/pin_defs_nrf5.h (100%) rename {nrf => ports/nrf}/pin_named_pins.c (100%) rename {nrf => ports/nrf}/qstrdefsport.h (100%) diff --git a/nrf/.gitignore b/ports/nrf/.gitignore similarity index 100% rename from nrf/.gitignore rename to ports/nrf/.gitignore diff --git a/nrf/Makefile b/ports/nrf/Makefile similarity index 100% rename from nrf/Makefile rename to ports/nrf/Makefile diff --git a/nrf/README.md b/ports/nrf/README.md similarity index 100% rename from nrf/README.md rename to ports/nrf/README.md diff --git a/nrf/bluetooth_conf.h b/ports/nrf/bluetooth_conf.h similarity index 100% rename from nrf/bluetooth_conf.h rename to ports/nrf/bluetooth_conf.h diff --git a/nrf/boards/arduino_primo/mpconfigboard.h b/ports/nrf/boards/arduino_primo/mpconfigboard.h similarity index 100% rename from nrf/boards/arduino_primo/mpconfigboard.h rename to ports/nrf/boards/arduino_primo/mpconfigboard.h diff --git a/nrf/boards/arduino_primo/mpconfigboard.mk b/ports/nrf/boards/arduino_primo/mpconfigboard.mk similarity index 100% rename from nrf/boards/arduino_primo/mpconfigboard.mk rename to ports/nrf/boards/arduino_primo/mpconfigboard.mk diff --git a/nrf/boards/arduino_primo/mpconfigboard_s132.mk b/ports/nrf/boards/arduino_primo/mpconfigboard_s132.mk similarity index 100% rename from nrf/boards/arduino_primo/mpconfigboard_s132.mk rename to ports/nrf/boards/arduino_primo/mpconfigboard_s132.mk diff --git a/nrf/boards/arduino_primo/nrf52_hal_conf.h b/ports/nrf/boards/arduino_primo/nrf52_hal_conf.h similarity index 100% rename from nrf/boards/arduino_primo/nrf52_hal_conf.h rename to ports/nrf/boards/arduino_primo/nrf52_hal_conf.h diff --git a/nrf/boards/arduino_primo/pins.csv b/ports/nrf/boards/arduino_primo/pins.csv similarity index 100% rename from nrf/boards/arduino_primo/pins.csv rename to ports/nrf/boards/arduino_primo/pins.csv diff --git a/nrf/boards/common.ld b/ports/nrf/boards/common.ld similarity index 100% rename from nrf/boards/common.ld rename to ports/nrf/boards/common.ld diff --git a/nrf/boards/dvk_bl652/mpconfigboard.h b/ports/nrf/boards/dvk_bl652/mpconfigboard.h similarity index 100% rename from nrf/boards/dvk_bl652/mpconfigboard.h rename to ports/nrf/boards/dvk_bl652/mpconfigboard.h diff --git a/nrf/boards/dvk_bl652/mpconfigboard.mk b/ports/nrf/boards/dvk_bl652/mpconfigboard.mk similarity index 100% rename from nrf/boards/dvk_bl652/mpconfigboard.mk rename to ports/nrf/boards/dvk_bl652/mpconfigboard.mk diff --git a/nrf/boards/dvk_bl652/mpconfigboard_s132.mk b/ports/nrf/boards/dvk_bl652/mpconfigboard_s132.mk similarity index 100% rename from nrf/boards/dvk_bl652/mpconfigboard_s132.mk rename to ports/nrf/boards/dvk_bl652/mpconfigboard_s132.mk diff --git a/nrf/boards/dvk_bl652/nrf52_hal_conf.h b/ports/nrf/boards/dvk_bl652/nrf52_hal_conf.h similarity index 100% rename from nrf/boards/dvk_bl652/nrf52_hal_conf.h rename to ports/nrf/boards/dvk_bl652/nrf52_hal_conf.h diff --git a/nrf/boards/dvk_bl652/pins.csv b/ports/nrf/boards/dvk_bl652/pins.csv similarity index 100% rename from nrf/boards/dvk_bl652/pins.csv rename to ports/nrf/boards/dvk_bl652/pins.csv diff --git a/nrf/boards/feather52/custom_nrf52832_dfu_app.ld b/ports/nrf/boards/feather52/custom_nrf52832_dfu_app.ld similarity index 100% rename from nrf/boards/feather52/custom_nrf52832_dfu_app.ld rename to ports/nrf/boards/feather52/custom_nrf52832_dfu_app.ld diff --git a/nrf/boards/feather52/mpconfigboard.h b/ports/nrf/boards/feather52/mpconfigboard.h similarity index 100% rename from nrf/boards/feather52/mpconfigboard.h rename to ports/nrf/boards/feather52/mpconfigboard.h diff --git a/nrf/boards/feather52/mpconfigboard.mk b/ports/nrf/boards/feather52/mpconfigboard.mk similarity index 100% rename from nrf/boards/feather52/mpconfigboard.mk rename to ports/nrf/boards/feather52/mpconfigboard.mk diff --git a/nrf/boards/feather52/mpconfigboard_s132.mk b/ports/nrf/boards/feather52/mpconfigboard_s132.mk similarity index 100% rename from nrf/boards/feather52/mpconfigboard_s132.mk rename to ports/nrf/boards/feather52/mpconfigboard_s132.mk diff --git a/nrf/boards/feather52/nrf52_hal_conf.h b/ports/nrf/boards/feather52/nrf52_hal_conf.h similarity index 100% rename from nrf/boards/feather52/nrf52_hal_conf.h rename to ports/nrf/boards/feather52/nrf52_hal_conf.h diff --git a/nrf/boards/feather52/pins.csv b/ports/nrf/boards/feather52/pins.csv similarity index 100% rename from nrf/boards/feather52/pins.csv rename to ports/nrf/boards/feather52/pins.csv diff --git a/nrf/boards/make-pins.py b/ports/nrf/boards/make-pins.py similarity index 100% rename from nrf/boards/make-pins.py rename to ports/nrf/boards/make-pins.py diff --git a/nrf/boards/microbit/mpconfigboard.h b/ports/nrf/boards/microbit/mpconfigboard.h similarity index 100% rename from nrf/boards/microbit/mpconfigboard.h rename to ports/nrf/boards/microbit/mpconfigboard.h diff --git a/nrf/boards/microbit/mpconfigboard.mk b/ports/nrf/boards/microbit/mpconfigboard.mk similarity index 100% rename from nrf/boards/microbit/mpconfigboard.mk rename to ports/nrf/boards/microbit/mpconfigboard.mk diff --git a/nrf/boards/microbit/mpconfigboard_s110.mk b/ports/nrf/boards/microbit/mpconfigboard_s110.mk similarity index 100% rename from nrf/boards/microbit/mpconfigboard_s110.mk rename to ports/nrf/boards/microbit/mpconfigboard_s110.mk diff --git a/nrf/boards/microbit/nrf51_hal_conf.h b/ports/nrf/boards/microbit/nrf51_hal_conf.h similarity index 100% rename from nrf/boards/microbit/nrf51_hal_conf.h rename to ports/nrf/boards/microbit/nrf51_hal_conf.h diff --git a/nrf/boards/microbit/pins.csv b/ports/nrf/boards/microbit/pins.csv similarity index 100% rename from nrf/boards/microbit/pins.csv rename to ports/nrf/boards/microbit/pins.csv diff --git a/nrf/boards/nrf51_prefix.c b/ports/nrf/boards/nrf51_prefix.c similarity index 100% rename from nrf/boards/nrf51_prefix.c rename to ports/nrf/boards/nrf51_prefix.c diff --git a/nrf/boards/nrf51x22_256k_16k.ld b/ports/nrf/boards/nrf51x22_256k_16k.ld similarity index 100% rename from nrf/boards/nrf51x22_256k_16k.ld rename to ports/nrf/boards/nrf51x22_256k_16k.ld diff --git a/nrf/boards/nrf51x22_256k_16k_s110_8.0.0.ld b/ports/nrf/boards/nrf51x22_256k_16k_s110_8.0.0.ld similarity index 100% rename from nrf/boards/nrf51x22_256k_16k_s110_8.0.0.ld rename to ports/nrf/boards/nrf51x22_256k_16k_s110_8.0.0.ld diff --git a/nrf/boards/nrf51x22_256k_32k.ld b/ports/nrf/boards/nrf51x22_256k_32k.ld similarity index 100% rename from nrf/boards/nrf51x22_256k_32k.ld rename to ports/nrf/boards/nrf51x22_256k_32k.ld diff --git a/nrf/boards/nrf51x22_256k_32k_s110_8.0.0.ld b/ports/nrf/boards/nrf51x22_256k_32k_s110_8.0.0.ld similarity index 100% rename from nrf/boards/nrf51x22_256k_32k_s110_8.0.0.ld rename to ports/nrf/boards/nrf51x22_256k_32k_s110_8.0.0.ld diff --git a/nrf/boards/nrf51x22_256k_32k_s120_2.1.0.ld b/ports/nrf/boards/nrf51x22_256k_32k_s120_2.1.0.ld similarity index 100% rename from nrf/boards/nrf51x22_256k_32k_s120_2.1.0.ld rename to ports/nrf/boards/nrf51x22_256k_32k_s120_2.1.0.ld diff --git a/nrf/boards/nrf51x22_256k_32k_s130_2.0.1.ld b/ports/nrf/boards/nrf51x22_256k_32k_s130_2.0.1.ld similarity index 100% rename from nrf/boards/nrf51x22_256k_32k_s130_2.0.1.ld rename to ports/nrf/boards/nrf51x22_256k_32k_s130_2.0.1.ld diff --git a/nrf/boards/nrf52832_512k_64k.ld b/ports/nrf/boards/nrf52832_512k_64k.ld similarity index 100% rename from nrf/boards/nrf52832_512k_64k.ld rename to ports/nrf/boards/nrf52832_512k_64k.ld diff --git a/nrf/boards/nrf52832_512k_64k_s132_2.0.1.ld b/ports/nrf/boards/nrf52832_512k_64k_s132_2.0.1.ld similarity index 100% rename from nrf/boards/nrf52832_512k_64k_s132_2.0.1.ld rename to ports/nrf/boards/nrf52832_512k_64k_s132_2.0.1.ld diff --git a/nrf/boards/nrf52832_512k_64k_s132_3.0.0.ld b/ports/nrf/boards/nrf52832_512k_64k_s132_3.0.0.ld similarity index 100% rename from nrf/boards/nrf52832_512k_64k_s132_3.0.0.ld rename to ports/nrf/boards/nrf52832_512k_64k_s132_3.0.0.ld diff --git a/nrf/boards/nrf52840_1M_256k.ld b/ports/nrf/boards/nrf52840_1M_256k.ld similarity index 100% rename from nrf/boards/nrf52840_1M_256k.ld rename to ports/nrf/boards/nrf52840_1M_256k.ld diff --git a/nrf/boards/nrf52_prefix.c b/ports/nrf/boards/nrf52_prefix.c similarity index 100% rename from nrf/boards/nrf52_prefix.c rename to ports/nrf/boards/nrf52_prefix.c diff --git a/nrf/boards/pca10000/mpconfigboard.h b/ports/nrf/boards/pca10000/mpconfigboard.h similarity index 100% rename from nrf/boards/pca10000/mpconfigboard.h rename to ports/nrf/boards/pca10000/mpconfigboard.h diff --git a/nrf/boards/pca10000/mpconfigboard.mk b/ports/nrf/boards/pca10000/mpconfigboard.mk similarity index 100% rename from nrf/boards/pca10000/mpconfigboard.mk rename to ports/nrf/boards/pca10000/mpconfigboard.mk diff --git a/nrf/boards/pca10000/mpconfigboard_s110.mk b/ports/nrf/boards/pca10000/mpconfigboard_s110.mk similarity index 100% rename from nrf/boards/pca10000/mpconfigboard_s110.mk rename to ports/nrf/boards/pca10000/mpconfigboard_s110.mk diff --git a/nrf/boards/pca10000/nrf51_hal_conf.h b/ports/nrf/boards/pca10000/nrf51_hal_conf.h similarity index 100% rename from nrf/boards/pca10000/nrf51_hal_conf.h rename to ports/nrf/boards/pca10000/nrf51_hal_conf.h diff --git a/nrf/boards/pca10000/pins.csv b/ports/nrf/boards/pca10000/pins.csv similarity index 100% rename from nrf/boards/pca10000/pins.csv rename to ports/nrf/boards/pca10000/pins.csv diff --git a/nrf/boards/pca10001/mpconfigboard.h b/ports/nrf/boards/pca10001/mpconfigboard.h similarity index 100% rename from nrf/boards/pca10001/mpconfigboard.h rename to ports/nrf/boards/pca10001/mpconfigboard.h diff --git a/nrf/boards/pca10001/mpconfigboard.mk b/ports/nrf/boards/pca10001/mpconfigboard.mk similarity index 100% rename from nrf/boards/pca10001/mpconfigboard.mk rename to ports/nrf/boards/pca10001/mpconfigboard.mk diff --git a/nrf/boards/pca10001/mpconfigboard_s110.mk b/ports/nrf/boards/pca10001/mpconfigboard_s110.mk similarity index 100% rename from nrf/boards/pca10001/mpconfigboard_s110.mk rename to ports/nrf/boards/pca10001/mpconfigboard_s110.mk diff --git a/nrf/boards/pca10001/nrf51_hal_conf.h b/ports/nrf/boards/pca10001/nrf51_hal_conf.h similarity index 100% rename from nrf/boards/pca10001/nrf51_hal_conf.h rename to ports/nrf/boards/pca10001/nrf51_hal_conf.h diff --git a/nrf/boards/pca10001/pins.csv b/ports/nrf/boards/pca10001/pins.csv similarity index 100% rename from nrf/boards/pca10001/pins.csv rename to ports/nrf/boards/pca10001/pins.csv diff --git a/nrf/boards/pca10028/mpconfigboard.h b/ports/nrf/boards/pca10028/mpconfigboard.h similarity index 100% rename from nrf/boards/pca10028/mpconfigboard.h rename to ports/nrf/boards/pca10028/mpconfigboard.h diff --git a/nrf/boards/pca10028/mpconfigboard.mk b/ports/nrf/boards/pca10028/mpconfigboard.mk similarity index 100% rename from nrf/boards/pca10028/mpconfigboard.mk rename to ports/nrf/boards/pca10028/mpconfigboard.mk diff --git a/nrf/boards/pca10028/mpconfigboard_s110.mk b/ports/nrf/boards/pca10028/mpconfigboard_s110.mk similarity index 100% rename from nrf/boards/pca10028/mpconfigboard_s110.mk rename to ports/nrf/boards/pca10028/mpconfigboard_s110.mk diff --git a/nrf/boards/pca10028/mpconfigboard_s120.mk b/ports/nrf/boards/pca10028/mpconfigboard_s120.mk similarity index 100% rename from nrf/boards/pca10028/mpconfigboard_s120.mk rename to ports/nrf/boards/pca10028/mpconfigboard_s120.mk diff --git a/nrf/boards/pca10028/mpconfigboard_s130.mk b/ports/nrf/boards/pca10028/mpconfigboard_s130.mk similarity index 100% rename from nrf/boards/pca10028/mpconfigboard_s130.mk rename to ports/nrf/boards/pca10028/mpconfigboard_s130.mk diff --git a/nrf/boards/pca10028/nrf51_hal_conf.h b/ports/nrf/boards/pca10028/nrf51_hal_conf.h similarity index 100% rename from nrf/boards/pca10028/nrf51_hal_conf.h rename to ports/nrf/boards/pca10028/nrf51_hal_conf.h diff --git a/nrf/boards/pca10028/pins.csv b/ports/nrf/boards/pca10028/pins.csv similarity index 100% rename from nrf/boards/pca10028/pins.csv rename to ports/nrf/boards/pca10028/pins.csv diff --git a/nrf/boards/pca10031/mpconfigboard.h b/ports/nrf/boards/pca10031/mpconfigboard.h similarity index 100% rename from nrf/boards/pca10031/mpconfigboard.h rename to ports/nrf/boards/pca10031/mpconfigboard.h diff --git a/nrf/boards/pca10031/mpconfigboard.mk b/ports/nrf/boards/pca10031/mpconfigboard.mk similarity index 100% rename from nrf/boards/pca10031/mpconfigboard.mk rename to ports/nrf/boards/pca10031/mpconfigboard.mk diff --git a/nrf/boards/pca10031/mpconfigboard_s110.mk b/ports/nrf/boards/pca10031/mpconfigboard_s110.mk similarity index 100% rename from nrf/boards/pca10031/mpconfigboard_s110.mk rename to ports/nrf/boards/pca10031/mpconfigboard_s110.mk diff --git a/nrf/boards/pca10031/mpconfigboard_s120.mk b/ports/nrf/boards/pca10031/mpconfigboard_s120.mk similarity index 100% rename from nrf/boards/pca10031/mpconfigboard_s120.mk rename to ports/nrf/boards/pca10031/mpconfigboard_s120.mk diff --git a/nrf/boards/pca10031/mpconfigboard_s130.mk b/ports/nrf/boards/pca10031/mpconfigboard_s130.mk similarity index 100% rename from nrf/boards/pca10031/mpconfigboard_s130.mk rename to ports/nrf/boards/pca10031/mpconfigboard_s130.mk diff --git a/nrf/boards/pca10031/nrf51_hal_conf.h b/ports/nrf/boards/pca10031/nrf51_hal_conf.h similarity index 100% rename from nrf/boards/pca10031/nrf51_hal_conf.h rename to ports/nrf/boards/pca10031/nrf51_hal_conf.h diff --git a/nrf/boards/pca10031/pins.csv b/ports/nrf/boards/pca10031/pins.csv similarity index 100% rename from nrf/boards/pca10031/pins.csv rename to ports/nrf/boards/pca10031/pins.csv diff --git a/nrf/boards/pca10040/mpconfigboard.h b/ports/nrf/boards/pca10040/mpconfigboard.h similarity index 100% rename from nrf/boards/pca10040/mpconfigboard.h rename to ports/nrf/boards/pca10040/mpconfigboard.h diff --git a/nrf/boards/pca10040/mpconfigboard.mk b/ports/nrf/boards/pca10040/mpconfigboard.mk similarity index 100% rename from nrf/boards/pca10040/mpconfigboard.mk rename to ports/nrf/boards/pca10040/mpconfigboard.mk diff --git a/nrf/boards/pca10040/mpconfigboard_s132.mk b/ports/nrf/boards/pca10040/mpconfigboard_s132.mk similarity index 100% rename from nrf/boards/pca10040/mpconfigboard_s132.mk rename to ports/nrf/boards/pca10040/mpconfigboard_s132.mk diff --git a/nrf/boards/pca10040/nrf52_hal_conf.h b/ports/nrf/boards/pca10040/nrf52_hal_conf.h similarity index 100% rename from nrf/boards/pca10040/nrf52_hal_conf.h rename to ports/nrf/boards/pca10040/nrf52_hal_conf.h diff --git a/nrf/boards/pca10040/pins.csv b/ports/nrf/boards/pca10040/pins.csv similarity index 100% rename from nrf/boards/pca10040/pins.csv rename to ports/nrf/boards/pca10040/pins.csv diff --git a/nrf/boards/pca10056/mpconfigboard.h b/ports/nrf/boards/pca10056/mpconfigboard.h similarity index 100% rename from nrf/boards/pca10056/mpconfigboard.h rename to ports/nrf/boards/pca10056/mpconfigboard.h diff --git a/nrf/boards/pca10056/mpconfigboard.mk b/ports/nrf/boards/pca10056/mpconfigboard.mk similarity index 100% rename from nrf/boards/pca10056/mpconfigboard.mk rename to ports/nrf/boards/pca10056/mpconfigboard.mk diff --git a/nrf/boards/pca10056/nrf52_hal_conf.h b/ports/nrf/boards/pca10056/nrf52_hal_conf.h similarity index 100% rename from nrf/boards/pca10056/nrf52_hal_conf.h rename to ports/nrf/boards/pca10056/nrf52_hal_conf.h diff --git a/nrf/boards/pca10056/pins.csv b/ports/nrf/boards/pca10056/pins.csv similarity index 100% rename from nrf/boards/pca10056/pins.csv rename to ports/nrf/boards/pca10056/pins.csv diff --git a/nrf/builtin_open.c b/ports/nrf/builtin_open.c similarity index 100% rename from nrf/builtin_open.c rename to ports/nrf/builtin_open.c diff --git a/nrf/device/compiler_abstraction.h b/ports/nrf/device/compiler_abstraction.h similarity index 100% rename from nrf/device/compiler_abstraction.h rename to ports/nrf/device/compiler_abstraction.h diff --git a/nrf/device/nrf.h b/ports/nrf/device/nrf.h similarity index 100% rename from nrf/device/nrf.h rename to ports/nrf/device/nrf.h diff --git a/nrf/device/nrf51/nrf51.h b/ports/nrf/device/nrf51/nrf51.h similarity index 100% rename from nrf/device/nrf51/nrf51.h rename to ports/nrf/device/nrf51/nrf51.h diff --git a/nrf/device/nrf51/nrf51_bitfields.h b/ports/nrf/device/nrf51/nrf51_bitfields.h similarity index 100% rename from nrf/device/nrf51/nrf51_bitfields.h rename to ports/nrf/device/nrf51/nrf51_bitfields.h diff --git a/nrf/device/nrf51/nrf51_deprecated.h b/ports/nrf/device/nrf51/nrf51_deprecated.h similarity index 100% rename from nrf/device/nrf51/nrf51_deprecated.h rename to ports/nrf/device/nrf51/nrf51_deprecated.h diff --git a/nrf/device/nrf51/startup_nrf51822.c b/ports/nrf/device/nrf51/startup_nrf51822.c similarity index 100% rename from nrf/device/nrf51/startup_nrf51822.c rename to ports/nrf/device/nrf51/startup_nrf51822.c diff --git a/nrf/device/nrf51/system_nrf51.h b/ports/nrf/device/nrf51/system_nrf51.h similarity index 100% rename from nrf/device/nrf51/system_nrf51.h rename to ports/nrf/device/nrf51/system_nrf51.h diff --git a/nrf/device/nrf51/system_nrf51822.c b/ports/nrf/device/nrf51/system_nrf51822.c similarity index 100% rename from nrf/device/nrf51/system_nrf51822.c rename to ports/nrf/device/nrf51/system_nrf51822.c diff --git a/nrf/device/nrf52/nrf51_to_nrf52.h b/ports/nrf/device/nrf52/nrf51_to_nrf52.h similarity index 100% rename from nrf/device/nrf52/nrf51_to_nrf52.h rename to ports/nrf/device/nrf52/nrf51_to_nrf52.h diff --git a/nrf/device/nrf52/nrf51_to_nrf52840.h b/ports/nrf/device/nrf52/nrf51_to_nrf52840.h similarity index 100% rename from nrf/device/nrf52/nrf51_to_nrf52840.h rename to ports/nrf/device/nrf52/nrf51_to_nrf52840.h diff --git a/nrf/device/nrf52/nrf52.h b/ports/nrf/device/nrf52/nrf52.h similarity index 100% rename from nrf/device/nrf52/nrf52.h rename to ports/nrf/device/nrf52/nrf52.h diff --git a/nrf/device/nrf52/nrf52840.h b/ports/nrf/device/nrf52/nrf52840.h similarity index 100% rename from nrf/device/nrf52/nrf52840.h rename to ports/nrf/device/nrf52/nrf52840.h diff --git a/nrf/device/nrf52/nrf52840_bitfields.h b/ports/nrf/device/nrf52/nrf52840_bitfields.h similarity index 100% rename from nrf/device/nrf52/nrf52840_bitfields.h rename to ports/nrf/device/nrf52/nrf52840_bitfields.h diff --git a/nrf/device/nrf52/nrf52_bitfields.h b/ports/nrf/device/nrf52/nrf52_bitfields.h similarity index 100% rename from nrf/device/nrf52/nrf52_bitfields.h rename to ports/nrf/device/nrf52/nrf52_bitfields.h diff --git a/nrf/device/nrf52/nrf52_name_change.h b/ports/nrf/device/nrf52/nrf52_name_change.h similarity index 100% rename from nrf/device/nrf52/nrf52_name_change.h rename to ports/nrf/device/nrf52/nrf52_name_change.h diff --git a/nrf/device/nrf52/nrf52_to_nrf52840.h b/ports/nrf/device/nrf52/nrf52_to_nrf52840.h similarity index 100% rename from nrf/device/nrf52/nrf52_to_nrf52840.h rename to ports/nrf/device/nrf52/nrf52_to_nrf52840.h diff --git a/nrf/device/nrf52/startup_nrf52832.c b/ports/nrf/device/nrf52/startup_nrf52832.c similarity index 100% rename from nrf/device/nrf52/startup_nrf52832.c rename to ports/nrf/device/nrf52/startup_nrf52832.c diff --git a/nrf/device/nrf52/startup_nrf52840.c b/ports/nrf/device/nrf52/startup_nrf52840.c similarity index 100% rename from nrf/device/nrf52/startup_nrf52840.c rename to ports/nrf/device/nrf52/startup_nrf52840.c diff --git a/nrf/device/nrf52/system_nrf52.h b/ports/nrf/device/nrf52/system_nrf52.h similarity index 100% rename from nrf/device/nrf52/system_nrf52.h rename to ports/nrf/device/nrf52/system_nrf52.h diff --git a/nrf/device/nrf52/system_nrf52832.c b/ports/nrf/device/nrf52/system_nrf52832.c similarity index 100% rename from nrf/device/nrf52/system_nrf52832.c rename to ports/nrf/device/nrf52/system_nrf52832.c diff --git a/nrf/device/nrf52/system_nrf52840.c b/ports/nrf/device/nrf52/system_nrf52840.c similarity index 100% rename from nrf/device/nrf52/system_nrf52840.c rename to ports/nrf/device/nrf52/system_nrf52840.c diff --git a/nrf/device/nrf52/system_nrf52840.h b/ports/nrf/device/nrf52/system_nrf52840.h similarity index 100% rename from nrf/device/nrf52/system_nrf52840.h rename to ports/nrf/device/nrf52/system_nrf52840.h diff --git a/nrf/drivers/bluetooth/ble_drv.c b/ports/nrf/drivers/bluetooth/ble_drv.c similarity index 100% rename from nrf/drivers/bluetooth/ble_drv.c rename to ports/nrf/drivers/bluetooth/ble_drv.c diff --git a/nrf/drivers/bluetooth/ble_drv.h b/ports/nrf/drivers/bluetooth/ble_drv.h similarity index 100% rename from nrf/drivers/bluetooth/ble_drv.h rename to ports/nrf/drivers/bluetooth/ble_drv.h diff --git a/nrf/drivers/bluetooth/ble_uart.c b/ports/nrf/drivers/bluetooth/ble_uart.c similarity index 100% rename from nrf/drivers/bluetooth/ble_uart.c rename to ports/nrf/drivers/bluetooth/ble_uart.c diff --git a/nrf/drivers/bluetooth/ble_uart.h b/ports/nrf/drivers/bluetooth/ble_uart.h similarity index 100% rename from nrf/drivers/bluetooth/ble_uart.h rename to ports/nrf/drivers/bluetooth/ble_uart.h diff --git a/nrf/drivers/bluetooth/bluetooth_common.mk b/ports/nrf/drivers/bluetooth/bluetooth_common.mk similarity index 100% rename from nrf/drivers/bluetooth/bluetooth_common.mk rename to ports/nrf/drivers/bluetooth/bluetooth_common.mk diff --git a/nrf/drivers/bluetooth/download_ble_stack.sh b/ports/nrf/drivers/bluetooth/download_ble_stack.sh similarity index 100% rename from nrf/drivers/bluetooth/download_ble_stack.sh rename to ports/nrf/drivers/bluetooth/download_ble_stack.sh diff --git a/nrf/drivers/bluetooth/ringbuffer.h b/ports/nrf/drivers/bluetooth/ringbuffer.h similarity index 100% rename from nrf/drivers/bluetooth/ringbuffer.h rename to ports/nrf/drivers/bluetooth/ringbuffer.h diff --git a/nrf/drivers/softpwm.c b/ports/nrf/drivers/softpwm.c similarity index 100% rename from nrf/drivers/softpwm.c rename to ports/nrf/drivers/softpwm.c diff --git a/nrf/drivers/softpwm.h b/ports/nrf/drivers/softpwm.h similarity index 100% rename from nrf/drivers/softpwm.h rename to ports/nrf/drivers/softpwm.h diff --git a/nrf/drivers/ticker.c b/ports/nrf/drivers/ticker.c similarity index 100% rename from nrf/drivers/ticker.c rename to ports/nrf/drivers/ticker.c diff --git a/nrf/drivers/ticker.h b/ports/nrf/drivers/ticker.h similarity index 100% rename from nrf/drivers/ticker.h rename to ports/nrf/drivers/ticker.h diff --git a/nrf/examples/mountsd.py b/ports/nrf/examples/mountsd.py similarity index 100% rename from nrf/examples/mountsd.py rename to ports/nrf/examples/mountsd.py diff --git a/nrf/examples/musictest.py b/ports/nrf/examples/musictest.py similarity index 100% rename from nrf/examples/musictest.py rename to ports/nrf/examples/musictest.py diff --git a/nrf/examples/nrf52_pwm.py b/ports/nrf/examples/nrf52_pwm.py similarity index 100% rename from nrf/examples/nrf52_pwm.py rename to ports/nrf/examples/nrf52_pwm.py diff --git a/nrf/examples/nrf52_servo.py b/ports/nrf/examples/nrf52_servo.py similarity index 100% rename from nrf/examples/nrf52_servo.py rename to ports/nrf/examples/nrf52_servo.py diff --git a/nrf/examples/powerup.py b/ports/nrf/examples/powerup.py similarity index 100% rename from nrf/examples/powerup.py rename to ports/nrf/examples/powerup.py diff --git a/nrf/examples/seeed_tft.py b/ports/nrf/examples/seeed_tft.py similarity index 100% rename from nrf/examples/seeed_tft.py rename to ports/nrf/examples/seeed_tft.py diff --git a/nrf/examples/ssd1306_mod.py b/ports/nrf/examples/ssd1306_mod.py similarity index 100% rename from nrf/examples/ssd1306_mod.py rename to ports/nrf/examples/ssd1306_mod.py diff --git a/nrf/examples/ubluepy_eddystone.py b/ports/nrf/examples/ubluepy_eddystone.py similarity index 100% rename from nrf/examples/ubluepy_eddystone.py rename to ports/nrf/examples/ubluepy_eddystone.py diff --git a/nrf/examples/ubluepy_scan.py b/ports/nrf/examples/ubluepy_scan.py similarity index 100% rename from nrf/examples/ubluepy_scan.py rename to ports/nrf/examples/ubluepy_scan.py diff --git a/nrf/examples/ubluepy_temp.py b/ports/nrf/examples/ubluepy_temp.py similarity index 100% rename from nrf/examples/ubluepy_temp.py rename to ports/nrf/examples/ubluepy_temp.py diff --git a/nrf/fatfs_port.c b/ports/nrf/fatfs_port.c similarity index 100% rename from nrf/fatfs_port.c rename to ports/nrf/fatfs_port.c diff --git a/nrf/freeze/test.py b/ports/nrf/freeze/test.py similarity index 100% rename from nrf/freeze/test.py rename to ports/nrf/freeze/test.py diff --git a/nrf/gccollect.c b/ports/nrf/gccollect.c similarity index 100% rename from nrf/gccollect.c rename to ports/nrf/gccollect.c diff --git a/nrf/gccollect.h b/ports/nrf/gccollect.h similarity index 100% rename from nrf/gccollect.h rename to ports/nrf/gccollect.h diff --git a/nrf/hal/hal_adc.c b/ports/nrf/hal/hal_adc.c similarity index 100% rename from nrf/hal/hal_adc.c rename to ports/nrf/hal/hal_adc.c diff --git a/nrf/hal/hal_adc.h b/ports/nrf/hal/hal_adc.h similarity index 100% rename from nrf/hal/hal_adc.h rename to ports/nrf/hal/hal_adc.h diff --git a/nrf/hal/hal_adce.c b/ports/nrf/hal/hal_adce.c similarity index 100% rename from nrf/hal/hal_adce.c rename to ports/nrf/hal/hal_adce.c diff --git a/nrf/hal/hal_gpio.c b/ports/nrf/hal/hal_gpio.c similarity index 100% rename from nrf/hal/hal_gpio.c rename to ports/nrf/hal/hal_gpio.c diff --git a/nrf/hal/hal_gpio.h b/ports/nrf/hal/hal_gpio.h similarity index 100% rename from nrf/hal/hal_gpio.h rename to ports/nrf/hal/hal_gpio.h diff --git a/nrf/hal/hal_irq.h b/ports/nrf/hal/hal_irq.h similarity index 100% rename from nrf/hal/hal_irq.h rename to ports/nrf/hal/hal_irq.h diff --git a/nrf/hal/hal_pwm.c b/ports/nrf/hal/hal_pwm.c similarity index 100% rename from nrf/hal/hal_pwm.c rename to ports/nrf/hal/hal_pwm.c diff --git a/nrf/hal/hal_pwm.h b/ports/nrf/hal/hal_pwm.h similarity index 100% rename from nrf/hal/hal_pwm.h rename to ports/nrf/hal/hal_pwm.h diff --git a/nrf/hal/hal_qspie.c b/ports/nrf/hal/hal_qspie.c similarity index 100% rename from nrf/hal/hal_qspie.c rename to ports/nrf/hal/hal_qspie.c diff --git a/nrf/hal/hal_qspie.h b/ports/nrf/hal/hal_qspie.h similarity index 100% rename from nrf/hal/hal_qspie.h rename to ports/nrf/hal/hal_qspie.h diff --git a/nrf/hal/hal_rng.c b/ports/nrf/hal/hal_rng.c similarity index 100% rename from nrf/hal/hal_rng.c rename to ports/nrf/hal/hal_rng.c diff --git a/nrf/hal/hal_rng.h b/ports/nrf/hal/hal_rng.h similarity index 100% rename from nrf/hal/hal_rng.h rename to ports/nrf/hal/hal_rng.h diff --git a/nrf/hal/hal_rtc.c b/ports/nrf/hal/hal_rtc.c similarity index 100% rename from nrf/hal/hal_rtc.c rename to ports/nrf/hal/hal_rtc.c diff --git a/nrf/hal/hal_rtc.h b/ports/nrf/hal/hal_rtc.h similarity index 100% rename from nrf/hal/hal_rtc.h rename to ports/nrf/hal/hal_rtc.h diff --git a/nrf/hal/hal_spi.c b/ports/nrf/hal/hal_spi.c similarity index 100% rename from nrf/hal/hal_spi.c rename to ports/nrf/hal/hal_spi.c diff --git a/nrf/hal/hal_spi.h b/ports/nrf/hal/hal_spi.h similarity index 100% rename from nrf/hal/hal_spi.h rename to ports/nrf/hal/hal_spi.h diff --git a/nrf/hal/hal_spie.c b/ports/nrf/hal/hal_spie.c similarity index 100% rename from nrf/hal/hal_spie.c rename to ports/nrf/hal/hal_spie.c diff --git a/nrf/hal/hal_temp.c b/ports/nrf/hal/hal_temp.c similarity index 100% rename from nrf/hal/hal_temp.c rename to ports/nrf/hal/hal_temp.c diff --git a/nrf/hal/hal_temp.h b/ports/nrf/hal/hal_temp.h similarity index 100% rename from nrf/hal/hal_temp.h rename to ports/nrf/hal/hal_temp.h diff --git a/nrf/hal/hal_time.c b/ports/nrf/hal/hal_time.c similarity index 100% rename from nrf/hal/hal_time.c rename to ports/nrf/hal/hal_time.c diff --git a/nrf/hal/hal_time.h b/ports/nrf/hal/hal_time.h similarity index 100% rename from nrf/hal/hal_time.h rename to ports/nrf/hal/hal_time.h diff --git a/nrf/hal/hal_timer.c b/ports/nrf/hal/hal_timer.c similarity index 100% rename from nrf/hal/hal_timer.c rename to ports/nrf/hal/hal_timer.c diff --git a/nrf/hal/hal_timer.h b/ports/nrf/hal/hal_timer.h similarity index 100% rename from nrf/hal/hal_timer.h rename to ports/nrf/hal/hal_timer.h diff --git a/nrf/hal/hal_twi.c b/ports/nrf/hal/hal_twi.c similarity index 100% rename from nrf/hal/hal_twi.c rename to ports/nrf/hal/hal_twi.c diff --git a/nrf/hal/hal_twi.h b/ports/nrf/hal/hal_twi.h similarity index 100% rename from nrf/hal/hal_twi.h rename to ports/nrf/hal/hal_twi.h diff --git a/nrf/hal/hal_twie.c b/ports/nrf/hal/hal_twie.c similarity index 100% rename from nrf/hal/hal_twie.c rename to ports/nrf/hal/hal_twie.c diff --git a/nrf/hal/hal_uart.c b/ports/nrf/hal/hal_uart.c similarity index 100% rename from nrf/hal/hal_uart.c rename to ports/nrf/hal/hal_uart.c diff --git a/nrf/hal/hal_uart.h b/ports/nrf/hal/hal_uart.h similarity index 100% rename from nrf/hal/hal_uart.h rename to ports/nrf/hal/hal_uart.h diff --git a/nrf/hal/hal_uarte.c b/ports/nrf/hal/hal_uarte.c similarity index 100% rename from nrf/hal/hal_uarte.c rename to ports/nrf/hal/hal_uarte.c diff --git a/nrf/hal/nrf51_hal.h b/ports/nrf/hal/nrf51_hal.h similarity index 100% rename from nrf/hal/nrf51_hal.h rename to ports/nrf/hal/nrf51_hal.h diff --git a/nrf/hal/nrf52_hal.h b/ports/nrf/hal/nrf52_hal.h similarity index 100% rename from nrf/hal/nrf52_hal.h rename to ports/nrf/hal/nrf52_hal.h diff --git a/nrf/help.c b/ports/nrf/help.c similarity index 100% rename from nrf/help.c rename to ports/nrf/help.c diff --git a/nrf/main.c b/ports/nrf/main.c similarity index 100% rename from nrf/main.c rename to ports/nrf/main.c diff --git a/nrf/modules/ble/help_sd.h b/ports/nrf/modules/ble/help_sd.h similarity index 100% rename from nrf/modules/ble/help_sd.h rename to ports/nrf/modules/ble/help_sd.h diff --git a/nrf/modules/ble/modble.c b/ports/nrf/modules/ble/modble.c similarity index 100% rename from nrf/modules/ble/modble.c rename to ports/nrf/modules/ble/modble.c diff --git a/nrf/modules/machine/adc.c b/ports/nrf/modules/machine/adc.c similarity index 100% rename from nrf/modules/machine/adc.c rename to ports/nrf/modules/machine/adc.c diff --git a/nrf/modules/machine/adc.h b/ports/nrf/modules/machine/adc.h similarity index 100% rename from nrf/modules/machine/adc.h rename to ports/nrf/modules/machine/adc.h diff --git a/nrf/modules/machine/i2c.c b/ports/nrf/modules/machine/i2c.c similarity index 100% rename from nrf/modules/machine/i2c.c rename to ports/nrf/modules/machine/i2c.c diff --git a/nrf/modules/machine/i2c.h b/ports/nrf/modules/machine/i2c.h similarity index 100% rename from nrf/modules/machine/i2c.h rename to ports/nrf/modules/machine/i2c.h diff --git a/nrf/modules/machine/led.c b/ports/nrf/modules/machine/led.c similarity index 100% rename from nrf/modules/machine/led.c rename to ports/nrf/modules/machine/led.c diff --git a/nrf/modules/machine/led.h b/ports/nrf/modules/machine/led.h similarity index 100% rename from nrf/modules/machine/led.h rename to ports/nrf/modules/machine/led.h diff --git a/nrf/modules/machine/modmachine.c b/ports/nrf/modules/machine/modmachine.c similarity index 100% rename from nrf/modules/machine/modmachine.c rename to ports/nrf/modules/machine/modmachine.c diff --git a/nrf/modules/machine/modmachine.h b/ports/nrf/modules/machine/modmachine.h similarity index 100% rename from nrf/modules/machine/modmachine.h rename to ports/nrf/modules/machine/modmachine.h diff --git a/nrf/modules/machine/pin.c b/ports/nrf/modules/machine/pin.c similarity index 100% rename from nrf/modules/machine/pin.c rename to ports/nrf/modules/machine/pin.c diff --git a/nrf/modules/machine/pin.h b/ports/nrf/modules/machine/pin.h similarity index 100% rename from nrf/modules/machine/pin.h rename to ports/nrf/modules/machine/pin.h diff --git a/nrf/modules/machine/pwm.c b/ports/nrf/modules/machine/pwm.c similarity index 100% rename from nrf/modules/machine/pwm.c rename to ports/nrf/modules/machine/pwm.c diff --git a/nrf/modules/machine/pwm.h b/ports/nrf/modules/machine/pwm.h similarity index 100% rename from nrf/modules/machine/pwm.h rename to ports/nrf/modules/machine/pwm.h diff --git a/nrf/modules/machine/rtc.c b/ports/nrf/modules/machine/rtc.c similarity index 100% rename from nrf/modules/machine/rtc.c rename to ports/nrf/modules/machine/rtc.c diff --git a/nrf/modules/machine/rtc.h b/ports/nrf/modules/machine/rtc.h similarity index 100% rename from nrf/modules/machine/rtc.h rename to ports/nrf/modules/machine/rtc.h diff --git a/nrf/modules/machine/spi.c b/ports/nrf/modules/machine/spi.c similarity index 100% rename from nrf/modules/machine/spi.c rename to ports/nrf/modules/machine/spi.c diff --git a/nrf/modules/machine/spi.h b/ports/nrf/modules/machine/spi.h similarity index 100% rename from nrf/modules/machine/spi.h rename to ports/nrf/modules/machine/spi.h diff --git a/nrf/modules/machine/temp.c b/ports/nrf/modules/machine/temp.c similarity index 100% rename from nrf/modules/machine/temp.c rename to ports/nrf/modules/machine/temp.c diff --git a/nrf/modules/machine/temp.h b/ports/nrf/modules/machine/temp.h similarity index 100% rename from nrf/modules/machine/temp.h rename to ports/nrf/modules/machine/temp.h diff --git a/nrf/modules/machine/timer.c b/ports/nrf/modules/machine/timer.c similarity index 100% rename from nrf/modules/machine/timer.c rename to ports/nrf/modules/machine/timer.c diff --git a/nrf/modules/machine/timer.h b/ports/nrf/modules/machine/timer.h similarity index 100% rename from nrf/modules/machine/timer.h rename to ports/nrf/modules/machine/timer.h diff --git a/nrf/modules/machine/uart.c b/ports/nrf/modules/machine/uart.c similarity index 100% rename from nrf/modules/machine/uart.c rename to ports/nrf/modules/machine/uart.c diff --git a/nrf/modules/machine/uart.h b/ports/nrf/modules/machine/uart.h similarity index 100% rename from nrf/modules/machine/uart.h rename to ports/nrf/modules/machine/uart.h diff --git a/nrf/modules/music/modmusic.c b/ports/nrf/modules/music/modmusic.c similarity index 100% rename from nrf/modules/music/modmusic.c rename to ports/nrf/modules/music/modmusic.c diff --git a/nrf/modules/music/modmusic.h b/ports/nrf/modules/music/modmusic.h similarity index 100% rename from nrf/modules/music/modmusic.h rename to ports/nrf/modules/music/modmusic.h diff --git a/nrf/modules/music/musictunes.c b/ports/nrf/modules/music/musictunes.c similarity index 100% rename from nrf/modules/music/musictunes.c rename to ports/nrf/modules/music/musictunes.c diff --git a/nrf/modules/music/musictunes.h b/ports/nrf/modules/music/musictunes.h similarity index 100% rename from nrf/modules/music/musictunes.h rename to ports/nrf/modules/music/musictunes.h diff --git a/nrf/modules/pyb/modpyb.c b/ports/nrf/modules/pyb/modpyb.c similarity index 100% rename from nrf/modules/pyb/modpyb.c rename to ports/nrf/modules/pyb/modpyb.c diff --git a/nrf/modules/random/modrandom.c b/ports/nrf/modules/random/modrandom.c similarity index 100% rename from nrf/modules/random/modrandom.c rename to ports/nrf/modules/random/modrandom.c diff --git a/nrf/modules/ubluepy/modubluepy.c b/ports/nrf/modules/ubluepy/modubluepy.c similarity index 100% rename from nrf/modules/ubluepy/modubluepy.c rename to ports/nrf/modules/ubluepy/modubluepy.c diff --git a/nrf/modules/ubluepy/modubluepy.h b/ports/nrf/modules/ubluepy/modubluepy.h similarity index 100% rename from nrf/modules/ubluepy/modubluepy.h rename to ports/nrf/modules/ubluepy/modubluepy.h diff --git a/nrf/modules/ubluepy/ubluepy_characteristic.c b/ports/nrf/modules/ubluepy/ubluepy_characteristic.c similarity index 100% rename from nrf/modules/ubluepy/ubluepy_characteristic.c rename to ports/nrf/modules/ubluepy/ubluepy_characteristic.c diff --git a/nrf/modules/ubluepy/ubluepy_constants.c b/ports/nrf/modules/ubluepy/ubluepy_constants.c similarity index 100% rename from nrf/modules/ubluepy/ubluepy_constants.c rename to ports/nrf/modules/ubluepy/ubluepy_constants.c diff --git a/nrf/modules/ubluepy/ubluepy_delegate.c b/ports/nrf/modules/ubluepy/ubluepy_delegate.c similarity index 100% rename from nrf/modules/ubluepy/ubluepy_delegate.c rename to ports/nrf/modules/ubluepy/ubluepy_delegate.c diff --git a/nrf/modules/ubluepy/ubluepy_descriptor.c b/ports/nrf/modules/ubluepy/ubluepy_descriptor.c similarity index 100% rename from nrf/modules/ubluepy/ubluepy_descriptor.c rename to ports/nrf/modules/ubluepy/ubluepy_descriptor.c diff --git a/nrf/modules/ubluepy/ubluepy_peripheral.c b/ports/nrf/modules/ubluepy/ubluepy_peripheral.c similarity index 100% rename from nrf/modules/ubluepy/ubluepy_peripheral.c rename to ports/nrf/modules/ubluepy/ubluepy_peripheral.c diff --git a/nrf/modules/ubluepy/ubluepy_scan_entry.c b/ports/nrf/modules/ubluepy/ubluepy_scan_entry.c similarity index 100% rename from nrf/modules/ubluepy/ubluepy_scan_entry.c rename to ports/nrf/modules/ubluepy/ubluepy_scan_entry.c diff --git a/nrf/modules/ubluepy/ubluepy_scanner.c b/ports/nrf/modules/ubluepy/ubluepy_scanner.c similarity index 100% rename from nrf/modules/ubluepy/ubluepy_scanner.c rename to ports/nrf/modules/ubluepy/ubluepy_scanner.c diff --git a/nrf/modules/ubluepy/ubluepy_service.c b/ports/nrf/modules/ubluepy/ubluepy_service.c similarity index 100% rename from nrf/modules/ubluepy/ubluepy_service.c rename to ports/nrf/modules/ubluepy/ubluepy_service.c diff --git a/nrf/modules/ubluepy/ubluepy_uuid.c b/ports/nrf/modules/ubluepy/ubluepy_uuid.c similarity index 100% rename from nrf/modules/ubluepy/ubluepy_uuid.c rename to ports/nrf/modules/ubluepy/ubluepy_uuid.c diff --git a/nrf/modules/uos/moduos.c b/ports/nrf/modules/uos/moduos.c similarity index 100% rename from nrf/modules/uos/moduos.c rename to ports/nrf/modules/uos/moduos.c diff --git a/nrf/modules/utime/modutime.c b/ports/nrf/modules/utime/modutime.c similarity index 100% rename from nrf/modules/utime/modutime.c rename to ports/nrf/modules/utime/modutime.c diff --git a/nrf/mpconfigport.h b/ports/nrf/mpconfigport.h similarity index 100% rename from nrf/mpconfigport.h rename to ports/nrf/mpconfigport.h diff --git a/nrf/mphalport.c b/ports/nrf/mphalport.c similarity index 100% rename from nrf/mphalport.c rename to ports/nrf/mphalport.c diff --git a/nrf/mphalport.h b/ports/nrf/mphalport.h similarity index 100% rename from nrf/mphalport.h rename to ports/nrf/mphalport.h diff --git a/nrf/nrf51_af.csv b/ports/nrf/nrf51_af.csv similarity index 100% rename from nrf/nrf51_af.csv rename to ports/nrf/nrf51_af.csv diff --git a/nrf/nrf52_af.csv b/ports/nrf/nrf52_af.csv similarity index 100% rename from nrf/nrf52_af.csv rename to ports/nrf/nrf52_af.csv diff --git a/nrf/pin_defs_nrf5.h b/ports/nrf/pin_defs_nrf5.h similarity index 100% rename from nrf/pin_defs_nrf5.h rename to ports/nrf/pin_defs_nrf5.h diff --git a/nrf/pin_named_pins.c b/ports/nrf/pin_named_pins.c similarity index 100% rename from nrf/pin_named_pins.c rename to ports/nrf/pin_named_pins.c diff --git a/nrf/qstrdefsport.h b/ports/nrf/qstrdefsport.h similarity index 100% rename from nrf/qstrdefsport.h rename to ports/nrf/qstrdefsport.h From 831759faaa448d31ee5a23e57e0b65bfb77ac026 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Oct 2017 21:52:08 +0200 Subject: [PATCH 805/809] ports/nrf: Align help.c builtin help text to use correct type after upmerge with upstream master. --- ports/nrf/help.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/nrf/help.c b/ports/nrf/help.c index a2f6878d0d..5cbb0fc911 100644 --- a/ports/nrf/help.c +++ b/ports/nrf/help.c @@ -31,7 +31,7 @@ #include "help_sd.h" #endif -const char * nrf5_help_text = +const char nrf5_help_text[] = "Welcome to MicroPython!\n" "\n" "For online help please visit http://micropython.org/help/.\n" From a414199793d78136fe2614994ba07f9b3a453205 Mon Sep 17 00:00:00 2001 From: Glenn Ruben Bakke Date: Wed, 4 Oct 2017 21:54:01 +0200 Subject: [PATCH 806/809] ports/nrf: Update Makefile and README.md after moving port to new directory --- ports/nrf/Makefile | 18 +++++++++--------- ports/nrf/README.md | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/ports/nrf/Makefile b/ports/nrf/Makefile index be52b749fd..5bc36cadee 100644 --- a/ports/nrf/Makefile +++ b/ports/nrf/Makefile @@ -15,12 +15,12 @@ SD_LOWER = $(shell echo $(SD) | tr '[:upper:]' '[:lower:]') ifeq ($(SD), ) # If the build directory is not given, make it reflect the board name. BUILD ?= build-$(BOARD) - include ../py/mkenv.mk + include ../../py/mkenv.mk include boards/$(BOARD)/mpconfigboard.mk else # If the build directory is not given, make it reflect the board name. BUILD ?= build-$(BOARD)-$(SD_LOWER) - include ../py/mkenv.mk + include ../../py/mkenv.mk include boards/$(BOARD)/mpconfigboard_$(SD_LOWER).mk include drivers/bluetooth/bluetooth_common.mk @@ -32,21 +32,21 @@ QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h FROZEN_MPY_DIR = freeze # include py core make definitions -include ../py/py.mk +include ../../py/py.mk FATFS_DIR = lib/oofatfs -MPY_CROSS = ../mpy-cross/mpy-cross -MPY_TOOL = ../tools/mpy-tool.py +MPY_CROSS = ../../mpy-cross/mpy-cross +MPY_TOOL = ../../tools/mpy-tool.py CROSS_COMPILE = arm-none-eabi- MCU_VARIANT_UPPER = $(shell echo $(MCU_VARIANT) | tr '[:lower:]' '[:upper:]') INC += -I. -INC += -I.. +INC += -I../.. INC += -I$(BUILD) -INC += -I./../lib/cmsis/inc +INC += -I./../../lib/cmsis/inc INC += -I./device INC += -I./device/$(MCU_VARIANT) INC += -I./hal @@ -56,7 +56,7 @@ INC += -I./modules/ubluepy INC += -I./modules/music INC += -I./modules/random INC += -I./modules/ble -INC += -I../lib/mp-readline +INC += -I../../lib/mp-readline INC += -I./drivers/bluetooth INC += -I./drivers @@ -288,5 +288,5 @@ CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool CFLAGS += -DMICROPY_MODULE_FROZEN_MPY endif -include ../py/mkrules.mk +include ../../py/mkrules.mk diff --git a/ports/nrf/README.md b/ports/nrf/README.md index 54d95087a1..db3e2d44be 100644 --- a/ports/nrf/README.md +++ b/ports/nrf/README.md @@ -45,7 +45,7 @@ Prerequisite steps for building the nrf port: git submodule update --init make -C mpy-cross -By default, the PCA10040 (nrf52832) is used as compile target. To build and flash issue the following command inside the nrf/ folder: +By default, the PCA10040 (nrf52832) is used as compile target. To build and flash issue the following command inside the ports/nrf/ folder: make make flash From d18bf876e37e401d2e4a4221603fae0d3e311ddd Mon Sep 17 00:00:00 2001 From: Ayke van Laethem Date: Fri, 6 Oct 2017 16:52:58 +0200 Subject: [PATCH 807/809] ports/nrf: Add WT51822-S4AT board. --- ports/nrf/README.md | 2 + ports/nrf/boards/wt51822_s4at/mpconfigboard.h | 65 +++++++++++++++++++ .../nrf/boards/wt51822_s4at/mpconfigboard.mk | 4 ++ .../boards/wt51822_s4at/mpconfigboard_s110.mk | 7 ++ .../nrf/boards/wt51822_s4at/nrf51_hal_conf.h | 14 ++++ ports/nrf/boards/wt51822_s4at/pins.csv | 7 ++ 6 files changed, 99 insertions(+) create mode 100644 ports/nrf/boards/wt51822_s4at/mpconfigboard.h create mode 100644 ports/nrf/boards/wt51822_s4at/mpconfigboard.mk create mode 100644 ports/nrf/boards/wt51822_s4at/mpconfigboard_s110.mk create mode 100644 ports/nrf/boards/wt51822_s4at/nrf51_hal_conf.h create mode 100644 ports/nrf/boards/wt51822_s4at/pins.csv diff --git a/ports/nrf/README.md b/ports/nrf/README.md index db3e2d44be..d1c292e7d0 100644 --- a/ports/nrf/README.md +++ b/ports/nrf/README.md @@ -28,6 +28,7 @@ This is a port of MicroPython to the Nordic Semiconductor nRF series of chips. * PCA10001 * PCA10028 * PCA10031 (dongle) + * [WT51822-S4AT](http://www.wireless-tag.com/wireless_module/BLE/WT51822-S4AT.html) * nRF52832 * [PCA10040](http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52%2Fdita%2Fnrf52%2Fdevelopment%2Fnrf52_dev_kit.html) * [Adafruit Feather nRF52](https://www.adafruit.com/product/3406) @@ -80,6 +81,7 @@ pca10000 | s110 | Peripheral | [Segge pca10001 | s110 | Peripheral | [Segger](#segger-targets) pca10028 | s110 | Peripheral | [Segger](#segger-targets) pca10031 | s110 | Peripheral | [Segger](#segger-targets) +wt51822_s4at | s110 | Peripheral | Manual, see [datasheet](https://4tronix.co.uk/picobot2/WT51822-S4AT.pdf) for pinout pca10040 | s132 | Peripheral and Central | [Segger](#segger-targets) feather52 | s132 | Peripheral and Central | [UART DFU](#dfu-targets) arduino_primo | s132 | Peripheral and Central | [PyOCD](#pyocdopenocd-targets) diff --git a/ports/nrf/boards/wt51822_s4at/mpconfigboard.h b/ports/nrf/boards/wt51822_s4at/mpconfigboard.h new file mode 100644 index 0000000000..f8b2405885 --- /dev/null +++ b/ports/nrf/boards/wt51822_s4at/mpconfigboard.h @@ -0,0 +1,65 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Ayke van Laethem + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define WT51822_S4AT + +// Datasheet for board: +// https://4tronix.co.uk/picobot2/WT51822-S4AT.pdf +#define MICROPY_HW_BOARD_NAME "WT51822-S4AT" +#define MICROPY_HW_MCU_NAME "NRF51822" +#define MICROPY_PY_SYS_PLATFORM "nrf51" + +#define MICROPY_PY_MACHINE_HW_SPI (1) +#define MICROPY_PY_MACHINE_TIMER (1) +#define MICROPY_PY_MACHINE_RTC (1) +#define MICROPY_PY_MACHINE_I2C (1) +#define MICROPY_PY_MACHINE_ADC (1) +#define MICROPY_PY_MACHINE_TEMP (1) + +#define MICROPY_HW_HAS_LED (0) +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (0) +#define MICROPY_HW_HAS_SDCARD (0) +#define MICROPY_HW_HAS_MMA7660 (0) +#define MICROPY_HW_HAS_LIS3DSH (0) +#define MICROPY_HW_HAS_LCD (0) +#define MICROPY_HW_ENABLE_RNG (0) +#define MICROPY_HW_ENABLE_RTC (0) +#define MICROPY_HW_ENABLE_TIMER (0) +#define MICROPY_HW_ENABLE_SERVO (0) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_CAN (0) + +// UART config +#define MICROPY_HW_UART1_RX (pin_A1) +#define MICROPY_HW_UART1_TX (pin_A2) +#define MICROPY_HW_UART1_HWFC (0) + +// SPI0 config +#define MICROPY_HW_SPI0_NAME "SPI0" +#define MICROPY_HW_SPI0_SCK (pin_A9) +#define MICROPY_HW_SPI0_MOSI (pin_A10) +#define MICROPY_HW_SPI0_MISO (pin_A13) diff --git a/ports/nrf/boards/wt51822_s4at/mpconfigboard.mk b/ports/nrf/boards/wt51822_s4at/mpconfigboard.mk new file mode 100644 index 0000000000..12087d6828 --- /dev/null +++ b/ports/nrf/boards/wt51822_s4at/mpconfigboard.mk @@ -0,0 +1,4 @@ +MCU_SERIES = m0 +MCU_VARIANT = nrf51 +MCU_SUB_VARIANT = nrf51822 +LD_FILE = boards/nrf51x22_256k_16k.ld diff --git a/ports/nrf/boards/wt51822_s4at/mpconfigboard_s110.mk b/ports/nrf/boards/wt51822_s4at/mpconfigboard_s110.mk new file mode 100644 index 0000000000..8f5433b47c --- /dev/null +++ b/ports/nrf/boards/wt51822_s4at/mpconfigboard_s110.mk @@ -0,0 +1,7 @@ +MCU_SERIES = m0 +MCU_VARIANT = nrf51 +MCU_SUB_VARIANT = nrf51822 +SOFTDEV_VERSION = 8.0.0 +LD_FILE = boards/nrf51x22_256k_16k_s110_$(SOFTDEV_VERSION).ld + +CFLAGS += -DBLUETOOTH_LFCLK_RC diff --git a/ports/nrf/boards/wt51822_s4at/nrf51_hal_conf.h b/ports/nrf/boards/wt51822_s4at/nrf51_hal_conf.h new file mode 100644 index 0000000000..79af193468 --- /dev/null +++ b/ports/nrf/boards/wt51822_s4at/nrf51_hal_conf.h @@ -0,0 +1,14 @@ +#ifndef NRF51_HAL_CONF_H__ +#define NRF51_HAL_CONF_H__ + +#define HAL_UART_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIME_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_TWI_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_TEMP_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED + +#endif // NRF51_HAL_CONF_H__ diff --git a/ports/nrf/boards/wt51822_s4at/pins.csv b/ports/nrf/boards/wt51822_s4at/pins.csv new file mode 100644 index 0000000000..01f5e8fcef --- /dev/null +++ b/ports/nrf/boards/wt51822_s4at/pins.csv @@ -0,0 +1,7 @@ +PA1,PA1 +PA2,PA2 +PA3,PA3 +PA4,PA4 +PA9,PA9 +PA10,PA10 +PA13,PA13 From 61b6faed15e37f2b09a281f4a8ab334703061297 Mon Sep 17 00:00:00 2001 From: Ayke van Laethem Date: Thu, 12 Oct 2017 00:44:24 +0200 Subject: [PATCH 808/809] ports/nrf: Use --gc-sections to reduce code size This saves about 6-7kB. --- ports/nrf/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ports/nrf/Makefile b/ports/nrf/Makefile index 5bc36cadee..ca22e093c3 100644 --- a/ports/nrf/Makefile +++ b/ports/nrf/Makefile @@ -65,7 +65,7 @@ NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET CFLAGS_CORTEX_M = -mthumb -mabi=aapcs -fsingle-precision-constant -Wdouble-promotion -CFLAGS_MCU_m4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections +CFLAGS_MCU_m4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard CFLAGS_MCU_m0 = $(CFLAGS_CORTEX_M) --short-enums -mtune=cortex-m0 -mcpu=cortex-m0 -mfloat-abi=soft -fno-builtin @@ -74,12 +74,14 @@ CFLAGS += $(CFLAGS_MCU_$(MCU_SERIES)) CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) $(CFLAGS_MOD) CFLAGS += -fno-strict-aliasing CFLAGS += -fstack-usage +CFLAGS += -fdata-sections -ffunction-sections CFLAGS += -Iboards/$(BOARD) CFLAGS += -DNRF5_HAL_H='<$(MCU_VARIANT)_hal.h>' LDFLAGS = $(CFLAGS) LDFLAGS += -Xlinker -Map=$(@:.elf=.map) LDFLAGS += -mthumb -mabi=aapcs -T $(LD_FILE) -L boards/ +LDFLAGS += -Wl,--gc-sections #Debugging/Optimization ifeq ($(DEBUG), 1) From f57be619fcd0b36b2a353bc2dc7815270524ff16 Mon Sep 17 00:00:00 2001 From: Ayke van Laethem Date: Thu, 12 Oct 2017 02:46:39 +0200 Subject: [PATCH 809/809] ports/nrf: Add compile switch to disable VFS. This saves about 17kB. --- ports/nrf/builtin_open.c | 30 ------------------------------ ports/nrf/main.c | 16 ++++++++++++++++ ports/nrf/modules/uos/moduos.c | 6 ++++++ ports/nrf/mpconfigport.h | 10 +++++++--- 4 files changed, 29 insertions(+), 33 deletions(-) delete mode 100644 ports/nrf/builtin_open.c diff --git a/ports/nrf/builtin_open.c b/ports/nrf/builtin_open.c deleted file mode 100644 index 697eec8eaa..0000000000 --- a/ports/nrf/builtin_open.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2013, 2014 Damien P. George - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/runtime.h" -#include "extmod/vfs_fat_file.h" - -MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, fatfs_builtin_open); diff --git a/ports/nrf/main.c b/ports/nrf/main.c index 262573d5ff..92f578cda1 100644 --- a/ports/nrf/main.c +++ b/ports/nrf/main.c @@ -30,6 +30,7 @@ #include #include "py/nlr.h" +#include "py/mperrno.h" #include "py/lexer.h" #include "py/parse.h" #include "py/obj.h" @@ -213,6 +214,21 @@ pin_init0(); return 0; } +#if !MICROPY_VFS +mp_lexer_t *mp_lexer_new_from_file(const char *filename) { + mp_raise_OSError(MP_ENOENT); +} + +mp_import_stat_t mp_import_stat(const char *path) { + return MP_IMPORT_STAT_NO_EXIST; +} + +STATIC mp_obj_t mp_builtin_open(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) { + mp_raise_OSError(MP_EPERM); +} +MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open); +#endif + void HardFault_Handler(void) { #if NRF52 diff --git a/ports/nrf/modules/uos/moduos.c b/ports/nrf/modules/uos/moduos.c index 84671bc59d..21ea2cde67 100644 --- a/ports/nrf/modules/uos/moduos.c +++ b/ports/nrf/modules/uos/moduos.c @@ -79,6 +79,7 @@ STATIC mp_obj_t os_uname(void) { } STATIC MP_DEFINE_CONST_FUN_OBJ_0(os_uname_obj, os_uname); +#if MICROPY_VFS /// \function sync() /// Sync all filesystems. STATIC mp_obj_t os_sync(void) { @@ -89,6 +90,7 @@ STATIC mp_obj_t os_sync(void) { return mp_const_none; } MP_DEFINE_CONST_FUN_OBJ_0(mod_os_sync_obj, os_sync); +#endif #if MICROPY_HW_ENABLE_RNG /// \function urandom(n) @@ -133,6 +135,7 @@ STATIC const mp_rom_map_elem_t os_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_uname), MP_ROM_PTR(&os_uname_obj) }, +#if MICROPY_VFS { MP_ROM_QSTR(MP_QSTR_chdir), MP_ROM_PTR(&mp_vfs_chdir_obj) }, { MP_ROM_QSTR(MP_QSTR_getcwd), MP_ROM_PTR(&mp_vfs_getcwd_obj) }, { MP_ROM_QSTR(MP_QSTR_listdir), MP_ROM_PTR(&mp_vfs_listdir_obj) }, @@ -145,6 +148,7 @@ STATIC const mp_rom_map_elem_t os_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_unlink), MP_ROM_PTR(&mp_vfs_remove_obj) }, // unlink aliases to remove { MP_ROM_QSTR(MP_QSTR_sync), MP_ROM_PTR(&mod_os_sync_obj) }, +#endif /// \constant sep - separation character used in paths { MP_ROM_QSTR(MP_QSTR_sep), MP_ROM_QSTR(MP_QSTR__slash_) }, @@ -155,9 +159,11 @@ STATIC const mp_rom_map_elem_t os_module_globals_table[] = { // these are MicroPython extensions { MP_ROM_QSTR(MP_QSTR_dupterm), MP_ROM_PTR(&mod_os_dupterm_obj) }, +#if MICROPY_VFS { MP_ROM_QSTR(MP_QSTR_mount), MP_ROM_PTR(&mp_vfs_mount_obj) }, { MP_ROM_QSTR(MP_QSTR_umount), MP_ROM_PTR(&mp_vfs_umount_obj) }, { MP_ROM_QSTR(MP_QSTR_VfsFat), MP_ROM_PTR(&mp_fat_vfs_type) }, +#endif }; STATIC MP_DEFINE_CONST_DICT(os_module_globals, os_module_globals_table); diff --git a/ports/nrf/mpconfigport.h b/ports/nrf/mpconfigport.h index bc924d514c..46ad669119 100644 --- a/ports/nrf/mpconfigport.h +++ b/ports/nrf/mpconfigport.h @@ -30,13 +30,17 @@ #include // options to control how MicroPython is built +#ifndef MICROPY_VFS +#define MICROPY_VFS (1) +#endif +#define MICROPY_VFS_FAT (MICROPY_VFS) #define MICROPY_ALLOC_PATH_MAX (512) #define MICROPY_PERSISTENT_CODE_LOAD (0) #define MICROPY_EMIT_THUMB (0) #define MICROPY_EMIT_INLINE_THUMB (0) #define MICROPY_COMP_MODULE_CONST (0) #define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0) -#define MICROPY_READER_VFS (1) +#define MICROPY_READER_VFS (MICROPY_VFS) #define MICROPY_ENABLE_GC (1) #define MICROPY_ENABLE_FINALISER (1) #define MICROPY_STACK_CHECK (0) @@ -54,8 +58,6 @@ #define MICROPY_OPT_COMPUTED_GOTO (0) #define MICROPY_OPT_CACHE_MAP_LOOKUP_IN_BYTECODE (0) #define MICROPY_OPT_MPZ_BITWISE (0) -#define MICROPY_VFS (1) -#define MICROPY_VFS_FAT (1) // fatfs configuration used in ffconf.h #define MICROPY_FATFS_ENABLE_LFN (1) @@ -69,9 +71,11 @@ #define mp_type_textio fatfs_type_textio // use vfs's functions for import stat and builtin open +#if MICROPY_VFS #define mp_import_stat mp_vfs_import_stat #define mp_builtin_open mp_vfs_open #define mp_builtin_open_obj mp_vfs_open_obj +#endif #define MICROPY_STREAMS_NON_BLOCK (1) #define MICROPY_MODULE_WEAK_LINKS (1)