From d14e34449b5b70ea5e39938324e27af76498b0dd Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Tue, 2 Jun 2020 17:51:51 -0400 Subject: [PATCH 1/2] Rework LSE clock init, allow clock overrides --- ports/stm/Makefile | 4 +- .../stm/boards/espruino_pico/mpconfigboard.h | 3 +- .../stm/boards/espruino_wifi/mpconfigboard.h | 3 +- .../feather_stm32f405_express/mpconfigboard.h | 4 +- ports/stm/boards/meowbit_v121/mpconfigboard.h | 5 +- .../stm/boards/nucleo_f746zg/mpconfigboard.h | 6 +- .../stm/boards/nucleo_f767zi/mpconfigboard.h | 6 +- .../boards/nucleo_h743zi_2/mpconfigboard.h | 6 +- ports/stm/boards/openmv_h7/mpconfigboard.h | 3 +- ports/stm/boards/pyb_nano_v2/mpconfigboard.h | 3 +- ports/stm/boards/pyboard_v11/mpconfigboard.h | 5 +- .../stm32f411ce_blackpill/mpconfigboard.h | 4 +- .../stm32f411ve_discovery/mpconfigboard.h | 4 +- .../stm32f412zg_discovery/mpconfigboard.h | 5 +- .../boards/stm32f4_discovery/mpconfigboard.h | 3 +- .../stm32f746g_discovery/mpconfigboard.h | 15 ++- ports/stm/boards/thunderpack/mpconfigboard.h | 3 +- ports/stm/peripherals/stm32f4/clocks.c | 120 +++++++++++++++++ .../peripherals/stm32f4/stm32f401xe/clocks.c | 62 --------- .../peripherals/stm32f4/stm32f401xe/clocks.h | 63 +++++++++ .../peripherals/stm32f4/stm32f405xx/clocks.c | 64 --------- .../peripherals/stm32f4/stm32f405xx/clocks.h | 63 +++++++++ .../peripherals/stm32f4/stm32f407xx/clocks.c | 62 --------- .../peripherals/stm32f4/stm32f407xx/clocks.h | 63 +++++++++ .../peripherals/stm32f4/stm32f411xe/clocks.c | 62 --------- .../peripherals/stm32f4/stm32f411xe/clocks.h | 67 ++++++++++ .../peripherals/stm32f4/stm32f412zx/clocks.c | 75 ----------- .../peripherals/stm32f4/stm32f412zx/clocks.h | 66 ++++++++++ ports/stm/peripherals/stm32f7/clocks.c | 118 +++++++++++++++++ .../peripherals/stm32f7/stm32f746xx/clocks.c | 96 -------------- .../peripherals/stm32f7/stm32f746xx/clocks.h | 63 +++++++++ .../peripherals/stm32f7/stm32f767xx/clocks.c | 66 ---------- .../peripherals/stm32f7/stm32f767xx/clocks.h | 63 +++++++++ ports/stm/peripherals/stm32h7/clocks.c | 123 ++++++++++++++++++ .../peripherals/stm32h7/stm32h743xx/clocks.c | 83 ------------ .../peripherals/stm32h7/stm32h743xx/clocks.h | 70 ++++++++++ ports/stm/supervisor/port.c | 60 +-------- 37 files changed, 926 insertions(+), 665 deletions(-) create mode 100644 ports/stm/peripherals/stm32f4/clocks.c delete mode 100644 ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c create mode 100644 ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h delete mode 100644 ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c create mode 100644 ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h delete mode 100644 ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c create mode 100644 ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h delete mode 100644 ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c create mode 100644 ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h delete mode 100644 ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c create mode 100644 ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h create mode 100644 ports/stm/peripherals/stm32f7/clocks.c delete mode 100644 ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c create mode 100644 ports/stm/peripherals/stm32f7/stm32f746xx/clocks.h delete mode 100644 ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c create mode 100644 ports/stm/peripherals/stm32f7/stm32f767xx/clocks.h create mode 100644 ports/stm/peripherals/stm32h7/clocks.c delete mode 100644 ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c create mode 100644 ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h diff --git a/ports/stm/Makefile b/ports/stm/Makefile index bd69d6fd7a..a7b519ffcb 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -207,11 +207,11 @@ SRC_C += \ mphalport.c \ boards/$(BOARD)/board.c \ boards/$(BOARD)/pins.c \ + peripherals/stm32$(MCU_SERIES_LOWER)/clocks.c \ peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/pins.c \ - peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/clocks.c \ peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/gpio.c \ peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/periph.c \ - packages/$(MCU_PACKAGE).c\ + packages/$(MCU_PACKAGE).c \ lib/libc/string0.c \ lib/mp-readline/readline.c \ lib/oofatfs/ff.c \ diff --git a/ports/stm/boards/espruino_pico/mpconfigboard.h b/ports/stm/boards/espruino_pico/mpconfigboard.h index 890b1b88e7..12e24244ff 100644 --- a/ports/stm/boards/espruino_pico/mpconfigboard.h +++ b/ports/stm/boards/espruino_pico/mpconfigboard.h @@ -35,6 +35,7 @@ #define AUTORESET_DELAY_MS (500) #define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000) -#define BOARD_OSC_DIV (8) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) diff --git a/ports/stm/boards/espruino_wifi/mpconfigboard.h b/ports/stm/boards/espruino_wifi/mpconfigboard.h index 80aae3ad42..b7f38f69be 100644 --- a/ports/stm/boards/espruino_wifi/mpconfigboard.h +++ b/ports/stm/boards/espruino_wifi/mpconfigboard.h @@ -32,6 +32,7 @@ #define FLASH_SIZE (0x80000) //512K #define FLASH_PAGE_SIZE (0x4000) //16K -#define BOARD_OSC_DIV (8) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) #define BOARD_OVERWRITE_SWD (1) diff --git a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h index 8f8e245665..0d49748c84 100644 --- a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h +++ b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h @@ -34,8 +34,8 @@ #define MICROPY_HW_NEOPIXEL (&pin_PC00) -#define BOARD_OSC_DIV (12) -#define HSE_VALUE ((uint32_t)12000000U) +#define HSE_VALUE ((uint32_t)12000000U) +#define LSE_VALUE ((uint32_t)32768) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) // On-board flash diff --git a/ports/stm/boards/meowbit_v121/mpconfigboard.h b/ports/stm/boards/meowbit_v121/mpconfigboard.h index 268a660159..106f25b15c 100644 --- a/ports/stm/boards/meowbit_v121/mpconfigboard.h +++ b/ports/stm/boards/meowbit_v121/mpconfigboard.h @@ -35,10 +35,9 @@ #define AUTORESET_DELAY_MS 500 #define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000) -#define BOARD_OSC_DIV (12) +#define HSE_VALUE ((uint32_t)12000000U) +#define LSE_VALUE ((uint32_t)32000U) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) -#define HSE_VALUE ((uint32_t)12000000U) -#define LSE_VALUE ((uint32_t)32000U) #define BOARD_NO_VBUS_SENSE (1) #define BOARD_VTOR_DEFER (1) //Leave VTOR relocation to bootloader diff --git a/ports/stm/boards/nucleo_f746zg/mpconfigboard.h b/ports/stm/boards/nucleo_f746zg/mpconfigboard.h index cd2c61b919..c1f0d59b2d 100644 --- a/ports/stm/boards/nucleo_f746zg/mpconfigboard.h +++ b/ports/stm/boards/nucleo_f746zg/mpconfigboard.h @@ -33,8 +33,10 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) -#define BOARD_HAS_LOW_SPEED_CRYSTAL (0) // TODO: enable this once LSE is fixed for H7/F7 +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) #define DEBUG_UART_TX (&pin_PD08) #define DEBUG_UART_RX (&pin_PD09) diff --git a/ports/stm/boards/nucleo_f767zi/mpconfigboard.h b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h index 1dcb26f49e..21e0ef0ba4 100644 --- a/ports/stm/boards/nucleo_f767zi/mpconfigboard.h +++ b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h @@ -32,5 +32,7 @@ #define FLASH_SIZE (0x200000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) -#define BOARD_HAS_LOW_SPEED_CRYSTAL (0) // TODO: enable this once LSE is fixed for H7/F7 +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) diff --git a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h index 14c2dfe308..1ae7f81a47 100644 --- a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h +++ b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h @@ -31,5 +31,7 @@ #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) -#define BOARD_HAS_LOW_SPEED_CRYSTAL (0) // TODO: enable this once LSE is fixed for H7/F7 +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) diff --git a/ports/stm/boards/openmv_h7/mpconfigboard.h b/ports/stm/boards/openmv_h7/mpconfigboard.h index 9a049ed2cf..300f38aff0 100644 --- a/ports/stm/boards/openmv_h7/mpconfigboard.h +++ b/ports/stm/boards/openmv_h7/mpconfigboard.h @@ -31,7 +31,6 @@ #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (12) -#define HSE_VALUE ((uint32_t)12000000) +#define HSE_VALUE ((uint32_t)12000000) #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) diff --git a/ports/stm/boards/pyb_nano_v2/mpconfigboard.h b/ports/stm/boards/pyb_nano_v2/mpconfigboard.h index 721a91defc..7c1ab31e34 100644 --- a/ports/stm/boards/pyb_nano_v2/mpconfigboard.h +++ b/ports/stm/boards/pyb_nano_v2/mpconfigboard.h @@ -32,7 +32,8 @@ #define FLASH_SIZE (0x80000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) // On-board flash diff --git a/ports/stm/boards/pyboard_v11/mpconfigboard.h b/ports/stm/boards/pyboard_v11/mpconfigboard.h index 77fab2c69e..50a90c52b0 100644 --- a/ports/stm/boards/pyboard_v11/mpconfigboard.h +++ b/ports/stm/boards/pyboard_v11/mpconfigboard.h @@ -32,10 +32,9 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (12) +#define HSE_VALUE ((uint32_t)12000000) +#define LSE_VALUE ((uint32_t)32000U) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) -#define HSE_VALUE ((uint32_t)12000000U) -#define LSE_VALUE ((uint32_t)32000U) #define DEFAULT_I2C_BUS_SCL (&pin_PB06) #define DEFAULT_I2C_BUS_SDA (&pin_PB07) diff --git a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h index a21060a848..83a8bded39 100644 --- a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h +++ b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h @@ -32,11 +32,9 @@ #define FLASH_SIZE (0x80000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (25) +#define HSE_VALUE ((uint32_t)25000000) #define BOARD_NO_VBUS_SENSE (1) - #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) -#define HSE_VALUE ((uint32_t)25000000U) // On-board flash // #define SPI_FLASH_MOSI_PIN (&pin_PA07) diff --git a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h index 3956a365cf..0be43f4fb7 100644 --- a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h @@ -32,8 +32,8 @@ #define FLASH_SIZE (0x80000) //512K #define FLASH_PAGE_SIZE (0x4000) //16K -#define BOARD_OSC_DIV (8) - +#define HSE_VALUE ((uint32_t)8000000) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) // The schematic has a 32k crystal that isn't fitted. Uncommented the line below if you add it. diff --git a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h index c0590b80c1..6b9ab64678 100644 --- a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h @@ -32,8 +32,11 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) +#define CPY_CLK_USB_USES_AUDIOPLL (1) #define DEFAULT_I2C_BUS_SCL (&pin_PB10) #define DEFAULT_I2C_BUS_SDA (&pin_PB09) diff --git a/ports/stm/boards/stm32f4_discovery/mpconfigboard.h b/ports/stm/boards/stm32f4_discovery/mpconfigboard.h index 6274345ade..44ee073780 100644 --- a/ports/stm/boards/stm32f4_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f4_discovery/mpconfigboard.h @@ -32,5 +32,6 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) +#define HSE_VALUE ((uint32_t)8000000) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) diff --git a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h index cace54e9b0..1fa69182a6 100644 --- a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h @@ -34,12 +34,15 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (25) -#define HSE_VALUE ((uint32_t)25000000) -#define BOARD_OSC_PLLN (400) -#define BOARD_OSC_PLLQ (9) +// Lower frequency to allow external RAM use +#define HSE_VALUE ((uint32_t)25000000) +#define LSE_VALUE ((uint32_t)32768) +#define CPY_CLK_PLLN (400) +#define CPY_CLK_PLLQ (9) +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_6) +#define CPY_CLK_USB_USES_AUDIOPLL (1) -#define BOARD_HAS_LOW_SPEED_CRYSTAL (0) // TODO: enable this once LSE is fixed for H7/F7 +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) -#define BOARD_FLASH_LATENCY FLASH_LATENCY_6 #define BOARD_NO_VBUS_SENSE 1 diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h index 7102b12429..394fbfd84f 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.h +++ b/ports/stm/boards/thunderpack/mpconfigboard.h @@ -40,12 +40,11 @@ #define FLASH_PAGE_SIZE (0x4000) #define BOARD_FLASH_SIZE (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE- 0x2000 - 0xC000) -#define BOARD_OSC_DIV (24) +#define HSE_VALUE ((uint32_t)24000000U) #define BOARD_OVERWRITE_SWD (1) #define BOARD_NO_VBUS_SENSE (1) #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) -#define HSE_VALUE ((uint32_t)24000000U) // Status LEDs #define MICROPY_HW_LED_STATUS (&pin_PA02) diff --git a/ports/stm/peripherals/stm32f4/clocks.c b/ports/stm/peripherals/stm32f4/clocks.c new file mode 100644 index 0000000000..7a16812b36 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/clocks.c @@ -0,0 +1,120 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" +#include "supervisor/shared/safe_mode.h" +#include + +// F4 Series +#ifdef STM32F401xE +#include "stm32f4/stm32f401xe/clocks.h" +#endif +#ifdef STM32F411xE +#include "stm32f4/stm32f411xe/clocks.h" +#endif +#ifdef STM32F412Zx +#include "stm32f4/stm32f412zx/clocks.h" +#endif +#ifdef STM32F405xx +#include "stm32f4/stm32f405xx/clocks.h" +#endif +#ifdef STM32F407xx +#include "stm32f4/stm32f407xx/clocks.h" +#endif + +void stm32_peripherals_clocks_init(void) { + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + bool lse_failure = false; + + // Set voltage scaling in accordance with system clock speed + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE); + + // Set up primary PLL and HSE clocks + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + #else + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + #endif + RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; + RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; + RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; + #if (CPY_CLK_USB_USES_AUDIOPLL) + RCC_OscInitStruct.PLL.PLLR = 2; // Unused but required by HAL + #endif + + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // Failure likely means a LSE issue - attempt to swap to LSI, and set to crash + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // No HSE means no USB, so just fail forever + while(1); + } + lse_failure = true; + } + + // Configure bus clock sources and divisors + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV; + RCC_ClkInitStruct.APB1CLKDivider = CPY_CLK_APB1DIV; + RCC_ClkInitStruct.APB2CLKDivider = CPY_CLK_APB2DIV; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, CPY_CLK_FLASH_LATENCY); + + // Set up non-bus peripherals + // TODO: I2S settings go here + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + #else + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + #endif + #if (CPY_CLK_USB_USES_AUDIOPLL) + // Not supported by all lines. Should always result in 48M. + PeriphClkInitStruct.PLLI2S.PLLI2SM = HSE_VALUE/1000000; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_CK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ; + #endif + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + if (lse_failure) { + reset_into_safe_mode(HARD_CRASH); //TODO: make safe mode category CLOCK_FAULT? + } +} diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c deleted file mode 100644 index 194992e819..0000000000 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c +++ /dev/null @@ -1,62 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h new file mode 100644 index 0000000000..be62370d88 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h @@ -0,0 +1,63 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F401 +// Line Type: Access Line +// Speed: 84MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE2) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (336) +#endif +#ifndef (CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV4) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (7) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_2) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c deleted file mode 100644 index f4c5830686..0000000000 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c +++ /dev/null @@ -1,64 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - // APB1 must always be on so that we can talk to the RTC for timing. - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - // TODO: Only turn on APB2 when it is needed to save power. - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h new file mode 100644 index 0000000000..87faec035d --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h @@ -0,0 +1,63 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F405 +// Line Type: Foundation Line +// Speed: 168MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (336) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (7) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV4) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_5) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c deleted file mode 100644 index a545aaec56..0000000000 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c +++ /dev/null @@ -1,62 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h new file mode 100644 index 0000000000..5894b4ae8b --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h @@ -0,0 +1,63 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F407 +// Line Type: Foundation Line +// Speed: 168MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (336) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (7) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV4) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_5) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c deleted file mode 100644 index 194992e819..0000000000 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c +++ /dev/null @@ -1,62 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h new file mode 100644 index 0000000000..adb60e8a9e --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h @@ -0,0 +1,67 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F411 +// Line Type: Access Line +// Speed: 96MHz + +// Note - the actual maximum frequency is 100MHz, but this requires divisors +// which are incompatible with USB, and there is no additional PLL such as on +// the F412. + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (192) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (4) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_3) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c deleted file mode 100644 index 6c4cb5b322..0000000000 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c +++ /dev/null @@ -1,75 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the - * device is clocked below the maximum system frequency, to update the - * voltage scaling value regarding system frequency refer to product - * datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 200; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - RCC_OscInitStruct.PLL.PLLR = 2; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLLSAI output as USB clock source */ - PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; - PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - * clocks dividers */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | - RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h new file mode 100644 index 0000000000..8f092adbac --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h @@ -0,0 +1,66 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F412 +// Line Type: Access Line +// Speed: 200MHz (MAX) + +// Note - uses the I2S PLL for SUSB to enable full 100MHz operation, since USB +// can't get the right divisors from 100MHz PLL settings. + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (200) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (7) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_3) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (1) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f7/clocks.c b/ports/stm/peripherals/stm32f7/clocks.c new file mode 100644 index 0000000000..93016f6828 --- /dev/null +++ b/ports/stm/peripherals/stm32f7/clocks.c @@ -0,0 +1,118 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f7xx_hal.h" +#include "supervisor/shared/safe_mode.h" +#include + +// F7 Series +#ifdef STM32F746xx +#include "stm32f7/stm32f746xx/clocks.h" +#endif +#ifdef STM32F767xx +#include "stm32f7/stm32f767xx/clocks.h" +#endif + +void stm32_peripherals_clocks_init(void) { + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + bool lse_failure = false; + + // Configure LSE Drive + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + // Set voltage scaling in accordance with system clock speed + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE); + + // Set up primary PLL and HSE clocks + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + #else + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + #endif + RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; + RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; + RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; + + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // Failure likely means a LSE issue - attempt to swap to LSI, and set to crash + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // No HSE means no USB, so just fail forever + while(1); + } + lse_failure = true; + } + + /* Activate the OverDrive to reach the 216 MHz Frequency */ + HAL_PWREx_EnableOverDrive(); + + // Configure bus clock sources and divisors + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV; + RCC_ClkInitStruct.APB1CLKDivider = CPY_CLK_APB1DIV; + RCC_ClkInitStruct.APB2CLKDivider = CPY_CLK_APB2DIV; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, CPY_CLK_FLASH_LATENCY); + + // Set up non-bus peripherals + // TODO: I2S settings go here + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + #else + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + #endif + #if (CPY_CLK_USB_USES_AUDIOPLL) + // Should always result in 48M. + PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; + PeriphClkInitStruct.PLLSAI.PLLSAIR = 2; + PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; + PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4; + PeriphClkInitStruct.PLLSAIDivQ = 1; + PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; + PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_CK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP; + #endif + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + if (lse_failure) { + reset_into_safe_mode(HARD_CRASH); //TODO: make safe mode category CLOCK_FAULT? + } +} diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c b/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c deleted file mode 100644 index 2afa2e377a..0000000000 --- a/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c +++ /dev/null @@ -1,96 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Lucian Copeland for Adafruit Industries - * Copyright (c) 2020 Mark Olsson - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include STM32_HAL_H - -#ifndef BOARD_OSC_DIV -#define BOARD_OSC_DIV (8) -#endif -#ifndef BOARD_OSC_PLLN -#define BOARD_OSC_PLLN (432) -#endif -#ifndef BOARD_OSC_PLLQ -#define BOARD_OSC_PLLQ (9) -#endif -#ifndef BOARD_FLASH_LATENCY -#define BOARD_FLASH_LATENCY FLASH_LATENCY_7 -#endif -#ifndef BOARD_OSC_HSESTATE -#define BOARD_OSC_HSESTATE RCC_HSE_BYPASS -#endif - -void stm32_peripherals_clocks_init(void) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = BOARD_OSC_HSESTATE; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = BOARD_OSC_PLLN; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = BOARD_OSC_PLLQ; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Activate the OverDrive to reach the 216 MHz Frequency */ - HAL_PWREx_EnableOverDrive(); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, BOARD_FLASH_LATENCY); - - #ifdef STM32F746G_DISCO - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; - PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; - PeriphClkInitStruct.PLLSAI.PLLSAIR = 2; - PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; - PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4; - PeriphClkInitStruct.PLLSAIDivQ = 1; - PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - #endif -} diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.h b/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.h new file mode 100644 index 0000000000..eb44625143 --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.h @@ -0,0 +1,63 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f7xx_hal.h" + +// Chip: STM32F746 +// Line Type: Advanced Line +// Speed: 216MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (432) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (9) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV4) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_7) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c deleted file mode 100644 index 18b202df56..0000000000 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c +++ /dev/null @@ -1,66 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f7xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 432; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 9; - RCC_OscInitStruct.PLL.PLLR = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Activate the OverDrive to reach the 216 MHz Frequency */ - HAL_PWREx_EnableOverDrive(); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); - -} diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.h b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.h new file mode 100644 index 0000000000..187a024ad0 --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.h @@ -0,0 +1,63 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f7xx_hal.h" + +// Chip: STM32F767 +// Line Type: Advanced Line +// Speed: 216MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (432) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (9) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV4) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_7) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32h7/clocks.c b/ports/stm/peripherals/stm32h7/clocks.c new file mode 100644 index 0000000000..d68137df0f --- /dev/null +++ b/ports/stm/peripherals/stm32h7/clocks.c @@ -0,0 +1,123 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32h7xx_hal.h" +#include "supervisor/shared/safe_mode.h" +#include + +// H7 Series +#ifdef STM32H743xx +#include "stm32h7/stm32h743xx/clocks.h" +#endif + +void stm32_peripherals_clocks_init(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + bool lse_failure = false; + + // Set voltage scaling in accordance with system clock speed + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + __HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE); + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + // Configure LSE Drive + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + // Set up primary PLL and HSE clocks + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + #else + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + #endif + #if (CPY_CLK_USB_USES_AUDIOPLL) // Not actually audio PLL in this case, swap macro? + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + #endif + RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/2000000; + RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; + RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; + RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // Failure likely means a LSE issue - attempt to swap to LSI, and set to crash + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // No HSE means no USB, so just fail forever + while(1); + } + lse_failure = true; + } + + // Configure bus clock sources and divisors + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV; + RCC_ClkInitStruct.APB1CLKDivider = CPY_CLK_APB1DIV; + RCC_ClkInitStruct.APB2CLKDivider = CPY_CLK_APB2DIV; + RCC_ClkInitStruct.APB3CLKDivider = CPY_CLK_APB3DIV; + RCC_ClkInitStruct.APB4CLKDivider = CPY_CLK_APB4DIV; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, CPY_CLK_FLASH_LATENCY); + + // Set up non-bus peripherals + // TODO: I2S settings go here + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART3 + |RCC_PERIPHCLK_USB; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + #else + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + #endif + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + #if (CPY_CLK_USB_USES_AUDIOPLL) // Not actually audio PLL in this case, swap macro? + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + #else + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; + #endif + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + // Enable USB Voltage detector + HAL_PWREx_EnableUSBVoltageDetector(); + + if (lse_failure) { + reset_into_safe_mode(HARD_CRASH); //TODO: make safe mode category CLOCK_FAULT? + } +} \ No newline at end of file diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c deleted file mode 100644 index 8ede6080e8..0000000000 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c +++ /dev/null @@ -1,83 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32h7xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The PWR block is always enabled on the H7 series- there is no clock - enable. For now, use the default VOS3 scale mode (lowest) and limit clock - frequencies to avoid potential current draw problems from bus - power when using the max clock speeds throughout the chip. */ - - /* Enable HSE Oscillator and activate PLL1 with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.CSIState = RCC_CSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 7; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; - RCC_OscInitStruct.PLL.PLLFRACN = 0; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \ - RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \ - RCC_CLOCKTYPE_D3PCLK1); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; - - /* Unlike on the STM32F4 family, it appears the maximum APB frequencies are - device-dependent- 120 MHz for this board according to Figure 2 of - the datasheet. Dividing by half will be safe for now. */ - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - - /* 4 wait states required for 168MHz and VOS3. */ - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); - - /* Like on F4, on H7, USB's actual peripheral clock and bus clock are - separate. However, the main system PLL (PLL1) doesn't have a direct - connection to the USB peripheral clock to generate 48 MHz, so we do this - dance. This will connect PLL1's Q output to the USB peripheral clock. */ - RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; - - RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; - HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); - -} diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h new file mode 100644 index 0000000000..ad241b7ef6 --- /dev/null +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h @@ -0,0 +1,70 @@ + +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32h7xx_hal.h" + +// Chip: STM32H743 +// Line Type: Single-Core +// Speed: 480MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE0) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (480) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (20) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_APB1_DIV2) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_APB2_DIV2) +#endif +#ifndef CPY_CLK_APB3DIV +#define CPY_CLK_APB3DIV (RCC_APB3_DIV2) +#endif +#ifndef CPY_CLK_APB4DIV +#define CPY_CLK_APB4DIV (RCC_APB4_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_4) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index 9b62fa2eb1..cb500addee 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -169,64 +169,7 @@ safe_mode_t port_init(void) { stm32_peripherals_clocks_init(); stm32_peripherals_gpio_init(); - HAL_PWR_EnableBkUpAccess(); - - // TODO: move all of this to clocks.c - #if BOARD_HAS_LOW_SPEED_CRYSTAL - uint32_t tickstart = HAL_GetTick(); - - // H7/F7 untested with LSE, so autofail them until above move is done - #if (CPY_STM32F4) - bool lse_setupsuccess = true; - #else - bool lse_setupsuccess = false; - #endif - - // Update LSE configuration in Backup Domain control register - // Requires to enable write access to Backup Domain of necessary - // TODO: should be using the HAL OSC initializer, otherwise we'll need - // preprocessor defines for every register to account for F7/H7 - #if (CPY_STM32F4) - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - // Enable write access to Backup domain - SET_BIT(PWR->CR, PWR_CR_DBP); - // Wait for Backup domain Write protection disable - tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - lse_setupsuccess = false; - } - } - } - #endif - - __HAL_RCC_LSE_CONFIG(RCC_LSE_ON); - tickstart = HAL_GetTick(); - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - if((HAL_GetTick() - tickstart ) > LSE_STARTUP_TIMEOUT) - { - lse_setupsuccess = false; - __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); - __HAL_RCC_LSI_ENABLE(); - rtc_clock_frequency = LSI_VALUE; - break; - } - } - - if (lse_setupsuccess) { - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - } else { - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - } - - #else - __HAL_RCC_LSI_ENABLE(); - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - #endif - + // RTC oscillator selection is handled in peripherals///clocks.c __HAL_RCC_RTC_ENABLE(); _hrtc.Instance = RTC; _hrtc.Init.HourFormat = RTC_HOURFORMAT_24; @@ -237,7 +180,6 @@ safe_mode_t port_init(void) { _hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; HAL_RTC_Init(&_hrtc); - HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); return NO_SAFE_MODE; From ad0971fb25347a8cc36ace2c45449ef7eac6995e Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Fri, 5 Jun 2020 11:42:34 -0400 Subject: [PATCH 2/2] Override HAL_Delay and HAL_GetTick --- .../peripherals/stm32f4/stm32f401xe/clocks.h | 2 +- .../peripherals/stm32f4/stm32f411xe/clocks.h | 2 +- .../peripherals/stm32f4/stm32f412zx/clocks.h | 2 +- ports/stm/peripherals/stm32h7/clocks.c | 2 +- ports/stm/supervisor/port.c | 32 +++++++++++++++++-- 5 files changed, 33 insertions(+), 7 deletions(-) diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h index be62370d88..d157d944a3 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h @@ -37,7 +37,7 @@ #ifndef CPY_CLK_PLLN #define CPY_CLK_PLLN (336) #endif -#ifndef (CPY_CLK_PLLP +#ifndef CPY_CLK_PLLP #define CPY_CLK_PLLP (RCC_PLLP_DIV4) #endif #ifndef CPY_CLK_PLLQ diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h index adb60e8a9e..a2fb7bd544 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h @@ -32,7 +32,7 @@ // Note - the actual maximum frequency is 100MHz, but this requires divisors // which are incompatible with USB, and there is no additional PLL such as on -// the F412. +// the F412. // Defaults: #ifndef CPY_CLK_VSCALE diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h index 8f092adbac..e1355c8f34 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h @@ -30,7 +30,7 @@ // Line Type: Access Line // Speed: 200MHz (MAX) -// Note - uses the I2S PLL for SUSB to enable full 100MHz operation, since USB +// Note - uses the I2S PLL for SUSB to enable full 100MHz operation, since USB // can't get the right divisors from 100MHz PLL settings. // Defaults: diff --git a/ports/stm/peripherals/stm32h7/clocks.c b/ports/stm/peripherals/stm32h7/clocks.c index d68137df0f..0e4e79f9f7 100644 --- a/ports/stm/peripherals/stm32h7/clocks.c +++ b/ports/stm/peripherals/stm32h7/clocks.c @@ -120,4 +120,4 @@ void stm32_peripherals_clocks_init(void) { if (lse_failure) { reset_into_safe_mode(HARD_CRASH); //TODO: make safe mode category CLOCK_FAULT? } -} \ No newline at end of file +} diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index 8156b2272a..25504ddece 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -147,9 +147,10 @@ __attribute__((used, naked)) void Reset_Handler(void) { __enable_irq(); main(); } - #endif //end H7 specific code +// Low power clock variables +static volatile uint32_t systick_ms; static RTC_HandleTypeDef _hrtc; #if BOARD_HAS_LOW_SPEED_CRYSTAL @@ -159,7 +160,7 @@ static uint32_t rtc_clock_frequency = LSI_VALUE; #endif safe_mode_t port_init(void) { - HAL_Init(); + HAL_Init(); // Turns on SysTick __HAL_RCC_SYSCFG_CLK_ENABLE(); #if (CPY_STM32F4) @@ -182,13 +183,38 @@ safe_mode_t port_init(void) { HAL_RTC_Init(&_hrtc); HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + // Turn off SysTick + SysTick->CTRL = 0; + return NO_SAFE_MODE; } +void HAL_Delay(uint32_t delay_ms) { + if (SysTick->CTRL != 0) { + // SysTick is on, so use it + uint32_t tickstart = systick_ms; + while (systick_ms - tickstart < delay_ms) { + } + } else { + mp_hal_delay_ms(delay_ms); + } +} + +uint32_t HAL_GetTick() { + if (SysTick->CTRL != 0) { + return systick_ms; + } else { + uint8_t subticks; + uint32_t result = (uint32_t)port_get_raw_ticks(&subticks); + return result; + } +} + + void SysTick_Handler(void) { + systick_ms += 1; // Read the CTRL register to clear the SysTick interrupt. SysTick->CTRL; - HAL_IncTick(); } void reset_port(void) {