2021-03-15 09:57:36 -04:00
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/*
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2020-06-02 17:51:51 -04:00
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "stm32f4xx_hal.h"
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// Chip: STM32F411
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// Line Type: Access Line
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// Speed: 96MHz
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// Note - the actual maximum frequency is 100MHz, but this requires divisors
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// which are incompatible with USB, and there is no additional PLL such as on
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2020-06-05 11:42:34 -04:00
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// the F412.
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2020-06-02 17:51:51 -04:00
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// Defaults:
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#ifndef CPY_CLK_VSCALE
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#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1)
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#endif
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#ifndef CPY_CLK_PLLN
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#define CPY_CLK_PLLN (192)
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#endif
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#ifndef CPY_CLK_PLLP
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#define CPY_CLK_PLLP (RCC_PLLP_DIV2)
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#endif
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#ifndef CPY_CLK_PLLQ
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#define CPY_CLK_PLLQ (4)
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#endif
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#ifndef CPY_CLK_AHBDIV
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#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1)
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#endif
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#ifndef CPY_CLK_APB1DIV
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#define CPY_CLK_APB1DIV (RCC_HCLK_DIV2)
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#endif
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#ifndef CPY_CLK_APB2DIV
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#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1)
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#endif
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#ifndef CPY_CLK_FLASH_LATENCY
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#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_3)
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#endif
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#ifndef CPY_CLK_USB_USES_AUDIOPLL
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#define CPY_CLK_USB_USES_AUDIOPLL (0)
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#endif
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#ifndef BOARD_HSE_SOURCE
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#define BOARD_HSE_SOURCE (RCC_HSE_ON)
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#endif
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