2016-11-03 18:50:59 -04:00
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mphal.h"
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2017-08-25 16:00:27 -04:00
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#include "py/obj.h"
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2017-09-22 21:05:51 -04:00
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#include "hal/include/hal_atomic.h"
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2018-01-02 21:25:41 -05:00
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#include "py/runtime.h"
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2016-11-03 18:50:59 -04:00
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2018-01-02 21:25:41 -05:00
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#include "reset.h"
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2016-11-03 18:50:59 -04:00
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2017-08-25 16:00:27 -04:00
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#include "shared-bindings/nvm/ByteArray.h"
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2018-01-02 21:25:41 -05:00
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#include "shared-bindings/microcontroller/__init__.h"
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2018-05-25 21:39:16 -04:00
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#include "shared-bindings/microcontroller/Pin.h"
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2017-08-31 13:48:30 -04:00
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#include "shared-bindings/microcontroller/Processor.h"
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2019-05-08 18:23:40 -04:00
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#include "supervisor/shared/safe_mode.h"
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2022-05-27 15:59:54 -04:00
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#include "supervisor/shared/translate/translate.h"
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2017-08-25 16:00:27 -04:00
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2016-11-03 18:50:59 -04:00
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void common_hal_mcu_delay_us(uint32_t delay) {
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mp_hal_delay_us(delay);
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}
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2018-05-31 19:47:18 -04:00
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volatile uint32_t nesting_count = 0;
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2016-11-30 18:08:34 -05:00
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void common_hal_mcu_disable_interrupts(void) {
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2018-06-05 15:38:31 -04:00
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__disable_irq();
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__DMB();
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2018-05-31 19:47:18 -04:00
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nesting_count++;
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}
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void common_hal_mcu_enable_interrupts(void) {
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2018-05-31 19:47:18 -04:00
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if (nesting_count == 0) {
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2023-02-11 23:50:20 -05:00
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// This is very very bad because it means there was mismatched disable/enables.
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reset_into_safe_mode(SAFE_MODE_INTERRUPT_ERROR);
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2018-05-31 19:47:18 -04:00
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}
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nesting_count--;
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if (nesting_count > 0) {
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return;
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}
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__DMB();
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2018-06-05 15:38:31 -04:00
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__enable_irq();
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2016-11-30 18:08:34 -05:00
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}
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2018-01-02 21:25:41 -05:00
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void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) {
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2019-05-09 13:15:28 -04:00
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if (runmode == RUNMODE_BOOTLOADER) {
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if (!bootloader_available()) {
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2022-05-13 15:33:43 -04:00
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mp_raise_ValueError(translate("Cannot reset into bootloader because no bootloader is present"));
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2019-05-09 13:15:28 -04:00
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}
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2018-01-02 21:25:41 -05:00
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// Pretend to be the first of the two reset presses needed to enter the
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// bootloader. That way one reset will end in the bootloader.
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_bootloader_dbl_tap = DBL_TAP_MAGIC;
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2019-05-08 18:23:40 -04:00
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} else {
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// Set up the default.
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_bootloader_dbl_tap = DBL_TAP_MAGIC_QUICK_BOOT;
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2018-01-02 21:25:41 -05:00
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}
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2019-05-09 13:15:28 -04:00
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if (runmode == RUNMODE_SAFE_MODE) {
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2023-02-11 23:50:20 -05:00
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safe_mode_on_next_reset(SAFE_MODE_PROGRAMMATIC);
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2019-05-08 18:23:40 -04:00
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}
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2019-05-09 13:15:28 -04:00
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}
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void common_hal_mcu_reset(void) {
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2018-01-02 21:25:41 -05:00
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reset();
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}
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2017-08-31 13:48:30 -04:00
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// The singleton microcontroller.Processor object, bound to microcontroller.cpu
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// It currently only has properties, and no state.
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2018-01-02 21:25:41 -05:00
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const mcu_processor_obj_t common_hal_mcu_processor_obj = {
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2017-08-31 13:48:30 -04:00
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.base = {
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.type = &mcu_processor_type,
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},
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};
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2017-08-25 16:00:27 -04:00
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#if CIRCUITPY_INTERNAL_NVM_SIZE > 0
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2017-08-31 13:48:30 -04:00
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// The singleton nvm.ByteArray object.
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2018-04-12 21:13:40 -04:00
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const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = {
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.base = {
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.type = &nvm_bytearray_type,
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},
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.len = CIRCUITPY_INTERNAL_NVM_SIZE,
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2021-04-30 16:30:13 -04:00
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.start_address = (uint8_t *)(CIRCUITPY_INTERNAL_NVM_START_ADDR)
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2018-04-12 21:13:40 -04:00
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};
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2017-08-25 16:00:27 -04:00
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#endif
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2021-10-19 11:26:09 -04:00
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#if CIRCUITPY_WATCHDOG
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// The singleton watchdog.WatchDogTimer object.
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watchdog_watchdogtimer_obj_t common_hal_mcu_watchdogtimer_obj = {
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.base = {
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.type = &watchdog_watchdogtimer_type,
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},
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.timeout = 0.0f,
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.mode = WATCHDOGMODE_NONE,
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};
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#endif
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2016-11-03 18:50:59 -04:00
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// This maps MCU pin names to pin objects.
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2017-08-27 15:02:50 -04:00
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STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = {
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2021-04-30 16:30:13 -04:00
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#if defined(PIN_PA00) && !defined(IGNORE_PIN_PA00)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA01) && !defined(IGNORE_PIN_PA01)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA02) && !defined(IGNORE_PIN_PA02)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA03) && !defined(IGNORE_PIN_PA03)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA04) && !defined(IGNORE_PIN_PA04)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA05) && !defined(IGNORE_PIN_PA05)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA06) && !defined(IGNORE_PIN_PA06)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA07) && !defined(IGNORE_PIN_PA07)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA08) && !defined(IGNORE_PIN_PA08)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA09) && !defined(IGNORE_PIN_PA09)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA10) && !defined(IGNORE_PIN_PA10)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA11) && !defined(IGNORE_PIN_PA11)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA12) && !defined(IGNORE_PIN_PA12)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA13) && !defined(IGNORE_PIN_PA13)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA14) && !defined(IGNORE_PIN_PA14)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA15) && !defined(IGNORE_PIN_PA15)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA16) && !defined(IGNORE_PIN_PA16)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA16), MP_ROM_PTR(&pin_PA16) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA17) && !defined(IGNORE_PIN_PA17)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA17), MP_ROM_PTR(&pin_PA17) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA18) && !defined(IGNORE_PIN_PA18)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA18), MP_ROM_PTR(&pin_PA18) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA19) && !defined(IGNORE_PIN_PA19)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA19), MP_ROM_PTR(&pin_PA19) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA20) && !defined(IGNORE_PIN_PA20)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA20), MP_ROM_PTR(&pin_PA20) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA21) && !defined(IGNORE_PIN_PA21)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA21), MP_ROM_PTR(&pin_PA21) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA22) && !defined(IGNORE_PIN_PA22)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA22), MP_ROM_PTR(&pin_PA22) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA23) && !defined(IGNORE_PIN_PA23)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA23), MP_ROM_PTR(&pin_PA23) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA24) && !defined(IGNORE_PIN_PA24)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA24), MP_ROM_PTR(&pin_PA24) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA25) && !defined(IGNORE_PIN_PA25)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA25), MP_ROM_PTR(&pin_PA25) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA27) && !defined(IGNORE_PIN_PA27)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA27), MP_ROM_PTR(&pin_PA27) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA28) && !defined(IGNORE_PIN_PA28)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA28), MP_ROM_PTR(&pin_PA28) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA30) && !defined(IGNORE_PIN_PA30)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA30), MP_ROM_PTR(&pin_PA30) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PA31) && !defined(IGNORE_PIN_PA31)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PA31), MP_ROM_PTR(&pin_PA31) },
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2021-04-30 16:30:13 -04:00
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#endif
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2018-10-19 21:46:22 -04:00
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2021-04-30 16:30:13 -04:00
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#if defined(PIN_PB00) && !defined(IGNORE_PIN_PB00)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PB01) && !defined(IGNORE_PIN_PB01)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PB02) && !defined(IGNORE_PIN_PB02)
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2017-08-27 15:02:50 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PB03) && !defined(IGNORE_PIN_PB03)
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2018-08-07 10:43:52 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PB04) && !defined(IGNORE_PIN_PB04)
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2018-10-19 21:46:22 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PB05) && !defined(IGNORE_PIN_PB05)
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2018-10-19 21:46:22 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
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2021-04-30 16:30:13 -04:00
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#endif
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#if defined(PIN_PB06) && !defined(IGNORE_PIN_PB06)
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2018-10-19 21:46:22 -04:00
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{ MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
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2021-04-30 16:30:13 -04:00
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#endif
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|
|
#if defined(PIN_PB07) && !defined(IGNORE_PIN_PB07)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB08) && !defined(IGNORE_PIN_PB08)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB09) && !defined(IGNORE_PIN_PB09)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB10) && !defined(IGNORE_PIN_PB10)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB11) && !defined(IGNORE_PIN_PB11)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB12) && !defined(IGNORE_PIN_PB12)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB13) && !defined(IGNORE_PIN_PB13)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB14) && !defined(IGNORE_PIN_PB14)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB15) && !defined(IGNORE_PIN_PB15)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB16) && !defined(IGNORE_PIN_PB16)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB16), MP_ROM_PTR(&pin_PB16) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB17) && !defined(IGNORE_PIN_PB17)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB17), MP_ROM_PTR(&pin_PB17) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB18) && !defined(IGNORE_PIN_PB18)
|
2019-01-09 13:19:07 -05:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB18), MP_ROM_PTR(&pin_PB18) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB19) && !defined(IGNORE_PIN_PB19)
|
2019-01-09 13:19:07 -05:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB19), MP_ROM_PTR(&pin_PB19) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB20) && !defined(IGNORE_PIN_PB20)
|
2019-01-09 13:19:07 -05:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB20), MP_ROM_PTR(&pin_PB20) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB21) && !defined(IGNORE_PIN_PB21)
|
2019-01-09 13:19:07 -05:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB21), MP_ROM_PTR(&pin_PB21) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB22) && !defined(IGNORE_PIN_PB22)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB22), MP_ROM_PTR(&pin_PB22) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB23) && !defined(IGNORE_PIN_PB23)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB23), MP_ROM_PTR(&pin_PB23) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
2021-05-03 09:33:18 -04:00
|
|
|
#if defined(PIN_PB24) && !defined(IGNORE_PIN_PB24)
|
2021-04-28 13:19:34 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB24), MP_ROM_PTR(&pin_PB24) },
|
2021-05-03 09:33:18 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB25) && !defined(IGNORE_PIN_PB25)
|
2021-04-28 13:19:34 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB25), MP_ROM_PTR(&pin_PB25) },
|
2021-05-03 09:33:18 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB26) && !defined(IGNORE_PIN_PB26)
|
2021-04-28 13:19:34 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB26), MP_ROM_PTR(&pin_PB26) },
|
2021-05-03 09:33:18 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB27) && !defined(IGNORE_PIN_PB27)
|
2021-04-28 13:19:34 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB27), MP_ROM_PTR(&pin_PB27) },
|
2021-05-03 09:33:18 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB28) && !defined(IGNORE_PIN_PB28)
|
2021-04-28 13:19:34 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB28), MP_ROM_PTR(&pin_PB28) },
|
2021-05-03 09:33:18 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB29) && !defined(IGNORE_PIN_PB29)
|
2021-04-28 13:19:34 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB29), MP_ROM_PTR(&pin_PB29) },
|
2021-05-03 09:33:18 -04:00
|
|
|
#endif
|
2021-04-30 16:30:13 -04:00
|
|
|
#if defined(PIN_PB30) && !defined(IGNORE_PIN_PB30)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB30), MP_ROM_PTR(&pin_PB30) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PB31) && !defined(IGNORE_PIN_PB31)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PB31), MP_ROM_PTR(&pin_PB31) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
2018-10-19 21:46:22 -04:00
|
|
|
|
2021-04-30 16:30:13 -04:00
|
|
|
#if defined(PIN_PC00) && !defined(IGNORE_PIN_PC00)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC01) && !defined(IGNORE_PIN_PC01)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC02) && !defined(IGNORE_PIN_PC02)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC03) && !defined(IGNORE_PIN_PC03)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC04) && !defined(IGNORE_PIN_PC04)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC05) && !defined(IGNORE_PIN_PC05)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC06) && !defined(IGNORE_PIN_PC06)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC07) && !defined(IGNORE_PIN_PC07)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC10) && !defined(IGNORE_PIN_PC10)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC11) && !defined(IGNORE_PIN_PC11)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC12) && !defined(IGNORE_PIN_PC12)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC13) && !defined(IGNORE_PIN_PC13)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC14) && !defined(IGNORE_PIN_PC14)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC15) && !defined(IGNORE_PIN_PC15)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC16) && !defined(IGNORE_PIN_PC16)
|
2018-08-07 10:43:52 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC16), MP_ROM_PTR(&pin_PC16) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC17) && !defined(IGNORE_PIN_PC17)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC17), MP_ROM_PTR(&pin_PC17) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC18) && !defined(IGNORE_PIN_PC18)
|
2018-08-07 10:43:52 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC18), MP_ROM_PTR(&pin_PC18) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC19) && !defined(IGNORE_PIN_PC19)
|
2018-08-07 10:43:52 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC19), MP_ROM_PTR(&pin_PC19) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC20) && !defined(IGNORE_PIN_PC20)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC20), MP_ROM_PTR(&pin_PC20) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC21) && !defined(IGNORE_PIN_PC21)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC21), MP_ROM_PTR(&pin_PC21) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC22) && !defined(IGNORE_PIN_PC22)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC22), MP_ROM_PTR(&pin_PC22) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC23) && !defined(IGNORE_PIN_PC23)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC23), MP_ROM_PTR(&pin_PC23) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC24) && !defined(IGNORE_PIN_PC24)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC24), MP_ROM_PTR(&pin_PC24) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC25) && !defined(IGNORE_PIN_PC25)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC25), MP_ROM_PTR(&pin_PC25) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC26) && !defined(IGNORE_PIN_PC26)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC26), MP_ROM_PTR(&pin_PC26) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC27) && !defined(IGNORE_PIN_PC27)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC27), MP_ROM_PTR(&pin_PC27) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC28) && !defined(IGNORE_PIN_PC28)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC28), MP_ROM_PTR(&pin_PC28) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC30) && !defined(IGNORE_PIN_PC30)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC30), MP_ROM_PTR(&pin_PC30) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PC31) && !defined(IGNORE_PIN_PC31)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PC31), MP_ROM_PTR(&pin_PC31) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
2018-10-19 21:46:22 -04:00
|
|
|
|
2021-04-30 16:30:13 -04:00
|
|
|
#if defined(PIN_PD00) && !defined(IGNORE_PIN_PD00)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PD01) && !defined(IGNORE_PIN_PD01)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PD08) && !defined(IGNORE_PIN_PD08)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PD09) && !defined(IGNORE_PIN_PD09)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PD10) && !defined(IGNORE_PIN_PD10)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PD11) && !defined(IGNORE_PIN_PD11)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PD12) && !defined(IGNORE_PIN_PD12)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PD20) && !defined(IGNORE_PIN_PD20)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PD20), MP_ROM_PTR(&pin_PD20) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
|
|
|
#if defined(PIN_PD21) && !defined(IGNORE_PIN_PD21)
|
2018-10-19 21:46:22 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PD21), MP_ROM_PTR(&pin_PD21) },
|
2021-04-30 16:30:13 -04:00
|
|
|
#endif
|
2016-11-03 18:50:59 -04:00
|
|
|
};
|
|
|
|
MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_global_dict_table);
|