2018-02-13 06:21:46 -05:00
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017-2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/obj.h"
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2018-03-09 06:22:29 -05:00
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#include "py/mperrno.h"
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2018-03-27 05:38:57 -04:00
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#include "irq.h"
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2018-03-02 07:11:47 -05:00
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#include "led.h"
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2018-02-13 06:21:46 -05:00
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#include "storage.h"
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2018-05-27 20:57:27 -04:00
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#if MICROPY_HW_ENABLE_STORAGE
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2018-03-09 08:22:38 -05:00
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int32_t spi_bdev_ioctl(spi_bdev_t *bdev, uint32_t op, uint32_t arg) {
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2018-03-09 06:22:29 -05:00
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switch (op) {
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case BDEV_IOCTL_INIT:
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2018-03-09 08:22:38 -05:00
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bdev->spiflash.config = (const mp_spiflash_config_t*)arg;
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mp_spiflash_init(&bdev->spiflash);
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bdev->flash_tick_counter_last_write = 0;
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2018-03-09 06:22:29 -05:00
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return 0;
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case BDEV_IOCTL_IRQ_HANDLER:
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2018-03-27 05:38:57 -04:00
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if ((bdev->spiflash.flags & 1) && HAL_GetTick() - bdev->flash_tick_counter_last_write >= 1000) {
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2018-06-07 01:36:27 -04:00
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mp_spiflash_cache_flush(&bdev->spiflash);
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2018-03-09 06:22:29 -05:00
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led_state(PYB_LED_RED, 0); // indicate a clean cache with LED off
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}
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return 0;
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case BDEV_IOCTL_SYNC:
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if (bdev->spiflash.flags & 1) {
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2018-09-12 01:46:04 -04:00
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uint32_t basepri = raise_irq_pri(IRQ_PRI_FLASH); // prevent cache flushing and USB access
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2018-06-07 01:36:27 -04:00
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mp_spiflash_cache_flush(&bdev->spiflash);
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2018-03-09 06:22:29 -05:00
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led_state(PYB_LED_RED, 0); // indicate a clean cache with LED off
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restore_irq_pri(basepri);
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}
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return 0;
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2019-11-13 01:31:35 -05:00
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case BDEV_IOCTL_BLOCK_ERASE: {
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uint32_t basepri = raise_irq_pri(IRQ_PRI_FLASH); // prevent cache flushing and USB access
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mp_spiflash_erase_block(&bdev->spiflash, arg * MP_SPIFLASH_ERASE_BLOCK_SIZE);
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restore_irq_pri(basepri);
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return 0;
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}
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2018-03-02 07:11:47 -05:00
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}
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return -MP_EINVAL;
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2018-02-13 06:21:46 -05:00
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}
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2018-03-09 08:22:38 -05:00
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int spi_bdev_readblocks(spi_bdev_t *bdev, uint8_t *dest, uint32_t block_num, uint32_t num_blocks) {
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2018-09-12 01:46:04 -04:00
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uint32_t basepri = raise_irq_pri(IRQ_PRI_FLASH); // prevent cache flushing and USB access
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2018-06-07 01:36:27 -04:00
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mp_spiflash_cached_read(&bdev->spiflash, block_num * FLASH_BLOCK_SIZE, num_blocks * FLASH_BLOCK_SIZE, dest);
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2018-02-13 06:21:46 -05:00
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restore_irq_pri(basepri);
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2018-03-02 08:13:15 -05:00
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return 0;
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2018-02-13 06:21:46 -05:00
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}
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2018-03-09 08:22:38 -05:00
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int spi_bdev_writeblocks(spi_bdev_t *bdev, const uint8_t *src, uint32_t block_num, uint32_t num_blocks) {
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2018-09-12 01:46:04 -04:00
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uint32_t basepri = raise_irq_pri(IRQ_PRI_FLASH); // prevent cache flushing and USB access
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2018-06-07 01:36:27 -04:00
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int ret = mp_spiflash_cached_write(&bdev->spiflash, block_num * FLASH_BLOCK_SIZE, num_blocks * FLASH_BLOCK_SIZE, src);
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2018-03-09 08:22:38 -05:00
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if (bdev->spiflash.flags & 1) {
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2018-03-02 07:11:47 -05:00
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led_state(PYB_LED_RED, 1); // indicate a dirty cache with LED on
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2018-03-09 08:22:38 -05:00
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bdev->flash_tick_counter_last_write = HAL_GetTick();
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2018-03-02 07:11:47 -05:00
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}
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2018-02-13 06:21:46 -05:00
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restore_irq_pri(basepri);
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2018-03-02 08:13:15 -05:00
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return ret;
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2018-02-13 06:21:46 -05:00
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}
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2018-05-27 20:57:27 -04:00
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2019-11-13 01:31:35 -05:00
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int spi_bdev_readblocks_raw(spi_bdev_t *bdev, uint8_t *dest, uint32_t block_num, uint32_t block_offset, uint32_t num_bytes) {
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uint32_t basepri = raise_irq_pri(IRQ_PRI_FLASH); // prevent cache flushing and USB access
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mp_spiflash_read(&bdev->spiflash, block_num * MP_SPIFLASH_ERASE_BLOCK_SIZE + block_offset, num_bytes, dest);
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restore_irq_pri(basepri);
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return 0;
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}
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int spi_bdev_writeblocks_raw(spi_bdev_t *bdev, const uint8_t *src, uint32_t block_num, uint32_t block_offset, uint32_t num_bytes) {
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uint32_t basepri = raise_irq_pri(IRQ_PRI_FLASH); // prevent cache flushing and USB access
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int ret = mp_spiflash_write(&bdev->spiflash, block_num * MP_SPIFLASH_ERASE_BLOCK_SIZE + block_offset, num_bytes, src);
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restore_irq_pri(basepri);
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return ret;
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}
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2018-05-27 20:57:27 -04:00
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#endif
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