2013-10-04 14:53:11 -04:00
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#define ASM_THUMB_PASS_1 (1)
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#define ASM_THUMB_PASS_2 (2)
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#define ASM_THUMB_PASS_3 (3)
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#define REG_R0 (0)
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#define REG_R1 (1)
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#define REG_R2 (2)
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#define REG_R3 (3)
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#define REG_R4 (4)
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#define REG_R5 (5)
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#define REG_R6 (6)
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#define REG_R7 (7)
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#define REG_R8 (8)
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#define REG_R9 (9)
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#define REG_R10 (10)
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#define REG_R11 (11)
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#define REG_R12 (12)
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#define REG_R13 (13)
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#define REG_R14 (14)
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#define REG_R15 (15)
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#define REG_LR (REG_R14)
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#define REG_RET REG_R0
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#define REG_ARG_1 REG_R0
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#define REG_ARG_2 REG_R1
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#define REG_ARG_3 REG_R2
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#define REG_ARG_4 REG_R3
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2013-11-03 08:58:19 -05:00
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#define THUMB_CC_EQ (0x0)
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#define THUMB_CC_NE (0x1)
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#define THUMB_CC_CS (0x2)
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#define THUMB_CC_CC (0x3)
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#define THUMB_CC_MI (0x4)
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#define THUMB_CC_PL (0x5)
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#define THUMB_CC_VS (0x6)
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#define THUMB_CC_VC (0x7)
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#define THUMB_CC_HI (0x8)
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#define THUMB_CC_LS (0x9)
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#define THUMB_CC_GE (0xa)
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#define THUMB_CC_LT (0xb)
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#define THUMB_CC_GT (0xc)
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#define THUMB_CC_LE (0xd)
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2013-10-04 14:53:11 -04:00
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typedef struct _asm_thumb_t asm_thumb_t;
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2013-10-05 13:41:24 -04:00
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asm_thumb_t *asm_thumb_new(uint max_num_labels);
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2013-10-04 14:53:11 -04:00
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void asm_thumb_free(asm_thumb_t *as, bool free_code);
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void asm_thumb_start_pass(asm_thumb_t *as, int pass);
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void asm_thumb_end_pass(asm_thumb_t *as);
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uint asm_thumb_get_code_size(asm_thumb_t *as);
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void *asm_thumb_get_code(asm_thumb_t *as);
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void asm_thumb_entry(asm_thumb_t *as, int num_locals);
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void asm_thumb_exit(asm_thumb_t *as);
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2014-04-10 09:11:31 -04:00
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void asm_thumb_label_assign(asm_thumb_t *as, uint label);
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2013-10-04 14:53:11 -04:00
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2014-04-21 08:33:15 -04:00
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void asm_thumb_align(asm_thumb_t* as, uint align);
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void asm_thumb_data(asm_thumb_t* as, uint bytesize, uint val);
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2013-10-04 14:53:11 -04:00
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// argument order follows ARM, in general dest is first
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2013-10-05 18:17:28 -04:00
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// note there is a difference between movw and mov.w, and many others!
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2013-10-04 14:53:11 -04:00
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2014-04-18 11:56:54 -04:00
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#define ASM_THUMB_OP_NOP (0xbf00)
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#define ASM_THUMB_OP_WFI (0xbf30)
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#define ASM_THUMB_OP_CPSID_I (0xb672) // cpsid i, disable irq
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#define ASM_THUMB_OP_CPSIE_I (0xb662) // cpsie i, enable irq
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void asm_thumb_op16(asm_thumb_t *as, uint op);
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void asm_thumb_op32(asm_thumb_t *as, uint op1, uint op2);
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2014-04-12 19:30:32 -04:00
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// FORMAT 2: add/subtract
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#define ASM_THUMB_FORMAT_2_ADD (0x1800)
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#define ASM_THUMB_FORMAT_2_SUB (0x1a00)
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#define ASM_THUMB_FORMAT_2_REG_OPERAND (0x0000)
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#define ASM_THUMB_FORMAT_2_IMM_OPERAND (0x0400)
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void asm_thumb_format_2(asm_thumb_t *as, uint op, uint rlo_dest, uint rlo_src, int src_b);
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static inline void asm_thumb_add_rlo_rlo_rlo(asm_thumb_t *as, uint rlo_dest, uint rlo_src_a, uint rlo_src_b)
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{ asm_thumb_format_2(as, ASM_THUMB_FORMAT_2_ADD | ASM_THUMB_FORMAT_2_REG_OPERAND, rlo_dest, rlo_src_a, rlo_src_b); }
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static inline void asm_thumb_add_rlo_rlo_i3(asm_thumb_t *as, uint rlo_dest, uint rlo_src_a, int i3_src)
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{ asm_thumb_format_2(as, ASM_THUMB_FORMAT_2_ADD | ASM_THUMB_FORMAT_2_IMM_OPERAND, rlo_dest, rlo_src_a, i3_src); }
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static inline void asm_thumb_sub_rlo_rlo_rlo(asm_thumb_t *as, uint rlo_dest, uint rlo_src_a, uint rlo_src_b)
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{ asm_thumb_format_2(as, ASM_THUMB_FORMAT_2_SUB | ASM_THUMB_FORMAT_2_REG_OPERAND, rlo_dest, rlo_src_a, rlo_src_b); }
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static inline void asm_thumb_sub_rlo_rlo_i3(asm_thumb_t *as, uint rlo_dest, uint rlo_src_a, int i3_src)
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{ asm_thumb_format_2(as, ASM_THUMB_FORMAT_2_SUB | ASM_THUMB_FORMAT_2_IMM_OPERAND, rlo_dest, rlo_src_a, i3_src); }
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// FORMAT 3: move/compare/add/subtract immediate
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// These instructions all do zero extension of the i8 value
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#define ASM_THUMB_FORMAT_3_MOV (0x2000)
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#define ASM_THUMB_FORMAT_3_CMP (0x2800)
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#define ASM_THUMB_FORMAT_3_ADD (0x3000)
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#define ASM_THUMB_FORMAT_3_SUB (0x3800)
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void asm_thumb_format_3(asm_thumb_t *as, uint op, uint rlo, int i8);
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static inline void asm_thumb_mov_rlo_i8(asm_thumb_t *as, uint rlo, int i8) { asm_thumb_format_3(as, ASM_THUMB_FORMAT_3_MOV, rlo, i8); }
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static inline void asm_thumb_cmp_rlo_i8(asm_thumb_t *as, uint rlo, int i8) { asm_thumb_format_3(as, ASM_THUMB_FORMAT_3_CMP, rlo, i8); }
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static inline void asm_thumb_add_rlo_i8(asm_thumb_t *as, uint rlo, int i8) { asm_thumb_format_3(as, ASM_THUMB_FORMAT_3_ADD, rlo, i8); }
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static inline void asm_thumb_sub_rlo_i8(asm_thumb_t *as, uint rlo, int i8) { asm_thumb_format_3(as, ASM_THUMB_FORMAT_3_SUB, rlo, i8); }
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// FORMAT 4: ALU operations
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#define ASM_THUMB_FORMAT_4_AND (0x4000)
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#define ASM_THUMB_FORMAT_4_EOR (0x4040)
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#define ASM_THUMB_FORMAT_4_LSL (0x4080)
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#define ASM_THUMB_FORMAT_4_LSR (0x40c0)
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#define ASM_THUMB_FORMAT_4_ASR (0x4100)
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#define ASM_THUMB_FORMAT_4_ADC (0x4140)
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#define ASM_THUMB_FORMAT_4_SBC (0x4180)
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#define ASM_THUMB_FORMAT_4_ROR (0x41c0)
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#define ASM_THUMB_FORMAT_4_TST (0x4200)
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#define ASM_THUMB_FORMAT_4_NEG (0x4240)
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#define ASM_THUMB_FORMAT_4_CMP (0x4280)
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#define ASM_THUMB_FORMAT_4_CMN (0x42c0)
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#define ASM_THUMB_FORMAT_4_ORR (0x4300)
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#define ASM_THUMB_FORMAT_4_MUL (0x4340)
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#define ASM_THUMB_FORMAT_4_BIC (0x4380)
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#define ASM_THUMB_FORMAT_4_MVN (0x43c0)
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void asm_thumb_format_4(asm_thumb_t *as, uint op, uint rlo_dest, uint rlo_src);
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static inline void asm_thumb_cmp_rlo_rlo(asm_thumb_t *as, uint rlo_dest, uint rlo_src) { asm_thumb_format_4(as, ASM_THUMB_FORMAT_4_CMP, rlo_dest, rlo_src); }
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// FORMAT 9: load/store with immediate offset
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// For word transfers the offset must be aligned, and >>2
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// FORMAT 10: load/store halfword
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// The offset must be aligned, and >>1
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// The load is zero extended into the register
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#define ASM_THUMB_FORMAT_9_STR (0x6000)
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#define ASM_THUMB_FORMAT_9_LDR (0x6800)
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#define ASM_THUMB_FORMAT_9_WORD_TRANSFER (0x0000)
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#define ASM_THUMB_FORMAT_9_BYTE_TRANSFER (0x1000)
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#define ASM_THUMB_FORMAT_10_STRH (0x8000)
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#define ASM_THUMB_FORMAT_10_LDRH (0x8800)
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void asm_thumb_format_9_10(asm_thumb_t *as, uint op, uint rlo_dest, uint rlo_base, uint offset);
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static inline void asm_thumb_str_rlo_rlo_i5(asm_thumb_t *as, uint rlo_src, uint rlo_base, uint word_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_9_STR | ASM_THUMB_FORMAT_9_WORD_TRANSFER, rlo_src, rlo_base, word_offset); }
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static inline void asm_thumb_strb_rlo_rlo_i5(asm_thumb_t *as, uint rlo_src, uint rlo_base, uint byte_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_9_STR | ASM_THUMB_FORMAT_9_BYTE_TRANSFER, rlo_src, rlo_base, byte_offset); }
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static inline void asm_thumb_ldr_rlo_rlo_i5(asm_thumb_t *as, uint rlo_dest, uint rlo_base, uint word_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_9_LDR | ASM_THUMB_FORMAT_9_WORD_TRANSFER, rlo_dest, rlo_base, word_offset); }
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static inline void asm_thumb_ldrb_rlo_rlo_i5(asm_thumb_t *as, uint rlo_dest, uint rlo_base, uint byte_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_9_LDR | ASM_THUMB_FORMAT_9_BYTE_TRANSFER , rlo_dest, rlo_base, byte_offset); }
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// TODO convert these to above format style
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void asm_thumb_mov_reg_reg(asm_thumb_t *as, uint reg_dest, uint reg_src);
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2013-10-05 18:17:28 -04:00
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void asm_thumb_movw_reg_i16(asm_thumb_t *as, uint reg_dest, int i16_src);
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void asm_thumb_movt_reg_i16(asm_thumb_t *as, uint reg_dest, int i16_src);
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2014-04-08 13:28:33 -04:00
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void asm_thumb_ite_ge(asm_thumb_t *as);
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2014-04-10 09:11:31 -04:00
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void asm_thumb_b_n(asm_thumb_t *as, uint label);
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void asm_thumb_bcc_n(asm_thumb_t *as, int cond, uint label);
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2013-10-04 14:53:11 -04:00
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2013-10-05 18:17:28 -04:00
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void asm_thumb_mov_reg_i32(asm_thumb_t *as, uint reg_dest, machine_uint_t i32_src); // convenience
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void asm_thumb_mov_reg_i32_optimised(asm_thumb_t *as, uint reg_dest, int i32_src); // convenience
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void asm_thumb_mov_local_reg(asm_thumb_t *as, int local_num_dest, uint rlo_src); // convenience
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void asm_thumb_mov_reg_local(asm_thumb_t *as, uint rlo_dest, int local_num); // convenience
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2013-11-03 09:25:43 -05:00
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void asm_thumb_mov_reg_local_addr(asm_thumb_t *as, uint rlo_dest, int local_num); // convenience
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2013-10-05 18:17:28 -04:00
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2014-04-10 09:11:31 -04:00
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void asm_thumb_b_label(asm_thumb_t *as, uint label); // convenience ?
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void asm_thumb_bcc_label(asm_thumb_t *as, int cc, uint label); // convenience: picks narrow or wide branch
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2013-10-05 18:17:28 -04:00
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void asm_thumb_bl_ind(asm_thumb_t *as, void *fun_ptr, uint fun_id, uint reg_temp); // convenience ?
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2013-10-04 14:53:11 -04:00
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