circuitpython/ports/stm32/boards/NUCLEO_L476RG/mpconfigboard.mk

MCU_SERIES = l4
CMSIS_MCU = STM32L476xx
AF_FILE = boards/stm32l476_af.csv
LD_FILES = boards/stm32l476xg.ld boards/common_basic.ld
OPENOCD_CONFIG = boards/openocd_stm32l4.cfg
stmhal: Add support for STM32 Nucleo64 L476RG. 2016-12-21 11:40:26 -05:00			`MCU_SERIES = l4`
			`CMSIS_MCU = STM32L476xx`
			`AF_FILE = boards/stm32l476_af.csv`
stm32/boards: Optimise flash and RAM allocation for L4 boards. Optimisations are: - Remove FLASH_ISR section since devices with a small flash sector erase size don't need special FLASH_ISR handling. This reduces flash image by approx 1.5k. - Make SRAM2 contiguous with SRAM1 where possible. - Simplify configuration of 2k RAM buffer used for flash filesystem. RAM changes with this commit: - L432: stack 6k -> 10k, bss + heap 42k -> 52k - L476: stack 16k -> 30k, bss + heap 80k -> 96k - L496: stack 206k -> 16k, bss + heap 112k -> 302k 2019-05-12 10:13:59 -04:00			`LD_FILES = boards/stm32l476xg.ld boards/common_basic.ld`
			`OPENOCD_CONFIG = boards/openocd_stm32l4.cfg`