249 lines
9.2 KiB
C
249 lines
9.2 KiB
C
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <string.h>
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "genhdr/pins.h"
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#include "qspi.h"
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#if defined(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2)
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void qspi_init(void) {
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// Configure pins
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mp_hal_pin_config(&MICROPY_HW_QSPIFLASH_CS, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, 10);
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mp_hal_pin_config(&MICROPY_HW_QSPIFLASH_SCK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, 9);
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mp_hal_pin_config(&MICROPY_HW_QSPIFLASH_IO0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, 9);
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mp_hal_pin_config(&MICROPY_HW_QSPIFLASH_IO1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, 9);
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mp_hal_pin_config(&MICROPY_HW_QSPIFLASH_IO2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, 9);
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mp_hal_pin_config(&MICROPY_HW_QSPIFLASH_IO3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, 9);
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// Bring up the QSPI peripheral
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__HAL_RCC_QSPI_CLK_ENABLE();
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QUADSPI->CR =
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2 << QUADSPI_CR_PRESCALER_Pos // F_CLK = F_AHB/3 (72MHz when CPU is 216MHz)
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#if defined(QUADSPI_CR_FSEL_Pos)
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| 0 << QUADSPI_CR_FSEL_Pos // FLASH 1 selected
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#endif
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#if defined(QUADSPI_CR_DFM_Pos)
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| 0 << QUADSPI_CR_DFM_Pos // dual-flash mode disabled
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#endif
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| 0 << QUADSPI_CR_SSHIFT_Pos // no sample shift
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| 1 << QUADSPI_CR_TCEN_Pos // timeout counter enabled
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| 1 << QUADSPI_CR_EN_Pos // enable the peripheral
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;
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QUADSPI->DCR =
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(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3 - 1) << QUADSPI_DCR_FSIZE_Pos
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| 1 << QUADSPI_DCR_CSHT_Pos // nCS stays high for 2 cycles
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| 0 << QUADSPI_DCR_CKMODE_Pos // CLK idles at low state
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;
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}
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void qspi_memory_map(void) {
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// Enable memory-mapped mode
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QUADSPI->ABR = 0; // disable continuous read mode
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QUADSPI->LPTR = 100; // to tune
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 3 << QUADSPI_CCR_FMODE_Pos // memory-mapped mode
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| 3 << QUADSPI_CCR_DMODE_Pos // data on 4 lines
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| 4 << QUADSPI_CCR_DCYC_Pos // 4 dummy cycles
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| 0 << QUADSPI_CCR_ABSIZE_Pos // 8-bit alternate byte
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| 3 << QUADSPI_CCR_ABMODE_Pos // alternate byte on 4 lines
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| 2 << QUADSPI_CCR_ADSIZE_Pos // 24-bit address size
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| 3 << QUADSPI_CCR_ADMODE_Pos // address on 4 lines
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| 0xeb << QUADSPI_CCR_INSTRUCTION_Pos // quad read opcode
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;
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}
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STATIC int qspi_ioctl(void *self_in, uint32_t cmd) {
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(void)self_in;
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switch (cmd) {
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case MP_QSPI_IOCTL_INIT:
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qspi_init();
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break;
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case MP_QSPI_IOCTL_BUS_RELEASE:
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// Switch to memory-map mode when bus is idle
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qspi_memory_map();
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break;
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}
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return 0; // success
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}
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STATIC void qspi_write_cmd_data(void *self_in, uint8_t cmd, size_t len, uint32_t data) {
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(void)self_in;
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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if (len == 0) {
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << QUADSPI_CCR_FMODE_Pos // indirect write mode
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| 0 << QUADSPI_CCR_DMODE_Pos // no data
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| 0 << QUADSPI_CCR_ADMODE_Pos // no address
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // write opcode
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;
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} else {
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QUADSPI->DLR = len - 1;
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << QUADSPI_CCR_FMODE_Pos // indirect write mode
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| 1 << QUADSPI_CCR_DMODE_Pos // data on 1 line
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| 0 << QUADSPI_CCR_ADMODE_Pos // no address
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // write opcode
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;
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// This assumes len==2
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*(uint16_t*)&QUADSPI->DR = data;
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}
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// Wait for write to finish
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while (!(QUADSPI->SR & QUADSPI_SR_TCF)) {
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}
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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}
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STATIC void qspi_write_cmd_addr_data(void *self_in, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) {
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(void)self_in;
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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if (len == 0) {
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << QUADSPI_CCR_FMODE_Pos // indirect write mode
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| 0 << QUADSPI_CCR_DMODE_Pos // no data
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| 2 << QUADSPI_CCR_ADSIZE_Pos // 24-bit address size
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| 1 << QUADSPI_CCR_ADMODE_Pos // address on 1 line
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // write opcode
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;
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QUADSPI->AR = addr;
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} else {
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QUADSPI->DLR = len - 1;
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << QUADSPI_CCR_FMODE_Pos // indirect write mode
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| 1 << QUADSPI_CCR_DMODE_Pos // data on 1 line
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| 2 << QUADSPI_CCR_ADSIZE_Pos // 24-bit address size
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| 1 << QUADSPI_CCR_ADMODE_Pos // address on 1 line
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // write opcode
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;
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QUADSPI->AR = addr;
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// Write out the data
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while (len) {
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while (!(QUADSPI->SR & QUADSPI_SR_FTF)) {
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}
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// TODO it seems that writes need to be 32-bit wide to start the xfer...
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//*(volatile uint8_t*)QUADSPI->DR = *src++;
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//--len;
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QUADSPI->DR = *(uint32_t*)src;
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src += 4;
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len -= 4;
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}
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}
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// Wait for write to finish
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while (!(QUADSPI->SR & QUADSPI_SR_TCF)) {
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}
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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}
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STATIC uint32_t qspi_read_cmd(void *self_in, uint8_t cmd, size_t len) {
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(void)self_in;
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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QUADSPI->DLR = len - 1; // number of bytes to read
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 1 << QUADSPI_CCR_FMODE_Pos // indirect read mode
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| 1 << QUADSPI_CCR_DMODE_Pos // data on 1 line
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| 0 << QUADSPI_CCR_ADMODE_Pos // no address
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // read opcode
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;
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// Wait for read to finish
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while (!(QUADSPI->SR & QUADSPI_SR_TCF)) {
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}
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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// Read result
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return QUADSPI->DR;
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}
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STATIC void qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) {
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(void)self_in;
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// This assumes that cmd=0xeb
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qspi_memory_map();
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memcpy(dest, (void*)(0x90000000 + addr), len);
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}
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const mp_qspi_proto_t qspi_proto = {
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.ioctl = qspi_ioctl,
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.write_cmd_data = qspi_write_cmd_data,
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.write_cmd_addr_data = qspi_write_cmd_addr_data,
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.read_cmd = qspi_read_cmd,
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.read_cmd_qaddr_qdata = qspi_read_cmd_qaddr_qdata,
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};
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#endif // defined(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2)
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