235 lines
6.7 KiB
Python
235 lines
6.7 KiB
Python
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"""NRF24L01 driver for Micro Python"""
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import pyb
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# nRF24L01+ registers
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CONFIG = const(0x00)
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EN_RXADDR = const(0x02)
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SETUP_AW = const(0x03)
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SETUP_RETR = const(0x04)
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RF_CH = const(0x05)
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RF_SETUP = const(0x06)
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STATUS = const(0x07)
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OBSERVE_TX = const(0x08)
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RX_ADDR_P0 = const(0x0a)
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TX_ADDR = const(0x10)
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RX_PW_P0 = const(0x11)
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FIFO_STATUS = const(0x17)
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DYNPD = const(0x1c)
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# CONFIG register
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EN_CRC = const(0x08) # enable CRC
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CRCO = const(0x04) # CRC encoding scheme; 0=1 byte, 1=2 bytes
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PWR_UP = const(0x02) # 1=power up, 0=power down
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PRIM_RX = const(0x01) # RX/TX control; 0=PTX, 1=PRX
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# RF_SETUP register
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POWER_0 = const(0x00) # -18 dBm
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POWER_1 = const(0x02) # -12 dBm
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POWER_2 = const(0x04) # -6 dBm
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POWER_3 = const(0x06) # 0 dBm
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SPEED_1M = const(0x00)
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SPEED_2M = const(0x08)
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SPEED_250K = const(0x20)
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# STATUS register
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RX_DR = const(0x40) # RX data ready; write 1 to clear
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TX_DS = const(0x20) # TX data sent; write 1 to clear
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MAX_RT = const(0x10) # max retransmits reached; write 1 to clear
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# FIFO_STATUS register
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RX_EMPTY = const(0x01) # 1 if RX FIFO is empty
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# constants for instructions
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R_RX_PL_WID = const(0x60) # read RX payload width
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R_RX_PAYLOAD = const(0x61) # read RX payload
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W_TX_PAYLOAD = const(0xa0) # write TX payload
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FLUSH_TX = const(0xe1) # flush TX FIFO
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FLUSH_RX = const(0xe2) # flush RX FIFO
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NOP = const(0xff) # use to read STATUS register
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class NRF24L01:
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def __init__(self, spi, cs, ce, channel=46, payload_size=16):
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assert payload_size <= 32
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# init the SPI bus and pins
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spi.init(spi.MASTER, baudrate=4000000, polarity=0, phase=1, firstbit=spi.MSB)
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cs.init(cs.OUT_PP, cs.PULL_NONE)
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ce.init(ce.OUT_PP, ce.PULL_NONE)
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# store the pins
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self.spi = spi
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self.cs = cs
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self.ce = ce
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# reset everything
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self.ce.low()
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self.cs.high()
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self.payload_size = payload_size
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self.pipe0_read_addr = None
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pyb.delay(5)
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# set address width to 5 bytes
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self.reg_write(SETUP_AW, 0b11)
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# disable dynamic payloads
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self.reg_write(DYNPD, 0)
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# auto retransmit delay: 1750us
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# auto retransmit count: 8
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self.reg_write(SETUP_RETR, (6 << 4) | 8)
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# set rf power and speed
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self.set_power_speed(POWER_3, SPEED_1M)
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# init CRC
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self.set_crc(2)
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# clear status flags
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self.reg_write(STATUS, RX_DR | TX_DS | MAX_RT)
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# set channel
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self.set_channel(channel)
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# flush buffers
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self.flush_rx()
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self.flush_tx()
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def reg_read(self, reg):
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self.cs.low()
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self.spi.send_recv(reg)
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buf = self.spi.recv(1)
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self.cs.high()
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return buf[0]
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def reg_read_ret_status(self, reg):
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self.cs.low()
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status = self.spi.send_recv(reg)[0]
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buf = self.spi.recv(1)
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self.cs.high()
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return status
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def reg_write(self, reg, buf):
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self.cs.low()
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status = self.spi.send_recv(0x20 | reg)[0]
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self.spi.send(buf)
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self.cs.high()
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return status
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def flush_rx(self):
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self.cs.low()
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self.spi.send(FLUSH_RX)
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self.cs.high()
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def flush_tx(self):
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self.cs.low()
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self.spi.send(FLUSH_TX)
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self.cs.high()
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# power is one of POWER_x defines; speed is one of SPEED_x defines
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def set_power_speed(self, power, speed):
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setup = self.reg_read(RF_SETUP) & 0b11010001
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self.reg_write(RF_SETUP, setup | power | speed)
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# length in bytes: 0, 1 or 2
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def set_crc(self, length):
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config = self.reg_read(CONFIG) & ~(CRCO | EN_CRC)
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if length == 0:
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pass
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elif length == 1:
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config |= EN_CRC
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else:
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config |= EN_CRC | CRCO
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self.reg_write(CONFIG, config)
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def set_channel(self, channel):
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self.reg_write(RF_CH, min(channel, 127))
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# address should be a bytes object 5 bytes long
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def open_tx_pipe(self, address):
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assert len(address) == 5
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self.reg_write(RX_ADDR_P0, address)
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self.reg_write(TX_ADDR, address)
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self.reg_write(RX_PW_P0, self.payload_size)
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# address should be a bytes object 5 bytes long
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# pipe 0 and 1 have 5 byte address
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# pipes 2-5 use same 4 most-significant bytes as pipe 1, plus 1 extra byte
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def open_rx_pipe(self, pipe_id, address):
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assert len(address) == 5
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assert 0 <= pipe_id <= 5
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if pipe_id == 0:
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self.pipe0_read_addr = address
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if pipe_id < 2:
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self.reg_write(RX_ADDR_P0 + pipe_id, address)
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else:
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self.reg_write(RX_ADDR_P0 + pipe_id, address[0])
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self.reg_write(RX_PW_P0 + pipe_id, self.payload_size)
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self.reg_write(EN_RXADDR, self.reg_read(EN_RXADDR) | (1 << pipe_id))
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def start_listening(self):
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self.reg_write(CONFIG, self.reg_read(CONFIG) | PWR_UP | PRIM_RX)
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self.reg_write(STATUS, RX_DR | TX_DS | MAX_RT)
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if self.pipe0_read_addr is not None:
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self.reg_write(RX_ADDR_P0, self.pipe0_read_addr)
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self.flush_rx()
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self.flush_tx()
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self.ce.high()
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pyb.udelay(130)
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def stop_listening(self):
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self.ce.low()
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self.flush_tx()
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self.flush_rx()
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# returns True if any data available to recv
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def any(self):
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return not bool(self.reg_read(FIFO_STATUS) & RX_EMPTY)
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def recv(self):
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# get the data
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self.cs.low()
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self.spi.send(R_RX_PAYLOAD)
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buf = self.spi.recv(self.payload_size)
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self.cs.high()
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# clear RX ready flag
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self.reg_write(STATUS, RX_DR)
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return buf
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def send(self, buf, timeout=500):
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# power up
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self.reg_write(CONFIG, (self.reg_read(CONFIG) | PWR_UP) & ~PRIM_RX)
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pyb.udelay(150)
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# send the data
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self.cs.low()
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self.spi.send(W_TX_PAYLOAD)
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self.spi.send(buf)
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if len(buf) < self.payload_size:
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self.spi.send(b'\x00' * (self.payload_size - len(buf))) # pad out data
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self.cs.high()
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# enable the chip so it can send the data
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self.ce.high()
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pyb.udelay(15) # needs to be >10us
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self.ce.low()
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# blocking wait for tx complete
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start = pyb.millis()
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while pyb.millis() - start < timeout:
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status = self.reg_read_ret_status(OBSERVE_TX)
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if status & (TX_DS | MAX_RT):
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break
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# get and clear all status flags
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status = self.reg_write(STATUS, RX_DR | TX_DS | MAX_RT)
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if not (status & TX_DS):
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raise OSError("send failed")
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# power down
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self.reg_write(CONFIG, self.reg_read(CONFIG) & ~PWR_UP)
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