2019-11-02 11:52:26 -04:00
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016 Scott Shawcroft
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* Copyright (c) 2019 Artur Pacholec
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "shared-bindings/busio/SPI.h"
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#include "py/mperrno.h"
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#include "py/runtime.h"
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#include "periph.h"
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#include "fsl_lpspi.h"
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#include <stdio.h>
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2020-05-01 10:06:40 -04:00
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//arrays use 0 based numbering: SPI1 is stored at index 0
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#define MAX_SPI 4
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STATIC bool reserved_spi[MAX_SPI];
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STATIC bool never_reset_spi[MAX_SPI];
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2019-11-02 11:52:26 -04:00
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2020-05-05 12:46:30 -04:00
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STATIC void config_periph_pin(const mcu_periph_obj_t *periph) {
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2019-11-02 11:52:26 -04:00
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IOMUXC_SetPinMux(
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periph->pin->mux_reg, periph->mux_mode,
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periph->input_reg, periph->input_idx,
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0,
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0);
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IOMUXC_SetPinConfig(0, 0, 0, 0,
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periph->pin->cfg_reg,
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IOMUXC_SW_PAD_CTL_PAD_HYS(0)
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| IOMUXC_SW_PAD_CTL_PAD_PUS(0)
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| IOMUXC_SW_PAD_CTL_PAD_PUE(0)
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| IOMUXC_SW_PAD_CTL_PAD_PKE(1)
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| IOMUXC_SW_PAD_CTL_PAD_ODE(0)
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| IOMUXC_SW_PAD_CTL_PAD_SPEED(2)
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| IOMUXC_SW_PAD_CTL_PAD_DSE(4)
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| IOMUXC_SW_PAD_CTL_PAD_SRE(0));
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}
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2020-02-26 09:28:54 -05:00
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#define LPSPI_MASTER_CLK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (CLOCK_GetDiv(kCLOCK_LpspiDiv)))
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2019-11-02 11:52:26 -04:00
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2020-05-01 10:06:40 -04:00
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void spi_reset(void) {
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for (int i = 0; i < MAX_SPI; i++) {
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reserved_spi[i] = false;
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}
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}
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2019-11-02 11:52:26 -04:00
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void common_hal_busio_spi_construct(busio_spi_obj_t *self,
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const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi,
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const mcu_pin_obj_t *miso) {
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2020-05-01 10:06:40 -04:00
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const uint32_t sck_count = MP_ARRAY_SIZE(mcu_spi_sck_list);
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const uint32_t miso_count = MP_ARRAY_SIZE(mcu_spi_miso_list);
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const uint32_t mosi_count = MP_ARRAY_SIZE(mcu_spi_mosi_list);
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bool spi_taken = false;
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2019-11-02 11:52:26 -04:00
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2020-05-01 10:06:40 -04:00
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for (uint i = 0; i < sck_count; i++) {
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if (mcu_spi_sck_list[i].pin != clock) {
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2019-11-02 11:52:26 -04:00
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continue;
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2020-05-01 10:06:40 -04:00
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}
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//if both MOSI and MISO exist, loop search normally
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if ((mosi != NULL) && (miso != NULL)) {
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for (uint j = 0; j < mosi_count; j++) {
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if ((mcu_spi_mosi_list[i].pin != mosi)
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|| (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)){
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2019-11-02 11:52:26 -04:00
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continue;
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2020-05-01 10:06:40 -04:00
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}
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for (uint k = 0; k < miso_count; k++) {
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if ((mcu_spi_miso_list[k].pin != miso) //everything needs the same index
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|| (mcu_spi_sck_list[i].bank_idx != mcu_spi_miso_list[k].bank_idx)) {
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continue;
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}
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//keep looking if the SPI is taken, edge case
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if (reserved_spi[mcu_spi_sck_list[i].bank_idx - 1]) {
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spi_taken = true;
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continue;
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}
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//store pins if not
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self->clock = &mcu_spi_sck_list[i];
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self->mosi = &mcu_spi_mosi_list[j];
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self->miso = &mcu_spi_miso_list[k];
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break;
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}
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if (self->clock != NULL) {
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break; // Multi-level break to pick lowest peripheral
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}
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}
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if (self->clock != NULL) {
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break;
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}
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// if just MISO, reduce search
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} else if (miso != NULL) {
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for (uint j = 0; j < miso_count; j++) {
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if ((mcu_spi_miso_list[j].pin != miso) //only SCK and MISO need the same index
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|| (mcu_spi_sck_list[i].bank_idx != mcu_spi_miso_list[j].bank_idx)) {
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2019-11-02 11:52:26 -04:00
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continue;
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2020-05-01 10:06:40 -04:00
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}
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if (reserved_spi[mcu_spi_sck_list[i].bank_idx - 1]) {
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spi_taken = true;
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continue;
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}
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self->clock = &mcu_spi_sck_list[i];
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self->mosi = NULL;
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self->miso = &mcu_spi_miso_list[j];
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break;
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}
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if (self->clock != NULL) {
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break;
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}
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// if just MOSI, reduce search
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} else if (mosi != NULL) {
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for (uint j = 0; j < mosi_count; j++) {
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if ((mcu_spi_mosi_list[j].pin != mosi) //only SCK and MOSI need the same index
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|| (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)) {
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continue;
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}
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if (reserved_spi[mcu_spi_sck_list[i].bank_idx - 1]) {
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spi_taken = true;
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continue;
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}
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self->clock = &mcu_spi_sck_list[i];
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self->mosi = &mcu_spi_mosi_list[j];
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self->miso = NULL;
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2019-11-02 11:52:26 -04:00
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break;
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}
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2020-05-01 10:06:40 -04:00
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if (self->clock != NULL) {
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break;
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}
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} else {
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//throw an error immediately
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mp_raise_ValueError(translate("Must provide MISO or MOSI pin"));
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2019-11-02 11:52:26 -04:00
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}
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}
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2020-05-01 10:06:40 -04:00
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if (self->clock != NULL && (self->mosi != NULL || self->miso != NULL)) {
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self->spi = mcu_spi_banks[self->clock->bank_idx - 1];
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2019-11-02 11:52:26 -04:00
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} else {
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2020-05-01 10:06:40 -04:00
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if (spi_taken) {
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mp_raise_ValueError(translate("Hardware busy, try alternative pins"));
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} else {
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mp_raise_ValueError(translate("Invalid SPI pin selection"));
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}
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2019-11-02 11:52:26 -04:00
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}
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2020-05-01 10:06:40 -04:00
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config_periph_pin(self->clock);
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if (self->mosi != NULL) {
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config_periph_pin(self->mosi);
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}
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if (self->miso != NULL) {
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config_periph_pin(self->miso);
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}
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reserved_spi[self->clock->bank_idx - 1] = true;
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2019-11-02 11:52:26 -04:00
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lpspi_master_config_t config = { 0 };
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LPSPI_MasterGetDefaultConfig(&config);
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// Always start at 250khz which is what SD cards need. They are sensitive to
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// SPI bus noise before they are put into SPI mode.
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config.baudRate = 250000;
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LPSPI_MasterInit(self->spi, &config, LPSPI_MASTER_CLK_FREQ);
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LPSPI_Enable(self->spi, false);
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uint32_t tcrPrescaleValue;
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self->baudrate = LPSPI_MasterSetBaudRate(self->spi, config.baudRate, LPSPI_MASTER_CLK_FREQ, &tcrPrescaleValue);
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LPSPI_Enable(self->spi, true);
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2020-05-01 10:06:40 -04:00
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claim_pin(self->clock->pin);
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if (self->mosi != NULL) {
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claim_pin(self->mosi->pin);
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}
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if (self->miso != NULL) {
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claim_pin(self->miso->pin);
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}
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2019-11-02 11:52:26 -04:00
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}
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void common_hal_busio_spi_never_reset(busio_spi_obj_t *self) {
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2020-05-01 10:06:40 -04:00
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// TODO
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2019-11-02 11:52:26 -04:00
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}
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bool common_hal_busio_spi_deinited(busio_spi_obj_t *self) {
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2020-05-01 10:06:40 -04:00
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return self->clock == NULL;
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2019-11-02 11:52:26 -04:00
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}
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void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
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if (common_hal_busio_spi_deinited(self)) {
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return;
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}
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2020-05-01 10:06:40 -04:00
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self->clock = NULL;
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2019-11-02 11:52:26 -04:00
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}
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bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
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uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
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2020-04-06 16:10:12 -04:00
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LPSPI_Enable(self->spi, false);
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uint32_t tcrPrescaleValue;
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self->baudrate = LPSPI_MasterSetBaudRate(self->spi, baudrate, LPSPI_MASTER_CLK_FREQ, &tcrPrescaleValue);
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LPSPI_Enable(self->spi, true);
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if ((polarity == common_hal_busio_spi_get_polarity(self)) &&
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(phase == common_hal_busio_spi_get_phase(self)) &&
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(bits == ((self->spi->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT)) + 1) {
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return true;
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}
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2019-11-02 11:52:26 -04:00
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lpspi_master_config_t config = { 0 };
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LPSPI_MasterGetDefaultConfig(&config);
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config.baudRate = baudrate;
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config.cpol = polarity;
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config.cpha = phase;
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config.bitsPerFrame = bits;
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LPSPI_Deinit(self->spi);
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LPSPI_MasterInit(self->spi, &config, LPSPI_MASTER_CLK_FREQ);
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return true;
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}
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bool common_hal_busio_spi_try_lock(busio_spi_obj_t *self) {
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bool grabbed_lock = false;
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// CRITICAL_SECTION_ENTER()
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if (!self->has_lock) {
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grabbed_lock = true;
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self->has_lock = true;
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}
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// CRITICAL_SECTION_LEAVE();
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return grabbed_lock;
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}
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bool common_hal_busio_spi_has_lock(busio_spi_obj_t *self) {
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return self->has_lock;
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}
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void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
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self->has_lock = false;
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}
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bool common_hal_busio_spi_write(busio_spi_obj_t *self,
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const uint8_t *data, size_t len) {
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if (len == 0) {
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return true;
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}
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2020-05-01 10:06:40 -04:00
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if (self->mosi == NULL) {
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mp_raise_ValueError(translate("No MOSI Pin"));
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}
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2019-11-02 11:52:26 -04:00
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lpspi_transfer_t xfer = { 0 };
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xfer.txData = (uint8_t*)data;
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xfer.dataSize = len;
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xfer.configFlags = kLPSPI_MasterPcs0;
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const status_t status = LPSPI_MasterTransferBlocking(self->spi, &xfer);
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if (status != kStatus_Success)
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printf("%s: status %ld\r\n", __func__, status);
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return (status == kStatus_Success);
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}
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bool common_hal_busio_spi_read(busio_spi_obj_t *self,
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uint8_t *data, size_t len, uint8_t write_value) {
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if (len == 0) {
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return true;
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}
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2020-05-01 10:06:40 -04:00
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if (self->miso == NULL) {
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mp_raise_ValueError(translate("No MISO Pin"));
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}
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2019-11-02 11:52:26 -04:00
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LPSPI_SetDummyData(self->spi, write_value);
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lpspi_transfer_t xfer = { 0 };
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xfer.rxData = data;
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xfer.dataSize = len;
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const status_t status = LPSPI_MasterTransferBlocking(self->spi, &xfer);
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if (status != kStatus_Success)
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printf("%s: status %ld\r\n", __func__, status);
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return (status == kStatus_Success);
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}
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bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, uint8_t *data_out, uint8_t *data_in, size_t len) {
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if (len == 0) {
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return true;
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}
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2020-05-01 10:06:40 -04:00
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if (self->miso == NULL || self->mosi == NULL) {
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mp_raise_ValueError(translate("Missing MISO or MOSI Pin"));
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}
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2019-11-02 11:52:26 -04:00
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LPSPI_SetDummyData(self->spi, 0xFF);
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lpspi_transfer_t xfer = { 0 };
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xfer.txData = data_out;
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xfer.rxData = data_in;
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xfer.dataSize = len;
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const status_t status = LPSPI_MasterTransferBlocking(self->spi, &xfer);
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if (status != kStatus_Success)
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printf("%s: status %ld\r\n", __func__, status);
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return (status == kStatus_Success);
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}
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uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) {
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return self->baudrate;
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}
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uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) {
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|
return ((self->spi->TCR & LPSPI_TCR_CPHA_MASK) == LPSPI_TCR_CPHA_MASK);
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}
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uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) {
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return ((self->spi->TCR & LPSPI_TCR_CPOL_MASK) == LPSPI_TCR_CPOL_MASK);
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}
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