502 lines
23 KiB
C
502 lines
23 KiB
C
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/**
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******************************************************************************
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* @file stm32f4xx_hal_dma2d.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 18-February-2014
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* @brief Header file of DMA2D HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_HAL_DMA2D_H
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#define __STM32F4xx_HAL_DMA2D_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal_def.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup DMA2D
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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#define MAX_DMA2D_LAYER 2
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/**
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* @brief DMA2D color Structure definition
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*/
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typedef struct
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{
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uint32_t Blue; /*!< Configures the blue value.
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This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
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uint32_t Green; /*!< Configures the green value.
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This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
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uint32_t Red; /*!< Configures the red value.
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This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
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} DMA2D_ColorTypeDef;
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/**
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* @brief DMA2D CLUT Structure definition
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*/
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typedef struct
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{
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uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address. */
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uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
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This parameter can be one value of @ref DMA2D_CLUT_CM */
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uint32_t Size; /*!< configures the DMA2D CLUT size.
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This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
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} DMA2D_CLUTCfgTypeDef;
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/**
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* @brief DMA2D Init structure definition
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*/
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typedef struct
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{
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uint32_t Mode; /*!< configures the DMA2D transfer mode.
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This parameter can be one value of @ref DMA2D_Mode */
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uint32_t ColorMode; /*!< configures the color format of the output image.
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This parameter can be one value of @ref DMA2D_Color_Mode */
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uint32_t OutputOffset; /*!< Specifies the Offset value.
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
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} DMA2D_InitTypeDef;
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/**
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* @brief DMA2D Layer structure definition
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*/
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typedef struct
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{
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uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
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uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
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This parameter can be one value of @ref DMA2D_Input_Color_Mode */
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uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
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This parameter can be one value of @ref DMA2D_ALPHA_MODE */
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uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value
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This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
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} DMA2D_LayerCfgTypeDef;
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/**
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* @brief HAL DMA2D State structures definition
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*/
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typedef enum
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{
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HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
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HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
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HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
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HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
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HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
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HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
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}HAL_DMA2D_StateTypeDef;
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/**
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* @brief DMA2D handle Structure definition
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*/
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typedef struct __DMA2D_HandleTypeDef
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{
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DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
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DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
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void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
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void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
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DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
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HAL_LockTypeDef Lock; /*!< DMA2D Lock */
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__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
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__IO uint32_t ErrorCode; /*!< DMA2D Error code */
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} DMA2D_HandleTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup DMA2D_Exported_Constants
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* @{
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*/
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/** @defgroup DMA2D_Layer
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* @{
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*/
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#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
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/**
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* @}
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*/
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/** @defgroup DMA2D_Error_Code
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* @{
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*/
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#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
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#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
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#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
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#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
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/**
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* @}
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*/
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/** @defgroup DMA2D_Mode
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* @{
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*/
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#define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
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#define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
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#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
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#define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
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#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
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((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
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/**
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* @}
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*/
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/** @defgroup DMA2D_Color_Mode
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* @{
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*/
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#define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
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#define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */
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#define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
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#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
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#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
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#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
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((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
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((MODE_ARGB) == DMA2D_ARGB4444))
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/**
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* @}
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*/
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/** @defgroup DMA2D_COLOR_VALUE
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* @{
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*/
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#define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
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#define IS_DMA2D_ALPHA_VALUE(ALPHA_VALUE) ((ALPHA_VALUE) <= COLOR_VALUE)
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#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
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/**
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* @}
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*/
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/** @defgroup DMA2D_SIZE
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* @{
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*/
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#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
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#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
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#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
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#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
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/**
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* @}
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*/
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/** @defgroup DMA2D_OFFSET
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* @{
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*/
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#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
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#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
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/**
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* @}
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*/
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/** @defgroup DMA2D_Input_Color_Mode
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* @{
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*/
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#define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
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#define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */
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#define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */
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#define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */
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#define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */
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#define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */
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#define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */
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#define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */
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#define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
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#define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
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#define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
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#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
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((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
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((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
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((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
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((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
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((INPUT_CM) == CM_A4))
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/**
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* @}
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*/
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/** @defgroup DMA2D_ALPHA_MODE
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* @{
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*/
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#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
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#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
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#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
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with original alpha channel value */
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#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
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((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
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((AlphaMode) == DMA2D_COMBINE_ALPHA))
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/**
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* @}
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*/
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/** @defgroup DMA2D_CLUT_CM
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* @{
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*/
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#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
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#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
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#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
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/**
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* @}
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*/
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/** @defgroup DMA2D_CLUT_SIZE
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* @{
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*/
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#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
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#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
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/**
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* @}
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*/
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/** @defgroup DMA2D_DeadTime
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* @{
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*/
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#define LINE_WATERMARK DMA2D_LWR_LW
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#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
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/**
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* @}
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*/
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/** @defgroup DMA2D_Interrupts
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* @{
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*/
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#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
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#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */
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#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */
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#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
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#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
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#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
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#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
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((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
|
||
|
|
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup DMA2D_Flag
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
|
||
|
|
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */
|
||
|
|
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */
|
||
|
|
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
|
||
|
|
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
|
||
|
|
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
|
||
|
|
|
||
|
|
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
|
||
|
|
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
|
||
|
|
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/* Exported macro ------------------------------------------------------------*/
|
||
|
|
/**
|
||
|
|
* @brief Enable the DMA2D.
|
||
|
|
* @param __HANDLE__: DMA2D handle
|
||
|
|
* @retval None.
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable the DMA2D.
|
||
|
|
* @param __HANDLE__: DMA2D handle
|
||
|
|
* @retval None.
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
|
||
|
|
|
||
|
|
/* Interrupt & Flag management */
|
||
|
|
/**
|
||
|
|
* @brief Get the DMA2D pending flags.
|
||
|
|
* @param __HANDLE__: DMA2D handle
|
||
|
|
* @param __FLAG__: Get the specified flag.
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg DMA2D_FLAG_CE: Configuration error flag
|
||
|
|
* @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
|
||
|
|
* @arg DMA2D_FLAG_CAE: C-LUT access error flag
|
||
|
|
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
|
||
|
|
* @arg DMA2D_FLAG_TC: Transfer complete flag
|
||
|
|
* @arg DMA2D_FLAG_TE: Transfer error flag
|
||
|
|
* @retval The state of FLAG.
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clears the DMA2D pending flags.
|
||
|
|
* @param __HANDLE__: DMA2D handle
|
||
|
|
* @param __FLAG__: specifies the flag to clear.
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg DMA2D_FLAG_CE: Configuration error flag
|
||
|
|
* @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
|
||
|
|
* @arg DMA2D_FLAG_CAE: C-LUT access error flag
|
||
|
|
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
|
||
|
|
* @arg DMA2D_FLAG_TC: Transfer complete flag
|
||
|
|
* @arg DMA2D_FLAG_TE: Transfer error flag
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR |= (__FLAG__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enables the specified DMA2D interrupts.
|
||
|
|
* @param __HANDLE__: DMA2D handle
|
||
|
|
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg DMA2D_IT_CE: Configuration error interrupt mask
|
||
|
|
* @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
|
||
|
|
* @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
|
||
|
|
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
|
||
|
|
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
|
||
|
|
* @arg DMA2D_IT_TE: Transfer error interrupt mask
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disables the specified DMA2D interrupts.
|
||
|
|
* @param __HANDLE__: DMA2D handle
|
||
|
|
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg DMA2D_IT_CE: Configuration error interrupt mask
|
||
|
|
* @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
|
||
|
|
* @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
|
||
|
|
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
|
||
|
|
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
|
||
|
|
* @arg DMA2D_IT_TE: Transfer error interrupt mask
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Checks whether the specified DMA2D interrupt has occurred or not.
|
||
|
|
* @param __HANDLE__: DMA2D handle
|
||
|
|
* @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg DMA2D_IT_CE: Configuration error interrupt mask
|
||
|
|
* @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
|
||
|
|
* @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
|
||
|
|
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
|
||
|
|
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
|
||
|
|
* @arg DMA2D_IT_TE: Transfer error interrupt mask
|
||
|
|
* @retval The state of INTERRUPT.
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
|
||
|
|
|
||
|
|
/* Exported functions --------------------------------------------------------*/
|
||
|
|
|
||
|
|
/* Initialization and de-initialization functions *******************************/
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
|
||
|
|
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
|
||
|
|
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
|
||
|
|
|
||
|
|
/* IO operation functions *******************************************************/
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
|
||
|
|
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
|
||
|
|
|
||
|
|
/* Peripheral Control functions *************************************************/
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||
|
|
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
|
||
|
|
|
||
|
|
/* Peripheral State functions ***************************************************/
|
||
|
|
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
|
||
|
|
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
||
|
|
|
||
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __STM32F4xx_HAL_DMA2D_H */
|
||
|
|
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|