2015-07-27 20:20:56 -04:00
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/**
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******************************************************************************
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* @file stm32f7xx_hal_uart.h
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* @author MCD Application Team
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2016-12-05 01:04:56 -05:00
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* @version V1.1.2
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* @date 23-September-2016
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2015-07-27 20:20:56 -04:00
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* @brief Header file of UART HAL module.
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******************************************************************************
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* @attention
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*
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2016-12-05 01:04:56 -05:00
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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2015-07-27 20:20:56 -04:00
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F7xx_HAL_UART_H
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#define __STM32F7xx_HAL_UART_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_hal_def.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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/** @addtogroup UART
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup UART_Exported_Types UART Exported Types
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* @{
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*/
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/**
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* @brief UART Init Structure definition
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*/
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typedef struct
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{
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uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
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The baud rate register is computed using the following formula:
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- If oversampling is 16 or in LIN mode,
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Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
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- If oversampling is 8,
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Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
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Baud Rate Register[3] = 0
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Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
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uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
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This parameter can be a value of @ref UARTEx_Word_Length */
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uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
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This parameter can be a value of @ref UART_Stop_Bits */
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uint32_t Parity; /*!< Specifies the parity mode.
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This parameter can be a value of @ref UART_Parity
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@note When parity is enabled, the computed parity is inserted
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at the MSB position of the transmitted data (9th bit when
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the word length is set to 9 data bits; 8th bit when the
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word length is set to 8 data bits). */
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uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
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This parameter can be a value of @ref UART_Mode */
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uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
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or disabled.
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This parameter can be a value of @ref UART_Hardware_Flow_Control */
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uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
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This parameter can be a value of @ref UART_Over_Sampling */
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uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
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Selecting the single sample method increases the receiver tolerance to clock
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deviations. This parameter can be a value of @ref UART_OneBit_Sampling */
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}UART_InitTypeDef;
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/**
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* @brief UART Advanced Features initialization structure definition
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*/
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typedef struct
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{
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uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
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Advanced Features may be initialized at the same time .
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This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */
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uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
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This parameter can be a value of @ref UART_Tx_Inv */
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uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
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This parameter can be a value of @ref UART_Rx_Inv */
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uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
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vs negative/inverted logic).
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This parameter can be a value of @ref UART_Data_Inv */
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uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
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This parameter can be a value of @ref UART_Rx_Tx_Swap */
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uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
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This parameter can be a value of @ref UART_Overrun_Disable */
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uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
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This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */
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uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
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This parameter can be a value of @ref UART_AutoBaudRate_Enable */
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uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
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detection is carried out.
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This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */
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uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
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This parameter can be a value of @ref UART_MSB_First */
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} UART_AdvFeatureInitTypeDef;
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/**
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* @brief HAL UART State structures definition
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* @note HAL UART State value is a combination of 2 different substates: gState and RxState.
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* - gState contains UART state information related to global Handle management
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* and also information related to Tx operations.
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* gState value coding follow below described bitmap :
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* b7-b6 Error information
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* 00 : No Error
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* 01 : (Not Used)
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* 10 : Timeout
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* 11 : Error
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* b5 IP initilisation status
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* 0 : Reset (IP not initialized)
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* 1 : Init done (IP not initialized. HAL UART Init function already called)
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* b4-b3 (not used)
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* xx : Should be set to 00
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* b2 Intrinsic process state
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* 0 : Ready
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* 1 : Busy (IP busy with some configuration or internal operations)
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* b1 (not used)
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* x : Should be set to 0
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* b0 Tx state
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* 0 : Ready (no Tx operation ongoing)
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* 1 : Busy (Tx operation ongoing)
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* - RxState contains information related to Rx operations.
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* RxState value coding follow below described bitmap :
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* b7-b6 (not used)
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* xx : Should be set to 00
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* b5 IP initilisation status
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* 0 : Reset (IP not initialized)
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* 1 : Init done (IP not initialized)
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* b4-b2 (not used)
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* xxx : Should be set to 000
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* b1 Rx state
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* 0 : Ready (no Rx operation ongoing)
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* 1 : Busy (Rx operation ongoing)
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* b0 (not used)
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* x : Should be set to 0.
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*/
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typedef enum
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{
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HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
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Value is allowed for gState and RxState */
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HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
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Value is allowed for gState and RxState */
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HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
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Value is allowed for gState only */
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HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
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Value is allowed for gState only */
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HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
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Value is allowed for RxState only */
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HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
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Not to be used for neither gState nor RxState.
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Value is result of combination (Or) between gState and RxState values */
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HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
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Value is allowed for gState only */
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HAL_UART_STATE_ERROR = 0xE0U /*!< Error
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Value is allowed for gState only */
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}HAL_UART_StateTypeDef;
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/**
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* @brief UART clock sources definition
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*/
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typedef enum
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{
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UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
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UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
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UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
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UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
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UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
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UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
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}UART_ClockSourceTypeDef;
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/**
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* @brief UART handle Structure definition
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*/
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typedef struct
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{
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USART_TypeDef *Instance; /*!< UART registers base address */
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UART_InitTypeDef Init; /*!< UART communication parameters */
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UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
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uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
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uint16_t TxXferSize; /*!< UART Tx Transfer size */
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__IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
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uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
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uint16_t RxXferSize; /*!< UART Rx Transfer size */
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__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
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uint16_t Mask; /*!< UART Rx RDR register mask */
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DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
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DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
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HAL_LockTypeDef Lock; /*!< Locking object */
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__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
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and also related to Tx operations.
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This parameter can be a value of @ref HAL_UART_StateTypeDef */
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__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
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This parameter can be a value of @ref HAL_UART_StateTypeDef */
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__IO uint32_t ErrorCode; /*!< UART Error code */
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}UART_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup UART_Exported_Constants UART Exported Constants
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* @{
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*/
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/** @defgroup UART_Error_Definition UART Error Definition
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* @{
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*/
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#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
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#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
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#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
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#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
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#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
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#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
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/**
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* @}
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*/
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/** @defgroup UART_Stop_Bits UART Number of Stop Bits
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* @{
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*/
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#define UART_STOPBITS_1 ((uint32_t)0x00000000U)
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#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
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/**
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* @}
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*/
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/** @defgroup UART_Parity UART Parity
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* @{
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*/
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#define UART_PARITY_NONE ((uint32_t)0x00000000U)
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#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
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#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
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/**
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* @}
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*/
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/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
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* @{
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*/
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#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U)
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#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
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#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
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#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
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/**
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* @}
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*/
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/** @defgroup UART_Mode UART Transfer Mode
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* @{
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*/
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#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
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#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
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#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
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/**
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* @}
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*/
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/** @defgroup UART_State UART State
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* @{
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*/
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#define UART_STATE_DISABLE ((uint32_t)0x00000000U)
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#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
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/**
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* @}
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*/
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/** @defgroup UART_Over_Sampling UART Over Sampling
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* @{
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*/
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2016-12-05 01:04:56 -05:00
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#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
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2015-07-27 20:20:56 -04:00
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#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
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/**
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* @}
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*/
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/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
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* @{
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*/
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2016-12-05 01:04:56 -05:00
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#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
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2015-07-27 20:20:56 -04:00
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#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
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/**
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* @}
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*/
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/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
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* @{
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*/
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2016-12-05 01:04:56 -05:00
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#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000U)
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2015-07-27 20:20:56 -04:00
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#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
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#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
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#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)
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/**
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|
* @}
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*/
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/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
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* @{
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*/
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2016-12-05 01:04:56 -05:00
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#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U)
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2015-07-27 20:20:56 -04:00
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#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
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/**
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|
* @}
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*/
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/** @defgroup UART_LIN UART Local Interconnection Network mode
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* @{
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*/
|
2016-12-05 01:04:56 -05:00
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#define UART_LIN_DISABLE ((uint32_t)0x00000000U)
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2015-07-27 20:20:56 -04:00
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#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)
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/**
|
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|
* @}
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|
*/
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/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
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* @{
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*/
|
2016-12-05 01:04:56 -05:00
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#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)
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2015-07-27 20:20:56 -04:00
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#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
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/**
|
|
|
|
* @}
|
|
|
|
*/
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/** @defgroup UART_DMA_Tx UART DMA Tx
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* @{
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|
*/
|
2016-12-05 01:04:56 -05:00
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|
#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
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|
#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
|
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|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
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/** @defgroup UART_DMA_Rx UART DMA Rx
|
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|
* @{
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|
*/
|
2016-12-05 01:04:56 -05:00
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|
#define UART_DMA_RX_DISABLE ((uint32_t)0x0000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
|
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|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
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|
|
/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
|
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|
|
* @{
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|
|
*/
|
2016-12-05 01:04:56 -05:00
|
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|
#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)
|
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|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
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|
|
/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
|
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|
|
* @{
|
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|
|
*/
|
2016-12-05 01:04:56 -05:00
|
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|
#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
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|
|
/** @defgroup UART_Request_Parameters UART Request Parameters
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
|
|
|
|
#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
|
|
|
|
#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
|
|
|
|
#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
|
|
|
|
#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U)
|
|
|
|
#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U)
|
|
|
|
#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U)
|
|
|
|
#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U)
|
|
|
|
#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U)
|
|
|
|
#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U)
|
|
|
|
#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U)
|
|
|
|
#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U)
|
|
|
|
#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U)
|
2015-07-27 20:20:56 -04:00
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U)
|
2015-07-27 20:20:56 -04:00
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U)
|
2015-07-27 20:20:56 -04:00
|
|
|
#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U)
|
2015-07-27 20:20:56 -04:00
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U)
|
2015-07-27 20:20:56 -04:00
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_IT_MASK ((uint32_t)0x001FU)
|
2015-07-27 20:20:56 -04:00
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU
|
2015-07-27 20:20:56 -04:00
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Flags UART Status Flags
|
|
|
|
* Elements values convention: 0xXXXX
|
|
|
|
* - 0xXXXX : Flag mask in the ISR register
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_FLAG_TEACK ((uint32_t)0x00200000U)
|
|
|
|
#define UART_FLAG_SBKF ((uint32_t)0x00040000U)
|
|
|
|
#define UART_FLAG_CMF ((uint32_t)0x00020000U)
|
|
|
|
#define UART_FLAG_BUSY ((uint32_t)0x00010000U)
|
|
|
|
#define UART_FLAG_ABRF ((uint32_t)0x00008000U)
|
|
|
|
#define UART_FLAG_ABRE ((uint32_t)0x00004000U)
|
|
|
|
#define UART_FLAG_EOBF ((uint32_t)0x00001000U)
|
|
|
|
#define UART_FLAG_RTOF ((uint32_t)0x00000800U)
|
|
|
|
#define UART_FLAG_CTS ((uint32_t)0x00000400U)
|
|
|
|
#define UART_FLAG_CTSIF ((uint32_t)0x00000200U)
|
|
|
|
#define UART_FLAG_LBDF ((uint32_t)0x00000100U)
|
|
|
|
#define UART_FLAG_TXE ((uint32_t)0x00000080U)
|
|
|
|
#define UART_FLAG_TC ((uint32_t)0x00000040U)
|
|
|
|
#define UART_FLAG_RXNE ((uint32_t)0x00000020U)
|
|
|
|
#define UART_FLAG_IDLE ((uint32_t)0x00000010U)
|
|
|
|
#define UART_FLAG_ORE ((uint32_t)0x00000008U)
|
|
|
|
#define UART_FLAG_NE ((uint32_t)0x00000004U)
|
|
|
|
#define UART_FLAG_FE ((uint32_t)0x00000002U)
|
|
|
|
#define UART_FLAG_PE ((uint32_t)0x00000001U)
|
2015-07-27 20:20:56 -04:00
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @defgroup UART_Interrupt_definition UART Interrupts Definition
|
|
|
|
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
|
|
|
* - YYYYY : Interrupt source position in the XX register (5bits)
|
|
|
|
* - XX : Interrupt source register (2bits)
|
|
|
|
* - 01: CR1 register
|
|
|
|
* - 10: CR2 register
|
|
|
|
* - 11: CR3 register
|
|
|
|
* - ZZZZ : Flag position in the ISR register(4bits)
|
|
|
|
* @{
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_IT_PE ((uint32_t)0x0028U)
|
|
|
|
#define UART_IT_TXE ((uint32_t)0x0727U)
|
|
|
|
#define UART_IT_TC ((uint32_t)0x0626U)
|
|
|
|
#define UART_IT_RXNE ((uint32_t)0x0525U)
|
|
|
|
#define UART_IT_IDLE ((uint32_t)0x0424U)
|
|
|
|
#define UART_IT_LBD ((uint32_t)0x0846U)
|
|
|
|
#define UART_IT_CTS ((uint32_t)0x096AU)
|
|
|
|
#define UART_IT_CM ((uint32_t)0x112EU)
|
2015-07-27 20:20:56 -04:00
|
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/** Elements values convention: 000000000XXYYYYYb
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* - YYYYY : Interrupt source position in the XX register (5bits)
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* - XX : Interrupt source register (2bits)
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* - 01: CR1 register
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* - 10: CR2 register
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* - 11: CR3 register
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*/
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2016-12-05 01:04:56 -05:00
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#define UART_IT_ERR ((uint32_t)0x0060U)
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2015-07-27 20:20:56 -04:00
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/** Elements values convention: 0000ZZZZ00000000b
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* - ZZZZ : Flag position in the ISR register(4bits)
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*/
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2016-12-05 01:04:56 -05:00
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#define UART_IT_ORE ((uint32_t)0x0300U)
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#define UART_IT_NE ((uint32_t)0x0200U)
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#define UART_IT_FE ((uint32_t)0x0100U)
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2015-07-27 20:20:56 -04:00
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/**
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* @}
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*/
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/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
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* @{
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*/
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#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
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#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
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#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
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#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
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#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
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#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
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#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
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#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
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#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
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#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
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#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macros -----------------------------------------------------------*/
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/** @defgroup UART_Exported_Macros UART Exported Macros
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* @{
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*/
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/** @brief Reset UART handle state
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* @param __HANDLE__: UART handle.
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* @retval None
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*/
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2016-12-05 01:04:56 -05:00
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#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
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(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
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(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
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} while(0)
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2015-07-27 20:20:56 -04:00
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/** @brief Flush the UART Data registers
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* @param __HANDLE__: specifies the UART Handle.
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*/
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#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
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do{ \
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SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
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SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
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} while(0)
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/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag.
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* @param __HANDLE__: specifies the UART Handle.
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* @param __FLAG__: specifies the interrupt clear register flag that needs to be set
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* to clear the corresponding interrupt
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* This parameter can be one of the following values:
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* @arg UART_CLEAR_PEF: Parity Error Clear Flag
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* @arg UART_CLEAR_FEF: Framing Error Clear Flag
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* @arg UART_CLEAR_NEF: Noise detected Clear Flag
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* @arg UART_CLEAR_OREF: OverRun Error Clear Flag
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* @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
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* @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
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* @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
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* @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
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* @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
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* @arg UART_CLEAR_EOBF: End Of Block Clear Flag
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* @arg UART_CLEAR_CMF: Character Match Clear Flag
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* @retval None
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*/
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2016-12-05 01:04:56 -05:00
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#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))
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2015-07-27 20:20:56 -04:00
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/** @brief Clear the UART PE pending flag.
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* @param __HANDLE__: specifies the UART Handle.
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* @retval None
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*/
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#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)
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/** @brief Clear the UART FE pending flag.
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* @param __HANDLE__: specifies the UART Handle.
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* @retval None
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*/
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#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)
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/** @brief Clear the UART NE pending flag.
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* @param __HANDLE__: specifies the UART Handle.
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* @retval None
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*/
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#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)
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/** @brief Clear the UART ORE pending flag.
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* @param __HANDLE__: specifies the UART Handle.
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* @retval None
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*/
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#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)
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/** @brief Clear the UART IDLE pending flag.
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* @param __HANDLE__: specifies the UART Handle.
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* @retval None
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*/
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#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)
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/** @brief Checks whether the specified UART flag is set or not.
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* @param __HANDLE__: specifies the UART Handle.
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* @param __FLAG__: specifies the flag to check.
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* This parameter can be one of the following values:
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* @arg UART_FLAG_REACK: Receive enable acknowledge flag
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* @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
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* @arg UART_FLAG_WUF: Wake up from stop mode flag
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* @arg UART_FLAG_RWU: Receiver wake up flag (is the UART in mute mode)
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* @arg UART_FLAG_SBKF: Send Break flag
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* @arg UART_FLAG_CMF: Character match flag
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* @arg UART_FLAG_BUSY: Busy flag
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* @arg UART_FLAG_ABRF: Auto Baud rate detection flag
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* @arg UART_FLAG_ABRE: Auto Baud rate detection error flag
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* @arg UART_FLAG_EOBF: End of block flag
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* @arg UART_FLAG_RTOF: Receiver timeout flag
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* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
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* @arg UART_FLAG_LBD: LIN Break detection flag
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* @arg UART_FLAG_TXE: Transmit data register empty flag
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* @arg UART_FLAG_TC: Transmission Complete flag
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* @arg UART_FLAG_RXNE: Receive data register not empty flag
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* @arg UART_FLAG_IDLE: Idle Line detection flag
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* @arg UART_FLAG_ORE: OverRun Error flag
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* @arg UART_FLAG_NE: Noise Error flag
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* @arg UART_FLAG_FE: Framing Error flag
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* @arg UART_FLAG_PE: Parity Error flag
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* @retval The new state of __FLAG__ (TRUE or FALSE).
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*/
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#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
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/** @brief Enables the specified UART interrupt.
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* @param __HANDLE__: specifies the UART Handle.
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* @param __INTERRUPT__: specifies the UART interrupt source to enable.
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* This parameter can be one of the following values:
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* @arg UART_IT_WUF: Wakeup from stop mode interrupt
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* @arg UART_IT_CM: Character match interrupt
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* @arg UART_IT_CTS: CTS change interrupt
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* @arg UART_IT_LBD: LIN Break detection interrupt
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* @arg UART_IT_TXE: Transmit Data Register empty interrupt
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* @arg UART_IT_TC: Transmission complete interrupt
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* @arg UART_IT_RXNE: Receive Data register not empty interrupt
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* @arg UART_IT_IDLE: Idle line detection interrupt
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* @arg UART_IT_PE: Parity Error interrupt
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* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
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* @retval None
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*/
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#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
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((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
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((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
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/** @brief Disables the specified UART interrupt.
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* @param __HANDLE__: specifies the UART Handle.
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* @param __INTERRUPT__: specifies the UART interrupt source to disable.
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* This parameter can be one of the following values:
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* @arg UART_IT_CM: Character match interrupt
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* @arg UART_IT_CTS: CTS change interrupt
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* @arg UART_IT_LBD: LIN Break detection interrupt
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* @arg UART_IT_TXE: Transmit Data Register empty interrupt
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* @arg UART_IT_TC: Transmission complete interrupt
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* @arg UART_IT_RXNE: Receive Data register not empty interrupt
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* @arg UART_IT_IDLE: Idle line detection interrupt
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* @arg UART_IT_PE: Parity Error interrupt
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* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
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* @retval None
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*/
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#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
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((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
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((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
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/** @brief Checks whether the specified UART interrupt has occurred or not.
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* @param __HANDLE__: specifies the UART Handle.
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* @param __IT__: specifies the UART interrupt to check.
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* This parameter can be one of the following values:
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* @arg UART_IT_CM: Character match interrupt
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* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
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* @arg UART_IT_LBD: LIN Break detection interrupt
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* @arg UART_IT_TXE: Transmit Data Register empty interrupt
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* @arg UART_IT_TC: Transmission complete interrupt
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* @arg UART_IT_RXNE: Receive Data register not empty interrupt
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* @arg UART_IT_IDLE: Idle line detection interrupt
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* @arg UART_IT_ORE: OverRun Error interrupt
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* @arg UART_IT_NE: Noise Error interrupt
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* @arg UART_IT_FE: Framing Error interrupt
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* @arg UART_IT_PE: Parity Error interrupt
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* @retval The new state of __IT__ (TRUE or FALSE).
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*/
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#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
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/** @brief Checks whether the specified UART interrupt source is enabled.
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* @param __HANDLE__: specifies the UART Handle.
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* @param __IT__: specifies the UART interrupt source to check.
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* This parameter can be one of the following values:
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* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
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* @arg UART_IT_LBD: LIN Break detection interrupt
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* @arg UART_IT_TXE: Transmit Data Register empty interrupt
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* @arg UART_IT_TC: Transmission complete interrupt
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* @arg UART_IT_RXNE: Receive Data register not empty interrupt
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* @arg UART_IT_IDLE: Idle line detection interrupt
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* @arg UART_IT_ORE: OverRun Error interrupt
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* @arg UART_IT_NE: Noise Error interrupt
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* @arg UART_IT_FE: Framing Error interrupt
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* @arg UART_IT_PE: Parity Error interrupt
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* @retval The new state of __IT__ (TRUE or FALSE).
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*/
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#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
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(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
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/** @brief Set a specific UART request flag.
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* @param __HANDLE__: specifies the UART Handle.
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* @param __REQ__: specifies the request flag to set
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* This parameter can be one of the following values:
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* @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
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* @arg UART_SENDBREAK_REQUEST: Send Break Request
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* @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
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* @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
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* @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
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* @retval None
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*/
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#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
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/** @brief Enables the UART one bit sample method
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* @param __HANDLE__: specifies the UART Handle.
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* @retval None
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*/
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#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
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/** @brief Disables the UART one bit sample method
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* @param __HANDLE__: specifies the UART Handle.
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* @retval None
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*/
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#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
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/** @brief Enable UART
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* @param __HANDLE__: specifies the UART Handle.
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* @retval None
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*/
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#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
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/** @brief Disable UART
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* @param __HANDLE__: specifies the UART Handle.
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* @retval None
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*/
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#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
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/** @brief Enable CTS flow control
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* This macro allows to enable CTS hardware flow control for a given UART instance,
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* without need to call HAL_UART_Init() function.
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* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
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* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
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* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
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* - UART instance should have already been initialised (through call of HAL_UART_Init() )
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* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
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* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
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* @param __HANDLE__: specifies the UART Handle.
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* The Handle Instance can be USART1, USART2 or LPUART.
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* @retval None
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*/
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#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
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do{ \
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SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
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(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
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} while(0)
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/** @brief Disable CTS flow control
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* This macro allows to disable CTS hardware flow control for a given UART instance,
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* without need to call HAL_UART_Init() function.
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* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
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* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
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|
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
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* - UART instance should have already been initialised (through call of HAL_UART_Init() )
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* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
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* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
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* @param __HANDLE__: specifies the UART Handle.
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|
|
* The Handle Instance can be USART1, USART2 or LPUART.
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
|
|
|
|
do{ \
|
|
|
|
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
|
|
|
|
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
/** @brief Enable RTS flow control
|
|
|
|
* This macro allows to enable RTS hardware flow control for a given UART instance,
|
|
|
|
* without need to call HAL_UART_Init() function.
|
|
|
|
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
|
|
|
|
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
|
|
|
|
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
|
|
|
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
|
|
|
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
|
|
|
|
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
|
|
|
|
* @param __HANDLE__: specifies the UART Handle.
|
|
|
|
* The Handle Instance can be USART1, USART2 or LPUART.
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
|
|
|
|
do{ \
|
|
|
|
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
|
|
|
|
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
/** @brief Disable RTS flow control
|
|
|
|
* This macro allows to disable RTS hardware flow control for a given UART instance,
|
|
|
|
* without need to call HAL_UART_Init() function.
|
|
|
|
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
|
|
|
|
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
|
|
|
|
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
|
|
|
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
|
|
|
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
|
|
|
|
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
|
|
|
|
* @param __HANDLE__: specifies the UART Handle.
|
|
|
|
* The Handle Instance can be USART1, USART2 or LPUART.
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
|
|
|
|
do{ \
|
|
|
|
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
|
|
|
|
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Private macros --------------------------------------------------------*/
|
|
|
|
/** @defgroup UART_Private_Macros UART Private Macros
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
/** @brief BRR division operation to set BRR register with LPUART
|
|
|
|
* @param _PCLK_: LPUART clock
|
|
|
|
* @param _BAUD_: Baud rate set by the user
|
|
|
|
* @retval Division result
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_DIV_LPUART(_PCLK_, _BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_)))
|
2015-07-27 20:20:56 -04:00
|
|
|
|
|
|
|
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode
|
|
|
|
* @param _PCLK_: UART clock
|
|
|
|
* @param _BAUD_: Baud rate set by the user
|
|
|
|
* @retval Division result
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_)))
|
2015-07-27 20:20:56 -04:00
|
|
|
|
|
|
|
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode
|
|
|
|
* @param _PCLK_: UART clock
|
|
|
|
* @param _BAUD_: Baud rate set by the user
|
|
|
|
* @retval Division result
|
|
|
|
*/
|
2016-12-05 01:04:56 -05:00
|
|
|
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_)))
|
2015-07-27 20:20:56 -04:00
|
|
|
|
|
|
|
/** @brief Check UART Baud rate
|
|
|
|
* @param BAUDRATE: Baudrate specified by the user
|
|
|
|
* The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)
|
|
|
|
* divided by the smallest oversampling used on the USART (i.e. 8)
|
|
|
|
* @retval Test result (TRUE or FALSE).
|
|
|
|
*/
|
|
|
|
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
|
|
|
|
|
|
|
|
/** @brief Check UART assertion time
|
|
|
|
* @param TIME: 5-bit value assertion time
|
|
|
|
* @retval Test result (TRUE or FALSE).
|
|
|
|
*/
|
|
|
|
#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)
|
|
|
|
|
|
|
|
/** @brief Check UART deassertion time
|
|
|
|
* @param TIME: 5-bit value deassertion time
|
|
|
|
* @retval Test result (TRUE or FALSE).
|
|
|
|
*/
|
|
|
|
#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
|
|
|
|
|
|
|
|
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
|
|
|
|
((STOPBITS) == UART_STOPBITS_2))
|
|
|
|
|
|
|
|
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
|
|
|
|
((PARITY) == UART_PARITY_EVEN) || \
|
|
|
|
((PARITY) == UART_PARITY_ODD))
|
|
|
|
|
|
|
|
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
|
|
|
(((CONTROL) == UART_HWCONTROL_NONE) || \
|
|
|
|
((CONTROL) == UART_HWCONTROL_RTS) || \
|
|
|
|
((CONTROL) == UART_HWCONTROL_CTS) || \
|
|
|
|
((CONTROL) == UART_HWCONTROL_RTS_CTS))
|
|
|
|
|
|
|
|
#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))
|
|
|
|
|
|
|
|
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
|
|
|
|
((STATE) == UART_STATE_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
|
|
|
|
((SAMPLING) == UART_OVERSAMPLING_8))
|
|
|
|
|
|
|
|
#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \
|
|
|
|
((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
|
|
|
|
((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
|
|
|
|
((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
|
|
|
|
((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
|
|
|
|
|
|
|
|
#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \
|
|
|
|
((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \
|
|
|
|
((LIN) == UART_LIN_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
|
|
|
|
((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
|
|
|
|
|
|
|
|
#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
|
|
|
|
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
|
|
|
|
|
|
|
|
#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \
|
|
|
|
((DMATX) == UART_DMA_TX_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \
|
|
|
|
((DMARX) == UART_DMA_RX_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \
|
|
|
|
((HDSEL) == UART_HALF_DUPLEX_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \
|
|
|
|
((PARAM) == UART_SENDBREAK_REQUEST) || \
|
|
|
|
((PARAM) == UART_MUTE_MODE_REQUEST) || \
|
|
|
|
((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \
|
|
|
|
((PARAM) == UART_TXDATA_FLUSH_REQUEST))
|
|
|
|
|
|
|
|
#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \
|
|
|
|
UART_ADVFEATURE_TXINVERT_INIT | \
|
|
|
|
UART_ADVFEATURE_RXINVERT_INIT | \
|
|
|
|
UART_ADVFEATURE_DATAINVERT_INIT | \
|
|
|
|
UART_ADVFEATURE_SWAP_INIT | \
|
|
|
|
UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
|
|
|
|
UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
|
|
|
|
UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
|
|
|
|
UART_ADVFEATURE_MSBFIRST_INIT))
|
|
|
|
|
|
|
|
#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \
|
|
|
|
((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \
|
|
|
|
((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \
|
|
|
|
((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \
|
|
|
|
((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
|
|
|
|
((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))
|
|
|
|
|
|
|
|
#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
|
|
|
|
((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
|
|
|
|
((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
|
|
|
|
|
|
|
|
#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
|
|
|
|
((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
|
|
|
|
((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))
|
|
|
|
|
|
|
|
#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \
|
|
|
|
((POLARITY) == UART_DE_POLARITY_LOW))
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
/* Include UART HAL Extension module */
|
|
|
|
#include "stm32f7xx_hal_uart_ex.h"
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
|
|
/** @addtogroup UART_Exported_Functions UART Exported Functions
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Initialization and de-initialization functions ****************************/
|
|
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
|
|
|
|
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
|
|
|
|
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
|
|
|
|
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
|
2016-12-05 01:04:56 -05:00
|
|
|
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
|
2015-07-27 20:20:56 -04:00
|
|
|
HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
|
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
|
|
|
|
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* IO operation functions *****************************************************/
|
|
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
|
|
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
|
|
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
|
|
|
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
|
|
|
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
|
|
|
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
|
|
|
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
|
|
|
|
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
|
|
|
|
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
|
2016-12-05 01:04:56 -05:00
|
|
|
|
2015-07-27 20:20:56 -04:00
|
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
|
|
|
|
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
|
|
|
|
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
|
|
|
|
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
|
|
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
|
|
|
|
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Peripheral Control functions ************************************************/
|
|
|
|
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
|
2016-12-05 01:04:56 -05:00
|
|
|
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
|
2015-07-27 20:20:56 -04:00
|
|
|
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
|
|
|
|
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
|
|
|
|
void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
|
|
|
|
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
|
|
|
|
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Peripheral State and Errors functions **************************************************/
|
|
|
|
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
|
|
|
|
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Private functions -----------------------------------------------------------*/
|
|
|
|
/** @addtogroup UART_Private_Functions UART Private Functions
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
|
|
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
|
|
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
|
2016-12-05 01:04:56 -05:00
|
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
|
2015-07-27 20:20:56 -04:00
|
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F7xx_HAL_UART_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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