205 lines
6.3 KiB
C
205 lines
6.3 KiB
C
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Jim Mussared
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#include "py/mphal.h"
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#include "extmod/machine_bitstream.h"
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#if MICROPY_PY_MACHINE_BITSTREAM
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#if __CORTEX_M == 0
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// No cycle counter on M0, do manual cycle counting instead.
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// STM32F091 @ 48MHz
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#define NS_CYCLES_PER_ITER_HIGH (6)
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#define NS_CYCLES_PER_ITER_LOW (6)
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#define NS_OVERHEAD_CYCLES_HIGH (12)
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#define NS_OVERHEAD_CYCLES_LOW (18)
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uint32_t mp_hal_delay_ns_calc(uint32_t ns, bool high) {
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uint32_t ncycles = SystemCoreClock / 1000000 * ns / 1000;
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uint32_t overhead = MIN(ncycles, high ? NS_OVERHEAD_CYCLES_HIGH : NS_OVERHEAD_CYCLES_LOW);
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return MAX(1, MP_ROUND_DIVIDE(ncycles - overhead, high ? NS_CYCLES_PER_ITER_HIGH : NS_CYCLES_PER_ITER_LOW));
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}
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void machine_bitstream_high_low(mp_hal_pin_obj_t pin, uint32_t *timing_ns, const uint8_t *buf, size_t len) {
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const uint32_t high_mask = pin->pin_mask;
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const uint32_t low_mask = pin->pin_mask << 16;
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volatile uint32_t *bsrr = &pin->gpio->BSRR;
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// Convert ns to loop iterations [high_time_0, low_time_0, high_time_1, low_time_1].
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for (size_t i = 0; i < 4; ++i) {
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timing_ns[i] = mp_hal_delay_ns_calc(timing_ns[i], i % 2 == 0);
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}
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mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION();
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// Measured timing for F091 at 48MHz (cycle=20.83ns)
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// timing_ns = (1,1,1,1)
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// high: 370
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// low: 500
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// low8: 660
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// timing_ns = (2,2,2,2)
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// high: 490
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// low: 620
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// low8: 805
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// --> high is 12 + n*6 cycles
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// low is 18 + n*6 cycles
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// NeoPixel timing (400, 850, 800, 450) (+/-150ns) gives timing_ns=(1, 4, 4, 1) which in cycles is
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// (12 + 6, 18 + 24, 12 + 24, 18 + 6) = (18, 42, 36, 24)
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// --> (375, 875, 750, 500) nanoseconds.
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// Measured output on logic analyser is (370, 870, 750, 490) (+/-10ns at 100MHz)
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// Note: final low of LSB is longer by 8 cycles (160ns) (due to start of outer loop and fetching next byte).
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// This is slightly outside spec, but doesn't seem to cause a problem.
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__asm volatile (
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// Force consistent register assignment.
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// r6 = len
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"ldr r6, %0\n"
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// r4 = buf
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"ldr r4, %1\n"
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// r5 = timing_ms
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"ldr r5, %2\n"
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// Must align for consistent timing.
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".align 4\n"
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// Don't increment/decrement before first iteration.
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"b .outer2\n"
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".outer:\n"
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// ++buf, --len
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" add r4, #1\n"
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" sub r6, #1\n"
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// len iterations
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".outer2:\n"
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" cmp r6, #0\n"
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" beq .done\n"
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// r0 = *buf
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" ldrb r0, [r4, #0]\n"
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// 8 bits in byte
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" mov r7, #8\n"
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" .inner:\n"
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// *bsrr = high_mask
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" ldr r1, %3\n"
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" ldr r2, %4\n"
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" str r2, [r1, #0]\n"
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// r3 = (r0 >> 4) & 8 (r0 is 8 if high bit is 1 else 0)
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" mov r8, r6\n"
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" lsr r3, r0, #4\n"
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" mov r6, #8\n"
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" and r3, r6\n"
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" mov r6, r8\n"
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// r2 = timing_ns[r2]
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" ldr r2, [r5, r3]\n"
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" .loop1:\n sub r2, #1\n bne .loop1\n"
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// *bsrr = low_mask
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" ldr r2, %5\n"
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" str r2, [r1, #0]\n"
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// r2 = timing_ns[r3 + 4]
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" add r3, #4\n"
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" ldr r2, [r5, r3]\n"
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" .loop2:\n sub r2, #1\n bne .loop2\n"
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// b >>= 1
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" lsl r0, r0, #1\n"
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" sub r7, #1\n"
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// end of inner loop
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" beq .outer\n"
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// continue inner loop
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" b .inner\n"
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".done:\n"
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:
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: "m" (len), "m" (buf), "m" (timing_ns), "m" (bsrr), "m" (high_mask), "m" (low_mask)
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: "r0", "r1", "r2", "r3", "r7", "r8"
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);
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MICROPY_END_ATOMIC_SECTION(atomic_state);
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}
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#else // > CORTEX_M0
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// Use cycle counter for timing.
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// Measured on PYBV11 at 168MHz & 128MHz and PYBD_SF6 at 128MHz & 144MHz.
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#define NS_CYCLES_OVERHEAD (6)
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void machine_bitstream_high_low(mp_hal_pin_obj_t pin, uint32_t *timing_ns, const uint8_t *buf, size_t len) {
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const uint32_t high_mask = pin->pin_mask;
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const uint32_t low_mask = pin->pin_mask << 16;
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volatile uint32_t *bsrr = &pin->gpio->BSRR;
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// Convert ns to cycles [high_time_0, low_time_0, high_time_1, low_time_1].
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for (size_t i = 0; i < 4; ++i) {
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timing_ns[i] = SystemCoreClock / 1000000 * timing_ns[i] / 1000;
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if (timing_ns[i] > NS_CYCLES_OVERHEAD) {
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timing_ns[i] -= NS_CYCLES_OVERHEAD;
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}
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if (i % 2 == 1) {
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timing_ns[i] += timing_ns[i - 1];
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}
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}
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mp_hal_ticks_cpu_enable();
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mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION();
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for (size_t i = 0; i < len; ++i) {
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uint8_t b = buf[i];
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for (size_t j = 0; j < 8; ++j) {
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DWT->CYCCNT = 0;
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*bsrr = high_mask;
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uint32_t *t = &timing_ns[b >> 6 & 2];
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while (DWT->CYCCNT < t[0]) {
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;
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}
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*bsrr = low_mask;
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b <<= 1;
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while (DWT->CYCCNT < t[1]) {
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;
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}
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}
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}
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MICROPY_END_ATOMIC_SECTION(atomic_state);
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}
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#endif // > CORTEX_M0
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#endif // MICROPY_PY_MACHINE_BITSTREAM
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