237 lines
9.9 KiB
C
237 lines
9.9 KiB
C
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/**
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******************************************************************************
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* @file stm32f4xx_hal_nand.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 18-February-2014
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* @brief Header file of NAND HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_HAL_NAND_H
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#define __STM32F4xx_HAL_NAND_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
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#include "stm32f4xx_ll_fsmc.h"
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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#include "stm32f4xx_ll_fmc.h"
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup NAND
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* @{
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*/
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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/* Exported typedef ----------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief HAL NAND State structures definition
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*/
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typedef enum
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{
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HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
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HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
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HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
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HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
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}HAL_NAND_StateTypeDef;
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/**
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* @brief NAND Memory electronic signature Structure definition
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*/
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typedef struct
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{
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/*<! NAND memory electronic signature maker and device IDs */
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uint8_t Maker_Id;
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uint8_t Device_Id;
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uint8_t Third_Id;
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uint8_t Fourth_Id;
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}NAND_IDTypeDef;
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/**
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* @brief NAND Memory address Structure definition
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*/
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typedef struct
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{
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uint16_t Page; /*!< NAND memory Page address */
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uint16_t Zone; /*!< NAND memory Zone address */
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uint16_t Block; /*!< NAND memory Block address */
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}NAND_AddressTypedef;
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/**
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* @brief NAND Memory info Structure definition
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*/
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typedef struct
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{
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uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
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uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
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uint32_t BlockSize; /*!< NAND memory block size number of pages */
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uint32_t BlockNbr; /*!< NAND memory number of blocks */
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uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
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}NAND_InfoTypeDef;
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/**
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* @brief NAND handle Structure definition
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*/
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typedef struct
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{
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FMC_NAND_TypeDef *Instance; /*!< Register base address */
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FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
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HAL_LockTypeDef Lock; /*!< NAND locking object */
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__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
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NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
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}NAND_HandleTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup NAND_Exported_Constants
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* @{
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*/
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#define NAND_DEVICE1 ((uint32_t)0x70000000)
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#define NAND_DEVICE2 ((uint32_t)0x80000000)
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#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
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#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
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#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
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#define NAND_CMD_AREA_A ((uint8_t)0x00)
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#define NAND_CMD_AREA_B ((uint8_t)0x01)
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#define NAND_CMD_AREA_C ((uint8_t)0x50)
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/* NAND memory status */
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#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
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#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
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#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
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#define NAND_BUSY ((uint32_t)0x00000000)
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#define NAND_ERROR ((uint32_t)0x00000001)
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#define NAND_READY ((uint32_t)0x00000040)
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/**
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* @brief NAND memory address computation.
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* @param __ADDRESS__: NAND memory address.
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* @param __HANDLE__ : NAND handle.
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* @retval NAND Raw address value
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*/
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#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.BlockSize)))* ((__HANDLE__)->Info.ZoneSize)))
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/**
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* @brief NAND memory address cycling.
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* @param __ADDRESS__: NAND memory address.
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* @retval NAND address cycling value.
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*/
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#define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__)& 0xFF) /* 1st addressing cycle */
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#define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF00) >> 8) /* 2nd addressing cycle */
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#define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF0000) >> 16) /* 3rd addressing cycle */
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#define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF000000) >> 24) /* 4th addressing cycle */
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/* Exported functions --------------------------------------------------------*/
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/* Initialization/de-initialization functions **********************************/
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HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
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HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
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void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
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void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
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void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
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void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
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/* IO operation functions *****************************************************/
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HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
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HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
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HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
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HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
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HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
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HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
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HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
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uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
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/* NAND Control functions ******************************************************/
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HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
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HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
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HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
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/* NAND State functions *********************************************************/
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HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
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uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F4xx_HAL_NAND_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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