118 lines
5.6 KiB
C
118 lines
5.6 KiB
C
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//*****************************************************************************
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// hw_ints.h - Macros that define the interrupt assignment on CC3200.
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//
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//*****************************************************************************
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#ifndef __HW_INTS_H__
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#define __HW_INTS_H__
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//*****************************************************************************
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//
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// The following are defines for the fault assignments.
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//
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//*****************************************************************************
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#define FAULT_NMI 2 // NMI fault
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#define FAULT_HARD 3 // Hard fault
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#define FAULT_MPU 4 // MPU fault
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#define FAULT_BUS 5 // Bus fault
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#define FAULT_USAGE 6 // Usage fault
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#define FAULT_SVCALL 11 // SVCall
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#define FAULT_DEBUG 12 // Debug monitor
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#define FAULT_PENDSV 14 // PendSV
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#define FAULT_SYSTICK 15 // System Tick
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//*****************************************************************************
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//
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// The following are defines for the interrupt assignments.
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//
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//*****************************************************************************
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#define INT_GPIOA0 16 // GPIO Port S0
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#define INT_GPIOA1 17 // GPIO Port S1
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#define INT_GPIOA2 18 // GPIO Port S2
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#define INT_GPIOA3 19 // GPIO Port S3
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#define INT_UARTA0 21 // UART0 Rx and Tx
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#define INT_UARTA1 22 // UART1 Rx and Tx
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#define INT_I2CA0 24 // I2C controller
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#define INT_ADCCH0 30 // ADC Sequence 0
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#define INT_ADCCH1 31 // ADC Sequence 1
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#define INT_ADCCH2 32 // ADC Sequence 2
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#define INT_ADCCH3 33 // ADC Sequence 3
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#define INT_WDT 34 // Watchdog Timer0
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#define INT_TIMERA0A 35 // Timer 0 subtimer A
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#define INT_TIMERA0B 36 // Timer 0 subtimer B
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#define INT_TIMERA1A 37 // Timer 1 subtimer A
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#define INT_TIMERA1B 38 // Timer 1 subtimer B
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#define INT_TIMERA2A 39 // Timer 2 subtimer A
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#define INT_TIMERA2B 40 // Timer 2 subtimer B
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#define INT_FLASH 45 // FLASH Control
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#define INT_TIMERA3A 51 // Timer 3 subtimer A
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#define INT_TIMERA3B 52 // Timer 3 subtimer B
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#define INT_UDMA 62 // uDMA controller
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#define INT_UDMAERR 63 // uDMA Error
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#define INT_SHA 164 // SHA
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#define INT_AES 167 // AES
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#define INT_DES 169 // DES
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#define INT_MMCHS 175 // SDIO
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#define INT_I2S 177 // McAPS
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#define INT_CAMERA 179 // Camera
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#define INT_NWPIC 187 // Interprocessor communication
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#define INT_PRCM 188 // Power, Reset and Clock Module
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#define INT_SSPI 191 // Shared SPI
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#define INT_GSPI 192 // Generic SPI
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#define INT_LSPI 193 // Link SPI
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//*****************************************************************************
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//
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// The following are defines for the total number of interrupts.
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//
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//*****************************************************************************
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#define NUM_INTERRUPTS 195 //The above number plus 2?
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//*****************************************************************************
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//
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// The following are defines for the total number of priority levels.
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//
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//*****************************************************************************
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#define NUM_PRIORITY 8
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#define NUM_PRIORITY_BITS 3
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#endif // __HW_INTS_H__
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