circuitpython/ports/litex/irq.h

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#ifndef __IRQ_H
#define __IRQ_H
#ifdef __cplusplus
extern "C" {
#endif
#define CSR_MSTATUS_MIE 0x8
#define CSR_IRQ_MASK 0xBC0
#define CSR_IRQ_PENDING 0xFC0
#define CSR_DCACHE_INFO 0xCC0
#define csrr(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " #reg : "=r" (__tmp)); \
__tmp; })
#define csrw(reg, val) ({ \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
asm volatile ("csrw " #reg ", %0" : : "i" (val)); \
else \
asm volatile ("csrw " #reg ", %0" : : "r" (val)); })
#define csrs(reg, bit) ({ \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrs x0, " #reg ", %0" : : "i" (bit)); \
else \
asm volatile ("csrrs x0, " #reg ", %0" : : "r" (bit)); })
#define csrc(reg, bit) ({ \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrc x0, " #reg ", %0" : : "i" (bit)); \
else \
asm volatile ("csrrc x0, " #reg ", %0" : : "r" (bit)); })
static inline unsigned int irq_getie(void) {
return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
}
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static inline void irq_setie(unsigned int ie) {
if (ie) {
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csrs(mstatus, CSR_MSTATUS_MIE);
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} else {
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csrc(mstatus, CSR_MSTATUS_MIE);
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}
}
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static inline unsigned int irq_getmask(void) {
unsigned int mask;
asm volatile ("csrr %0, %1" : "=r" (mask) : "i" (CSR_IRQ_MASK));
return mask;
}
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static inline void irq_setmask(unsigned int mask) {
asm volatile ("csrw %0, %1" : : "i" (CSR_IRQ_MASK), "r" (mask));
}
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static inline unsigned int irq_pending(void) {
unsigned int pending;
asm volatile ("csrr %0, %1" : "=r" (pending) : "i" (CSR_IRQ_PENDING));
return pending;
}
#ifdef __cplusplus
}
#endif
#endif /* __IRQ_H */