circuitpython/ports/stm/peripherals/stm32l4/stm32l4r5xx/clocks.h

/*
 * This file is part of the Micro Python project, http://micropython.org/
 *
 * The MIT License (MIT)
 *
 * Copyright (c) 2021 Blues Wireless Contributors
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "stm32l4xx_hal.h"

// Chip:                STM32L4R5
// Line Type:           Foundation Line
// Speed:               120MHz (MAX)

// Defaults:
#ifndef CPY_CLK_VSCALE
#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)      // up to 120MHz
#endif
#ifndef CPY_CLK_PLLM
#define CPY_CLK_PLLM (12)
#endif
#ifndef CPY_CLK_PLLN
#define CPY_CLK_PLLN (60)
#endif
#ifndef CPY_CLK_PLLP
#define CPY_CLK_PLLP (RCC_PLLP_DIV2)
#endif
#ifndef CPY_CLK_PLLQ
#define CPY_CLK_PLLQ (2)
#endif
#ifndef CPY_CLK_AHBDIV
#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1)
#endif
#ifndef CPY_CLK_APB1DIV
#define CPY_CLK_APB1DIV (RCC_HCLK_DIV1)
#endif
#ifndef CPY_CLK_APB2DIV
#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1)
#endif
#ifndef CPY_CLK_FLASH_LATENCY
#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_5)
#endif
#ifndef CPY_CLK_USB_USES_AUDIOPLL
#define CPY_CLK_USB_USES_AUDIOPLL (0)
#endif

#ifndef BOARD_HAS_HIGH_SPEED_CRYSTAL
#define BOARD_HAS_HIGH_SPEED_CRYSTAL (1)
#endif
feat: add Blues Swan R5 support complete pin mapping for Feather pins stubbed out files needed for complilation. still to be modified 0 out all CPY modules in mpconfigboard.mk until we get the build running add csv for pin generation for STM32L4R5 add F4R5 references in peripherals files refactored out board files BECAUSE I AM AN IDIOT; add L4 series system clocks file from CubeMX took a guess at the number of USB endpoint pairs to get the build done guess was close, but wrong. It is 8 clean up peripheral DEFs Fixes build error: ``` In file included from ../../py/mpstate.h:33, from ../../py/mpstate.c:27: ../../py/misc.h: In function 'vstr_str': ../../py/misc.h:196:1: sorry, unimplemented: Thumb-1 hard-float VFP ABI static inline char vstr_str(vstr_t vstr) { ^~~~~~ ``` Sleuthing steps: * verify that the feather_stm32f4_express board builds correctly * put a `#error` at the bottom of the `mpstate.c` file. * build for the feather and swan boards, with V=2 to capture the build command for that file. * use a differencing tool to inspect the differences between the two invocations * inspecting the differences, I saw a missing `-mcpu=cortex-m4` I tested by adding that to the Swan build command. The file built fine (stopping at the hard error, but no other warnings.) A grep through the sources revealed where this flag was being set for the stm ports. With this commit, the build gets further, but does not complete. The next exciting episode in this unfolding coding saga is just a commit away! working build with minimal set of modules for the Blues Swan r5 chore:change header copyright name to Blues Wireless Contributors USB operational. Fixed up clocks to be hardwired for LSE no HSE case. (Trying to combine HSE in there made the code much more complex, and I don't have a board to test it out on.) USART working adds support for `ENABLE_3V3` and `DISCHARGE_3V3` pins. I am surprised that pin definitions are quite low-level and don't include default direction and state, so the code currently has to initialize `ENABLE_3V3` pin as output. The LED takes over a second to discharge, so I wonder if the board startup code is not having the desired affect. short circuit implementation of backup memory for the STM32L4 all the ports remove company name from board name to be consistent with the Arduino board definition. add default pins for I2C, SPI and UART, so that `board.I2C` et al. works as expected. Confirmed I2C timing. fix board name fix incorrect pin definition. add test to allow manual check of each output pin analog IO code changes for WebUSB. Doesn't appear to work, will revisit later. ensure that `sys.platform` is available checkin missing file feat: make room for a larger filesystem so the sensor tutorial will fit on the device. fix:(stm32l4r5zi.csv): merged AF0-7 and AF8-15 into single lines and removed extraneous headers mixed in with the data. fix(parse_af_csv.py): pin index in the csv is 0 not 1, and AF index made 1 larger chore(Swan R5): update peripherals pins from `parse_af_csv.py` output optimize flash sector access 2021-07-29 18:06:31 -04:00			`/*`
			`* This file is part of the Micro Python project, http://micropython.org/`
			`*`
			`* The MIT License (MIT)`
			`*`
			`* Copyright (c) 2021 Blues Wireless Contributors`
			`*`
			`* Permission is hereby granted, free of charge, to any person obtaining a copy`
			`* of this software and associated documentation files (the "Software"), to deal`
			`* in the Software without restriction, including without limitation the rights`
			`* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell`
			`* copies of the Software, and to permit persons to whom the Software is`
			`* furnished to do so, subject to the following conditions:`
			`*`
			`* The above copyright notice and this permission notice shall be included in`
			`* all copies or substantial portions of the Software.`
			`*`
			`* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
			`* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
			`* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
			`* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
			`* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
			`* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN`
			`* THE SOFTWARE.`
			`*/`

			`#include "stm32l4xx_hal.h"`

			`// Chip: STM32L4R5`
			`// Line Type: Foundation Line`
			`// Speed: 120MHz (MAX)`

			`// Defaults:`
			`#ifndef CPY_CLK_VSCALE`
			`#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) // up to 120MHz`
			`#endif`
			`#ifndef CPY_CLK_PLLM`
			`#define CPY_CLK_PLLM (12)`
			`#endif`
			`#ifndef CPY_CLK_PLLN`
			`#define CPY_CLK_PLLN (60)`
			`#endif`
			`#ifndef CPY_CLK_PLLP`
			`#define CPY_CLK_PLLP (RCC_PLLP_DIV2)`
			`#endif`
			`#ifndef CPY_CLK_PLLQ`
			`#define CPY_CLK_PLLQ (2)`
			`#endif`
			`#ifndef CPY_CLK_AHBDIV`
			`#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1)`
			`#endif`
			`#ifndef CPY_CLK_APB1DIV`
			`#define CPY_CLK_APB1DIV (RCC_HCLK_DIV1)`
			`#endif`
			`#ifndef CPY_CLK_APB2DIV`
			`#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1)`
			`#endif`
			`#ifndef CPY_CLK_FLASH_LATENCY`
			`#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_5)`
			`#endif`
			`#ifndef CPY_CLK_USB_USES_AUDIOPLL`
			`#define CPY_CLK_USB_USES_AUDIOPLL (0)`
			`#endif`

			`#ifndef BOARD_HAS_HIGH_SPEED_CRYSTAL`
			`#define BOARD_HAS_HIGH_SPEED_CRYSTAL (1)`
			`#endif`