djsundog
/
circuitpython
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
circuitpython/ports/stm32/boards/stm32f401_af.csv

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

84 lines
4.7 KiB
Plaintext
Raw Normal View History

stmhal: Add stm32f401_af.csv, for AF definitions of F401 MCUs.
2015-04-18 11:33:53 -04:00
Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,
stmhal: Provide ADC capabilities for F401 and F411 MCUs. Simply needed to define which pins have which ADC channel on them.
2015-04-18 17:39:06 -04:00
,,SYS_AF,TIM1/TIM2,TIM3/TIM4/TIM5,TIM9/TIM10/TIM11,I2C1/I2C2/I2C3,SPI1/SPI2/I2S2/SPI3/I2S3/SPI4,SPI2/I2S2/SPI3/I2S3,SPI3/I2S3/USART1/USART2,USART6,I2C2/I2C3,OTG1_FS,,SDIO,,,,ADC
PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,,EVENTOUT,ADC1_IN0
PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,,,,,EVENTOUT,ADC1_IN1
PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,,,,,EVENTOUT,ADC1_IN2
PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,,,,,EVENTOUT,ADC1_IN3
PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT,ADC1_IN4
PortA,PA5,,TIM2_CH1/TIM2_ETR,,,,SPI1_SCK,,,,,,,,,,EVENTOUT,ADC1_IN5
PortA,PA6,,TIM1_BKIN,TIM3_CH1,,,SPI1_MISO,,,,,,,,,,EVENTOUT,ADC1_IN6
PortA,PA7,,TIM1_CH1N,TIM3_CH2,,,SPI1_MOSI,,,,,,,,,,EVENTOUT,ADC1_IN7
stmhal: Add stm32f401_af.csv, for AF definitions of F401 MCUs.
2015-04-18 11:33:53 -04:00
PortA,PA8,MCO_1,TIM1_CH1,,,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT,
PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,,,USART1_TX,,,OTG_FS_VBUS,,,,,EVENTOUT,
PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,,,EVENTOUT,
PortA,PA11,,TIM1_CH4,,,,,,USART1_CTS,USART6_TX,,OTG_FS_DM,,,,,EVENTOUT,
PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,USART6_RX,,OTG_FS_DP,,,,,EVENTOUT,
stm32/boards/*_af.csv: Make consistent use of JTMS, JTCK, SWDIO, SWCLK. 5-pin JTAG and 2-pin SWD are logically separate interfaces so encode them in the AF tables as separate entries (separated by /, not -).
2017-11-30 22:51:36 -05:00
PortA,PA13,JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT,
PortA,PA14,JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT,
stmhal: Add stm32f401_af.csv, for AF definitions of F401 MCUs.
2015-04-18 11:33:53 -04:00
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,,,,,EVENTOUT,
stmhal: Provide ADC capabilities for F401 and F411 MCUs. Simply needed to define which pins have which ADC channel on them.
2015-04-18 17:39:06 -04:00
PortB,PB0,,TIM1_CH2N,TIM3_CH3,,,,,,,,,,,,,EVENTOUT,ADC1_IN8
PortB,PB1,,TIM1_CH3N,TIM3_CH4,,,,,,,,,,,,,EVENTOUT,ADC1_IN9
stmhal: Add stm32f401_af.csv, for AF definitions of F401 MCUs.
2015-04-18 11:33:53 -04:00
PortB,PB2,,,,,,,,,,,,,,,,EVENTOUT,
stm32/boards: Split combined alt-func labels and fix some other errors. Pins with multiple alt-funcs for the same peripheral (eg USART_CTS_NSS) need to be split into individual alt-funcs for make-pins.py to work correctly. This patch changes the following: - Split `..._CTS_NSS` into `..._CTS/..._NSS` - Split `..._RTS_DE` into `..._RTS/..._DE` - Split `JTDO_SWO` into `JTDO/TRACESWO` for consistency - Fixed `TRACECK` to `TRACECLK` for consistency
2018-05-29 05:14:13 -04:00
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,I2C2_SDA,,,,,,EVENTOUT,
stmhal: Add stm32f401_af.csv, for AF definitions of F401 MCUs.
2015-04-18 11:33:53 -04:00
PortB,PB4,JTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,I2S3ext_SD,,I2C3_SDA,,,,,,EVENTOUT,
PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,,,,,EVENTOUT,
PortB,PB6,,,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT,
PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT,
PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,,SDIO_D4,,,EVENTOUT,
PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,,,,SDIO_D5,,,EVENTOUT,
PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,,,,,,,,,EVENTOUT,
PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,,,,,,,,,EVENTOUT,
PortB,PB13,,TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,,,,,,,,,EVENTOUT,
PortB,PB14,,TIM1_CH2N,,,,SPI2_MISO,I2S2ext_SD,,,,,,,,,EVENTOUT,
PortB,PB15,RTC_REFIN,TIM1_CH3N,,,,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT,
stmhal: Provide ADC capabilities for F401 and F411 MCUs. Simply needed to define which pins have which ADC channel on them.
2015-04-18 17:39:06 -04:00
PortC,PC0,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN10
PortC,PC1,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN11
PortC,PC2,,,,,,SPI2_MISO,I2S2ext_SD,,,,,,,,,EVENTOUT,ADC1_IN12
PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT,ADC1_IN13
PortC,PC4,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN14
PortC,PC5,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN15
stmhal: Add stm32f401_af.csv, for AF definitions of F401 MCUs.
2015-04-18 11:33:53 -04:00
PortC,PC6,,,TIM3_CH1,,,I2S2_MCK,,,USART6_TX,,,,SDIO_D6,,,EVENTOUT,
PortC,PC7,,,TIM3_CH2,,,,I2S3_MCK,,USART6_RX,,,,SDIO_D7,,,EVENTOUT,
PortC,PC8,,,TIM3_CH3,,,,,,USART6_CK,,,,SDIO_D0,,,EVENTOUT,
PortC,PC9,MCO_2,,TIM3_CH4,,I2C3_SDA,I2S_CKIN,,,,,,,SDIO_D1,,,EVENTOUT,
PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,,,,,,SDIO_D2,,,EVENTOUT,
PortC,PC11,,,,,,I2S3ext_SD,SPI3_MISO,,,,,,SDIO_D3,,,EVENTOUT,
PortC,PC12,,,,,,,SPI3_MOSI/I2S3_SD,,,,,,SDIO_CK,,,EVENTOUT,
PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD0,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD1,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD2,,,TIM3_ETR,,,,,,,,,,SDIO_CMD,,,EVENTOUT,
PortD,PD3,,,,,,SPI2_SCK/I2S2_CK,,USART2_CTS,,,,,,,,EVENTOUT,
PortD,PD4,,,,,,,,USART2_RTS,,,,,,,,EVENTOUT,
PortD,PD5,,,,,,,,USART2_TX,,,,,,,,EVENTOUT,
PortD,PD6,,,,,,SPI3_MOSI/I2S3_SD,,USART2_RX,,,,,,,,EVENTOUT,
PortD,PD7,,,,,,,,USART2_CK,,,,,,,,EVENTOUT,
PortD,PD8,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD9,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD10,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD11,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD12,,,TIM4_CH1,,,,,,,,,,,,,EVENTOUT,
PortD,PD13,,,TIM4_CH2,,,,,,,,,,,,,EVENTOUT,
PortD,PD14,,,TIM4_CH3,,,,,,,,,,,,,EVENTOUT,
PortD,PD15,,,TIM4_CH4,,,,,,,,,,,,,EVENTOUT,
PortE,PE0,,,TIM4_ETR,,,,,,,,,,,,,EVENTOUT,
PortE,PE1,,TIM1_CH2N,,,,,,,,,,,,,,EVENTOUT,
PortE,PE2,TRACECLK,,,,,SPI4_SCK,,,,,,,,,,EVENTOUT,
PortE,PE3,TRACED0,,,,,,,,,,,,,,,EVENTOUT,
PortE,PE4,TRACED1,,,,,SPI4_NSS,,,,,,,,,,EVENTOUT,
PortE,PE5,TRACED2,,,TIM9_CH1,,SPI4_MISO,,,,,,,,,,EVENTOUT,
PortE,PE6,TRACED3,,,TIM9_CH2,,SPI4_MOSI,,,,,,,,,,EVENTOUT,
PortE,PE7,,TIM1_ETR,,,,,,,,,,,,,,EVENTOUT,
PortE,PE8,,TIM1_CH1N,,,,,,,,,,,,,,EVENTOUT,
PortE,PE9,,TIM1_CH1,,,,,,,,,,,,,,EVENTOUT,
PortE,PE10,,TIM1_CH2N,,,,,,,,,,,,,,EVENTOUT,
PortE,PE11,,TIM1_CH2,,,,SPI4_NSS,,,,,,,,,,EVENTOUT,
PortE,PE12,,TIM1_CH3N,,,,SPI4_SCK,,,,,,,,,,EVENTOUT,
PortE,PE13,,TIM1_CH3,,,,SPI4_MISO,,,,,,,,,,EVENTOUT,
PortE,PE14,,TIM1_CH4,,,,SPI4_MOSI,,,,,,,,,,EVENTOUT,
PortE,PE15,,TIM1_BKIN,,,,,,,,,,,,,,EVENTOUT,
PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,
PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT,